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authorTomi Valkeinen <tomi.valkeinen@ti.com>2013-03-05 10:23:59 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2013-04-03 08:19:18 -0400
commitb7ec96c78b0d5c89f5a1082e62e0d0021b2920ed (patch)
tree4aaec4504f381e75bf1c8422e857035a71be8fea
parentf1e0001f973cfbec62d702cbd3d56f6b703cc90e (diff)
OMAPDSS: remove unused old clock calculation code
Now that the old clock calculation code is no longer used, we can remove it from the driver. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat
-rw-r--r--drivers/video/omap2/dss/dispc.c48
-rw-r--r--drivers/video/omap2/dss/dsi.c317
-rw-r--r--drivers/video/omap2/dss/dss.c115
-rw-r--r--drivers/video/omap2/dss/dss.h15
4 files changed, 0 insertions, 495 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index cd54e8fe2d58..8cfa27b4fdd8 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -3311,54 +3311,6 @@ static void dispc_dump_regs(struct seq_file *s)
3311#undef DUMPREG 3311#undef DUMPREG
3312} 3312}
3313 3313
3314/* with fck as input clock rate, find dispc dividers that produce req_pck */
3315void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
3316 struct dispc_clock_info *cinfo)
3317{
3318 u16 pcd_min, pcd_max;
3319 unsigned long best_pck;
3320 u16 best_ld, cur_ld;
3321 u16 best_pd, cur_pd;
3322
3323 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3324 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3325
3326 best_pck = 0;
3327 best_ld = 0;
3328 best_pd = 0;
3329
3330 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3331 unsigned long lck = fck / cur_ld;
3332
3333 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
3334 unsigned long pck = lck / cur_pd;
3335 long old_delta = abs(best_pck - req_pck);
3336 long new_delta = abs(pck - req_pck);
3337
3338 if (best_pck == 0 || new_delta < old_delta) {
3339 best_pck = pck;
3340 best_ld = cur_ld;
3341 best_pd = cur_pd;
3342
3343 if (pck == req_pck)
3344 goto found;
3345 }
3346
3347 if (pck < req_pck)
3348 break;
3349 }
3350
3351 if (lck / pcd_min < req_pck)
3352 break;
3353 }
3354
3355found:
3356 cinfo->lck_div = best_ld;
3357 cinfo->pck_div = best_pd;
3358 cinfo->lck = fck / cinfo->lck_div;
3359 cinfo->pck = cinfo->lck / cinfo->pck_div;
3360}
3361
3362/* calculate clock rates using dividers in cinfo */ 3314/* calculate clock rates using dividers in cinfo */
3363int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 3315int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3364 struct dispc_clock_info *cinfo) 3316 struct dispc_clock_info *cinfo)
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index de88e69ef0a2..8db29bff0423 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1430,190 +1430,6 @@ static int dsi_calc_clock_rates(struct platform_device *dsidev,
1430 return 0; 1430 return 0;
1431} 1431}
1432 1432
1433int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
1434 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1435 struct dispc_clock_info *dispc_cinfo)
1436{
1437 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1438 struct dsi_clock_info cur, best;
1439 struct dispc_clock_info best_dispc;
1440 int min_fck_per_pck;
1441 int match = 0;
1442 unsigned long dss_sys_clk, max_dss_fck;
1443
1444 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1445
1446 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1447
1448 if (req_pck == dsi->cache_req_pck &&
1449 dsi->cache_cinfo.clkin == dss_sys_clk) {
1450 DSSDBG("DSI clock info found from cache\n");
1451 *dsi_cinfo = dsi->cache_cinfo;
1452 dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
1453 dispc_cinfo);
1454 return 0;
1455 }
1456
1457 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1458
1459 if (min_fck_per_pck &&
1460 req_pck * min_fck_per_pck > max_dss_fck) {
1461 DSSERR("Requested pixel clock not possible with the current "
1462 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1463 "the constraint off.\n");
1464 min_fck_per_pck = 0;
1465 }
1466
1467 DSSDBG("dsi_pll_calc\n");
1468
1469retry:
1470 memset(&best, 0, sizeof(best));
1471 memset(&best_dispc, 0, sizeof(best_dispc));
1472
1473 memset(&cur, 0, sizeof(cur));
1474 cur.clkin = dss_sys_clk;
1475
1476 /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1477 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1478 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1479 cur.fint = cur.clkin / cur.regn;
1480
1481 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1482 continue;
1483
1484 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1485 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1486 unsigned long a, b;
1487
1488 a = 2 * cur.regm * (cur.clkin/1000);
1489 b = cur.regn;
1490 cur.clkin4ddr = a / b * 1000;
1491
1492 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1493 break;
1494
1495 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1496 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1497 for (cur.regm_dispc = 1; cur.regm_dispc <
1498 dsi->regm_dispc_max; ++cur.regm_dispc) {
1499 struct dispc_clock_info cur_dispc;
1500 cur.dsi_pll_hsdiv_dispc_clk =
1501 cur.clkin4ddr / cur.regm_dispc;
1502
1503 if (cur.regm_dispc > 1 &&
1504 cur.regm_dispc % 2 != 0 &&
1505 req_pck >= 1000000)
1506 continue;
1507
1508 /* this will narrow down the search a bit,
1509 * but still give pixclocks below what was
1510 * requested */
1511 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1512 break;
1513
1514 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1515 continue;
1516
1517 if (min_fck_per_pck &&
1518 cur.dsi_pll_hsdiv_dispc_clk <
1519 req_pck * min_fck_per_pck)
1520 continue;
1521
1522 match = 1;
1523
1524 dispc_find_clk_divs(req_pck,
1525 cur.dsi_pll_hsdiv_dispc_clk,
1526 &cur_dispc);
1527
1528 if (abs(cur_dispc.pck - req_pck) <
1529 abs(best_dispc.pck - req_pck)) {
1530 best = cur;
1531 best_dispc = cur_dispc;
1532
1533 if (cur_dispc.pck == req_pck)
1534 goto found;
1535 }
1536 }
1537 }
1538 }
1539found:
1540 if (!match) {
1541 if (min_fck_per_pck) {
1542 DSSERR("Could not find suitable clock settings.\n"
1543 "Turning FCK/PCK constraint off and"
1544 "trying again.\n");
1545 min_fck_per_pck = 0;
1546 goto retry;
1547 }
1548
1549 DSSERR("Could not find suitable clock settings.\n");
1550
1551 return -EINVAL;
1552 }
1553
1554 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1555 best.regm_dsi = 0;
1556 best.dsi_pll_hsdiv_dsi_clk = 0;
1557
1558 if (dsi_cinfo)
1559 *dsi_cinfo = best;
1560 if (dispc_cinfo)
1561 *dispc_cinfo = best_dispc;
1562
1563 dsi->cache_req_pck = req_pck;
1564 dsi->cache_clk_freq = 0;
1565 dsi->cache_cinfo = best;
1566
1567 return 0;
1568}
1569
1570static int dsi_pll_calc_ddrfreq(struct platform_device *dsidev,
1571 unsigned long req_clkin4ddr, struct dsi_clock_info *cinfo)
1572{
1573 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1574 struct dsi_clock_info cur, best;
1575
1576 DSSDBG("dsi_pll_calc_ddrfreq\n");
1577
1578 memset(&best, 0, sizeof(best));
1579 memset(&cur, 0, sizeof(cur));
1580
1581 cur.clkin = clk_get_rate(dsi->sys_clk);
1582
1583 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1584 cur.fint = cur.clkin / cur.regn;
1585
1586 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1587 continue;
1588
1589 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1590 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1591 unsigned long a, b;
1592
1593 a = 2 * cur.regm * (cur.clkin/1000);
1594 b = cur.regn;
1595 cur.clkin4ddr = a / b * 1000;
1596
1597 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1598 break;
1599
1600 if (abs(cur.clkin4ddr - req_clkin4ddr) <
1601 abs(best.clkin4ddr - req_clkin4ddr)) {
1602 best = cur;
1603 DSSDBG("best %ld\n", best.clkin4ddr);
1604 }
1605
1606 if (cur.clkin4ddr == req_clkin4ddr)
1607 goto found;
1608 }
1609 }
1610found:
1611 if (cinfo)
1612 *cinfo = best;
1613
1614 return 0;
1615}
1616
1617static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo) 1433static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
1618{ 1434{
1619 unsigned long max_dsi_fck; 1435 unsigned long max_dsi_fck;
@@ -1624,90 +1440,6 @@ static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
1624 cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi; 1440 cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1625} 1441}
1626 1442
1627static int dsi_pll_calc_dispc_fck(struct platform_device *dsidev,
1628 unsigned long req_pck, struct dsi_clock_info *cinfo,
1629 struct dispc_clock_info *dispc_cinfo)
1630{
1631 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1632 unsigned regm_dispc, best_regm_dispc;
1633 unsigned long dispc_clk, best_dispc_clk;
1634 int min_fck_per_pck;
1635 unsigned long max_dss_fck;
1636 struct dispc_clock_info best_dispc;
1637 bool match;
1638
1639 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1640
1641 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1642
1643 if (min_fck_per_pck &&
1644 req_pck * min_fck_per_pck > max_dss_fck) {
1645 DSSERR("Requested pixel clock not possible with the current "
1646 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1647 "the constraint off.\n");
1648 min_fck_per_pck = 0;
1649 }
1650
1651retry:
1652 best_regm_dispc = 0;
1653 best_dispc_clk = 0;
1654 memset(&best_dispc, 0, sizeof(best_dispc));
1655 match = false;
1656
1657 for (regm_dispc = 1; regm_dispc < dsi->regm_dispc_max; ++regm_dispc) {
1658 struct dispc_clock_info cur_dispc;
1659
1660 dispc_clk = cinfo->clkin4ddr / regm_dispc;
1661
1662 /* this will narrow down the search a bit,
1663 * but still give pixclocks below what was
1664 * requested */
1665 if (dispc_clk < req_pck)
1666 break;
1667
1668 if (dispc_clk > max_dss_fck)
1669 continue;
1670
1671 if (min_fck_per_pck && dispc_clk < req_pck * min_fck_per_pck)
1672 continue;
1673
1674 match = true;
1675
1676 dispc_find_clk_divs(req_pck, dispc_clk, &cur_dispc);
1677
1678 if (abs(cur_dispc.pck - req_pck) <
1679 abs(best_dispc.pck - req_pck)) {
1680 best_regm_dispc = regm_dispc;
1681 best_dispc_clk = dispc_clk;
1682 best_dispc = cur_dispc;
1683
1684 if (cur_dispc.pck == req_pck)
1685 goto found;
1686 }
1687 }
1688
1689 if (!match) {
1690 if (min_fck_per_pck) {
1691 DSSERR("Could not find suitable clock settings.\n"
1692 "Turning FCK/PCK constraint off and"
1693 "trying again.\n");
1694 min_fck_per_pck = 0;
1695 goto retry;
1696 }
1697
1698 DSSERR("Could not find suitable clock settings.\n");
1699
1700 return -EINVAL;
1701 }
1702found:
1703 cinfo->regm_dispc = best_regm_dispc;
1704 cinfo->dsi_pll_hsdiv_dispc_clk = best_dispc_clk;
1705
1706 *dispc_cinfo = best_dispc;
1707
1708 return 0;
1709}
1710
1711int dsi_pll_set_clock_div(struct platform_device *dsidev, 1443int dsi_pll_set_clock_div(struct platform_device *dsidev,
1712 struct dsi_clock_info *cinfo) 1444 struct dsi_clock_info *cinfo)
1713{ 1445{
@@ -4384,55 +4116,6 @@ int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
4384} 4116}
4385EXPORT_SYMBOL(omapdss_dsi_configure_pins); 4117EXPORT_SYMBOL(omapdss_dsi_configure_pins);
4386 4118
4387static int dsi_set_clocks(struct omap_dss_device *dssdev,
4388 unsigned long ddr_clk, unsigned long lp_clk)
4389{
4390 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4391 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4392 struct dsi_clock_info cinfo;
4393 struct dispc_clock_info dispc_cinfo;
4394 unsigned lp_clk_div;
4395 unsigned long dsi_fclk;
4396 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
4397 unsigned long pck;
4398 int r;
4399
4400 DSSDBG("Setting DSI clocks: ddr_clk %lu, lp_clk %lu", ddr_clk, lp_clk);
4401
4402 /* Calculate PLL output clock */
4403 r = dsi_pll_calc_ddrfreq(dsidev, ddr_clk * 4, &cinfo);
4404 if (r)
4405 goto err;
4406
4407 /* Calculate PLL's DSI clock */
4408 dsi_pll_calc_dsi_fck(&cinfo);
4409
4410 /* Calculate PLL's DISPC clock and pck & lck divs */
4411 pck = cinfo.clkin4ddr / 16 * (dsi->num_lanes_used - 1) * 8 / bpp;
4412 DSSDBG("finding dispc dividers for pck %lu\n", pck);
4413 r = dsi_pll_calc_dispc_fck(dsidev, pck, &cinfo, &dispc_cinfo);
4414 if (r)
4415 goto err;
4416
4417 /* Calculate LP clock */
4418 dsi_fclk = cinfo.dsi_pll_hsdiv_dsi_clk;
4419 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk * 2);
4420
4421 dsi->user_dsi_cinfo.regn = cinfo.regn;
4422 dsi->user_dsi_cinfo.regm = cinfo.regm;
4423 dsi->user_dsi_cinfo.regm_dispc = cinfo.regm_dispc;
4424 dsi->user_dsi_cinfo.regm_dsi = cinfo.regm_dsi;
4425
4426 dsi->user_dsi_cinfo.lp_clk_div = lp_clk_div;
4427
4428 dsi->user_dispc_cinfo.lck_div = dispc_cinfo.lck_div;
4429 dsi->user_dispc_cinfo.pck_div = dispc_cinfo.pck_div;
4430
4431 return 0;
4432err:
4433 return r;
4434}
4435
4436int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) 4119int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4437{ 4120{
4438 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4121 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index eba4127b61a6..fdd32e8d9212 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -581,121 +581,6 @@ static int dss_setup_default_clock(void)
581 return 0; 581 return 0;
582} 582}
583 583
584int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
585 struct dispc_clock_info *dispc_cinfo)
586{
587 unsigned long prate;
588 struct dss_clock_info best_dss;
589 struct dispc_clock_info best_dispc;
590
591 unsigned long fck, max_dss_fck;
592
593 u16 fck_div;
594
595 int match = 0;
596 int min_fck_per_pck;
597
598 prate = dss_get_dpll4_rate();
599
600 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
601
602 fck = clk_get_rate(dss.dss_clk);
603 if (req_pck == dss.cache_req_pck && prate == dss.cache_prate &&
604 dss.cache_dss_cinfo.fck == fck) {
605 DSSDBG("dispc clock info found from cache.\n");
606 *dss_cinfo = dss.cache_dss_cinfo;
607 *dispc_cinfo = dss.cache_dispc_cinfo;
608 return 0;
609 }
610
611 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
612
613 if (min_fck_per_pck &&
614 req_pck * min_fck_per_pck > max_dss_fck) {
615 DSSERR("Requested pixel clock not possible with the current "
616 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
617 "the constraint off.\n");
618 min_fck_per_pck = 0;
619 }
620
621retry:
622 memset(&best_dss, 0, sizeof(best_dss));
623 memset(&best_dispc, 0, sizeof(best_dispc));
624
625 if (dss.dpll4_m4_ck == NULL) {
626 struct dispc_clock_info cur_dispc;
627 /* XXX can we change the clock on omap2? */
628 fck = clk_get_rate(dss.dss_clk);
629 fck_div = 1;
630
631 dispc_find_clk_divs(req_pck, fck, &cur_dispc);
632 match = 1;
633
634 best_dss.fck = fck;
635 best_dss.fck_div = fck_div;
636
637 best_dispc = cur_dispc;
638
639 goto found;
640 } else {
641 for (fck_div = dss.feat->fck_div_max; fck_div > 0; --fck_div) {
642 struct dispc_clock_info cur_dispc;
643
644 fck = prate / fck_div * dss.feat->dss_fck_multiplier;
645
646 if (fck > max_dss_fck)
647 continue;
648
649 if (min_fck_per_pck &&
650 fck < req_pck * min_fck_per_pck)
651 continue;
652
653 match = 1;
654
655 dispc_find_clk_divs(req_pck, fck, &cur_dispc);
656
657 if (abs(cur_dispc.pck - req_pck) <
658 abs(best_dispc.pck - req_pck)) {
659
660 best_dss.fck = fck;
661 best_dss.fck_div = fck_div;
662
663 best_dispc = cur_dispc;
664
665 if (cur_dispc.pck == req_pck)
666 goto found;
667 }
668 }
669 }
670
671found:
672 if (!match) {
673 if (min_fck_per_pck) {
674 DSSERR("Could not find suitable clock settings.\n"
675 "Turning FCK/PCK constraint off and"
676 "trying again.\n");
677 min_fck_per_pck = 0;
678 goto retry;
679 }
680
681 DSSERR("Could not find suitable clock settings.\n");
682
683 return -EINVAL;
684 }
685
686 if (dss_cinfo)
687 *dss_cinfo = best_dss;
688 if (dispc_cinfo)
689 *dispc_cinfo = best_dispc;
690
691 dss.cache_req_pck = req_pck;
692 dss.cache_prate = prate;
693 dss.cache_dss_cinfo = best_dss;
694 dss.cache_dispc_cinfo = best_dispc;
695
696 return 0;
697}
698
699void dss_set_venc_output(enum omap_dss_venc_type type) 584void dss_set_venc_output(enum omap_dss_venc_type type)
700{ 585{
701 int l = 0; 586 int l = 0;
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index dde6cc109480..faaf35857b0e 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -268,8 +268,6 @@ void dss_set_dac_pwrdn_bgz(bool enable);
268unsigned long dss_get_dpll4_rate(void); 268unsigned long dss_get_dpll4_rate(void);
269int dss_calc_clock_rates(struct dss_clock_info *cinfo); 269int dss_calc_clock_rates(struct dss_clock_info *cinfo);
270int dss_set_clock_div(struct dss_clock_info *cinfo); 270int dss_set_clock_div(struct dss_clock_info *cinfo);
271int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
272 struct dispc_clock_info *dispc_cinfo);
273 271
274typedef bool (*dss_div_calc_func)(int fckd, unsigned long fck, void *data); 272typedef bool (*dss_div_calc_func)(int fckd, unsigned long fck, void *data);
275bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data); 273bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data);
@@ -310,9 +308,6 @@ bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
310unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev); 308unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
311int dsi_pll_set_clock_div(struct platform_device *dsidev, 309int dsi_pll_set_clock_div(struct platform_device *dsidev,
312 struct dsi_clock_info *cinfo); 310 struct dsi_clock_info *cinfo);
313int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
314 unsigned long req_pck, struct dsi_clock_info *cinfo,
315 struct dispc_clock_info *dispc_cinfo);
316int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, 311int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
317 bool enable_hsdiv); 312 bool enable_hsdiv);
318void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes); 313void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
@@ -343,14 +338,6 @@ static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
343 WARN("%s: DSI not compiled in\n", __func__); 338 WARN("%s: DSI not compiled in\n", __func__);
344 return -ENODEV; 339 return -ENODEV;
345} 340}
346static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
347 unsigned long req_pck,
348 struct dsi_clock_info *dsi_cinfo,
349 struct dispc_clock_info *dispc_cinfo)
350{
351 WARN("%s: DSI not compiled in\n", __func__);
352 return -ENODEV;
353}
354static inline int dsi_pll_init(struct platform_device *dsidev, 341static inline int dsi_pll_init(struct platform_device *dsidev,
355 bool enable_hsclk, bool enable_hsdiv) 342 bool enable_hsclk, bool enable_hsdiv)
356{ 343{
@@ -400,8 +387,6 @@ bool dispc_div_calc(unsigned long dispc,
400bool dispc_mgr_timings_ok(enum omap_channel channel, 387bool dispc_mgr_timings_ok(enum omap_channel channel,
401 const struct omap_video_timings *timings); 388 const struct omap_video_timings *timings);
402unsigned long dispc_fclk_rate(void); 389unsigned long dispc_fclk_rate(void);
403void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
404 struct dispc_clock_info *cinfo);
405int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 390int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
406 struct dispc_clock_info *cinfo); 391 struct dispc_clock_info *cinfo);
407 392
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 14:30:01 -0500