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authorLinus Torvalds <torvalds@linux-foundation.org>2012-01-08 16:35:24 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-01-08 16:35:24 -0500
commitb7d845f8825b058b80e76320f573505afbf4a1fc (patch)
treedc66dec44b489723427c9c4a9a92ef6e9f17c55b
parent2943c833222ef87c111ee0c6b7b8519ad2983e99 (diff)
parent0a92815db789bd5a922d882826cf710f9b0b9d85 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap: (36 commits) mfd: Clearing events requires event registers to be writable for da9052-core mfd: Fix annotations in da9052-core gpiolib: Mark da9052 driver broken mfd: Declare da9052_regmap_config for the bus drivers MFD: DA9052/53 MFD core module add SPI support v2 MFD: DA9052/53 MFD core module regmap: Add irq_base accessor to regmap_irq regmap: Allow drivers to reinitialise the register cache at runtime regmap: Add trace event for successful cache reads regmap: Allow regmap_update_bits() users to detect changes regmap: Report if we actually handled an interrupt in regmap-irq regmap: Fix rbtreee build when not using debugfs regmap: Provide debugfs dump of the rbtree cache data regmap: Do debugfs init before cache init regmap: Suppress noop writes in regmap_update_bits() regmap: Remove indexed cache type regmap: Drop check whether a register is readable in regcache_read regmap: Properly round cache_word_size regmap: Add support for 10/14 register formating regmap: Try cached read before checking if a hardware read is possible ...
Diffstat
-rw-r--r--drivers/base/regmap/Kconfig3
-rw-r--r--drivers/base/regmap/Makefile4
-rw-r--r--drivers/base/regmap/internal.h6
-rw-r--r--drivers/base/regmap/regcache-indexed.c64
-rw-r--r--drivers/base/regmap/regcache-lzo.c21
-rw-r--r--drivers/base/regmap/regcache-rbtree.c61
-rw-r--r--drivers/base/regmap/regcache.c87
-rw-r--r--drivers/base/regmap/regmap-irq.c302
-rw-r--r--drivers/base/regmap/regmap.c179
-rw-r--r--drivers/gpio/Kconfig2
-rw-r--r--drivers/mfd/Kconfig28
-rw-r--r--drivers/mfd/Makefile5
-rw-r--r--drivers/mfd/da9052-core.c694
-rw-r--r--drivers/mfd/da9052-i2c.c140
-rw-r--r--drivers/mfd/da9052-spi.c115
-rw-r--r--include/linux/mfd/da9052/da9052.h131
-rw-r--r--include/linux/mfd/da9052/pdata.h40
-rw-r--r--include/linux/mfd/da9052/reg.h749
-rw-r--r--include/linux/regmap.h59
-rw-r--r--include/trace/events/regmap.h9
20 files changed, 2542 insertions, 157 deletions
diff --git a/drivers/base/regmap/Kconfig b/drivers/base/regmap/Kconfig
index 2fc6a66f39a4..0f6c7fb418e8 100644
--- a/drivers/base/regmap/Kconfig
+++ b/drivers/base/regmap/Kconfig
@@ -13,3 +13,6 @@ config REGMAP_I2C
13 13
14config REGMAP_SPI 14config REGMAP_SPI
15 tristate 15 tristate
16
17config REGMAP_IRQ
18 bool
diff --git a/drivers/base/regmap/Makefile b/drivers/base/regmap/Makefile
index 0573c8a9dacb..defd57963c84 100644
--- a/drivers/base/regmap/Makefile
+++ b/drivers/base/regmap/Makefile
@@ -1,4 +1,6 @@
1obj-$(CONFIG_REGMAP) += regmap.o regcache.o regcache-indexed.o regcache-rbtree.o regcache-lzo.o 1obj-$(CONFIG_REGMAP) += regmap.o regcache.o
2obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-lzo.o
2obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o 3obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o
3obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o 4obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
4obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o 5obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o
6obj-$(CONFIG_REGMAP_IRQ) += regmap-irq.o
diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h
index 348ff02eb93e..1a02b7537c8b 100644
--- a/drivers/base/regmap/internal.h
+++ b/drivers/base/regmap/internal.h
@@ -74,6 +74,7 @@ struct regmap {
74 struct reg_default *reg_defaults; 74 struct reg_default *reg_defaults;
75 const void *reg_defaults_raw; 75 const void *reg_defaults_raw;
76 void *cache; 76 void *cache;
77 bool cache_dirty;
77}; 78};
78 79
79struct regcache_ops { 80struct regcache_ops {
@@ -105,7 +106,7 @@ static inline void regmap_debugfs_exit(struct regmap *map) { }
105#endif 106#endif
106 107
107/* regcache core declarations */ 108/* regcache core declarations */
108int regcache_init(struct regmap *map); 109int regcache_init(struct regmap *map, const struct regmap_config *config);
109void regcache_exit(struct regmap *map); 110void regcache_exit(struct regmap *map);
110int regcache_read(struct regmap *map, 111int regcache_read(struct regmap *map,
111 unsigned int reg, unsigned int *value); 112 unsigned int reg, unsigned int *value);
@@ -118,10 +119,7 @@ unsigned int regcache_get_val(const void *base, unsigned int idx,
118bool regcache_set_val(void *base, unsigned int idx, 119bool regcache_set_val(void *base, unsigned int idx,
119 unsigned int val, unsigned int word_size); 120 unsigned int val, unsigned int word_size);
120int regcache_lookup_reg(struct regmap *map, unsigned int reg); 121int regcache_lookup_reg(struct regmap *map, unsigned int reg);
121int regcache_insert_reg(struct regmap *map, unsigned int reg,
122 unsigned int val);
123 122
124extern struct regcache_ops regcache_indexed_ops;
125extern struct regcache_ops regcache_rbtree_ops; 123extern struct regcache_ops regcache_rbtree_ops;
126extern struct regcache_ops regcache_lzo_ops; 124extern struct regcache_ops regcache_lzo_ops;
127 125
diff --git a/drivers/base/regmap/regcache-indexed.c b/drivers/base/regmap/regcache-indexed.c
deleted file mode 100644
index 507731ad8ec1..000000000000
--- a/drivers/base/regmap/regcache-indexed.c
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * Register cache access API - indexed caching support
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/slab.h>
14
15#include "internal.h"
16
17static int regcache_indexed_read(struct regmap *map, unsigned int reg,
18 unsigned int *value)
19{
20 int ret;
21
22 ret = regcache_lookup_reg(map, reg);
23 if (ret >= 0)
24 *value = map->reg_defaults[ret].def;
25
26 return ret;
27}
28
29static int regcache_indexed_write(struct regmap *map, unsigned int reg,
30 unsigned int value)
31{
32 int ret;
33
34 ret = regcache_lookup_reg(map, reg);
35 if (ret < 0)
36 return regcache_insert_reg(map, reg, value);
37 map->reg_defaults[ret].def = value;
38 return 0;
39}
40
41static int regcache_indexed_sync(struct regmap *map)
42{
43 unsigned int i;
44 int ret;
45
46 for (i = 0; i < map->num_reg_defaults; i++) {
47 ret = _regmap_write(map, map->reg_defaults[i].reg,
48 map->reg_defaults[i].def);
49 if (ret < 0)
50 return ret;
51 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
52 map->reg_defaults[i].reg,
53 map->reg_defaults[i].def);
54 }
55 return 0;
56}
57
58struct regcache_ops regcache_indexed_ops = {
59 .type = REGCACHE_INDEXED,
60 .name = "indexed",
61 .read = regcache_indexed_read,
62 .write = regcache_indexed_write,
63 .sync = regcache_indexed_sync
64};
diff --git a/drivers/base/regmap/regcache-lzo.c b/drivers/base/regmap/regcache-lzo.c
index 066aeece3626..b7d16143edeb 100644
--- a/drivers/base/regmap/regcache-lzo.c
+++ b/drivers/base/regmap/regcache-lzo.c
@@ -15,6 +15,8 @@
15 15
16#include "internal.h" 16#include "internal.h"
17 17
18static int regcache_lzo_exit(struct regmap *map);
19
18struct regcache_lzo_ctx { 20struct regcache_lzo_ctx {
19 void *wmem; 21 void *wmem;
20 void *dst; 22 void *dst;
@@ -27,7 +29,7 @@ struct regcache_lzo_ctx {
27}; 29};
28 30
29#define LZO_BLOCK_NUM 8 31#define LZO_BLOCK_NUM 8
30static int regcache_lzo_block_count(void) 32static int regcache_lzo_block_count(struct regmap *map)
31{ 33{
32 return LZO_BLOCK_NUM; 34 return LZO_BLOCK_NUM;
33} 35}
@@ -106,19 +108,22 @@ static inline int regcache_lzo_get_blkindex(struct regmap *map,
106 unsigned int reg) 108 unsigned int reg)
107{ 109{
108 return (reg * map->cache_word_size) / 110 return (reg * map->cache_word_size) /
109 DIV_ROUND_UP(map->cache_size_raw, regcache_lzo_block_count()); 111 DIV_ROUND_UP(map->cache_size_raw,
112 regcache_lzo_block_count(map));
110} 113}
111 114
112static inline int regcache_lzo_get_blkpos(struct regmap *map, 115static inline int regcache_lzo_get_blkpos(struct regmap *map,
113 unsigned int reg) 116 unsigned int reg)
114{ 117{
115 return reg % (DIV_ROUND_UP(map->cache_size_raw, regcache_lzo_block_count()) / 118 return reg % (DIV_ROUND_UP(map->cache_size_raw,
119 regcache_lzo_block_count(map)) /
116 map->cache_word_size); 120 map->cache_word_size);
117} 121}
118 122
119static inline int regcache_lzo_get_blksize(struct regmap *map) 123static inline int regcache_lzo_get_blksize(struct regmap *map)
120{ 124{
121 return DIV_ROUND_UP(map->cache_size_raw, regcache_lzo_block_count()); 125 return DIV_ROUND_UP(map->cache_size_raw,
126 regcache_lzo_block_count(map));
122} 127}
123 128
124static int regcache_lzo_init(struct regmap *map) 129static int regcache_lzo_init(struct regmap *map)
@@ -131,7 +136,7 @@ static int regcache_lzo_init(struct regmap *map)
131 136
132 ret = 0; 137 ret = 0;
133 138
134 blkcount = regcache_lzo_block_count(); 139 blkcount = regcache_lzo_block_count(map);
135 map->cache = kzalloc(blkcount * sizeof *lzo_blocks, 140 map->cache = kzalloc(blkcount * sizeof *lzo_blocks,
136 GFP_KERNEL); 141 GFP_KERNEL);
137 if (!map->cache) 142 if (!map->cache)
@@ -190,7 +195,7 @@ static int regcache_lzo_init(struct regmap *map)
190 195
191 return 0; 196 return 0;
192err: 197err:
193 regcache_exit(map); 198 regcache_lzo_exit(map);
194 return ret; 199 return ret;
195} 200}
196 201
@@ -203,7 +208,7 @@ static int regcache_lzo_exit(struct regmap *map)
203 if (!lzo_blocks) 208 if (!lzo_blocks)
204 return 0; 209 return 0;
205 210
206 blkcount = regcache_lzo_block_count(); 211 blkcount = regcache_lzo_block_count(map);
207 /* 212 /*
208 * the pointer to the bitmap used for syncing the cache 213 * the pointer to the bitmap used for syncing the cache
209 * is shared amongst all lzo_blocks. Ensure it is freed 214 * is shared amongst all lzo_blocks. Ensure it is freed
@@ -351,7 +356,7 @@ static int regcache_lzo_sync(struct regmap *map)
351} 356}
352 357
353struct regcache_ops regcache_lzo_ops = { 358struct regcache_ops regcache_lzo_ops = {
354 .type = REGCACHE_LZO, 359 .type = REGCACHE_COMPRESSED,
355 .name = "lzo", 360 .name = "lzo",
356 .init = regcache_lzo_init, 361 .init = regcache_lzo_init,
357 .exit = regcache_lzo_exit, 362 .exit = regcache_lzo_exit,
diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index e31498499b0f..32620c4f1683 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -11,12 +11,15 @@
11 */ 11 */
12 12
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/debugfs.h>
14#include <linux/rbtree.h> 15#include <linux/rbtree.h>
16#include <linux/seq_file.h>
15 17
16#include "internal.h" 18#include "internal.h"
17 19
18static int regcache_rbtree_write(struct regmap *map, unsigned int reg, 20static int regcache_rbtree_write(struct regmap *map, unsigned int reg,
19 unsigned int value); 21 unsigned int value);
22static int regcache_rbtree_exit(struct regmap *map);
20 23
21struct regcache_rbtree_node { 24struct regcache_rbtree_node {
22 /* the actual rbtree node holding this block */ 25 /* the actual rbtree node holding this block */
@@ -124,6 +127,60 @@ static int regcache_rbtree_insert(struct rb_root *root,
124 return 1; 127 return 1;
125} 128}
126 129
130#ifdef CONFIG_DEBUG_FS
131static int rbtree_show(struct seq_file *s, void *ignored)
132{
133 struct regmap *map = s->private;
134 struct regcache_rbtree_ctx *rbtree_ctx = map->cache;
135 struct regcache_rbtree_node *n;
136 struct rb_node *node;
137 unsigned int base, top;
138 int nodes = 0;
139 int registers = 0;
140
141 mutex_lock(&map->lock);
142
143 for (node = rb_first(&rbtree_ctx->root); node != NULL;
144 node = rb_next(node)) {
145 n = container_of(node, struct regcache_rbtree_node, node);
146
147 regcache_rbtree_get_base_top_reg(n, &base, &top);
148 seq_printf(s, "%x-%x (%d)\n", base, top, top - base + 1);
149
150 nodes++;
151 registers += top - base + 1;
152 }
153
154 seq_printf(s, "%d nodes, %d registers, average %d registers\n",
155 nodes, registers, registers / nodes);
156
157 mutex_unlock(&map->lock);
158
159 return 0;
160}
161
162static int rbtree_open(struct inode *inode, struct file *file)
163{
164 return single_open(file, rbtree_show, inode->i_private);
165}
166
167static const struct file_operations rbtree_fops = {
168 .open = rbtree_open,
169 .read = seq_read,
170 .llseek = seq_lseek,
171 .release = single_release,
172};
173
174static void rbtree_debugfs_init(struct regmap *map)
175{
176 debugfs_create_file("rbtree", 0400, map->debugfs, map, &rbtree_fops);
177}
178#else
179static void rbtree_debugfs_init(struct regmap *map)
180{
181}
182#endif
183
127static int regcache_rbtree_init(struct regmap *map) 184static int regcache_rbtree_init(struct regmap *map)
128{ 185{
129 struct regcache_rbtree_ctx *rbtree_ctx; 186 struct regcache_rbtree_ctx *rbtree_ctx;
@@ -146,10 +203,12 @@ static int regcache_rbtree_init(struct regmap *map)
146 goto err; 203 goto err;
147 } 204 }
148 205
206 rbtree_debugfs_init(map);
207
149 return 0; 208 return 0;
150 209
151err: 210err:
152 regcache_exit(map); 211 regcache_rbtree_exit(map);
153 return ret; 212 return ret;
154} 213}
155 214
diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c
index 666f6f5011dc..1ead66186b7c 100644
--- a/drivers/base/regmap/regcache.c
+++ b/drivers/base/regmap/regcache.c
@@ -19,7 +19,6 @@
19#include "internal.h" 19#include "internal.h"
20 20
21static const struct regcache_ops *cache_types[] = { 21static const struct regcache_ops *cache_types[] = {
22 &regcache_indexed_ops,
23 &regcache_rbtree_ops, 22 &regcache_rbtree_ops,
24 &regcache_lzo_ops, 23 &regcache_lzo_ops,
25}; 24};
@@ -61,8 +60,10 @@ static int regcache_hw_init(struct regmap *map)
61 60
62 map->reg_defaults = kmalloc(count * sizeof(struct reg_default), 61 map->reg_defaults = kmalloc(count * sizeof(struct reg_default),
63 GFP_KERNEL); 62 GFP_KERNEL);
64 if (!map->reg_defaults) 63 if (!map->reg_defaults) {
65 return -ENOMEM; 64 ret = -ENOMEM;
65 goto err_free;
66 }
66 67
67 /* fill the reg_defaults */ 68 /* fill the reg_defaults */
68 map->num_reg_defaults = count; 69 map->num_reg_defaults = count;
@@ -77,9 +78,15 @@ static int regcache_hw_init(struct regmap *map)
77 } 78 }
78 79
79 return 0; 80 return 0;
81
82err_free:
83 if (map->cache_free)
84 kfree(map->reg_defaults_raw);
85
86 return ret;
80} 87}
81 88
82int regcache_init(struct regmap *map) 89int regcache_init(struct regmap *map, const struct regmap_config *config)
83{ 90{
84 int ret; 91 int ret;
85 int i; 92 int i;
@@ -100,6 +107,12 @@ int regcache_init(struct regmap *map)
100 return -EINVAL; 107 return -EINVAL;
101 } 108 }
102 109
110 map->num_reg_defaults = config->num_reg_defaults;
111 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
112 map->reg_defaults_raw = config->reg_defaults_raw;
113 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
114 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
115
103 map->cache = NULL; 116 map->cache = NULL;
104 map->cache_ops = cache_types[i]; 117 map->cache_ops = cache_types[i];
105 118
@@ -112,10 +125,10 @@ int regcache_init(struct regmap *map)
112 * won't vanish from under us. We'll need to make 125 * won't vanish from under us. We'll need to make
113 * a copy of it. 126 * a copy of it.
114 */ 127 */
115 if (map->reg_defaults) { 128 if (config->reg_defaults) {
116 if (!map->num_reg_defaults) 129 if (!map->num_reg_defaults)
117 return -EINVAL; 130 return -EINVAL;
118 tmp_buf = kmemdup(map->reg_defaults, map->num_reg_defaults * 131 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
119 sizeof(struct reg_default), GFP_KERNEL); 132 sizeof(struct reg_default), GFP_KERNEL);
120 if (!tmp_buf) 133 if (!tmp_buf)
121 return -ENOMEM; 134 return -ENOMEM;
@@ -136,9 +149,18 @@ int regcache_init(struct regmap *map)
136 if (map->cache_ops->init) { 149 if (map->cache_ops->init) {
137 dev_dbg(map->dev, "Initializing %s cache\n", 150 dev_dbg(map->dev, "Initializing %s cache\n",
138 map->cache_ops->name); 151 map->cache_ops->name);
139 return map->cache_ops->init(map); 152 ret = map->cache_ops->init(map);
153 if (ret)
154 goto err_free;
140 } 155 }
141 return 0; 156 return 0;
157
158err_free:
159 kfree(map->reg_defaults);
160 if (map->cache_free)
161 kfree(map->reg_defaults_raw);
162
163 return ret;
142} 164}
143 165
144void regcache_exit(struct regmap *map) 166void regcache_exit(struct regmap *map)
@@ -171,16 +193,21 @@ void regcache_exit(struct regmap *map)
171int regcache_read(struct regmap *map, 193int regcache_read(struct regmap *map,
172 unsigned int reg, unsigned int *value) 194 unsigned int reg, unsigned int *value)
173{ 195{
196 int ret;
197
174 if (map->cache_type == REGCACHE_NONE) 198 if (map->cache_type == REGCACHE_NONE)
175 return -ENOSYS; 199 return -ENOSYS;
176 200
177 BUG_ON(!map->cache_ops); 201 BUG_ON(!map->cache_ops);
178 202
179 if (!regmap_readable(map, reg)) 203 if (!regmap_volatile(map, reg)) {
180 return -EIO; 204 ret = map->cache_ops->read(map, reg, value);
181 205
182 if (!regmap_volatile(map, reg)) 206 if (ret == 0)
183 return map->cache_ops->read(map, reg, value); 207 trace_regmap_reg_read_cache(map->dev, reg, *value);
208
209 return ret;
210 }
184 211
185 return -EINVAL; 212 return -EINVAL;
186} 213}
@@ -241,6 +268,8 @@ int regcache_sync(struct regmap *map)
241 map->cache_ops->name); 268 map->cache_ops->name);
242 name = map->cache_ops->name; 269 name = map->cache_ops->name;
243 trace_regcache_sync(map->dev, name, "start"); 270 trace_regcache_sync(map->dev, name, "start");
271 if (!map->cache_dirty)
272 goto out;
244 if (map->cache_ops->sync) { 273 if (map->cache_ops->sync) {
245 ret = map->cache_ops->sync(map); 274 ret = map->cache_ops->sync(map);
246 } else { 275 } else {
@@ -291,6 +320,23 @@ void regcache_cache_only(struct regmap *map, bool enable)
291EXPORT_SYMBOL_GPL(regcache_cache_only); 320EXPORT_SYMBOL_GPL(regcache_cache_only);
292 321
293/** 322/**
323 * regcache_mark_dirty: Mark the register cache as dirty
324 *
325 * @map: map to mark
326 *
327 * Mark the register cache as dirty, for example due to the device
328 * having been powered down for suspend. If the cache is not marked
329 * as dirty then the cache sync will be suppressed.
330 */
331void regcache_mark_dirty(struct regmap *map)
332{
333 mutex_lock(&map->lock);
334 map->cache_dirty = true;
335 mutex_unlock(&map->lock);
336}
337EXPORT_SYMBOL_GPL(regcache_mark_dirty);
338
339/**
294 * regcache_cache_bypass: Put a register map into cache bypass mode 340 * regcache_cache_bypass: Put a register map into cache bypass mode
295 * 341 *
296 * @map: map to configure 342 * @map: map to configure
@@ -381,22 +427,3 @@ int regcache_lookup_reg(struct regmap *map, unsigned int reg)
381 else 427 else
382 return -ENOENT; 428 return -ENOENT;
383} 429}
384
385int regcache_insert_reg(struct regmap *map, unsigned int reg,
386 unsigned int val)
387{
388 void *tmp;
389
390 tmp = krealloc(map->reg_defaults,
391 (map->num_reg_defaults + 1) * sizeof(struct reg_default),
392 GFP_KERNEL);
393 if (!tmp)
394 return -ENOMEM;
395 map->reg_defaults = tmp;
396 map->num_reg_defaults++;
397 map->reg_defaults[map->num_reg_defaults - 1].reg = reg;
398 map->reg_defaults[map->num_reg_defaults - 1].def = val;
399 sort(map->reg_defaults, map->num_reg_defaults,
400 sizeof(struct reg_default), regcache_default_cmp, NULL);
401 return 0;
402}
diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
new file mode 100644
index 000000000000..428836fc5835
--- /dev/null
+++ b/drivers/base/regmap/regmap-irq.c
@@ -0,0 +1,302 @@
1/*
2 * regmap based irq_chip
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/export.h>
14#include <linux/regmap.h>
15#include <linux/irq.h>
16#include <linux/interrupt.h>
17#include <linux/slab.h>
18
19#include "internal.h"
20
21struct regmap_irq_chip_data {
22 struct mutex lock;
23
24 struct regmap *map;
25 struct regmap_irq_chip *chip;
26
27 int irq_base;
28
29 void *status_reg_buf;
30 unsigned int *status_buf;
31 unsigned int *mask_buf;
32 unsigned int *mask_buf_def;
33};
34
35static inline const
36struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
37 int irq)
38{
39 return &data->chip->irqs[irq - data->irq_base];
40}
41
42static void regmap_irq_lock(struct irq_data *data)
43{
44 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
45
46 mutex_lock(&d->lock);
47}
48
49static void regmap_irq_sync_unlock(struct irq_data *data)
50{
51 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
52 int i, ret;
53
54 /*
55 * If there's been a change in the mask write it back to the
56 * hardware. We rely on the use of the regmap core cache to
57 * suppress pointless writes.
58 */
59 for (i = 0; i < d->chip->num_regs; i++) {
60 ret = regmap_update_bits(d->map, d->chip->mask_base + i,
61 d->mask_buf_def[i], d->mask_buf[i]);
62 if (ret != 0)
63 dev_err(d->map->dev, "Failed to sync masks in %x\n",
64 d->chip->mask_base + i);
65 }
66
67 mutex_unlock(&d->lock);
68}
69
70static void regmap_irq_enable(struct irq_data *data)
71{
72 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
73 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq);
74
75 d->mask_buf[irq_data->reg_offset] &= ~irq_data->mask;
76}
77
78static void regmap_irq_disable(struct irq_data *data)
79{
80 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
81 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq);
82
83 d->mask_buf[irq_data->reg_offset] |= irq_data->mask;
84}
85
86static struct irq_chip regmap_irq_chip = {
87 .name = "regmap",
88 .irq_bus_lock = regmap_irq_lock,
89 .irq_bus_sync_unlock = regmap_irq_sync_unlock,
90 .irq_disable = regmap_irq_disable,
91 .irq_enable = regmap_irq_enable,
92};
93
94static irqreturn_t regmap_irq_thread(int irq, void *d)
95{
96 struct regmap_irq_chip_data *data = d;
97 struct regmap_irq_chip *chip = data->chip;
98 struct regmap *map = data->map;
99 int ret, i;
100 u8 *buf8 = data->status_reg_buf;
101 u16 *buf16 = data->status_reg_buf;
102 u32 *buf32 = data->status_reg_buf;
103 bool handled = false;
104
105 ret = regmap_bulk_read(map, chip->status_base, data->status_reg_buf,
106 chip->num_regs);
107 if (ret != 0) {
108 dev_err(map->dev, "Failed to read IRQ status: %d\n", ret);
109 return IRQ_NONE;
110 }
111
112 /*
113 * Ignore masked IRQs and ack if we need to; we ack early so
114 * there is no race between handling and acknowleding the
115 * interrupt. We assume that typically few of the interrupts
116 * will fire simultaneously so don't worry about overhead from
117 * doing a write per register.
118 */
119 for (i = 0; i < data->chip->num_regs; i++) {
120 switch (map->format.val_bytes) {
121 case 1:
122 data->status_buf[i] = buf8[i];
123 break;
124 case 2:
125 data->status_buf[i] = buf16[i];
126 break;
127 case 4:
128 data->status_buf[i] = buf32[i];
129 break;
130 default:
131 BUG();
132 return IRQ_NONE;
133 }
134
135 data->status_buf[i] &= ~data->mask_buf[i];
136
137 if (data->status_buf[i] && chip->ack_base) {
138 ret = regmap_write(map, chip->ack_base + i,
139 data->status_buf[i]);
140 if (ret != 0)
141 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
142 chip->ack_base + i, ret);
143 }
144 }
145
146 for (i = 0; i < chip->num_irqs; i++) {
147 if (data->status_buf[chip->irqs[i].reg_offset] &
148 chip->irqs[i].mask) {
149 handle_nested_irq(data->irq_base + i);
150 handled = true;
151 }
152 }
153
154 if (handled)
155 return IRQ_HANDLED;
156 else
157 return IRQ_NONE;
158}
159
160/**
161 * regmap_add_irq_chip(): Use standard regmap IRQ controller handling
162 *
163 * map: The regmap for the device.
164 * irq: The IRQ the device uses to signal interrupts
165 * irq_flags: The IRQF_ flags to use for the primary interrupt.
166 * chip: Configuration for the interrupt controller.
167 * data: Runtime data structure for the controller, allocated on success
168 *
169 * Returns 0 on success or an errno on failure.
170 *
171 * In order for this to be efficient the chip really should use a
172 * register cache. The chip driver is responsible for restoring the
173 * register values used by the IRQ controller over suspend and resume.
174 */
175int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
176 int irq_base, struct regmap_irq_chip *chip,
177 struct regmap_irq_chip_data **data)
178{
179 struct regmap_irq_chip_data *d;
180 int cur_irq, i;
181 int ret = -ENOMEM;
182
183 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
184 if (irq_base < 0) {
185 dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
186 irq_base);
187 return irq_base;
188 }
189
190 d = kzalloc(sizeof(*d), GFP_KERNEL);
191 if (!d)
192 return -ENOMEM;
193
194 d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
195 GFP_KERNEL);
196 if (!d->status_buf)
197 goto err_alloc;
198
199 d->status_reg_buf = kzalloc(map->format.val_bytes * chip->num_regs,
200 GFP_KERNEL);
201 if (!d->status_reg_buf)
202 goto err_alloc;
203
204 d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
205 GFP_KERNEL);
206 if (!d->mask_buf)
207 goto err_alloc;
208
209 d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
210 GFP_KERNEL);
211 if (!d->mask_buf_def)
212 goto err_alloc;
213
214 d->map = map;
215 d->chip = chip;
216 d->irq_base = irq_base;
217 mutex_init(&d->lock);
218
219 for (i = 0; i < chip->num_irqs; i++)
220 d->mask_buf_def[chip->irqs[i].reg_offset]
221 |= chip->irqs[i].mask;
222
223 /* Mask all the interrupts by default */
224 for (i = 0; i < chip->num_regs; i++) {
225 d->mask_buf[i] = d->mask_buf_def[i];
226 ret = regmap_write(map, chip->mask_base + i, d->mask_buf[i]);
227 if (ret != 0) {
228 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
229 chip->mask_base + i, ret);
230 goto err_alloc;
231 }
232 }
233
234 /* Register them with genirq */
235 for (cur_irq = irq_base;
236 cur_irq < chip->num_irqs + irq_base;
237 cur_irq++) {
238 irq_set_chip_data(cur_irq, d);
239 irq_set_chip_and_handler(cur_irq, &regmap_irq_chip,
240 handle_edge_irq);
241 irq_set_nested_thread(cur_irq, 1);
242
243 /* ARM needs us to explicitly flag the IRQ as valid
244 * and will set them noprobe when we do so. */
245#ifdef CONFIG_ARM
246 set_irq_flags(cur_irq, IRQF_VALID);
247#else
248 irq_set_noprobe(cur_irq);
249#endif
250 }
251
252 ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
253 chip->name, d);
254 if (ret != 0) {
255 dev_err(map->dev, "Failed to request IRQ %d: %d\n", irq, ret);
256 goto err_alloc;
257 }
258
259 return 0;
260
261err_alloc:
262 kfree(d->mask_buf_def);
263 kfree(d->mask_buf);
264 kfree(d->status_reg_buf);
265 kfree(d->status_buf);
266 kfree(d);
267 return ret;
268}
269EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
270
271/**
272 * regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
273 *
274 * @irq: Primary IRQ for the device
275 * @d: regmap_irq_chip_data allocated by regmap_add_irq_chip()
276 */
277void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
278{
279 if (!d)
280 return;
281
282 free_irq(irq, d);
283 kfree(d->mask_buf_def);
284 kfree(d->mask_buf);
285 kfree(d->status_reg_buf);
286 kfree(d->status_buf);
287 kfree(d);
288}
289EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
290
291/**
292 * regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
293 *
294 * Useful for drivers to request their own IRQs.
295 *
296 * @data: regmap_irq controller to operate on.
297 */
298int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
299{
300 return data->irq_base;
301}
302EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index bf441db1ee90..be10a4ff6609 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -64,6 +64,18 @@ bool regmap_precious(struct regmap *map, unsigned int reg)
64 return false; 64 return false;
65} 65}
66 66
67static bool regmap_volatile_range(struct regmap *map, unsigned int reg,
68 unsigned int num)
69{
70 unsigned int i;
71
72 for (i = 0; i < num; i++)
73 if (!regmap_volatile(map, reg + i))
74 return false;
75
76 return true;
77}
78
67static void regmap_format_4_12_write(struct regmap *map, 79static void regmap_format_4_12_write(struct regmap *map,
68 unsigned int reg, unsigned int val) 80 unsigned int reg, unsigned int val)
69{ 81{
@@ -78,6 +90,16 @@ static void regmap_format_7_9_write(struct regmap *map,
78 *out = cpu_to_be16((reg << 9) | val); 90 *out = cpu_to_be16((reg << 9) | val);
79} 91}
80 92
93static void regmap_format_10_14_write(struct regmap *map,
94 unsigned int reg, unsigned int val)
95{
96 u8 *out = map->work_buf;
97
98 out[2] = val;
99 out[1] = (val >> 8) | (reg << 6);
100 out[0] = reg >> 2;
101}
102
81static void regmap_format_8(void *buf, unsigned int val) 103static void regmap_format_8(void *buf, unsigned int val)
82{ 104{
83 u8 *b = buf; 105 u8 *b = buf;
@@ -127,7 +149,7 @@ struct regmap *regmap_init(struct device *dev,
127 int ret = -EINVAL; 149 int ret = -EINVAL;
128 150
129 if (!bus || !config) 151 if (!bus || !config)
130 return NULL; 152 goto err;
131 153
132 map = kzalloc(sizeof(*map), GFP_KERNEL); 154 map = kzalloc(sizeof(*map), GFP_KERNEL);
133 if (map == NULL) { 155 if (map == NULL) {
@@ -147,12 +169,6 @@ struct regmap *regmap_init(struct device *dev,
147 map->volatile_reg = config->volatile_reg; 169 map->volatile_reg = config->volatile_reg;
148 map->precious_reg = config->precious_reg; 170 map->precious_reg = config->precious_reg;
149 map->cache_type = config->cache_type; 171 map->cache_type = config->cache_type;
150 map->reg_defaults = config->reg_defaults;
151 map->num_reg_defaults = config->num_reg_defaults;
152 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
153 map->reg_defaults_raw = config->reg_defaults_raw;
154 map->cache_size_raw = (config->val_bits / 8) * config->num_reg_defaults_raw;
155 map->cache_word_size = config->val_bits / 8;
156 172
157 if (config->read_flag_mask || config->write_flag_mask) { 173 if (config->read_flag_mask || config->write_flag_mask) {
158 map->read_flag_mask = config->read_flag_mask; 174 map->read_flag_mask = config->read_flag_mask;
@@ -182,6 +198,16 @@ struct regmap *regmap_init(struct device *dev,
182 } 198 }
183 break; 199 break;
184 200
201 case 10:
202 switch (config->val_bits) {
203 case 14:
204 map->format.format_write = regmap_format_10_14_write;
205 break;
206 default:
207 goto err_map;
208 }
209 break;
210
185 case 8: 211 case 8:
186 map->format.format_reg = regmap_format_8; 212 map->format.format_reg = regmap_format_8;
187 break; 213 break;
@@ -215,14 +241,16 @@ struct regmap *regmap_init(struct device *dev,
215 goto err_map; 241 goto err_map;
216 } 242 }
217 243
218 ret = regcache_init(map);
219 if (ret < 0)
220 goto err_map;
221
222 regmap_debugfs_init(map); 244 regmap_debugfs_init(map);
223 245
246 ret = regcache_init(map, config);
247 if (ret < 0)
248 goto err_free_workbuf;
249
224 return map; 250 return map;
225 251
252err_free_workbuf:
253 kfree(map->work_buf);
226err_map: 254err_map:
227 kfree(map); 255 kfree(map);
228err: 256err:
@@ -231,6 +259,39 @@ err:
231EXPORT_SYMBOL_GPL(regmap_init); 259EXPORT_SYMBOL_GPL(regmap_init);
232 260
233/** 261/**
262 * regmap_reinit_cache(): Reinitialise the current register cache
263 *
264 * @map: Register map to operate on.
265 * @config: New configuration. Only the cache data will be used.
266 *
267 * Discard any existing register cache for the map and initialize a
268 * new cache. This can be used to restore the cache to defaults or to
269 * update the cache configuration to reflect runtime discovery of the
270 * hardware.
271 */
272int regmap_reinit_cache(struct regmap *map, const struct regmap_config *config)
273{
274 int ret;
275
276 mutex_lock(&map->lock);
277
278 regcache_exit(map);
279
280 map->max_register = config->max_register;
281 map->writeable_reg = config->writeable_reg;
282 map->readable_reg = config->readable_reg;
283 map->volatile_reg = config->volatile_reg;
284 map->precious_reg = config->precious_reg;
285 map->cache_type = config->cache_type;
286
287 ret = regcache_init(map, config);
288
289 mutex_unlock(&map->lock);
290
291 return ret;
292}
293
294/**
234 * regmap_exit(): Free a previously allocated register map 295 * regmap_exit(): Free a previously allocated register map
235 */ 296 */
236void regmap_exit(struct regmap *map) 297void regmap_exit(struct regmap *map)
@@ -306,8 +367,10 @@ int _regmap_write(struct regmap *map, unsigned int reg,
306 ret = regcache_write(map, reg, val); 367 ret = regcache_write(map, reg, val);
307 if (ret != 0) 368 if (ret != 0)
308 return ret; 369 return ret;
309 if (map->cache_only) 370 if (map->cache_only) {
371 map->cache_dirty = true;
310 return 0; 372 return 0;
373 }
311 } 374 }
312 375
313 trace_regmap_reg_write(map->dev, reg, val); 376 trace_regmap_reg_write(map->dev, reg, val);
@@ -375,9 +438,11 @@ EXPORT_SYMBOL_GPL(regmap_write);
375int regmap_raw_write(struct regmap *map, unsigned int reg, 438int regmap_raw_write(struct regmap *map, unsigned int reg,
376 const void *val, size_t val_len) 439 const void *val, size_t val_len)
377{ 440{
441 size_t val_count = val_len / map->format.val_bytes;
378 int ret; 442 int ret;
379 443
380 WARN_ON(map->cache_type != REGCACHE_NONE); 444 WARN_ON(!regmap_volatile_range(map, reg, val_count) &&
445 map->cache_type != REGCACHE_NONE);
381 446
382 mutex_lock(&map->lock); 447 mutex_lock(&map->lock);
383 448
@@ -422,15 +487,15 @@ static int _regmap_read(struct regmap *map, unsigned int reg,
422{ 487{
423 int ret; 488 int ret;
424 489
425 if (!map->format.parse_val)
426 return -EINVAL;
427
428 if (!map->cache_bypass) { 490 if (!map->cache_bypass) {
429 ret = regcache_read(map, reg, val); 491 ret = regcache_read(map, reg, val);
430 if (ret == 0) 492 if (ret == 0)
431 return 0; 493 return 0;
432 } 494 }
433 495
496 if (!map->format.parse_val)
497 return -EINVAL;
498
434 if (map->cache_only) 499 if (map->cache_only)
435 return -EBUSY; 500 return -EBUSY;
436 501
@@ -481,15 +546,11 @@ EXPORT_SYMBOL_GPL(regmap_read);
481int regmap_raw_read(struct regmap *map, unsigned int reg, void *val, 546int regmap_raw_read(struct regmap *map, unsigned int reg, void *val,
482 size_t val_len) 547 size_t val_len)
483{ 548{
549 size_t val_count = val_len / map->format.val_bytes;
484 int ret; 550 int ret;
485 int i;
486 bool vol = true;
487 551
488 for (i = 0; i < val_len / map->format.val_bytes; i++) 552 WARN_ON(!regmap_volatile_range(map, reg, val_count) &&
489 if (!regmap_volatile(map, reg + i)) 553 map->cache_type != REGCACHE_NONE);
490 vol = false;
491
492 WARN_ON(!vol && map->cache_type != REGCACHE_NONE);
493 554
494 mutex_lock(&map->lock); 555 mutex_lock(&map->lock);
495 556
@@ -517,16 +578,11 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
517{ 578{
518 int ret, i; 579 int ret, i;
519 size_t val_bytes = map->format.val_bytes; 580 size_t val_bytes = map->format.val_bytes;
520 bool vol = true; 581 bool vol = regmap_volatile_range(map, reg, val_count);
521 582
522 if (!map->format.parse_val) 583 if (!map->format.parse_val)
523 return -EINVAL; 584 return -EINVAL;
524 585
525 /* Is this a block of volatile registers? */
526 for (i = 0; i < val_count; i++)
527 if (!regmap_volatile(map, reg + i))
528 vol = false;
529
530 if (vol || map->cache_type == REGCACHE_NONE) { 586 if (vol || map->cache_type == REGCACHE_NONE) {
531 ret = regmap_raw_read(map, reg, val, val_bytes * val_count); 587 ret = regmap_raw_read(map, reg, val, val_bytes * val_count);
532 if (ret != 0) 588 if (ret != 0)
@@ -546,40 +602,73 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
546} 602}
547EXPORT_SYMBOL_GPL(regmap_bulk_read); 603EXPORT_SYMBOL_GPL(regmap_bulk_read);
548 604
549/** 605static int _regmap_update_bits(struct regmap *map, unsigned int reg,
550 * remap_update_bits: Perform a read/modify/write cycle on the register map 606 unsigned int mask, unsigned int val,
551 * 607 bool *change)
552 * @map: Register map to update
553 * @reg: Register to update
554 * @mask: Bitmask to change
555 * @val: New value for bitmask
556 *
557 * Returns zero for success, a negative number on error.
558 */
559int regmap_update_bits(struct regmap *map, unsigned int reg,
560 unsigned int mask, unsigned int val)
561{ 608{
562 int ret; 609 int ret;
563 unsigned int tmp; 610 unsigned int tmp, orig;
564 611
565 mutex_lock(&map->lock); 612 mutex_lock(&map->lock);
566 613
567 ret = _regmap_read(map, reg, &tmp); 614 ret = _regmap_read(map, reg, &orig);
568 if (ret != 0) 615 if (ret != 0)
569 goto out; 616 goto out;
570 617
571 tmp &= ~mask; 618 tmp = orig & ~mask;
572 tmp |= val & mask; 619 tmp |= val & mask;
573 620
574 ret = _regmap_write(map, reg, tmp); 621 if (tmp != orig) {
622 ret = _regmap_write(map, reg, tmp);
623 *change = true;
624 } else {
625 *change = false;
626 }
575 627
576out: 628out:
577 mutex_unlock(&map->lock); 629 mutex_unlock(&map->lock);
578 630
579 return ret; 631 return ret;
580} 632}
633
634/**
635 * regmap_update_bits: Perform a read/modify/write cycle on the register map
636 *
637 * @map: Register map to update
638 * @reg: Register to update
639 * @mask: Bitmask to change
640 * @val: New value for bitmask
641 *
642 * Returns zero for success, a negative number on error.
643 */
644int regmap_update_bits(struct regmap *map, unsigned int reg,
645 unsigned int mask, unsigned int val)
646{
647 bool change;
648 return _regmap_update_bits(map, reg, mask, val, &change);
649}
581EXPORT_SYMBOL_GPL(regmap_update_bits); 650EXPORT_SYMBOL_GPL(regmap_update_bits);
582 651
652/**
653 * regmap_update_bits_check: Perform a read/modify/write cycle on the
654 * register map and report if updated
655 *
656 * @map: Register map to update
657 * @reg: Register to update
658 * @mask: Bitmask to change
659 * @val: New value for bitmask
660 * @change: Boolean indicating if a write was done
661 *
662 * Returns zero for success, a negative number on error.
663 */
664int regmap_update_bits_check(struct regmap *map, unsigned int reg,
665 unsigned int mask, unsigned int val,
666 bool *change)
667{
668 return _regmap_update_bits(map, reg, mask, val, change);
669}
670EXPORT_SYMBOL_GPL(regmap_update_bits_check);
671
583static int __init regmap_initcall(void) 672static int __init regmap_initcall(void)
584{ 673{
585 regmap_debugfs_initcall(); 674 regmap_debugfs_initcall();
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d476880c6fff..5099681cf503 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -70,7 +70,7 @@ config GPIO_GENERIC
70 70
71config GPIO_DA9052 71config GPIO_DA9052
72 tristate "Dialog DA9052 GPIO" 72 tristate "Dialog DA9052 GPIO"
73 depends on PMIC_DA9052 73 depends on PMIC_DA9052 && BROKEN
74 help 74 help
75 Say yes here to enable the GPIO driver for the DA9052 chip. 75 Say yes here to enable the GPIO driver for the DA9052 chip.
76 76
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index f1391c21ef26..c8322eefc865 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -328,6 +328,34 @@ config PMIC_DA903X
328 individual components like LCD backlight, voltage regulators, 328 individual components like LCD backlight, voltage regulators,
329 LEDs and battery-charger under the corresponding menus. 329 LEDs and battery-charger under the corresponding menus.
330 330
331config PMIC_DA9052
332 bool
333 select MFD_CORE
334
335config MFD_DA9052_SPI
336 bool "Support Dialog Semiconductor DA9052/53 PMIC variants with SPI"
337 select REGMAP_SPI
338 select REGMAP_IRQ
339 select PMIC_DA9052
340 depends on SPI_MASTER=y
341 help
342 Support for the Dialog Semiconductor DA9052 PMIC
343 when controlled using SPI. This driver provides common support
344 for accessing the device, additional drivers must be enabled in
345 order to use the functionality of the device.
346
347config MFD_DA9052_I2C
348 bool "Support Dialog Semiconductor DA9052/53 PMIC variants with I2C"
349 select REGMAP_I2C
350 select REGMAP_IRQ
351 select PMIC_DA9052
352 depends on I2C=y
353 help
354 Support for the Dialog Semiconductor DA9052 PMIC
355 when controlled using I2C. This driver provides common support
356 for accessing the device, additional drivers must be enabled in
357 order to use the functionality of the device.
358
331config PMIC_ADP5520 359config PMIC_ADP5520
332 bool "Analog Devices ADP5520/01 MFD PMIC Core Support" 360 bool "Analog Devices ADP5520/01 MFD PMIC Core Support"
333 depends on I2C=y 361 depends on I2C=y
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b2292eb75242..d5f574306c7f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -67,6 +67,11 @@ endif
67obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o 67obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o
68 68
69obj-$(CONFIG_PMIC_DA903X) += da903x.o 69obj-$(CONFIG_PMIC_DA903X) += da903x.o
70
71obj-$(CONFIG_PMIC_DA9052) += da9052-core.o
72obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o
73obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o
74
70max8925-objs := max8925-core.o max8925-i2c.o 75max8925-objs := max8925-core.o max8925-i2c.o
71obj-$(CONFIG_MFD_MAX8925) += max8925.o 76obj-$(CONFIG_MFD_MAX8925) += max8925.o
72obj-$(CONFIG_MFD_MAX8997) += max8997.o max8997-irq.o 77obj-$(CONFIG_MFD_MAX8997) += max8997.o max8997-irq.o
diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c
new file mode 100644
index 000000000000..5ddde2a9176a
--- /dev/null
+++ b/drivers/mfd/da9052-core.c
@@ -0,0 +1,694 @@
1/*
2 * Device access for Dialog DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/device.h>
15#include <linux/delay.h>
16#include <linux/input.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/mutex.h>
20#include <linux/mfd/core.h>
21#include <linux/slab.h>
22#include <linux/module.h>
23
24#include <linux/mfd/da9052/da9052.h>
25#include <linux/mfd/da9052/pdata.h>
26#include <linux/mfd/da9052/reg.h>
27
28#define DA9052_NUM_IRQ_REGS 4
29#define DA9052_IRQ_MASK_POS_1 0x01
30#define DA9052_IRQ_MASK_POS_2 0x02
31#define DA9052_IRQ_MASK_POS_3 0x04
32#define DA9052_IRQ_MASK_POS_4 0x08
33#define DA9052_IRQ_MASK_POS_5 0x10
34#define DA9052_IRQ_MASK_POS_6 0x20
35#define DA9052_IRQ_MASK_POS_7 0x40
36#define DA9052_IRQ_MASK_POS_8 0x80
37
38static bool da9052_reg_readable(struct device *dev, unsigned int reg)
39{
40 switch (reg) {
41 case DA9052_PAGE0_CON_REG:
42 case DA9052_STATUS_A_REG:
43 case DA9052_STATUS_B_REG:
44 case DA9052_STATUS_C_REG:
45 case DA9052_STATUS_D_REG:
46 case DA9052_EVENT_A_REG:
47 case DA9052_EVENT_B_REG:
48 case DA9052_EVENT_C_REG:
49 case DA9052_EVENT_D_REG:
50 case DA9052_FAULTLOG_REG:
51 case DA9052_IRQ_MASK_A_REG:
52 case DA9052_IRQ_MASK_B_REG:
53 case DA9052_IRQ_MASK_C_REG:
54 case DA9052_IRQ_MASK_D_REG:
55 case DA9052_CONTROL_A_REG:
56 case DA9052_CONTROL_B_REG:
57 case DA9052_CONTROL_C_REG:
58 case DA9052_CONTROL_D_REG:
59 case DA9052_PDDIS_REG:
60 case DA9052_INTERFACE_REG:
61 case DA9052_RESET_REG:
62 case DA9052_GPIO_0_1_REG:
63 case DA9052_GPIO_2_3_REG:
64 case DA9052_GPIO_4_5_REG:
65 case DA9052_GPIO_6_7_REG:
66 case DA9052_GPIO_14_15_REG:
67 case DA9052_ID_0_1_REG:
68 case DA9052_ID_2_3_REG:
69 case DA9052_ID_4_5_REG:
70 case DA9052_ID_6_7_REG:
71 case DA9052_ID_8_9_REG:
72 case DA9052_ID_10_11_REG:
73 case DA9052_ID_12_13_REG:
74 case DA9052_ID_14_15_REG:
75 case DA9052_ID_16_17_REG:
76 case DA9052_ID_18_19_REG:
77 case DA9052_ID_20_21_REG:
78 case DA9052_SEQ_STATUS_REG:
79 case DA9052_SEQ_A_REG:
80 case DA9052_SEQ_B_REG:
81 case DA9052_SEQ_TIMER_REG:
82 case DA9052_BUCKA_REG:
83 case DA9052_BUCKB_REG:
84 case DA9052_BUCKCORE_REG:
85 case DA9052_BUCKPRO_REG:
86 case DA9052_BUCKMEM_REG:
87 case DA9052_BUCKPERI_REG:
88 case DA9052_LDO1_REG:
89 case DA9052_LDO2_REG:
90 case DA9052_LDO3_REG:
91 case DA9052_LDO4_REG:
92 case DA9052_LDO5_REG:
93 case DA9052_LDO6_REG:
94 case DA9052_LDO7_REG:
95 case DA9052_LDO8_REG:
96 case DA9052_LDO9_REG:
97 case DA9052_LDO10_REG:
98 case DA9052_SUPPLY_REG:
99 case DA9052_PULLDOWN_REG:
100 case DA9052_CHGBUCK_REG:
101 case DA9052_WAITCONT_REG:
102 case DA9052_ISET_REG:
103 case DA9052_BATCHG_REG:
104 case DA9052_CHG_CONT_REG:
105 case DA9052_INPUT_CONT_REG:
106 case DA9052_CHG_TIME_REG:
107 case DA9052_BBAT_CONT_REG:
108 case DA9052_BOOST_REG:
109 case DA9052_LED_CONT_REG:
110 case DA9052_LEDMIN123_REG:
111 case DA9052_LED1_CONF_REG:
112 case DA9052_LED2_CONF_REG:
113 case DA9052_LED3_CONF_REG:
114 case DA9052_LED1CONT_REG:
115 case DA9052_LED2CONT_REG:
116 case DA9052_LED3CONT_REG:
117 case DA9052_LED_CONT_4_REG:
118 case DA9052_LED_CONT_5_REG:
119 case DA9052_ADC_MAN_REG:
120 case DA9052_ADC_CONT_REG:
121 case DA9052_ADC_RES_L_REG:
122 case DA9052_ADC_RES_H_REG:
123 case DA9052_VDD_RES_REG:
124 case DA9052_VDD_MON_REG:
125 case DA9052_ICHG_AV_REG:
126 case DA9052_ICHG_THD_REG:
127 case DA9052_ICHG_END_REG:
128 case DA9052_TBAT_RES_REG:
129 case DA9052_TBAT_HIGHP_REG:
130 case DA9052_TBAT_HIGHN_REG:
131 case DA9052_TBAT_LOW_REG:
132 case DA9052_T_OFFSET_REG:
133 case DA9052_ADCIN4_RES_REG:
134 case DA9052_AUTO4_HIGH_REG:
135 case DA9052_AUTO4_LOW_REG:
136 case DA9052_ADCIN5_RES_REG:
137 case DA9052_AUTO5_HIGH_REG:
138 case DA9052_AUTO5_LOW_REG:
139 case DA9052_ADCIN6_RES_REG:
140 case DA9052_AUTO6_HIGH_REG:
141 case DA9052_AUTO6_LOW_REG:
142 case DA9052_TJUNC_RES_REG:
143 case DA9052_TSI_CONT_A_REG:
144 case DA9052_TSI_CONT_B_REG:
145 case DA9052_TSI_X_MSB_REG:
146 case DA9052_TSI_Y_MSB_REG:
147 case DA9052_TSI_LSB_REG:
148 case DA9052_TSI_Z_MSB_REG:
149 case DA9052_COUNT_S_REG:
150 case DA9052_COUNT_MI_REG:
151 case DA9052_COUNT_H_REG:
152 case DA9052_COUNT_D_REG:
153 case DA9052_COUNT_MO_REG:
154 case DA9052_COUNT_Y_REG:
155 case DA9052_ALARM_MI_REG:
156 case DA9052_ALARM_H_REG:
157 case DA9052_ALARM_D_REG:
158 case DA9052_ALARM_MO_REG:
159 case DA9052_ALARM_Y_REG:
160 case DA9052_SECOND_A_REG:
161 case DA9052_SECOND_B_REG:
162 case DA9052_SECOND_C_REG:
163 case DA9052_SECOND_D_REG:
164 case DA9052_PAGE1_CON_REG:
165 return true;
166 default:
167 return false;
168 }
169}
170
171static bool da9052_reg_writeable(struct device *dev, unsigned int reg)
172{
173 switch (reg) {
174 case DA9052_PAGE0_CON_REG:
175 case DA9052_EVENT_A_REG:
176 case DA9052_EVENT_B_REG:
177 case DA9052_EVENT_C_REG:
178 case DA9052_EVENT_D_REG:
179 case DA9052_IRQ_MASK_A_REG:
180 case DA9052_IRQ_MASK_B_REG:
181 case DA9052_IRQ_MASK_C_REG:
182 case DA9052_IRQ_MASK_D_REG:
183 case DA9052_CONTROL_A_REG:
184 case DA9052_CONTROL_B_REG:
185 case DA9052_CONTROL_C_REG:
186 case DA9052_CONTROL_D_REG:
187 case DA9052_PDDIS_REG:
188 case DA9052_RESET_REG:
189 case DA9052_GPIO_0_1_REG:
190 case DA9052_GPIO_2_3_REG:
191 case DA9052_GPIO_4_5_REG:
192 case DA9052_GPIO_6_7_REG:
193 case DA9052_GPIO_14_15_REG:
194 case DA9052_ID_0_1_REG:
195 case DA9052_ID_2_3_REG:
196 case DA9052_ID_4_5_REG:
197 case DA9052_ID_6_7_REG:
198 case DA9052_ID_8_9_REG:
199 case DA9052_ID_10_11_REG:
200 case DA9052_ID_12_13_REG:
201 case DA9052_ID_14_15_REG:
202 case DA9052_ID_16_17_REG:
203 case DA9052_ID_18_19_REG:
204 case DA9052_ID_20_21_REG:
205 case DA9052_SEQ_STATUS_REG:
206 case DA9052_SEQ_A_REG:
207 case DA9052_SEQ_B_REG:
208 case DA9052_SEQ_TIMER_REG:
209 case DA9052_BUCKA_REG:
210 case DA9052_BUCKB_REG:
211 case DA9052_BUCKCORE_REG:
212 case DA9052_BUCKPRO_REG:
213 case DA9052_BUCKMEM_REG:
214 case DA9052_BUCKPERI_REG:
215 case DA9052_LDO1_REG:
216 case DA9052_LDO2_REG:
217 case DA9052_LDO3_REG:
218 case DA9052_LDO4_REG:
219 case DA9052_LDO5_REG:
220 case DA9052_LDO6_REG:
221 case DA9052_LDO7_REG:
222 case DA9052_LDO8_REG:
223 case DA9052_LDO9_REG:
224 case DA9052_LDO10_REG:
225 case DA9052_SUPPLY_REG:
226 case DA9052_PULLDOWN_REG:
227 case DA9052_CHGBUCK_REG:
228 case DA9052_WAITCONT_REG:
229 case DA9052_ISET_REG:
230 case DA9052_BATCHG_REG:
231 case DA9052_CHG_CONT_REG:
232 case DA9052_INPUT_CONT_REG:
233 case DA9052_BBAT_CONT_REG:
234 case DA9052_BOOST_REG:
235 case DA9052_LED_CONT_REG:
236 case DA9052_LEDMIN123_REG:
237 case DA9052_LED1_CONF_REG:
238 case DA9052_LED2_CONF_REG:
239 case DA9052_LED3_CONF_REG:
240 case DA9052_LED1CONT_REG:
241 case DA9052_LED2CONT_REG:
242 case DA9052_LED3CONT_REG:
243 case DA9052_LED_CONT_4_REG:
244 case DA9052_LED_CONT_5_REG:
245 case DA9052_ADC_MAN_REG:
246 case DA9052_ADC_CONT_REG:
247 case DA9052_ADC_RES_L_REG:
248 case DA9052_ADC_RES_H_REG:
249 case DA9052_VDD_RES_REG:
250 case DA9052_VDD_MON_REG:
251 case DA9052_ICHG_THD_REG:
252 case DA9052_ICHG_END_REG:
253 case DA9052_TBAT_HIGHP_REG:
254 case DA9052_TBAT_HIGHN_REG:
255 case DA9052_TBAT_LOW_REG:
256 case DA9052_T_OFFSET_REG:
257 case DA9052_AUTO4_HIGH_REG:
258 case DA9052_AUTO4_LOW_REG:
259 case DA9052_AUTO5_HIGH_REG:
260 case DA9052_AUTO5_LOW_REG:
261 case DA9052_AUTO6_HIGH_REG:
262 case DA9052_AUTO6_LOW_REG:
263 case DA9052_TSI_CONT_A_REG:
264 case DA9052_TSI_CONT_B_REG:
265 case DA9052_COUNT_S_REG:
266 case DA9052_COUNT_MI_REG:
267 case DA9052_COUNT_H_REG:
268 case DA9052_COUNT_D_REG:
269 case DA9052_COUNT_MO_REG:
270 case DA9052_COUNT_Y_REG:
271 case DA9052_ALARM_MI_REG:
272 case DA9052_ALARM_H_REG:
273 case DA9052_ALARM_D_REG:
274 case DA9052_ALARM_MO_REG:
275 case DA9052_ALARM_Y_REG:
276 case DA9052_PAGE1_CON_REG:
277 return true;
278 default:
279 return false;
280 }
281}
282
283static bool da9052_reg_volatile(struct device *dev, unsigned int reg)
284{
285 switch (reg) {
286 case DA9052_STATUS_A_REG:
287 case DA9052_STATUS_B_REG:
288 case DA9052_STATUS_C_REG:
289 case DA9052_STATUS_D_REG:
290 case DA9052_EVENT_A_REG:
291 case DA9052_EVENT_B_REG:
292 case DA9052_EVENT_C_REG:
293 case DA9052_EVENT_D_REG:
294 case DA9052_FAULTLOG_REG:
295 case DA9052_CHG_TIME_REG:
296 case DA9052_ADC_RES_L_REG:
297 case DA9052_ADC_RES_H_REG:
298 case DA9052_VDD_RES_REG:
299 case DA9052_ICHG_AV_REG:
300 case DA9052_TBAT_RES_REG:
301 case DA9052_ADCIN4_RES_REG:
302 case DA9052_ADCIN5_RES_REG:
303 case DA9052_ADCIN6_RES_REG:
304 case DA9052_TJUNC_RES_REG:
305 case DA9052_TSI_X_MSB_REG:
306 case DA9052_TSI_Y_MSB_REG:
307 case DA9052_TSI_LSB_REG:
308 case DA9052_TSI_Z_MSB_REG:
309 case DA9052_COUNT_S_REG:
310 case DA9052_COUNT_MI_REG:
311 case DA9052_COUNT_H_REG:
312 case DA9052_COUNT_D_REG:
313 case DA9052_COUNT_MO_REG:
314 case DA9052_COUNT_Y_REG:
315 case DA9052_ALARM_MI_REG:
316 return true;
317 default:
318 return false;
319 }
320}
321
322static struct resource da9052_rtc_resource = {
323 .name = "ALM",
324 .start = DA9052_IRQ_ALARM,
325 .end = DA9052_IRQ_ALARM,
326 .flags = IORESOURCE_IRQ,
327};
328
329static struct resource da9052_onkey_resource = {
330 .name = "ONKEY",
331 .start = DA9052_IRQ_NONKEY,
332 .end = DA9052_IRQ_NONKEY,
333 .flags = IORESOURCE_IRQ,
334};
335
336static struct resource da9052_bat_resources[] = {
337 {
338 .name = "BATT TEMP",
339 .start = DA9052_IRQ_TBAT,
340 .end = DA9052_IRQ_TBAT,
341 .flags = IORESOURCE_IRQ,
342 },
343 {
344 .name = "DCIN DET",
345 .start = DA9052_IRQ_DCIN,
346 .end = DA9052_IRQ_DCIN,
347 .flags = IORESOURCE_IRQ,
348 },
349 {
350 .name = "DCIN REM",
351 .start = DA9052_IRQ_DCINREM,
352 .end = DA9052_IRQ_DCINREM,
353 .flags = IORESOURCE_IRQ,
354 },
355 {
356 .name = "VBUS DET",
357 .start = DA9052_IRQ_VBUS,
358 .end = DA9052_IRQ_VBUS,
359 .flags = IORESOURCE_IRQ,
360 },
361 {
362 .name = "VBUS REM",
363 .start = DA9052_IRQ_VBUSREM,
364 .end = DA9052_IRQ_VBUSREM,
365 .flags = IORESOURCE_IRQ,
366 },
367 {
368 .name = "CHG END",
369 .start = DA9052_IRQ_CHGEND,
370 .end = DA9052_IRQ_CHGEND,
371 .flags = IORESOURCE_IRQ,
372 },
373};
374
375static struct resource da9052_tsi_resources[] = {
376 {
377 .name = "PENDWN",
378 .start = DA9052_IRQ_PENDOWN,
379 .end = DA9052_IRQ_PENDOWN,
380 .flags = IORESOURCE_IRQ,
381 },
382 {
383 .name = "TSIRDY",
384 .start = DA9052_IRQ_TSIREADY,
385 .end = DA9052_IRQ_TSIREADY,
386 .flags = IORESOURCE_IRQ,
387 },
388};
389
390static struct mfd_cell __devinitdata da9052_subdev_info[] = {
391 {
392 .name = "da9052-regulator",
393 .id = 1,
394 },
395 {
396 .name = "da9052-regulator",
397 .id = 2,
398 },
399 {
400 .name = "da9052-regulator",
401 .id = 3,
402 },
403 {
404 .name = "da9052-regulator",
405 .id = 4,
406 },
407 {
408 .name = "da9052-regulator",
409 .id = 5,
410 },
411 {
412 .name = "da9052-regulator",
413 .id = 6,
414 },
415 {
416 .name = "da9052-regulator",
417 .id = 7,
418 },
419 {
420 .name = "da9052-regulator",
421 .id = 8,
422 },
423 {
424 .name = "da9052-regulator",
425 .id = 9,
426 },
427 {
428 .name = "da9052-regulator",
429 .id = 10,
430 },
431 {
432 .name = "da9052-regulator",
433 .id = 11,
434 },
435 {
436 .name = "da9052-regulator",
437 .id = 12,
438 },
439 {
440 .name = "da9052-regulator",
441 .id = 13,
442 },
443 {
444 .name = "da9052-regulator",
445 .id = 14,
446 },
447 {
448 .name = "da9052-onkey",
449 .resources = &da9052_onkey_resource,
450 .num_resources = 1,
451 },
452 {
453 .name = "da9052-rtc",
454 .resources = &da9052_rtc_resource,
455 .num_resources = 1,
456 },
457 {
458 .name = "da9052-gpio",
459 },
460 {
461 .name = "da9052-hwmon",
462 },
463 {
464 .name = "da9052-leds",
465 },
466 {
467 .name = "da9052-wled1",
468 },
469 {
470 .name = "da9052-wled2",
471 },
472 {
473 .name = "da9052-wled3",
474 },
475 {
476 .name = "da9052-tsi",
477 .resources = da9052_tsi_resources,
478 .num_resources = ARRAY_SIZE(da9052_tsi_resources),
479 },
480 {
481 .name = "da9052-bat",
482 .resources = da9052_bat_resources,
483 .num_resources = ARRAY_SIZE(da9052_bat_resources),
484 },
485 {
486 .name = "da9052-watchdog",
487 },
488};
489
490static struct regmap_irq da9052_irqs[] = {
491 [DA9052_IRQ_DCIN] = {
492 .reg_offset = 0,
493 .mask = DA9052_IRQ_MASK_POS_1,
494 },
495 [DA9052_IRQ_VBUS] = {
496 .reg_offset = 0,
497 .mask = DA9052_IRQ_MASK_POS_2,
498 },
499 [DA9052_IRQ_DCINREM] = {
500 .reg_offset = 0,
501 .mask = DA9052_IRQ_MASK_POS_3,
502 },
503 [DA9052_IRQ_VBUSREM] = {
504 .reg_offset = 0,
505 .mask = DA9052_IRQ_MASK_POS_4,
506 },
507 [DA9052_IRQ_VDDLOW] = {
508 .reg_offset = 0,
509 .mask = DA9052_IRQ_MASK_POS_5,
510 },
511 [DA9052_IRQ_ALARM] = {
512 .reg_offset = 0,
513 .mask = DA9052_IRQ_MASK_POS_6,
514 },
515 [DA9052_IRQ_SEQRDY] = {
516 .reg_offset = 0,
517 .mask = DA9052_IRQ_MASK_POS_7,
518 },
519 [DA9052_IRQ_COMP1V2] = {
520 .reg_offset = 0,
521 .mask = DA9052_IRQ_MASK_POS_8,
522 },
523 [DA9052_IRQ_NONKEY] = {
524 .reg_offset = 1,
525 .mask = DA9052_IRQ_MASK_POS_1,
526 },
527 [DA9052_IRQ_IDFLOAT] = {
528 .reg_offset = 1,
529 .mask = DA9052_IRQ_MASK_POS_2,
530 },
531 [DA9052_IRQ_IDGND] = {
532 .reg_offset = 1,
533 .mask = DA9052_IRQ_MASK_POS_3,
534 },
535 [DA9052_IRQ_CHGEND] = {
536 .reg_offset = 1,
537 .mask = DA9052_IRQ_MASK_POS_4,
538 },
539 [DA9052_IRQ_TBAT] = {
540 .reg_offset = 1,
541 .mask = DA9052_IRQ_MASK_POS_5,
542 },
543 [DA9052_IRQ_ADC_EOM] = {
544 .reg_offset = 1,
545 .mask = DA9052_IRQ_MASK_POS_6,
546 },
547 [DA9052_IRQ_PENDOWN] = {
548 .reg_offset = 1,
549 .mask = DA9052_IRQ_MASK_POS_7,
550 },
551 [DA9052_IRQ_TSIREADY] = {
552 .reg_offset = 1,
553 .mask = DA9052_IRQ_MASK_POS_8,
554 },
555 [DA9052_IRQ_GPI0] = {
556 .reg_offset = 2,
557 .mask = DA9052_IRQ_MASK_POS_1,
558 },
559 [DA9052_IRQ_GPI1] = {
560 .reg_offset = 2,
561 .mask = DA9052_IRQ_MASK_POS_2,
562 },
563 [DA9052_IRQ_GPI2] = {
564 .reg_offset = 2,
565 .mask = DA9052_IRQ_MASK_POS_3,
566 },
567 [DA9052_IRQ_GPI3] = {
568 .reg_offset = 2,
569 .mask = DA9052_IRQ_MASK_POS_4,
570 },
571 [DA9052_IRQ_GPI4] = {
572 .reg_offset = 2,
573 .mask = DA9052_IRQ_MASK_POS_5,
574 },
575 [DA9052_IRQ_GPI5] = {
576 .reg_offset = 2,
577 .mask = DA9052_IRQ_MASK_POS_6,
578 },
579 [DA9052_IRQ_GPI6] = {
580 .reg_offset = 2,
581 .mask = DA9052_IRQ_MASK_POS_7,
582 },
583 [DA9052_IRQ_GPI7] = {
584 .reg_offset = 2,
585 .mask = DA9052_IRQ_MASK_POS_8,
586 },
587 [DA9052_IRQ_GPI8] = {
588 .reg_offset = 3,
589 .mask = DA9052_IRQ_MASK_POS_1,
590 },
591 [DA9052_IRQ_GPI9] = {
592 .reg_offset = 3,
593 .mask = DA9052_IRQ_MASK_POS_2,
594 },
595 [DA9052_IRQ_GPI10] = {
596 .reg_offset = 3,
597 .mask = DA9052_IRQ_MASK_POS_3,
598 },
599 [DA9052_IRQ_GPI11] = {
600 .reg_offset = 3,
601 .mask = DA9052_IRQ_MASK_POS_4,
602 },
603 [DA9052_IRQ_GPI12] = {
604 .reg_offset = 3,
605 .mask = DA9052_IRQ_MASK_POS_5,
606 },
607 [DA9052_IRQ_GPI13] = {
608 .reg_offset = 3,
609 .mask = DA9052_IRQ_MASK_POS_6,
610 },
611 [DA9052_IRQ_GPI14] = {
612 .reg_offset = 3,
613 .mask = DA9052_IRQ_MASK_POS_7,
614 },
615 [DA9052_IRQ_GPI15] = {
616 .reg_offset = 3,
617 .mask = DA9052_IRQ_MASK_POS_8,
618 },
619};
620
621static struct regmap_irq_chip da9052_regmap_irq_chip = {
622 .name = "da9052_irq",
623 .status_base = DA9052_EVENT_A_REG,
624 .mask_base = DA9052_IRQ_MASK_A_REG,
625 .ack_base = DA9052_EVENT_A_REG,
626 .num_regs = DA9052_NUM_IRQ_REGS,
627 .irqs = da9052_irqs,
628 .num_irqs = ARRAY_SIZE(da9052_irqs),
629};
630
631struct regmap_config da9052_regmap_config = {
632 .reg_bits = 8,
633 .val_bits = 8,
634
635 .cache_type = REGCACHE_RBTREE,
636
637 .max_register = DA9052_PAGE1_CON_REG,
638 .readable_reg = da9052_reg_readable,
639 .writeable_reg = da9052_reg_writeable,
640 .volatile_reg = da9052_reg_volatile,
641};
642EXPORT_SYMBOL_GPL(da9052_regmap_config);
643
644int __devinit da9052_device_init(struct da9052 *da9052, u8 chip_id)
645{
646 struct da9052_pdata *pdata = da9052->dev->platform_data;
647 struct irq_desc *desc;
648 int ret;
649
650 mutex_init(&da9052->io_lock);
651
652 if (pdata && pdata->init != NULL)
653 pdata->init(da9052);
654
655 da9052->chip_id = chip_id;
656
657 if (!pdata || !pdata->irq_base)
658 da9052->irq_base = -1;
659 else
660 da9052->irq_base = pdata->irq_base;
661
662 ret = regmap_add_irq_chip(da9052->regmap, da9052->chip_irq,
663 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
664 da9052->irq_base, &da9052_regmap_irq_chip,
665 NULL);
666 if (ret < 0)
667 goto regmap_err;
668
669 desc = irq_to_desc(da9052->chip_irq);
670 da9052->irq_base = regmap_irq_chip_get_base(desc->action->dev_id);
671
672 ret = mfd_add_devices(da9052->dev, -1, da9052_subdev_info,
673 ARRAY_SIZE(da9052_subdev_info), NULL, 0);
674 if (ret)
675 goto err;
676
677 return 0;
678
679err:
680 mfd_remove_devices(da9052->dev);
681regmap_err:
682 return ret;
683}
684
685void da9052_device_exit(struct da9052 *da9052)
686{
687 regmap_del_irq_chip(da9052->chip_irq,
688 irq_get_irq_data(da9052->irq_base)->chip_data);
689 mfd_remove_devices(da9052->dev);
690}
691
692MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
693MODULE_DESCRIPTION("DA9052 MFD Core");
694MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/da9052-i2c.c b/drivers/mfd/da9052-i2c.c
new file mode 100644
index 000000000000..44b97c70a61f
--- /dev/null
+++ b/drivers/mfd/da9052-i2c.c
@@ -0,0 +1,140 @@
1/*
2 * I2C access for DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15#include <linux/device.h>
16#include <linux/module.h>
17#include <linux/input.h>
18#include <linux/mfd/core.h>
19#include <linux/i2c.h>
20#include <linux/err.h>
21
22#include <linux/mfd/da9052/da9052.h>
23#include <linux/mfd/da9052/reg.h>
24
25static int da9052_i2c_enable_multiwrite(struct da9052 *da9052)
26{
27 int reg_val, ret;
28
29 ret = regmap_read(da9052->regmap, DA9052_CONTROL_B_REG, &reg_val);
30 if (ret < 0)
31 return ret;
32
33 if (reg_val & DA9052_CONTROL_B_WRITEMODE) {
34 reg_val &= ~DA9052_CONTROL_B_WRITEMODE;
35 ret = regmap_write(da9052->regmap, DA9052_CONTROL_B_REG,
36 reg_val);
37 if (ret < 0)
38 return ret;
39 }
40
41 return 0;
42}
43
44static int __devinit da9052_i2c_probe(struct i2c_client *client,
45 const struct i2c_device_id *id)
46{
47 struct da9052 *da9052;
48 int ret;
49
50 da9052 = kzalloc(sizeof(struct da9052), GFP_KERNEL);
51 if (!da9052)
52 return -ENOMEM;
53
54 if (!i2c_check_functionality(client->adapter,
55 I2C_FUNC_SMBUS_BYTE_DATA)) {
56 dev_info(&client->dev, "Error in %s:i2c_check_functionality\n",
57 __func__);
58 ret = -ENODEV;
59 goto err;
60 }
61
62 da9052->dev = &client->dev;
63 da9052->chip_irq = client->irq;
64
65 i2c_set_clientdata(client, da9052);
66
67 da9052->regmap = regmap_init_i2c(client, &da9052_regmap_config);
68 if (IS_ERR(da9052->regmap)) {
69 ret = PTR_ERR(da9052->regmap);
70 dev_err(&client->dev, "Failed to allocate register map: %d\n",
71 ret);
72 goto err;
73 }
74
75 ret = da9052_i2c_enable_multiwrite(da9052);
76 if (ret < 0)
77 goto err;
78
79 ret = da9052_device_init(da9052, id->driver_data);
80 if (ret != 0)
81 goto err;
82
83 return 0;
84
85err:
86 kfree(da9052);
87 return ret;
88}
89
90static int da9052_i2c_remove(struct i2c_client *client)
91{
92 struct da9052 *da9052 = i2c_get_clientdata(client);
93
94 da9052_device_exit(da9052);
95 kfree(da9052);
96
97 return 0;
98}
99
100static struct i2c_device_id da9052_i2c_id[] = {
101 {"da9052", DA9052},
102 {"da9053-aa", DA9053_AA},
103 {"da9053-ba", DA9053_BA},
104 {"da9053-bb", DA9053_BB},
105 {}
106};
107
108static struct i2c_driver da9052_i2c_driver = {
109 .probe = da9052_i2c_probe,
110 .remove = da9052_i2c_remove,
111 .id_table = da9052_i2c_id,
112 .driver = {
113 .name = "da9052",
114 .owner = THIS_MODULE,
115 },
116};
117
118static int __init da9052_i2c_init(void)
119{
120 int ret;
121
122 ret = i2c_add_driver(&da9052_i2c_driver);
123 if (ret != 0) {
124 pr_err("DA9052 I2C registration failed %d\n", ret);
125 return ret;
126 }
127
128 return 0;
129}
130subsys_initcall(da9052_i2c_init);
131
132static void __exit da9052_i2c_exit(void)
133{
134 i2c_del_driver(&da9052_i2c_driver);
135}
136module_exit(da9052_i2c_exit);
137
138MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
139MODULE_DESCRIPTION("I2C driver for Dialog DA9052 PMIC");
140MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/da9052-spi.c b/drivers/mfd/da9052-spi.c
new file mode 100644
index 000000000000..cdbc7cad326f
--- /dev/null
+++ b/drivers/mfd/da9052-spi.c
@@ -0,0 +1,115 @@
1/*
2 * SPI access for Dialog DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15#include <linux/device.h>
16#include <linux/module.h>
17#include <linux/input.h>
18#include <linux/mfd/core.h>
19#include <linux/spi/spi.h>
20#include <linux/err.h>
21
22#include <linux/mfd/da9052/da9052.h>
23
24static int da9052_spi_probe(struct spi_device *spi)
25{
26 int ret;
27 const struct spi_device_id *id = spi_get_device_id(spi);
28 struct da9052 *da9052 = kzalloc(sizeof(struct da9052), GFP_KERNEL);
29
30 if (!da9052)
31 return -ENOMEM;
32
33 spi->mode = SPI_MODE_0 | SPI_CPOL;
34 spi->bits_per_word = 8;
35 spi_setup(spi);
36
37 da9052->dev = &spi->dev;
38 da9052->chip_irq = spi->irq;
39
40 dev_set_drvdata(&spi->dev, da9052);
41
42 da9052_regmap_config.read_flag_mask = 1;
43 da9052_regmap_config.write_flag_mask = 0;
44
45 da9052->regmap = regmap_init_spi(spi, &da9052_regmap_config);
46 if (IS_ERR(da9052->regmap)) {
47 ret = PTR_ERR(da9052->regmap);
48 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
49 ret);
50 goto err;
51 }
52
53 ret = da9052_device_init(da9052, id->driver_data);
54 if (ret != 0)
55 goto err;
56
57 return 0;
58
59err:
60 kfree(da9052);
61 return ret;
62}
63
64static int da9052_spi_remove(struct spi_device *spi)
65{
66 struct da9052 *da9052 = dev_get_drvdata(&spi->dev);
67
68 da9052_device_exit(da9052);
69 kfree(da9052);
70
71 return 0;
72}
73
74static struct spi_device_id da9052_spi_id[] = {
75 {"da9052", DA9052},
76 {"da9053-aa", DA9053_AA},
77 {"da9053-ba", DA9053_BA},
78 {"da9053-bb", DA9053_BB},
79 {}
80};
81
82static struct spi_driver da9052_spi_driver = {
83 .probe = da9052_spi_probe,
84 .remove = __devexit_p(da9052_spi_remove),
85 .id_table = da9052_spi_id,
86 .driver = {
87 .name = "da9052",
88 .bus = &spi_bus_type,
89 .owner = THIS_MODULE,
90 },
91};
92
93static int __init da9052_spi_init(void)
94{
95 int ret;
96
97 ret = spi_register_driver(&da9052_spi_driver);
98 if (ret != 0) {
99 pr_err("Failed to register DA9052 SPI driver, %d\n", ret);
100 return ret;
101 }
102
103 return 0;
104}
105subsys_initcall(da9052_spi_init);
106
107static void __exit da9052_spi_exit(void)
108{
109 spi_unregister_driver(&da9052_spi_driver);
110}
111module_exit(da9052_spi_exit);
112
113MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
114MODULE_DESCRIPTION("SPI driver for Dialog DA9052 PMIC");
115MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
new file mode 100644
index 000000000000..5702d1be13b4
--- /dev/null
+++ b/include/linux/mfd/da9052/da9052.h
@@ -0,0 +1,131 @@
1/*
2 * da9052 declarations for DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#ifndef __MFD_DA9052_DA9052_H
25#define __MFD_DA9052_DA9052_H
26
27#include <linux/interrupt.h>
28#include <linux/regmap.h>
29#include <linux/slab.h>
30#include <linux/completion.h>
31#include <linux/list.h>
32#include <linux/mfd/core.h>
33
34#include <linux/mfd/da9052/reg.h>
35
36#define DA9052_IRQ_DCIN 0
37#define DA9052_IRQ_VBUS 1
38#define DA9052_IRQ_DCINREM 2
39#define DA9052_IRQ_VBUSREM 3
40#define DA9052_IRQ_VDDLOW 4
41#define DA9052_IRQ_ALARM 5
42#define DA9052_IRQ_SEQRDY 6
43#define DA9052_IRQ_COMP1V2 7
44#define DA9052_IRQ_NONKEY 8
45#define DA9052_IRQ_IDFLOAT 9
46#define DA9052_IRQ_IDGND 10
47#define DA9052_IRQ_CHGEND 11
48#define DA9052_IRQ_TBAT 12
49#define DA9052_IRQ_ADC_EOM 13
50#define DA9052_IRQ_PENDOWN 14
51#define DA9052_IRQ_TSIREADY 15
52#define DA9052_IRQ_GPI0 16
53#define DA9052_IRQ_GPI1 17
54#define DA9052_IRQ_GPI2 18
55#define DA9052_IRQ_GPI3 19
56#define DA9052_IRQ_GPI4 20
57#define DA9052_IRQ_GPI5 21
58#define DA9052_IRQ_GPI6 22
59#define DA9052_IRQ_GPI7 23
60#define DA9052_IRQ_GPI8 24
61#define DA9052_IRQ_GPI9 25
62#define DA9052_IRQ_GPI10 26
63#define DA9052_IRQ_GPI11 27
64#define DA9052_IRQ_GPI12 28
65#define DA9052_IRQ_GPI13 29
66#define DA9052_IRQ_GPI14 30
67#define DA9052_IRQ_GPI15 31
68
69enum da9052_chip_id {
70 DA9052,
71 DA9053_AA,
72 DA9053_BA,
73 DA9053_BB,
74};
75
76struct da9052_pdata;
77
78struct da9052 {
79 struct mutex io_lock;
80
81 struct device *dev;
82 struct regmap *regmap;
83
84 int irq_base;
85 u8 chip_id;
86
87 int chip_irq;
88};
89
90/* Device I/O API */
91static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg)
92{
93 int val, ret;
94
95 ret = regmap_read(da9052->regmap, reg, &val);
96 if (ret < 0)
97 return ret;
98 return val;
99}
100
101static inline int da9052_reg_write(struct da9052 *da9052, unsigned char reg,
102 unsigned char val)
103{
104 return regmap_write(da9052->regmap, reg, val);
105}
106
107static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg,
108 unsigned reg_cnt, unsigned char *val)
109{
110 return regmap_bulk_read(da9052->regmap, reg, val, reg_cnt);
111}
112
113static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,
114 unsigned reg_cnt, unsigned char *val)
115{
116 return regmap_raw_write(da9052->regmap, reg, val, reg_cnt);
117}
118
119static inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg,
120 unsigned char bit_mask,
121 unsigned char reg_val)
122{
123 return regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val);
124}
125
126int da9052_device_init(struct da9052 *da9052, u8 chip_id);
127void da9052_device_exit(struct da9052 *da9052);
128
129extern struct regmap_config da9052_regmap_config;
130
131#endif /* __MFD_DA9052_DA9052_H */
diff --git a/include/linux/mfd/da9052/pdata.h b/include/linux/mfd/da9052/pdata.h
new file mode 100644
index 000000000000..62c5c3c2992e
--- /dev/null
+++ b/include/linux/mfd/da9052/pdata.h
@@ -0,0 +1,40 @@
1/*
2 * Platform data declarations for DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#ifndef __MFD_DA9052_PDATA_H__
25#define __MFD_DA9052_PDATA_H__
26
27#define DA9052_MAX_REGULATORS 14
28
29struct da9052;
30
31struct da9052_pdata {
32 struct led_platform_data *pled;
33 int (*init) (struct da9052 *da9052);
34 int irq_base;
35 int gpio_base;
36 int use_for_apm;
37 struct regulator_init_data *regulators[DA9052_MAX_REGULATORS];
38};
39
40#endif
diff --git a/include/linux/mfd/da9052/reg.h b/include/linux/mfd/da9052/reg.h
new file mode 100644
index 000000000000..b97f7309d7f6
--- /dev/null
+++ b/include/linux/mfd/da9052/reg.h
@@ -0,0 +1,749 @@
1/*
2 * Register declarations for DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#ifndef __LINUX_MFD_DA9052_REG_H
25#define __LINUX_MFD_DA9052_REG_H
26
27/* PAGE REGISTERS */
28#define DA9052_PAGE0_CON_REG 0
29#define DA9052_PAGE1_CON_REG 128
30
31/* STATUS REGISTERS */
32#define DA9052_STATUS_A_REG 1
33#define DA9052_STATUS_B_REG 2
34#define DA9052_STATUS_C_REG 3
35#define DA9052_STATUS_D_REG 4
36
37/* EVENT REGISTERS */
38#define DA9052_EVENT_A_REG 5
39#define DA9052_EVENT_B_REG 6
40#define DA9052_EVENT_C_REG 7
41#define DA9052_EVENT_D_REG 8
42#define DA9052_FAULTLOG_REG 9
43
44/* IRQ REGISTERS */
45#define DA9052_IRQ_MASK_A_REG 10
46#define DA9052_IRQ_MASK_B_REG 11
47#define DA9052_IRQ_MASK_C_REG 12
48#define DA9052_IRQ_MASK_D_REG 13
49
50/* CONTROL REGISTERS */
51#define DA9052_CONTROL_A_REG 14
52#define DA9052_CONTROL_B_REG 15
53#define DA9052_CONTROL_C_REG 16
54#define DA9052_CONTROL_D_REG 17
55
56#define DA9052_PDDIS_REG 18
57#define DA9052_INTERFACE_REG 19
58#define DA9052_RESET_REG 20
59
60/* GPIO REGISTERS */
61#define DA9052_GPIO_0_1_REG 21
62#define DA9052_GPIO_2_3_REG 22
63#define DA9052_GPIO_4_5_REG 23
64#define DA9052_GPIO_6_7_REG 24
65#define DA9052_GPIO_14_15_REG 28
66
67/* POWER SEQUENCER CONTROL REGISTERS */
68#define DA9052_ID_0_1_REG 29
69#define DA9052_ID_2_3_REG 30
70#define DA9052_ID_4_5_REG 31
71#define DA9052_ID_6_7_REG 32
72#define DA9052_ID_8_9_REG 33
73#define DA9052_ID_10_11_REG 34
74#define DA9052_ID_12_13_REG 35
75#define DA9052_ID_14_15_REG 36
76#define DA9052_ID_16_17_REG 37
77#define DA9052_ID_18_19_REG 38
78#define DA9052_ID_20_21_REG 39
79#define DA9052_SEQ_STATUS_REG 40
80#define DA9052_SEQ_A_REG 41
81#define DA9052_SEQ_B_REG 42
82#define DA9052_SEQ_TIMER_REG 43
83
84/* LDO AND BUCK REGISTERS */
85#define DA9052_BUCKA_REG 44
86#define DA9052_BUCKB_REG 45
87#define DA9052_BUCKCORE_REG 46
88#define DA9052_BUCKPRO_REG 47
89#define DA9052_BUCKMEM_REG 48
90#define DA9052_BUCKPERI_REG 49
91#define DA9052_LDO1_REG 50
92#define DA9052_LDO2_REG 51
93#define DA9052_LDO3_REG 52
94#define DA9052_LDO4_REG 53
95#define DA9052_LDO5_REG 54
96#define DA9052_LDO6_REG 55
97#define DA9052_LDO7_REG 56
98#define DA9052_LDO8_REG 57
99#define DA9052_LDO9_REG 58
100#define DA9052_LDO10_REG 59
101#define DA9052_SUPPLY_REG 60
102#define DA9052_PULLDOWN_REG 61
103#define DA9052_CHGBUCK_REG 62
104#define DA9052_WAITCONT_REG 63
105#define DA9052_ISET_REG 64
106#define DA9052_BATCHG_REG 65
107
108/* BATTERY CONTROL REGISTRS */
109#define DA9052_CHG_CONT_REG 66
110#define DA9052_INPUT_CONT_REG 67
111#define DA9052_CHG_TIME_REG 68
112#define DA9052_BBAT_CONT_REG 69
113
114/* LED CONTROL REGISTERS */
115#define DA9052_BOOST_REG 70
116#define DA9052_LED_CONT_REG 71
117#define DA9052_LEDMIN123_REG 72
118#define DA9052_LED1_CONF_REG 73
119#define DA9052_LED2_CONF_REG 74
120#define DA9052_LED3_CONF_REG 75
121#define DA9052_LED1CONT_REG 76
122#define DA9052_LED2CONT_REG 77
123#define DA9052_LED3CONT_REG 78
124#define DA9052_LED_CONT_4_REG 79
125#define DA9052_LED_CONT_5_REG 80
126
127/* ADC CONTROL REGISTERS */
128#define DA9052_ADC_MAN_REG 81
129#define DA9052_ADC_CONT_REG 82
130#define DA9052_ADC_RES_L_REG 83
131#define DA9052_ADC_RES_H_REG 84
132#define DA9052_VDD_RES_REG 85
133#define DA9052_VDD_MON_REG 86
134
135#define DA9052_ICHG_AV_REG 87
136#define DA9052_ICHG_THD_REG 88
137#define DA9052_ICHG_END_REG 89
138#define DA9052_TBAT_RES_REG 90
139#define DA9052_TBAT_HIGHP_REG 91
140#define DA9052_TBAT_HIGHN_REG 92
141#define DA9052_TBAT_LOW_REG 93
142#define DA9052_T_OFFSET_REG 94
143
144#define DA9052_ADCIN4_RES_REG 95
145#define DA9052_AUTO4_HIGH_REG 96
146#define DA9052_AUTO4_LOW_REG 97
147#define DA9052_ADCIN5_RES_REG 98
148#define DA9052_AUTO5_HIGH_REG 99
149#define DA9052_AUTO5_LOW_REG 100
150#define DA9052_ADCIN6_RES_REG 101
151#define DA9052_AUTO6_HIGH_REG 102
152#define DA9052_AUTO6_LOW_REG 103
153
154#define DA9052_TJUNC_RES_REG 104
155
156/* TSI CONTROL REGISTERS */
157#define DA9052_TSI_CONT_A_REG 105
158#define DA9052_TSI_CONT_B_REG 106
159#define DA9052_TSI_X_MSB_REG 107
160#define DA9052_TSI_Y_MSB_REG 108
161#define DA9052_TSI_LSB_REG 109
162#define DA9052_TSI_Z_MSB_REG 110
163
164/* RTC COUNT REGISTERS */
165#define DA9052_COUNT_S_REG 111
166#define DA9052_COUNT_MI_REG 112
167#define DA9052_COUNT_H_REG 113
168#define DA9052_COUNT_D_REG 114
169#define DA9052_COUNT_MO_REG 115
170#define DA9052_COUNT_Y_REG 116
171
172/* RTC CONTROL REGISTERS */
173#define DA9052_ALARM_MI_REG 117
174#define DA9052_ALARM_H_REG 118
175#define DA9052_ALARM_D_REG 119
176#define DA9052_ALARM_MO_REG 120
177#define DA9052_ALARM_Y_REG 121
178#define DA9052_SECOND_A_REG 122
179#define DA9052_SECOND_B_REG 123
180#define DA9052_SECOND_C_REG 124
181#define DA9052_SECOND_D_REG 125
182
183/* PAGE CONFIGURATION BIT */
184#define DA9052_PAGE_CONF 0X80
185
186/* STATUS REGISTER A BITS */
187#define DA9052_STATUSA_VDATDET 0X80
188#define DA9052_STATUSA_VBUSSEL 0X40
189#define DA9052_STATUSA_DCINSEL 0X20
190#define DA9052_STATUSA_VBUSDET 0X10
191#define DA9052_STATUSA_DCINDET 0X08
192#define DA9052_STATUSA_IDGND 0X04
193#define DA9052_STATUSA_IDFLOAT 0X02
194#define DA9052_STATUSA_NONKEY 0X01
195
196/* STATUS REGISTER B BITS */
197#define DA9052_STATUSB_COMPDET 0X80
198#define DA9052_STATUSB_SEQUENCING 0X40
199#define DA9052_STATUSB_GPFB2 0X20
200#define DA9052_STATUSB_CHGTO 0X10
201#define DA9052_STATUSB_CHGEND 0X08
202#define DA9052_STATUSB_CHGLIM 0X04
203#define DA9052_STATUSB_CHGPRE 0X02
204#define DA9052_STATUSB_CHGATT 0X01
205
206/* STATUS REGISTER C BITS */
207#define DA9052_STATUSC_GPI7 0X80
208#define DA9052_STATUSC_GPI6 0X40
209#define DA9052_STATUSC_GPI5 0X20
210#define DA9052_STATUSC_GPI4 0X10
211#define DA9052_STATUSC_GPI3 0X08
212#define DA9052_STATUSC_GPI2 0X04
213#define DA9052_STATUSC_GPI1 0X02
214#define DA9052_STATUSC_GPI0 0X01
215
216/* STATUS REGISTER D BITS */
217#define DA9052_STATUSD_GPI15 0X80
218#define DA9052_STATUSD_GPI14 0X40
219#define DA9052_STATUSD_GPI13 0X20
220#define DA9052_STATUSD_GPI12 0X10
221#define DA9052_STATUSD_GPI11 0X08
222#define DA9052_STATUSD_GPI10 0X04
223#define DA9052_STATUSD_GPI9 0X02
224#define DA9052_STATUSD_GPI8 0X01
225
226/* EVENT REGISTER A BITS */
227#define DA9052_EVENTA_ECOMP1V2 0X80
228#define DA9052_EVENTA_ESEQRDY 0X40
229#define DA9052_EVENTA_EALRAM 0X20
230#define DA9052_EVENTA_EVDDLOW 0X10
231#define DA9052_EVENTA_EVBUSREM 0X08
232#define DA9052_EVENTA_EDCINREM 0X04
233#define DA9052_EVENTA_EVBUSDET 0X02
234#define DA9052_EVENTA_EDCINDET 0X01
235
236/* EVENT REGISTER B BITS */
237#define DA9052_EVENTB_ETSIREADY 0X80
238#define DA9052_EVENTB_EPENDOWN 0X40
239#define DA9052_EVENTB_EADCEOM 0X20
240#define DA9052_EVENTB_ETBAT 0X10
241#define DA9052_EVENTB_ECHGEND 0X08
242#define DA9052_EVENTB_EIDGND 0X04
243#define DA9052_EVENTB_EIDFLOAT 0X02
244#define DA9052_EVENTB_ENONKEY 0X01
245
246/* EVENT REGISTER C BITS */
247#define DA9052_EVENTC_EGPI7 0X80
248#define DA9052_EVENTC_EGPI6 0X40
249#define DA9052_EVENTC_EGPI5 0X20
250#define DA9052_EVENTC_EGPI4 0X10
251#define DA9052_EVENTC_EGPI3 0X08
252#define DA9052_EVENTC_EGPI2 0X04
253#define DA9052_EVENTC_EGPI1 0X02
254#define DA9052_EVENTC_EGPI0 0X01
255
256/* EVENT REGISTER D BITS */
257#define DA9052_EVENTD_EGPI15 0X80
258#define DA9052_EVENTD_EGPI14 0X40
259#define DA9052_EVENTD_EGPI13 0X20
260#define DA9052_EVENTD_EGPI12 0X10
261#define DA9052_EVENTD_EGPI11 0X08
262#define DA9052_EVENTD_EGPI10 0X04
263#define DA9052_EVENTD_EGPI9 0X02
264#define DA9052_EVENTD_EGPI8 0X01
265
266/* IRQ MASK REGISTERS BITS */
267#define DA9052_M_NONKEY 0X0100
268
269/* TSI EVENT REGISTERS BITS */
270#define DA9052_E_PEN_DOWN 0X4000
271#define DA9052_E_TSI_READY 0X8000
272
273/* FAULT LOG REGISTER BITS */
274#define DA9052_FAULTLOG_WAITSET 0X80
275#define DA9052_FAULTLOG_NSDSET 0X40
276#define DA9052_FAULTLOG_KEYSHUT 0X20
277#define DA9052_FAULTLOG_TEMPOVER 0X08
278#define DA9052_FAULTLOG_VDDSTART 0X04
279#define DA9052_FAULTLOG_VDDFAULT 0X02
280#define DA9052_FAULTLOG_TWDERROR 0X01
281
282/* CONTROL REGISTER A BITS */
283#define DA9052_CONTROLA_GPIV 0X80
284#define DA9052_CONTROLA_PMOTYPE 0X20
285#define DA9052_CONTROLA_PMOV 0X10
286#define DA9052_CONTROLA_PMIV 0X08
287#define DA9052_CONTROLA_PMIFV 0X08
288#define DA9052_CONTROLA_PWR1EN 0X04
289#define DA9052_CONTROLA_PWREN 0X02
290#define DA9052_CONTROLA_SYSEN 0X01
291
292/* CONTROL REGISTER B BITS */
293#define DA9052_CONTROLB_SHUTDOWN 0X80
294#define DA9052_CONTROLB_DEEPSLEEP 0X40
295#define DA9052_CONTROL_B_WRITEMODE 0X20
296#define DA9052_CONTROLB_BBATEN 0X10
297#define DA9052_CONTROLB_OTPREADEN 0X08
298#define DA9052_CONTROLB_AUTOBOOT 0X04
299#define DA9052_CONTROLB_ACTDIODE 0X02
300#define DA9052_CONTROLB_BUCKMERGE 0X01
301
302/* CONTROL REGISTER C BITS */
303#define DA9052_CONTROLC_BLINKDUR 0X80
304#define DA9052_CONTROLC_BLINKFRQ 0X60
305#define DA9052_CONTROLC_DEBOUNCING 0X1C
306#define DA9052_CONTROLC_PMFB2PIN 0X02
307#define DA9052_CONTROLC_PMFB1PIN 0X01
308
309/* CONTROL REGISTER D BITS */
310#define DA9052_CONTROLD_WATCHDOG 0X80
311#define DA9052_CONTROLD_ACCDETEN 0X40
312#define DA9052_CONTROLD_GPI1415SD 0X20
313#define DA9052_CONTROLD_NONKEYSD 0X10
314#define DA9052_CONTROLD_KEEPACTEN 0X08
315#define DA9052_CONTROLD_TWDSCALE 0X07
316
317/* POWER DOWN DISABLE REGISTER BITS */
318#define DA9052_PDDIS_PMCONTPD 0X80
319#define DA9052_PDDIS_OUT32KPD 0X40
320#define DA9052_PDDIS_CHGBBATPD 0X20
321#define DA9052_PDDIS_CHGPD 0X10
322#define DA9052_PDDIS_HS2WIREPD 0X08
323#define DA9052_PDDIS_PMIFPD 0X04
324#define DA9052_PDDIS_GPADCPD 0X02
325#define DA9052_PDDIS_GPIOPD 0X01
326
327/* CONTROL REGISTER D BITS */
328#define DA9052_INTERFACE_IFBASEADDR 0XE0
329#define DA9052_INTERFACE_NCSPOL 0X10
330#define DA9052_INTERFACE_RWPOL 0X08
331#define DA9052_INTERFACE_CPHA 0X04
332#define DA9052_INTERFACE_CPOL 0X02
333#define DA9052_INTERFACE_IFTYPE 0X01
334
335/* CONTROL REGISTER D BITS */
336#define DA9052_RESET_RESETEVENT 0XC0
337#define DA9052_RESET_RESETTIMER 0X3F
338
339/* GPIO REGISTERS */
340/* GPIO CONTROL REGISTER BITS */
341#define DA9052_GPIO_EVEN_PORT_PIN 0X03
342#define DA9052_GPIO_EVEN_PORT_TYPE 0X04
343#define DA9052_GPIO_EVEN_PORT_MODE 0X08
344
345#define DA9052_GPIO_ODD_PORT_PIN 0X30
346#define DA9052_GPIO_ODD_PORT_TYPE 0X40
347#define DA9052_GPIO_ODD_PORT_MODE 0X80
348
349/*POWER SEQUENCER REGISTER BITS */
350/* SEQ CONTROL REGISTER BITS FOR ID 0 AND 1 */
351#define DA9052_ID01_LDO1STEP 0XF0
352#define DA9052_ID01_SYSPRE 0X04
353#define DA9052_ID01_DEFSUPPLY 0X02
354#define DA9052_ID01_NRESMODE 0X01
355
356/* SEQ CONTROL REGISTER BITS FOR ID 2 AND 3 */
357#define DA9052_ID23_LDO3STEP 0XF0
358#define DA9052_ID23_LDO2STEP 0X0F
359
360/* SEQ CONTROL REGISTER BITS FOR ID 4 AND 5 */
361#define DA9052_ID45_LDO5STEP 0XF0
362#define DA9052_ID45_LDO4STEP 0X0F
363
364/* SEQ CONTROL REGISTER BITS FOR ID 6 AND 7 */
365#define DA9052_ID67_LDO7STEP 0XF0
366#define DA9052_ID67_LDO6STEP 0X0F
367
368/* SEQ CONTROL REGISTER BITS FOR ID 8 AND 9 */
369#define DA9052_ID89_LDO9STEP 0XF0
370#define DA9052_ID89_LDO8STEP 0X0F
371
372/* SEQ CONTROL REGISTER BITS FOR ID 10 AND 11 */
373#define DA9052_ID1011_PDDISSTEP 0XF0
374#define DA9052_ID1011_LDO10STEP 0X0F
375
376/* SEQ CONTROL REGISTER BITS FOR ID 12 AND 13 */
377#define DA9052_ID1213_VMEMSWSTEP 0XF0
378#define DA9052_ID1213_VPERISWSTEP 0X0F
379
380/* SEQ CONTROL REGISTER BITS FOR ID 14 AND 15 */
381#define DA9052_ID1415_BUCKPROSTEP 0XF0
382#define DA9052_ID1415_BUCKCORESTEP 0X0F
383
384/* SEQ CONTROL REGISTER BITS FOR ID 16 AND 17 */
385#define DA9052_ID1617_BUCKPERISTEP 0XF0
386#define DA9052_ID1617_BUCKMEMSTEP 0X0F
387
388/* SEQ CONTROL REGISTER BITS FOR ID 18 AND 19 */
389#define DA9052_ID1819_GPRISE2STEP 0XF0
390#define DA9052_ID1819_GPRISE1STEP 0X0F
391
392/* SEQ CONTROL REGISTER BITS FOR ID 20 AND 21 */
393#define DA9052_ID2021_GPFALL2STEP 0XF0
394#define DA9052_ID2021_GPFALL1STEP 0X0F
395
396/* POWER SEQ STATUS REGISTER BITS */
397#define DA9052_SEQSTATUS_SEQPOINTER 0XF0
398#define DA9052_SEQSTATUS_WAITSTEP 0X0F
399
400/* POWER SEQ A REGISTER BITS */
401#define DA9052_SEQA_POWEREND 0XF0
402#define DA9052_SEQA_SYSTEMEND 0X0F
403
404/* POWER SEQ B REGISTER BITS */
405#define DA9052_SEQB_PARTDOWN 0XF0
406#define DA9052_SEQB_MAXCOUNT 0X0F
407
408/* POWER SEQ TIMER REGISTER BITS */
409#define DA9052_SEQTIMER_SEQDUMMY 0XF0
410#define DA9052_SEQTIMER_SEQTIME 0X0F
411
412/*POWER SUPPLY CONTROL REGISTER BITS */
413/* BUCK REGISTER A BITS */
414#define DA9052_BUCKA_BPROILIM 0XC0
415#define DA9052_BUCKA_BPROMODE 0X30
416#define DA9052_BUCKA_BCOREILIM 0X0C
417#define DA9052_BUCKA_BCOREMODE 0X03
418
419/* BUCK REGISTER B BITS */
420#define DA9052_BUCKB_BERIILIM 0XC0
421#define DA9052_BUCKB_BPERIMODE 0X30
422#define DA9052_BUCKB_BMEMILIM 0X0C
423#define DA9052_BUCKB_BMEMMODE 0X03
424
425/* BUCKCORE REGISTER BITS */
426#define DA9052_BUCKCORE_BCORECONF 0X80
427#define DA9052_BUCKCORE_BCOREEN 0X40
428#define DA9052_BUCKCORE_VBCORE 0X3F
429
430/* BUCKPRO REGISTER BITS */
431#define DA9052_BUCKPRO_BPROCONF 0X80
432#define DA9052_BUCKPRO_BPROEN 0X40
433#define DA9052_BUCKPRO_VBPRO 0X3F
434
435/* BUCKMEM REGISTER BITS */
436#define DA9052_BUCKMEM_BMEMCONF 0X80
437#define DA9052_BUCKMEM_BMEMEN 0X40
438#define DA9052_BUCKMEM_VBMEM 0X3F
439
440/* BUCKPERI REGISTER BITS */
441#define DA9052_BUCKPERI_BPERICONF 0X80
442#define DA9052_BUCKPERI_BPERIEN 0X40
443#define DA9052_BUCKPERI_BPERIHS 0X20
444#define DA9052_BUCKPERI_VBPERI 0X1F
445
446/* LDO1 REGISTER BITS */
447#define DA9052_LDO1_LDO1CONF 0X80
448#define DA9052_LDO1_LDO1EN 0X40
449#define DA9052_LDO1_VLDO1 0X1F
450
451/* LDO2 REGISTER BITS */
452#define DA9052_LDO2_LDO2CONF 0X80
453#define DA9052_LDO2_LDO2EN 0X40
454#define DA9052_LDO2_VLDO2 0X3F
455
456/* LDO3 REGISTER BITS */
457#define DA9052_LDO3_LDO3CONF 0X80
458#define DA9052_LDO3_LDO3EN 0X40
459#define DA9052_LDO3_VLDO3 0X3F
460
461/* LDO4 REGISTER BITS */
462#define DA9052_LDO4_LDO4CONF 0X80
463#define DA9052_LDO4_LDO4EN 0X40
464#define DA9052_LDO4_VLDO4 0X3F
465
466/* LDO5 REGISTER BITS */
467#define DA9052_LDO5_LDO5CONF 0X80
468#define DA9052_LDO5_LDO5EN 0X40
469#define DA9052_LDO5_VLDO5 0X3F
470
471/* LDO6 REGISTER BITS */
472#define DA9052_LDO6_LDO6CONF 0X80
473#define DA9052_LDO6_LDO6EN 0X40
474#define DA9052_LDO6_VLDO6 0X3F
475
476/* LDO7 REGISTER BITS */
477#define DA9052_LDO7_LDO7CONF 0X80
478#define DA9052_LDO7_LDO7EN 0X40
479#define DA9052_LDO7_VLDO7 0X3F
480
481/* LDO8 REGISTER BITS */
482#define DA9052_LDO8_LDO8CONF 0X80
483#define DA9052_LDO8_LDO8EN 0X40
484#define DA9052_LDO8_VLDO8 0X3F
485
486/* LDO9 REGISTER BITS */
487#define DA9052_LDO9_LDO9CONF 0X80
488#define DA9052_LDO9_LDO9EN 0X40
489#define DA9052_LDO9_VLDO9 0X3F
490
491/* LDO10 REGISTER BITS */
492#define DA9052_LDO10_LDO10CONF 0X80
493#define DA9052_LDO10_LDO10EN 0X40
494#define DA9052_LDO10_VLDO10 0X3F
495
496/* SUPPLY REGISTER BITS */
497#define DA9052_SUPPLY_VLOCK 0X80
498#define DA9052_SUPPLY_VMEMSWEN 0X40
499#define DA9052_SUPPLY_VPERISWEN 0X20
500#define DA9052_SUPPLY_VLDO3GO 0X10
501#define DA9052_SUPPLY_VLDO2GO 0X08
502#define DA9052_SUPPLY_VBMEMGO 0X04
503#define DA9052_SUPPLY_VBPROGO 0X02
504#define DA9052_SUPPLY_VBCOREGO 0X01
505
506/* PULLDOWN REGISTER BITS */
507#define DA9052_PULLDOWN_LDO5PDDIS 0X20
508#define DA9052_PULLDOWN_LDO2PDDIS 0X10
509#define DA9052_PULLDOWN_LDO1PDDIS 0X08
510#define DA9052_PULLDOWN_MEMPDDIS 0X04
511#define DA9052_PULLDOWN_PROPDDIS 0X02
512#define DA9052_PULLDOWN_COREPDDIS 0X01
513
514/* BAT CHARGER REGISTER BITS */
515/* CHARGER BUCK REGISTER BITS */
516#define DA9052_CHGBUCK_CHGTEMP 0X80
517#define DA9052_CHGBUCK_CHGUSBILIM 0X40
518#define DA9052_CHGBUCK_CHGBUCKLP 0X20
519#define DA9052_CHGBUCK_CHGBUCKEN 0X10
520#define DA9052_CHGBUCK_ISETBUCK 0X0F
521
522/* WAIT COUNTER REGISTER BITS */
523#define DA9052_WAITCONT_WAITDIR 0X80
524#define DA9052_WAITCONT_RTCCLOCK 0X40
525#define DA9052_WAITCONT_WAITMODE 0X20
526#define DA9052_WAITCONT_EN32KOUT 0X10
527#define DA9052_WAITCONT_DELAYTIME 0X0F
528
529/* ISET CONTROL REGISTER BITS */
530#define DA9052_ISET_ISETDCIN 0XF0
531#define DA9052_ISET_ISETVBUS 0X0F
532
533/* BATTERY CHARGER CONTROL REGISTER BITS */
534#define DA9052_BATCHG_ICHGPRE 0XC0
535#define DA9052_BATCHG_ICHGBAT 0X3F
536
537/* CHARGER COUNTER REGISTER BITS */
538#define DA9052_CHG_CONT_VCHG_BAT 0XF8
539#define DA9052_CHG_CONT_TCTR 0X07
540
541/* INPUT CONTROL REGISTER BITS */
542#define DA9052_INPUT_CONT_TCTR_MODE 0X80
543#define DA9052_INPUT_CONT_VBUS_SUSP 0X10
544#define DA9052_INPUT_CONT_DCIN_SUSP 0X08
545
546/* CHARGING TIME REGISTER BITS */
547#define DA9052_CHGTIME_CHGTIME 0XFF
548
549/* BACKUP BATTERY CONTROL REGISTER BITS */
550#define DA9052_BBATCONT_BCHARGERISET 0XF0
551#define DA9052_BBATCONT_BCHARGERVSET 0X0F
552
553/* LED REGISTERS BITS */
554/* LED BOOST REGISTER BITS */
555#define DA9052_BOOST_EBFAULT 0X80
556#define DA9052_BOOST_MBFAULT 0X40
557#define DA9052_BOOST_BOOSTFRQ 0X20
558#define DA9052_BOOST_BOOSTILIM 0X10
559#define DA9052_BOOST_LED3INEN 0X08
560#define DA9052_BOOST_LED2INEN 0X04
561#define DA9052_BOOST_LED1INEN 0X02
562#define DA9052_BOOST_BOOSTEN 0X01
563
564/* LED CONTROL REGISTER BITS */
565#define DA9052_LEDCONT_SELLEDMODE 0X80
566#define DA9052_LEDCONT_LED3ICONT 0X40
567#define DA9052_LEDCONT_LED3RAMP 0X20
568#define DA9052_LEDCONT_LED3EN 0X10
569#define DA9052_LEDCONT_LED2RAMP 0X08
570#define DA9052_LEDCONT_LED2EN 0X04
571#define DA9052_LEDCONT_LED1RAMP 0X02
572#define DA9052_LEDCONT_LED1EN 0X01
573
574/* LEDMIN123 REGISTER BIT */
575#define DA9052_LEDMIN123_LEDMINCURRENT 0XFF
576
577/* LED1CONF REGISTER BIT */
578#define DA9052_LED1CONF_LED1CURRENT 0XFF
579
580/* LED2CONF REGISTER BIT */
581#define DA9052_LED2CONF_LED2CURRENT 0XFF
582
583/* LED3CONF REGISTER BIT */
584#define DA9052_LED3CONF_LED3CURRENT 0XFF
585
586/* LED COUNT REGISTER BIT */
587#define DA9052_LED_CONT_DIM 0X80
588
589/* ADC MAN REGISTERS BITS */
590#define DA9052_ADC_MAN_MAN_CONV 0X10
591#define DA9052_ADC_MAN_MUXSEL_VDDOUT 0X00
592#define DA9052_ADC_MAN_MUXSEL_ICH 0X01
593#define DA9052_ADC_MAN_MUXSEL_TBAT 0X02
594#define DA9052_ADC_MAN_MUXSEL_VBAT 0X03
595#define DA9052_ADC_MAN_MUXSEL_AD4 0X04
596#define DA9052_ADC_MAN_MUXSEL_AD5 0X05
597#define DA9052_ADC_MAN_MUXSEL_AD6 0X06
598#define DA9052_ADC_MAN_MUXSEL_VBBAT 0X09
599
600/* ADC CONTROL REGSISTERS BITS */
601#define DA9052_ADCCONT_COMP1V2EN 0X80
602#define DA9052_ADCCONT_ADCMODE 0X40
603#define DA9052_ADCCONT_TBATISRCEN 0X20
604#define DA9052_ADCCONT_AD4ISRCEN 0X10
605#define DA9052_ADCCONT_AUTOAD6EN 0X08
606#define DA9052_ADCCONT_AUTOAD5EN 0X04
607#define DA9052_ADCCONT_AUTOAD4EN 0X02
608#define DA9052_ADCCONT_AUTOVDDEN 0X01
609
610/* ADC 10 BIT MANUAL CONVERSION RESULT LOW REGISTER */
611#define DA9052_ADC_RES_LSB 0X03
612
613/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH REGISTER */
614#define DA9052_ADCRESH_ADCRESMSB 0XFF
615
616/* VDD RES REGSISTER BIT*/
617#define DA9052_VDDRES_VDDOUTRES 0XFF
618
619/* VDD MON REGSISTER BIT */
620#define DA9052_VDDMON_VDDOUTMON 0XFF
621
622/* ICHG_AV REGSISTER BIT */
623#define DA9052_ICHGAV_ICHGAV 0XFF
624
625/* ICHG_THD REGSISTER BIT */
626#define DA9052_ICHGTHD_ICHGTHD 0XFF
627
628/* ICHG_END REGSISTER BIT */
629#define DA9052_ICHGEND_ICHGEND 0XFF
630
631/* TBAT_RES REGSISTER BIT */
632#define DA9052_TBATRES_TBATRES 0XFF
633
634/* TBAT_HIGHP REGSISTER BIT */
635#define DA9052_TBATHIGHP_TBATHIGHP 0XFF
636
637/* TBAT_HIGHN REGSISTER BIT */
638#define DA9052_TBATHIGHN_TBATHIGHN 0XFF
639
640/* TBAT_LOW REGSISTER BIT */
641#define DA9052_TBATLOW_TBATLOW 0XFF
642
643/* T_OFFSET REGSISTER BIT */
644#define DA9052_TOFFSET_TOFFSET 0XFF
645
646/* ADCIN4_RES REGSISTER BIT */
647#define DA9052_ADCIN4RES_ADCIN4RES 0XFF
648
649/* ADCIN4_HIGH REGSISTER BIT */
650#define DA9052_AUTO4HIGH_AUTO4HIGH 0XFF
651
652/* ADCIN4_LOW REGSISTER BIT */
653#define DA9052_AUTO4LOW_AUTO4LOW 0XFF
654
655/* ADCIN5_RES REGSISTER BIT */
656#define DA9052_ADCIN5RES_ADCIN5RES 0XFF
657
658/* ADCIN5_HIGH REGSISTER BIT */
659#define DA9052_AUTO5HIGH_AUTOHIGH 0XFF
660
661/* ADCIN5_LOW REGSISTER BIT */
662#define DA9052_AUTO5LOW_AUTO5LOW 0XFF
663
664/* ADCIN6_RES REGSISTER BIT */
665#define DA9052_ADCIN6RES_ADCIN6RES 0XFF
666
667/* ADCIN6_HIGH REGSISTER BIT */
668#define DA9052_AUTO6HIGH_AUTO6HIGH 0XFF
669
670/* ADCIN6_LOW REGSISTER BIT */
671#define DA9052_AUTO6LOW_AUTO6LOW 0XFF
672
673/* TJUNC_RES REGSISTER BIT*/
674#define DA9052_TJUNCRES_TJUNCRES 0XFF
675
676/* TSI REGISTER */
677/* TSI CONTROL REGISTER A BITS */
678#define DA9052_TSICONTA_TSIDELAY 0XC0
679#define DA9052_TSICONTA_TSISKIP 0X38
680#define DA9052_TSICONTA_TSIMODE 0X04
681#define DA9052_TSICONTA_PENDETEN 0X02
682#define DA9052_TSICONTA_AUTOTSIEN 0X01
683
684/* TSI CONTROL REGISTER B BITS */
685#define DA9052_TSICONTB_ADCREF 0X80
686#define DA9052_TSICONTB_TSIMAN 0X40
687#define DA9052_TSICONTB_TSIMUX 0X30
688#define DA9052_TSICONTB_TSISEL3 0X08
689#define DA9052_TSICONTB_TSISEL2 0X04
690#define DA9052_TSICONTB_TSISEL1 0X02
691#define DA9052_TSICONTB_TSISEL0 0X01
692
693/* TSI X CO-ORDINATE MSB RESULT REGISTER BITS */
694#define DA9052_TSIXMSB_TSIXM 0XFF
695
696/* TSI Y CO-ORDINATE MSB RESULT REGISTER BITS */
697#define DA9052_TSIYMSB_TSIYM 0XFF
698
699/* TSI CO-ORDINATE LSB RESULT REGISTER BITS */
700#define DA9052_TSILSB_PENDOWN 0X40
701#define DA9052_TSILSB_TSIZL 0X30
702#define DA9052_TSILSB_TSIYL 0X0C
703#define DA9052_TSILSB_TSIXL 0X03
704
705/* TSI Z MEASUREMENT MSB RESULT REGISTER BIT */
706#define DA9052_TSIZMSB_TSIZM 0XFF
707
708/* RTC REGISTER */
709/* RTC TIMER SECONDS REGISTER BITS */
710#define DA9052_COUNTS_MONITOR 0X40
711#define DA9052_RTC_SEC 0X3F
712
713/* RTC TIMER MINUTES REGISTER BIT */
714#define DA9052_RTC_MIN 0X3F
715
716/* RTC TIMER HOUR REGISTER BIT */
717#define DA9052_RTC_HOUR 0X1F
718
719/* RTC TIMER DAYS REGISTER BIT */
720#define DA9052_RTC_DAY 0X1F
721
722/* RTC TIMER MONTHS REGISTER BIT */
723#define DA9052_RTC_MONTH 0X0F
724
725/* RTC TIMER YEARS REGISTER BIT */
726#define DA9052_RTC_YEAR 0X3F
727
728/* RTC ALARM MINUTES REGISTER BITS */
729#define DA9052_ALARMM_I_TICK_TYPE 0X80
730#define DA9052_ALARMMI_ALARMTYPE 0X40
731
732/* RTC ALARM YEARS REGISTER BITS */
733#define DA9052_ALARM_Y_TICK_ON 0X80
734#define DA9052_ALARM_Y_ALARM_ON 0X40
735
736/* RTC SECONDS REGISTER A BITS */
737#define DA9052_SECONDA_SECONDSA 0XFF
738
739/* RTC SECONDS REGISTER B BITS */
740#define DA9052_SECONDB_SECONDSB 0XFF
741
742/* RTC SECONDS REGISTER C BITS */
743#define DA9052_SECONDC_SECONDSC 0XFF
744
745/* RTC SECONDS REGISTER D BITS */
746#define DA9052_SECONDD_SECONDSD 0XFF
747
748#endif
749/* __LINUX_MFD_DA9052_REG_H */
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 690276a642cf..eb93921cdd30 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -23,9 +23,8 @@ struct spi_device;
23/* An enum of all the supported cache types */ 23/* An enum of all the supported cache types */
24enum regcache_type { 24enum regcache_type {
25 REGCACHE_NONE, 25 REGCACHE_NONE,
26 REGCACHE_INDEXED,
27 REGCACHE_RBTREE, 26 REGCACHE_RBTREE,
28 REGCACHE_LZO 27 REGCACHE_COMPRESSED
29}; 28};
30 29
31/** 30/**
@@ -83,7 +82,7 @@ struct regmap_config {
83 bool (*precious_reg)(struct device *dev, unsigned int reg); 82 bool (*precious_reg)(struct device *dev, unsigned int reg);
84 83
85 unsigned int max_register; 84 unsigned int max_register;
86 struct reg_default *reg_defaults; 85 const struct reg_default *reg_defaults;
87 unsigned int num_reg_defaults; 86 unsigned int num_reg_defaults;
88 enum regcache_type cache_type; 87 enum regcache_type cache_type;
89 const void *reg_defaults_raw; 88 const void *reg_defaults_raw;
@@ -129,6 +128,8 @@ struct regmap *regmap_init_spi(struct spi_device *dev,
129 const struct regmap_config *config); 128 const struct regmap_config *config);
130 129
131void regmap_exit(struct regmap *map); 130void regmap_exit(struct regmap *map);
131int regmap_reinit_cache(struct regmap *map,
132 const struct regmap_config *config);
132int regmap_write(struct regmap *map, unsigned int reg, unsigned int val); 133int regmap_write(struct regmap *map, unsigned int reg, unsigned int val);
133int regmap_raw_write(struct regmap *map, unsigned int reg, 134int regmap_raw_write(struct regmap *map, unsigned int reg,
134 const void *val, size_t val_len); 135 const void *val, size_t val_len);
@@ -139,9 +140,61 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
139 size_t val_count); 140 size_t val_count);
140int regmap_update_bits(struct regmap *map, unsigned int reg, 141int regmap_update_bits(struct regmap *map, unsigned int reg,
141 unsigned int mask, unsigned int val); 142 unsigned int mask, unsigned int val);
143int regmap_update_bits_check(struct regmap *map, unsigned int reg,
144 unsigned int mask, unsigned int val,
145 bool *change);
142 146
143int regcache_sync(struct regmap *map); 147int regcache_sync(struct regmap *map);
144void regcache_cache_only(struct regmap *map, bool enable); 148void regcache_cache_only(struct regmap *map, bool enable);
145void regcache_cache_bypass(struct regmap *map, bool enable); 149void regcache_cache_bypass(struct regmap *map, bool enable);
150void regcache_mark_dirty(struct regmap *map);
151
152/**
153 * Description of an IRQ for the generic regmap irq_chip.
154 *
155 * @reg_offset: Offset of the status/mask register within the bank
156 * @mask: Mask used to flag/control the register.
157 */
158struct regmap_irq {
159 unsigned int reg_offset;
160 unsigned int mask;
161};
162
163/**
164 * Description of a generic regmap irq_chip. This is not intended to
165 * handle every possible interrupt controller, but it should handle a
166 * substantial proportion of those that are found in the wild.
167 *
168 * @name: Descriptive name for IRQ controller.
169 *
170 * @status_base: Base status register address.
171 * @mask_base: Base mask register address.
172 * @ack_base: Base ack address. If zero then the chip is clear on read.
173 *
174 * @num_regs: Number of registers in each control bank.
175 * @irqs: Descriptors for individual IRQs. Interrupt numbers are
176 * assigned based on the index in the array of the interrupt.
177 * @num_irqs: Number of descriptors.
178 */
179struct regmap_irq_chip {
180 const char *name;
181
182 unsigned int status_base;
183 unsigned int mask_base;
184 unsigned int ack_base;
185
186 int num_regs;
187
188 const struct regmap_irq *irqs;
189 int num_irqs;
190};
191
192struct regmap_irq_chip_data;
193
194int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
195 int irq_base, struct regmap_irq_chip *chip,
196 struct regmap_irq_chip_data **data);
197void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data);
198int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data);
146 199
147#endif 200#endif
diff --git a/include/trace/events/regmap.h b/include/trace/events/regmap.h
index 1e3193b8fcc8..12fbf43524e9 100644
--- a/include/trace/events/regmap.h
+++ b/include/trace/events/regmap.h
@@ -55,6 +55,15 @@ DEFINE_EVENT(regmap_reg, regmap_reg_read,
55 55
56); 56);
57 57
58DEFINE_EVENT(regmap_reg, regmap_reg_read_cache,
59
60 TP_PROTO(struct device *dev, unsigned int reg,
61 unsigned int val),
62
63 TP_ARGS(dev, reg, val)
64
65);
66
58DECLARE_EVENT_CLASS(regmap_block, 67DECLARE_EVENT_CLASS(regmap_block,
59 68
60 TP_PROTO(struct device *dev, unsigned int reg, int count), 69 TP_PROTO(struct device *dev, unsigned int reg, int count),
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 10:43:22 -0500