drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well

This needs to be done before we power back on the CMN_BC well so the PHY
can calibrate properly.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 11 insertions, 8 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bcbd742149c6..4973fe03f9aa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1484,14 +1484,6 @@ static void intel_reset_dpio(struct drm_device *dev)
         if (!IS_VALLEYVIEW(dev))
                 return;
 
-        /*
-         * Enable the CRI clock source so we can get at the display and the
-         * reference clock for VGA hotplug / manual detection.
-         */
-        I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
-                   DPLL_REFA_CLK_ENABLE_VLV |
-                   DPLL_INTEGRATED_CRI_CLK_VLV);
-
         if (IS_CHERRYVIEW(dev)) {
                 enum dpio_phy phy;
                 u32 val;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 25caf8fb6656..813afac04ddf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5715,6 +5715,17 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv,
         u32 state;
         u32 ctrl;
 
+        if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable) {
+                /*
+                 * Enable the CRI clock source so we can get at the display
+                 * and the reference clock for VGA hotplug / manual detection.
+                 */
+                I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+                           DPLL_REFA_CLK_ENABLE_VLV |
+                           DPLL_INTEGRATED_CRI_CLK_VLV);
+                udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
+        }
+
         mask = PUNIT_PWRGT_MASK(power_well_id);
         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
                          PUNIT_PWRGT_PWR_GATE(power_well_id);