aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJesse Barnes <jbarnes@virtuousgeek.org>2011-10-20 18:09:17 -0400
committerKeith Packard <keithp@keithp.com>2011-10-21 02:22:01 -0400
commita60f0e38d72a5e24085d6e7e27a4cadc20ae268a (patch)
tree65dfb758c4b13423203aeb8535f547b5718cd256
parenta2006cf5a7ad3463e7c1e9da2c4bc90499427558 (diff)
drm/i915: add DP test request handling
DPCD 1.1+ adds some automated test infrastructure support. Add support for reading the IRQ source and jumping to a test handling routine if needed. Subsequent patches will handle particular tests; this patch just ACKs any requested tests by default. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c37
-rw-r--r--include/drm/drm_dp_helper.h25
2 files changed, 62 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e0ff9085fd86..58c827b52a29 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1776,6 +1776,27 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
1776 return false; 1776 return false;
1777} 1777}
1778 1778
1779static bool
1780intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1781{
1782 int ret;
1783
1784 ret = intel_dp_aux_native_read_retry(intel_dp,
1785 DP_DEVICE_SERVICE_IRQ_VECTOR,
1786 sink_irq_vector, 1);
1787 if (!ret)
1788 return false;
1789
1790 return true;
1791}
1792
1793static void
1794intel_dp_handle_test_request(struct intel_dp *intel_dp)
1795{
1796 /* NAK by default */
1797 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1798}
1799
1779/* 1800/*
1780 * According to DP spec 1801 * According to DP spec
1781 * 5.1.2: 1802 * 5.1.2:
@@ -1788,6 +1809,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
1788static void 1809static void
1789intel_dp_check_link_status(struct intel_dp *intel_dp) 1810intel_dp_check_link_status(struct intel_dp *intel_dp)
1790{ 1811{
1812 u8 sink_irq_vector;
1813
1791 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) 1814 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1792 return; 1815 return;
1793 1816
@@ -1806,6 +1829,20 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
1806 return; 1829 return;
1807 } 1830 }
1808 1831
1832 /* Try to read the source of the interrupt */
1833 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1834 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1835 /* Clear interrupt source */
1836 intel_dp_aux_native_write_1(intel_dp,
1837 DP_DEVICE_SERVICE_IRQ_VECTOR,
1838 sink_irq_vector);
1839
1840 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
1841 intel_dp_handle_test_request(intel_dp);
1842 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
1843 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
1844 }
1845
1809 if (!intel_channel_eq_ok(intel_dp)) { 1846 if (!intel_channel_eq_ok(intel_dp)) {
1810 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 1847 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1811 drm_get_encoder_name(&intel_dp->base.base)); 1848 drm_get_encoder_name(&intel_dp->base.base));
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 2b1a3585f8d8..0d2f727e96be 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -153,6 +153,12 @@
153# define DP_PSR_CRC_VERIFICATION (1 << 2) 153# define DP_PSR_CRC_VERIFICATION (1 << 2)
154# define DP_PSR_FRAME_CAPTURE (1 << 3) 154# define DP_PSR_FRAME_CAPTURE (1 << 3)
155 155
156#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
157# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
158# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
159# define DP_CP_IRQ (1 << 2)
160# define DP_SINK_SPECIFIC_IRQ (1 << 6)
161
156#define DP_LANE0_1_STATUS 0x202 162#define DP_LANE0_1_STATUS 0x202
157#define DP_LANE2_3_STATUS 0x203 163#define DP_LANE2_3_STATUS 0x203
158# define DP_LANE_CR_DONE (1 << 0) 164# define DP_LANE_CR_DONE (1 << 0)
@@ -185,6 +191,25 @@
185# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 191# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
186# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 192# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
187 193
194#define DP_TEST_REQUEST 0x218
195# define DP_TEST_LINK_TRAINING (1 << 0)
196# define DP_TEST_LINK_PATTERN (1 << 1)
197# define DP_TEST_LINK_EDID_READ (1 << 2)
198# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
199
200#define DP_TEST_LINK_RATE 0x219
201# define DP_LINK_RATE_162 (0x6)
202# define DP_LINK_RATE_27 (0xa)
203
204#define DP_TEST_LANE_COUNT 0x220
205
206#define DP_TEST_PATTERN 0x221
207
208#define DP_TEST_RESPONSE 0x260
209# define DP_TEST_ACK (1 << 0)
210# define DP_TEST_NAK (1 << 1)
211# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
212
188#define DP_SET_POWER 0x600 213#define DP_SET_POWER 0x600
189# define DP_SET_POWER_D0 0x1 214# define DP_SET_POWER_D0 0x1
190# define DP_SET_POWER_D3 0x2 215# define DP_SET_POWER_D3 0x2