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authorAlexander Graf <agraf@suse.de>2014-04-25 10:07:21 -0400
committerAlexander Graf <agraf@suse.de>2014-05-30 08:26:22 -0400
commita5948fa092a04dfd6b9ee31c99eb6896c158eb08 (patch)
tree228059928f720af84ba0a9211eee2bf557e238ee
parentf8f6eb0d189cf2724af5ebc8cad460c78fb1994e (diff)
KVM: PPC: Book3S PR: Emulate TIR register
In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a Thread ID Register (TIR). Since PR KVM doesn't emulate more than one thread per core, we can just always expose 0 here. Signed-off-by: Alexander Graf <agraf@suse.de>
-rw-r--r--arch/powerpc/kvm/book3s_emulate.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 52448ef499cb..0a1de29a4caf 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -566,6 +566,7 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
566 case SPRN_MMCR0: 566 case SPRN_MMCR0:
567 case SPRN_MMCR1: 567 case SPRN_MMCR1:
568 case SPRN_MMCR2: 568 case SPRN_MMCR2:
569 case SPRN_TIR:
569#endif 570#endif
570 *spr_val = 0; 571 *spr_val = 0;
571 break; 572 break;