Merge branch 'bnx2x'

Yuval Mintz says:

====================
bnx2x: Bug fixes patch series

This patch series contains various bug fixes - 2 link related fixes,
one sriov-related issue and an additional fix for a theoretical bug
on new boards.

Please consider applying these patches to `net'.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

3 files changed, 54 insertions, 21 deletions

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index 4fef1e199366..53fb4fa61b40 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -3702,7 +3702,8 @@ static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
                                         struct link_params *params,
                                         struct link_vars *vars) {
-        u16 lane, i, cl72_ctrl, an_adv = 0;
+        u16 lane, i, cl72_ctrl, an_adv = 0, val;
+        u32 wc_lane_config;
         struct bnx2x *bp = params->bp;
         static struct bnx2x_reg_set reg_set[] = {
                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
@@ -3821,15 +3822,27 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
                 /* Enable Auto-Detect to support 1G over CL37 as well */
                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
-
+                wc_lane_config = REG_RD(bp, params->shmem_base +
+                                        offsetof(struct shmem_region, dev_info.
+                                        shared_hw_config.wc_lane_config));
+                bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
+                                MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
                 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
                  * parallel-detect loop when CL73 and CL37 are enabled.
                  */
-                CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
-                                  MDIO_AER_BLOCK_AER_REG, 0);
+                val |= 1 << 11;
+
+                /* Restore Polarity settings in case it was run over by
+                 * previous link owner
+                 */
+                if (wc_lane_config &
+                    (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
+                        val |= 3 << 2;
+                else
+                        val &= ~(3 << 2);
                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
-                                 MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
-                bnx2x_set_aer_mmd(params, phy);
+                                 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
+                                 val);
 
                 bnx2x_disable_kr2(params, vars, phy);
         }
@@ -12459,6 +12472,7 @@ static int bnx2x_avoid_link_flap(struct link_params *params,
         u32 dont_clear_stat, lfa_sts;
         struct bnx2x *bp = params->bp;
 
+        bnx2x_set_mdio_emac_per_phy(bp, params);
         /* Sync the link parameters */
         bnx2x_link_status_update(params, vars);
 
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index cf14218697e4..c5061353a475 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -10053,6 +10053,24 @@ static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
 #define BNX2X_PREV_UNDI_MF_PORT(p) (BAR_TSTRORM_INTMEM + 0x150c + ((p) << 4))
 #define BNX2X_PREV_UNDI_MF_FUNC(f) (BAR_TSTRORM_INTMEM + 0x184c + ((f) << 4))
+
+static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
+{
+        /* UNDI marks its presence in DORQ -
+         * it initializes CID offset for normal bell to 0x7
+         */
+        if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
+            MISC_REGISTERS_RESET_REG_1_RST_DORQ))
+                return false;
+
+        if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
+                BNX2X_DEV_INFO("UNDI previously loaded\n");
+                return true;
+        }
+
+        return false;
+}
+
 static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
 {
         u8 major, minor, version;
@@ -10302,6 +10320,10 @@ static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
 
         BNX2X_DEV_INFO("Path is unmarked\n");
 
+        /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
+        if (bnx2x_prev_is_after_undi(bp))
+                goto out;
+
         /* If function has FLR capabilities, and existing FW version matches
          * the one required, then FLR will be sufficient to clean any residue
          * left by previous driver
@@ -10322,6 +10344,7 @@ static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
 
         BNX2X_DEV_INFO("Could not FLR\n");
 
+out:
         /* Close the MCP request, return failure*/
         rc = bnx2x_prev_mcp_done(bp);
         if (!rc)
@@ -10360,19 +10383,13 @@ static int bnx2x_prev_unload_common(struct bnx2x *bp)
                 /* close LLH filters towards the BRB */
                 bnx2x_set_rx_filter(&bp->link_params, 0);
 
-                /* Check if the UNDI driver was previously loaded
-                 * UNDI driver initializes CID offset for normal bell to 0x7
-                 */
-                if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
-                        tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
-                        if (tmp_reg == 0x7) {
-                                BNX2X_DEV_INFO("UNDI previously loaded\n");
-                                prev_undi = true;
-                                /* clear the UNDI indication */
-                                REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
-                                /* clear possible idle check errors */
-                                REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
-                        }
+                /* Check if the UNDI driver was previously loaded */
+                if (bnx2x_prev_is_after_undi(bp)) {
+                        prev_undi = true;
+                        /* clear the UNDI indication */
+                        REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
+                        /* clear possible idle check errors */
+                        REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
                 }
                 if (!CHIP_IS_E1x(bp))
                         /* block FW from writing to host */
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
index a93c7af7afe6..f7edb4204f91 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
@@ -1071,8 +1071,10 @@ void bnx2x_iov_init_dq(struct bnx2x *bp)
         REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
         REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
 
-        /* set the VF doorbell threshold */
-        REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 4);
+        /* set the VF doorbell threshold. This threshold represents the amount
+         * of doorbells allowed in the main DORQ fifo for a specific VF.
+         */
+        REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64);
 }
 
 void bnx2x_iov_init_dmae(struct bnx2x *bp)