diff options
| author | Jingoo Han <jg1.han@samsung.com> | 2012-07-18 05:50:59 -0400 |
|---|---|---|
| committer | Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | 2012-07-24 16:56:18 -0400 |
| commit | a2c81bc12c81189928a03a94da1565d0c14e32eb (patch) | |
| tree | e9f20a421b085d2b50e780e97a10cc0bbca86008 | |
| parent | 1f61ce508a2e88d19045aa77f90f366251419529 (diff) | |
video: exynos_dp: use usleep_range instead of delay
This patch replaces udelay and mdelay with usleep_range to remove
the busy loop waiting.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
| -rw-r--r-- | drivers/video/exynos/exynos_dp_core.c | 14 | ||||
| -rw-r--r-- | drivers/video/exynos/exynos_dp_reg.c | 4 |
2 files changed, 9 insertions, 9 deletions
diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c index 0f3a64baecc9..c6c016a506ce 100644 --- a/drivers/video/exynos/exynos_dp_core.c +++ b/drivers/video/exynos/exynos_dp_core.c | |||
| @@ -47,7 +47,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp) | |||
| 47 | 47 | ||
| 48 | exynos_dp_init_hpd(dp); | 48 | exynos_dp_init_hpd(dp); |
| 49 | 49 | ||
| 50 | udelay(200); | 50 | usleep_range(200, 210); |
| 51 | 51 | ||
| 52 | while (exynos_dp_get_plug_in_status(dp) != 0) { | 52 | while (exynos_dp_get_plug_in_status(dp) != 0) { |
| 53 | timeout_loop++; | 53 | timeout_loop++; |
| @@ -55,7 +55,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp) | |||
| 55 | dev_err(dp->dev, "failed to get hpd plug status\n"); | 55 | dev_err(dp->dev, "failed to get hpd plug status\n"); |
| 56 | return -ETIMEDOUT; | 56 | return -ETIMEDOUT; |
| 57 | } | 57 | } |
| 58 | udelay(10); | 58 | usleep_range(10, 11); |
| 59 | } | 59 | } |
| 60 | 60 | ||
| 61 | return 0; | 61 | return 0; |
| @@ -486,7 +486,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) | |||
| 486 | u8 pre_emphasis; | 486 | u8 pre_emphasis; |
| 487 | u8 training_lane; | 487 | u8 training_lane; |
| 488 | 488 | ||
| 489 | udelay(100); | 489 | usleep_range(100, 101); |
| 490 | 490 | ||
| 491 | exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, | 491 | exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, |
| 492 | 6, link_status); | 492 | 6, link_status); |
| @@ -571,7 +571,7 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) | |||
| 571 | 571 | ||
| 572 | u8 adjust_request[2]; | 572 | u8 adjust_request[2]; |
| 573 | 573 | ||
| 574 | udelay(400); | 574 | usleep_range(400, 401); |
| 575 | 575 | ||
| 576 | exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, | 576 | exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, |
| 577 | 6, link_status); | 577 | 6, link_status); |
| @@ -739,7 +739,7 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp, | |||
| 739 | if (retval == 0) | 739 | if (retval == 0) |
| 740 | break; | 740 | break; |
| 741 | 741 | ||
| 742 | udelay(100); | 742 | usleep_range(100, 110); |
| 743 | } | 743 | } |
| 744 | 744 | ||
| 745 | return retval; | 745 | return retval; |
| @@ -773,7 +773,7 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp, | |||
| 773 | return -ETIMEDOUT; | 773 | return -ETIMEDOUT; |
| 774 | } | 774 | } |
| 775 | 775 | ||
| 776 | udelay(1); | 776 | usleep_range(1, 2); |
| 777 | } | 777 | } |
| 778 | 778 | ||
| 779 | /* Set to use the register calculated M/N video */ | 779 | /* Set to use the register calculated M/N video */ |
| @@ -807,7 +807,7 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp, | |||
| 807 | return -ETIMEDOUT; | 807 | return -ETIMEDOUT; |
| 808 | } | 808 | } |
| 809 | 809 | ||
| 810 | mdelay(1); | 810 | usleep_range(1000, 1001); |
| 811 | } | 811 | } |
| 812 | 812 | ||
| 813 | if (retval != 0) | 813 | if (retval != 0) |
diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c index 6ce76d56c3a1..ce401c83f638 100644 --- a/drivers/video/exynos/exynos_dp_reg.c +++ b/drivers/video/exynos/exynos_dp_reg.c | |||
| @@ -122,7 +122,7 @@ void exynos_dp_reset(struct exynos_dp_device *dp) | |||
| 122 | LS_CLK_DOMAIN_FUNC_EN_N; | 122 | LS_CLK_DOMAIN_FUNC_EN_N; |
| 123 | writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); | 123 | writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); |
| 124 | 124 | ||
| 125 | udelay(20); | 125 | usleep_range(20, 30); |
| 126 | 126 | ||
| 127 | exynos_dp_lane_swap(dp, 0); | 127 | exynos_dp_lane_swap(dp, 0); |
| 128 | 128 | ||
| @@ -988,7 +988,7 @@ void exynos_dp_reset_macro(struct exynos_dp_device *dp) | |||
| 988 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); | 988 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); |
| 989 | 989 | ||
| 990 | /* 10 us is the minimum reset time. */ | 990 | /* 10 us is the minimum reset time. */ |
| 991 | udelay(10); | 991 | usleep_range(10, 20); |
| 992 | 992 | ||
| 993 | reg &= ~MACRO_RST; | 993 | reg &= ~MACRO_RST; |
| 994 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); | 994 | writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); |
