diff options
author | Javier Martinez Canillas <javier@dowhile0.org> | 2014-06-27 16:17:37 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2014-07-09 06:22:56 -0400 |
commit | a0e827c68d9c159bc028851061e21b4f73aeeef4 (patch) | |
tree | 5b1432bf6a87726aa663e38bcbcec435b3154a6d | |
parent | 598f64d40daa32419c3914dbe57589184d135d60 (diff) |
gpio: omap: Add an omap prefix to all functions
The GPIO OMAP driver didn't have a consistent naming scheme for
all its functions. Some of them had an omap prefix while others
didn't. There are many advantages on having a separate namespace
for driver functions so let's add an "omap" prefix to all of them.
Signed-off-by: Javier Martinez Canillas <jmartinez@softcrates.net>
Acked-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r-- | drivers/gpio/gpio-omap.c | 268 |
1 files changed, 137 insertions, 131 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index ef461e7bbbe0..174932165fcb 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c | |||
@@ -88,18 +88,19 @@ struct gpio_bank { | |||
88 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) | 88 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
89 | #define LINE_USED(line, offset) (line & (BIT(offset))) | 89 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
90 | 90 | ||
91 | static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) | 91 | static int omap_irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
92 | { | 92 | { |
93 | return bank->chip.base + gpio_irq; | 93 | return bank->chip.base + gpio_irq; |
94 | } | 94 | } |
95 | 95 | ||
96 | static inline struct gpio_bank *_irq_data_get_bank(struct irq_data *d) | 96 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
97 | { | 97 | { |
98 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); | 98 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
99 | return container_of(chip, struct gpio_bank, chip); | 99 | return container_of(chip, struct gpio_bank, chip); |
100 | } | 100 | } |
101 | 101 | ||
102 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | 102 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
103 | int is_input) | ||
103 | { | 104 | { |
104 | void __iomem *reg = bank->base; | 105 | void __iomem *reg = bank->base; |
105 | u32 l; | 106 | u32 l; |
@@ -116,7 +117,8 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |||
116 | 117 | ||
117 | 118 | ||
118 | /* set data out value using dedicate set/clear register */ | 119 | /* set data out value using dedicate set/clear register */ |
119 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | 120 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, |
121 | int enable) | ||
120 | { | 122 | { |
121 | void __iomem *reg = bank->base; | 123 | void __iomem *reg = bank->base; |
122 | u32 l = GPIO_BIT(bank, gpio); | 124 | u32 l = GPIO_BIT(bank, gpio); |
@@ -133,7 +135,8 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |||
133 | } | 135 | } |
134 | 136 | ||
135 | /* set data out value using mask register */ | 137 | /* set data out value using mask register */ |
136 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | 138 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, |
139 | int enable) | ||
137 | { | 140 | { |
138 | void __iomem *reg = bank->base + bank->regs->dataout; | 141 | void __iomem *reg = bank->base + bank->regs->dataout; |
139 | u32 gpio_bit = GPIO_BIT(bank, gpio); | 142 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
@@ -148,21 +151,21 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |||
148 | bank->context.dataout = l; | 151 | bank->context.dataout = l; |
149 | } | 152 | } |
150 | 153 | ||
151 | static int _get_gpio_datain(struct gpio_bank *bank, int offset) | 154 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
152 | { | 155 | { |
153 | void __iomem *reg = bank->base + bank->regs->datain; | 156 | void __iomem *reg = bank->base + bank->regs->datain; |
154 | 157 | ||
155 | return (readl_relaxed(reg) & (BIT(offset))) != 0; | 158 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
156 | } | 159 | } |
157 | 160 | ||
158 | static int _get_gpio_dataout(struct gpio_bank *bank, int offset) | 161 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
159 | { | 162 | { |
160 | void __iomem *reg = bank->base + bank->regs->dataout; | 163 | void __iomem *reg = bank->base + bank->regs->dataout; |
161 | 164 | ||
162 | return (readl_relaxed(reg) & (BIT(offset))) != 0; | 165 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
163 | } | 166 | } |
164 | 167 | ||
165 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) | 168 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
166 | { | 169 | { |
167 | int l = readl_relaxed(base + reg); | 170 | int l = readl_relaxed(base + reg); |
168 | 171 | ||
@@ -174,7 +177,7 @@ static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) | |||
174 | writel_relaxed(l, base + reg); | 177 | writel_relaxed(l, base + reg); |
175 | } | 178 | } |
176 | 179 | ||
177 | static inline void _gpio_dbck_enable(struct gpio_bank *bank) | 180 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
178 | { | 181 | { |
179 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | 182 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { |
180 | clk_prepare_enable(bank->dbck); | 183 | clk_prepare_enable(bank->dbck); |
@@ -185,7 +188,7 @@ static inline void _gpio_dbck_enable(struct gpio_bank *bank) | |||
185 | } | 188 | } |
186 | } | 189 | } |
187 | 190 | ||
188 | static inline void _gpio_dbck_disable(struct gpio_bank *bank) | 191 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
189 | { | 192 | { |
190 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | 193 | if (bank->dbck_enable_mask && bank->dbck_enabled) { |
191 | /* | 194 | /* |
@@ -201,7 +204,7 @@ static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |||
201 | } | 204 | } |
202 | 205 | ||
203 | /** | 206 | /** |
204 | * _set_gpio_debounce - low level gpio debounce time | 207 | * omap2_set_gpio_debounce - low level gpio debounce time |
205 | * @bank: the gpio bank we're acting upon | 208 | * @bank: the gpio bank we're acting upon |
206 | * @gpio: the gpio number on this @gpio | 209 | * @gpio: the gpio number on this @gpio |
207 | * @debounce: debounce time to use | 210 | * @debounce: debounce time to use |
@@ -209,8 +212,8 @@ static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |||
209 | * OMAP's debounce time is in 31us steps so we need | 212 | * OMAP's debounce time is in 31us steps so we need |
210 | * to convert and round up to the closest unit. | 213 | * to convert and round up to the closest unit. |
211 | */ | 214 | */ |
212 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | 215 | static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, |
213 | unsigned debounce) | 216 | unsigned debounce) |
214 | { | 217 | { |
215 | void __iomem *reg; | 218 | void __iomem *reg; |
216 | u32 val; | 219 | u32 val; |
@@ -251,7 +254,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |||
251 | * used within _gpio_dbck_enable() is still not initialized at | 254 | * used within _gpio_dbck_enable() is still not initialized at |
252 | * that point. Therefore we have to enable dbck here. | 255 | * that point. Therefore we have to enable dbck here. |
253 | */ | 256 | */ |
254 | _gpio_dbck_enable(bank); | 257 | omap_gpio_dbck_enable(bank); |
255 | if (bank->dbck_enable_mask) { | 258 | if (bank->dbck_enable_mask) { |
256 | bank->context.debounce = debounce; | 259 | bank->context.debounce = debounce; |
257 | bank->context.debounce_en = val; | 260 | bank->context.debounce_en = val; |
@@ -259,7 +262,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |||
259 | } | 262 | } |
260 | 263 | ||
261 | /** | 264 | /** |
262 | * _clear_gpio_debounce - clear debounce settings for a gpio | 265 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
263 | * @bank: the gpio bank we're acting upon | 266 | * @bank: the gpio bank we're acting upon |
264 | * @gpio: the gpio number on this @gpio | 267 | * @gpio: the gpio number on this @gpio |
265 | * | 268 | * |
@@ -268,7 +271,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |||
268 | * time too. The debounce clock will also be disabled when calling this function | 271 | * time too. The debounce clock will also be disabled when calling this function |
269 | * if this is the only gpio in the bank using debounce. | 272 | * if this is the only gpio in the bank using debounce. |
270 | */ | 273 | */ |
271 | static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) | 274 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) |
272 | { | 275 | { |
273 | u32 gpio_bit = GPIO_BIT(bank, gpio); | 276 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
274 | 277 | ||
@@ -292,20 +295,20 @@ static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) | |||
292 | } | 295 | } |
293 | } | 296 | } |
294 | 297 | ||
295 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, | 298 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
296 | unsigned trigger) | 299 | unsigned trigger) |
297 | { | 300 | { |
298 | void __iomem *base = bank->base; | 301 | void __iomem *base = bank->base; |
299 | u32 gpio_bit = BIT(gpio); | 302 | u32 gpio_bit = BIT(gpio); |
300 | 303 | ||
301 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, | 304 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
302 | trigger & IRQ_TYPE_LEVEL_LOW); | 305 | trigger & IRQ_TYPE_LEVEL_LOW); |
303 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | 306 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, |
304 | trigger & IRQ_TYPE_LEVEL_HIGH); | 307 | trigger & IRQ_TYPE_LEVEL_HIGH); |
305 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | 308 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, |
306 | trigger & IRQ_TYPE_EDGE_RISING); | 309 | trigger & IRQ_TYPE_EDGE_RISING); |
307 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | 310 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, |
308 | trigger & IRQ_TYPE_EDGE_FALLING); | 311 | trigger & IRQ_TYPE_EDGE_FALLING); |
309 | 312 | ||
310 | bank->context.leveldetect0 = | 313 | bank->context.leveldetect0 = |
311 | readl_relaxed(bank->base + bank->regs->leveldetect0); | 314 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
@@ -317,7 +320,7 @@ static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, | |||
317 | readl_relaxed(bank->base + bank->regs->fallingdetect); | 320 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
318 | 321 | ||
319 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | 322 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
320 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); | 323 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
321 | bank->context.wake_en = | 324 | bank->context.wake_en = |
322 | readl_relaxed(bank->base + bank->regs->wkup_en); | 325 | readl_relaxed(bank->base + bank->regs->wkup_en); |
323 | } | 326 | } |
@@ -353,7 +356,7 @@ exit: | |||
353 | * This only applies to chips that can't do both rising and falling edge | 356 | * This only applies to chips that can't do both rising and falling edge |
354 | * detection at once. For all other chips, this function is a noop. | 357 | * detection at once. For all other chips, this function is a noop. |
355 | */ | 358 | */ |
356 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | 359 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
357 | { | 360 | { |
358 | void __iomem *reg = bank->base; | 361 | void __iomem *reg = bank->base; |
359 | u32 l = 0; | 362 | u32 l = 0; |
@@ -372,18 +375,18 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |||
372 | writel_relaxed(l, reg); | 375 | writel_relaxed(l, reg); |
373 | } | 376 | } |
374 | #else | 377 | #else |
375 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | 378 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
376 | #endif | 379 | #endif |
377 | 380 | ||
378 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, | 381 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
379 | unsigned trigger) | 382 | unsigned trigger) |
380 | { | 383 | { |
381 | void __iomem *reg = bank->base; | 384 | void __iomem *reg = bank->base; |
382 | void __iomem *base = bank->base; | 385 | void __iomem *base = bank->base; |
383 | u32 l = 0; | 386 | u32 l = 0; |
384 | 387 | ||
385 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { | 388 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
386 | set_gpio_trigger(bank, gpio, trigger); | 389 | omap_set_gpio_trigger(bank, gpio, trigger); |
387 | } else if (bank->regs->irqctrl) { | 390 | } else if (bank->regs->irqctrl) { |
388 | reg += bank->regs->irqctrl; | 391 | reg += bank->regs->irqctrl; |
389 | 392 | ||
@@ -413,7 +416,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, | |||
413 | l |= BIT(gpio << 1); | 416 | l |= BIT(gpio << 1); |
414 | 417 | ||
415 | /* Enable wake-up during idle for dynamic tick */ | 418 | /* Enable wake-up during idle for dynamic tick */ |
416 | _gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); | 419 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
417 | bank->context.wake_en = | 420 | bank->context.wake_en = |
418 | readl_relaxed(bank->base + bank->regs->wkup_en); | 421 | readl_relaxed(bank->base + bank->regs->wkup_en); |
419 | writel_relaxed(l, reg); | 422 | writel_relaxed(l, reg); |
@@ -421,7 +424,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, | |||
421 | return 0; | 424 | return 0; |
422 | } | 425 | } |
423 | 426 | ||
424 | static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset) | 427 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
425 | { | 428 | { |
426 | if (bank->regs->pinctrl) { | 429 | if (bank->regs->pinctrl) { |
427 | void __iomem *reg = bank->base + bank->regs->pinctrl; | 430 | void __iomem *reg = bank->base + bank->regs->pinctrl; |
@@ -442,7 +445,7 @@ static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset) | |||
442 | } | 445 | } |
443 | } | 446 | } |
444 | 447 | ||
445 | static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset) | 448 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
446 | { | 449 | { |
447 | void __iomem *base = bank->base; | 450 | void __iomem *base = bank->base; |
448 | 451 | ||
@@ -450,7 +453,7 @@ static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset) | |||
450 | !LINE_USED(bank->mod_usage, offset) && | 453 | !LINE_USED(bank->mod_usage, offset) && |
451 | !LINE_USED(bank->irq_usage, offset)) { | 454 | !LINE_USED(bank->irq_usage, offset)) { |
452 | /* Disable wake-up during idle for dynamic tick */ | 455 | /* Disable wake-up during idle for dynamic tick */ |
453 | _gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); | 456 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
454 | bank->context.wake_en = | 457 | bank->context.wake_en = |
455 | readl_relaxed(bank->base + bank->regs->wkup_en); | 458 | readl_relaxed(bank->base + bank->regs->wkup_en); |
456 | } | 459 | } |
@@ -467,16 +470,16 @@ static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset) | |||
467 | } | 470 | } |
468 | } | 471 | } |
469 | 472 | ||
470 | static int gpio_is_input(struct gpio_bank *bank, int mask) | 473 | static int omap_gpio_is_input(struct gpio_bank *bank, int mask) |
471 | { | 474 | { |
472 | void __iomem *reg = bank->base + bank->regs->direction; | 475 | void __iomem *reg = bank->base + bank->regs->direction; |
473 | 476 | ||
474 | return readl_relaxed(reg) & mask; | 477 | return readl_relaxed(reg) & mask; |
475 | } | 478 | } |
476 | 479 | ||
477 | static int gpio_irq_type(struct irq_data *d, unsigned type) | 480 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
478 | { | 481 | { |
479 | struct gpio_bank *bank = _irq_data_get_bank(d); | 482 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
480 | unsigned gpio = 0; | 483 | unsigned gpio = 0; |
481 | int retval; | 484 | int retval; |
482 | unsigned long flags; | 485 | unsigned long flags; |
@@ -491,7 +494,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) | |||
491 | #endif | 494 | #endif |
492 | 495 | ||
493 | if (!gpio) | 496 | if (!gpio) |
494 | gpio = irq_to_gpio(bank, d->hwirq); | 497 | gpio = omap_irq_to_gpio(bank, d->hwirq); |
495 | 498 | ||
496 | if (type & ~IRQ_TYPE_SENSE_MASK) | 499 | if (type & ~IRQ_TYPE_SENSE_MASK) |
497 | return -EINVAL; | 500 | return -EINVAL; |
@@ -502,11 +505,11 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) | |||
502 | 505 | ||
503 | spin_lock_irqsave(&bank->lock, flags); | 506 | spin_lock_irqsave(&bank->lock, flags); |
504 | offset = GPIO_INDEX(bank, gpio); | 507 | offset = GPIO_INDEX(bank, gpio); |
505 | retval = _set_gpio_triggering(bank, offset, type); | 508 | retval = omap_set_gpio_triggering(bank, offset, type); |
506 | if (!LINE_USED(bank->mod_usage, offset)) { | 509 | if (!LINE_USED(bank->mod_usage, offset)) { |
507 | _enable_gpio_module(bank, offset); | 510 | omap_enable_gpio_module(bank, offset); |
508 | _set_gpio_direction(bank, offset, 1); | 511 | omap_set_gpio_direction(bank, offset, 1); |
509 | } else if (!gpio_is_input(bank, BIT(offset))) { | 512 | } else if (!omap_gpio_is_input(bank, BIT(offset))) { |
510 | spin_unlock_irqrestore(&bank->lock, flags); | 513 | spin_unlock_irqrestore(&bank->lock, flags); |
511 | return -EINVAL; | 514 | return -EINVAL; |
512 | } | 515 | } |
@@ -522,7 +525,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) | |||
522 | return retval; | 525 | return retval; |
523 | } | 526 | } |
524 | 527 | ||
525 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | 528 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
526 | { | 529 | { |
527 | void __iomem *reg = bank->base; | 530 | void __iomem *reg = bank->base; |
528 | 531 | ||
@@ -539,12 +542,12 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |||
539 | readl_relaxed(reg); | 542 | readl_relaxed(reg); |
540 | } | 543 | } |
541 | 544 | ||
542 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | 545 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) |
543 | { | 546 | { |
544 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | 547 | omap_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
545 | } | 548 | } |
546 | 549 | ||
547 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) | 550 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
548 | { | 551 | { |
549 | void __iomem *reg = bank->base; | 552 | void __iomem *reg = bank->base; |
550 | u32 l; | 553 | u32 l; |
@@ -558,7 +561,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) | |||
558 | return l; | 561 | return l; |
559 | } | 562 | } |
560 | 563 | ||
561 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | 564 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
562 | { | 565 | { |
563 | void __iomem *reg = bank->base; | 566 | void __iomem *reg = bank->base; |
564 | u32 l; | 567 | u32 l; |
@@ -580,7 +583,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |||
580 | writel_relaxed(l, reg); | 583 | writel_relaxed(l, reg); |
581 | } | 584 | } |
582 | 585 | ||
583 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | 586 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
584 | { | 587 | { |
585 | void __iomem *reg = bank->base; | 588 | void __iomem *reg = bank->base; |
586 | u32 l; | 589 | u32 l; |
@@ -602,12 +605,13 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |||
602 | writel_relaxed(l, reg); | 605 | writel_relaxed(l, reg); |
603 | } | 606 | } |
604 | 607 | ||
605 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | 608 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, int gpio, |
609 | int enable) | ||
606 | { | 610 | { |
607 | if (enable) | 611 | if (enable) |
608 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | 612 | omap_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
609 | else | 613 | else |
610 | _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | 614 | omap_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
611 | } | 615 | } |
612 | 616 | ||
613 | /* | 617 | /* |
@@ -618,7 +622,7 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena | |||
618 | * enabled. When system is suspended, only selected GPIO interrupts need | 622 | * enabled. When system is suspended, only selected GPIO interrupts need |
619 | * to have wake-up enabled. | 623 | * to have wake-up enabled. |
620 | */ | 624 | */ |
621 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | 625 | static int omap_set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) |
622 | { | 626 | { |
623 | u32 gpio_bit = GPIO_BIT(bank, gpio); | 627 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
624 | unsigned long flags; | 628 | unsigned long flags; |
@@ -641,22 +645,22 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |||
641 | return 0; | 645 | return 0; |
642 | } | 646 | } |
643 | 647 | ||
644 | static void _reset_gpio(struct gpio_bank *bank, int gpio) | 648 | static void omap_reset_gpio(struct gpio_bank *bank, int gpio) |
645 | { | 649 | { |
646 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); | 650 | omap_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
647 | _set_gpio_irqenable(bank, gpio, 0); | 651 | omap_set_gpio_irqenable(bank, gpio, 0); |
648 | _clear_gpio_irqstatus(bank, gpio); | 652 | omap_clear_gpio_irqstatus(bank, gpio); |
649 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); | 653 | omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
650 | _clear_gpio_debounce(bank, gpio); | 654 | omap_clear_gpio_debounce(bank, gpio); |
651 | } | 655 | } |
652 | 656 | ||
653 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ | 657 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
654 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) | 658 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
655 | { | 659 | { |
656 | struct gpio_bank *bank = _irq_data_get_bank(d); | 660 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
657 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); | 661 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); |
658 | 662 | ||
659 | return _set_gpio_wakeup(bank, gpio, enable); | 663 | return omap_set_gpio_wakeup(bank, gpio, enable); |
660 | } | 664 | } |
661 | 665 | ||
662 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) | 666 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
@@ -677,8 +681,8 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) | |||
677 | * not already been requested. | 681 | * not already been requested. |
678 | */ | 682 | */ |
679 | if (!LINE_USED(bank->irq_usage, offset)) { | 683 | if (!LINE_USED(bank->irq_usage, offset)) { |
680 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | 684 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
681 | _enable_gpio_module(bank, offset); | 685 | omap_enable_gpio_module(bank, offset); |
682 | } | 686 | } |
683 | bank->mod_usage |= BIT(offset); | 687 | bank->mod_usage |= BIT(offset); |
684 | spin_unlock_irqrestore(&bank->lock, flags); | 688 | spin_unlock_irqrestore(&bank->lock, flags); |
@@ -693,8 +697,8 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |||
693 | 697 | ||
694 | spin_lock_irqsave(&bank->lock, flags); | 698 | spin_lock_irqsave(&bank->lock, flags); |
695 | bank->mod_usage &= ~(BIT(offset)); | 699 | bank->mod_usage &= ~(BIT(offset)); |
696 | _disable_gpio_module(bank, offset); | 700 | omap_disable_gpio_module(bank, offset); |
697 | _reset_gpio(bank, bank->chip.base + offset); | 701 | omap_reset_gpio(bank, bank->chip.base + offset); |
698 | spin_unlock_irqrestore(&bank->lock, flags); | 702 | spin_unlock_irqrestore(&bank->lock, flags); |
699 | 703 | ||
700 | /* | 704 | /* |
@@ -714,7 +718,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |||
714 | * line's interrupt handler has been run, we may miss some nested | 718 | * line's interrupt handler has been run, we may miss some nested |
715 | * interrupts. | 719 | * interrupts. |
716 | */ | 720 | */ |
717 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 721 | static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
718 | { | 722 | { |
719 | void __iomem *isr_reg = NULL; | 723 | void __iomem *isr_reg = NULL; |
720 | u32 isr; | 724 | u32 isr; |
@@ -737,7 +741,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
737 | u32 isr_saved, level_mask = 0; | 741 | u32 isr_saved, level_mask = 0; |
738 | u32 enabled; | 742 | u32 enabled; |
739 | 743 | ||
740 | enabled = _get_gpio_irqbank_mask(bank); | 744 | enabled = omap_get_gpio_irqbank_mask(bank); |
741 | isr_saved = isr = readl_relaxed(isr_reg) & enabled; | 745 | isr_saved = isr = readl_relaxed(isr_reg) & enabled; |
742 | 746 | ||
743 | if (bank->level_mask) | 747 | if (bank->level_mask) |
@@ -746,9 +750,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
746 | /* clear edge sensitive interrupts before handler(s) are | 750 | /* clear edge sensitive interrupts before handler(s) are |
747 | called so that we don't miss any interrupt occurred while | 751 | called so that we don't miss any interrupt occurred while |
748 | executing them */ | 752 | executing them */ |
749 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); | 753 | omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
750 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | 754 | omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
751 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); | 755 | omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
752 | 756 | ||
753 | /* if there is only edge sensitive GPIO pin interrupts | 757 | /* if there is only edge sensitive GPIO pin interrupts |
754 | configured, we could unmask GPIO bank interrupt immediately */ | 758 | configured, we could unmask GPIO bank interrupt immediately */ |
@@ -772,7 +776,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
772 | * This will be indicated in the bank toggle_mask. | 776 | * This will be indicated in the bank toggle_mask. |
773 | */ | 777 | */ |
774 | if (bank->toggle_mask & (BIT(bit))) | 778 | if (bank->toggle_mask & (BIT(bit))) |
775 | _toggle_gpio_edge_triggering(bank, bit); | 779 | omap_toggle_gpio_edge_triggering(bank, bit); |
776 | 780 | ||
777 | generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, | 781 | generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, |
778 | bit)); | 782 | bit)); |
@@ -788,18 +792,18 @@ exit: | |||
788 | pm_runtime_put(bank->dev); | 792 | pm_runtime_put(bank->dev); |
789 | } | 793 | } |
790 | 794 | ||
791 | static void gpio_irq_shutdown(struct irq_data *d) | 795 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
792 | { | 796 | { |
793 | struct gpio_bank *bank = _irq_data_get_bank(d); | 797 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
794 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); | 798 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); |
795 | unsigned long flags; | 799 | unsigned long flags; |
796 | unsigned offset = GPIO_INDEX(bank, gpio); | 800 | unsigned offset = GPIO_INDEX(bank, gpio); |
797 | 801 | ||
798 | spin_lock_irqsave(&bank->lock, flags); | 802 | spin_lock_irqsave(&bank->lock, flags); |
799 | gpio_unlock_as_irq(&bank->chip, offset); | 803 | gpio_unlock_as_irq(&bank->chip, offset); |
800 | bank->irq_usage &= ~(BIT(offset)); | 804 | bank->irq_usage &= ~(BIT(offset)); |
801 | _disable_gpio_module(bank, offset); | 805 | omap_disable_gpio_module(bank, offset); |
802 | _reset_gpio(bank, gpio); | 806 | omap_reset_gpio(bank, gpio); |
803 | spin_unlock_irqrestore(&bank->lock, flags); | 807 | spin_unlock_irqrestore(&bank->lock, flags); |
804 | 808 | ||
805 | /* | 809 | /* |
@@ -810,57 +814,57 @@ static void gpio_irq_shutdown(struct irq_data *d) | |||
810 | pm_runtime_put(bank->dev); | 814 | pm_runtime_put(bank->dev); |
811 | } | 815 | } |
812 | 816 | ||
813 | static void gpio_ack_irq(struct irq_data *d) | 817 | static void omap_gpio_ack_irq(struct irq_data *d) |
814 | { | 818 | { |
815 | struct gpio_bank *bank = _irq_data_get_bank(d); | 819 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
816 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); | 820 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); |
817 | 821 | ||
818 | _clear_gpio_irqstatus(bank, gpio); | 822 | omap_clear_gpio_irqstatus(bank, gpio); |
819 | } | 823 | } |
820 | 824 | ||
821 | static void gpio_mask_irq(struct irq_data *d) | 825 | static void omap_gpio_mask_irq(struct irq_data *d) |
822 | { | 826 | { |
823 | struct gpio_bank *bank = _irq_data_get_bank(d); | 827 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
824 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); | 828 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); |
825 | unsigned long flags; | 829 | unsigned long flags; |
826 | 830 | ||
827 | spin_lock_irqsave(&bank->lock, flags); | 831 | spin_lock_irqsave(&bank->lock, flags); |
828 | _set_gpio_irqenable(bank, gpio, 0); | 832 | omap_set_gpio_irqenable(bank, gpio, 0); |
829 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); | 833 | omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
830 | spin_unlock_irqrestore(&bank->lock, flags); | 834 | spin_unlock_irqrestore(&bank->lock, flags); |
831 | } | 835 | } |
832 | 836 | ||
833 | static void gpio_unmask_irq(struct irq_data *d) | 837 | static void omap_gpio_unmask_irq(struct irq_data *d) |
834 | { | 838 | { |
835 | struct gpio_bank *bank = _irq_data_get_bank(d); | 839 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
836 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); | 840 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); |
837 | unsigned int irq_mask = GPIO_BIT(bank, gpio); | 841 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
838 | u32 trigger = irqd_get_trigger_type(d); | 842 | u32 trigger = irqd_get_trigger_type(d); |
839 | unsigned long flags; | 843 | unsigned long flags; |
840 | 844 | ||
841 | spin_lock_irqsave(&bank->lock, flags); | 845 | spin_lock_irqsave(&bank->lock, flags); |
842 | if (trigger) | 846 | if (trigger) |
843 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); | 847 | omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
844 | 848 | ||
845 | /* For level-triggered GPIOs, the clearing must be done after | 849 | /* For level-triggered GPIOs, the clearing must be done after |
846 | * the HW source is cleared, thus after the handler has run */ | 850 | * the HW source is cleared, thus after the handler has run */ |
847 | if (bank->level_mask & irq_mask) { | 851 | if (bank->level_mask & irq_mask) { |
848 | _set_gpio_irqenable(bank, gpio, 0); | 852 | omap_set_gpio_irqenable(bank, gpio, 0); |
849 | _clear_gpio_irqstatus(bank, gpio); | 853 | omap_clear_gpio_irqstatus(bank, gpio); |
850 | } | 854 | } |
851 | 855 | ||
852 | _set_gpio_irqenable(bank, gpio, 1); | 856 | omap_set_gpio_irqenable(bank, gpio, 1); |
853 | spin_unlock_irqrestore(&bank->lock, flags); | 857 | spin_unlock_irqrestore(&bank->lock, flags); |
854 | } | 858 | } |
855 | 859 | ||
856 | static struct irq_chip gpio_irq_chip = { | 860 | static struct irq_chip gpio_irq_chip = { |
857 | .name = "GPIO", | 861 | .name = "GPIO", |
858 | .irq_shutdown = gpio_irq_shutdown, | 862 | .irq_shutdown = omap_gpio_irq_shutdown, |
859 | .irq_ack = gpio_ack_irq, | 863 | .irq_ack = omap_gpio_ack_irq, |
860 | .irq_mask = gpio_mask_irq, | 864 | .irq_mask = omap_gpio_mask_irq, |
861 | .irq_unmask = gpio_unmask_irq, | 865 | .irq_unmask = omap_gpio_unmask_irq, |
862 | .irq_set_type = gpio_irq_type, | 866 | .irq_set_type = omap_gpio_irq_type, |
863 | .irq_set_wake = gpio_wake_enable, | 867 | .irq_set_wake = omap_gpio_wake_enable, |
864 | }; | 868 | }; |
865 | 869 | ||
866 | /*---------------------------------------------------------------------*/ | 870 | /*---------------------------------------------------------------------*/ |
@@ -917,7 +921,7 @@ static struct platform_device omap_mpuio_device = { | |||
917 | /* could list the /proc/iomem resources */ | 921 | /* could list the /proc/iomem resources */ |
918 | }; | 922 | }; |
919 | 923 | ||
920 | static inline void mpuio_init(struct gpio_bank *bank) | 924 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
921 | { | 925 | { |
922 | platform_set_drvdata(&omap_mpuio_device, bank); | 926 | platform_set_drvdata(&omap_mpuio_device, bank); |
923 | 927 | ||
@@ -927,7 +931,7 @@ static inline void mpuio_init(struct gpio_bank *bank) | |||
927 | 931 | ||
928 | /*---------------------------------------------------------------------*/ | 932 | /*---------------------------------------------------------------------*/ |
929 | 933 | ||
930 | static int gpio_get_direction(struct gpio_chip *chip, unsigned offset) | 934 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
931 | { | 935 | { |
932 | struct gpio_bank *bank; | 936 | struct gpio_bank *bank; |
933 | unsigned long flags; | 937 | unsigned long flags; |
@@ -942,19 +946,19 @@ static int gpio_get_direction(struct gpio_chip *chip, unsigned offset) | |||
942 | return dir; | 946 | return dir; |
943 | } | 947 | } |
944 | 948 | ||
945 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | 949 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
946 | { | 950 | { |
947 | struct gpio_bank *bank; | 951 | struct gpio_bank *bank; |
948 | unsigned long flags; | 952 | unsigned long flags; |
949 | 953 | ||
950 | bank = container_of(chip, struct gpio_bank, chip); | 954 | bank = container_of(chip, struct gpio_bank, chip); |
951 | spin_lock_irqsave(&bank->lock, flags); | 955 | spin_lock_irqsave(&bank->lock, flags); |
952 | _set_gpio_direction(bank, offset, 1); | 956 | omap_set_gpio_direction(bank, offset, 1); |
953 | spin_unlock_irqrestore(&bank->lock, flags); | 957 | spin_unlock_irqrestore(&bank->lock, flags); |
954 | return 0; | 958 | return 0; |
955 | } | 959 | } |
956 | 960 | ||
957 | static int gpio_get(struct gpio_chip *chip, unsigned offset) | 961 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
958 | { | 962 | { |
959 | struct gpio_bank *bank; | 963 | struct gpio_bank *bank; |
960 | u32 mask; | 964 | u32 mask; |
@@ -962,13 +966,13 @@ static int gpio_get(struct gpio_chip *chip, unsigned offset) | |||
962 | bank = container_of(chip, struct gpio_bank, chip); | 966 | bank = container_of(chip, struct gpio_bank, chip); |
963 | mask = (BIT(offset)); | 967 | mask = (BIT(offset)); |
964 | 968 | ||
965 | if (gpio_is_input(bank, mask)) | 969 | if (omap_gpio_is_input(bank, mask)) |
966 | return _get_gpio_datain(bank, offset); | 970 | return omap_get_gpio_datain(bank, offset); |
967 | else | 971 | else |
968 | return _get_gpio_dataout(bank, offset); | 972 | return omap_get_gpio_dataout(bank, offset); |
969 | } | 973 | } |
970 | 974 | ||
971 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | 975 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
972 | { | 976 | { |
973 | struct gpio_bank *bank; | 977 | struct gpio_bank *bank; |
974 | unsigned long flags; | 978 | unsigned long flags; |
@@ -976,13 +980,13 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |||
976 | bank = container_of(chip, struct gpio_bank, chip); | 980 | bank = container_of(chip, struct gpio_bank, chip); |
977 | spin_lock_irqsave(&bank->lock, flags); | 981 | spin_lock_irqsave(&bank->lock, flags); |
978 | bank->set_dataout(bank, offset, value); | 982 | bank->set_dataout(bank, offset, value); |
979 | _set_gpio_direction(bank, offset, 0); | 983 | omap_set_gpio_direction(bank, offset, 0); |
980 | spin_unlock_irqrestore(&bank->lock, flags); | 984 | spin_unlock_irqrestore(&bank->lock, flags); |
981 | return 0; | 985 | return 0; |
982 | } | 986 | } |
983 | 987 | ||
984 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, | 988 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
985 | unsigned debounce) | 989 | unsigned debounce) |
986 | { | 990 | { |
987 | struct gpio_bank *bank; | 991 | struct gpio_bank *bank; |
988 | unsigned long flags; | 992 | unsigned long flags; |
@@ -990,13 +994,13 @@ static int gpio_debounce(struct gpio_chip *chip, unsigned offset, | |||
990 | bank = container_of(chip, struct gpio_bank, chip); | 994 | bank = container_of(chip, struct gpio_bank, chip); |
991 | 995 | ||
992 | spin_lock_irqsave(&bank->lock, flags); | 996 | spin_lock_irqsave(&bank->lock, flags); |
993 | _set_gpio_debounce(bank, offset, debounce); | 997 | omap2_set_gpio_debounce(bank, offset, debounce); |
994 | spin_unlock_irqrestore(&bank->lock, flags); | 998 | spin_unlock_irqrestore(&bank->lock, flags); |
995 | 999 | ||
996 | return 0; | 1000 | return 0; |
997 | } | 1001 | } |
998 | 1002 | ||
999 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | 1003 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
1000 | { | 1004 | { |
1001 | struct gpio_bank *bank; | 1005 | struct gpio_bank *bank; |
1002 | unsigned long flags; | 1006 | unsigned long flags; |
@@ -1037,8 +1041,10 @@ static void omap_gpio_mod_init(struct gpio_bank *bank) | |||
1037 | return; | 1041 | return; |
1038 | } | 1042 | } |
1039 | 1043 | ||
1040 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | 1044 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1041 | _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv); | 1045 | bank->regs->irqenable_inv); |
1046 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | ||
1047 | !bank->regs->irqenable_inv); | ||
1042 | if (bank->regs->debounce_en) | 1048 | if (bank->regs->debounce_en) |
1043 | writel_relaxed(0, base + bank->regs->debounce_en); | 1049 | writel_relaxed(0, base + bank->regs->debounce_en); |
1044 | 1050 | ||
@@ -1072,10 +1078,10 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, | |||
1072 | /* NOTE: No ack required, reading IRQ status clears it. */ | 1078 | /* NOTE: No ack required, reading IRQ status clears it. */ |
1073 | ct->chip.irq_mask = irq_gc_mask_set_bit; | 1079 | ct->chip.irq_mask = irq_gc_mask_set_bit; |
1074 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | 1080 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; |
1075 | ct->chip.irq_set_type = gpio_irq_type; | 1081 | ct->chip.irq_set_type = omap_gpio_irq_type; |
1076 | 1082 | ||
1077 | if (bank->regs->wkup_en) | 1083 | if (bank->regs->wkup_en) |
1078 | ct->chip.irq_set_wake = gpio_wake_enable; | 1084 | ct->chip.irq_set_wake = omap_gpio_wake_enable; |
1079 | 1085 | ||
1080 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | 1086 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; |
1081 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | 1087 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, |
@@ -1095,12 +1101,12 @@ static int omap_gpio_chip_init(struct gpio_bank *bank) | |||
1095 | */ | 1101 | */ |
1096 | bank->chip.request = omap_gpio_request; | 1102 | bank->chip.request = omap_gpio_request; |
1097 | bank->chip.free = omap_gpio_free; | 1103 | bank->chip.free = omap_gpio_free; |
1098 | bank->chip.get_direction = gpio_get_direction; | 1104 | bank->chip.get_direction = omap_gpio_get_direction; |
1099 | bank->chip.direction_input = gpio_input; | 1105 | bank->chip.direction_input = omap_gpio_input; |
1100 | bank->chip.get = gpio_get; | 1106 | bank->chip.get = omap_gpio_get; |
1101 | bank->chip.direction_output = gpio_output; | 1107 | bank->chip.direction_output = omap_gpio_output; |
1102 | bank->chip.set_debounce = gpio_debounce; | 1108 | bank->chip.set_debounce = omap_gpio_debounce; |
1103 | bank->chip.set = gpio_set; | 1109 | bank->chip.set = omap_gpio_set; |
1104 | if (bank->is_mpuio) { | 1110 | if (bank->is_mpuio) { |
1105 | bank->chip.label = "mpuio"; | 1111 | bank->chip.label = "mpuio"; |
1106 | if (bank->regs->wkup_en) | 1112 | if (bank->regs->wkup_en) |
@@ -1132,7 +1138,7 @@ static int omap_gpio_chip_init(struct gpio_bank *bank) | |||
1132 | #endif | 1138 | #endif |
1133 | 1139 | ||
1134 | ret = gpiochip_irqchip_add(&bank->chip, &gpio_irq_chip, | 1140 | ret = gpiochip_irqchip_add(&bank->chip, &gpio_irq_chip, |
1135 | irq_base, gpio_irq_handler, | 1141 | irq_base, omap_gpio_irq_handler, |
1136 | IRQ_TYPE_NONE); | 1142 | IRQ_TYPE_NONE); |
1137 | 1143 | ||
1138 | if (ret) { | 1144 | if (ret) { |
@@ -1142,7 +1148,7 @@ static int omap_gpio_chip_init(struct gpio_bank *bank) | |||
1142 | } | 1148 | } |
1143 | 1149 | ||
1144 | gpiochip_set_chained_irqchip(&bank->chip, &gpio_irq_chip, | 1150 | gpiochip_set_chained_irqchip(&bank->chip, &gpio_irq_chip, |
1145 | bank->irq, gpio_irq_handler); | 1151 | bank->irq, omap_gpio_irq_handler); |
1146 | 1152 | ||
1147 | for (j = 0; j < bank->width; j++) { | 1153 | for (j = 0; j < bank->width; j++) { |
1148 | int irq = irq_find_mapping(bank->chip.irqdomain, j); | 1154 | int irq = irq_find_mapping(bank->chip.irqdomain, j); |
@@ -1210,9 +1216,9 @@ static int omap_gpio_probe(struct platform_device *pdev) | |||
1210 | } | 1216 | } |
1211 | 1217 | ||
1212 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | 1218 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
1213 | bank->set_dataout = _set_gpio_dataout_reg; | 1219 | bank->set_dataout = omap_set_gpio_dataout_reg; |
1214 | else | 1220 | else |
1215 | bank->set_dataout = _set_gpio_dataout_mask; | 1221 | bank->set_dataout = omap_set_gpio_dataout_mask; |
1216 | 1222 | ||
1217 | spin_lock_init(&bank->lock); | 1223 | spin_lock_init(&bank->lock); |
1218 | 1224 | ||
@@ -1231,7 +1237,7 @@ static int omap_gpio_probe(struct platform_device *pdev) | |||
1231 | pm_runtime_get_sync(bank->dev); | 1237 | pm_runtime_get_sync(bank->dev); |
1232 | 1238 | ||
1233 | if (bank->is_mpuio) | 1239 | if (bank->is_mpuio) |
1234 | mpuio_init(bank); | 1240 | omap_mpuio_init(bank); |
1235 | 1241 | ||
1236 | omap_gpio_mod_init(bank); | 1242 | omap_gpio_mod_init(bank); |
1237 | 1243 | ||
@@ -1313,7 +1319,7 @@ update_gpio_context_count: | |||
1313 | bank->context_loss_count = | 1319 | bank->context_loss_count = |
1314 | bank->get_context_loss_count(bank->dev); | 1320 | bank->get_context_loss_count(bank->dev); |
1315 | 1321 | ||
1316 | _gpio_dbck_disable(bank); | 1322 | omap_gpio_dbck_disable(bank); |
1317 | spin_unlock_irqrestore(&bank->lock, flags); | 1323 | spin_unlock_irqrestore(&bank->lock, flags); |
1318 | 1324 | ||
1319 | return 0; | 1325 | return 0; |
@@ -1344,7 +1350,7 @@ static int omap_gpio_runtime_resume(struct device *dev) | |||
1344 | bank->get_context_loss_count(bank->dev); | 1350 | bank->get_context_loss_count(bank->dev); |
1345 | } | 1351 | } |
1346 | 1352 | ||
1347 | _gpio_dbck_enable(bank); | 1353 | omap_gpio_dbck_enable(bank); |
1348 | 1354 | ||
1349 | /* | 1355 | /* |
1350 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | 1356 | * In ->runtime_suspend(), level-triggered, wakeup-enabled |