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authorHante Meuleman <meuleman@broadcom.com>2014-07-30 07:20:04 -0400
committerJohn W. Linville <linville@tuxdriver.com>2014-07-31 13:45:26 -0400
commit9e37f045d5e7f33450515f237c2f6f6bfee137dd (patch)
tree2be1781642b4c9d4df1a0a2fb78429fd0cc418f7
parent9a1bb60250d2b6b546a62e5b73f55c4f1d22016b (diff)
brcmfmac: Adding PCIe bus layer support.
This patch will add PCIe support. With this patch the PCIe chipsets 43602, 4354, 4356, 43567, and 43570 will be supported. Reviewed-by: Arend Van Spriel <arend@broadcom.com> Reviewed-by: Franky (Zhenhui) Lin <frankyl@broadcom.com> Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Daniel (Deognyoun) Kim <dekim@broadcom.com> Signed-off-by: Hante Meuleman <meuleman@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/brcm80211/Kconfig10
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/Makefile2
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/chip.c8
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h1
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h1
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c7
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/pcie.c1811
-rw-r--r--drivers/net/wireless/brcm80211/brcmfmac/pcie.h29
-rw-r--r--drivers/net/wireless/brcm80211/include/brcm_hw_ids.h11
9 files changed, 1880 insertions, 0 deletions
diff --git a/drivers/net/wireless/brcm80211/Kconfig b/drivers/net/wireless/brcm80211/Kconfig
index fcfed6b99a62..b8e2561ea645 100644
--- a/drivers/net/wireless/brcm80211/Kconfig
+++ b/drivers/net/wireless/brcm80211/Kconfig
@@ -48,6 +48,16 @@ config BRCMFMAC_USB
48 IEEE802.11n embedded FullMAC WLAN driver. Say Y if you want to 48 IEEE802.11n embedded FullMAC WLAN driver. Say Y if you want to
49 use the driver for an USB wireless card. 49 use the driver for an USB wireless card.
50 50
51config BRCMFMAC_PCIE
52 bool "PCIE bus interface support for FullMAC driver"
53 depends on BRCMFMAC
54 depends on PCI
55 select FW_LOADER
56 ---help---
57 This option enables the PCIE bus interface support for Broadcom
58 IEEE802.11ac embedded FullMAC WLAN driver. Say Y if you want to
59 use the driver for an PCIE wireless card.
60
51config BRCM_TRACING 61config BRCM_TRACING
52 bool "Broadcom device tracing" 62 bool "Broadcom device tracing"
53 depends on BRCMSMAC || BRCMFMAC 63 depends on BRCMSMAC || BRCMFMAC
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/Makefile b/drivers/net/wireless/brcm80211/brcmfmac/Makefile
index 0447a47fe237..c35adf4bc70b 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/Makefile
+++ b/drivers/net/wireless/brcm80211/brcmfmac/Makefile
@@ -45,6 +45,8 @@ brcmfmac-$(CONFIG_BRCMFMAC_SDIO) += \
45 bcmsdh.o 45 bcmsdh.o
46brcmfmac-$(CONFIG_BRCMFMAC_USB) += \ 46brcmfmac-$(CONFIG_BRCMFMAC_USB) += \
47 usb.o 47 usb.o
48brcmfmac-$(CONFIG_BRCMFMAC_PCIE) += \
49 pcie.o
48brcmfmac-$(CONFIG_BRCMDBG) += \ 50brcmfmac-$(CONFIG_BRCMDBG) += \
49 dhd_dbg.o 51 dhd_dbg.o
50brcmfmac-$(CONFIG_BRCM_TRACING) += \ 52brcmfmac-$(CONFIG_BRCM_TRACING) += \
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/chip.c b/drivers/net/wireless/brcm80211/brcmfmac/chip.c
index 96800db0536b..95efde868db8 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/chip.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/chip.c
@@ -506,9 +506,17 @@ static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
506 break; 506 break;
507 case BRCM_CC_4339_CHIP_ID: 507 case BRCM_CC_4339_CHIP_ID:
508 case BRCM_CC_4354_CHIP_ID: 508 case BRCM_CC_4354_CHIP_ID:
509 case BRCM_CC_4356_CHIP_ID:
510 case BRCM_CC_43567_CHIP_ID:
511 case BRCM_CC_43569_CHIP_ID:
512 case BRCM_CC_43570_CHIP_ID:
509 ci->pub.ramsize = 0xc0000; 513 ci->pub.ramsize = 0xc0000;
510 ci->pub.rambase = 0x180000; 514 ci->pub.rambase = 0x180000;
511 break; 515 break;
516 case BRCM_CC_43602_CHIP_ID:
517 ci->pub.ramsize = 0xf0000;
518 ci->pub.rambase = 0x180000;
519 break;
512 default: 520 default:
513 brcmf_err("unknown chip: %s\n", ci->pub.name); 521 brcmf_err("unknown chip: %s\n", ci->pub.name);
514 break; 522 break;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h b/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h
index 4053368eb743..3122b86050a1 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h
@@ -120,6 +120,7 @@ struct brcmf_bus {
120 union { 120 union {
121 struct brcmf_sdio_dev *sdio; 121 struct brcmf_sdio_dev *sdio;
122 struct brcmf_usbdev *usb; 122 struct brcmf_usbdev *usb;
123 struct brcmf_pciedev *pcie;
123 } bus_priv; 124 } bus_priv;
124 enum brcmf_bus_protocol_type proto_type; 125 enum brcmf_bus_protocol_type proto_type;
125 struct device *dev; 126 struct device *dev;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h b/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h
index 6804eeca7688..dec40d316c82 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h
@@ -36,6 +36,7 @@
36#define BRCMF_BCDC_VAL 0x00010000 36#define BRCMF_BCDC_VAL 0x00010000
37#define BRCMF_SDIO_VAL 0x00020000 37#define BRCMF_SDIO_VAL 0x00020000
38#define BRCMF_MSGBUF_VAL 0x00040000 38#define BRCMF_MSGBUF_VAL 0x00040000
39#define BRCMF_PCIE_VAL 0x00080000
39 40
40/* set default print format */ 41/* set default print format */
41#undef pr_fmt 42#undef pr_fmt
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
index 7e14e5fa4744..b456bcb7f916 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
@@ -32,6 +32,7 @@
32#include "fwsignal.h" 32#include "fwsignal.h"
33#include "feature.h" 33#include "feature.h"
34#include "proto.h" 34#include "proto.h"
35#include "pcie.h"
35 36
36MODULE_AUTHOR("Broadcom Corporation"); 37MODULE_AUTHOR("Broadcom Corporation");
37MODULE_DESCRIPTION("Broadcom 802.11 wireless LAN fullmac driver."); 38MODULE_DESCRIPTION("Broadcom 802.11 wireless LAN fullmac driver.");
@@ -1084,6 +1085,9 @@ static void brcmf_driver_register(struct work_struct *work)
1084#ifdef CONFIG_BRCMFMAC_USB 1085#ifdef CONFIG_BRCMFMAC_USB
1085 brcmf_usb_register(); 1086 brcmf_usb_register();
1086#endif 1087#endif
1088#ifdef CONFIG_BRCMFMAC_PCIE
1089 brcmf_pcie_register();
1090#endif
1087} 1091}
1088static DECLARE_WORK(brcmf_driver_work, brcmf_driver_register); 1092static DECLARE_WORK(brcmf_driver_work, brcmf_driver_register);
1089 1093
@@ -1109,6 +1113,9 @@ static void __exit brcmfmac_module_exit(void)
1109#ifdef CONFIG_BRCMFMAC_USB 1113#ifdef CONFIG_BRCMFMAC_USB
1110 brcmf_usb_exit(); 1114 brcmf_usb_exit();
1111#endif 1115#endif
1116#ifdef CONFIG_BRCMFMAC_PCIE
1117 brcmf_pcie_exit();
1118#endif
1112 brcmf_debugfs_exit(); 1119 brcmf_debugfs_exit();
1113} 1120}
1114 1121
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/brcm80211/brcmfmac/pcie.c
new file mode 100644
index 000000000000..89be96d3b6e9
--- /dev/null
+++ b/drivers/net/wireless/brcm80211/brcmfmac/pcie.c
@@ -0,0 +1,1811 @@
1/* Copyright (c) 2014 Broadcom Corporation
2 *
3 * Permission to use, copy, modify, and/or distribute this software for any
4 * purpose with or without fee is hereby granted, provided that the above
5 * copyright notice and this permission notice appear in all copies.
6 *
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/firmware.h>
19#include <linux/pci.h>
20#include <linux/vmalloc.h>
21#include <linux/delay.h>
22#include <linux/unaligned/access_ok.h>
23#include <linux/interrupt.h>
24#include <linux/bcma/bcma.h>
25#include <linux/sched.h>
26
27#include <soc.h>
28#include <chipcommon.h>
29#include <brcmu_utils.h>
30#include <brcmu_wifi.h>
31#include <brcm_hw_ids.h>
32
33#include "dhd_dbg.h"
34#include "dhd_bus.h"
35#include "commonring.h"
36#include "msgbuf.h"
37#include "pcie.h"
38#include "firmware.h"
39#include "chip.h"
40
41
42enum brcmf_pcie_state {
43 BRCMFMAC_PCIE_STATE_DOWN,
44 BRCMFMAC_PCIE_STATE_UP
45};
46
47
48#define BRCMF_PCIE_43602_FW_NAME "brcm/brcmfmac43602-pcie.bin"
49#define BRCMF_PCIE_43602_NVRAM_NAME "brcm/brcmfmac43602-pcie.txt"
50#define BRCMF_PCIE_4354_FW_NAME "brcm/brcmfmac4354-pcie.bin"
51#define BRCMF_PCIE_4354_NVRAM_NAME "brcm/brcmfmac4354-pcie.txt"
52#define BRCMF_PCIE_4356_FW_NAME "brcm/brcmfmac4356-pcie.bin"
53#define BRCMF_PCIE_4356_NVRAM_NAME "brcm/brcmfmac4356-pcie.txt"
54#define BRCMF_PCIE_43570_FW_NAME "brcm/brcmfmac43570-pcie.bin"
55#define BRCMF_PCIE_43570_NVRAM_NAME "brcm/brcmfmac43570-pcie.txt"
56
57#define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */
58
59#define BRCMF_PCIE_TCM_MAP_SIZE (4096 * 1024)
60#define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
61
62/* backplane addres space accessed by BAR0 */
63#define BRCMF_PCIE_BAR0_WINDOW 0x80
64#define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
65#define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
66
67#define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
68#define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
69
70#define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
71#define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
72
73#define BRCMF_PCIE_REG_INTSTATUS 0x90
74#define BRCMF_PCIE_REG_INTMASK 0x94
75#define BRCMF_PCIE_REG_SBMBX 0x98
76
77#define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
78#define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
79#define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
80#define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
81#define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
82#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140
83
84#define BRCMF_PCIE_GENREV1 1
85#define BRCMF_PCIE_GENREV2 2
86
87#define BRCMF_PCIE2_INTA 0x01
88#define BRCMF_PCIE2_INTB 0x02
89
90#define BRCMF_PCIE_INT_0 0x01
91#define BRCMF_PCIE_INT_1 0x02
92#define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
93 BRCMF_PCIE_INT_1)
94
95#define BRCMF_PCIE_MB_INT_FN0_0 0x0100
96#define BRCMF_PCIE_MB_INT_FN0_1 0x0200
97#define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
98#define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
99#define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
100#define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
101#define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
102#define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
103#define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
104#define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
105
106#define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
107 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
108 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
109 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
110 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
111 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
112 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
113 BRCMF_PCIE_MB_INT_D2H3_DB1)
114
115#define BRCMF_PCIE_MIN_SHARED_VERSION 4
116#define BRCMF_PCIE_MAX_SHARED_VERSION 5
117#define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
118#define BRCMF_PCIE_SHARED_TXPUSH_SUPPORT 0x4000
119
120#define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
121#define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
122
123#define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
124#define BRCMF_SHARED_RING_BASE_OFFSET 52
125#define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
126#define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
127#define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
128#define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
129#define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
130#define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
131#define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
132#define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
133#define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
134
135#define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
136#define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
137#define BRCMF_RING_H2D_RING_MEM_OFFSET 4
138#define BRCMF_RING_H2D_RING_STATE_OFFSET 8
139
140#define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
141#define BRCMF_RING_MAX_ITEM_OFFSET 4
142#define BRCMF_RING_LEN_ITEMS_OFFSET 6
143#define BRCMF_RING_MEM_SZ 16
144#define BRCMF_RING_STATE_SZ 8
145
146#define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET 4
147#define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8
148#define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12
149#define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16
150#define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0
151#define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52
152
153#define BRCMF_DEF_MAX_RXBUFPOST 255
154
155#define BRCMF_CONSOLE_BUFADDR_OFFSET 8
156#define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
157#define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
158
159#define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
160#define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
161
162#define BRCMF_D2H_DEV_D3_ACK 0x00000001
163#define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
164#define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
165
166#define BRCMF_H2D_HOST_D3_INFORM 0x00000001
167#define BRCMF_H2D_HOST_DS_ACK 0x00000002
168
169#define BRCMF_PCIE_MBDATA_TIMEOUT 2000
170
171
172MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
173MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
174MODULE_FIRMWARE(BRCMF_PCIE_4354_FW_NAME);
175MODULE_FIRMWARE(BRCMF_PCIE_4354_NVRAM_NAME);
176MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
177MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
178
179
180struct brcmf_pcie_console {
181 u32 base_addr;
182 u32 buf_addr;
183 u32 bufsize;
184 u32 read_idx;
185 u8 log_str[256];
186 u8 log_idx;
187};
188
189struct brcmf_pcie_shared_info {
190 u32 tcm_base_address;
191 u32 flags;
192 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
193 struct brcmf_pcie_ringbuf *flowrings;
194 u16 max_rxbufpost;
195 u32 nrof_flowrings;
196 u32 rx_dataoffset;
197 u32 htod_mb_data_addr;
198 u32 dtoh_mb_data_addr;
199 u32 ring_info_addr;
200 struct brcmf_pcie_console console;
201 void *scratch;
202 dma_addr_t scratch_dmahandle;
203 void *ringupd;
204 dma_addr_t ringupd_dmahandle;
205};
206
207struct brcmf_pcie_core_info {
208 u32 base;
209 u32 wrapbase;
210};
211
212struct brcmf_pciedev_info {
213 enum brcmf_pcie_state state;
214 bool in_irq;
215 bool irq_requested;
216 struct pci_dev *pdev;
217 char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
218 char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
219 void __iomem *regs;
220 void __iomem *tcm;
221 u32 tcm_size;
222 u32 ram_base;
223 u32 ram_size;
224 struct brcmf_chip *ci;
225 u32 coreid;
226 u32 generic_corerev;
227 struct brcmf_pcie_shared_info shared;
228 void (*ringbell)(struct brcmf_pciedev_info *devinfo);
229 wait_queue_head_t mbdata_resp_wait;
230 bool mbdata_completed;
231 bool irq_allocated;
232};
233
234struct brcmf_pcie_ringbuf {
235 struct brcmf_commonring commonring;
236 dma_addr_t dma_handle;
237 u32 w_idx_addr;
238 u32 r_idx_addr;
239 struct brcmf_pciedev_info *devinfo;
240 u8 id;
241};
242
243
244static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
245 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
246 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
247 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
248 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
249 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
250};
251
252static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
253 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
254 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
255 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
256 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
257 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
258};
259
260
261/* dma flushing needs implementation for mips and arm platforms. Should
262 * be put in util. Note, this is not real flushing. It is virtual non
263 * cached memory. Only write buffers should have to be drained. Though
264 * this may be different depending on platform......
265 */
266#define brcmf_dma_flush(addr, len)
267#define brcmf_dma_invalidate_cache(addr, len)
268
269
270static u32
271brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
272{
273 void __iomem *address = devinfo->regs + reg_offset;
274
275 return (ioread32(address));
276}
277
278
279static void
280brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
281 u32 value)
282{
283 void __iomem *address = devinfo->regs + reg_offset;
284
285 iowrite32(value, address);
286}
287
288
289static u8
290brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
291{
292 void __iomem *address = devinfo->tcm + mem_offset;
293
294 return (ioread8(address));
295}
296
297
298static u16
299brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
300{
301 void __iomem *address = devinfo->tcm + mem_offset;
302
303 return (ioread16(address));
304}
305
306
307static void
308brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
309 u16 value)
310{
311 void __iomem *address = devinfo->tcm + mem_offset;
312
313 iowrite16(value, address);
314}
315
316
317static u32
318brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
319{
320 void __iomem *address = devinfo->tcm + mem_offset;
321
322 return (ioread32(address));
323}
324
325
326static void
327brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
328 u32 value)
329{
330 void __iomem *address = devinfo->tcm + mem_offset;
331
332 iowrite32(value, address);
333}
334
335
336static u32
337brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
338{
339 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
340
341 return (ioread32(addr));
342}
343
344
345static void
346brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
347 u32 value)
348{
349 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
350
351 iowrite32(value, addr);
352}
353
354
355static void
356brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
357 void *srcaddr, u32 len)
358{
359 void __iomem *address = devinfo->tcm + mem_offset;
360 __le32 *src32;
361 __le16 *src16;
362 u8 *src8;
363
364 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
365 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
366 src8 = (u8 *)srcaddr;
367 while (len) {
368 iowrite8(*src8, address);
369 address++;
370 src8++;
371 len--;
372 }
373 } else {
374 len = len / 2;
375 src16 = (__le16 *)srcaddr;
376 while (len) {
377 iowrite16(le16_to_cpu(*src16), address);
378 address += 2;
379 src16++;
380 len--;
381 }
382 }
383 } else {
384 len = len / 4;
385 src32 = (__le32 *)srcaddr;
386 while (len) {
387 iowrite32(le32_to_cpu(*src32), address);
388 address += 4;
389 src32++;
390 len--;
391 }
392 }
393}
394
395
396#define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
397 CHIPCREGOFFS(reg), value)
398
399
400static void
401brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
402{
403 const struct pci_dev *pdev = devinfo->pdev;
404 struct brcmf_core *core;
405 u32 bar0_win;
406
407 core = brcmf_chip_get_core(devinfo->ci, coreid);
408 if (core) {
409 bar0_win = core->base;
410 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
411 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
412 &bar0_win) == 0) {
413 if (bar0_win != core->base) {
414 bar0_win = core->base;
415 pci_write_config_dword(pdev,
416 BRCMF_PCIE_BAR0_WINDOW,
417 bar0_win);
418 }
419 }
420 } else {
421 brcmf_err("Unsupported core selected %x\n", coreid);
422 }
423}
424
425
426static void brcmf_pcie_detach(struct brcmf_pciedev_info *devinfo)
427{
428 u16 cfg_offset[] = { 0x4, 0x4C, 0x58, 0x5C, 0x60, 0x64, 0xDC, 0x228,
429 0x248, 0x4e0, 0x4f4 };
430 u32 i;
431 u32 val;
432
433 if (!devinfo->ci)
434 return;
435
436 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
437 WRITECC32(devinfo, watchdog, 0x4e0);
438
439 msleep(100);
440
441 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
442 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
443 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
444 cfg_offset[i]);
445 val = brcmf_pcie_read_reg32(devinfo,
446 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
447 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
448 cfg_offset[i], val);
449 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA,
450 val);
451 }
452}
453
454
455static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
456{
457 u32 config;
458
459 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
460 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0)
461 brcmf_pcie_detach(devinfo);
462 /* BAR1 window may not be sized properly */
463 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
464 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
465 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
466 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
467
468 device_wakeup_enable(&devinfo->pdev->dev);
469}
470
471
472static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
473{
474 brcmf_chip_enter_download(devinfo->ci);
475
476 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
477 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
478 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
479 5);
480 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
481 0);
482 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
483 7);
484 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
485 0);
486 }
487 return 0;
488}
489
490
491static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
492 u32 resetintr)
493{
494 struct brcmf_core *core;
495
496 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
497 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
498 brcmf_chip_resetcore(core, 0, 0, 0);
499 }
500
501 return !brcmf_chip_exit_download(devinfo->ci, resetintr);
502}
503
504
505static void
506brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
507{
508 struct brcmf_pcie_shared_info *shared;
509 u32 addr;
510 u32 cur_htod_mb_data;
511 u32 i;
512
513 shared = &devinfo->shared;
514 addr = shared->htod_mb_data_addr;
515 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
516
517 if (cur_htod_mb_data != 0)
518 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
519 cur_htod_mb_data);
520
521 i = 0;
522 while (cur_htod_mb_data != 0) {
523 msleep(10);
524 i++;
525 if (i > 100)
526 break;
527 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
528 }
529
530 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
531 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
532 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
533}
534
535
536static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
537{
538 struct brcmf_pcie_shared_info *shared;
539 u32 addr;
540 u32 dtoh_mb_data;
541
542 shared = &devinfo->shared;
543 addr = shared->dtoh_mb_data_addr;
544 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
545
546 if (!dtoh_mb_data)
547 return;
548
549 brcmf_pcie_write_tcm32(devinfo, addr, 0);
550
551 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
552 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
553 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
554 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
555 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
556 }
557 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
558 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
559 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK)
560 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
561 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
562 devinfo->mbdata_completed = true;
563 wake_up(&devinfo->mbdata_resp_wait);
564 }
565}
566
567
568static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
569{
570 struct brcmf_pcie_shared_info *shared;
571 struct brcmf_pcie_console *console;
572 u32 addr;
573
574 shared = &devinfo->shared;
575 console = &shared->console;
576 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
577 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
578
579 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
580 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
581 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
582 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
583
584 brcmf_dbg(PCIE, "Console: base %x, buf %x, size %d\n",
585 console->base_addr, console->buf_addr, console->bufsize);
586}
587
588
589static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
590{
591 struct brcmf_pcie_console *console;
592 u32 addr;
593 u8 ch;
594 u32 newidx;
595
596 console = &devinfo->shared.console;
597 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
598 newidx = brcmf_pcie_read_tcm32(devinfo, addr);
599 while (newidx != console->read_idx) {
600 addr = console->buf_addr + console->read_idx;
601 ch = brcmf_pcie_read_tcm8(devinfo, addr);
602 console->read_idx++;
603 if (console->read_idx == console->bufsize)
604 console->read_idx = 0;
605 if (ch == '\r')
606 continue;
607 console->log_str[console->log_idx] = ch;
608 console->log_idx++;
609 if ((ch != '\n') &&
610 (console->log_idx == (sizeof(console->log_str) - 2))) {
611 ch = '\n';
612 console->log_str[console->log_idx] = ch;
613 console->log_idx++;
614 }
615
616 if (ch == '\n') {
617 console->log_str[console->log_idx] = 0;
618 brcmf_dbg(PCIE, "CONSOLE: %s\n", console->log_str);
619 console->log_idx = 0;
620 }
621 }
622}
623
624
625static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
626{
627 u32 reg_value;
628
629 brcmf_dbg(PCIE, "RING !\n");
630 reg_value = brcmf_pcie_read_reg32(devinfo,
631 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
632 reg_value |= BRCMF_PCIE2_INTB;
633 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
634 reg_value);
635}
636
637
638static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
639{
640 brcmf_dbg(PCIE, "RING !\n");
641 /* Any arbitrary value will do, lets use 1 */
642 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
643}
644
645
646static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
647{
648 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
649 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
650 0);
651 else
652 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
653 0);
654}
655
656
657static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
658{
659 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
660 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
661 BRCMF_PCIE_INT_DEF);
662 else
663 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
664 BRCMF_PCIE_MB_INT_D2H_DB |
665 BRCMF_PCIE_MB_INT_FN0_0 |
666 BRCMF_PCIE_MB_INT_FN0_1);
667}
668
669
670static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
671{
672 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
673 u32 status;
674
675 status = 0;
676 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
677 if (status) {
678 brcmf_pcie_intr_disable(devinfo);
679 brcmf_dbg(PCIE, "Enter\n");
680 return IRQ_WAKE_THREAD;
681 }
682 return IRQ_NONE;
683}
684
685
686static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
687{
688 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
689
690 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
691 brcmf_pcie_intr_disable(devinfo);
692 brcmf_dbg(PCIE, "Enter\n");
693 return IRQ_WAKE_THREAD;
694 }
695 return IRQ_NONE;
696}
697
698
699static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
700{
701 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
702 const struct pci_dev *pdev = devinfo->pdev;
703 u32 status;
704
705 devinfo->in_irq = true;
706 status = 0;
707 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
708 brcmf_dbg(PCIE, "Enter %x\n", status);
709 if (status) {
710 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
711 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
712 brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
713 }
714 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
715 brcmf_pcie_intr_enable(devinfo);
716 devinfo->in_irq = false;
717 return IRQ_HANDLED;
718}
719
720
721static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
722{
723 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
724 u32 status;
725
726 devinfo->in_irq = true;
727 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
728 brcmf_dbg(PCIE, "Enter %x\n", status);
729 if (status) {
730 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
731 status);
732 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
733 BRCMF_PCIE_MB_INT_FN0_1))
734 brcmf_pcie_handle_mb_data(devinfo);
735 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
736 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
737 brcmf_proto_msgbuf_rx_trigger(
738 &devinfo->pdev->dev);
739 }
740 }
741 brcmf_pcie_bus_console_read(devinfo);
742 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
743 brcmf_pcie_intr_enable(devinfo);
744 devinfo->in_irq = false;
745 return IRQ_HANDLED;
746}
747
748
749static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
750{
751 struct pci_dev *pdev;
752
753 pdev = devinfo->pdev;
754
755 brcmf_pcie_intr_disable(devinfo);
756
757 brcmf_dbg(PCIE, "Enter\n");
758 /* is it a v1 or v2 implementation */
759 devinfo->irq_requested = false;
760 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
761 if (request_threaded_irq(pdev->irq,
762 brcmf_pcie_quick_check_isr_v1,
763 brcmf_pcie_isr_thread_v1,
764 IRQF_SHARED, "brcmf_pcie_intr",
765 devinfo)) {
766 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
767 return -EIO;
768 }
769 } else {
770 if (request_threaded_irq(pdev->irq,
771 brcmf_pcie_quick_check_isr_v2,
772 brcmf_pcie_isr_thread_v2,
773 IRQF_SHARED, "brcmf_pcie_intr",
774 devinfo)) {
775 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
776 return -EIO;
777 }
778 }
779 devinfo->irq_requested = true;
780 devinfo->irq_allocated = true;
781 return 0;
782}
783
784
785static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
786{
787 struct pci_dev *pdev;
788 u32 status;
789 u32 count;
790
791 if (!devinfo->irq_allocated)
792 return;
793
794 pdev = devinfo->pdev;
795
796 brcmf_pcie_intr_disable(devinfo);
797 if (!devinfo->irq_requested)
798 return;
799 devinfo->irq_requested = false;
800 free_irq(pdev->irq, devinfo);
801
802 msleep(50);
803 count = 0;
804 while ((devinfo->in_irq) && (count < 20)) {
805 msleep(50);
806 count++;
807 }
808 if (devinfo->in_irq)
809 brcmf_err("Still in IRQ (processing) !!!\n");
810
811 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
812 status = 0;
813 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
814 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
815 } else {
816 status = brcmf_pcie_read_reg32(devinfo,
817 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
818 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
819 status);
820 }
821 devinfo->irq_allocated = false;
822}
823
824
825static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
826{
827 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
828 struct brcmf_pciedev_info *devinfo = ring->devinfo;
829 struct brcmf_commonring *commonring = &ring->commonring;
830
831 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
832 return -EIO;
833
834 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
835 commonring->w_ptr, ring->id);
836
837 brcmf_pcie_write_tcm16(devinfo, ring->r_idx_addr, commonring->r_ptr);
838
839 return 0;
840}
841
842
843static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
844{
845 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
846 struct brcmf_pciedev_info *devinfo = ring->devinfo;
847 struct brcmf_commonring *commonring = &ring->commonring;
848
849 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
850 return -EIO;
851
852 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
853 commonring->r_ptr, ring->id);
854
855 brcmf_pcie_write_tcm16(devinfo, ring->w_idx_addr, commonring->w_ptr);
856
857 return 0;
858}
859
860
861static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
862{
863 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
864 struct brcmf_pciedev_info *devinfo = ring->devinfo;
865
866 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
867 return -EIO;
868
869 devinfo->ringbell(devinfo);
870
871 return 0;
872}
873
874
875static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
876{
877 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
878 struct brcmf_pciedev_info *devinfo = ring->devinfo;
879 struct brcmf_commonring *commonring = &ring->commonring;
880
881 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
882 return -EIO;
883
884 commonring->r_ptr = brcmf_pcie_read_tcm16(devinfo, ring->r_idx_addr);
885
886 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
887 commonring->w_ptr, ring->id);
888
889 return 0;
890}
891
892
893static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
894{
895 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
896 struct brcmf_pciedev_info *devinfo = ring->devinfo;
897 struct brcmf_commonring *commonring = &ring->commonring;
898
899 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
900 return -EIO;
901
902 commonring->w_ptr = brcmf_pcie_read_tcm16(devinfo, ring->w_idx_addr);
903
904 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
905 commonring->r_ptr, ring->id);
906
907 return 0;
908}
909
910
911static void *
912brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
913 u32 size, u32 tcm_dma_phys_addr,
914 dma_addr_t *dma_handle)
915{
916 void *ring;
917 long long address;
918
919 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
920 GFP_KERNEL);
921 if (!ring)
922 return NULL;
923
924 address = (long long)(long)*dma_handle;
925 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
926 address & 0xffffffff);
927 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
928
929 memset(ring, 0, size);
930
931 return (ring);
932}
933
934
935static struct brcmf_pcie_ringbuf *
936brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
937 u32 tcm_ring_phys_addr)
938{
939 void *dma_buf;
940 dma_addr_t dma_handle;
941 struct brcmf_pcie_ringbuf *ring;
942 u32 size;
943 u32 addr;
944
945 size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
946 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
947 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
948 &dma_handle);
949 if (!dma_buf)
950 return NULL;
951
952 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
953 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
954 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
955 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
956
957 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
958 if (!ring) {
959 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
960 dma_handle);
961 return NULL;
962 }
963 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
964 brcmf_ring_itemsize[ring_id], dma_buf);
965 ring->dma_handle = dma_handle;
966 ring->devinfo = devinfo;
967 brcmf_commonring_register_cb(&ring->commonring,
968 brcmf_pcie_ring_mb_ring_bell,
969 brcmf_pcie_ring_mb_update_rptr,
970 brcmf_pcie_ring_mb_update_wptr,
971 brcmf_pcie_ring_mb_write_rptr,
972 brcmf_pcie_ring_mb_write_wptr, ring);
973
974 return (ring);
975}
976
977
978static void brcmf_pcie_release_ringbuffer(struct device *dev,
979 struct brcmf_pcie_ringbuf *ring)
980{
981 void *dma_buf;
982 u32 size;
983
984 if (!ring)
985 return;
986
987 dma_buf = ring->commonring.buf_addr;
988 if (dma_buf) {
989 size = ring->commonring.depth * ring->commonring.item_len;
990 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
991 }
992 kfree(ring);
993}
994
995
996static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
997{
998 u32 i;
999
1000 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1001 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1002 devinfo->shared.commonrings[i]);
1003 devinfo->shared.commonrings[i] = NULL;
1004 }
1005 kfree(devinfo->shared.flowrings);
1006 devinfo->shared.flowrings = NULL;
1007}
1008
1009
1010static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1011{
1012 struct brcmf_pcie_ringbuf *ring;
1013 struct brcmf_pcie_ringbuf *rings;
1014 u32 ring_addr;
1015 u32 d2h_w_idx_ptr;
1016 u32 d2h_r_idx_ptr;
1017 u32 h2d_w_idx_ptr;
1018 u32 h2d_r_idx_ptr;
1019 u32 addr;
1020 u32 ring_mem_ptr;
1021 u32 i;
1022 u16 max_sub_queues;
1023
1024 ring_addr = devinfo->shared.ring_info_addr;
1025 brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1026
1027 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1028 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1029 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1030 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1031 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1032 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1033 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1034 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1035
1036 addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1037 ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1038
1039 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1040 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1041 if (!ring)
1042 goto fail;
1043 ring->w_idx_addr = h2d_w_idx_ptr;
1044 ring->r_idx_addr = h2d_r_idx_ptr;
1045 ring->id = i;
1046 devinfo->shared.commonrings[i] = ring;
1047
1048 h2d_w_idx_ptr += sizeof(u32);
1049 h2d_r_idx_ptr += sizeof(u32);
1050 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1051 }
1052
1053 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1054 i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1055 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1056 if (!ring)
1057 goto fail;
1058 ring->w_idx_addr = d2h_w_idx_ptr;
1059 ring->r_idx_addr = d2h_r_idx_ptr;
1060 ring->id = i;
1061 devinfo->shared.commonrings[i] = ring;
1062
1063 d2h_w_idx_ptr += sizeof(u32);
1064 d2h_r_idx_ptr += sizeof(u32);
1065 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1066 }
1067
1068 addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1069 max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1070 devinfo->shared.nrof_flowrings =
1071 max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1072 rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1073 GFP_KERNEL);
1074 if (!rings)
1075 goto fail;
1076
1077 brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1078 devinfo->shared.nrof_flowrings);
1079
1080 for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1081 ring = &rings[i];
1082 ring->devinfo = devinfo;
1083 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1084 brcmf_commonring_register_cb(&ring->commonring,
1085 brcmf_pcie_ring_mb_ring_bell,
1086 brcmf_pcie_ring_mb_update_rptr,
1087 brcmf_pcie_ring_mb_update_wptr,
1088 brcmf_pcie_ring_mb_write_rptr,
1089 brcmf_pcie_ring_mb_write_wptr,
1090 ring);
1091 ring->w_idx_addr = h2d_w_idx_ptr;
1092 ring->r_idx_addr = h2d_r_idx_ptr;
1093 h2d_w_idx_ptr += sizeof(u32);
1094 h2d_r_idx_ptr += sizeof(u32);
1095 }
1096 devinfo->shared.flowrings = rings;
1097
1098 return 0;
1099
1100fail:
1101 brcmf_err("Allocating commonring buffers failed\n");
1102 brcmf_pcie_release_ringbuffers(devinfo);
1103 return -ENOMEM;
1104}
1105
1106
1107static void
1108brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1109{
1110 if (devinfo->shared.scratch)
1111 dma_free_coherent(&devinfo->pdev->dev,
1112 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1113 devinfo->shared.scratch,
1114 devinfo->shared.scratch_dmahandle);
1115 if (devinfo->shared.ringupd)
1116 dma_free_coherent(&devinfo->pdev->dev,
1117 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1118 devinfo->shared.ringupd,
1119 devinfo->shared.ringupd_dmahandle);
1120}
1121
1122static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1123{
1124 long long address;
1125 u32 addr;
1126
1127 devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1128 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1129 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1130 if (!devinfo->shared.scratch)
1131 goto fail;
1132
1133 memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1134 brcmf_dma_flush(devinfo->shared.scratch, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1135
1136 addr = devinfo->shared.tcm_base_address +
1137 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1138 address = (long long)(long)devinfo->shared.scratch_dmahandle;
1139 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1140 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1141 addr = devinfo->shared.tcm_base_address +
1142 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1143 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1144
1145 devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1146 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1147 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1148 if (!devinfo->shared.ringupd)
1149 goto fail;
1150
1151 memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1152 brcmf_dma_flush(devinfo->shared.ringupd, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1153
1154 addr = devinfo->shared.tcm_base_address +
1155 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1156 address = (long long)(long)devinfo->shared.ringupd_dmahandle;
1157 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1158 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1159 addr = devinfo->shared.tcm_base_address +
1160 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1161 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1162 return 0;
1163
1164fail:
1165 brcmf_err("Allocating scratch buffers failed\n");
1166 brcmf_pcie_release_scratchbuffers(devinfo);
1167 return -ENOMEM;
1168}
1169
1170
1171static void brcmf_pcie_down(struct device *dev)
1172{
1173}
1174
1175
1176static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1177{
1178 return 0;
1179}
1180
1181
1182static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1183 uint len)
1184{
1185 return 0;
1186}
1187
1188
1189static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1190 uint len)
1191{
1192 return 0;
1193}
1194
1195
1196static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1197 .txdata = brcmf_pcie_tx,
1198 .stop = brcmf_pcie_down,
1199 .txctl = brcmf_pcie_tx_ctlpkt,
1200 .rxctl = brcmf_pcie_rx_ctlpkt,
1201};
1202
1203
1204static int
1205brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1206 u32 sharedram_addr)
1207{
1208 struct brcmf_pcie_shared_info *shared;
1209 u32 addr;
1210 u32 version;
1211
1212 shared = &devinfo->shared;
1213 shared->tcm_base_address = sharedram_addr;
1214
1215 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1216 version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1217 brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1218 if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1219 (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1220 brcmf_err("Unsupported PCIE version %d\n", version);
1221 return -EINVAL;
1222 }
1223 if (shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT) {
1224 brcmf_err("Unsupported legacy TX mode 0x%x\n",
1225 shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT);
1226 return -EINVAL;
1227 }
1228
1229 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1230 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1231 if (shared->max_rxbufpost == 0)
1232 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1233
1234 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1235 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1236
1237 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1238 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1239
1240 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1241 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1242
1243 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1244 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1245
1246 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1247 shared->max_rxbufpost, shared->rx_dataoffset);
1248
1249 brcmf_pcie_bus_console_init(devinfo);
1250
1251 return 0;
1252}
1253
1254
1255static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1256{
1257 char *fw_name;
1258 char *nvram_name;
1259 uint fw_len, nv_len;
1260 char end;
1261
1262 brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1263 devinfo->ci->chiprev);
1264
1265 switch (devinfo->ci->chip) {
1266 case BRCM_CC_43602_CHIP_ID:
1267 fw_name = BRCMF_PCIE_43602_FW_NAME;
1268 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1269 break;
1270 case BRCM_CC_4354_CHIP_ID:
1271 fw_name = BRCMF_PCIE_4354_FW_NAME;
1272 nvram_name = BRCMF_PCIE_4354_NVRAM_NAME;
1273 break;
1274 case BRCM_CC_4356_CHIP_ID:
1275 fw_name = BRCMF_PCIE_4356_FW_NAME;
1276 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1277 break;
1278 case BRCM_CC_43567_CHIP_ID:
1279 case BRCM_CC_43569_CHIP_ID:
1280 case BRCM_CC_43570_CHIP_ID:
1281 fw_name = BRCMF_PCIE_43570_FW_NAME;
1282 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1283 break;
1284 default:
1285 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1286 return -ENODEV;
1287 }
1288
1289 fw_len = sizeof(devinfo->fw_name) - 1;
1290 nv_len = sizeof(devinfo->nvram_name) - 1;
1291 /* check if firmware path is provided by module parameter */
1292 if (brcmf_firmware_path[0] != '\0') {
1293 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1294 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1295 fw_len -= strlen(devinfo->fw_name);
1296 nv_len -= strlen(devinfo->nvram_name);
1297
1298 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1299 if (end != '/') {
1300 strncat(devinfo->fw_name, "/", fw_len);
1301 strncat(devinfo->nvram_name, "/", nv_len);
1302 fw_len--;
1303 nv_len--;
1304 }
1305 }
1306 strncat(devinfo->fw_name, fw_name, fw_len);
1307 strncat(devinfo->nvram_name, nvram_name, nv_len);
1308
1309 return 0;
1310}
1311
1312
1313static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1314 const struct firmware *fw, void *nvram,
1315 u32 nvram_len)
1316{
1317 u32 sharedram_addr;
1318 u32 sharedram_addr_written;
1319 u32 loop_counter;
1320 int err;
1321 u32 address;
1322 u32 resetintr;
1323
1324 devinfo->ringbell = brcmf_pcie_ringbell_v2;
1325 devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1326
1327 brcmf_dbg(PCIE, "Halt ARM.\n");
1328 err = brcmf_pcie_enter_download_state(devinfo);
1329 if (err)
1330 return err;
1331
1332 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1333 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1334 (void *)fw->data, fw->size);
1335
1336 resetintr = get_unaligned_le32(fw->data);
1337 release_firmware(fw);
1338
1339 /* reset last 4 bytes of RAM address. to be used for shared
1340 * area. This identifies when FW is running
1341 */
1342 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1343
1344 if (nvram) {
1345 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1346 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1347 nvram_len;
1348 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1349 brcmf_fw_nvram_free(nvram);
1350 } else {
1351 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1352 devinfo->nvram_name);
1353 }
1354
1355 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1356 devinfo->ci->ramsize -
1357 4);
1358 brcmf_dbg(PCIE, "Bring ARM in running state\n");
1359 err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1360 if (err)
1361 return err;
1362
1363 brcmf_dbg(PCIE, "Wait for FW init\n");
1364 sharedram_addr = sharedram_addr_written;
1365 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1366 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1367 msleep(50);
1368 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1369 devinfo->ci->ramsize -
1370 4);
1371 loop_counter--;
1372 }
1373 if (sharedram_addr == sharedram_addr_written) {
1374 brcmf_err("FW failed to initialize\n");
1375 return -ENODEV;
1376 }
1377 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1378
1379 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1380}
1381
1382
1383static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1384{
1385 struct pci_dev *pdev;
1386 int err;
1387 phys_addr_t bar0_addr, bar1_addr;
1388 ulong bar1_size;
1389
1390 pdev = devinfo->pdev;
1391
1392 err = pci_enable_device(pdev);
1393 if (err) {
1394 brcmf_err("pci_enable_device failed err=%d\n", err);
1395 return err;
1396 }
1397
1398 pci_set_master(pdev);
1399
1400 /* Bar-0 mapped address */
1401 bar0_addr = pci_resource_start(pdev, 0);
1402 /* Bar-1 mapped address */
1403 bar1_addr = pci_resource_start(pdev, 2);
1404 /* read Bar-1 mapped memory range */
1405 bar1_size = pci_resource_len(pdev, 2);
1406 if ((bar1_size == 0) || (bar1_addr == 0)) {
1407 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1408 bar1_size, (unsigned long long)bar1_addr);
1409 return -EINVAL;
1410 }
1411
1412 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1413 devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1414 devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1415
1416 if (!devinfo->regs || !devinfo->tcm) {
1417 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1418 devinfo->tcm);
1419 return -EINVAL;
1420 }
1421 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1422 devinfo->regs, (unsigned long long)bar0_addr);
1423 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1424 devinfo->tcm, (unsigned long long)bar1_addr);
1425
1426 return 0;
1427}
1428
1429
1430static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1431{
1432 if (devinfo->tcm)
1433 iounmap(devinfo->tcm);
1434 if (devinfo->regs)
1435 iounmap(devinfo->regs);
1436
1437 pci_disable_device(devinfo->pdev);
1438}
1439
1440
1441static int brcmf_pcie_attach_bus(struct device *dev)
1442{
1443 int ret;
1444
1445 /* Attach to the common driver interface */
1446 ret = brcmf_attach(dev);
1447 if (ret) {
1448 brcmf_err("brcmf_attach failed\n");
1449 } else {
1450 ret = brcmf_bus_start(dev);
1451 if (ret)
1452 brcmf_err("dongle is not responding\n");
1453 }
1454
1455 return ret;
1456}
1457
1458
1459static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1460{
1461 u32 ret_addr;
1462
1463 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1464 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1465 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1466
1467 return ret_addr;
1468}
1469
1470
1471static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1472{
1473 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1474
1475 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1476 return brcmf_pcie_read_reg32(devinfo, addr);
1477}
1478
1479
1480static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1481{
1482 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1483
1484 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1485 brcmf_pcie_write_reg32(devinfo, addr, value);
1486}
1487
1488
1489static int brcmf_pcie_buscoreprep(void *ctx)
1490{
1491 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1492 int err;
1493
1494 err = brcmf_pcie_get_resource(devinfo);
1495 if (err == 0) {
1496 /* Set CC watchdog to reset all the cores on the chip to bring
1497 * back dongle to a sane state.
1498 */
1499 brcmf_pcie_buscore_write32(ctx, CORE_CC_REG(SI_ENUM_BASE,
1500 watchdog), 4);
1501 msleep(100);
1502 }
1503
1504 return err;
1505}
1506
1507
1508static void brcmf_pcie_buscore_exitdl(void *ctx, struct brcmf_chip *chip,
1509 u32 rstvec)
1510{
1511 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1512
1513 brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1514}
1515
1516
1517static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1518 .prepare = brcmf_pcie_buscoreprep,
1519 .exit_dl = brcmf_pcie_buscore_exitdl,
1520 .read32 = brcmf_pcie_buscore_read32,
1521 .write32 = brcmf_pcie_buscore_write32,
1522};
1523
1524static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1525 void *nvram, u32 nvram_len)
1526{
1527 struct brcmf_bus *bus = dev_get_drvdata(dev);
1528 struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1529 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1530 struct brcmf_commonring **flowrings;
1531 int ret;
1532 u32 i;
1533
1534 brcmf_pcie_attach(devinfo);
1535
1536 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1537 if (ret)
1538 goto fail;
1539
1540 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1541
1542 ret = brcmf_pcie_init_ringbuffers(devinfo);
1543 if (ret)
1544 goto fail;
1545
1546 ret = brcmf_pcie_init_scratchbuffers(devinfo);
1547 if (ret)
1548 goto fail;
1549
1550 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1551 ret = brcmf_pcie_request_irq(devinfo);
1552 if (ret)
1553 goto fail;
1554
1555 /* hook the commonrings in the bus structure. */
1556 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1557 bus->msgbuf->commonrings[i] =
1558 &devinfo->shared.commonrings[i]->commonring;
1559
1560 flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(flowrings),
1561 GFP_KERNEL);
1562 if (!flowrings)
1563 goto fail;
1564
1565 for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1566 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1567 bus->msgbuf->flowrings = flowrings;
1568
1569 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1570 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1571 bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1572
1573 init_waitqueue_head(&devinfo->mbdata_resp_wait);
1574
1575 brcmf_pcie_intr_enable(devinfo);
1576 if (brcmf_pcie_attach_bus(bus->dev) == 0)
1577 return;
1578
1579 brcmf_pcie_bus_console_read(devinfo);
1580
1581fail:
1582 device_release_driver(dev);
1583}
1584
1585static int
1586brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1587{
1588 int ret;
1589 struct brcmf_pciedev_info *devinfo;
1590 struct brcmf_pciedev *pcie_bus_dev;
1591 struct brcmf_bus *bus;
1592
1593 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
1594
1595 ret = -ENOMEM;
1596 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1597 if (devinfo == NULL)
1598 return ret;
1599
1600 devinfo->pdev = pdev;
1601 pcie_bus_dev = NULL;
1602 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1603 if (IS_ERR(devinfo->ci)) {
1604 ret = PTR_ERR(devinfo->ci);
1605 devinfo->ci = NULL;
1606 goto fail;
1607 }
1608
1609 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1610 if (pcie_bus_dev == NULL) {
1611 ret = -ENOMEM;
1612 goto fail;
1613 }
1614
1615 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1616 if (!bus) {
1617 ret = -ENOMEM;
1618 goto fail;
1619 }
1620 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1621 if (!bus->msgbuf) {
1622 ret = -ENOMEM;
1623 kfree(bus);
1624 goto fail;
1625 }
1626
1627 /* hook it all together. */
1628 pcie_bus_dev->devinfo = devinfo;
1629 pcie_bus_dev->bus = bus;
1630 bus->dev = &pdev->dev;
1631 bus->bus_priv.pcie = pcie_bus_dev;
1632 bus->ops = &brcmf_pcie_bus_ops;
1633 bus->proto_type = BRCMF_PROTO_MSGBUF;
1634 bus->chip = devinfo->coreid;
1635 dev_set_drvdata(&pdev->dev, bus);
1636
1637 ret = brcmf_pcie_get_fwnames(devinfo);
1638 if (ret)
1639 goto fail_bus;
1640
1641 ret = brcmf_fw_get_firmwares(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1642 BRCMF_FW_REQ_NV_OPTIONAL,
1643 devinfo->fw_name, devinfo->nvram_name,
1644 brcmf_pcie_setup);
1645 if (ret == 0)
1646 return 0;
1647fail_bus:
1648 kfree(bus->msgbuf);
1649 kfree(bus);
1650fail:
1651 brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1652 brcmf_pcie_release_resource(devinfo);
1653 if (devinfo->ci)
1654 brcmf_chip_detach(devinfo->ci);
1655 kfree(pcie_bus_dev);
1656 kfree(devinfo);
1657 return ret;
1658}
1659
1660
1661static void
1662brcmf_pcie_remove(struct pci_dev *pdev)
1663{
1664 struct brcmf_pciedev_info *devinfo;
1665 struct brcmf_bus *bus;
1666
1667 brcmf_dbg(PCIE, "Enter\n");
1668
1669 bus = dev_get_drvdata(&pdev->dev);
1670 if (bus == NULL)
1671 return;
1672
1673 devinfo = bus->bus_priv.pcie->devinfo;
1674
1675 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1676 if (devinfo->ci)
1677 brcmf_pcie_intr_disable(devinfo);
1678
1679 brcmf_detach(&pdev->dev);
1680
1681 kfree(bus->bus_priv.pcie);
1682 kfree(bus->msgbuf->flowrings);
1683 kfree(bus->msgbuf);
1684 kfree(bus);
1685
1686 brcmf_pcie_release_irq(devinfo);
1687 brcmf_pcie_release_scratchbuffers(devinfo);
1688 brcmf_pcie_release_ringbuffers(devinfo);
1689 brcmf_pcie_detach(devinfo);
1690 brcmf_pcie_release_resource(devinfo);
1691
1692 if (devinfo->ci)
1693 brcmf_chip_detach(devinfo->ci);
1694
1695 kfree(devinfo);
1696 dev_set_drvdata(&pdev->dev, NULL);
1697}
1698
1699
1700#ifdef CONFIG_PM
1701
1702
1703static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1704{
1705 struct brcmf_pciedev_info *devinfo;
1706 struct brcmf_bus *bus;
1707 int err;
1708
1709 brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1710
1711 bus = dev_get_drvdata(&pdev->dev);
1712 devinfo = bus->bus_priv.pcie->devinfo;
1713
1714 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1715
1716 devinfo->mbdata_completed = false;
1717 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1718
1719 wait_event_timeout(devinfo->mbdata_resp_wait,
1720 devinfo->mbdata_completed,
1721 msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1722 if (!devinfo->mbdata_completed) {
1723 brcmf_err("Timeout on response for entering D3 substate\n");
1724 return -EIO;
1725 }
1726 brcmf_pcie_release_irq(devinfo);
1727
1728 err = pci_save_state(pdev);
1729 if (err) {
1730 brcmf_err("pci_save_state failed, err=%d\n", err);
1731 return err;
1732 }
1733
1734 brcmf_chip_detach(devinfo->ci);
1735 devinfo->ci = NULL;
1736
1737 brcmf_pcie_remove(pdev);
1738
1739 return pci_prepare_to_sleep(pdev);
1740}
1741
1742
1743static int brcmf_pcie_resume(struct pci_dev *pdev)
1744{
1745 int err;
1746
1747 brcmf_dbg(PCIE, "Enter, pdev=%p\n", pdev);
1748
1749 err = pci_set_power_state(pdev, PCI_D0);
1750 if (err) {
1751 brcmf_err("pci_set_power_state failed, err=%d\n", err);
1752 return err;
1753 }
1754 pci_restore_state(pdev);
1755
1756 err = brcmf_pcie_probe(pdev, NULL);
1757 if (err)
1758 brcmf_err("probe after resume failed, err=%d\n", err);
1759
1760 return err;
1761}
1762
1763
1764#endif /* CONFIG_PM */
1765
1766
1767#define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1768 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1769
1770static struct pci_device_id brcmf_pcie_devid_table[] = {
1771 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_DEVICE_ID),
1772 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1773 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1774 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1775 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1776 { /* end: all zeroes */ }
1777};
1778
1779
1780MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1781
1782
1783static struct pci_driver brcmf_pciedrvr = {
1784 .node = {},
1785 .name = KBUILD_MODNAME,
1786 .id_table = brcmf_pcie_devid_table,
1787 .probe = brcmf_pcie_probe,
1788 .remove = brcmf_pcie_remove,
1789#ifdef CONFIG_PM
1790 .suspend = brcmf_pcie_suspend,
1791 .resume = brcmf_pcie_resume
1792#endif /* CONFIG_PM */
1793};
1794
1795
1796void brcmf_pcie_register(void)
1797{
1798 int err;
1799
1800 brcmf_dbg(PCIE, "Enter\n");
1801 err = pci_register_driver(&brcmf_pciedrvr);
1802 if (err)
1803 brcmf_err("PCIE driver registration failed, err=%d\n", err);
1804}
1805
1806
1807void brcmf_pcie_exit(void)
1808{
1809 brcmf_dbg(PCIE, "Enter\n");
1810 pci_unregister_driver(&brcmf_pciedrvr);
1811}
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/pcie.h b/drivers/net/wireless/brcm80211/brcmfmac/pcie.h
new file mode 100644
index 000000000000..6edaaf8ef5ce
--- /dev/null
+++ b/drivers/net/wireless/brcm80211/brcmfmac/pcie.h
@@ -0,0 +1,29 @@
1/* Copyright (c) 2014 Broadcom Corporation
2 *
3 * Permission to use, copy, modify, and/or distribute this software for any
4 * purpose with or without fee is hereby granted, provided that the above
5 * copyright notice and this permission notice appear in all copies.
6 *
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14 */
15#ifndef BRCMFMAC_PCIE_H
16#define BRCMFMAC_PCIE_H
17
18
19struct brcmf_pciedev {
20 struct brcmf_bus *bus;
21 struct brcmf_pciedev_info *devinfo;
22};
23
24
25void brcmf_pcie_exit(void);
26void brcmf_pcie_register(void);
27
28
29#endif /* BRCMFMAC_PCIE_H */
diff --git a/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h
index 64d1a7ba040c..af26e0de1e5c 100644
--- a/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h
+++ b/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h
@@ -38,8 +38,12 @@
38#define BRCM_CC_4335_CHIP_ID 0x4335 38#define BRCM_CC_4335_CHIP_ID 0x4335
39#define BRCM_CC_4339_CHIP_ID 0x4339 39#define BRCM_CC_4339_CHIP_ID 0x4339
40#define BRCM_CC_4354_CHIP_ID 0x4354 40#define BRCM_CC_4354_CHIP_ID 0x4354
41#define BRCM_CC_4356_CHIP_ID 0x4356
41#define BRCM_CC_43566_CHIP_ID 43566 42#define BRCM_CC_43566_CHIP_ID 43566
43#define BRCM_CC_43567_CHIP_ID 43567
42#define BRCM_CC_43569_CHIP_ID 43569 44#define BRCM_CC_43569_CHIP_ID 43569
45#define BRCM_CC_43570_CHIP_ID 43570
46#define BRCM_CC_43602_CHIP_ID 43602
43 47
44/* SDIO Device IDs */ 48/* SDIO Device IDs */
45#define BRCM_SDIO_43143_DEVICE_ID BRCM_CC_43143_CHIP_ID 49#define BRCM_SDIO_43143_DEVICE_ID BRCM_CC_43143_CHIP_ID
@@ -58,6 +62,13 @@
58#define BRCM_USB_43569_DEVICE_ID 0xbd27 62#define BRCM_USB_43569_DEVICE_ID 0xbd27
59#define BRCM_USB_BCMFW_DEVICE_ID 0x0bdc 63#define BRCM_USB_BCMFW_DEVICE_ID 0x0bdc
60 64
65/* PCIE Device IDs */
66#define BRCM_PCIE_4354_DEVICE_ID 0x43df
67#define BRCM_PCIE_4356_DEVICE_ID 0x43ec
68#define BRCM_PCIE_43567_DEVICE_ID 0x43d3
69#define BRCM_PCIE_43570_DEVICE_ID 0x43d9
70#define BRCM_PCIE_43602_DEVICE_ID 0x43ba
71
61/* brcmsmac IDs */ 72/* brcmsmac IDs */
62#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */ 73#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
63#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */ 74#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 06:21:58 -0400