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authorMatt Carlson <mcarlson@broadcom.com>2011-11-04 05:15:02 -0400
committerDavid S. Miller <davem@davemloft.net>2011-11-04 17:31:48 -0400
commit9dc5e342703948ea7b086d063c85c0e79dac8149 (patch)
tree664ce50ab14d997f01f44f84a982440257413b78
parent5bc09186deba2a016b60aa3923fc0e42838ce877 (diff)
tg3: Obtain PCI function number from device
This patch adds code to attempt to obtain the PCI function number from the device rather than accept the number handed by the kernel. In pass-through scenarios, the function number handed by the kernel may not reflect the true function of the device. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/broadcom/tg3.c30
-rw-r--r--drivers/net/ethernet/broadcom/tg3.h9
2 files changed, 33 insertions, 6 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 0413e1e85641..6973d01ae85a 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -14230,12 +14230,30 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14230 val = tr32(MEMARB_MODE); 14230 val = tr32(MEMARB_MODE);
14231 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); 14231 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14232 14232
14233 if (tg3_flag(tp, PCIX_MODE)) { 14233 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14234 pci_read_config_dword(tp->pdev, 14234 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14235 tp->pcix_cap + PCI_X_STATUS, &val); 14235 tg3_flag(tp, 5780_CLASS)) {
14236 tp->pci_fn = val & 0x7; 14236 if (tg3_flag(tp, PCIX_MODE)) {
14237 } else { 14237 pci_read_config_dword(tp->pdev,
14238 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; 14238 tp->pcix_cap + PCI_X_STATUS,
14239 &val);
14240 tp->pci_fn = val & 0x7;
14241 }
14242 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14243 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14244 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14245 NIC_SRAM_CPMUSTAT_SIG) {
14246 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14247 tp->pci_fn = tp->pci_fn ? 1 : 0;
14248 }
14249 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14251 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14252 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14253 NIC_SRAM_CPMUSTAT_SIG) {
14254 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14255 TG3_CPMU_STATUS_FSHFT_5719;
14256 }
14239 } 14257 }
14240 14258
14241 /* Get eeprom hw config before calling tg3_set_power_state(). 14259 /* Get eeprom hw config before calling tg3_set_power_state().
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index 03fab8cadd86..acfa265733ad 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -1095,6 +1095,11 @@
1095#define TG3_CPMU_CLCK_ORIDE 0x00003624 1095#define TG3_CPMU_CLCK_ORIDE 0x00003624
1096#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1096#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1097 1097
1098#define TG3_CPMU_STATUS 0x0000362c
1099#define TG3_CPMU_STATUS_FMSK_5717 0x20000000
1100#define TG3_CPMU_STATUS_FMSK_5719 0xc0000000
1101#define TG3_CPMU_STATUS_FSHFT_5719 30
1102
1098#define TG3_CPMU_CLCK_STAT 0x00003630 1103#define TG3_CPMU_CLCK_STAT 0x00003630
1099#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 1104#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1100#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1105#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
@@ -2128,6 +2133,10 @@
2128#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008 2133#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
2129#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010 2134#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
2130 2135
2136#define NIC_SRAM_CPMU_STATUS 0x00000e00
2137#define NIC_SRAM_CPMUSTAT_SIG 0x0000362c
2138#define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff
2139
2131#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 2140#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
2132 2141
2133#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 2142#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000