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authorOlivier Grenie <Olivier.Grenie@dibcom.fr>2009-12-07 05:49:40 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-12-15 21:18:16 -0500
commit9c78303681278b983fac3c6c3c0aa3f93cf2ffa8 (patch)
tree1407987d9fa1d4234c46fcab6d22da1997e303a2
parent03245a5ee69a5faa99b020fe1aca9bafe10c46a9 (diff)
V4L/DVB (13584): DiBXXX0: fix most of the Codingstyle violations from the previous patch
This patch changes most of the Codingstyle violations which were introduced by the previous patch. Line length less that 80 chars are not corrected. Signed-off-by: Olivier Grenie <Olivier.Grenie@dibcom.fr> Signed-off-by: Patrick Boettcher <pboettcher@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat
-rw-r--r--drivers/media/dvb/dvb-usb/dib0700_devices.c596
-rw-r--r--drivers/media/dvb/frontends/dib0070.c226
-rw-r--r--drivers/media/dvb/frontends/dib0090.c29
-rw-r--r--drivers/media/dvb/frontends/dib0090.h2
-rw-r--r--drivers/media/dvb/frontends/dib8000.c14
-rw-r--r--drivers/media/dvb/frontends/dib8000.h8
-rw-r--r--drivers/media/dvb/frontends/dibx000_common.h4
7 files changed, 442 insertions, 437 deletions
diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c
index 80a126354477..d4673c71dff5 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c
@@ -131,93 +131,95 @@ static int bristol_tuner_attach(struct dvb_usb_adapter *adap)
131/* MT226x */ 131/* MT226x */
132static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = { 132static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = {
133 { 133 {
134 BAND_UHF, // band_caps 134 BAND_UHF,
135 135
136 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1, 136 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
137 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ 137 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
138 (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup 138 (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8)
139 139 | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
140 1130, // inv_gain 140
141 21, // time_stabiliz 141 1130,
142 142 21,
143 0, // alpha_level 143
144 118, // thlock 144 0,
145 145 118,
146 0, // wbd_inv 146
147 3530, // wbd_ref 147 0,
148 1, // wbd_sel 148 3530,
149 0, // wbd_alpha 149 1,
150 150 0,
151 65535, // agc1_max 151
152 33770, // agc1_min 152 65535,
153 65535, // agc2_max 153 33770,
154 23592, // agc2_min 154 65535,
155 155 23592,
156 0, // agc1_pt1 156
157 62, // agc1_pt2 157 0,
158 255, // agc1_pt3 158 62,
159 64, // agc1_slope1 159 255,
160 64, // agc1_slope2 160 64,
161 132, // agc2_pt1 161 64,
162 192, // agc2_pt2 162 132,
163 80, // agc2_slope1 163 192,
164 80, // agc2_slope2 164 80,
165 165 80,
166 17, // alpha_mant 166
167 27, // alpha_exp 167 17,
168 23, // beta_mant 168 27,
169 51, // beta_exp 169 23,
170 170 51,
171 1, // perform_agc_softsplit 171
172 1,
172 }, { 173 }, {
173 BAND_VHF | BAND_LBAND, // band_caps 174 BAND_VHF | BAND_LBAND,
174 175
175 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1, 176 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
176 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ 177 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
177 (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup 178 (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8)
178 179 | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
179 2372, // inv_gain 180
180 21, // time_stabiliz 181 2372,
181 182 21,
182 0, // alpha_level 183
183 118, // thlock 184 0,
184 185 118,
185 0, // wbd_inv 186
186 3530, // wbd_ref 187 0,
187 1, // wbd_sel 188 3530,
188 0, // wbd_alpha 189 1,
189 190 0,
190 65535, // agc1_max 191
191 0, // agc1_min 192 65535,
192 65535, // agc2_max 193 0,
193 23592, // agc2_min 194 65535,
194 195 23592,
195 0, // agc1_pt1 196
196 128, // agc1_pt2 197 0,
197 128, // agc1_pt3 198 128,
198 128, // agc1_slope1 199 128,
199 0, // agc1_slope2 200 128,
200 128, // agc2_pt1 201 0,
201 253, // agc2_pt2 202 128,
202 81, // agc2_slope1 203 253,
203 0, // agc2_slope2 204 81,
204 205 0,
205 17, // alpha_mant 206
206 27, // alpha_exp 207 17,
207 23, // beta_mant 208 27,
208 51, // beta_exp 209 23,
209 210 51,
210 1, // perform_agc_softsplit 211
212 1,
211 } 213 }
212}; 214};
213 215
214static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = { 216static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = {
215 60000, 30000, // internal, sampling 217 60000, 30000,
216 1, 8, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 218 1, 8, 3, 1, 0,
217 0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 219 0, 0, 1, 1, 2,
218 (3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k 220 (3 << 14) | (1 << 12) | (524 << 0),
219 0, // ifreq 221 0,
220 20452225, // timf 222 20452225,
221}; 223};
222 224
223static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = { 225static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = {
@@ -934,47 +936,48 @@ static struct dvb_usb_rc_key dib0700_rc_keys[] = {
934 936
935/* STK7700P: Hauppauge Nova-T Stick, AVerMedia Volar */ 937/* STK7700P: Hauppauge Nova-T Stick, AVerMedia Volar */
936static struct dibx000_agc_config stk7700p_7000m_mt2060_agc_config = { 938static struct dibx000_agc_config stk7700p_7000m_mt2060_agc_config = {
937 BAND_UHF | BAND_VHF, // band_caps 939 BAND_UHF | BAND_VHF,
938 940
939 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, 941 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
940 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ 942 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
941 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup 943 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
942 944 | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
943 712, // inv_gain 945
944 41, // time_stabiliz 946 712,
945 947 41,
946 0, // alpha_level 948
947 118, // thlock 949 0,
948 950 118,
949 0, // wbd_inv 951
950 4095, // wbd_ref 952 0,
951 0, // wbd_sel 953 4095,
952 0, // wbd_alpha 954 0,
953 955 0,
954 42598, // agc1_max 956
955 17694, // agc1_min 957 42598,
956 45875, // agc2_max 958 17694,
957 2621, // agc2_min 959 45875,
958 0, // agc1_pt1 960 2621,
959 76, // agc1_pt2 961 0,
960 139, // agc1_pt3 962 76,
961 52, // agc1_slope1 963 139,
962 59, // agc1_slope2 964 52,
963 107, // agc2_pt1 965 59,
964 172, // agc2_pt2 966 107,
965 57, // agc2_slope1 967 172,
966 70, // agc2_slope2 968 57,
967 969 70,
968 21, // alpha_mant 970
969 25, // alpha_exp 971 21,
970 28, // beta_mant 972 25,
971 48, // beta_exp 973 28,
972 974 48,
973 1, // perform_agc_softsplit 975
974 { 0, // split_min 976 1,
975 107, // split_max 977 { 0,
976 51800, // global_split_min 978 107,
977 24700 // global_split_max 979 51800,
980 24700
978 }, 981 },
979}; 982};
980 983
@@ -983,54 +986,55 @@ static struct dibx000_agc_config stk7700p_7000p_mt2060_agc_config = {
983 986
984 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, 987 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
985 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ 988 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
986 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup 989 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
990 | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
987 991
988 712, // inv_gain 992 712,
989 41, // time_stabiliz 993 41,
990 994
991 0, // alpha_level 995 0,
992 118, // thlock 996 118,
993 997
994 0, // wbd_inv 998 0,
995 4095, // wbd_ref 999 4095,
996 0, // wbd_sel 1000 0,
997 0, // wbd_alpha 1001 0,
998 1002
999 42598, // agc1_max 1003 42598,
1000 16384, // agc1_min 1004 16384,
1001 42598, // agc2_max 1005 42598,
1002 0, // agc2_min 1006 0,
1003 1007
1004 0, // agc1_pt1 1008 0,
1005 137, // agc1_pt2 1009 137,
1006 255, // agc1_pt3 1010 255,
1007 1011
1008 0, // agc1_slope1 1012 0,
1009 255, // agc1_slope2 1013 255,
1010 1014
1011 0, // agc2_pt1 1015 0,
1012 0, // agc2_pt2 1016 0,
1013 1017
1014 0, // agc2_slope1 1018 0,
1015 41, // agc2_slope2 1019 41,
1016 1020
1017 15, // alpha_mant 1021 15,
1018 25, // alpha_exp 1022 25,
1019 1023
1020 28, // beta_mant 1024 28,
1021 48, // beta_exp 1025 48,
1022 1026
1023 0, // perform_agc_softsplit 1027 0,
1024}; 1028};
1025 1029
1026static struct dibx000_bandwidth_config stk7700p_pll_config = { 1030static struct dibx000_bandwidth_config stk7700p_pll_config = {
1027 60000, 30000, // internal, sampling 1031 60000, 30000,
1028 1, 8, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1032 1, 8, 3, 1, 0,
1029 0, 0, 1, 1, 0, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 1033 0, 0, 1, 1, 0,
1030 (3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k 1034 (3 << 14) | (1 << 12) | (524 << 0),
1031 60258167, // ifreq 1035 60258167,
1032 20452225, // timf 1036 20452225,
1033 30000000, // xtal 1037 30000000,
1034}; 1038};
1035 1039
1036static struct dib7000m_config stk7700p_dib7000m_config = { 1040static struct dib7000m_config stk7700p_dib7000m_config = {
@@ -1116,41 +1120,42 @@ static struct dibx000_agc_config dib7070_agc_config = {
1116 BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, 1120 BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
1117 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, 1121 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
1118 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ 1122 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
1119 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup 1123 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
1120 1124 | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
1121 600, // inv_gain 1125
1122 10, // time_stabiliz 1126 600,
1123 1127 10,
1124 0, // alpha_level 1128
1125 118, // thlock 1129 0,
1126 1130 118,
1127 0, // wbd_inv 1131
1128 3530, // wbd_ref 1132 0,
1129 1, // wbd_sel 1133 3530,
1130 5, // wbd_alpha 1134 1,
1131 1135 5,
1132 65535, // agc1_max 1136
1133 0, // agc1_min 1137 65535,
1134 1138 0,
1135 65535, // agc2_max 1139
1136 0, // agc2_min 1140 65535,
1137 1141 0,
1138 0, // agc1_pt1 1142
1139 40, // agc1_pt2 1143 0,
1140 183, // agc1_pt3 1144 40,
1141 206, // agc1_slope1 1145 183,
1142 255, // agc1_slope2 1146 206,
1143 72, // agc2_pt1 1147 255,
1144 152, // agc2_pt2 1148 72,
1145 88, // agc2_slope1 1149 152,
1146 90, // agc2_slope2 1150 88,
1147 1151 90,
1148 17, // alpha_mant 1152
1149 27, // alpha_exp 1153 17,
1150 23, // beta_mant 1154 27,
1151 51, // beta_exp 1155 23,
1152 1156 51,
1153 0, // perform_agc_softsplit 1157
1158 0,
1154}; 1159};
1155 1160
1156static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff) 1161static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
@@ -1277,13 +1282,13 @@ static int stk70x0p_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
1277} 1282}
1278 1283
1279static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = { 1284static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
1280 60000, 15000, // internal, sampling 1285 60000, 15000,
1281 1, 20, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1286 1, 20, 3, 1, 0,
1282 0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 1287 0, 0, 1, 1, 2,
1283 (3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k 1288 (3 << 14) | (1 << 12) | (524 << 0),
1284 (0 << 25) | 0, // ifreq = 0.000000 MHz 1289 (0 << 25) | 0,
1285 20452225, // timf 1290 20452225,
1286 12000000, // xtal_hz 1291 12000000,
1287}; 1292};
1288 1293
1289static struct dib7000p_config dib7070p_dib7000p_config = { 1294static struct dib7000p_config dib7070p_dib7000p_config = {
@@ -1567,12 +1572,14 @@ static int dib807x_tuner_attach(struct dvb_usb_adapter *adap)
1567 return 0; 1572 return 0;
1568} 1573}
1569 1574
1570static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff) 1575static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index,
1576 u16 pid, int onoff)
1571{ 1577{
1572 return dib8000_pid_filter(adapter->fe, index, pid, onoff); 1578 return dib8000_pid_filter(adapter->fe, index, pid, onoff);
1573} 1579}
1574 1580
1575static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff) 1581static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter,
1582 int onoff)
1576{ 1583{
1577 return dib8000_pid_filter_ctrl(adapter->fe, onoff); 1584 return dib8000_pid_filter_ctrl(adapter->fe, onoff);
1578} 1585}
@@ -1648,94 +1655,98 @@ static int stk807xpvr_frontend_attach1(struct dvb_usb_adapter *adap)
1648struct dibx000_agc_config dib8090_agc_config[2] = { 1655struct dibx000_agc_config dib8090_agc_config[2] = {
1649 { 1656 {
1650 BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, 1657 BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
1651 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, 1658 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
1652 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ 1659 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
1653 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup 1660 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
1654 1661 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
1655 787,// inv_gain = 1/ 90.4dB // no boost, lower gain due to ramp quantification 1662 | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
1656 10, // time_stabiliz 1663
1657 1664 787,
1658 0, // alpha_level 1665 10,
1659 118, // thlock 1666
1660 1667 0,
1661 0, // wbd_inv 1668 118,
1662 3530, // wbd_ref 1669
1663 1, // wbd_sel 1670 0,
1664 5, // wbd_alpha 1671 3530,
1665 1672 1,
1666 65535, // agc1_max 1673 5,
1667 0, // agc1_min 1674
1668 1675 65535,
1669 65535, // agc2_max 1676 0,
1670 0, // agc2_min 1677
1671 1678 65535,
1672 0, // agc1_pt1 1679 0,
1673 32, // agc1_pt2 1680
1674 114, // agc1_pt3 // 40.4dB 1681 0,
1675 143, // agc1_slope1 1682 32,
1676 144, // agc1_slope2 1683 114,
1677 114, // agc2_pt1 1684 143,
1678 227, // agc2_pt2 1685 144,
1679 116, // agc2_slope1 1686 114,
1680 117, // agc2_slope2 1687 227,
1681 1688 116,
1682 28, // alpha_mant // 5Hz with 90.2dB 1689 117,
1683 26, // alpha_exp 1690
1684 31, // beta_mant 1691 28,
1685 51, // beta_exp 1692 26,
1686 1693 31,
1687 0, // perform_agc_softsplit 1694 51,
1695
1696 0,
1688 }, 1697 },
1689 { 1698 {
1690 BAND_CBAND, 1699 BAND_CBAND,
1691 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, 1700 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
1692 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ 1701 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
1693 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup 1702 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
1694 1703 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
1695 787,// inv_gain = 1/ 90.4dB // no boost, lower gain due to ramp quantification 1704 | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
1696 10, // time_stabiliz 1705
1697 1706 787,
1698 0, // alpha_level 1707 10,
1699 118, // thlock 1708
1700 1709 0,
1701 0, // wbd_inv 1710 118,
1702 3530, // wbd_ref 1711
1703 1, // wbd_sel 1712 0,
1704 5, // wbd_alpha 1713 3530,
1705 1714 1,
1706 0, // agc1_max 1715 5,
1707 0, // agc1_min 1716
1708 1717 0,
1709 65535, // agc2_max 1718 0,
1710 0, // agc2_min 1719
1711 1720 65535,
1712 0, // agc1_pt1 1721 0,
1713 32, // agc1_pt2 1722
1714 114, // agc1_pt3 // 40.4dB 1723 0,
1715 143, // agc1_slope1 1724 32,
1716 144, // agc1_slope2 1725 114,
1717 114, // agc2_pt1 1726 143,
1718 227, // agc2_pt2 1727 144,
1719 116, // agc2_slope1 1728 114,
1720 117, // agc2_slope2 1729 227,
1721 1730 116,
1722 28, // alpha_mant // 5Hz with 90.2dB 1731 117,
1723 26, // alpha_exp 1732
1724 31, // beta_mant 1733 28,
1725 51, // beta_exp 1734 26,
1726 1735 31,
1727 0, // perform_agc_softsplit 1736 51,
1737
1738 0,
1728 } 1739 }
1729}; 1740};
1730 1741
1731static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = { 1742static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = {
1732 54000, 13500, // internal, sampling 1743 54000, 13500,
1733 1, 18, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1744 1, 18, 3, 1, 0,
1734 0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 1745 0, 0, 1, 1, 2,
1735 (3 << 14) | (1 << 12) | (599 << 0), // sad_cfg: refsel, sel, freq_15k 1746 (3 << 14) | (1 << 12) | (599 << 0),
1736 (0 << 25) | 0, // ifreq = 0 MHz 1747 (0 << 25) | 0,
1737 20199727, // timf 1748 20199727,
1738 12000000, // xtal_hz 1749 12000000,
1739}; 1750};
1740 1751
1741static int dib8090_get_adc_power(struct dvb_frontend *fe) 1752static int dib8090_get_adc_power(struct dvb_frontend *fe)
@@ -1802,13 +1813,13 @@ static int dib8096_set_param_override(struct dvb_frontend *fe,
1802 return ret; 1813 return ret;
1803 1814
1804 switch (band) { 1815 switch (band) {
1805 case BAND_VHF: 1816 case BAND_VHF:
1806 offset = 100; 1817 offset = 100;
1807 break; 1818 break;
1808 case BAND_UHF: 1819 case BAND_UHF:
1809 offset = 550; 1820 offset = 550;
1810 break; 1821 break;
1811 default: 1822 default:
1812 offset = 0; 1823 offset = 0;
1813 break; 1824 break;
1814 } 1825 }
@@ -1816,31 +1827,26 @@ static int dib8096_set_param_override(struct dvb_frontend *fe,
1816 dib8000_set_wbd_ref(fe, offset); 1827 dib8000_set_wbd_ref(fe, offset);
1817 1828
1818 1829
1819 if (band == BAND_CBAND) 1830 if (band == BAND_CBAND) {
1820 {
1821 deb_info("tuning in CBAND - soft-AGC startup\n"); 1831 deb_info("tuning in CBAND - soft-AGC startup\n");
1822 /* TODO specific wbd target for dib0090 - needed for startup ? */ 1832 /* TODO specific wbd target for dib0090 - needed for startup ? */
1823 dib0090_set_tune_state(fe, CT_AGC_START); 1833 dib0090_set_tune_state(fe, CT_AGC_START);
1824 do 1834 do {
1825 { 1835 ret = dib0090_gain_control(fe);
1826 ret = dib0090_gain_control(fe); 1836 msleep(ret);
1827 msleep(ret); 1837 tune_state = dib0090_get_tune_state(fe);
1828 tune_state = dib0090_get_tune_state(fe); 1838 if (tune_state == CT_AGC_STEP_0)
1829 if (tune_state == CT_AGC_STEP_0) 1839 dib8000_set_gpio(fe, 6, 0, 1);
1830 dib8000_set_gpio(fe, 6, 0, 1); 1840 else if (tune_state == CT_AGC_STEP_1) {
1831 else if (tune_state == CT_AGC_STEP_1) 1841 dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
1832 { 1842 if (rf_gain_limit == 0)
1833 dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain); 1843 dib8000_set_gpio(fe, 6, 0, 0);
1834 if (rf_gain_limit == 0) 1844 }
1835 dib8000_set_gpio(fe, 6, 0, 0); 1845 } while (tune_state < CT_AGC_STOP);
1836 }
1837 }
1838 while(tune_state<CT_AGC_STOP);
1839 dib0090_pwm_gain_reset(fe); 1846 dib0090_pwm_gain_reset(fe);
1840 dib8000_pwm_agc_reset(fe); 1847 dib8000_pwm_agc_reset(fe);
1841 dib8000_set_tune_state(fe, CT_DEMOD_START); 1848 dib8000_set_tune_state(fe, CT_DEMOD_START);
1842 } 1849 } else {
1843 else {
1844 deb_info("not tuning in CBAND - standard AGC startup\n"); 1850 deb_info("not tuning in CBAND - standard AGC startup\n");
1845 dib0090_pwm_gain_reset(fe); 1851 dib0090_pwm_gain_reset(fe);
1846 } 1852 }
diff --git a/drivers/media/dvb/frontends/dib0070.c b/drivers/media/dvb/frontends/dib0070.c
index 81860b2cfe98..0d12763603b4 100644
--- a/drivers/media/dvb/frontends/dib0070.c
+++ b/drivers/media/dvb/frontends/dib0070.c
@@ -163,7 +163,7 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
163 163
164 adc = dib0070_read_reg(state, 0x19); 164 adc = dib0070_read_reg(state, 0x19);
165 165
166 dprintk( "CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024); 166 dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024);
167 167
168 if (adc >= 400) { 168 if (adc >= 400) {
169 adc -= 400; 169 adc -= 400;
@@ -174,7 +174,7 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
174 } 174 }
175 175
176 if (adc < state->adc_diff) { 176 if (adc < state->adc_diff) {
177 dprintk( "CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff); 177 dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff);
178 state->adc_diff = adc; 178 state->adc_diff = adc;
179 state->fcaptrim = state->captrim; 179 state->fcaptrim = state->captrim;
180 180
@@ -201,7 +201,7 @@ static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf
201{ 201{
202 struct dib0070_state *state = fe->tuner_priv; 202 struct dib0070_state *state = fe->tuner_priv;
203 u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0); 203 u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
204 dprintk( "CTRL_LO5: 0x%x", lo5); 204 dprintk("CTRL_LO5: 0x%x", lo5);
205 return dib0070_write_reg(state, 0x15, lo5); 205 return dib0070_write_reg(state, 0x15, lo5);
206} 206}
207 207
@@ -215,10 +215,10 @@ void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
215 } else { 215 } else {
216 dib0070_write_reg(state, 0x1b, 0x4112); 216 dib0070_write_reg(state, 0x1b, 0x4112);
217 if (state->cfg->vga_filter != 0) { 217 if (state->cfg->vga_filter != 0) {
218 dib0070_write_reg(state, 0x1a, state->cfg->vga_filter); 218 dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
219 dprintk( "vga filter register is set to %x", state->cfg->vga_filter); 219 dprintk("vga filter register is set to %x", state->cfg->vga_filter);
220 } else 220 } else
221 dib0070_write_reg(state, 0x1a, 0x0009); 221 dib0070_write_reg(state, 0x1a, 0x0009);
222 } 222 }
223} 223}
224 224
@@ -255,7 +255,7 @@ static const struct dib0070_tuning dib0070_tuning_table[] = {
255 { 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 }, 255 { 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
256 { 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 }, 256 { 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
257 { 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */ 257 { 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
258 { 699999, 2, 0 ,1, 4, 2, 2, 0x4000 | 0x0800 }, 258 { 699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800 },
259 { 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 }, 259 { 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 },
260 { 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */ 260 { 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
261}; 261};
@@ -291,7 +291,7 @@ static const struct dib0070_lna_match dib0070_lna[] = {
291 { 0xffffffff, 7 }, 291 { 0xffffffff, 7 },
292}; 292};
293 293
294#define LPF 100 // define for the loop filter 100kHz by default 16-07-06 294#define LPF 100
295static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) 295static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
296{ 296{
297 struct dib0070_state *state = fe->tuner_priv; 297 struct dib0070_state *state = fe->tuner_priv;
@@ -313,7 +313,7 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
313 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2))) 313 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
314 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) 314 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
315 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))) 315 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
316 freq += 850; 316 freq += 850;
317#endif 317#endif
318 if (state->current_rf != freq) { 318 if (state->current_rf != freq) {
319 319
@@ -340,95 +340,95 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
340 } 340 }
341 341
342 if (*tune_state == CT_TUNER_START) { 342 if (*tune_state == CT_TUNER_START) {
343 dprintk( "Tuning for Band: %hd (%d kHz)", band, freq); 343 dprintk("Tuning for Band: %hd (%d kHz)", band, freq);
344 if (state->current_rf != freq) { 344 if (state->current_rf != freq) {
345 u8 REFDIV; 345 u8 REFDIV;
346 u32 FBDiv, Rest, FREF, VCOF_kHz; 346 u32 FBDiv, Rest, FREF, VCOF_kHz;
347 u8 Den; 347 u8 Den;
348 348
349 state->current_rf = freq; 349 state->current_rf = freq;
350 state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7); 350 state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
351 351
352 352
353 dib0070_write_reg(state, 0x17, 0x30); 353 dib0070_write_reg(state, 0x17, 0x30);
354 354
355 355
356 VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2; 356 VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
357 357
358 switch (band) { 358 switch (band) {
359 case BAND_VHF: 359 case BAND_VHF:
360 REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000); 360 REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
361 break; 361 break;
362 case BAND_FM: 362 case BAND_FM:
363 REFDIV = (u8) ((state->cfg->clock_khz) / 1000); 363 REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
364 break; 364 break;
365 default: 365 default:
366 REFDIV = (u8) ( state->cfg->clock_khz / 10000); 366 REFDIV = (u8) (state->cfg->clock_khz / 10000);
367 break; 367 break;
368 } 368 }
369 FREF = state->cfg->clock_khz / REFDIV; 369 FREF = state->cfg->clock_khz / REFDIV;
370 370
371 371
372 372
373 switch (state->revision) { 373 switch (state->revision) {
374 case DIB0070S_P1A: 374 case DIB0070S_P1A:
375 FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF); 375 FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
376 Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF; 376 Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
377 break; 377 break;
378 378
379 case DIB0070_P1G: 379 case DIB0070_P1G:
380 case DIB0070_P1F: 380 case DIB0070_P1F:
381 default: 381 default:
382 FBDiv = (freq / (FREF / 2)); 382 FBDiv = (freq / (FREF / 2));
383 Rest = 2 * freq - FBDiv * FREF; 383 Rest = 2 * freq - FBDiv * FREF;
384 break; 384 break;
385 } 385 }
386 386
387 if (Rest < LPF) 387 if (Rest < LPF)
388 Rest = 0; 388 Rest = 0;
389 else if (Rest < 2 * LPF) 389 else if (Rest < 2 * LPF)
390 Rest = 2 * LPF; 390 Rest = 2 * LPF;
391 else if (Rest > (FREF - LPF)) { 391 else if (Rest > (FREF - LPF)) {
392 Rest = 0; 392 Rest = 0;
393 FBDiv += 1; 393 FBDiv += 1;
394 } else if (Rest > (FREF - 2 * LPF)) 394 } else if (Rest > (FREF - 2 * LPF))
395 Rest = FREF - 2 * LPF; 395 Rest = FREF - 2 * LPF;
396 Rest = (Rest * 6528) / (FREF / 10); 396 Rest = (Rest * 6528) / (FREF / 10);
397 397
398 Den = 1; 398 Den = 1;
399 if (Rest > 0) { 399 if (Rest > 0) {
400 state->lo4 |= (1 << 14) | (1 << 12); 400 state->lo4 |= (1 << 14) | (1 << 12);
401 Den = 255; 401 Den = 255;
402 } 402 }
403 403
404 404
405 dib0070_write_reg(state, 0x11, (u16)FBDiv); 405 dib0070_write_reg(state, 0x11, (u16)FBDiv);
406 dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV); 406 dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
407 dib0070_write_reg(state, 0x13, (u16) Rest); 407 dib0070_write_reg(state, 0x13, (u16) Rest);
408 408
409 if (state->revision == DIB0070S_P1A) { 409 if (state->revision == DIB0070S_P1A) {
410 410
411 if (band == BAND_SBAND) { 411 if (band == BAND_SBAND) {
412 dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0); 412 dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
413 dib0070_write_reg(state, 0x1d,0xFFFF); 413 dib0070_write_reg(state, 0x1d, 0xFFFF);
414 } else 414 } else
415 dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1); 415 dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
416 } 416 }
417 417
418 dib0070_write_reg(state, 0x20, 418 dib0070_write_reg(state, 0x20,
419 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable); 419 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
420 420
421 dprintk( "REFDIV: %hd, FREF: %d", REFDIV, FREF); 421 dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF);
422 dprintk( "FBDIV: %d, Rest: %d", FBDiv, Rest); 422 dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest);
423 dprintk( "Num: %hd, Den: %hd, SD: %hd",(u16) Rest, Den, (state->lo4 >> 12) & 0x1); 423 dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
424 dprintk( "HFDIV code: %hd", state->current_tune_table_index->hfdiv); 424 dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv);
425 dprintk( "VCO = %hd", state->current_tune_table_index->vco_band); 425 dprintk("VCO = %hd", state->current_tune_table_index->vco_band);
426 dprintk( "VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq); 426 dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq);
427 427
428 *tune_state = CT_TUNER_STEP_0; 428 *tune_state = CT_TUNER_STEP_0;
429 } else { /* we are already tuned to this frequency - the configuration is correct */ 429 } else { /* we are already tuned to this frequency - the configuration is correct */
430 ret = 50; /* wakeup time */ 430 ret = 50; /* wakeup time */
431 *tune_state = CT_TUNER_STEP_5; 431 *tune_state = CT_TUNER_STEP_5;
432 } 432 }
433 } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) { 433 } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
434 434
@@ -437,13 +437,13 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
437 } else if (*tune_state == CT_TUNER_STEP_4) { 437 } else if (*tune_state == CT_TUNER_STEP_4) {
438 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain; 438 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
439 if (tmp != NULL) { 439 if (tmp != NULL) {
440 while (freq/1000 > tmp->freq) /* find the right one */ 440 while (freq/1000 > tmp->freq) /* find the right one */
441 tmp++; 441 tmp++;
442 dib0070_write_reg(state, 0x0f, 442 dib0070_write_reg(state, 0x0f,
443 (0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (state-> 443 (0 << 15) | (1 << 14) | (3 << 12)
444 current_tune_table_index-> 444 | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7)
445 wbdmux << 0)); 445 | (state->current_tune_table_index->wbdmux << 0));
446 state->wbd_gain_current = tmp->wbd_gain_val; 446 state->wbd_gain_current = tmp->wbd_gain_val;
447 } else { 447 } else {
448 dib0070_write_reg(state, 0x0f, 448 dib0070_write_reg(state, 0x0f,
449 (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index-> 449 (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index->
@@ -483,7 +483,7 @@ static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters
483 do { 483 do {
484 ret = dib0070_tune_digital(fe, p); 484 ret = dib0070_tune_digital(fe, p);
485 if (ret != FE_CALLBACK_TIME_NEVER) 485 if (ret != FE_CALLBACK_TIME_NEVER)
486 msleep(ret/10); 486 msleep(ret/10);
487 else 487 else
488 break; 488 break;
489 } while (state->tune_state != CT_TUNER_STOP); 489 } while (state->tune_state != CT_TUNER_STOP);
@@ -512,18 +512,20 @@ u8 dib0070_get_rf_output(struct dvb_frontend *fe)
512 struct dib0070_state *state = fe->tuner_priv; 512 struct dib0070_state *state = fe->tuner_priv;
513 return (dib0070_read_reg(state, 0x07) >> 11) & 0x3; 513 return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
514} 514}
515
516EXPORT_SYMBOL(dib0070_get_rf_output); 515EXPORT_SYMBOL(dib0070_get_rf_output);
516
517int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no) 517int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no)
518{ 518{
519 struct dib0070_state *state = fe->tuner_priv; 519 struct dib0070_state *state = fe->tuner_priv;
520 u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff; 520 u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
521 if (no > 3) no = 3; 521 if (no > 3)
522 if (no < 1) no = 1; 522 no = 3;
523 if (no < 1)
524 no = 1;
523 return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11)); 525 return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
524} 526}
525
526EXPORT_SYMBOL(dib0070_set_rf_output); 527EXPORT_SYMBOL(dib0070_set_rf_output);
528
527static const u16 dib0070_p1f_defaults[] = 529static const u16 dib0070_p1f_defaults[] =
528 530
529{ 531{
@@ -582,7 +584,7 @@ static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
582 u8 gain; 584 u8 gain;
583 for (gain = 6; gain < 8; gain++) { 585 for (gain = 6; gain < 8; gain++) {
584 state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2); 586 state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
585 dprintk( "Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]); 587 dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]);
586 } 588 }
587} 589}
588 590
@@ -622,10 +624,10 @@ static int dib0070_reset(struct dvb_frontend *fe)
622 state->revision = DIB0070S_P1A; 624 state->revision = DIB0070S_P1A;
623 625
624 /* P1F or not */ 626 /* P1F or not */
625 dprintk( "Revision: %x", state->revision); 627 dprintk("Revision: %x", state->revision);
626 628
627 if (state->revision == DIB0070_P1D) { 629 if (state->revision == DIB0070_P1D) {
628 dprintk( "Error: this driver is not to be used meant for P1D or earlier"); 630 dprintk("Error: this driver is not to be used meant for P1D or earlier");
629 return -EINVAL; 631 return -EINVAL;
630 } 632 }
631 633
@@ -702,7 +704,7 @@ static const struct dvb_tuner_ops dib0070_ops = {
702// .get_bandwidth = dib0070_get_bandwidth 704// .get_bandwidth = dib0070_get_bandwidth
703}; 705};
704 706
705struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg) 707struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
706{ 708{
707 struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL); 709 struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
708 if (state == NULL) 710 if (state == NULL)
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
index e37d32dbd5c5..614552709a6f 100644
--- a/drivers/media/dvb/frontends/dib0090.c
+++ b/drivers/media/dvb/frontends/dib0090.c
@@ -149,8 +149,8 @@ static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
149{ 149{
150 u8 b[2]; 150 u8 b[2];
151 struct i2c_msg msg[2] = { 151 struct i2c_msg msg[2] = {
152 {.addr = state->config->i2c_address,.flags = 0,.buf = &reg,.len = 1}, 152 {.addr = state->config->i2c_address, .flags = 0, .buf = &reg, .len = 1},
153 {.addr = state->config->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2}, 153 {.addr = state->config->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2},
154 }; 154 };
155 if (i2c_transfer(state->i2c, msg, 2) != 2) { 155 if (i2c_transfer(state->i2c, msg, 2) != 2) {
156 printk(KERN_WARNING "DiB0090 I2C read failed\n"); 156 printk(KERN_WARNING "DiB0090 I2C read failed\n");
@@ -162,7 +162,7 @@ static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
162static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) 162static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
163{ 163{
164 u8 b[3] = { reg & 0xff, val >> 8, val & 0xff }; 164 u8 b[3] = { reg & 0xff, val >> 8, val & 0xff };
165 struct i2c_msg msg = {.addr = state->config->i2c_address,.flags = 0,.buf = b,.len = 3 }; 165 struct i2c_msg msg = {.addr = state->config->i2c_address, .flags = 0, .buf = b, .len = 3 };
166 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 166 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
167 printk(KERN_WARNING "DiB0090 I2C write failed\n"); 167 printk(KERN_WARNING "DiB0090 I2C write failed\n");
168 return -EREMOTEIO; 168 return -EREMOTEIO;
@@ -287,12 +287,12 @@ extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
287{ 287{
288 struct dib0090_state *state = fe->tuner_priv; 288 struct dib0090_state *state = fe->tuner_priv;
289 if (fast) 289 if (fast)
290 dib0090_write_reg(state, 0x04, 0); //1kHz 290 dib0090_write_reg(state, 0x04, 0);
291 else 291 else
292 dib0090_write_reg(state, 0x04, 1); //almost frozen 292 dib0090_write_reg(state, 0x04, 1);
293} 293}
294
295EXPORT_SYMBOL(dib0090_dcc_freq); 294EXPORT_SYMBOL(dib0090_dcc_freq);
295
296static const u16 rf_ramp_pwm_cband[] = { 296static const u16 rf_ramp_pwm_cband[] = {
297 0, /* max RF gain in 10th of dB */ 297 0, /* max RF gain in 10th of dB */
298 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */ 298 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
@@ -616,11 +616,11 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
616 else 616 else
617 dib0090_write_reg(state, 0x32, (0 << 11)); 617 dib0090_write_reg(state, 0x32, (0 << 11));
618 618
619 dib0090_write_reg(state, 0x39, (1 << 10)); // 0 gain by default 619 dib0090_write_reg(state, 0x39, (1 << 10));
620 } 620 }
621} 621}
622
623EXPORT_SYMBOL(dib0090_pwm_gain_reset); 622EXPORT_SYMBOL(dib0090_pwm_gain_reset);
623
624int dib0090_gain_control(struct dvb_frontend *fe) 624int dib0090_gain_control(struct dvb_frontend *fe)
625{ 625{
626 struct dib0090_state *state = fe->tuner_priv; 626 struct dib0090_state *state = fe->tuner_priv;
@@ -760,7 +760,7 @@ int dib0090_gain_control(struct dvb_frontend *fe)
760#ifdef DEBUG_AGC 760#ifdef DEBUG_AGC
761 dprintk 761 dprintk
762 ("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm", 762 ("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
763 (u32) fe->id, (u32) * tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val, 763 (u32) fe->id, (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
764 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA)); 764 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
765#endif 765#endif
766 } 766 }
@@ -770,8 +770,8 @@ int dib0090_gain_control(struct dvb_frontend *fe)
770 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); 770 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
771 return ret; 771 return ret;
772} 772}
773
774EXPORT_SYMBOL(dib0090_gain_control); 773EXPORT_SYMBOL(dib0090_gain_control);
774
775void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt) 775void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
776{ 776{
777 struct dib0090_state *state = fe->tuner_priv; 777 struct dib0090_state *state = fe->tuner_priv;
@@ -784,15 +784,15 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 *
784 if (rflt) 784 if (rflt)
785 *rflt = (state->rf_lt_def >> 10) & 0x7; 785 *rflt = (state->rf_lt_def >> 10) & 0x7;
786} 786}
787
788EXPORT_SYMBOL(dib0090_get_current_gain); 787EXPORT_SYMBOL(dib0090_get_current_gain);
788
789u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner) 789u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner)
790{ 790{
791 struct dib0090_state *st = tuner->tuner_priv; 791 struct dib0090_state *st = tuner->tuner_priv;
792 return st->wbd_offset; 792 return st->wbd_offset;
793} 793}
794
795EXPORT_SYMBOL(dib0090_get_wbd_offset); 794EXPORT_SYMBOL(dib0090_get_wbd_offset);
795
796static const u16 dib0090_defaults[] = { 796static const u16 dib0090_defaults[] = {
797 797
798 25, 0x01, 798 25, 0x01,
@@ -891,7 +891,7 @@ static int dib0090_reset(struct dvb_frontend *fe)
891 return 0; 891 return 0;
892} 892}
893 893
894#define steps(u) (((u)>15)?((u)-16):(u)) 894#define steps(u) (((u) > 15) ? ((u)-16) : (u))
895#define INTERN_WAIT 10 895#define INTERN_WAIT 10
896static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state) 896static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state)
897{ 897{
@@ -1439,7 +1439,6 @@ enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
1439 1439
1440 return state->tune_state; 1440 return state->tune_state;
1441} 1441}
1442
1443EXPORT_SYMBOL(dib0090_get_tune_state); 1442EXPORT_SYMBOL(dib0090_get_tune_state);
1444 1443
1445int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state) 1444int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
@@ -1449,7 +1448,6 @@ int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
1449 state->tune_state = tune_state; 1448 state->tune_state = tune_state;
1450 return 0; 1449 return 0;
1451} 1450}
1452
1453EXPORT_SYMBOL(dib0090_set_tune_state); 1451EXPORT_SYMBOL(dib0090_set_tune_state);
1454 1452
1455static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency) 1453static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
@@ -1516,7 +1514,6 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
1516 fe->tuner_priv = NULL; 1514 fe->tuner_priv = NULL;
1517 return NULL; 1515 return NULL;
1518} 1516}
1519
1520EXPORT_SYMBOL(dib0090_register); 1517EXPORT_SYMBOL(dib0090_register);
1521 1518
1522MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); 1519MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
diff --git a/drivers/media/dvb/frontends/dib0090.h b/drivers/media/dvb/frontends/dib0090.h
index d72b7d758aa6..83cc8ae9ba3e 100644
--- a/drivers/media/dvb/frontends/dib0090.h
+++ b/drivers/media/dvb/frontends/dib0090.h
@@ -24,7 +24,7 @@ struct dib0090_io_config {
24 u8 pll_loopdiv:6; 24 u8 pll_loopdiv:6;
25 25
26 u8 adc_clock_ratio; /* valid is 8, 7 ,6 */ 26 u8 adc_clock_ratio; /* valid is 8, 7 ,6 */
27 u16 pll_int_loop_filt; // internal loop filt value. If not fill in , default is 8165 27 u16 pll_int_loop_filt;
28}; 28};
29 29
30struct dib0090_config { 30struct dib0090_config {
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c
index b924e7eec5ac..5218a5c19d1f 100644
--- a/drivers/media/dvb/frontends/dib8000.c
+++ b/drivers/media/dvb/frontends/dib8000.c
@@ -937,21 +937,21 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
937 937
938static const int32_t lut_1000ln_mant[] = 938static const int32_t lut_1000ln_mant[] =
939{ 939{
940 908,7003,7090,7170,7244,7313,7377,7438,7495,7549,7600 940 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
941}; 941};
942 942
943int32_t dib8000_get_adc_power(struct dvb_frontend *fe, uint8_t mode) 943int32_t dib8000_get_adc_power(struct dvb_frontend *fe, uint8_t mode)
944{ 944{
945 struct dib8000_state *state = fe->demodulator_priv; 945 struct dib8000_state *state = fe->demodulator_priv;
946 uint32_t ix =0, tmp_val =0, exp = 0, mant = 0; 946 uint32_t ix = 0, tmp_val = 0, exp = 0, mant = 0;
947 int32_t val; 947 int32_t val;
948 948
949 val = dib8000_read32(state, 384); 949 val = dib8000_read32(state, 384);
950 /* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */ 950 /* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */
951 if(mode) { 951 if (mode) {
952 tmp_val = val; 952 tmp_val = val;
953 while(tmp_val>>=1) 953 while (tmp_val >>= 1)
954 exp++; 954 exp++;
955 mant = (val * 1000 / (1<<exp)); 955 mant = (val * 1000 / (1<<exp));
956 ix = (uint8_t)((mant-1000)/100); /* index of the LUT */ 956 ix = (uint8_t)((mant-1000)/100); /* index of the LUT */
957 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */ 957 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */
@@ -1876,14 +1876,14 @@ static int dib8000_sleep(struct dvb_frontend *fe)
1876 } 1876 }
1877} 1877}
1878 1878
1879enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend* fe) 1879enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
1880{ 1880{
1881 struct dib8000_state *state = fe->demodulator_priv; 1881 struct dib8000_state *state = fe->demodulator_priv;
1882 return state->tune_state; 1882 return state->tune_state;
1883} 1883}
1884EXPORT_SYMBOL(dib8000_get_tune_state); 1884EXPORT_SYMBOL(dib8000_get_tune_state);
1885 1885
1886int dib8000_set_tune_state(struct dvb_frontend* fe, enum frontend_tune_state tune_state) 1886int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
1887{ 1887{
1888 struct dib8000_state *state = fe->demodulator_priv; 1888 struct dib8000_state *state = fe->demodulator_priv;
1889 state->tune_state = tune_state; 1889 state->tune_state = tune_state;
diff --git a/drivers/media/dvb/frontends/dib8000.h b/drivers/media/dvb/frontends/dib8000.h
index de05a0ae9d98..d99619ae983c 100644
--- a/drivers/media/dvb/frontends/dib8000.h
+++ b/drivers/media/dvb/frontends/dib8000.h
@@ -46,8 +46,8 @@ extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
46extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value); 46extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value);
47extern int dib8000_pid_filter_ctrl(struct dvb_frontend *, u8 onoff); 47extern int dib8000_pid_filter_ctrl(struct dvb_frontend *, u8 onoff);
48extern int dib8000_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff); 48extern int dib8000_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
49extern int dib8000_set_tune_state(struct dvb_frontend* fe, enum frontend_tune_state tune_state); 49extern int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state);
50extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend* fe); 50extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe);
51extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe); 51extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe);
52extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode); 52extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode);
53#else 53#else
@@ -92,12 +92,12 @@ static inline int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8
92 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 92 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
93 return -ENODEV; 93 return -ENODEV;
94} 94}
95static inline int dib8000_set_tune_state(struct dvb_frontend* fe, enum frontend_tune_state tune_state) 95static inline int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
96{ 96{
97 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 97 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
98 return -ENODEV; 98 return -ENODEV;
99} 99}
100static inline enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend* fe) 100static inline enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
101{ 101{
102 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 102 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
103 return CT_SHUTDOWN, 103 return CT_SHUTDOWN,
diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h
index 06328d8742f8..4f5d141a308d 100644
--- a/drivers/media/dvb/frontends/dibx000_common.h
+++ b/drivers/media/dvb/frontends/dibx000_common.h
@@ -45,7 +45,7 @@ extern u32 systime(void);
45#define BAND_FM 0x10 45#define BAND_FM 0x10
46#define BAND_CBAND 0x20 46#define BAND_CBAND 0x20
47 47
48#define BAND_OF_FREQUENCY(freq_kHz) ( (freq_kHz) <= 170000 ? BAND_CBAND : \ 48#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
49 (freq_kHz) <= 115000 ? BAND_FM : \ 49 (freq_kHz) <= 115000 ? BAND_FM : \
50 (freq_kHz) <= 250000 ? BAND_VHF : \ 50 (freq_kHz) <= 250000 ? BAND_VHF : \
51 (freq_kHz) <= 863000 ? BAND_UHF : \ 51 (freq_kHz) <= 863000 ? BAND_UHF : \
@@ -214,6 +214,6 @@ struct dvb_frontend_parametersContext {
214 214
215#define FE_CALLBACK_TIME_NEVER 0xffffffff 215#define FE_CALLBACK_TIME_NEVER 0xffffffff
216 216
217#define ABS(x) ((x<0)?(-x):(x)) 217#define ABS(x) ((x < 0) ? (-x) : (x))
218 218
219#endif 219#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 12:49:37 -0500