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authorPekon Gupta <pekon@ti.com>2014-05-19 05:15:46 -0400
committerTony Lindgren <tony@atomide.com>2014-05-27 17:22:31 -0400
commit99ffa6425f1b9ac39c5e9946c1c286f687b97c3e (patch)
treeacf10444f4b64f6ff73d3223a2e73aa7e20ca405
parent2e091d13e65d26f21159323b95b426e5bc42670c (diff)
ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Adds pinmux and DT node for Micron (MT29F4G08AB) x8 NAND device present on am437x-gp-evm board. (1) As NAND Flash data lines are muxed with eMMC, Thus at a given time either eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled: (a) By dynamically driving following GPIO pin from software SPI2_CS0(GPIO) == 0 NAND is selected (default) SPI2_CS0(GPIO) == 1 eMMC is selected (b) By statically using Jumper (J89) on the board (2) As NAND device connnected to this board has page-size=4K and oob-size=224, So ROM code expects boot-loaders to be flashed in BCH16 ECC scheme for NAND boot. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts108
1 files changed, 108 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 30ace1b399ee..f432685957b8 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -150,6 +150,27 @@
150 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 150 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
151 >; 151 >;
152 }; 152 };
153
154 nand_flash_x8: nand_flash_x8 {
155 pinctrl-single,pins = <
156 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
157 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
158 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
159 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
160 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
161 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
162 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
163 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
164 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
165 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
166 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
167 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
168 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
169 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
170 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
171 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
172 >;
173 };
153}; 174};
154 175
155&i2c0 { 176&i2c0 {
@@ -246,3 +267,90 @@
246 phy_id = <&davinci_mdio>, <0>; 267 phy_id = <&davinci_mdio>, <0>;
247 phy-mode = "rgmii"; 268 phy-mode = "rgmii";
248}; 269};
270
271&elm {
272 status = "okay";
273};
274
275&gpmc {
276 status = "okay";
277 pinctrl-names = "default";
278 pinctrl-0 = <&nand_flash_x8>;
279 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
280 nand@0,0 {
281 reg = <0 0 4>; /* device IO registers */
282 ti,nand-ecc-opt = "bch8";
283 ti,elm-id = <&elm>;
284 nand-bus-width = <8>;
285 gpmc,device-width = <1>;
286 gpmc,sync-clk-ps = <0>;
287 gpmc,cs-on-ns = <0>;
288 gpmc,cs-rd-off-ns = <40>;
289 gpmc,cs-wr-off-ns = <40>;
290 gpmc,adv-on-ns = <0>;
291 gpmc,adv-rd-off-ns = <25>;
292 gpmc,adv-wr-off-ns = <25>;
293 gpmc,we-on-ns = <0>;
294 gpmc,we-off-ns = <20>;
295 gpmc,oe-on-ns = <3>;
296 gpmc,oe-off-ns = <30>;
297 gpmc,access-ns = <30>;
298 gpmc,rd-cycle-ns = <40>;
299 gpmc,wr-cycle-ns = <40>;
300 gpmc,wait-pin = <0>;
301 gpmc,wait-on-read;
302 gpmc,wait-on-write;
303 gpmc,bus-turnaround-ns = <0>;
304 gpmc,cycle2cycle-delay-ns = <0>;
305 gpmc,clk-activation-ns = <0>;
306 gpmc,wait-monitoring-ns = <0>;
307 gpmc,wr-access-ns = <40>;
308 gpmc,wr-data-mux-bus-ns = <0>;
309 /* MTD partition table */
310 /* All SPL-* partitions are sized to minimal length
311 * which can be independently programmable. For
312 * NAND flash this is equal to size of erase-block */
313 #address-cells = <1>;
314 #size-cells = <1>;
315 partition@0 {
316 label = "NAND.SPL";
317 reg = <0x00000000 0x00040000>;
318 };
319 partition@1 {
320 label = "NAND.SPL.backup1";
321 reg = <0x00040000 0x00040000>;
322 };
323 partition@2 {
324 label = "NAND.SPL.backup2";
325 reg = <0x00080000 0x00040000>;
326 };
327 partition@3 {
328 label = "NAND.SPL.backup3";
329 reg = <0x000c0000 0x00040000>;
330 };
331 partition@4 {
332 label = "NAND.u-boot-spl-os";
333 reg = <0x00100000 0x00080000>;
334 };
335 partition@5 {
336 label = "NAND.u-boot";
337 reg = <0x00180000 0x00100000>;
338 };
339 partition@6 {
340 label = "NAND.u-boot-env";
341 reg = <0x00280000 0x00040000>;
342 };
343 partition@7 {
344 label = "NAND.u-boot-env.backup1";
345 reg = <0x002c0000 0x00040000>;
346 };
347 partition@8 {
348 label = "NAND.kernel";
349 reg = <0x00300000 0x00700000>;
350 };
351 partition@9 {
352 label = "NAND.file-system";
353 reg = <0x00a00000 0x1f600000>;
354 };
355 };
356};