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authorJacek Anaszewski <j.anaszewski@samsung.com>2014-01-16 06:26:32 -0500
committerMauro Carvalho Chehab <m.chehab@samsung.com>2014-03-14 09:37:24 -0400
commit9982d82eecb37956a4c70293b304b546c6207b70 (patch)
treeb438ee63e9a31e5a30f25fcb65ac699aef2fbfb9
parent34947b8aebe3f2d4eceb65fceafa92bf8dc97d96 (diff)
[media] s5p-jpeg: Fix broken indentation in jpeg-regs.h
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
-rw-r--r--drivers/media/platform/s5p-jpeg/jpeg-regs.h24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-regs.h b/drivers/media/platform/s5p-jpeg/jpeg-regs.h
index 33f2c7374cfd..57fb05bb8c77 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-regs.h
+++ b/drivers/media/platform/s5p-jpeg/jpeg-regs.h
@@ -210,19 +210,19 @@
210 210
211/* JPEG CNTL Register bit */ 211/* JPEG CNTL Register bit */
212#define EXYNOS4_ENC_DEC_MODE_MASK (0xfffffffc << 0) 212#define EXYNOS4_ENC_DEC_MODE_MASK (0xfffffffc << 0)
213#define EXYNOS4_DEC_MODE (1 << 0) 213#define EXYNOS4_DEC_MODE (1 << 0)
214#define EXYNOS4_ENC_MODE (1 << 1) 214#define EXYNOS4_ENC_MODE (1 << 1)
215#define EXYNOS4_AUTO_RST_MARKER (1 << 2) 215#define EXYNOS4_AUTO_RST_MARKER (1 << 2)
216#define EXYNOS4_RST_INTERVAL_SHIFT 3 216#define EXYNOS4_RST_INTERVAL_SHIFT 3
217#define EXYNOS4_RST_INTERVAL(x) (((x) & 0xffff) \ 217#define EXYNOS4_RST_INTERVAL(x) (((x) & 0xffff) \
218 << EXYNOS4_RST_INTERVAL_SHIFT) 218 << EXYNOS4_RST_INTERVAL_SHIFT)
219#define EXYNOS4_HUF_TBL_EN (1 << 19) 219#define EXYNOS4_HUF_TBL_EN (1 << 19)
220#define EXYNOS4_HOR_SCALING_SHIFT 20 220#define EXYNOS4_HOR_SCALING_SHIFT 20
221#define EXYNOS4_HOR_SCALING_MASK (3 << EXYNOS4_HOR_SCALING_SHIFT) 221#define EXYNOS4_HOR_SCALING_MASK (3 << EXYNOS4_HOR_SCALING_SHIFT)
222#define EXYNOS4_HOR_SCALING(x) (((x) & 0x3) \ 222#define EXYNOS4_HOR_SCALING(x) (((x) & 0x3) \
223 << EXYNOS4_HOR_SCALING_SHIFT) 223 << EXYNOS4_HOR_SCALING_SHIFT)
224#define EXYNOS4_VER_SCALING_SHIFT 22 224#define EXYNOS4_VER_SCALING_SHIFT 22
225#define EXYNOS4_VER_SCALING_MASK (3 << EXYNOS4_VER_SCALING_SHIFT) 225#define EXYNOS4_VER_SCALING_MASK (3 << EXYNOS4_VER_SCALING_SHIFT)
226#define EXYNOS4_VER_SCALING(x) (((x) & 0x3) \ 226#define EXYNOS4_VER_SCALING(x) (((x) & 0x3) \
227 << EXYNOS4_VER_SCALING_SHIFT) 227 << EXYNOS4_VER_SCALING_SHIFT)
228#define EXYNOS4_PADDING (1 << 27) 228#define EXYNOS4_PADDING (1 << 27)
@@ -238,8 +238,8 @@
238#define EXYNOS4_FRAME_ERR_EN (1 << 4) 238#define EXYNOS4_FRAME_ERR_EN (1 << 4)
239#define EXYNOS4_INT_EN_ALL (0x1f << 0) 239#define EXYNOS4_INT_EN_ALL (0x1f << 0)
240 240
241#define EXYNOS4_MOD_REG_PROC_ENC (0 << 3) 241#define EXYNOS4_MOD_REG_PROC_ENC (0 << 3)
242#define EXYNOS4_MOD_REG_PROC_DEC (1 << 3) 242#define EXYNOS4_MOD_REG_PROC_DEC (1 << 3)
243 243
244#define EXYNOS4_MOD_REG_SUBSAMPLE_444 (0 << 0) 244#define EXYNOS4_MOD_REG_SUBSAMPLE_444 (0 << 0)
245#define EXYNOS4_MOD_REG_SUBSAMPLE_422 (1 << 0) 245#define EXYNOS4_MOD_REG_SUBSAMPLE_422 (1 << 0)
@@ -270,7 +270,7 @@
270#define EXYNOS4_DEC_YUV_420_IMG (4 << 0) 270#define EXYNOS4_DEC_YUV_420_IMG (4 << 0)
271 271
272#define EXYNOS4_GRAY_IMG_IP_SHIFT 3 272#define EXYNOS4_GRAY_IMG_IP_SHIFT 3
273#define EXYNOS4_GRAY_IMG_IP_MASK (7 << EXYNOS4_GRAY_IMG_IP_SHIFT) 273#define EXYNOS4_GRAY_IMG_IP_MASK (7 << EXYNOS4_GRAY_IMG_IP_SHIFT)
274#define EXYNOS4_GRAY_IMG_IP (4 << EXYNOS4_GRAY_IMG_IP_SHIFT) 274#define EXYNOS4_GRAY_IMG_IP (4 << EXYNOS4_GRAY_IMG_IP_SHIFT)
275 275
276#define EXYNOS4_RGB_IP_SHIFT 6 276#define EXYNOS4_RGB_IP_SHIFT 6
@@ -278,18 +278,18 @@
278#define EXYNOS4_RGB_IP_RGB_16BIT_IMG (4 << EXYNOS4_RGB_IP_SHIFT) 278#define EXYNOS4_RGB_IP_RGB_16BIT_IMG (4 << EXYNOS4_RGB_IP_SHIFT)
279#define EXYNOS4_RGB_IP_RGB_32BIT_IMG (5 << EXYNOS4_RGB_IP_SHIFT) 279#define EXYNOS4_RGB_IP_RGB_32BIT_IMG (5 << EXYNOS4_RGB_IP_SHIFT)
280 280
281#define EXYNOS4_YUV_444_IP_SHIFT 9 281#define EXYNOS4_YUV_444_IP_SHIFT 9
282#define EXYNOS4_YUV_444_IP_MASK (7 << EXYNOS4_YUV_444_IP_SHIFT) 282#define EXYNOS4_YUV_444_IP_MASK (7 << EXYNOS4_YUV_444_IP_SHIFT)
283#define EXYNOS4_YUV_444_IP_YUV_444_2P_IMG (4 << EXYNOS4_YUV_444_IP_SHIFT) 283#define EXYNOS4_YUV_444_IP_YUV_444_2P_IMG (4 << EXYNOS4_YUV_444_IP_SHIFT)
284#define EXYNOS4_YUV_444_IP_YUV_444_3P_IMG (5 << EXYNOS4_YUV_444_IP_SHIFT) 284#define EXYNOS4_YUV_444_IP_YUV_444_3P_IMG (5 << EXYNOS4_YUV_444_IP_SHIFT)
285 285
286#define EXYNOS4_YUV_422_IP_SHIFT 12 286#define EXYNOS4_YUV_422_IP_SHIFT 12
287#define EXYNOS4_YUV_422_IP_MASK (7 << EXYNOS4_YUV_422_IP_SHIFT) 287#define EXYNOS4_YUV_422_IP_MASK (7 << EXYNOS4_YUV_422_IP_SHIFT)
288#define EXYNOS4_YUV_422_IP_YUV_422_1P_IMG (4 << EXYNOS4_YUV_422_IP_SHIFT) 288#define EXYNOS4_YUV_422_IP_YUV_422_1P_IMG (4 << EXYNOS4_YUV_422_IP_SHIFT)
289#define EXYNOS4_YUV_422_IP_YUV_422_2P_IMG (5 << EXYNOS4_YUV_422_IP_SHIFT) 289#define EXYNOS4_YUV_422_IP_YUV_422_2P_IMG (5 << EXYNOS4_YUV_422_IP_SHIFT)
290#define EXYNOS4_YUV_422_IP_YUV_422_3P_IMG (6 << EXYNOS4_YUV_422_IP_SHIFT) 290#define EXYNOS4_YUV_422_IP_YUV_422_3P_IMG (6 << EXYNOS4_YUV_422_IP_SHIFT)
291 291
292#define EXYNOS4_YUV_420_IP_SHIFT 15 292#define EXYNOS4_YUV_420_IP_SHIFT 15
293#define EXYNOS4_YUV_420_IP_MASK (7 << EXYNOS4_YUV_420_IP_SHIFT) 293#define EXYNOS4_YUV_420_IP_MASK (7 << EXYNOS4_YUV_420_IP_SHIFT)
294#define EXYNOS4_YUV_420_IP_YUV_420_2P_IMG (4 << EXYNOS4_YUV_420_IP_SHIFT) 294#define EXYNOS4_YUV_420_IP_YUV_420_2P_IMG (4 << EXYNOS4_YUV_420_IP_SHIFT)
295#define EXYNOS4_YUV_420_IP_YUV_420_3P_IMG (5 << EXYNOS4_YUV_420_IP_SHIFT) 295#define EXYNOS4_YUV_420_IP_YUV_420_3P_IMG (5 << EXYNOS4_YUV_420_IP_SHIFT)
@@ -303,8 +303,8 @@
303 303
304#define EXYNOS4_JPEG_DECODED_IMG_FMT_MASK 0x03 304#define EXYNOS4_JPEG_DECODED_IMG_FMT_MASK 0x03
305 305
306#define EXYNOS4_SWAP_CHROMA_CRCB (1 << 26) 306#define EXYNOS4_SWAP_CHROMA_CRCB (1 << 26)
307#define EXYNOS4_SWAP_CHROMA_CBCR (0 << 26) 307#define EXYNOS4_SWAP_CHROMA_CBCR (0 << 26)
308 308
309/* JPEG HUFF count Register bit */ 309/* JPEG HUFF count Register bit */
310#define EXYNOS4_HUFF_COUNT_MASK 0xffff 310#define EXYNOS4_HUFF_COUNT_MASK 0xffff