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authorMike Frysinger <vapier@gentoo.org>2011-06-08 18:15:18 -0400
committerMike Frysinger <vapier@gentoo.org>2011-07-23 01:18:18 -0400
commit979365ba4e4f29dd1b6f985bba66426423a26f27 (patch)
treeb692e9b230d1630f357f8901ccd04ddfe039cf12
parent4e12b08b7228a607a6183186bbe21f269a287137 (diff)
Blackfin: update anomaly lists to latest public info
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h24
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h34
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h19
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h34
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h38
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h220
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h132
7 files changed, 290 insertions, 211 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index d2f076fbbc9e..56383f7cbc07 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -11,10 +11,9 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List 14 * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
18#if __SILICON_REVISION__ < 0 17#if __SILICON_REVISION__ < 0
19# error will not work on BF518 silicon version 18# error will not work on BF518 silicon version
20#endif 19#endif
@@ -77,19 +76,29 @@
77/* False Hardware Error when RETI Points to Invalid Memory */ 76/* False Hardware Error when RETI Points to Invalid Memory */
78#define ANOMALY_05000461 (1) 77#define ANOMALY_05000461 (1)
79/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 78/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
80#define ANOMALY_05000462 (1) 79#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
81/* PLL Latches Incorrect Settings During Reset */
82#define ANOMALY_05000469 (1)
83/* Incorrect Default MSEL Value in PLL_CTL */ 80/* Incorrect Default MSEL Value in PLL_CTL */
84#define ANOMALY_05000472 (1) 81#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
85/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ 82/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
86#define ANOMALY_05000473 (1) 83#define ANOMALY_05000473 (1)
87/* TESTSET Instruction Cannot Be Interrupted */ 84/* TESTSET Instruction Cannot Be Interrupted */
88#define ANOMALY_05000477 (1) 85#define ANOMALY_05000477 (1)
89/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 86/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
90#define ANOMALY_05000481 (1) 87#define ANOMALY_05000481 (1)
91/* IFLUSH sucks at life */ 88/* PLL Latches Incorrect Settings During Reset */
89#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
90/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
91#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
92/* SPI Master Boot Can Fail Under Certain Conditions */
93#define ANOMALY_05000490 (1)
94/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
92#define ANOMALY_05000491 (1) 95#define ANOMALY_05000491 (1)
96/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
97#define ANOMALY_05000494 (1)
98/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
99#define ANOMALY_05000498 (1)
100/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
101#define ANOMALY_05000501 (1)
93 102
94/* Anomalies that don't exist on this proc */ 103/* Anomalies that don't exist on this proc */
95#define ANOMALY_05000099 (0) 104#define ANOMALY_05000099 (0)
@@ -157,6 +166,5 @@
157#define ANOMALY_05000474 (0) 166#define ANOMALY_05000474 (0)
158#define ANOMALY_05000475 (0) 167#define ANOMALY_05000475 (0)
159#define ANOMALY_05000480 (0) 168#define ANOMALY_05000480 (0)
160#define ANOMALY_05000485 (0)
161 169
162#endif 170#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index e66a7e89cd3c..688470611e15 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -11,8 +11,8 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List 14 * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
15 * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List 15 * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -57,7 +57,7 @@
57/* Incorrect Access of OTP_STATUS During otp_write() Function */ 57/* Incorrect Access of OTP_STATUS During otp_write() Function */
58#define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) 58#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
59/* Host DMA Boot Modes Are Not Functional */ 59/* Host DMA Boot Modes Are Not Functional */
60#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) 60#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
61/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 61/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
62#define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) 62#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
63/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 63/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
@@ -135,7 +135,7 @@
135/* Incorrect Default Internal Voltage Regulator Setting */ 135/* Incorrect Default Internal Voltage Regulator Setting */
136#define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) 136#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
137/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ 137/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
138#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) 138#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
139/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ 139/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
140#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) 140#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
141/* DEB2_URGENT Bit Not Functional */ 141/* DEB2_URGENT Bit Not Functional */
@@ -181,11 +181,11 @@
181/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 181/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
182#define ANOMALY_05000443 (1) 182#define ANOMALY_05000443 (1)
183/* The WURESET Bit in the SYSCR Register is not Functional */ 183/* The WURESET Bit in the SYSCR Register is not Functional */
184#define ANOMALY_05000445 (1) 184#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
185/* USB DMA Mode 1 Short Packet Data Corruption */ 185/* USB DMA Short Packet Data Corruption */
186#define ANOMALY_05000450 (1) 186#define ANOMALY_05000450 (1)
187/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ 187/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
188#define ANOMALY_05000451 (1) 188#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
189/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ 189/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
190#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) 190#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
191/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ 191/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
@@ -198,19 +198,19 @@
198#define ANOMALY_05000461 (1) 198#define ANOMALY_05000461 (1)
199/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 199/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
200#define ANOMALY_05000462 (1) 200#define ANOMALY_05000462 (1)
201/* USB Rx DMA hang */ 201/* USB Rx DMA Hang */
202#define ANOMALY_05000465 (1) 202#define ANOMALY_05000465 (1)
203/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ 203/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
204#define ANOMALY_05000466 (1) 204#define ANOMALY_05000466 (1)
205/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ 205/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
206#define ANOMALY_05000467 (1) 206#define ANOMALY_05000467 (1)
207/* PLL Latches Incorrect Settings During Reset */ 207/* PLL Latches Incorrect Settings During Reset */
208#define ANOMALY_05000469 (1) 208#define ANOMALY_05000469 (1)
209/* Incorrect Default MSEL Value in PLL_CTL */ 209/* Incorrect Default MSEL Value in PLL_CTL */
210#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) 210#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
211/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 211/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
212#define ANOMALY_05000473 (1) 212#define ANOMALY_05000473 (1)
213/* Possible Lockup Condition whem Modifying PLL from External Memory */ 213/* Possible Lockup Condition when Modifying PLL from External Memory */
214#define ANOMALY_05000475 (1) 214#define ANOMALY_05000475 (1)
215/* TESTSET Instruction Cannot Be Interrupted */ 215/* TESTSET Instruction Cannot Be Interrupted */
216#define ANOMALY_05000477 (1) 216#define ANOMALY_05000477 (1)
@@ -219,11 +219,19 @@
219/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ 219/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
220#define ANOMALY_05000483 (1) 220#define ANOMALY_05000483 (1)
221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ 221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) 222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
223/* The CODEC Zero-Cross Detect Feature is not Functional */ 223/* The CODEC Zero-Cross Detect Feature is not Functional */
224#define ANOMALY_05000487 (1) 224#define ANOMALY_05000487 (1)
225/* IFLUSH sucks at life */ 225/* SPI Master Boot Can Fail Under Certain Conditions */
226#define ANOMALY_05000490 (1)
227/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
226#define ANOMALY_05000491 (1) 228#define ANOMALY_05000491 (1)
229/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
230#define ANOMALY_05000494 (1)
231/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
232#define ANOMALY_05000498 (1)
233/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
234#define ANOMALY_05000501 (1)
227 235
228/* Anomalies that don't exist on this proc */ 236/* Anomalies that don't exist on this proc */
229#define ANOMALY_05000099 (0) 237#define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 72aa59440f82..03f2b40912a3 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List 14 * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -152,7 +152,7 @@
152#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) 152#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
153/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 153/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
154#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) 154#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
155/* False Hardware Error Exception when ISR Context Is Not Restored */ 155/* False Hardware Error when ISR Context Is Not Restored */
156#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) 156#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
157/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 157/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
158#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) 158#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
@@ -210,18 +210,25 @@
210#define ANOMALY_05000462 (1) 210#define ANOMALY_05000462 (1)
211/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ 211/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
212#define ANOMALY_05000471 (1) 212#define ANOMALY_05000471 (1)
213/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 213/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
214#define ANOMALY_05000473 (1) 214#define ANOMALY_05000473 (1)
215/* Possible Lockup Condition whem Modifying PLL from External Memory */ 215/* Possible Lockup Condition when Modifying PLL from External Memory */
216#define ANOMALY_05000475 (1) 216#define ANOMALY_05000475 (1)
217/* TESTSET Instruction Cannot Be Interrupted */ 217/* TESTSET Instruction Cannot Be Interrupted */
218#define ANOMALY_05000477 (1) 218#define ANOMALY_05000477 (1)
219/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 219/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
220#define ANOMALY_05000481 (1) 220#define ANOMALY_05000481 (1)
221/* IFLUSH sucks at life */ 221/* PLL May Latch Incorrect Values Coming Out of Reset */
222#define ANOMALY_05000489 (1)
223/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
222#define ANOMALY_05000491 (1) 224#define ANOMALY_05000491 (1)
225/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
226#define ANOMALY_05000494 (1)
227/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
228#define ANOMALY_05000501 (1)
223 229
224/* These anomalies have been "phased" out of analog.com anomaly sheets and are 230/*
231 * These anomalies have been "phased" out of analog.com anomaly sheets and are
225 * here to show running on older silicon just isn't feasible. 232 * here to show running on older silicon just isn't feasible.
226 */ 233 */
227 234
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 7f8e5a9f5db6..543cd3fb305e 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List 14 * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -44,18 +44,12 @@
44#define ANOMALY_05000119 (1) 44#define ANOMALY_05000119 (1)
45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
46#define ANOMALY_05000122 (1) 46#define ANOMALY_05000122 (1)
47/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
48#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
49/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ 47/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
50#define ANOMALY_05000180 (1) 48#define ANOMALY_05000180 (1)
51/* Instruction Cache Is Not Functional */
52#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
53/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ 49/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
54#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) 50#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
55/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 51/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
56#define ANOMALY_05000245 (1) 52#define ANOMALY_05000245 (1)
57/* Buffered CLKIN Output Is Disabled by Default */
58#define ANOMALY_05000247 (1)
59/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 53/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
60#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) 54#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
61/* EMAC TX DMA Error After an Early Frame Abort */ 55/* EMAC TX DMA Error After an Early Frame Abort */
@@ -98,7 +92,7 @@
98#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) 92#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
99/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ 93/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
100#define ANOMALY_05000280 (1) 94#define ANOMALY_05000280 (1)
101/* False Hardware Error Exception when ISR Context Is Not Restored */ 95/* False Hardware Error when ISR Context Is Not Restored */
102#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) 96#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
103/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 97/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
104#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) 98#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
@@ -162,9 +156,9 @@
162#define ANOMALY_05000461 (1) 156#define ANOMALY_05000461 (1)
163/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 157/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
164#define ANOMALY_05000462 (1) 158#define ANOMALY_05000462 (1)
165/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 159/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
166#define ANOMALY_05000473 (1) 160#define ANOMALY_05000473 (1)
167/* Possible Lockup Condition whem Modifying PLL from External Memory */ 161/* Possible Lockup Condition when Modifying PLL from External Memory */
168#define ANOMALY_05000475 (1) 162#define ANOMALY_05000475 (1)
169/* TESTSET Instruction Cannot Be Interrupted */ 163/* TESTSET Instruction Cannot Be Interrupted */
170#define ANOMALY_05000477 (1) 164#define ANOMALY_05000477 (1)
@@ -172,8 +166,26 @@
172#define ANOMALY_05000480 (__SILICON_REVISION__ < 3) 166#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
173/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 167/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
174#define ANOMALY_05000481 (1) 168#define ANOMALY_05000481 (1)
175/* IFLUSH sucks at life */ 169/* PLL May Latch Incorrect Values Coming Out of Reset */
170#define ANOMALY_05000489 (1)
171/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
176#define ANOMALY_05000491 (1) 172#define ANOMALY_05000491 (1)
173/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
174#define ANOMALY_05000494 (1)
175/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
176#define ANOMALY_05000501 (1)
177
178/*
179 * These anomalies have been "phased" out of analog.com anomaly sheets and are
180 * here to show running on older silicon just isn't feasible.
181 */
182
183/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
184#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
185/* Instruction Cache Is Not Functional */
186#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
187/* Buffered CLKIN Output Is Disabled by Default */
188#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
177 189
178/* Anomalies that don't exist on this proc */ 190/* Anomalies that don't exist on this proc */
179#define ANOMALY_05000099 (0) 191#define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 55e7d0712a94..b6ca99788710 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -11,8 +11,8 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List 14 * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
15 * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List 15 * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -56,25 +56,21 @@
56#define ANOMALY_05000229 (1) 56#define ANOMALY_05000229 (1)
57/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ 57/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
58#define ANOMALY_05000233 (1) 58#define ANOMALY_05000233 (1)
59/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
60#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
61/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 59/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
62#define ANOMALY_05000245 (1) 60#define ANOMALY_05000245 (1)
63/* Maximum External Clock Speed for Timers */ 61/* Maximum External Clock Speed for Timers */
64#define ANOMALY_05000253 (1) 62#define ANOMALY_05000253 (1)
65/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
66#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
67/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ 63/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
68#define ANOMALY_05000270 (__SILICON_REVISION__ < 4) 64#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
69/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 65/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
70#define ANOMALY_05000272 (1) 66#define ANOMALY_05000272 (ANOMALY_BF538)
71/* Writes to Synchronous SDRAM Memory May Be Lost */ 67/* Writes to Synchronous SDRAM Memory May Be Lost */
72#define ANOMALY_05000273 (__SILICON_REVISION__ < 4) 68#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
73/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 69/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
74#define ANOMALY_05000277 (__SILICON_REVISION__ < 4) 70#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
75/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 71/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
76#define ANOMALY_05000278 (__SILICON_REVISION__ < 4) 72#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
77/* False Hardware Error Exception when ISR Context Is Not Restored */ 73/* False Hardware Error when ISR Context Is Not Restored */
78#define ANOMALY_05000281 (__SILICON_REVISION__ < 4) 74#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
79/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 75/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
80#define ANOMALY_05000282 (__SILICON_REVISION__ < 4) 76#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
@@ -102,8 +98,10 @@
102#define ANOMALY_05000313 (__SILICON_REVISION__ < 4) 98#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
103/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ 99/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
104#define ANOMALY_05000315 (__SILICON_REVISION__ < 4) 100#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
101/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
102#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
105/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ 103/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
106#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) 104#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
107/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ 105/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
108#define ANOMALY_05000355 (__SILICON_REVISION__ < 5) 106#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
109/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 107/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
@@ -134,16 +132,32 @@
134#define ANOMALY_05000461 (1) 132#define ANOMALY_05000461 (1)
135/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 133/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
136#define ANOMALY_05000462 (1) 134#define ANOMALY_05000462 (1)
137/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 135/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
138#define ANOMALY_05000473 (1) 136#define ANOMALY_05000473 (1)
139/* Possible Lockup Condition whem Modifying PLL from External Memory */ 137/* Possible Lockup Condition when Modifying PLL from External Memory */
140#define ANOMALY_05000475 (1) 138#define ANOMALY_05000475 (1)
141/* TESTSET Instruction Cannot Be Interrupted */ 139/* TESTSET Instruction Cannot Be Interrupted */
142#define ANOMALY_05000477 (1) 140#define ANOMALY_05000477 (1)
143/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 141/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
144#define ANOMALY_05000481 (1) 142#define ANOMALY_05000481 (1)
145/* IFLUSH sucks at life */ 143/* PLL May Latch Incorrect Values Coming Out of Reset */
144#define ANOMALY_05000489 (1)
145/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
146#define ANOMALY_05000491 (1) 146#define ANOMALY_05000491 (1)
147/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
148#define ANOMALY_05000494 (1)
149/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
150#define ANOMALY_05000501 (1)
151
152/*
153 * These anomalies have been "phased" out of analog.com anomaly sheets and are
154 * here to show running on older silicon just isn't feasible.
155 */
156
157/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
158#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
159/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
160#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
147 161
148/* Anomalies that don't exist on this proc */ 162/* Anomalies that don't exist on this proc */
149#define ANOMALY_05000099 (0) 163#define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 9e70785bdde3..ac96ee83b00e 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List 14 * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -29,117 +29,37 @@
29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 (1) 30#define ANOMALY_05000122 (1)
31/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ 31/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
32#define ANOMALY_05000220 (1) 32#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
33/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 33/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
34#define ANOMALY_05000245 (1) 34#define ANOMALY_05000245 (1)
35/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 35/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
36#define ANOMALY_05000265 (1) 36#define ANOMALY_05000265 (1)
37/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 37/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
38#define ANOMALY_05000272 (1) 38#define ANOMALY_05000272 (1)
39/* False Hardware Error Exception when ISR Context Is Not Restored */
40#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
41/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
42#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
43/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 39/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
44#define ANOMALY_05000310 (1) 40#define ANOMALY_05000310 (1)
45/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
46#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
47/* TWI Slave Boot Mode Is Not Functional */
48#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
49/* FIFO Boot Mode Not Functional */ 41/* FIFO Boot Mode Not Functional */
50#define ANOMALY_05000325 (__SILICON_REVISION__ < 2) 42#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
51/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
52#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
53/* Incorrect Access of OTP_STATUS During otp_write() Function */
54#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
55/* Synchronous Burst Flash Boot Mode Is Not Functional */
56#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
57/* Host DMA Boot Modes Are Not Functional */
58#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
59/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
60#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
61/* Inadequate Rotary Debounce Logic Duration */
62#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
63/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
64#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
65/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
66#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
67/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
68#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
69/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
70#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
71/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
72#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
73/* USB Calibration Value Is Not Initialized */
74#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
75/* USB Calibration Value to use */
76#define ANOMALY_05000346_value 0x5411
77/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
78#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
79/* Data Lost when Core Reads SDH Data FIFO */
80#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
81/* PLL Status Register Is Inaccurate */
82#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
83/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ 43/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
84/* 44/*
85 * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing 45 * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
86 * shows that the fix itself does not cover all cases. 46 * shows that the fix itself does not cover all cases.
87 */ 47 */
88#define ANOMALY_05000353 (1) 48#define ANOMALY_05000353 (1)
89/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
90#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
91/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
92#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
93/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 49/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
94#define ANOMALY_05000357 (1) 50#define ANOMALY_05000357 (1)
95/* External Memory Read Access Hangs Core With PLL Bypass */ 51/* External Memory Read Access Hangs Core With PLL Bypass */
96#define ANOMALY_05000360 (1) 52#define ANOMALY_05000360 (1)
97/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ 53/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
98#define ANOMALY_05000365 (1) 54#define ANOMALY_05000365 (1)
99/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
100#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
101/* Addressing Conflict between Boot ROM and Asynchronous Memory */ 55/* Addressing Conflict between Boot ROM and Asynchronous Memory */
102#define ANOMALY_05000369 (1) 56#define ANOMALY_05000369 (1)
103/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
104#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
105/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 57/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
106#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) 58#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
107/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
108#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
109/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ 59/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
110#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) 60#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
111/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ 61/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
112#define ANOMALY_05000379 (1) 62#define ANOMALY_05000379 (1)
113/* 8-Bit NAND Flash Boot Mode Not Functional */
114#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
115/* Some ATAPI Modes Are Not Functional */
116#define ANOMALY_05000383 (1)
117/* Boot from OTP Memory Not Functional */
118#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
119/* bfrom_SysControl() Firmware Routine Not Functional */
120#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
121/* Programmable Preboot Settings Not Functional */
122#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
123/* CRC32 Checksum Support Not Functional */
124#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
125/* Reset Vector Must Not Be in SDRAM Memory Space */
126#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
127/* Changed Meaning of BCODE Field in SYSCR Register */
128#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
129/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
130#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
131/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
132#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
133/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
134#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
135/* Log Buffer Not Functional */
136#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
137/* Hook Routine Not Functional */
138#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
139/* Header Indirect Bit Not Functional */
140#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
141/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
142#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
143/* Lockbox SESR Disallows Certain User Interrupts */ 63/* Lockbox SESR Disallows Certain User Interrupts */
144#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) 64#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
145/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ 65/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
@@ -161,7 +81,7 @@
161/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 81/* Speculative Fetches Can Cause Undesired External FIFO Operations */
162#define ANOMALY_05000416 (1) 82#define ANOMALY_05000416 (1)
163/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ 83/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
164#define ANOMALY_05000425 (1) 84#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
165/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 85/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
166#define ANOMALY_05000426 (1) 86#define ANOMALY_05000426 (1)
167/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ 87/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
@@ -174,8 +94,6 @@
174#define ANOMALY_05000431 (__SILICON_REVISION__ < 3) 94#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
175/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ 95/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
176#define ANOMALY_05000434 (1) 96#define ANOMALY_05000434 (1)
177/* OTP Write Accesses Not Supported */
178#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
179/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 97/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
180#define ANOMALY_05000443 (1) 98#define ANOMALY_05000443 (1)
181/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ 99/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
@@ -186,34 +104,32 @@
186#define ANOMALY_05000448 (__SILICON_REVISION__ == 1) 104#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
187/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ 105/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
188#define ANOMALY_05000449 (__SILICON_REVISION__ == 1) 106#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
189/* USB DMA Mode 1 Short Packet Data Corruption */ 107/* USB DMA Short Packet Data Corruption */
190#define ANOMALY_05000450 (1) 108#define ANOMALY_05000450 (1)
191/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
192#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
193/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ 109/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
194#define ANOMALY_05000456 (1) 110#define ANOMALY_05000456 (1)
195/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ 111/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
196#define ANOMALY_05000457 (1) 112#define ANOMALY_05000457 (1)
197/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ 113/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
198#define ANOMALY_05000460 (1) 114#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
199/* False Hardware Error when RETI Points to Invalid Memory */ 115/* False Hardware Error when RETI Points to Invalid Memory */
200#define ANOMALY_05000461 (1) 116#define ANOMALY_05000461 (1)
201/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 117/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
202#define ANOMALY_05000462 (1) 118#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
203/* USB DMA RX Data Corruption */ 119/* USB DMA RX Data Corruption */
204#define ANOMALY_05000463 (1) 120#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
205/* USB TX DMA Hang */ 121/* USB TX DMA Hang */
206#define ANOMALY_05000464 (1) 122#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
207/* USB Rx DMA hang */ 123/* USB Rx DMA Hang */
208#define ANOMALY_05000465 (1) 124#define ANOMALY_05000465 (1)
209/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ 125/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
210#define ANOMALY_05000466 (1) 126#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
211/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ 127/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
212#define ANOMALY_05000467 (1) 128#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
213/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 129/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
214#define ANOMALY_05000473 (1) 130#define ANOMALY_05000473 (1)
215/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ 131/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
216#define ANOMALY_05000474 (1) 132#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
217/* TESTSET Instruction Cannot Be Interrupted */ 133/* TESTSET Instruction Cannot Be Interrupted */
218#define ANOMALY_05000477 (1) 134#define ANOMALY_05000477 (1)
219/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 135/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@@ -223,9 +139,111 @@
223/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */ 139/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
224#define ANOMALY_05000484 (__SILICON_REVISION__ < 3) 140#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
225/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ 141/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
226#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) 142#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
227/* IFLUSH sucks at life */ 143/* PLL May Latch Incorrect Values Coming Out of Reset */
144#define ANOMALY_05000489 (1)
145/* SPI Master Boot Can Fail Under Certain Conditions */
146#define ANOMALY_05000490 (1)
147/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
228#define ANOMALY_05000491 (1) 148#define ANOMALY_05000491 (1)
149/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
150#define ANOMALY_05000494 (1)
151/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
152#define ANOMALY_05000498 (1)
153/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
154#define ANOMALY_05000500 (1)
155/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
156#define ANOMALY_05000501 (1)
157/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
158#define ANOMALY_05000502 (1)
159
160/*
161 * These anomalies have been "phased" out of analog.com anomaly sheets and are
162 * here to show running on older silicon just isn't feasible.
163 */
164
165/* False Hardware Error when ISR Context Is Not Restored */
166#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
167/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
168#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
169/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
170#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
171/* TWI Slave Boot Mode Is Not Functional */
172#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
173/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
174#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
175/* Incorrect Access of OTP_STATUS During otp_write() Function */
176#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
177/* Synchronous Burst Flash Boot Mode Is Not Functional */
178#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
179/* Host DMA Boot Modes Are Not Functional */
180#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
181/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
182#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
183/* Inadequate Rotary Debounce Logic Duration */
184#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
185/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
186#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
187/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
188#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
189/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
190#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
191/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
192#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
193/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
194#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
195/* USB Calibration Value Is Not Initialized */
196#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
197/* USB Calibration Value to use */
198#define ANOMALY_05000346_value 0x5411
199/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
200#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
201/* Data Lost when Core Reads SDH Data FIFO */
202#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
203/* PLL Status Register Is Inaccurate */
204#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
205/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
206#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
207/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
208#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
209/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
210#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
211/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
212#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
213/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
214#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
215/* 8-Bit NAND Flash Boot Mode Not Functional */
216#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
217/* Boot from OTP Memory Not Functional */
218#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
219/* bfrom_SysControl() Firmware Routine Not Functional */
220#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
221/* Programmable Preboot Settings Not Functional */
222#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
223/* CRC32 Checksum Support Not Functional */
224#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
225/* Reset Vector Must Not Be in SDRAM Memory Space */
226#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
227/* Changed Meaning of BCODE Field in SYSCR Register */
228#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
229/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
230#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
231/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
232#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
233/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
234#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
235/* Log Buffer Not Functional */
236#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
237/* Hook Routine Not Functional */
238#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
239/* Header Indirect Bit Not Functional */
240#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
241/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
242#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
243/* OTP Write Accesses Not Supported */
244#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
245/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
246#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
229 247
230/* Anomalies that don't exist on this proc */ 248/* Anomalies that don't exist on this proc */
231#define ANOMALY_05000099 (0) 249#define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 22b5ab773027..836baeed303a 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List 14 * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -26,62 +26,16 @@
26#define ANOMALY_05000074 (1) 26#define ANOMALY_05000074 (1)
27/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 27/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
28#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) 28#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
29/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
30#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
31/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ 29/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
32#define ANOMALY_05000120 (1) 30#define ANOMALY_05000120 (1)
33/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 31/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
34#define ANOMALY_05000122 (1) 32#define ANOMALY_05000122 (1)
35/* Erroneous Exception when Enabling Cache */
36#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
37/* SIGNBITS Instruction Not Functional under Certain Conditions */ 33/* SIGNBITS Instruction Not Functional under Certain Conditions */
38#define ANOMALY_05000127 (1) 34#define ANOMALY_05000127 (1)
39/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
40#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
41/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
42#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
43/* Stall in multi-unit DMA operations */
44#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
45/* Allowing the SPORT RX FIFO to fill will cause an overflow */
46#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
47/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
48#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
49/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
50#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
51/* DMA and TESTSET conflict when both are accessing external memory */
52#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
53/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
54#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
55/* MDMA may lose the first few words of a descriptor chain */
56#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
57/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
58#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
59/* IMDMA S1/D1 Channel May Stall */ 35/* IMDMA S1/D1 Channel May Stall */
60#define ANOMALY_05000149 (1) 36#define ANOMALY_05000149 (1)
61/* DMA engine may lose data due to incorrect handshaking */
62#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
63/* DMA stalls when all three controllers read data from the same source */
64#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
65/* Execution stall when executing in L2 and doing external accesses */
66#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
67/* Frame Delay in SPORT Multichannel Mode */
68#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
69/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
70#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
71/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ 37/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
72#define ANOMALY_05000156 (__SILICON_REVISION__ < 4) 38#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
73/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
74#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
75/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
76#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
77/* A read from external memory may return a wrong value with data cache enabled */
78#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
79/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
80#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
81/* DMEM_CONTROL<12> is not set on Reset */
82#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
83/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
84#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
85/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ 39/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
86#define ANOMALY_05000166 (1) 40#define ANOMALY_05000166 (1)
87/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ 41/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
@@ -92,10 +46,6 @@
92#define ANOMALY_05000169 (__SILICON_REVISION__ < 5) 46#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
93/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ 47/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
94#define ANOMALY_05000171 (__SILICON_REVISION__ < 5) 48#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
95/* DSPID register values incorrect */
96#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
97/* DMA vs Core accesses to external memory */
98#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
99/* Cache Fill Buffer Data lost */ 49/* Cache Fill Buffer Data lost */
100#define ANOMALY_05000174 (__SILICON_REVISION__ < 5) 50#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
101/* Overlapping Sequencer and Memory Stalls */ 51/* Overlapping Sequencer and Memory Stalls */
@@ -124,8 +74,6 @@
124#define ANOMALY_05000189 (__SILICON_REVISION__ < 5) 74#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
125/* PPI Not Functional at Core Voltage < 1Volt */ 75/* PPI Not Functional at Core Voltage < 1Volt */
126#define ANOMALY_05000190 (1) 76#define ANOMALY_05000190 (1)
127/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
128#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
129/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ 77/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
130#define ANOMALY_05000193 (__SILICON_REVISION__ < 5) 78#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
131/* Restarting SPORT in Specific Modes May Cause Data Corruption */ 79/* Restarting SPORT in Specific Modes May Cause Data Corruption */
@@ -217,10 +165,10 @@
217/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 165/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
218#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
219/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 167/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
220#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) 168#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
221/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 169/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
222#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) 170#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
223/* False Hardware Error Exception when ISR Context Is Not Restored */ 171/* False Hardware Error when ISR Context Is Not Restored */
224/* Temporarily walk around for bug 5423 till this issue is confirmed by 172/* Temporarily walk around for bug 5423 till this issue is confirmed by
225 * official anomaly document. It looks 05000281 still exists on bf561 173 * official anomaly document. It looks 05000281 still exists on bf561
226 * v0.5. 174 * v0.5.
@@ -274,8 +222,6 @@
274#define ANOMALY_05000366 (1) 222#define ANOMALY_05000366 (1)
275/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 223/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
276#define ANOMALY_05000371 (1) 224#define ANOMALY_05000371 (1)
277/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
278#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
279/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 225/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
280#define ANOMALY_05000403 (1) 226#define ANOMALY_05000403 (1)
281/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ 227/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
@@ -298,16 +244,82 @@
298#define ANOMALY_05000462 (1) 244#define ANOMALY_05000462 (1)
299/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ 245/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
300#define ANOMALY_05000471 (1) 246#define ANOMALY_05000471 (1)
301/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 247/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
302#define ANOMALY_05000473 (1) 248#define ANOMALY_05000473 (1)
303/* Possible Lockup Condition whem Modifying PLL from External Memory */ 249/* Possible Lockup Condition when Modifying PLL from External Memory */
304#define ANOMALY_05000475 (1) 250#define ANOMALY_05000475 (1)
305/* TESTSET Instruction Cannot Be Interrupted */ 251/* TESTSET Instruction Cannot Be Interrupted */
306#define ANOMALY_05000477 (1) 252#define ANOMALY_05000477 (1)
307/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 253/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
308#define ANOMALY_05000481 (1) 254#define ANOMALY_05000481 (1)
309/* IFLUSH sucks at life */ 255/* PLL May Latch Incorrect Values Coming Out of Reset */
256#define ANOMALY_05000489 (1)
257/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
310#define ANOMALY_05000491 (1) 258#define ANOMALY_05000491 (1)
259/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
260#define ANOMALY_05000494 (1)
261/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
262#define ANOMALY_05000501 (1)
263
264/*
265 * These anomalies have been "phased" out of analog.com anomaly sheets and are
266 * here to show running on older silicon just isn't feasible.
267 */
268
269/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
270#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
271/* Erroneous Exception when Enabling Cache */
272#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
273/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
274#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
275/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
276#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
277/* Stall in multi-unit DMA operations */
278#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
279/* Allowing the SPORT RX FIFO to fill will cause an overflow */
280#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
281/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
282#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
283/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
284#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
285/* DMA and TESTSET conflict when both are accessing external memory */
286#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
287/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
288#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
289/* MDMA may lose the first few words of a descriptor chain */
290#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
291/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
292#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
293/* DMA engine may lose data due to incorrect handshaking */
294#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
295/* DMA stalls when all three controllers read data from the same source */
296#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
297/* Execution stall when executing in L2 and doing external accesses */
298#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
299/* Frame Delay in SPORT Multichannel Mode */
300#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
301/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
302#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
303/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
304#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
305/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
306#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
307/* A read from external memory may return a wrong value with data cache enabled */
308#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
309/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
310#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
311/* DMEM_CONTROL<12> is not set on Reset */
312#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
313/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
314#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
315/* DSPID register values incorrect */
316#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
317/* DMA vs Core accesses to external memory */
318#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
319/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
320#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
321/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
322#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
311 323
312/* Anomalies that don't exist on this proc */ 324/* Anomalies that don't exist on this proc */
313#define ANOMALY_05000119 (0) 325#define ANOMALY_05000119 (0)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 21:02:38 -0500