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authorPhilip Avinash <avinashphilip@ti.com>2013-01-02 08:24:49 -0500
committerPaul Walmsley <paul@pwsan.com>2013-02-08 10:10:36 -0500
commit9652d19afc23b80509e23f1d7c3f37786e50e401 (patch)
treed37bf24d8254bf6908569df7aca75b2f349b709d
parentbee76659e268ab9165e4dceee5b5410f3b22cd1c (diff)
ARM: OMAP: AM33xx hwmod: Add parent-child relationship for PWM subsystem
As part of PWM subsystem integration, PWM subsystem are sharing resources like clock across submodules (ECAP, EQEP & EHRPWM). To handle resource sharing & IP integration rework on parent child relation between PWMSS and ECAP, EQEP & EHRPWM child devices to support runtime PM. Signed-off-by: Philip Avinash <avinashphilip@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c434
1 files changed, 203 insertions, 231 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 4b1cc4d4c9a3..8441538872cd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -783,9 +783,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
783 }, 783 },
784}; 784};
785 785
786/* 786/* pwmss */
787 * 'epwmss' class: ehrpwm0,1,2 eqep0,1,2 ecap0,1,2
788 */
789static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { 787static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
790 .rev_offs = 0x0, 788 .rev_offs = 0x0,
791 .sysc_offs = 0x4, 789 .sysc_offs = 0x4,
@@ -801,67 +799,44 @@ static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
801 .sysc = &am33xx_epwmss_sysc, 799 .sysc = &am33xx_epwmss_sysc,
802}; 800};
803 801
804/* ehrpwm0 */ 802static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
805static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = { 803 .name = "ecap",
806 { .name = "int", .irq = 86 + OMAP_INTC_START, },
807 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
808 { .irq = -1 },
809}; 804};
810 805
811static struct omap_hwmod am33xx_ehrpwm0_hwmod = { 806static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
812 .name = "ehrpwm0", 807 .name = "eqep",
813 .class = &am33xx_epwmss_hwmod_class,
814 .clkdm_name = "l4ls_clkdm",
815 .mpu_irqs = am33xx_ehrpwm0_irqs,
816 .main_clk = "l4ls_gclk",
817 .prcm = {
818 .omap4 = {
819 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
820 .modulemode = MODULEMODE_SWCTRL,
821 },
822 },
823}; 808};
824 809
825/* ehrpwm1 */ 810static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
826static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = { 811 .name = "ehrpwm",
827 { .name = "int", .irq = 87 + OMAP_INTC_START, },
828 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
829 { .irq = -1 },
830}; 812};
831 813
832static struct omap_hwmod am33xx_ehrpwm1_hwmod = { 814/* epwmss0 */
833 .name = "ehrpwm1", 815static struct omap_hwmod am33xx_epwmss0_hwmod = {
816 .name = "epwmss0",
834 .class = &am33xx_epwmss_hwmod_class, 817 .class = &am33xx_epwmss_hwmod_class,
835 .clkdm_name = "l4ls_clkdm", 818 .clkdm_name = "l4ls_clkdm",
836 .mpu_irqs = am33xx_ehrpwm1_irqs,
837 .main_clk = "l4ls_gclk", 819 .main_clk = "l4ls_gclk",
838 .prcm = { 820 .prcm = {
839 .omap4 = { 821 .omap4 = {
840 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, 822 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
841 .modulemode = MODULEMODE_SWCTRL, 823 .modulemode = MODULEMODE_SWCTRL,
842 }, 824 },
843 }, 825 },
844}; 826};
845 827
846/* ehrpwm2 */ 828/* ecap0 */
847static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = { 829static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
848 { .name = "int", .irq = 39 + OMAP_INTC_START, }, 830 { .irq = 31 + OMAP_INTC_START, },
849 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
850 { .irq = -1 }, 831 { .irq = -1 },
851}; 832};
852 833
853static struct omap_hwmod am33xx_ehrpwm2_hwmod = { 834static struct omap_hwmod am33xx_ecap0_hwmod = {
854 .name = "ehrpwm2", 835 .name = "ecap0",
855 .class = &am33xx_epwmss_hwmod_class, 836 .class = &am33xx_ecap_hwmod_class,
856 .clkdm_name = "l4ls_clkdm", 837 .clkdm_name = "l4ls_clkdm",
857 .mpu_irqs = am33xx_ehrpwm2_irqs, 838 .mpu_irqs = am33xx_ecap0_irqs,
858 .main_clk = "l4ls_gclk", 839 .main_clk = "l4ls_gclk",
859 .prcm = {
860 .omap4 = {
861 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
862 .modulemode = MODULEMODE_SWCTRL,
863 },
864 },
865}; 840};
866 841
867/* eqep0 */ 842/* eqep0 */
@@ -872,29 +847,32 @@ static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
872 847
873static struct omap_hwmod am33xx_eqep0_hwmod = { 848static struct omap_hwmod am33xx_eqep0_hwmod = {
874 .name = "eqep0", 849 .name = "eqep0",
875 .class = &am33xx_epwmss_hwmod_class, 850 .class = &am33xx_eqep_hwmod_class,
876 .clkdm_name = "l4ls_clkdm", 851 .clkdm_name = "l4ls_clkdm",
877 .mpu_irqs = am33xx_eqep0_irqs, 852 .mpu_irqs = am33xx_eqep0_irqs,
878 .main_clk = "l4ls_gclk", 853 .main_clk = "l4ls_gclk",
879 .prcm = {
880 .omap4 = {
881 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
882 .modulemode = MODULEMODE_SWCTRL,
883 },
884 },
885}; 854};
886 855
887/* eqep1 */ 856/* ehrpwm0 */
888static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = { 857static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
889 { .irq = 88 + OMAP_INTC_START, }, 858 { .name = "int", .irq = 86 + OMAP_INTC_START, },
859 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
890 { .irq = -1 }, 860 { .irq = -1 },
891}; 861};
892 862
893static struct omap_hwmod am33xx_eqep1_hwmod = { 863static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
894 .name = "eqep1", 864 .name = "ehrpwm0",
865 .class = &am33xx_ehrpwm_hwmod_class,
866 .clkdm_name = "l4ls_clkdm",
867 .mpu_irqs = am33xx_ehrpwm0_irqs,
868 .main_clk = "l4ls_gclk",
869};
870
871/* epwmss1 */
872static struct omap_hwmod am33xx_epwmss1_hwmod = {
873 .name = "epwmss1",
895 .class = &am33xx_epwmss_hwmod_class, 874 .class = &am33xx_epwmss_hwmod_class,
896 .clkdm_name = "l4ls_clkdm", 875 .clkdm_name = "l4ls_clkdm",
897 .mpu_irqs = am33xx_eqep1_irqs,
898 .main_clk = "l4ls_gclk", 876 .main_clk = "l4ls_gclk",
899 .prcm = { 877 .prcm = {
900 .omap4 = { 878 .omap4 = {
@@ -904,61 +882,58 @@ static struct omap_hwmod am33xx_eqep1_hwmod = {
904 }, 882 },
905}; 883};
906 884
907/* eqep2 */ 885/* ecap1 */
908static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = { 886static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
909 { .irq = 89 + OMAP_INTC_START, }, 887 { .irq = 47 + OMAP_INTC_START, },
910 { .irq = -1 }, 888 { .irq = -1 },
911}; 889};
912 890
913static struct omap_hwmod am33xx_eqep2_hwmod = { 891static struct omap_hwmod am33xx_ecap1_hwmod = {
914 .name = "eqep2", 892 .name = "ecap1",
915 .class = &am33xx_epwmss_hwmod_class, 893 .class = &am33xx_ecap_hwmod_class,
916 .clkdm_name = "l4ls_clkdm", 894 .clkdm_name = "l4ls_clkdm",
917 .mpu_irqs = am33xx_eqep2_irqs, 895 .mpu_irqs = am33xx_ecap1_irqs,
918 .main_clk = "l4ls_gclk", 896 .main_clk = "l4ls_gclk",
919 .prcm = {
920 .omap4 = {
921 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
922 .modulemode = MODULEMODE_SWCTRL,
923 },
924 },
925}; 897};
926 898
927/* ecap0 */ 899/* eqep1 */
928static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { 900static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
929 { .irq = 31 + OMAP_INTC_START, }, 901 { .irq = 88 + OMAP_INTC_START, },
930 { .irq = -1 }, 902 { .irq = -1 },
931}; 903};
932 904
933static struct omap_hwmod am33xx_ecap0_hwmod = { 905static struct omap_hwmod am33xx_eqep1_hwmod = {
934 .name = "ecap0", 906 .name = "eqep1",
935 .class = &am33xx_epwmss_hwmod_class, 907 .class = &am33xx_eqep_hwmod_class,
936 .clkdm_name = "l4ls_clkdm", 908 .clkdm_name = "l4ls_clkdm",
937 .mpu_irqs = am33xx_ecap0_irqs, 909 .mpu_irqs = am33xx_eqep1_irqs,
938 .main_clk = "l4ls_gclk", 910 .main_clk = "l4ls_gclk",
939 .prcm = {
940 .omap4 = {
941 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
942 .modulemode = MODULEMODE_SWCTRL,
943 },
944 },
945}; 911};
946 912
947/* ecap1 */ 913/* ehrpwm1 */
948static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = { 914static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
949 { .irq = 47 + OMAP_INTC_START, }, 915 { .name = "int", .irq = 87 + OMAP_INTC_START, },
916 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
950 { .irq = -1 }, 917 { .irq = -1 },
951}; 918};
952 919
953static struct omap_hwmod am33xx_ecap1_hwmod = { 920static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
954 .name = "ecap1", 921 .name = "ehrpwm1",
922 .class = &am33xx_ehrpwm_hwmod_class,
923 .clkdm_name = "l4ls_clkdm",
924 .mpu_irqs = am33xx_ehrpwm1_irqs,
925 .main_clk = "l4ls_gclk",
926};
927
928/* epwmss2 */
929static struct omap_hwmod am33xx_epwmss2_hwmod = {
930 .name = "epwmss2",
955 .class = &am33xx_epwmss_hwmod_class, 931 .class = &am33xx_epwmss_hwmod_class,
956 .clkdm_name = "l4ls_clkdm", 932 .clkdm_name = "l4ls_clkdm",
957 .mpu_irqs = am33xx_ecap1_irqs,
958 .main_clk = "l4ls_gclk", 933 .main_clk = "l4ls_gclk",
959 .prcm = { 934 .prcm = {
960 .omap4 = { 935 .omap4 = {
961 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, 936 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
962 .modulemode = MODULEMODE_SWCTRL, 937 .modulemode = MODULEMODE_SWCTRL,
963 }, 938 },
964 }, 939 },
@@ -972,16 +947,39 @@ static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
972 947
973static struct omap_hwmod am33xx_ecap2_hwmod = { 948static struct omap_hwmod am33xx_ecap2_hwmod = {
974 .name = "ecap2", 949 .name = "ecap2",
950 .class = &am33xx_ecap_hwmod_class,
951 .clkdm_name = "l4ls_clkdm",
975 .mpu_irqs = am33xx_ecap2_irqs, 952 .mpu_irqs = am33xx_ecap2_irqs,
976 .class = &am33xx_epwmss_hwmod_class, 953 .main_clk = "l4ls_gclk",
954};
955
956/* eqep2 */
957static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
958 { .irq = 89 + OMAP_INTC_START, },
959 { .irq = -1 },
960};
961
962static struct omap_hwmod am33xx_eqep2_hwmod = {
963 .name = "eqep2",
964 .class = &am33xx_eqep_hwmod_class,
977 .clkdm_name = "l4ls_clkdm", 965 .clkdm_name = "l4ls_clkdm",
966 .mpu_irqs = am33xx_eqep2_irqs,
967 .main_clk = "l4ls_gclk",
968};
969
970/* ehrpwm2 */
971static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
972 { .name = "int", .irq = 39 + OMAP_INTC_START, },
973 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
974 { .irq = -1 },
975};
976
977static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
978 .name = "ehrpwm2",
979 .class = &am33xx_ehrpwm_hwmod_class,
980 .clkdm_name = "l4ls_clkdm",
981 .mpu_irqs = am33xx_ehrpwm2_irqs,
978 .main_clk = "l4ls_gclk", 982 .main_clk = "l4ls_gclk",
979 .prcm = {
980 .omap4 = {
981 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
982 .modulemode = MODULEMODE_SWCTRL,
983 },
984 },
985}; 983};
986 984
987/* 985/*
@@ -2607,116 +2605,106 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2607 .user = OCP_USER_MPU, 2605 .user = OCP_USER_MPU,
2608}; 2606};
2609 2607
2610/* 2608static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
2611 * Splitting the resources to handle access of PWMSS config space
2612 * and module specific part independently
2613 */
2614static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2615 { 2609 {
2616 .pa_start = 0x48300000, 2610 .pa_start = 0x48300000,
2617 .pa_end = 0x48300000 + SZ_16 - 1, 2611 .pa_end = 0x48300000 + SZ_16 - 1,
2618 .flags = ADDR_TYPE_RT 2612 .flags = ADDR_TYPE_RT
2619 }, 2613 },
2620 {
2621 .pa_start = 0x48300200,
2622 .pa_end = 0x48300200 + SZ_128 - 1,
2623 },
2624 { } 2614 { }
2625}; 2615};
2626 2616
2627static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = { 2617static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2628 .master = &am33xx_l4_ls_hwmod, 2618 .master = &am33xx_l4_ls_hwmod,
2629 .slave = &am33xx_ehrpwm0_hwmod, 2619 .slave = &am33xx_epwmss0_hwmod,
2630 .clk = "l4ls_gclk", 2620 .clk = "l4ls_gclk",
2631 .addr = am33xx_ehrpwm0_addr_space, 2621 .addr = am33xx_epwmss0_addr_space,
2632 .user = OCP_USER_MPU, 2622 .user = OCP_USER_MPU,
2633}; 2623};
2634 2624
2635/* 2625static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2636 * Splitting the resources to handle access of PWMSS config space
2637 * and module specific part independently
2638 */
2639static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2640 {
2641 .pa_start = 0x48302000,
2642 .pa_end = 0x48302000 + SZ_16 - 1,
2643 .flags = ADDR_TYPE_RT
2644 },
2645 { 2626 {
2646 .pa_start = 0x48302200, 2627 .pa_start = 0x48300100,
2647 .pa_end = 0x48302200 + SZ_128 - 1, 2628 .pa_end = 0x48300100 + SZ_128 - 1,
2648 }, 2629 },
2649 { } 2630 { }
2650}; 2631};
2651 2632
2652static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = { 2633static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2653 .master = &am33xx_l4_ls_hwmod, 2634 .master = &am33xx_epwmss0_hwmod,
2654 .slave = &am33xx_ehrpwm1_hwmod, 2635 .slave = &am33xx_ecap0_hwmod,
2655 .clk = "l4ls_gclk", 2636 .clk = "l4ls_gclk",
2656 .addr = am33xx_ehrpwm1_addr_space, 2637 .addr = am33xx_ecap0_addr_space,
2657 .user = OCP_USER_MPU, 2638 .user = OCP_USER_MPU,
2658}; 2639};
2659 2640
2660/* 2641static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2661 * Splitting the resources to handle access of PWMSS config space
2662 * and module specific part independently
2663 */
2664static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2665 { 2642 {
2666 .pa_start = 0x48304000, 2643 .pa_start = 0x48300180,
2667 .pa_end = 0x48304000 + SZ_16 - 1, 2644 .pa_end = 0x48300180 + SZ_128 - 1,
2668 .flags = ADDR_TYPE_RT
2669 }, 2645 },
2646 { }
2647};
2648
2649static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2650 .master = &am33xx_epwmss0_hwmod,
2651 .slave = &am33xx_eqep0_hwmod,
2652 .clk = "l4ls_gclk",
2653 .addr = am33xx_eqep0_addr_space,
2654 .user = OCP_USER_MPU,
2655};
2656
2657static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2670 { 2658 {
2671 .pa_start = 0x48304200, 2659 .pa_start = 0x48300200,
2672 .pa_end = 0x48304200 + SZ_128 - 1, 2660 .pa_end = 0x48300200 + SZ_128 - 1,
2673 }, 2661 },
2674 { } 2662 { }
2675}; 2663};
2676 2664
2677static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = { 2665static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2678 .master = &am33xx_l4_ls_hwmod, 2666 .master = &am33xx_epwmss0_hwmod,
2679 .slave = &am33xx_ehrpwm2_hwmod, 2667 .slave = &am33xx_ehrpwm0_hwmod,
2680 .clk = "l4ls_gclk", 2668 .clk = "l4ls_gclk",
2681 .addr = am33xx_ehrpwm2_addr_space, 2669 .addr = am33xx_ehrpwm0_addr_space,
2682 .user = OCP_USER_MPU, 2670 .user = OCP_USER_MPU,
2683}; 2671};
2684 2672
2685/* 2673
2686 * Splitting the resources to handle access of PWMSS config space 2674static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
2687 * and module specific part independently
2688 */
2689static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2690 { 2675 {
2691 .pa_start = 0x48300000, 2676 .pa_start = 0x48302000,
2692 .pa_end = 0x48300000 + SZ_16 - 1, 2677 .pa_end = 0x48302000 + SZ_16 - 1,
2693 .flags = ADDR_TYPE_RT 2678 .flags = ADDR_TYPE_RT
2694 }, 2679 },
2695 {
2696 .pa_start = 0x48300180,
2697 .pa_end = 0x48300180 + SZ_128 - 1,
2698 },
2699 { } 2680 { }
2700}; 2681};
2701 2682
2702static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep0 = { 2683static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2703 .master = &am33xx_l4_ls_hwmod, 2684 .master = &am33xx_l4_ls_hwmod,
2704 .slave = &am33xx_eqep0_hwmod, 2685 .slave = &am33xx_epwmss1_hwmod,
2705 .clk = "l4ls_gclk", 2686 .clk = "l4ls_gclk",
2706 .addr = am33xx_eqep0_addr_space, 2687 .addr = am33xx_epwmss1_addr_space,
2707 .user = OCP_USER_MPU, 2688 .user = OCP_USER_MPU,
2708}; 2689};
2709 2690
2710/* 2691static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2711 * Splitting the resources to handle access of PWMSS config space
2712 * and module specific part independently
2713 */
2714static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2715 { 2692 {
2716 .pa_start = 0x48302000, 2693 .pa_start = 0x48302100,
2717 .pa_end = 0x48302000 + SZ_16 - 1, 2694 .pa_end = 0x48302100 + SZ_128 - 1,
2718 .flags = ADDR_TYPE_RT
2719 }, 2695 },
2696 { }
2697};
2698
2699static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2700 .master = &am33xx_epwmss1_hwmod,
2701 .slave = &am33xx_ecap1_hwmod,
2702 .clk = "l4ls_gclk",
2703 .addr = am33xx_ecap1_addr_space,
2704 .user = OCP_USER_MPU,
2705};
2706
2707static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2720 { 2708 {
2721 .pa_start = 0x48302180, 2709 .pa_start = 0x48302180,
2722 .pa_end = 0x48302180 + SZ_128 - 1, 2710 .pa_end = 0x48302180 + SZ_128 - 1,
@@ -2724,111 +2712,92 @@ static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2724 { } 2712 { }
2725}; 2713};
2726 2714
2727static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep1 = { 2715static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2728 .master = &am33xx_l4_ls_hwmod, 2716 .master = &am33xx_epwmss1_hwmod,
2729 .slave = &am33xx_eqep1_hwmod, 2717 .slave = &am33xx_eqep1_hwmod,
2730 .clk = "l4ls_gclk", 2718 .clk = "l4ls_gclk",
2731 .addr = am33xx_eqep1_addr_space, 2719 .addr = am33xx_eqep1_addr_space,
2732 .user = OCP_USER_MPU, 2720 .user = OCP_USER_MPU,
2733}; 2721};
2734 2722
2735/* 2723static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2736 * Splitting the resources to handle access of PWMSS config space
2737 * and module specific part independently
2738 */
2739static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2740 {
2741 .pa_start = 0x48304000,
2742 .pa_end = 0x48304000 + SZ_16 - 1,
2743 .flags = ADDR_TYPE_RT
2744 },
2745 { 2724 {
2746 .pa_start = 0x48304180, 2725 .pa_start = 0x48302200,
2747 .pa_end = 0x48304180 + SZ_128 - 1, 2726 .pa_end = 0x48302200 + SZ_128 - 1,
2748 }, 2727 },
2749 { } 2728 { }
2750}; 2729};
2751 2730
2752static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep2 = { 2731static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2753 .master = &am33xx_l4_ls_hwmod, 2732 .master = &am33xx_epwmss1_hwmod,
2754 .slave = &am33xx_eqep2_hwmod, 2733 .slave = &am33xx_ehrpwm1_hwmod,
2755 .clk = "l4ls_gclk", 2734 .clk = "l4ls_gclk",
2756 .addr = am33xx_eqep2_addr_space, 2735 .addr = am33xx_ehrpwm1_addr_space,
2757 .user = OCP_USER_MPU, 2736 .user = OCP_USER_MPU,
2758}; 2737};
2759 2738
2760/* 2739static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2761 * Splitting the resources to handle access of PWMSS config space
2762 * and module specific part independently
2763 */
2764static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2765 { 2740 {
2766 .pa_start = 0x48300000, 2741 .pa_start = 0x48304000,
2767 .pa_end = 0x48300000 + SZ_16 - 1, 2742 .pa_end = 0x48304000 + SZ_16 - 1,
2768 .flags = ADDR_TYPE_RT 2743 .flags = ADDR_TYPE_RT
2769 }, 2744 },
2770 {
2771 .pa_start = 0x48300100,
2772 .pa_end = 0x48300100 + SZ_128 - 1,
2773 },
2774 { } 2745 { }
2775}; 2746};
2776 2747
2777static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = { 2748static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2778 .master = &am33xx_l4_ls_hwmod, 2749 .master = &am33xx_l4_ls_hwmod,
2779 .slave = &am33xx_ecap0_hwmod, 2750 .slave = &am33xx_epwmss2_hwmod,
2780 .clk = "l4ls_gclk", 2751 .clk = "l4ls_gclk",
2781 .addr = am33xx_ecap0_addr_space, 2752 .addr = am33xx_epwmss2_addr_space,
2782 .user = OCP_USER_MPU, 2753 .user = OCP_USER_MPU,
2783}; 2754};
2784 2755
2785/* 2756static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2786 * Splitting the resources to handle access of PWMSS config space
2787 * and module specific part independently
2788 */
2789static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2790 {
2791 .pa_start = 0x48302000,
2792 .pa_end = 0x48302000 + SZ_16 - 1,
2793 .flags = ADDR_TYPE_RT
2794 },
2795 { 2757 {
2796 .pa_start = 0x48302100, 2758 .pa_start = 0x48304100,
2797 .pa_end = 0x48302100 + SZ_128 - 1, 2759 .pa_end = 0x48304100 + SZ_128 - 1,
2798 }, 2760 },
2799 { } 2761 { }
2800}; 2762};
2801 2763
2802static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = { 2764static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2803 .master = &am33xx_l4_ls_hwmod, 2765 .master = &am33xx_epwmss2_hwmod,
2804 .slave = &am33xx_ecap1_hwmod, 2766 .slave = &am33xx_ecap2_hwmod,
2805 .clk = "l4ls_gclk", 2767 .clk = "l4ls_gclk",
2806 .addr = am33xx_ecap1_addr_space, 2768 .addr = am33xx_ecap2_addr_space,
2807 .user = OCP_USER_MPU, 2769 .user = OCP_USER_MPU,
2808}; 2770};
2809 2771
2810/* 2772static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2811 * Splitting the resources to handle access of PWMSS config space
2812 * and module specific part independently
2813 */
2814static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2815 { 2773 {
2816 .pa_start = 0x48304000, 2774 .pa_start = 0x48304180,
2817 .pa_end = 0x48304000 + SZ_16 - 1, 2775 .pa_end = 0x48304180 + SZ_128 - 1,
2818 .flags = ADDR_TYPE_RT
2819 }, 2776 },
2777 { }
2778};
2779
2780static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2781 .master = &am33xx_epwmss2_hwmod,
2782 .slave = &am33xx_eqep2_hwmod,
2783 .clk = "l4ls_gclk",
2784 .addr = am33xx_eqep2_addr_space,
2785 .user = OCP_USER_MPU,
2786};
2787
2788static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2820 { 2789 {
2821 .pa_start = 0x48304100, 2790 .pa_start = 0x48304200,
2822 .pa_end = 0x48304100 + SZ_128 - 1, 2791 .pa_end = 0x48304200 + SZ_128 - 1,
2823 }, 2792 },
2824 { } 2793 { }
2825}; 2794};
2826 2795
2827static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = { 2796static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2828 .master = &am33xx_l4_ls_hwmod, 2797 .master = &am33xx_epwmss2_hwmod,
2829 .slave = &am33xx_ecap2_hwmod, 2798 .slave = &am33xx_ehrpwm2_hwmod,
2830 .clk = "l4ls_gclk", 2799 .clk = "l4ls_gclk",
2831 .addr = am33xx_ecap2_addr_space, 2800 .addr = am33xx_ehrpwm2_addr_space,
2832 .user = OCP_USER_MPU, 2801 .user = OCP_USER_MPU,
2833}; 2802};
2834 2803
@@ -3521,15 +3490,18 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3521 &am33xx_l4_ls__uart6, 3490 &am33xx_l4_ls__uart6,
3522 &am33xx_l4_ls__spinlock, 3491 &am33xx_l4_ls__spinlock,
3523 &am33xx_l4_ls__elm, 3492 &am33xx_l4_ls__elm,
3524 &am33xx_l4_ls__ehrpwm0, 3493 &am33xx_l4_ls__epwmss0,
3525 &am33xx_l4_ls__ehrpwm1, 3494 &am33xx_epwmss0__ecap0,
3526 &am33xx_l4_ls__ehrpwm2, 3495 &am33xx_epwmss0__eqep0,
3527 &am33xx_l4_ls__eqep0, 3496 &am33xx_epwmss0__ehrpwm0,
3528 &am33xx_l4_ls__eqep1, 3497 &am33xx_l4_ls__epwmss1,
3529 &am33xx_l4_ls__eqep2, 3498 &am33xx_epwmss1__ecap1,
3530 &am33xx_l4_ls__ecap0, 3499 &am33xx_epwmss1__eqep1,
3531 &am33xx_l4_ls__ecap1, 3500 &am33xx_epwmss1__ehrpwm1,
3532 &am33xx_l4_ls__ecap2, 3501 &am33xx_l4_ls__epwmss2,
3502 &am33xx_epwmss2__ecap2,
3503 &am33xx_epwmss2__eqep2,
3504 &am33xx_epwmss2__ehrpwm2,
3533 &am33xx_l3_s__gpmc, 3505 &am33xx_l3_s__gpmc,
3534 &am33xx_l3_main__lcdc, 3506 &am33xx_l3_main__lcdc,
3535 &am33xx_l4_ls__mcspi0, 3507 &am33xx_l4_ls__mcspi0,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-20 19:51:14 -0400