diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-09-22 21:18:55 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-09-22 21:18:55 -0400 |
commit | 9478303619bc87c575e894d867049b25f33bf124 (patch) | |
tree | e3f36c3b64fb24624f065bc47d53eb6996e3769d | |
parent | e2519c2c85c376666c96705239c5c7d1aef14b2d (diff) | |
parent | 8ce8ebeb572d70e672a8d158e93ffaac80ea7576 (diff) |
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock layer fixes from Mike Turquette:
"The fixes for the clock tree are mostly run-time bugs in clock
drivers.
The fixes for TI DRA7 remove divide-by-zero errors. The recently
merged AT91 clock driver fixes some bad error checking and the QCOM
driver fix restores audio for that platform, a clear regression. A
list iteration bug in the framework core was hit recently and is fixed
up here. Finally a compilation warning is fixed for efm32gg, which is
also a regression fix"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk/efm32gg: fix dt init prototype
clk: prevent erronous parsing of children during rate change
clk: rockchip: Fix the clocks for i2c1 and i2c2
clk: qcom: Fix sdc 144kHz frequency entry
clk: at91: fix num_parents test in at91sam9260 slow clk implementation
clk: ti: dra7-atl: Provide error check for incoming parameters in set_rate
clk: ti: divider: Provide error check for incoming parameters in set_rate
-rw-r--r-- | drivers/clk/at91/clk-slow.c | 2 | ||||
-rw-r--r-- | drivers/clk/clk-efm32gg.c | 6 | ||||
-rw-r--r-- | drivers/clk/clk.c | 7 | ||||
-rw-r--r-- | drivers/clk/qcom/gcc-ipq806x.c | 2 | ||||
-rw-r--r-- | drivers/clk/rockchip/clk-rk3288.c | 4 | ||||
-rw-r--r-- | drivers/clk/ti/clk-dra7-atl.c | 6 | ||||
-rw-r--r-- | drivers/clk/ti/divider.c | 7 |
7 files changed, 24 insertions, 10 deletions
diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index 0300c46ee247..32f7c1b36204 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c | |||
@@ -447,7 +447,7 @@ void __init of_at91sam9260_clk_slow_setup(struct device_node *np, | |||
447 | int i; | 447 | int i; |
448 | 448 | ||
449 | num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells"); | 449 | num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells"); |
450 | if (num_parents <= 0 || num_parents > 1) | 450 | if (num_parents != 2) |
451 | return; | 451 | return; |
452 | 452 | ||
453 | for (i = 0; i < num_parents; ++i) { | 453 | for (i = 0; i < num_parents; ++i) { |
diff --git a/drivers/clk/clk-efm32gg.c b/drivers/clk/clk-efm32gg.c index bac2ddf49d02..73a8d0ff530c 100644 --- a/drivers/clk/clk-efm32gg.c +++ b/drivers/clk/clk-efm32gg.c | |||
@@ -22,7 +22,7 @@ static struct clk_onecell_data clk_data = { | |||
22 | .clk_num = ARRAY_SIZE(clk), | 22 | .clk_num = ARRAY_SIZE(clk), |
23 | }; | 23 | }; |
24 | 24 | ||
25 | static int __init efm32gg_cmu_init(struct device_node *np) | 25 | static void __init efm32gg_cmu_init(struct device_node *np) |
26 | { | 26 | { |
27 | int i; | 27 | int i; |
28 | void __iomem *base; | 28 | void __iomem *base; |
@@ -33,7 +33,7 @@ static int __init efm32gg_cmu_init(struct device_node *np) | |||
33 | base = of_iomap(np, 0); | 33 | base = of_iomap(np, 0); |
34 | if (!base) { | 34 | if (!base) { |
35 | pr_warn("Failed to map address range for efm32gg,cmu node\n"); | 35 | pr_warn("Failed to map address range for efm32gg,cmu node\n"); |
36 | return -EADDRNOTAVAIL; | 36 | return; |
37 | } | 37 | } |
38 | 38 | ||
39 | clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL, | 39 | clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL, |
@@ -76,6 +76,6 @@ static int __init efm32gg_cmu_init(struct device_node *np) | |||
76 | clk[clk_HFPERCLKDAC0] = clk_register_gate(NULL, "HFPERCLK.DAC0", | 76 | clk[clk_HFPERCLKDAC0] = clk_register_gate(NULL, "HFPERCLK.DAC0", |
77 | "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL); | 77 | "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL); |
78 | 78 | ||
79 | return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | 79 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
80 | } | 80 | } |
81 | CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init); | 81 | CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init); |
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index b76fa69b44cb..bacc06ff939b 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c | |||
@@ -1467,6 +1467,7 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even | |||
1467 | static void clk_change_rate(struct clk *clk) | 1467 | static void clk_change_rate(struct clk *clk) |
1468 | { | 1468 | { |
1469 | struct clk *child; | 1469 | struct clk *child; |
1470 | struct hlist_node *tmp; | ||
1470 | unsigned long old_rate; | 1471 | unsigned long old_rate; |
1471 | unsigned long best_parent_rate = 0; | 1472 | unsigned long best_parent_rate = 0; |
1472 | bool skip_set_rate = false; | 1473 | bool skip_set_rate = false; |
@@ -1502,7 +1503,11 @@ static void clk_change_rate(struct clk *clk) | |||
1502 | if (clk->notifier_count && old_rate != clk->rate) | 1503 | if (clk->notifier_count && old_rate != clk->rate) |
1503 | __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate); | 1504 | __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate); |
1504 | 1505 | ||
1505 | hlist_for_each_entry(child, &clk->children, child_node) { | 1506 | /* |
1507 | * Use safe iteration, as change_rate can actually swap parents | ||
1508 | * for certain clock types. | ||
1509 | */ | ||
1510 | hlist_for_each_entry_safe(child, tmp, &clk->children, child_node) { | ||
1506 | /* Skip children who will be reparented to another clock */ | 1511 | /* Skip children who will be reparented to another clock */ |
1507 | if (child->new_parent && child->new_parent != clk) | 1512 | if (child->new_parent && child->new_parent != clk) |
1508 | continue; | 1513 | continue; |
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 4032e510d9aa..3b83b7dd78c7 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c | |||
@@ -1095,7 +1095,7 @@ static struct clk_branch prng_clk = { | |||
1095 | }; | 1095 | }; |
1096 | 1096 | ||
1097 | static const struct freq_tbl clk_tbl_sdc[] = { | 1097 | static const struct freq_tbl clk_tbl_sdc[] = { |
1098 | { 144000, P_PXO, 5, 18,625 }, | 1098 | { 200000, P_PXO, 2, 2, 125 }, |
1099 | { 400000, P_PLL8, 4, 1, 240 }, | 1099 | { 400000, P_PLL8, 4, 1, 240 }, |
1100 | { 16000000, P_PLL8, 4, 1, 6 }, | 1100 | { 16000000, P_PLL8, 4, 1, 6 }, |
1101 | { 17070000, P_PLL8, 1, 2, 45 }, | 1101 | { 17070000, P_PLL8, 1, 2, 45 }, |
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 0d8c6c59a75e..b22a2d2f21e9 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c | |||
@@ -545,7 +545,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { | |||
545 | GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS), | 545 | GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS), |
546 | GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS), | 546 | GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS), |
547 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS), | 547 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS), |
548 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS), | 548 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS), |
549 | GATE(0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS), | 549 | GATE(0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS), |
550 | GATE(0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS), | 550 | GATE(0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS), |
551 | GATE(0, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS), | 551 | GATE(0, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS), |
@@ -603,7 +603,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { | |||
603 | GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS), | 603 | GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS), |
604 | GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS), | 604 | GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS), |
605 | GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS), | 605 | GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS), |
606 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS), | 606 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS), |
607 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS), | 607 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS), |
608 | GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS), | 608 | GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS), |
609 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS), | 609 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS), |
diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c index 4a65b410e4d5..af29359677da 100644 --- a/drivers/clk/ti/clk-dra7-atl.c +++ b/drivers/clk/ti/clk-dra7-atl.c | |||
@@ -139,9 +139,13 @@ static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |||
139 | static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate, | 139 | static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
140 | unsigned long parent_rate) | 140 | unsigned long parent_rate) |
141 | { | 141 | { |
142 | struct dra7_atl_desc *cdesc = to_atl_desc(hw); | 142 | struct dra7_atl_desc *cdesc; |
143 | u32 divider; | 143 | u32 divider; |
144 | 144 | ||
145 | if (!hw || !rate) | ||
146 | return -EINVAL; | ||
147 | |||
148 | cdesc = to_atl_desc(hw); | ||
145 | divider = ((parent_rate + rate / 2) / rate) - 1; | 149 | divider = ((parent_rate + rate / 2) / rate) - 1; |
146 | if (divider > DRA7_ATL_DIVIDER_MASK) | 150 | if (divider > DRA7_ATL_DIVIDER_MASK) |
147 | divider = DRA7_ATL_DIVIDER_MASK; | 151 | divider = DRA7_ATL_DIVIDER_MASK; |
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index e6aa10db7bba..a837f703be65 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c | |||
@@ -211,11 +211,16 @@ static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, | |||
211 | static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | 211 | static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, |
212 | unsigned long parent_rate) | 212 | unsigned long parent_rate) |
213 | { | 213 | { |
214 | struct clk_divider *divider = to_clk_divider(hw); | 214 | struct clk_divider *divider; |
215 | unsigned int div, value; | 215 | unsigned int div, value; |
216 | unsigned long flags = 0; | 216 | unsigned long flags = 0; |
217 | u32 val; | 217 | u32 val; |
218 | 218 | ||
219 | if (!hw || !rate) | ||
220 | return -EINVAL; | ||
221 | |||
222 | divider = to_clk_divider(hw); | ||
223 | |||
219 | div = DIV_ROUND_UP(parent_rate, rate); | 224 | div = DIV_ROUND_UP(parent_rate, rate); |
220 | value = _get_val(divider, div); | 225 | value = _get_val(divider, div); |
221 | 226 | ||