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authorHaojian Zhuang <haojian.zhuang@gmail.com>2013-06-02 22:26:47 -0400
committerHaojian Zhuang <haojian.zhuang@gmail.com>2013-08-24 05:45:47 -0400
commit942f42214d693f98b6165d0202d21291f95bc37d (patch)
tree4e9fcf1dc66bba4bb837d08bca51626032695fd6
parent0f102b6ccec15c057d4d82f9731e6b780c9f8132 (diff)
irqchip: mmp: avoid to include irqs head file
Since <mach/irqs.h> in irq-mmp.c blocks the multiplatform build, remove it instead. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
-rw-r--r--drivers/irqchip/irq-mmp.c45
1 files changed, 21 insertions, 24 deletions
diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
index 1f8143278d4b..2cb7cd0bc2f5 100644
--- a/drivers/irqchip/irq-mmp.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -24,8 +24,6 @@
24#include <asm/exception.h> 24#include <asm/exception.h>
25#include <asm/mach/irq.h> 25#include <asm/mach/irq.h>
26 26
27#include <mach/irqs.h>
28
29#include "irqchip.h" 27#include "irqchip.h"
30 28
31#define MAX_ICU_NR 16 29#define MAX_ICU_NR 16
@@ -249,7 +247,7 @@ void __init icu_init_irq(void)
249/* MMP2 (ARMv7) */ 247/* MMP2 (ARMv7) */
250void __init mmp2_init_icu(void) 248void __init mmp2_init_icu(void)
251{ 249{
252 int irq; 250 int irq, end;
253 251
254 max_icu_nr = 8; 252 max_icu_nr = 8;
255 mmp_icu_base = ioremap(0xd4282000, 0x1000); 253 mmp_icu_base = ioremap(0xd4282000, 0x1000);
@@ -263,11 +261,12 @@ void __init mmp2_init_icu(void)
263 &icu_data[0]); 261 &icu_data[0]);
264 icu_data[1].reg_status = mmp_icu_base + 0x150; 262 icu_data[1].reg_status = mmp_icu_base + 0x150;
265 icu_data[1].reg_mask = mmp_icu_base + 0x168; 263 icu_data[1].reg_mask = mmp_icu_base + 0x168;
266 icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE; 264 icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
267 icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE; 265 icu_data[0].nr_irqs;
266 icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */
268 icu_data[1].nr_irqs = 2; 267 icu_data[1].nr_irqs = 2;
269 icu_data[1].cascade_irq = 4; 268 icu_data[1].cascade_irq = 4;
270 icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE; 269 icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
271 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, 270 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
272 icu_data[1].virq_base, 0, 271 icu_data[1].virq_base, 0,
273 &irq_domain_simple_ops, 272 &irq_domain_simple_ops,
@@ -276,7 +275,7 @@ void __init mmp2_init_icu(void)
276 icu_data[2].reg_mask = mmp_icu_base + 0x16c; 275 icu_data[2].reg_mask = mmp_icu_base + 0x16c;
277 icu_data[2].nr_irqs = 2; 276 icu_data[2].nr_irqs = 2;
278 icu_data[2].cascade_irq = 5; 277 icu_data[2].cascade_irq = 5;
279 icu_data[2].virq_base = IRQ_MMP2_RTC_BASE; 278 icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
280 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, 279 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
281 icu_data[2].virq_base, 0, 280 icu_data[2].virq_base, 0,
282 &irq_domain_simple_ops, 281 &irq_domain_simple_ops,
@@ -285,7 +284,7 @@ void __init mmp2_init_icu(void)
285 icu_data[3].reg_mask = mmp_icu_base + 0x17c; 284 icu_data[3].reg_mask = mmp_icu_base + 0x17c;
286 icu_data[3].nr_irqs = 3; 285 icu_data[3].nr_irqs = 3;
287 icu_data[3].cascade_irq = 9; 286 icu_data[3].cascade_irq = 9;
288 icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE; 287 icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
289 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, 288 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
290 icu_data[3].virq_base, 0, 289 icu_data[3].virq_base, 0,
291 &irq_domain_simple_ops, 290 &irq_domain_simple_ops,
@@ -294,7 +293,7 @@ void __init mmp2_init_icu(void)
294 icu_data[4].reg_mask = mmp_icu_base + 0x170; 293 icu_data[4].reg_mask = mmp_icu_base + 0x170;
295 icu_data[4].nr_irqs = 5; 294 icu_data[4].nr_irqs = 5;
296 icu_data[4].cascade_irq = 17; 295 icu_data[4].cascade_irq = 17;
297 icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE; 296 icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
298 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, 297 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
299 icu_data[4].virq_base, 0, 298 icu_data[4].virq_base, 0,
300 &irq_domain_simple_ops, 299 &irq_domain_simple_ops,
@@ -303,7 +302,7 @@ void __init mmp2_init_icu(void)
303 icu_data[5].reg_mask = mmp_icu_base + 0x174; 302 icu_data[5].reg_mask = mmp_icu_base + 0x174;
304 icu_data[5].nr_irqs = 15; 303 icu_data[5].nr_irqs = 15;
305 icu_data[5].cascade_irq = 35; 304 icu_data[5].cascade_irq = 35;
306 icu_data[5].virq_base = IRQ_MMP2_MISC_BASE; 305 icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
307 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, 306 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
308 icu_data[5].virq_base, 0, 307 icu_data[5].virq_base, 0,
309 &irq_domain_simple_ops, 308 &irq_domain_simple_ops,
@@ -312,7 +311,7 @@ void __init mmp2_init_icu(void)
312 icu_data[6].reg_mask = mmp_icu_base + 0x178; 311 icu_data[6].reg_mask = mmp_icu_base + 0x178;
313 icu_data[6].nr_irqs = 2; 312 icu_data[6].nr_irqs = 2;
314 icu_data[6].cascade_irq = 51; 313 icu_data[6].cascade_irq = 51;
315 icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE; 314 icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
316 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, 315 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
317 icu_data[6].virq_base, 0, 316 icu_data[6].virq_base, 0,
318 &irq_domain_simple_ops, 317 &irq_domain_simple_ops,
@@ -321,28 +320,26 @@ void __init mmp2_init_icu(void)
321 icu_data[7].reg_mask = mmp_icu_base + 0x184; 320 icu_data[7].reg_mask = mmp_icu_base + 0x184;
322 icu_data[7].nr_irqs = 2; 321 icu_data[7].nr_irqs = 2;
323 icu_data[7].cascade_irq = 55; 322 icu_data[7].cascade_irq = 55;
324 icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE; 323 icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
325 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, 324 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
326 icu_data[7].virq_base, 0, 325 icu_data[7].virq_base, 0,
327 &irq_domain_simple_ops, 326 &irq_domain_simple_ops,
328 &icu_data[7]); 327 &icu_data[7]);
329 for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) { 328 end = icu_data[7].virq_base + icu_data[7].nr_irqs;
329 for (irq = 0; irq < end; irq++) {
330 icu_mask_irq(irq_get_irq_data(irq)); 330 icu_mask_irq(irq_get_irq_data(irq));
331 switch (irq) { 331 if (irq == icu_data[1].cascade_irq ||
332 case IRQ_MMP2_PMIC_MUX: 332 irq == icu_data[2].cascade_irq ||
333 case IRQ_MMP2_RTC_MUX: 333 irq == icu_data[3].cascade_irq ||
334 case IRQ_MMP2_KEYPAD_MUX: 334 irq == icu_data[4].cascade_irq ||
335 case IRQ_MMP2_TWSI_MUX: 335 irq == icu_data[5].cascade_irq ||
336 case IRQ_MMP2_MISC_MUX: 336 irq == icu_data[6].cascade_irq ||
337 case IRQ_MMP2_MIPI_HSI1_MUX: 337 irq == icu_data[7].cascade_irq) {
338 case IRQ_MMP2_MIPI_HSI0_MUX:
339 irq_set_chip(irq, &icu_irq_chip); 338 irq_set_chip(irq, &icu_irq_chip);
340 irq_set_chained_handler(irq, icu_mux_irq_demux); 339 irq_set_chained_handler(irq, icu_mux_irq_demux);
341 break; 340 } else {
342 default:
343 irq_set_chip_and_handler(irq, &icu_irq_chip, 341 irq_set_chip_and_handler(irq, &icu_irq_chip,
344 handle_level_irq); 342 handle_level_irq);
345 break;
346 } 343 }
347 set_irq_flags(irq, IRQF_VALID); 344 set_irq_flags(irq, IRQF_VALID);
348 } 345 }