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authorStephen Warren <swarren@nvidia.com>2014-03-07 14:22:17 -0500
committerLinus Walleij <linus.walleij@linaro.org>2014-03-12 10:27:33 -0400
commit93cfb2d86285a7aa9a9ca47bff44d3035005cb8c (patch)
treebb2d00c6907066fcbacf394f2ca96e90538280a5
parentce4362546612c00a059c255f5c55373d6ee1022a (diff)
pinctrl: tegra: consistency cleanup
Fix Tegra30/114/124 pinmux drivers consistency issues. * Sort all lists of the same object type (e.g. #defines for pins, and the array that defines their names) in the same order. * Whitespace fixes. * Consistency in layout between the 3 drivers. These driver files were also auto-generated, which should allow us to make e.g. the U-Boot drivers completely consistent with the kernel in the future:-) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c53
-rw-r--r--drivers/pinctrl/pinctrl-tegra124.c106
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c32
3 files changed, 93 insertions, 98 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
index 1c9346f28b84..7407d0069375 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -1,10 +1,8 @@
1/* 1/*
2 * Pinctrl data and driver for the NVIDIA Tegra114 pinmux 2 * Pinctrl data for the NVIDIA Tegra114 pinmux
3 * 3 *
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Author: Pritesh Raithatha <praithatha@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation. 8 * version 2, as published by the Free Software Foundation.
@@ -13,9 +11,6 @@
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details. 13 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */ 14 */
20 15
21#include <linux/module.h> 16#include <linux/module.h>
@@ -203,8 +198,8 @@
203#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245) 198#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
204 199
205/* All non-GPIO pins follow */ 200/* All non-GPIO pins follow */
206#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1) 201#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
207#define _PIN(offset) (NUM_GPIOS + (offset)) 202#define _PIN(offset) (NUM_GPIOS + (offset))
208 203
209/* Non-GPIO pins */ 204/* Non-GPIO pins */
210#define TEGRA_PIN_CORE_PWR_REQ _PIN(0) 205#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
@@ -213,7 +208,7 @@
213#define TEGRA_PIN_RESET_OUT_N _PIN(3) 208#define TEGRA_PIN_RESET_OUT_N _PIN(3)
214#define TEGRA_PIN_OWR _PIN(4) 209#define TEGRA_PIN_OWR _PIN(4)
215 210
216static const struct pinctrl_pin_desc tegra114_pins[] = { 211static const struct pinctrl_pin_desc tegra114_pins[] = {
217 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), 212 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
218 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"), 213 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
219 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"), 214 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
@@ -385,9 +380,9 @@ static const struct pinctrl_pin_desc tegra114_pins[] = {
385 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"), 380 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
386 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"), 381 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
387 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"), 382 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
388 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
389 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"), 383 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
390 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"), 384 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
385 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
391}; 386};
392 387
393static const unsigned clk_32k_out_pa0_pins[] = { 388static const unsigned clk_32k_out_pa0_pins[] = {
@@ -1074,10 +1069,6 @@ static const unsigned cpu_pwr_req_pins[] = {
1074 TEGRA_PIN_CPU_PWR_REQ, 1069 TEGRA_PIN_CPU_PWR_REQ,
1075}; 1070};
1076 1071
1077static const unsigned owr_pins[] = {
1078 TEGRA_PIN_OWR,
1079};
1080
1081static const unsigned pwr_int_n_pins[] = { 1072static const unsigned pwr_int_n_pins[] = {
1082 TEGRA_PIN_PWR_INT_N, 1073 TEGRA_PIN_PWR_INT_N,
1083}; 1074};
@@ -1086,6 +1077,10 @@ static const unsigned reset_out_n_pins[] = {
1086 TEGRA_PIN_RESET_OUT_N, 1077 TEGRA_PIN_RESET_OUT_N,
1087}; 1078};
1088 1079
1080static const unsigned owr_pins[] = {
1081 TEGRA_PIN_OWR,
1082};
1083
1089static const unsigned drive_ao1_pins[] = { 1084static const unsigned drive_ao1_pins[] = {
1090 TEGRA_PIN_KB_ROW0_PR0, 1085 TEGRA_PIN_KB_ROW0_PR0,
1091 TEGRA_PIN_KB_ROW1_PR1, 1086 TEGRA_PIN_KB_ROW1_PR1,
@@ -1127,7 +1122,6 @@ static const unsigned drive_at1_pins[] = {
1127 TEGRA_PIN_GMI_AD13_PH5, 1122 TEGRA_PIN_GMI_AD13_PH5,
1128 TEGRA_PIN_GMI_AD14_PH6, 1123 TEGRA_PIN_GMI_AD14_PH6,
1129 TEGRA_PIN_GMI_AD15_PH7, 1124 TEGRA_PIN_GMI_AD15_PH7,
1130
1131 TEGRA_PIN_GMI_IORDY_PI5, 1125 TEGRA_PIN_GMI_IORDY_PI5,
1132 TEGRA_PIN_GMI_CS7_N_PI6, 1126 TEGRA_PIN_GMI_CS7_N_PI6,
1133}; 1127};
@@ -1141,15 +1135,12 @@ static const unsigned drive_at2_pins[] = {
1141 TEGRA_PIN_GMI_AD5_PG5, 1135 TEGRA_PIN_GMI_AD5_PG5,
1142 TEGRA_PIN_GMI_AD6_PG6, 1136 TEGRA_PIN_GMI_AD6_PG6,
1143 TEGRA_PIN_GMI_AD7_PG7, 1137 TEGRA_PIN_GMI_AD7_PG7,
1144
1145 TEGRA_PIN_GMI_WR_N_PI0, 1138 TEGRA_PIN_GMI_WR_N_PI0,
1146 TEGRA_PIN_GMI_OE_N_PI1, 1139 TEGRA_PIN_GMI_OE_N_PI1,
1147 TEGRA_PIN_GMI_CS6_N_PI3, 1140 TEGRA_PIN_GMI_CS6_N_PI3,
1148 TEGRA_PIN_GMI_RST_N_PI4, 1141 TEGRA_PIN_GMI_RST_N_PI4,
1149 TEGRA_PIN_GMI_WAIT_PI7, 1142 TEGRA_PIN_GMI_WAIT_PI7,
1150
1151 TEGRA_PIN_GMI_DQS_P_PJ3, 1143 TEGRA_PIN_GMI_DQS_P_PJ3,
1152
1153 TEGRA_PIN_GMI_ADV_N_PK0, 1144 TEGRA_PIN_GMI_ADV_N_PK0,
1154 TEGRA_PIN_GMI_CLK_PK1, 1145 TEGRA_PIN_GMI_CLK_PK1,
1155 TEGRA_PIN_GMI_CS4_N_PK2, 1146 TEGRA_PIN_GMI_CS4_N_PK2,
@@ -1425,7 +1416,7 @@ enum tegra_mux {
1425 .name = #fname, \ 1416 .name = #fname, \
1426 } 1417 }
1427 1418
1428static struct tegra_function tegra114_functions[] = { 1419static struct tegra_function tegra114_functions[] = {
1429 FUNCTION(blink), 1420 FUNCTION(blink),
1430 FUNCTION(cec), 1421 FUNCTION(cec),
1431 FUNCTION(cldvfs), 1422 FUNCTION(cldvfs),
@@ -1504,11 +1495,11 @@ static struct tegra_function tegra114_functions[] = {
1504 FUNCTION(vi_alt3), 1495 FUNCTION(vi_alt3),
1505}; 1496};
1506 1497
1507#define DRV_PINGROUP_REG_START 0x868 /* bank 0 */ 1498#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1508#define PINGROUP_REG_START 0x3000 /* bank 1 */ 1499#define PINGROUP_REG_A 0x3000 /* bank 1 */
1509 1500
1510#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_START) 1501#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
1511#define PINGROUP_REG_N(r) -1 1502#define PINGROUP_REG_N(r) -1
1512 1503
1513#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \ 1504#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
1514 { \ 1505 { \
@@ -1550,13 +1541,14 @@ static struct tegra_function tegra114_functions[] = {
1550 .drvtype_reg = -1, \ 1541 .drvtype_reg = -1, \
1551 } 1542 }
1552 1543
1553#define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_START) 1544#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A)
1554#define DRV_PINGROUP_DVRTYPE_N(r) -1 1545#define DRV_PINGROUP_REG_N(r) -1
1546
1555 1547
1556#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1548#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
1557 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 1549 drvdn_b, drvdn_w, drvup_b, drvup_w, \
1558 slwr_b, slwr_w, slwf_b, slwf_w, \ 1550 slwr_b, slwr_w, slwf_b, slwf_w, \
1559 drvtype) \ 1551 drvtype) \
1560 { \ 1552 { \
1561 .name = "drive_" #pg_name, \ 1553 .name = "drive_" #pg_name, \
1562 .pins = drive_##pg_name##_pins, \ 1554 .pins = drive_##pg_name##_pins, \
@@ -1569,7 +1561,7 @@ static struct tegra_function tegra114_functions[] = {
1569 .lock_reg = -1, \ 1561 .lock_reg = -1, \
1570 .ioreset_reg = -1, \ 1562 .ioreset_reg = -1, \
1571 .rcv_sel_reg = -1, \ 1563 .rcv_sel_reg = -1, \
1572 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \ 1564 .drv_reg = DRV_PINGROUP_REG_Y(r), \
1573 .drv_bank = 0, \ 1565 .drv_bank = 0, \
1574 .hsm_bit = hsm_b, \ 1566 .hsm_bit = hsm_b, \
1575 .schmitt_bit = schmitt_b, \ 1567 .schmitt_bit = schmitt_b, \
@@ -1582,14 +1574,13 @@ static struct tegra_function tegra114_functions[] = {
1582 .slwr_width = slwr_w, \ 1574 .slwr_width = slwr_w, \
1583 .slwf_bit = slwf_b, \ 1575 .slwf_bit = slwf_b, \
1584 .slwf_width = slwf_w, \ 1576 .slwf_width = slwf_w, \
1585 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \ 1577 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \
1586 .drvtype_bank = 0, \ 1578 .drvtype_bank = 0, \
1587 .drvtype_bit = 6, \ 1579 .drvtype_bit = 6, \
1588 } 1580 }
1589 1581
1590static const struct tegra_pingroup tegra114_groups[] = { 1582static const struct tegra_pingroup tegra114_groups[] = {
1591 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */ 1583 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */
1592 /* FIXME: Fill in correct data in safe column */
1593 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N, N), 1584 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N, N),
1594 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N, N), 1585 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N, N),
1595 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N, N), 1586 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N, N),
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index 3b03d77d454b..d1ec687ddfff 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -212,8 +212,8 @@
212#define TEGRA_PIN_PFF2 _GPIO(250) 212#define TEGRA_PIN_PFF2 _GPIO(250)
213 213
214/* All non-GPIO pins follow */ 214/* All non-GPIO pins follow */
215#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1) 215#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
216#define _PIN(offset) (NUM_GPIOS + (offset)) 216#define _PIN(offset) (NUM_GPIOS + (offset))
217 217
218/* Non-GPIO pins */ 218/* Non-GPIO pins */
219#define TEGRA_PIN_CORE_PWR_REQ _PIN(0) 219#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
@@ -406,16 +406,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
406 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"), 406 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
407 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"), 407 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
408 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"), 408 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
409 PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
410 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
411 PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
409 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"), 412 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
410 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"), 413 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
411 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
412 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"), 414 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
415 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
413 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"), 416 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
414 PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"), 417 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
415 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
416 PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
417 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), 418 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
418 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
419 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), 419 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
420}; 420};
421 421
@@ -1138,6 +1138,7 @@ static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1138static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = { 1138static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1139 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, 1139 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1140}; 1140};
1141
1141static const unsigned dp_hpd_pff0_pins[] = { 1142static const unsigned dp_hpd_pff0_pins[] = {
1142 TEGRA_PIN_DP_HPD_PFF0, 1143 TEGRA_PIN_DP_HPD_PFF0,
1143}; 1144};
@@ -1158,24 +1159,24 @@ static const unsigned cpu_pwr_req_pins[] = {
1158 TEGRA_PIN_CPU_PWR_REQ, 1159 TEGRA_PIN_CPU_PWR_REQ,
1159}; 1160};
1160 1161
1161static const unsigned owr_pins[] = {
1162 TEGRA_PIN_OWR,
1163};
1164
1165static const unsigned pwr_int_n_pins[] = { 1162static const unsigned pwr_int_n_pins[] = {
1166 TEGRA_PIN_PWR_INT_N, 1163 TEGRA_PIN_PWR_INT_N,
1167}; 1164};
1168 1165
1166static const unsigned gmi_clk_lb_pins[] = {
1167 TEGRA_PIN_GMI_CLK_LB,
1168};
1169
1169static const unsigned reset_out_n_pins[] = { 1170static const unsigned reset_out_n_pins[] = {
1170 TEGRA_PIN_RESET_OUT_N, 1171 TEGRA_PIN_RESET_OUT_N,
1171}; 1172};
1172 1173
1173static const unsigned clk_32k_in_pins[] = { 1174static const unsigned owr_pins[] = {
1174 TEGRA_PIN_CLK_32K_IN, 1175 TEGRA_PIN_OWR,
1175}; 1176};
1176 1177
1177static const unsigned gmi_clk_lb_pins[] = { 1178static const unsigned clk_32k_in_pins[] = {
1178 TEGRA_PIN_GMI_CLK_LB, 1179 TEGRA_PIN_CLK_32K_IN,
1179}; 1180};
1180 1181
1181static const unsigned jtag_rtck_pins[] = { 1182static const unsigned jtag_rtck_pins[] = {
@@ -1441,15 +1442,15 @@ static const unsigned drive_gpv_pins[] = {
1441 TEGRA_PIN_PFF2, 1442 TEGRA_PIN_PFF2,
1442}; 1443};
1443 1444
1444static const unsigned drive_cec_pins[] = {
1445 TEGRA_PIN_HDMI_CEC_PEE3,
1446};
1447
1448static const unsigned drive_dev3_pins[] = { 1445static const unsigned drive_dev3_pins[] = {
1449 TEGRA_PIN_CLK3_OUT_PEE0, 1446 TEGRA_PIN_CLK3_OUT_PEE0,
1450 TEGRA_PIN_CLK3_REQ_PEE1, 1447 TEGRA_PIN_CLK3_REQ_PEE1,
1451}; 1448};
1452 1449
1450static const unsigned drive_cec_pins[] = {
1451 TEGRA_PIN_HDMI_CEC_PEE3,
1452};
1453
1453static const unsigned drive_at6_pins[] = { 1454static const unsigned drive_at6_pins[] = {
1454 TEGRA_PIN_PK1, 1455 TEGRA_PIN_PK1,
1455 TEGRA_PIN_PK3, 1456 TEGRA_PIN_PK3,
@@ -1496,8 +1497,10 @@ static const unsigned drive_ao4_pins[] = {
1496 1497
1497enum tegra_mux { 1498enum tegra_mux {
1498 TEGRA_MUX_BLINK, 1499 TEGRA_MUX_BLINK,
1500 TEGRA_MUX_CCLA,
1499 TEGRA_MUX_CEC, 1501 TEGRA_MUX_CEC,
1500 TEGRA_MUX_CLDVFS, 1502 TEGRA_MUX_CLDVFS,
1503 TEGRA_MUX_CLK,
1501 TEGRA_MUX_CLK12, 1504 TEGRA_MUX_CLK12,
1502 TEGRA_MUX_CPU, 1505 TEGRA_MUX_CPU,
1503 TEGRA_MUX_DAP, 1506 TEGRA_MUX_DAP,
@@ -1507,6 +1510,7 @@ enum tegra_mux {
1507 TEGRA_MUX_DISPLAYA, 1510 TEGRA_MUX_DISPLAYA,
1508 TEGRA_MUX_DISPLAYA_ALT, 1511 TEGRA_MUX_DISPLAYA_ALT,
1509 TEGRA_MUX_DISPLAYB, 1512 TEGRA_MUX_DISPLAYB,
1513 TEGRA_MUX_DP,
1510 TEGRA_MUX_DTV, 1514 TEGRA_MUX_DTV,
1511 TEGRA_MUX_EXTPERIPH1, 1515 TEGRA_MUX_EXTPERIPH1,
1512 TEGRA_MUX_EXTPERIPH2, 1516 TEGRA_MUX_EXTPERIPH2,
@@ -1528,6 +1532,9 @@ enum tegra_mux {
1528 TEGRA_MUX_IRDA, 1532 TEGRA_MUX_IRDA,
1529 TEGRA_MUX_KBC, 1533 TEGRA_MUX_KBC,
1530 TEGRA_MUX_OWR, 1534 TEGRA_MUX_OWR,
1535 TEGRA_MUX_PE,
1536 TEGRA_MUX_PE0,
1537 TEGRA_MUX_PE1,
1531 TEGRA_MUX_PMI, 1538 TEGRA_MUX_PMI,
1532 TEGRA_MUX_PWM0, 1539 TEGRA_MUX_PWM0,
1533 TEGRA_MUX_PWM1, 1540 TEGRA_MUX_PWM1,
@@ -1539,6 +1546,8 @@ enum tegra_mux {
1539 TEGRA_MUX_RSVD2, 1546 TEGRA_MUX_RSVD2,
1540 TEGRA_MUX_RSVD3, 1547 TEGRA_MUX_RSVD3,
1541 TEGRA_MUX_RSVD4, 1548 TEGRA_MUX_RSVD4,
1549 TEGRA_MUX_RTCK,
1550 TEGRA_MUX_SATA,
1542 TEGRA_MUX_SDMMC1, 1551 TEGRA_MUX_SDMMC1,
1543 TEGRA_MUX_SDMMC2, 1552 TEGRA_MUX_SDMMC2,
1544 TEGRA_MUX_SDMMC3, 1553 TEGRA_MUX_SDMMC3,
@@ -1551,6 +1560,8 @@ enum tegra_mux {
1551 TEGRA_MUX_SPI4, 1560 TEGRA_MUX_SPI4,
1552 TEGRA_MUX_SPI5, 1561 TEGRA_MUX_SPI5,
1553 TEGRA_MUX_SPI6, 1562 TEGRA_MUX_SPI6,
1563 TEGRA_MUX_SYS,
1564 TEGRA_MUX_TMDS,
1554 TEGRA_MUX_TRACE, 1565 TEGRA_MUX_TRACE,
1555 TEGRA_MUX_UARTA, 1566 TEGRA_MUX_UARTA,
1556 TEGRA_MUX_UARTB, 1567 TEGRA_MUX_UARTB,
@@ -1569,16 +1580,6 @@ enum tegra_mux {
1569 TEGRA_MUX_VI_ALT3, 1580 TEGRA_MUX_VI_ALT3,
1570 TEGRA_MUX_VIMCLK2, 1581 TEGRA_MUX_VIMCLK2,
1571 TEGRA_MUX_VIMCLK2_ALT, 1582 TEGRA_MUX_VIMCLK2_ALT,
1572 TEGRA_MUX_SATA,
1573 TEGRA_MUX_CCLA,
1574 TEGRA_MUX_PE0,
1575 TEGRA_MUX_PE,
1576 TEGRA_MUX_PE1,
1577 TEGRA_MUX_DP,
1578 TEGRA_MUX_RTCK,
1579 TEGRA_MUX_SYS,
1580 TEGRA_MUX_CLK,
1581 TEGRA_MUX_TMDS,
1582}; 1583};
1583 1584
1584#define FUNCTION(fname) \ 1585#define FUNCTION(fname) \
@@ -1588,8 +1589,10 @@ enum tegra_mux {
1588 1589
1589static struct tegra_function tegra124_functions[] = { 1590static struct tegra_function tegra124_functions[] = {
1590 FUNCTION(blink), 1591 FUNCTION(blink),
1592 FUNCTION(ccla),
1591 FUNCTION(cec), 1593 FUNCTION(cec),
1592 FUNCTION(cldvfs), 1594 FUNCTION(cldvfs),
1595 FUNCTION(clk),
1593 FUNCTION(clk12), 1596 FUNCTION(clk12),
1594 FUNCTION(cpu), 1597 FUNCTION(cpu),
1595 FUNCTION(dap), 1598 FUNCTION(dap),
@@ -1599,6 +1602,7 @@ static struct tegra_function tegra124_functions[] = {
1599 FUNCTION(displaya), 1602 FUNCTION(displaya),
1600 FUNCTION(displaya_alt), 1603 FUNCTION(displaya_alt),
1601 FUNCTION(displayb), 1604 FUNCTION(displayb),
1605 FUNCTION(dp),
1602 FUNCTION(dtv), 1606 FUNCTION(dtv),
1603 FUNCTION(extperiph1), 1607 FUNCTION(extperiph1),
1604 FUNCTION(extperiph2), 1608 FUNCTION(extperiph2),
@@ -1620,6 +1624,9 @@ static struct tegra_function tegra124_functions[] = {
1620 FUNCTION(irda), 1624 FUNCTION(irda),
1621 FUNCTION(kbc), 1625 FUNCTION(kbc),
1622 FUNCTION(owr), 1626 FUNCTION(owr),
1627 FUNCTION(pe),
1628 FUNCTION(pe0),
1629 FUNCTION(pe1),
1623 FUNCTION(pmi), 1630 FUNCTION(pmi),
1624 FUNCTION(pwm0), 1631 FUNCTION(pwm0),
1625 FUNCTION(pwm1), 1632 FUNCTION(pwm1),
@@ -1631,6 +1638,8 @@ static struct tegra_function tegra124_functions[] = {
1631 FUNCTION(rsvd2), 1638 FUNCTION(rsvd2),
1632 FUNCTION(rsvd3), 1639 FUNCTION(rsvd3),
1633 FUNCTION(rsvd4), 1640 FUNCTION(rsvd4),
1641 FUNCTION(rtck),
1642 FUNCTION(sata),
1634 FUNCTION(sdmmc1), 1643 FUNCTION(sdmmc1),
1635 FUNCTION(sdmmc2), 1644 FUNCTION(sdmmc2),
1636 FUNCTION(sdmmc3), 1645 FUNCTION(sdmmc3),
@@ -1643,6 +1652,8 @@ static struct tegra_function tegra124_functions[] = {
1643 FUNCTION(spi4), 1652 FUNCTION(spi4),
1644 FUNCTION(spi5), 1653 FUNCTION(spi5),
1645 FUNCTION(spi6), 1654 FUNCTION(spi6),
1655 FUNCTION(sys),
1656 FUNCTION(tmds),
1646 FUNCTION(trace), 1657 FUNCTION(trace),
1647 FUNCTION(uarta), 1658 FUNCTION(uarta),
1648 FUNCTION(uartb), 1659 FUNCTION(uartb),
@@ -1661,23 +1672,13 @@ static struct tegra_function tegra124_functions[] = {
1661 FUNCTION(vi_alt3), 1672 FUNCTION(vi_alt3),
1662 FUNCTION(vimclk2), 1673 FUNCTION(vimclk2),
1663 FUNCTION(vimclk2_alt), 1674 FUNCTION(vimclk2_alt),
1664 FUNCTION(sata),
1665 FUNCTION(ccla),
1666 FUNCTION(pe0),
1667 FUNCTION(pe),
1668 FUNCTION(pe1),
1669 FUNCTION(dp),
1670 FUNCTION(rtck),
1671 FUNCTION(sys),
1672 FUNCTION(clk),
1673 FUNCTION(tmds),
1674}; 1675};
1675 1676
1676#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1677#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1677#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1678#define PINGROUP_REG_A 0x3000 /* bank 1 */
1678 1679
1679#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 1680#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
1680#define PINGROUP_REG_N(r) -1 1681#define PINGROUP_REG_N(r) -1
1681 1682
1682#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \ 1683#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
1683 { \ 1684 { \
@@ -1685,12 +1686,12 @@ static struct tegra_function tegra124_functions[] = {
1685 .pins = pg_name##_pins, \ 1686 .pins = pg_name##_pins, \
1686 .npins = ARRAY_SIZE(pg_name##_pins), \ 1687 .npins = ARRAY_SIZE(pg_name##_pins), \
1687 .funcs = { \ 1688 .funcs = { \
1688 TEGRA_MUX_ ## f0, \ 1689 TEGRA_MUX_##f0, \
1689 TEGRA_MUX_ ## f1, \ 1690 TEGRA_MUX_##f1, \
1690 TEGRA_MUX_ ## f2, \ 1691 TEGRA_MUX_##f2, \
1691 TEGRA_MUX_ ## f3, \ 1692 TEGRA_MUX_##f3, \
1692 }, \ 1693 }, \
1693 .func_safe = TEGRA_MUX_ ## f_safe, \ 1694 .func_safe = TEGRA_MUX_##f_safe, \
1694 .mux_reg = PINGROUP_REG_Y(r), \ 1695 .mux_reg = PINGROUP_REG_Y(r), \
1695 .mux_bank = 1, \ 1696 .mux_bank = 1, \
1696 .mux_bit = 0, \ 1697 .mux_bit = 0, \
@@ -1719,8 +1720,9 @@ static struct tegra_function tegra124_functions[] = {
1719 .drvtype_reg = -1, \ 1720 .drvtype_reg = -1, \
1720 } 1721 }
1721 1722
1722#define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_A) 1723#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A)
1723#define DRV_PINGROUP_DVRTYPE_N(r) -1 1724#define DRV_PINGROUP_REG_N(r) -1
1725
1724 1726
1725#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1727#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
1726 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 1728 drvdn_b, drvdn_w, drvup_b, drvup_w, \
@@ -1738,7 +1740,7 @@ static struct tegra_function tegra124_functions[] = {
1738 .lock_reg = -1, \ 1740 .lock_reg = -1, \
1739 .ioreset_reg = -1, \ 1741 .ioreset_reg = -1, \
1740 .rcv_sel_reg = -1, \ 1742 .rcv_sel_reg = -1, \
1741 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \ 1743 .drv_reg = DRV_PINGROUP_REG_Y(r), \
1742 .drv_bank = 0, \ 1744 .drv_bank = 0, \
1743 .hsm_bit = hsm_b, \ 1745 .hsm_bit = hsm_b, \
1744 .schmitt_bit = schmitt_b, \ 1746 .schmitt_bit = schmitt_b, \
@@ -1751,7 +1753,7 @@ static struct tegra_function tegra124_functions[] = {
1751 .slwr_width = slwr_w, \ 1753 .slwr_width = slwr_w, \
1752 .slwf_bit = slwf_b, \ 1754 .slwf_bit = slwf_b, \
1753 .slwf_width = slwf_w, \ 1755 .slwf_width = slwf_w, \
1754 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \ 1756 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \
1755 .drvtype_bank = 0, \ 1757 .drvtype_bank = 0, \
1756 .drvtype_bit = 6, \ 1758 .drvtype_bit = 6, \
1757 } 1759 }
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 4bc95802ea67..41d24f5c2854 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -25,7 +25,7 @@
25 * Most pins affected by the pinmux can also be GPIOs. Define these first. 25 * Most pins affected by the pinmux can also be GPIOs. Define these first.
26 * These must match how the GPIO driver names/numbers its pins. 26 * These must match how the GPIO driver names/numbers its pins.
27 */ 27 */
28#define _GPIO(offset) (offset) 28#define _GPIO(offset) (offset)
29 29
30#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0) 30#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
31#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1) 31#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
@@ -277,8 +277,8 @@
277#define TEGRA_PIN_PEE7 _GPIO(247) 277#define TEGRA_PIN_PEE7 _GPIO(247)
278 278
279/* All non-GPIO pins follow */ 279/* All non-GPIO pins follow */
280#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1) 280#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1)
281#define _PIN(offset) (NUM_GPIOS + (offset)) 281#define _PIN(offset) (NUM_GPIOS + (offset))
282 282
283/* Non-GPIO pins */ 283/* Non-GPIO pins */
284#define TEGRA_PIN_CLK_32K_IN _PIN(0) 284#define TEGRA_PIN_CLK_32K_IN _PIN(0)
@@ -2105,11 +2105,11 @@ static struct tegra_function tegra30_functions[] = {
2105 FUNCTION(vi_alt3), 2105 FUNCTION(vi_alt3),
2106}; 2106};
2107 2107
2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2109#define PINGROUP_REG_A 0x3000 /* bank 1 */ 2109#define PINGROUP_REG_A 0x3000 /* bank 1 */
2110 2110
2111#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 2111#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
2112#define PINGROUP_REG_N(r) -1 2112#define PINGROUP_REG_N(r) -1
2113 2113
2114#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \ 2114#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \
2115 { \ 2115 { \
@@ -2117,12 +2117,12 @@ static struct tegra_function tegra30_functions[] = {
2117 .pins = pg_name##_pins, \ 2117 .pins = pg_name##_pins, \
2118 .npins = ARRAY_SIZE(pg_name##_pins), \ 2118 .npins = ARRAY_SIZE(pg_name##_pins), \
2119 .funcs = { \ 2119 .funcs = { \
2120 TEGRA_MUX_ ## f0, \ 2120 TEGRA_MUX_##f0, \
2121 TEGRA_MUX_ ## f1, \ 2121 TEGRA_MUX_##f1, \
2122 TEGRA_MUX_ ## f2, \ 2122 TEGRA_MUX_##f2, \
2123 TEGRA_MUX_ ## f3, \ 2123 TEGRA_MUX_##f3, \
2124 }, \ 2124 }, \
2125 .func_safe = TEGRA_MUX_ ## f_safe, \ 2125 .func_safe = TEGRA_MUX_##f_safe, \
2126 .mux_reg = PINGROUP_REG_Y(r), \ 2126 .mux_reg = PINGROUP_REG_Y(r), \
2127 .mux_bank = 1, \ 2127 .mux_bank = 1, \
2128 .mux_bit = 0, \ 2128 .mux_bit = 0, \
@@ -2149,6 +2149,9 @@ static struct tegra_function tegra30_functions[] = {
2149 .drvtype_reg = -1, \ 2149 .drvtype_reg = -1, \
2150 } 2150 }
2151 2151
2152#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A)
2153#define DRV_PINGROUP_REG_N(r) -1
2154
2152#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 2155#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2153 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 2156 drvdn_b, drvdn_w, drvup_b, drvup_w, \
2154 slwr_b, slwr_w, slwf_b, slwf_w) \ 2157 slwr_b, slwr_w, slwf_b, slwf_w) \
@@ -2164,7 +2167,7 @@ static struct tegra_function tegra30_functions[] = {
2164 .lock_reg = -1, \ 2167 .lock_reg = -1, \
2165 .ioreset_reg = -1, \ 2168 .ioreset_reg = -1, \
2166 .rcv_sel_reg = -1, \ 2169 .rcv_sel_reg = -1, \
2167 .drv_reg = ((r) - DRV_PINGROUP_REG_A), \ 2170 .drv_reg = DRV_PINGROUP_REG_Y(r), \
2168 .drv_bank = 0, \ 2171 .drv_bank = 0, \
2169 .hsm_bit = hsm_b, \ 2172 .hsm_bit = hsm_b, \
2170 .schmitt_bit = schmitt_b, \ 2173 .schmitt_bit = schmitt_b, \
@@ -2182,7 +2185,6 @@ static struct tegra_function tegra30_functions[] = {
2182 2185
2183static const struct tegra_pingroup tegra30_groups[] = { 2186static const struct tegra_pingroup tegra30_groups[] = {
2184 /* pg_name, f0, f1, f2, f3, safe, r, od, ior */ 2187 /* pg_name, f0, f1, f2, f3, safe, r, od, ior */
2185 /* FIXME: Fill in correct data in safe column */
2186 PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, RSVD4, 0x331c, N, N), 2188 PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, RSVD4, 0x331c, N, N),
2187 PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x317c, N, N), 2189 PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x317c, N, N),
2188 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3358, N, N), 2190 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3358, N, N),
@@ -2495,6 +2497,7 @@ static struct of_device_id tegra30_pinctrl_of_match[] = {
2495 { .compatible = "nvidia,tegra30-pinmux", }, 2497 { .compatible = "nvidia,tegra30-pinmux", },
2496 { }, 2498 { },
2497}; 2499};
2500MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
2498 2501
2499static struct platform_driver tegra30_pinctrl_driver = { 2502static struct platform_driver tegra30_pinctrl_driver = {
2500 .driver = { 2503 .driver = {
@@ -2510,4 +2513,3 @@ module_platform_driver(tegra30_pinctrl_driver);
2510MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 2513MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
2511MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver"); 2514MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
2512MODULE_LICENSE("GPL v2"); 2515MODULE_LICENSE("GPL v2");
2513MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 13:02:40 -0400