Merge branch 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/edac

* 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/edac: (25 commits)
  i7300_edac: Properly initialize per-csrow memory size
  V4L/DVB: i7300_edac: better initialize page counts
  MAINTAINERS: Add maintainer for i7300-edac driver
  i7300-edac: CodingStyle cleanup
  i7300_edac: Improve comments
  i7300_edac: Cleanup: reorganize the file contents
  i7300_edac: Properly detect channel on CE errors
  i7300_edac: enrich FBD error info for corrected errors
  i7300_edac: enrich FBD error info for fatal errors
  i7300_edac: pre-allocate a buffer used to prepare err messages
  i7300_edac: Fix MTR x4/x8 detection logic
  i7300_edac: Make the debug messages coherent with the others
  i7300_edac: Cleanup: remove get_error_info logic
  i7300_edac: Add a code to cleanup error registers
  i7300_edac: Add support for reporting FBD errors
  i7300_edac: Properly detect the type of error correction
  i7300_edac: Detect if the device is on single mode
  i7300_edac: Adds detection for enhanced scrub mode on x8
  i7300_edac: Clear the error bit after reading
  i7300_edac: Add error detection code for global errors
  ...

5 files changed, 1273 insertions, 8 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 0e265fcc103b..23a4ca9e27f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2212,6 +2212,13 @@ W:	bluesmoke.sourceforge.net
 S:      Maintained
 F:      drivers/edac/i5400_edac.c
 
+EDAC-I7300
+M:      Mauro Carvalho Chehab <mchehab@redhat.com>
+L:      linux-edac@vger.kernel.org
+W:      bluesmoke.sourceforge.net
+S:      Maintained
+F:      drivers/edac/i7300_edac.c
+
 EDAC-I7CORE
 M:      Mauro Carvalho Chehab <mchehab@redhat.com>
 L:      linux-edac@vger.kernel.org
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 9dbb28b9559f..f436a2fa9f38 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -209,6 +209,13 @@ config EDAC_I5100
           Support for error detection and correction the Intel
           San Clemente MCH.
 
+config EDAC_I7300
+        tristate "Intel Clarksboro MCH"
+        depends on EDAC_MM_EDAC && X86 && PCI
+        help
+          Support for error detection and correction the Intel
+          Clarksboro MCH (Intel 7300 chipset).
+
 config EDAC_MPC85XX
         tristate "Freescale MPC83xx / MPC85xx"
         depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 32c7bc93c525..b3781399b38a 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_EDAC_CPC925)		+= cpc925_edac.o
 obj-$(CONFIG_EDAC_I5000)                += i5000_edac.o
 obj-$(CONFIG_EDAC_I5100)                += i5100_edac.o
 obj-$(CONFIG_EDAC_I5400)                += i5400_edac.o
+obj-$(CONFIG_EDAC_I7300)                += i7300_edac.o
 obj-$(CONFIG_EDAC_I7CORE)               += i7core_edac.o
 obj-$(CONFIG_EDAC_E7XXX)                += e7xxx_edac.o
 obj-$(CONFIG_EDAC_E752X)                += e752x_edac.o
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
new file mode 100644
index 000000000000..05523b504271
--- /dev/null
+++ b/drivers/edac/i7300_edac.c
@@ -0,0 +1,1247 @@
+/*
+ * Intel 7300 class Memory Controllers kernel module (Clarksboro)
+ *
+ * This file may be distributed under the terms of the
+ * GNU General Public License version 2 only.
+ *
+ * Copyright (c) 2010 by:
+ *       Mauro Carvalho Chehab <mchehab@redhat.com>
+ *
+ * Red Hat Inc. http://www.redhat.com
+ *
+ * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
+ *      http://www.intel.com/Assets/PDF/datasheet/318082.pdf
+ *
+ * TODO: The chipset allow checking for PCI Express errors also. Currently,
+ *       the driver covers only memory error errors
+ *
+ * This driver uses "csrows" EDAC attribute to represent DIMM slot#
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/slab.h>
+#include <linux/edac.h>
+#include <linux/mmzone.h>
+
+#include "edac_core.h"
+
+/*
+ * Alter this version for the I7300 module when modifications are made
+ */
+#define I7300_REVISION    " Ver: 1.0.0 " __DATE__
+
+#define EDAC_MOD_STR      "i7300_edac"
+
+#define i7300_printk(level, fmt, arg...) \
+        edac_printk(level, "i7300", fmt, ##arg)
+
+#define i7300_mc_printk(mci, level, fmt, arg...) \
+        edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
+
+/***********************************************
+ * i7300 Limit constants Structs and static vars
+ ***********************************************/
+
+/*
+ * Memory topology is organized as:
+ *      Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
+ *      Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
+ * Each channel can have to 8 DIMM sets (called as SLOTS)
+ * Slots should generally be filled in pairs
+ *      Except on Single Channel mode of operation
+ *              just slot 0/channel0 filled on this mode
+ *      On normal operation mode, the two channels on a branch should be
+ *              filled together for the same SLOT#
+ * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
+ *              channels on both branches should be filled
+ */
+
+/* Limits for i7300 */
+#define MAX_SLOTS               8
+#define MAX_BRANCHES            2
+#define MAX_CH_PER_BRANCH       2
+#define MAX_CHANNELS            (MAX_CH_PER_BRANCH * MAX_BRANCHES)
+#define MAX_MIR                 3
+
+#define to_channel(ch, branch)  ((((branch)) << 1) | (ch))
+
+#define to_csrow(slot, ch, branch)                                      \
+                (to_channel(ch, branch) | ((slot) << 2))
+
+/* Device name and register DID (Device ID) */
+struct i7300_dev_info {
+        const char *ctl_name;   /* name for this device */
+        u16 fsb_mapping_errors; /* DID for the branchmap,control */
+};
+
+/* Table of devices attributes supported by this driver */
+static const struct i7300_dev_info i7300_devs[] = {
+        {
+                .ctl_name = "I7300",
+                .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
+        },
+};
+
+struct i7300_dimm_info {
+        int megabytes;          /* size, 0 means not present  */
+};
+
+/* driver private data structure */
+struct i7300_pvt {
+        struct pci_dev *pci_dev_16_0_fsb_ctlr;          /* 16.0 */
+        struct pci_dev *pci_dev_16_1_fsb_addr_map;      /* 16.1 */
+        struct pci_dev *pci_dev_16_2_fsb_err_regs;      /* 16.2 */
+        struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES];  /* 21.0  and 22.0 */
+
+        u16 tolm;                               /* top of low memory */
+        u64 ambase;                             /* AMB BAR */
+
+        u32 mc_settings;                        /* Report several settings */
+        u32 mc_settings_a;
+
+        u16 mir[MAX_MIR];                       /* Memory Interleave Reg*/
+
+        u16 mtr[MAX_SLOTS][MAX_BRANCHES];       /* Memory Technlogy Reg */
+        u16 ambpresent[MAX_CHANNELS];           /* AMB present regs */
+
+        /* DIMM information matrix, allocating architecture maximums */
+        struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
+
+        /* Temporary buffer for use when preparing error messages */
+        char *tmp_prt_buffer;
+};
+
+/* FIXME: Why do we need to have this static? */
+static struct edac_pci_ctl_info *i7300_pci;
+
+/***************************************************
+ * i7300 Register definitions for memory enumeration
+ ***************************************************/
+
+/*
+ * Device 16,
+ * Function 0: System Address (not documented)
+ * Function 1: Memory Branch Map, Control, Errors Register
+ */
+
+        /* OFFSETS for Function 0 */
+#define AMBASE                  0x48 /* AMB Mem Mapped Reg Region Base */
+#define MAXCH                   0x56 /* Max Channel Number */
+#define MAXDIMMPERCH            0x57 /* Max DIMM PER Channel Number */
+
+        /* OFFSETS for Function 1 */
+#define MC_SETTINGS             0x40