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authorPeter Crosthwaite <crosthwaitepeter@gmail.com>2014-11-30 19:25:49 -0500
committerMichal Simek <michal.simek@xilinx.com>2014-12-01 03:22:50 -0500
commit8c7634c0ee4e2b62a361cc0285418e201d162f37 (patch)
tree32c12892e63dc8d908fca8247e3dabff103a4dec
parentd86e3104e8066a5412ad3f9790592477a947a77e (diff)
arm: dts: zynq: Move crystal freq. to board level
The fact that all supported boards use the same 33MHz crystal is a co-incidence. The Zynq PS support a range of crystal freqs so the hardcoded setting should be removed from the dtsi. Re-implement it on the board level. This prepares support for Zynq boards with different crystal frequencies (e.g. the Digilent ZYBO). Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi1
-rw-r--r--arch/arm/boot/dts/zynq-parallella.dts4
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts4
-rw-r--r--arch/arm/boot/dts/zynq-zc706.dts4
-rw-r--r--arch/arm/boot/dts/zynq-zed.dts4
5 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 24036c440440..f8e4a28adfc0 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -244,7 +244,6 @@
244 clkc: clkc@100 { 244 clkc: clkc@100 {
245 #clock-cells = <1>; 245 #clock-cells = <1>;
246 compatible = "xlnx,ps7-clkc"; 246 compatible = "xlnx,ps7-clkc";
247 ps-clk-frequency = <33333333>;
248 fclk-enable = <0>; 247 fclk-enable = <0>;
249 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 248 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
250 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 249 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index e1f51ca127fe..538a40a32eb4 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
34 }; 34 };
35}; 35};
36 36
37&clkc {
38 ps-clk-frequency = <33333333>;
39};
40
37&gem0 { 41&gem0 {
38 status = "okay"; 42 status = "okay";
39 phy-mode = "rgmii-id"; 43 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 94e2cda6f9b6..280f02dd4ddc 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -42,6 +42,10 @@
42 status = "okay"; 42 status = "okay";
43}; 43};
44 44
45&clkc {
46 ps-clk-frequency = <33333333>;
47};
48
45&gem0 { 49&gem0 {
46 status = "okay"; 50 status = "okay";
47 phy-mode = "rgmii-id"; 51 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index a8bbdfbc7093..34f7812d2ee8 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -29,6 +29,10 @@
29 29
30}; 30};
31 31
32&clkc {
33 ps-clk-frequency = <33333333>;
34};
35
32&gem0 { 36&gem0 {
33 status = "okay"; 37 status = "okay";
34 phy-mode = "rgmii-id"; 38 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 697779a353ed..1c7cc990b47a 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -29,6 +29,10 @@
29 29
30}; 30};
31 31
32&clkc {
33 ps-clk-frequency = <33333333>;
34};
35
32&gem0 { 36&gem0 {
33 status = "okay"; 37 status = "okay";
34 phy-mode = "rgmii-id"; 38 phy-mode = "rgmii-id";