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authorLinus Torvalds <torvalds@linux-foundation.org>2014-05-07 18:45:13 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-05-07 18:45:13 -0400
commit8a207d3e84535e9de14cee59bcf0ea3ede61aca8 (patch)
tree3b07e950dfc4cd0bbd285b90a3d2d18cdda32bba
parent38583f095c5a8138ae2a1c9173d0fd8a9f10e8aa (diff)
parent2a1235e53bed8fa111e1c1ee2e7d8d91efa71ebc (diff)
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "radeon, i915 and nouveau fixes, all fixes for regressions or black screens, or possible oopses" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon: lower the ref * post PLL maximum drm/radeon: check that we have a clock before PLL setup drm/radeon: drm/radeon: add missing radeon_semaphore_free to error path drm/radeon: Fix num_banks calculation for SI agp: info leak in agpioc_info_wrap() drm/gm107/gr: bump attrib cb size quite a bit drm/nouveau: fix another lock unbalance in nouveau_crtc_page_flip drm/nouveau/bios: fix shadowing from PROM on big-endian systems drm/nouveau/acpi: allow non-optimus setups to load vbios from acpi drm/radeon/dp: check for errors in dpcd reads drm/radeon: avoid high jitter with small frac divs drm/radeon: check buffer relocation offset drm/radeon: use pflip irq on R600+ v2 drm/radeon/uvd: use lower clocks on old UVD to boot v2 drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX drm/i915: Sanitize the enable_ppgtt module option once drm/i915: Break encoder->crtc link separately in intel_sanitize_crtc()
Diffstat
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h3
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c32
-rw-r--r--drivers/gpu/drm/i915/intel_display.c26
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/base.c10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_acpi.c3
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.c2
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c49
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c44
-rw-r--r--drivers/gpu/drm/radeon/cik.c77
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c1
-rw-r--r--drivers/gpu/drm/radeon/cikd.h9
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c28
-rw-r--r--drivers/gpu/drm/radeon/evergreen_dma.c1
-rw-r--r--drivers/gpu/drm/radeon/r600.c14
-rw-r--r--drivers/gpu/drm/radeon/r600_dma.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon.h6
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c20
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c4
-rw-r--r--drivers/gpu/drm/radeon/rv770_dma.c1
-rw-r--r--drivers/gpu/drm/radeon/si.c28
-rw-r--r--drivers/gpu/drm/radeon/si_dma.c1
-rw-r--r--drivers/gpu/drm/radeon/uvd_v1_0.c10
-rw-r--r--include/drm/i915_pciids.h4
25 files changed, 294 insertions, 87 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ec82f6bff122..108e1ec2fa4b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1954,6 +1954,9 @@ struct drm_i915_cmd_table {
1954#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) 1954#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1955#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 1955#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1956 ((dev)->pdev->device & 0x00F0) == 0x0020) 1956 ((dev)->pdev->device & 0x00F0) == 0x0020)
1957/* ULX machines are also considered ULT. */
1958#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
1959 (dev)->pdev->device == 0x0A1E)
1957#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 1960#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1958 1961
1959/* 1962/*
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 62a5c3627b90..154b0f8bb88d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -34,25 +34,35 @@ static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv);
34 34
35bool intel_enable_ppgtt(struct drm_device *dev, bool full) 35bool intel_enable_ppgtt(struct drm_device *dev, bool full)
36{ 36{
37 if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) 37 if (i915.enable_ppgtt == 0)
38 return false; 38 return false;
39 39
40 if (i915.enable_ppgtt == 1 && full) 40 if (i915.enable_ppgtt == 1 && full)
41 return false; 41 return false;
42 42
43 return true;
44}
45
46static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
47{
48 if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
49 return 0;
50
51 if (enable_ppgtt == 1)
52 return 1;
53
54 if (enable_ppgtt == 2 && HAS_PPGTT(dev))
55 return 2;
56
43#ifdef CONFIG_INTEL_IOMMU 57#ifdef CONFIG_INTEL_IOMMU
44 /* Disable ppgtt on SNB if VT-d is on. */ 58 /* Disable ppgtt on SNB if VT-d is on. */
45 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { 59 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
46 DRM_INFO("Disabling PPGTT because VT-d is on\n"); 60 DRM_INFO("Disabling PPGTT because VT-d is on\n");
47 return false; 61 return 0;
48 } 62 }
49#endif 63#endif
50 64
51 /* Full ppgtt disabled by default for now due to issues. */ 65 return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
52 if (full)
53 return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2);
54 else
55 return HAS_ALIASING_PPGTT(dev);
56} 66}
57 67
58#define GEN6_PPGTT_PD_ENTRIES 512 68#define GEN6_PPGTT_PD_ENTRIES 512
@@ -2031,6 +2041,14 @@ int i915_gem_gtt_init(struct drm_device *dev)
2031 gtt->base.total >> 20); 2041 gtt->base.total >> 20);
2032 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); 2042 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2033 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); 2043 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2044 /*
2045 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2046 * user's requested state against the hardware/driver capabilities. We
2047 * do this now so that we can print out any log messages once rather
2048 * than every time we check intel_enable_ppgtt().
2049 */
2050 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2051 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2034 2052
2035 return 0; 2053 return 0;
2036} 2054}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 69bcc42a0e44..48aa516a1ac0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11395,15 +11395,6 @@ void intel_modeset_init(struct drm_device *dev)
11395 } 11395 }
11396} 11396}
11397 11397
11398static void
11399intel_connector_break_all_links(struct intel_connector *connector)
11400{
11401 connector->base.dpms = DRM_MODE_DPMS_OFF;
11402 connector->base.encoder = NULL;
11403 connector->encoder->connectors_active = false;
11404 connector->encoder->base.crtc = NULL;
11405}
11406
11407static void intel_enable_pipe_a(struct drm_device *dev) 11398static void intel_enable_pipe_a(struct drm_device *dev)
11408{ 11399{
11409 struct intel_connector *connector; 11400 struct intel_connector *connector;
@@ -11485,8 +11476,17 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
11485 if (connector->encoder->base.crtc != &crtc->base) 11476 if (connector->encoder->base.crtc != &crtc->base)
11486 continue; 11477 continue;
11487 11478
11488 intel_connector_break_all_links(connector); 11479 connector->base.dpms = DRM_MODE_DPMS_OFF;
11480 connector->base.encoder = NULL;
11489 } 11481 }
11482 /* multiple connectors may have the same encoder:
11483 * handle them and break crtc link separately */
11484 list_for_each_entry(connector, &dev->mode_config.connector_list,
11485 base.head)
11486 if (connector->encoder->base.crtc == &crtc->base) {
11487 connector->encoder->base.crtc = NULL;
11488 connector->encoder->connectors_active = false;
11489 }
11490 11490
11491 WARN_ON(crtc->active); 11491 WARN_ON(crtc->active);
11492 crtc->base.enabled = false; 11492 crtc->base.enabled = false;
@@ -11568,6 +11568,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
11568 drm_get_encoder_name(&encoder->base)); 11568 drm_get_encoder_name(&encoder->base));
11569 encoder->disable(encoder); 11569 encoder->disable(encoder);
11570 } 11570 }
11571 encoder->base.crtc = NULL;
11572 encoder->connectors_active = false;
11571 11573
11572 /* Inconsistent output/port/pipe state happens presumably due to 11574 /* Inconsistent output/port/pipe state happens presumably due to
11573 * a bug in one of the get_hw_state functions. Or someplace else 11575 * a bug in one of the get_hw_state functions. Or someplace else
@@ -11578,8 +11580,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
11578 base.head) { 11580 base.head) {
11579 if (connector->encoder != encoder) 11581 if (connector->encoder != encoder)
11580 continue; 11582 continue;
11581 11583 connector->base.dpms = DRM_MODE_DPMS_OFF;
11582 intel_connector_break_all_links(connector); 11584 connector->base.encoder = NULL;
11583 } 11585 }
11584 } 11586 }
11585 /* Enabled encoders without active connectors will be fixed in 11587 /* Enabled encoders without active connectors will be fixed in
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dfa85289f28f..5ca68aa9f237 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -105,7 +105,8 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
105 case DP_LINK_BW_2_7: 105 case DP_LINK_BW_2_7:
106 break; 106 break;
107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && 108 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
109 INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 110 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4; 111 max_link_bw = DP_LINK_BW_5_4;
111 else 112 else
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
index 1dc37b1ddbfa..b0d0fb2f4d08 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
@@ -863,7 +863,7 @@ gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
863{ 863{
864 mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); 864 mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
865 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); 865 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
866 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); 866 mmio_data(0x200000, 0x1000, NV_MEM_ACCESS_RW);
867 867
868 mmio_list(0x40800c, 0x00000000, 8, 1); 868 mmio_list(0x40800c, 0x00000000, 8, 1);
869 mmio_list(0x408010, 0x80000000, 0, 0); 869 mmio_list(0x408010, 0x80000000, 0, 0);
@@ -877,6 +877,8 @@ gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
877 mmio_list(0x418e24, 0x00000000, 8, 0); 877 mmio_list(0x418e24, 0x00000000, 8, 0);
878 mmio_list(0x418e28, 0x80000030, 0, 0); 878 mmio_list(0x418e28, 0x80000030, 0, 0);
879 879
880 mmio_list(0x4064c8, 0x018002c0, 0, 0);
881
880 mmio_list(0x418810, 0x80000000, 12, 2); 882 mmio_list(0x418810, 0x80000000, 12, 2);
881 mmio_list(0x419848, 0x10000000, 12, 2); 883 mmio_list(0x419848, 0x10000000, 12, 2);
882 mmio_list(0x419c2c, 0x10000000, 12, 2); 884 mmio_list(0x419c2c, 0x10000000, 12, 2);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
index fb0b6b2d1427..222e8ebb669d 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
@@ -168,7 +168,8 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
168 */ 168 */
169 i = 16; 169 i = 16;
170 do { 170 do {
171 if ((nv_rd32(bios, 0x300000) & 0xffff) == 0xaa55) 171 u32 data = le32_to_cpu(nv_rd32(bios, 0x300000)) & 0xffff;
172 if (data == 0xaa55)
172 break; 173 break;
173 } while (i--); 174 } while (i--);
174 175
@@ -176,14 +177,15 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
176 goto out; 177 goto out;
177 178
178 /* read entire bios image to system memory */ 179 /* read entire bios image to system memory */
179 bios->size = ((nv_rd32(bios, 0x300000) >> 16) & 0xff) * 512; 180 bios->size = (le32_to_cpu(nv_rd32(bios, 0x300000)) >> 16) & 0xff;
181 bios->size = bios->size * 512;
180 if (!bios->size) 182 if (!bios->size)
181 goto out; 183 goto out;
182 184
183 bios->data = kmalloc(bios->size, GFP_KERNEL); 185 bios->data = kmalloc(bios->size, GFP_KERNEL);
184 if (bios->data) { 186 if (bios->data) {
185 for (i = 0; i < bios->size; i+=4) 187 for (i = 0; i < bios->size; i += 4)
186 nv_wo32(bios, i, nv_rd32(bios, 0x300000 + i)); 188 ((u32 *)bios->data)[i/4] = nv_rd32(bios, 0x300000 + i);
187 } 189 }
188 190
189 /* check the PCI record header */ 191 /* check the PCI record header */
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 83face3f608f..279206997e5c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -389,9 +389,6 @@ bool nouveau_acpi_rom_supported(struct pci_dev *pdev)
389 acpi_status status; 389 acpi_status status;
390 acpi_handle dhandle, rom_handle; 390 acpi_handle dhandle, rom_handle;
391 391
392 if (!nouveau_dsm_priv.dsm_detected && !nouveau_dsm_priv.optimus_detected)
393 return false;
394
395 dhandle = ACPI_HANDLE(&pdev->dev); 392 dhandle = ACPI_HANDLE(&pdev->dev);
396 if (!dhandle) 393 if (!dhandle)
397 return false; 394 return false;
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 3ff030dc1ee3..da764a4ed958 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -764,9 +764,9 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
764 } 764 }
765 765
766 ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence); 766 ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence);
767 mutex_unlock(&chan->cli->mutex);
768 if (ret) 767 if (ret)
769 goto fail_unreserve; 768 goto fail_unreserve;
769 mutex_unlock(&chan->cli->mutex);
770 770
771 /* Update the crtc struct and cleanup */ 771 /* Update the crtc struct and cleanup */
772 crtc->primary->fb = fb; 772 crtc->primary->fb = fb;
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index fb187c78978f..b7983aaee445 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1177,27 +1177,43 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1177 1177
1178 /* Set NUM_BANKS. */ 1178 /* Set NUM_BANKS. */
1179 if (rdev->family >= CHIP_TAHITI) { 1179 if (rdev->family >= CHIP_TAHITI) {
1180 unsigned tileb, index, num_banks, tile_split_bytes; 1180 unsigned index, num_banks;
1181 1181
1182 /* Calculate the macrotile mode index. */ 1182 if (rdev->family >= CHIP_BONAIRE) {
1183 tile_split_bytes = 64 << tile_split; 1183 unsigned tileb, tile_split_bytes;
1184 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1185 tileb = min(tile_split_bytes, tileb);
1186 1184
1187 for (index = 0; tileb > 64; index++) { 1185 /* Calculate the macrotile mode index. */
1188 tileb >>= 1; 1186 tile_split_bytes = 64 << tile_split;
1189 } 1187 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1188 tileb = min(tile_split_bytes, tileb);
1190 1189
1191 if (index >= 16) { 1190 for (index = 0; tileb > 64; index++)
1192 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1191 tileb >>= 1;
1193 target_fb->bits_per_pixel, tile_split); 1192
1194 return -EINVAL; 1193 if (index >= 16) {
1195 } 1194 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1195 target_fb->bits_per_pixel, tile_split);
1196 return -EINVAL;
1197 }
1196 1198
1197 if (rdev->family >= CHIP_BONAIRE)
1198 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1199 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1199 else 1200 } else {
1201 switch (target_fb->bits_per_pixel) {
1202 case 8:
1203 index = 10;
1204 break;
1205 case 16:
1206 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1207 break;
1208 default:
1209 case 32:
1210 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1211 break;
1212 }
1213
1200 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; 1214 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1215 }
1216
1201 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1217 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1202 } else { 1218 } else {
1203 /* NI and older. */ 1219 /* NI and older. */
@@ -1885,6 +1901,9 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1885 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1901 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1886 is_tvcv = true; 1902 is_tvcv = true;
1887 1903
1904 if (!radeon_crtc->adjusted_clock)
1905 return -EINVAL;
1906
1888 atombios_crtc_set_pll(crtc, adjusted_mode); 1907 atombios_crtc_set_pll(crtc, adjusted_mode);
1889 1908
1890 if (ASIC_IS_DCE4(rdev)) 1909 if (ASIC_IS_DCE4(rdev))
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index bc0119fb6c12..54e4f52549af 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -366,11 +366,11 @@ static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
366 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 366 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
367 return; 367 return;
368 368
369 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3)) 369 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
370 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 370 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
371 buf[0], buf[1], buf[2]); 371 buf[0], buf[1], buf[2]);
372 372
373 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3)) 373 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
374 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 374 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
375 buf[0], buf[1], buf[2]); 375 buf[0], buf[1], buf[2]);
376} 376}
@@ -419,21 +419,23 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
419 419
420 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 420 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
421 /* DP bridge chips */ 421 /* DP bridge chips */
422 drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 422 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
423 DP_EDP_CONFIGURATION_CAP, &tmp); 423 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
424 if (tmp & 1) 424 if (tmp & 1)
425 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 425 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
426 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 426 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
427 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 427 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
428 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 428 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
429 else 429 else
430 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 430 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
431 }
431 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 432 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
432 /* eDP */ 433 /* eDP */
433 drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 434 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
434 DP_EDP_CONFIGURATION_CAP, &tmp); 435 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
435 if (tmp & 1) 436 if (tmp & 1)
436 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 437 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
438 }
437 } 439 }
438 440
439 return panel_mode; 441 return panel_mode;
@@ -809,11 +811,15 @@ void radeon_dp_link_train(struct drm_encoder *encoder,
809 else 811 else
810 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 812 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
811 813
812 drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp); 814 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
813 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 815 == 1) {
814 dp_info.tp3_supported = true; 816 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
815 else 817 dp_info.tp3_supported = true;
818 else
819 dp_info.tp3_supported = false;
820 } else {
816 dp_info.tp3_supported = false; 821 dp_info.tp3_supported = false;
822 }
817 823
818 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 824 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
819 dp_info.rdev = rdev; 825 dp_info.rdev = rdev;
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 199eb194716f..5143e0bf2172 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3702,6 +3702,7 @@ int cik_copy_cpdma(struct radeon_device *rdev,
3702 r = radeon_fence_emit(rdev, fence, ring->idx); 3702 r = radeon_fence_emit(rdev, fence, ring->idx);
3703 if (r) { 3703 if (r) {
3704 radeon_ring_unlock_undo(rdev, ring); 3704 radeon_ring_unlock_undo(rdev, ring);
3705 radeon_semaphore_free(rdev, &sem, NULL);
3705 return r; 3706 return r;
3706 } 3707 }
3707 3708
@@ -6693,6 +6694,19 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev)
6693 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 6694 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6694 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 6695 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
6695 } 6696 }
6697 /* pflip */
6698 if (rdev->num_crtc >= 2) {
6699 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
6700 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
6701 }
6702 if (rdev->num_crtc >= 4) {
6703 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
6704 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
6705 }
6706 if (rdev->num_crtc >= 6) {
6707 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6708 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
6709 }
6696 6710
6697 /* dac hotplug */ 6711 /* dac hotplug */
6698 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); 6712 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
@@ -7049,6 +7063,25 @@ int cik_irq_set(struct radeon_device *rdev)
7049 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 7063 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
7050 } 7064 }
7051 7065
7066 if (rdev->num_crtc >= 2) {
7067 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
7068 GRPH_PFLIP_INT_MASK);
7069 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
7070 GRPH_PFLIP_INT_MASK);
7071 }
7072 if (rdev->num_crtc >= 4) {
7073 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
7074 GRPH_PFLIP_INT_MASK);
7075 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
7076 GRPH_PFLIP_INT_MASK);
7077 }
7078 if (rdev->num_crtc >= 6) {
7079 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
7080 GRPH_PFLIP_INT_MASK);
7081 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
7082 GRPH_PFLIP_INT_MASK);
7083 }
7084
7052 WREG32(DC_HPD1_INT_CONTROL, hpd1); 7085 WREG32(DC_HPD1_INT_CONTROL, hpd1);
7053 WREG32(DC_HPD2_INT_CONTROL, hpd2); 7086 WREG32(DC_HPD2_INT_CONTROL, hpd2);
7054 WREG32(DC_HPD3_INT_CONTROL, hpd3); 7087 WREG32(DC_HPD3_INT_CONTROL, hpd3);
@@ -7085,6 +7118,29 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
7085 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 7118 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
7086 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6); 7119 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
7087 7120
7121 rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
7122 EVERGREEN_CRTC0_REGISTER_OFFSET);
7123 rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
7124 EVERGREEN_CRTC1_REGISTER_OFFSET);
7125 if (rdev->num_crtc >= 4) {
7126 rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
7127 EVERGREEN_CRTC2_REGISTER_OFFSET);
7128 rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
7129 EVERGREEN_CRTC3_REGISTER_OFFSET);
7130 }
7131 if (rdev->num_crtc >= 6) {
7132 rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
7133 EVERGREEN_CRTC4_REGISTER_OFFSET);
7134 rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
7135 EVERGREEN_CRTC5_REGISTER_OFFSET);
7136 }
7137
7138 if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
7139 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
7140 GRPH_PFLIP_INT_CLEAR);
7141 if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
7142 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
7143 GRPH_PFLIP_INT_CLEAR);
7088 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) 7144 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
7089 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 7145 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
7090 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) 7146 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
@@ -7095,6 +7151,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
7095 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 7151 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
7096 7152
7097 if (rdev->num_crtc >= 4) { 7153 if (rdev->num_crtc >= 4) {
7154 if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
7155 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
7156 GRPH_PFLIP_INT_CLEAR);
7157 if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
7158 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
7159 GRPH_PFLIP_INT_CLEAR);
7098 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 7160 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
7099 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 7161 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
7100 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 7162 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
@@ -7106,6 +7168,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
7106 } 7168 }
7107 7169
7108 if (rdev->num_crtc >= 6) { 7170 if (rdev->num_crtc >= 6) {
7171 if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
7172 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
7173 GRPH_PFLIP_INT_CLEAR);
7174 if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
7175 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
7176 GRPH_PFLIP_INT_CLEAR);
7109 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 7177 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
7110 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 7178 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
7111 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 7179 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
@@ -7457,6 +7525,15 @@ restart_ih:
7457 break; 7525 break;
7458 } 7526 }
7459 break; 7527 break;
7528 case 8: /* D1 page flip */
7529 case 10: /* D2 page flip */
7530 case 12: /* D3 page flip */
7531 case 14: /* D4 page flip */
7532 case 16: /* D5 page flip */
7533 case 18: /* D6 page flip */
7534 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
7535 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
7536 break;
7460 case 42: /* HPD hotplug */ 7537 case 42: /* HPD hotplug */
7461 switch (src_data) { 7538 switch (src_data) {
7462 case 0: 7539 case 0:
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index f7e46cf682af..72e464c79a88 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -562,6 +562,7 @@ int cik_copy_dma(struct radeon_device *rdev,
562 r = radeon_fence_emit(rdev, fence, ring->idx); 562 r = radeon_fence_emit(rdev, fence, ring->idx);
563 if (r) { 563 if (r) {
564 radeon_ring_unlock_undo(rdev, ring); 564 radeon_ring_unlock_undo(rdev, ring);
565 radeon_semaphore_free(rdev, &sem, NULL);
565 return r; 566 return r;
566 } 567 }
567 568
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 213873270d5f..dd7926394a8f 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -888,6 +888,15 @@
888# define DC_HPD6_RX_INTERRUPT (1 << 18) 888# define DC_HPD6_RX_INTERRUPT (1 << 18)
889#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 889#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
890 890
891/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
892#define GRPH_INT_STATUS 0x6858
893# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
894# define GRPH_PFLIP_INT_CLEAR (1 << 8)
895/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
896#define GRPH_INT_CONTROL 0x685c
897# define GRPH_PFLIP_INT_MASK (1 << 0)
898# define GRPH_PFLIP_INT_TYPE (1 << 8)
899
891#define DAC_AUTODETECT_INT_CONTROL 0x67c8 900#define DAC_AUTODETECT_INT_CONTROL 0x67c8
892 901
893#define DC_HPD1_INT_STATUS 0x601c 902#define DC_HPD1_INT_STATUS 0x601c
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index b406546440da..0f7a51a3694f 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4371,7 +4371,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
4371 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 4371 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
4372 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 4372 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
4373 u32 grbm_int_cntl = 0; 4373 u32 grbm_int_cntl = 0;
4374 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
4375 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; 4374 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
4376 u32 dma_cntl, dma_cntl1 = 0; 4375 u32 dma_cntl, dma_cntl1 = 0;
4377 u32 thermal_int = 0; 4376 u32 thermal_int = 0;
@@ -4554,15 +4553,21 @@ int evergreen_irq_set(struct radeon_device *rdev)
4554 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 4553 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
4555 } 4554 }
4556 4555
4557 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 4556 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
4558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 4557 GRPH_PFLIP_INT_MASK);
4558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
4559 GRPH_PFLIP_INT_MASK);
4559 if (rdev->num_crtc >= 4) { 4560 if (rdev->num_crtc >= 4) {
4560 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 4561 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
4561 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 4562 GRPH_PFLIP_INT_MASK);
4563 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
4564 GRPH_PFLIP_INT_MASK);
4562 } 4565 }
4563 if (rdev->num_crtc >= 6) { 4566 if (rdev->num_crtc >= 6) {
4564 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 4567 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
4565 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 4568 GRPH_PFLIP_INT_MASK);
4569 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
4570 GRPH_PFLIP_INT_MASK);
4566 } 4571 }
4567 4572
4568 WREG32(DC_HPD1_INT_CONTROL, hpd1); 4573 WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -4951,6 +4956,15 @@ restart_ih:
4951 break; 4956 break;
4952 } 4957 }
4953 break; 4958 break;
4959 case 8: /* D1 page flip */
4960 case 10: /* D2 page flip */
4961 case 12: /* D3 page flip */
4962 case 14: /* D4 page flip */
4963 case 16: /* D5 page flip */
4964 case 18: /* D6 page flip */
4965 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
4966 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
4967 break;
4954 case 42: /* HPD hotplug */ 4968 case 42: /* HPD hotplug */
4955 switch (src_data) { 4969 switch (src_data) {
4956 case 0: 4970 case 0:
diff --git a/drivers/gpu/drm/radeon/evergreen_dma.c b/drivers/gpu/drm/radeon/evergreen_dma.c
index 287fe966d7de..478caefe0fef 100644
--- a/drivers/gpu/drm/radeon/evergreen_dma.c
+++ b/drivers/gpu/drm/radeon/evergreen_dma.c
@@ -151,6 +151,7 @@ int evergreen_copy_dma(struct radeon_device *rdev,
151 r = radeon_fence_emit(rdev, fence, ring->idx); 151 r = radeon_fence_emit(rdev, fence, ring->idx);
152 if (r) { 152 if (r) {
153 radeon_ring_unlock_undo(rdev, ring); 153 radeon_ring_unlock_undo(rdev, ring);
154 radeon_semaphore_free(rdev, &sem, NULL);
154 return r; 155 return r;
155 } 156 }
156 157
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 6e887d004eba..bbc189fd3ddc 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2839,6 +2839,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
2839 r = radeon_fence_emit(rdev, fence, ring->idx); 2839 r = radeon_fence_emit(rdev, fence, ring->idx);
2840 if (r) { 2840 if (r) {
2841 radeon_ring_unlock_undo(rdev, ring); 2841 radeon_ring_unlock_undo(rdev, ring);
2842 radeon_semaphore_free(rdev, &sem, NULL);
2842 return r; 2843 return r;
2843 } 2844 }
2844 2845
@@ -3505,7 +3506,6 @@ int r600_irq_set(struct radeon_device *rdev)
3505 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3506 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3506 u32 grbm_int_cntl = 0; 3507 u32 grbm_int_cntl = 0;
3507 u32 hdmi0, hdmi1; 3508 u32 hdmi0, hdmi1;
3508 u32 d1grph = 0, d2grph = 0;
3509 u32 dma_cntl; 3509 u32 dma_cntl;
3510 u32 thermal_int = 0; 3510 u32 thermal_int = 0;
3511 3511
@@ -3614,8 +3614,8 @@ int r600_irq_set(struct radeon_device *rdev)
3614 WREG32(CP_INT_CNTL, cp_int_cntl); 3614 WREG32(CP_INT_CNTL, cp_int_cntl);
3615 WREG32(DMA_CNTL, dma_cntl); 3615 WREG32(DMA_CNTL, dma_cntl);
3616 WREG32(DxMODE_INT_MASK, mode_int); 3616 WREG32(DxMODE_INT_MASK, mode_int);
3617 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 3617 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3618 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 3618 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3619 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3619 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3620 if (ASIC_IS_DCE3(rdev)) { 3620 if (ASIC_IS_DCE3(rdev)) {
3621 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3621 WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -3918,6 +3918,14 @@ restart_ih:
3918 break; 3918 break;
3919 } 3919 }
3920 break; 3920 break;
3921 case 9: /* D1 pflip */
3922 DRM_DEBUG("IH: D1 flip\n");
3923 radeon_crtc_handle_flip(rdev, 0);
3924 break;
3925 case 11: /* D2 pflip */
3926 DRM_DEBUG("IH: D2 flip\n");
3927 radeon_crtc_handle_flip(rdev, 1);
3928 break;
3921 case 19: /* HPD/DAC hotplug */ 3929 case 19: /* HPD/DAC hotplug */
3922 switch (src_data) { 3930 switch (src_data) {
3923 case 0: 3931 case 0:
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c
index 53fcb28f5578..4969cef44a19 100644
--- a/drivers/gpu/drm/radeon/r600_dma.c
+++ b/drivers/gpu/drm/radeon/r600_dma.c
@@ -489,6 +489,7 @@ int r600_copy_dma(struct radeon_device *rdev,
489 r = radeon_fence_emit(rdev, fence, ring->idx); 489 r = radeon_fence_emit(rdev, fence, ring->idx);
490 if (r) { 490 if (r) {
491 radeon_ring_unlock_undo(rdev, ring); 491 radeon_ring_unlock_undo(rdev, ring);
492 radeon_semaphore_free(rdev, &sem, NULL);
492 return r; 493 return r;
493 } 494 }
494 495
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b58e1afdda76..68528619834a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -730,6 +730,12 @@ struct cik_irq_stat_regs {
730 u32 disp_int_cont4; 730 u32 disp_int_cont4;
731 u32 disp_int_cont5; 731 u32 disp_int_cont5;
732 u32 disp_int_cont6; 732 u32 disp_int_cont6;
733 u32 d1grph_int;
734 u32 d2grph_int;
735 u32 d3grph_int;
736 u32 d4grph_int;
737 u32 d5grph_int;
738 u32 d6grph_int;
733}; 739};
734 740
735union radeon_irq_stat_regs { 741union radeon_irq_stat_regs {
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 8d99d5ee8014..408b6ac53f0b 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -284,6 +284,10 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
284 u32 update_pending; 284 u32 update_pending;
285 int vpos, hpos; 285 int vpos, hpos;
286 286
287 /* can happen during initialization */
288 if (radeon_crtc == NULL)
289 return;
290
287 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 291 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
288 work = radeon_crtc->unpin_work; 292 work = radeon_crtc->unpin_work;
289 if (work == NULL || 293 if (work == NULL ||
@@ -826,14 +830,14 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
826 830
827 /* make sure nominator is large enough */ 831 /* make sure nominator is large enough */
828 if (*nom < nom_min) { 832 if (*nom < nom_min) {
829 tmp = (nom_min + *nom - 1) / *nom; 833 tmp = DIV_ROUND_UP(nom_min, *nom);
830 *nom *= tmp; 834 *nom *= tmp;
831 *den *= tmp; 835 *den *= tmp;
832 } 836 }
833 837
834 /* make sure the denominator is large enough */ 838 /* make sure the denominator is large enough */
835 if (*den < den_min) { 839 if (*den < den_min) {
836 tmp = (den_min + *den - 1) / *den; 840 tmp = DIV_ROUND_UP(den_min, *den);
837 *nom *= tmp; 841 *nom *= tmp;
838 *den *= tmp; 842 *den *= tmp;
839 } 843 }
@@ -858,7 +862,7 @@ static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
858 unsigned *fb_div, unsigned *ref_div) 862 unsigned *fb_div, unsigned *ref_div)
859{ 863{
860 /* limit reference * post divider to a maximum */ 864 /* limit reference * post divider to a maximum */
861 ref_div_max = min(210 / post_div, ref_div_max); 865 ref_div_max = min(128 / post_div, ref_div_max);
862 866
863 /* get matching reference and feedback divider */ 867 /* get matching reference and feedback divider */
864 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 868 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
@@ -993,6 +997,16 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
993 /* this also makes sure that the reference divider is large enough */ 997 /* this also makes sure that the reference divider is large enough */
994 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 998 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
995 999
1000 /* avoid high jitter with small fractional dividers */
1001 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1002 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
1003 if (fb_div < fb_div_min) {
1004 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1005 fb_div *= tmp;
1006 ref_div *= tmp;
1007 }
1008 }
1009
996 /* and finally save the result */ 1010 /* and finally save the result */
997 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1011 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
998 *fb_div_p = fb_div / 10; 1012 *fb_div_p = fb_div / 10;
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index 5748bdaeacce..0f96c471c6d8 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -465,6 +465,10 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
465 cmd = radeon_get_ib_value(p, p->idx) >> 1; 465 cmd = radeon_get_ib_value(p, p->idx) >> 1;
466 466
467 if (cmd < 0x4) { 467 if (cmd < 0x4) {
468 if (end <= start) {
469 DRM_ERROR("invalid reloc offset %X!\n", offset);
470 return -EINVAL;
471 }
468 if ((end - start) < buf_sizes[cmd]) { 472 if ((end - start) < buf_sizes[cmd]) {
469 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 473 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
470 (unsigned)(end - start), buf_sizes[cmd]); 474 (unsigned)(end - start), buf_sizes[cmd]);
diff --git a/drivers/gpu/drm/radeon/rv770_dma.c b/drivers/gpu/drm/radeon/rv770_dma.c
index aca8cbe8a335..bbf2e076ee45 100644
--- a/drivers/gpu/drm/radeon/rv770_dma.c
+++ b/drivers/gpu/drm/radeon/rv770_dma.c
@@ -86,6 +86,7 @@ int rv770_copy_dma(struct radeon_device *rdev,
86 r = radeon_fence_emit(rdev, fence, ring->idx); 86 r = radeon_fence_emit(rdev, fence, ring->idx);
87 if (r) { 87 if (r) {
88 radeon_ring_unlock_undo(rdev, ring); 88 radeon_ring_unlock_undo(rdev, ring);
89 radeon_semaphore_free(rdev, &sem, NULL);
89 return r; 90 return r;
90 } 91 }
91 92
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index ac708e006180..22a63c98ba14 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5780,7 +5780,6 @@ int si_irq_set(struct radeon_device *rdev)
5780 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 5780 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
5781 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0; 5781 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
5782 u32 grbm_int_cntl = 0; 5782 u32 grbm_int_cntl = 0;
5783 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
5784 u32 dma_cntl, dma_cntl1; 5783 u32 dma_cntl, dma_cntl1;
5785 u32 thermal_int = 0; 5784 u32 thermal_int = 0;
5786 5785
@@ -5919,16 +5918,22 @@ int si_irq_set(struct radeon_device *rdev)
5919 } 5918 }
5920 5919
5921 if (rdev->num_crtc >= 2) { 5920 if (rdev->num_crtc >= 2) {
5922 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 5921 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
5923 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 5922 GRPH_PFLIP_INT_MASK);
5923 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
5924 GRPH_PFLIP_INT_MASK);
5924 } 5925 }
5925 if (rdev->num_crtc >= 4) { 5926 if (rdev->num_crtc >= 4) {
5926 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 5927 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
5927 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 5928 GRPH_PFLIP_INT_MASK);
5929 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
5930 GRPH_PFLIP_INT_MASK);
5928 } 5931 }
5929 if (rdev->num_crtc >= 6) { 5932 if (rdev->num_crtc >= 6) {
5930 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 5933 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
5931 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 5934 GRPH_PFLIP_INT_MASK);
5935 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
5936 GRPH_PFLIP_INT_MASK);
5932 } 5937 }
5933 5938
5934 if (!ASIC_IS_NODCE(rdev)) { 5939 if (!ASIC_IS_NODCE(rdev)) {
@@ -6292,6 +6297,15 @@ restart_ih:
6292 break; 6297 break;
6293 } 6298 }
6294 break; 6299 break;
6300 case 8: /* D1 page flip */
6301 case 10: /* D2 page flip */
6302 case 12: /* D3 page flip */
6303 case 14: /* D4 page flip */
6304 case 16: /* D5 page flip */
6305 case 18: /* D6 page flip */
6306 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
6307 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
6308 break;
6295 case 42: /* HPD hotplug */ 6309 case 42: /* HPD hotplug */
6296 switch (src_data) { 6310 switch (src_data) {
6297 case 0: 6311 case 0:
diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c
index cf0fdad8c278..de0ca070122f 100644
--- a/drivers/gpu/drm/radeon/si_dma.c
+++ b/drivers/gpu/drm/radeon/si_dma.c
@@ -213,6 +213,7 @@ int si_copy_dma(struct radeon_device *rdev,
213 r = radeon_fence_emit(rdev, fence, ring->idx); 213 r = radeon_fence_emit(rdev, fence, ring->idx);
214 if (r) { 214 if (r) {
215 radeon_ring_unlock_undo(rdev, ring); 215 radeon_ring_unlock_undo(rdev, ring);
216 radeon_semaphore_free(rdev, &sem, NULL);
216 return r; 217 return r;
217 } 218 }
218 219
diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c
index 0a243f0e5d68..be42c8125203 100644
--- a/drivers/gpu/drm/radeon/uvd_v1_0.c
+++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
@@ -83,7 +83,10 @@ int uvd_v1_0_init(struct radeon_device *rdev)
83 int r; 83 int r;
84 84
85 /* raise clocks while booting up the VCPU */ 85 /* raise clocks while booting up the VCPU */
86 radeon_set_uvd_clocks(rdev, 53300, 40000); 86 if (rdev->family < CHIP_RV740)
87 radeon_set_uvd_clocks(rdev, 10000, 10000);
88 else
89 radeon_set_uvd_clocks(rdev, 53300, 40000);
87 90
88 r = uvd_v1_0_start(rdev); 91 r = uvd_v1_0_start(rdev);
89 if (r) 92 if (r)
@@ -407,7 +410,10 @@ int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
407 struct radeon_fence *fence = NULL; 410 struct radeon_fence *fence = NULL;
408 int r; 411 int r;
409 412
410 r = radeon_set_uvd_clocks(rdev, 53300, 40000); 413 if (rdev->family < CHIP_RV740)
414 r = radeon_set_uvd_clocks(rdev, 10000, 10000);
415 else
416 r = radeon_set_uvd_clocks(rdev, 53300, 40000);
411 if (r) { 417 if (r) {
412 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r); 418 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
413 return r; 419 return r;
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 940ece4934ba..012d58fa8ff0 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -191,8 +191,8 @@
191 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ 191 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
192 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ 192 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
193 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ 193 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
194 INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \ 194 INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
195 INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \ 195 INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
196 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ 196 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
197 INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ 197 INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
198 INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ 198 INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 14:48:55 -0400