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author | Daniel Lezcano <daniel.lezcano@linaro.org> | 2014-09-28 19:59:51 -0400 |
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committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2014-09-28 19:59:51 -0400 |
commit | 867f667fb9c6734e06cc24e96fc7f06a7e772084 (patch) | |
tree | 13e3c29b74d986b631f22ca7b3d6020b4aec56a2 | |
parent | e1ce5c7adc735ce96a35806ca32ceb78e607a283 (diff) | |
parent | fb0eee2f141976b5d7f31e477a71556d312f7dc3 (diff) |
Merge tag 'renesas-clocksource-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into clockevents/3.18
Renesas Clocksource Updates for v3.18
* Document per-SoC bindings
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
3 files changed, 48 insertions, 10 deletions
diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index a17418b0ece3..1a05c1b243c1 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt | |||
@@ -11,15 +11,47 @@ datasheets. | |||
11 | 11 | ||
12 | Required Properties: | 12 | Required Properties: |
13 | 13 | ||
14 | - compatible: must contain one of the following. | 14 | - compatible: must contain one or more of the following: |
15 | - "renesas,cmt-32" for the 32-bit CMT | 15 | - "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT |
16 | (CMT0) | ||
17 | - "renesas,cmt-32-sh7372" for the sh7372 32-bit CMT | ||
18 | (CMT0) | ||
19 | - "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT | ||
20 | (CMT0) | ||
21 | - "renesas,cmt-32" for all 32-bit CMT without fast clock support | ||
16 | (CMT0 on sh7372, sh73a0 and r8a7740) | 22 | (CMT0 on sh7372, sh73a0 and r8a7740) |
17 | - "renesas,cmt-32-fast" for the 32-bit CMT with fast clock support | 23 | This is a fallback for the above renesas,cmt-32-* entries. |
24 | |||
25 | - "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast | ||
26 | clock support (CMT[234]) | ||
27 | - "renesas,cmt-32-fast-sh7372" for the sh7372 32-bit CMT with fast | ||
28 | clock support (CMT[234]) | ||
29 | - "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast | ||
30 | clock support (CMT[234]) | ||
31 | - "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support | ||
18 | (CMT[234] on sh7372, sh73a0 and r8a7740) | 32 | (CMT[234] on sh7372, sh73a0 and r8a7740) |
19 | - "renesas,cmt-48" for the 48-bit CMT | 33 | This is a fallback for the above renesas,cmt-32-fast-* entries. |
34 | |||
35 | - "renesas,cmt-48-sh7372" for the sh7372 48-bit CMT | ||
36 | (CMT1) | ||
37 | - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT | ||
38 | (CMT1) | ||
39 | - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT | ||
40 | (CMT1) | ||
41 | - "renesas,cmt-48" for all non-second generation 48-bit CMT | ||
20 | (CMT1 on sh7372, sh73a0 and r8a7740) | 42 | (CMT1 on sh7372, sh73a0 and r8a7740) |
21 | - "renesas,cmt-48-gen2" for the second generation 48-bit CMT | 43 | This is a fallback for the above renesas,cmt-48-* entries. |
44 | |||
45 | - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT | ||
46 | (CMT[01]) | ||
47 | - "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT | ||
48 | (CMT[01]) | ||
49 | - "renesas,cmt-48-r8a7791" for the r8a7791 48-bit CMT | ||
50 | (CMT[01]) | ||
51 | - "renesas,cmt-48-gen2" for all second generation 48-bit CMT | ||
22 | (CMT[01] on r8a73a4, r8a7790 and r8a7791) | 52 | (CMT[01] on r8a73a4, r8a7790 and r8a7791) |
53 | This is a fallback for the renesas,cmt-48-r8a73a4, | ||
54 | renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. | ||
23 | 55 | ||
24 | - reg: base address and length of the registers block for the timer module. | 56 | - reg: base address and length of the registers block for the timer module. |
25 | - interrupts: interrupt-specifier for the timer, one per channel. | 57 | - interrupts: interrupt-specifier for the timer, one per channel. |
@@ -36,7 +68,7 @@ Example: R8A7790 (R-Car H2) CMT0 node | |||
36 | them channels 0 and 1 in the documentation. | 68 | them channels 0 and 1 in the documentation. |
37 | 69 | ||
38 | cmt0: timer@ffca0000 { | 70 | cmt0: timer@ffca0000 { |
39 | compatible = "renesas,cmt-48-gen2"; | 71 | compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; |
40 | reg = <0 0xffca0000 0 0x1004>; | 72 | reg = <0 0xffca0000 0 0x1004>; |
41 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | 73 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, |
42 | <0 142 IRQ_TYPE_LEVEL_HIGH>; | 74 | <0 142 IRQ_TYPE_LEVEL_HIGH>; |
diff --git a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt index 917453f826bc..d9a8d5af1a21 100644 --- a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt +++ b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt | |||
@@ -8,7 +8,10 @@ are independent. The MTU2 hardware supports five channels indexed from 0 to 4. | |||
8 | 8 | ||
9 | Required Properties: | 9 | Required Properties: |
10 | 10 | ||
11 | - compatible: must contain "renesas,mtu2" | 11 | - compatible: must be one or more of the following: |
12 | - "renesas,mtu2-r7s72100" for the r7s72100 MTU2 | ||
13 | - "renesas,mtu2" for any MTU2 | ||
14 | This is a fallback for the above renesas,mtu2-* entries | ||
12 | 15 | ||
13 | - reg: base address and length of the registers block for the timer module. | 16 | - reg: base address and length of the registers block for the timer module. |
14 | 17 | ||
@@ -26,7 +29,7 @@ Required Properties: | |||
26 | Example: R7S72100 (RZ/A1H) MTU2 node | 29 | Example: R7S72100 (RZ/A1H) MTU2 node |
27 | 30 | ||
28 | mtu2: timer@fcff0000 { | 31 | mtu2: timer@fcff0000 { |
29 | compatible = "renesas,mtu2"; | 32 | compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; |
30 | reg = <0xfcff0000 0x400>; | 33 | reg = <0xfcff0000 0x400>; |
31 | interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>, | 34 | interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>, |
32 | <0 146 IRQ_TYPE_LEVEL_HIGH>, | 35 | <0 146 IRQ_TYPE_LEVEL_HIGH>, |
diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt index 425d0c5f4aee..7db89fb25444 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt | |||
@@ -8,7 +8,10 @@ are independent. The TMU hardware supports up to three channels. | |||
8 | 8 | ||
9 | Required Properties: | 9 | Required Properties: |
10 | 10 | ||
11 | - compatible: must contain "renesas,tmu" | 11 | - compatible: must contain one or more of the following: |
12 | - "renesas,tmu-r8a7779" for the r8a7779 TMU | ||
13 | - "renesas,tmu" for any TMU. | ||
14 | This is a fallback for the above renesas,tmu-* entries | ||
12 | 15 | ||
13 | - reg: base address and length of the registers block for the timer module. | 16 | - reg: base address and length of the registers block for the timer module. |
14 | 17 | ||
@@ -27,7 +30,7 @@ Optional Properties: | |||
27 | Example: R8A7779 (R-Car H1) TMU0 node | 30 | Example: R8A7779 (R-Car H1) TMU0 node |
28 | 31 | ||
29 | tmu0: timer@ffd80000 { | 32 | tmu0: timer@ffd80000 { |
30 | compatible = "renesas,tmu"; | 33 | compatible = "renesas,tmu-r8a7779", "renesas,tmu"; |
31 | reg = <0xffd80000 0x30>; | 34 | reg = <0xffd80000 0x30>; |
32 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, | 35 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, |
33 | <0 33 IRQ_TYPE_LEVEL_HIGH>, | 36 | <0 33 IRQ_TYPE_LEVEL_HIGH>, |