diff options
author | Paul Mundt <lethal@linux-sh.org> | 2009-08-04 05:06:01 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-04 05:06:01 -0400 |
commit | 817425275271f2514f0dc6952182aa057ce80973 (patch) | |
tree | 09c32a42c4700bc0cf7ea31a232a17c45d1e0824 | |
parent | d14d751ff9234595639a16e53b3cf0c575946bde (diff) |
sh: Split out SH-4 __flush_xxx_region() ops.
This splits out the SH-4 __flush_xxx_region() functions and defines them
as weak symbols. This allows us to provide optimized versions without
having to ifdef cache-sh4.c to death.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r-- | arch/sh/mm/Makefile_32 | 2 | ||||
-rw-r--r-- | arch/sh/mm/cache-sh4.c | 60 | ||||
-rw-r--r-- | arch/sh/mm/flush-sh4.c | 63 |
3 files changed, 64 insertions, 61 deletions
diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32 index 62e280734dcb..17b02522214f 100644 --- a/arch/sh/mm/Makefile_32 +++ b/arch/sh/mm/Makefile_32 | |||
@@ -8,7 +8,7 @@ ifndef CONFIG_CACHE_OFF | |||
8 | cache-$(CONFIG_CPU_SH2) := cache-sh2.o | 8 | cache-$(CONFIG_CPU_SH2) := cache-sh2.o |
9 | cache-$(CONFIG_CPU_SH2A) := cache-sh2a.o | 9 | cache-$(CONFIG_CPU_SH2A) := cache-sh2a.o |
10 | cache-$(CONFIG_CPU_SH3) := cache-sh3.o | 10 | cache-$(CONFIG_CPU_SH3) := cache-sh3.o |
11 | cache-$(CONFIG_CPU_SH4) := cache-sh4.o | 11 | cache-$(CONFIG_CPU_SH4) := cache-sh4.o flush-sh4.o |
12 | cache-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o | 12 | cache-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o |
13 | endif | 13 | endif |
14 | 14 | ||
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index c3a09b27f8d5..dfc1d0379479 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c | |||
@@ -119,66 +119,6 @@ void __init p3_cache_init(void) | |||
119 | } | 119 | } |
120 | 120 | ||
121 | /* | 121 | /* |
122 | * Write back the dirty D-caches, but not invalidate them. | ||
123 | * | ||
124 | * START: Virtual Address (U0, P1, or P3) | ||
125 | * SIZE: Size of the region. | ||
126 | */ | ||
127 | void __flush_wback_region(void *start, int size) | ||
128 | { | ||
129 | unsigned long v; | ||
130 | unsigned long begin, end; | ||
131 | |||
132 | begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); | ||
133 | end = ((unsigned long)start + size + L1_CACHE_BYTES-1) | ||
134 | & ~(L1_CACHE_BYTES-1); | ||
135 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | ||
136 | asm volatile("ocbwb %0" | ||
137 | : /* no output */ | ||
138 | : "m" (__m(v))); | ||
139 | } | ||
140 | } | ||
141 | |||
142 | /* | ||
143 | * Write back the dirty D-caches and invalidate them. | ||
144 | * | ||
145 | * START: Virtual Address (U0, P1, or P3) | ||
146 | * SIZE: Size of the region. | ||
147 | */ | ||
148 | void __flush_purge_region(void *start, int size) | ||
149 | { | ||
150 | unsigned long v; | ||
151 | unsigned long begin, end; | ||
152 | |||
153 | begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); | ||
154 | end = ((unsigned long)start + size + L1_CACHE_BYTES-1) | ||
155 | & ~(L1_CACHE_BYTES-1); | ||
156 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | ||
157 | asm volatile("ocbp %0" | ||
158 | : /* no output */ | ||
159 | : "m" (__m(v))); | ||
160 | } | ||
161 | } | ||
162 | |||
163 | /* | ||
164 | * No write back please | ||
165 | */ | ||
166 | void __flush_invalidate_region(void *start, int size) | ||
167 | { | ||
168 | unsigned long v; | ||
169 | unsigned long begin, end; | ||
170 | |||
171 | begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); | ||
172 | end = ((unsigned long)start + size + L1_CACHE_BYTES-1) | ||
173 | & ~(L1_CACHE_BYTES-1); | ||
174 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | ||
175 | asm volatile("ocbi %0" | ||
176 | : /* no output */ | ||
177 | : "m" (__m(v))); | ||
178 | } | ||
179 | } | ||
180 | |||
181 | /* | ||
182 | * Write back the range of D-cache, and purge the I-cache. | 122 | * Write back the range of D-cache, and purge the I-cache. |
183 | * | 123 | * |
184 | * Called from kernel/module.c:sys_init_module and routine for a.out format, | 124 | * Called from kernel/module.c:sys_init_module and routine for a.out format, |
diff --git a/arch/sh/mm/flush-sh4.c b/arch/sh/mm/flush-sh4.c new file mode 100644 index 000000000000..e6d918f6ec0b --- /dev/null +++ b/arch/sh/mm/flush-sh4.c | |||
@@ -0,0 +1,63 @@ | |||
1 | #include <linux/mm.h> | ||
2 | #include <asm/mmu_context.h> | ||
3 | #include <asm/cacheflush.h> | ||
4 | |||
5 | /* | ||
6 | * Write back the dirty D-caches, but not invalidate them. | ||
7 | * | ||
8 | * START: Virtual Address (U0, P1, or P3) | ||
9 | * SIZE: Size of the region. | ||
10 | */ | ||
11 | void __weak __flush_wback_region(void *start, int size) | ||
12 | { | ||
13 | unsigned long v; | ||
14 | unsigned long begin, end; | ||
15 | |||
16 | begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); | ||
17 | end = ((unsigned long)start + size + L1_CACHE_BYTES-1) | ||
18 | & ~(L1_CACHE_BYTES-1); | ||
19 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | ||
20 | asm volatile("ocbwb %0" | ||
21 | : /* no output */ | ||
22 | : "m" (__m(v))); | ||
23 | } | ||
24 | } | ||
25 | |||
26 | /* | ||
27 | * Write back the dirty D-caches and invalidate them. | ||
28 | * | ||
29 | * START: Virtual Address (U0, P1, or P3) | ||
30 | * SIZE: Size of the region. | ||
31 | */ | ||
32 | void __weak __flush_purge_region(void *start, int size) | ||
33 | { | ||
34 | unsigned long v; | ||
35 | unsigned long begin, end; | ||
36 | |||
37 | begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); | ||
38 | end = ((unsigned long)start + size + L1_CACHE_BYTES-1) | ||
39 | & ~(L1_CACHE_BYTES-1); | ||
40 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | ||
41 | asm volatile("ocbp %0" | ||
42 | : /* no output */ | ||
43 | : "m" (__m(v))); | ||
44 | } | ||
45 | } | ||
46 | |||
47 | /* | ||
48 | * No write back please | ||
49 | */ | ||
50 | void __weak __flush_invalidate_region(void *start, int size) | ||
51 | { | ||
52 | unsigned long v; | ||
53 | unsigned long begin, end; | ||
54 | |||
55 | begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); | ||
56 | end = ((unsigned long)start + size + L1_CACHE_BYTES-1) | ||
57 | & ~(L1_CACHE_BYTES-1); | ||
58 | for (v = begin; v < end; v+=L1_CACHE_BYTES) { | ||
59 | asm volatile("ocbi %0" | ||
60 | : /* no output */ | ||
61 | : "m" (__m(v))); | ||
62 | } | ||
63 | } | ||