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authorTomasz Figa <tomasz.figa@gmail.com>2014-09-23 15:05:41 -0400
committerTomasz Figa <tomasz.figa@gmail.com>2014-11-09 07:30:15 -0500
commit8100cf47698fedbde6dc3fa540b1fefcee69fd40 (patch)
treefa53c113ac0c37c15c26eae99940332d5c7f4d7b
parent1bf00d7a6dbff0a29eff4f8c022653b2bc9f5b97 (diff)
pinctrl: samsung: Separate per-bank init and runtime data
Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c44
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c24xx.c8
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c64xx.c2
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.c18
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.h33
5 files changed, 72 insertions, 33 deletions
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 552f7c75243d..b4490cb2a439 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -633,7 +633,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
633} 633}
634 634
635/* pin banks of s5pv210 pin-controller */ 635/* pin banks of s5pv210 pin-controller */
636static struct samsung_pin_bank s5pv210_pin_bank[] = { 636static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
637 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 637 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
638 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), 638 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
639 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 639 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -683,7 +683,7 @@ const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
683}; 683};
684 684
685/* pin banks of exynos3250 pin-controller 0 */ 685/* pin banks of exynos3250 pin-controller 0 */
686static struct samsung_pin_bank exynos3250_pin_banks0[] = { 686static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
687 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 687 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
688 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 688 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
689 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 689 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -694,7 +694,7 @@ static struct samsung_pin_bank exynos3250_pin_banks0[] = {
694}; 694};
695 695
696/* pin banks of exynos3250 pin-controller 1 */ 696/* pin banks of exynos3250 pin-controller 1 */
697static struct samsung_pin_bank exynos3250_pin_banks1[] = { 697static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
698 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), 698 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
699 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), 699 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
700 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), 700 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
@@ -737,7 +737,7 @@ const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
737}; 737};
738 738
739/* pin banks of exynos4210 pin-controller 0 */ 739/* pin banks of exynos4210 pin-controller 0 */
740static struct samsung_pin_bank exynos4210_pin_banks0[] = { 740static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
741 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 741 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
742 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 742 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
743 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 743 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -757,7 +757,7 @@ static struct samsung_pin_bank exynos4210_pin_banks0[] = {
757}; 757};
758 758
759/* pin banks of exynos4210 pin-controller 1 */ 759/* pin banks of exynos4210 pin-controller 1 */
760static struct samsung_pin_bank exynos4210_pin_banks1[] = { 760static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
761 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), 761 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
762 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), 762 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
763 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 763 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
@@ -781,7 +781,7 @@ static struct samsung_pin_bank exynos4210_pin_banks1[] = {
781}; 781};
782 782
783/* pin banks of exynos4210 pin-controller 2 */ 783/* pin banks of exynos4210 pin-controller 2 */
784static struct samsung_pin_bank exynos4210_pin_banks2[] = { 784static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
785 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), 785 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
786}; 786};
787 787
@@ -813,7 +813,7 @@ const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
813}; 813};
814 814
815/* pin banks of exynos4x12 pin-controller 0 */ 815/* pin banks of exynos4x12 pin-controller 0 */
816static struct samsung_pin_bank exynos4x12_pin_banks0[] = { 816static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
817 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 817 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
818 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 818 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
819 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 819 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -830,7 +830,7 @@ static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
830}; 830};
831 831
832/* pin banks of exynos4x12 pin-controller 1 */ 832/* pin banks of exynos4x12 pin-controller 1 */
833static struct samsung_pin_bank exynos4x12_pin_banks1[] = { 833static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
834 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 834 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
835 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 835 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
836 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 836 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
@@ -857,12 +857,12 @@ static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
857}; 857};
858 858
859/* pin banks of exynos4x12 pin-controller 2 */ 859/* pin banks of exynos4x12 pin-controller 2 */
860static struct samsung_pin_bank exynos4x12_pin_banks2[] = { 860static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
861 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 861 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
862}; 862};
863 863
864/* pin banks of exynos4x12 pin-controller 3 */ 864/* pin banks of exynos4x12 pin-controller 3 */
865static struct samsung_pin_bank exynos4x12_pin_banks3[] = { 865static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
866 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 866 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
867 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 867 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
868 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), 868 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
@@ -908,7 +908,7 @@ const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
908}; 908};
909 909
910/* pin banks of exynos5250 pin-controller 0 */ 910/* pin banks of exynos5250 pin-controller 0 */
911static struct samsung_pin_bank exynos5250_pin_banks0[] = { 911static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
912 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 912 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
913 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 913 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
914 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 914 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -937,7 +937,7 @@ static struct samsung_pin_bank exynos5250_pin_banks0[] = {
937}; 937};
938 938
939/* pin banks of exynos5250 pin-controller 1 */ 939/* pin banks of exynos5250 pin-controller 1 */
940static struct samsung_pin_bank exynos5250_pin_banks1[] = { 940static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
941 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 941 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
942 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 942 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
943 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), 943 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
@@ -950,7 +950,7 @@ static struct samsung_pin_bank exynos5250_pin_banks1[] = {
950}; 950};
951 951
952/* pin banks of exynos5250 pin-controller 2 */ 952/* pin banks of exynos5250 pin-controller 2 */
953static struct samsung_pin_bank exynos5250_pin_banks2[] = { 953static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
954 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 954 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
955 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 955 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
956 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 956 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
@@ -959,7 +959,7 @@ static struct samsung_pin_bank exynos5250_pin_banks2[] = {
959}; 959};
960 960
961/* pin banks of exynos5250 pin-controller 3 */ 961/* pin banks of exynos5250 pin-controller 3 */
962static struct samsung_pin_bank exynos5250_pin_banks3[] = { 962static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
963 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 963 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
964}; 964};
965 965
@@ -1001,7 +1001,7 @@ const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
1001}; 1001};
1002 1002
1003/* pin banks of exynos5260 pin-controller 0 */ 1003/* pin banks of exynos5260 pin-controller 0 */
1004static struct samsung_pin_bank exynos5260_pin_banks0[] = { 1004static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
1005 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), 1005 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1006 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), 1006 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1007 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1007 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -1026,7 +1026,7 @@ static struct samsung_pin_bank exynos5260_pin_banks0[] = {
1026}; 1026};
1027 1027
1028/* pin banks of exynos5260 pin-controller 1 */ 1028/* pin banks of exynos5260 pin-controller 1 */
1029static struct samsung_pin_bank exynos5260_pin_banks1[] = { 1029static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
1030 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), 1030 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1031 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), 1031 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1032 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1032 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
@@ -1035,7 +1035,7 @@ static struct samsung_pin_bank exynos5260_pin_banks1[] = {
1035}; 1035};
1036 1036
1037/* pin banks of exynos5260 pin-controller 2 */ 1037/* pin banks of exynos5260 pin-controller 2 */
1038static struct samsung_pin_bank exynos5260_pin_banks2[] = { 1038static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
1039 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1039 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1040 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1040 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1041}; 1041};
@@ -1065,7 +1065,7 @@ const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
1065}; 1065};
1066 1066
1067/* pin banks of exynos5420 pin-controller 0 */ 1067/* pin banks of exynos5420 pin-controller 0 */
1068static struct samsung_pin_bank exynos5420_pin_banks0[] = { 1068static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
1069 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), 1069 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1070 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1070 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1071 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1071 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
@@ -1074,7 +1074,7 @@ static struct samsung_pin_bank exynos5420_pin_banks0[] = {
1074}; 1074};
1075 1075
1076/* pin banks of exynos5420 pin-controller 1 */ 1076/* pin banks of exynos5420 pin-controller 1 */
1077static struct samsung_pin_bank exynos5420_pin_banks1[] = { 1077static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
1078 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), 1078 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1079 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), 1079 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1080 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1080 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
@@ -1091,7 +1091,7 @@ static struct samsung_pin_bank exynos5420_pin_banks1[] = {
1091}; 1091};
1092 1092
1093/* pin banks of exynos5420 pin-controller 2 */ 1093/* pin banks of exynos5420 pin-controller 2 */
1094static struct samsung_pin_bank exynos5420_pin_banks2[] = { 1094static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
1095 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1095 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1096 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 1096 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1097 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), 1097 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
@@ -1103,7 +1103,7 @@ static struct samsung_pin_bank exynos5420_pin_banks2[] = {
1103}; 1103};
1104 1104
1105/* pin banks of exynos5420 pin-controller 3 */ 1105/* pin banks of exynos5420 pin-controller 3 */
1106static struct samsung_pin_bank exynos5420_pin_banks3[] = { 1106static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
1107 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1107 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1108 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1108 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1109 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1109 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -1116,7 +1116,7 @@ static struct samsung_pin_bank exynos5420_pin_banks3[] = {
1116}; 1116};
1117 1117
1118/* pin banks of exynos5420 pin-controller 4 */ 1118/* pin banks of exynos5420 pin-controller 4 */
1119static struct samsung_pin_bank exynos5420_pin_banks4[] = { 1119static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
1120 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1120 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1121}; 1121};
1122 1122
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index c0c7924657e6..f1993f42114c 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
@@ -561,7 +561,7 @@ static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
561 return 0; 561 return 0;
562} 562}
563 563
564static struct samsung_pin_bank s3c2412_pin_banks[] = { 564static const struct samsung_pin_bank_data s3c2412_pin_banks[] __initconst = {
565 PIN_BANK_A(23, 0x000, "gpa"), 565 PIN_BANK_A(23, 0x000, "gpa"),
566 PIN_BANK_2BIT(11, 0x010, "gpb"), 566 PIN_BANK_2BIT(11, 0x010, "gpb"),
567 PIN_BANK_2BIT(16, 0x020, "gpc"), 567 PIN_BANK_2BIT(16, 0x020, "gpc"),
@@ -581,7 +581,7 @@ const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = {
581 }, 581 },
582}; 582};
583 583
584static struct samsung_pin_bank s3c2416_pin_banks[] = { 584static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = {
585 PIN_BANK_A(27, 0x000, "gpa"), 585 PIN_BANK_A(27, 0x000, "gpa"),
586 PIN_BANK_2BIT(11, 0x010, "gpb"), 586 PIN_BANK_2BIT(11, 0x010, "gpb"),
587 PIN_BANK_2BIT(16, 0x020, "gpc"), 587 PIN_BANK_2BIT(16, 0x020, "gpc"),
@@ -603,7 +603,7 @@ const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = {
603 }, 603 },
604}; 604};
605 605
606static struct samsung_pin_bank s3c2440_pin_banks[] = { 606static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = {
607 PIN_BANK_A(25, 0x000, "gpa"), 607 PIN_BANK_A(25, 0x000, "gpa"),
608 PIN_BANK_2BIT(11, 0x010, "gpb"), 608 PIN_BANK_2BIT(11, 0x010, "gpb"),
609 PIN_BANK_2BIT(16, 0x020, "gpc"), 609 PIN_BANK_2BIT(16, 0x020, "gpc"),
@@ -623,7 +623,7 @@ const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = {
623 }, 623 },
624}; 624};
625 625
626static struct samsung_pin_bank s3c2450_pin_banks[] = { 626static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = {
627 PIN_BANK_A(28, 0x000, "gpa"), 627 PIN_BANK_A(28, 0x000, "gpa"),
628 PIN_BANK_2BIT(11, 0x010, "gpb"), 628 PIN_BANK_2BIT(11, 0x010, "gpb"),
629 PIN_BANK_2BIT(16, 0x020, "gpc"), 629 PIN_BANK_2BIT(16, 0x020, "gpc"),
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
index 14c3f9823cc5..7756c1e9e763 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
@@ -780,7 +780,7 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
780} 780}
781 781
782/* pin banks of s3c64xx pin-controller 0 */ 782/* pin banks of s3c64xx pin-controller 0 */
783static struct samsung_pin_bank s3c64xx_pin_banks0[] = { 783static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = {
784 PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0), 784 PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
785 PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8), 785 PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
786 PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16), 786 PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 6e14811d1316..96ef6e50f1f6 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -973,6 +973,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
973 const struct of_device_id *match; 973 const struct of_device_id *match;
974 struct device_node *node = pdev->dev.of_node; 974 struct device_node *node = pdev->dev.of_node;
975 struct device_node *np; 975 struct device_node *np;
976 const struct samsung_pin_bank_data *bdata;
976 const struct samsung_pin_ctrl *ctrl; 977 const struct samsung_pin_ctrl *ctrl;
977 struct samsung_pin_bank *bank; 978 struct samsung_pin_bank *bank;
978 int i; 979 int i;
@@ -987,11 +988,24 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
987 988
988 d->suspend = ctrl->suspend; 989 d->suspend = ctrl->suspend;
989 d->resume = ctrl->resume; 990 d->resume = ctrl->resume;
990 d->pin_banks = ctrl->pin_banks;
991 d->nr_banks = ctrl->nr_banks; 991 d->nr_banks = ctrl->nr_banks;
992 d->pin_banks = devm_kcalloc(&pdev->dev, d->nr_banks,
993 sizeof(*d->pin_banks), GFP_KERNEL);
994 if (!d->pin_banks)
995 return ERR_PTR(-ENOMEM);
992 996
993 bank = d->pin_banks; 997 bank = d->pin_banks;
994 for (i = 0; i < d->nr_banks; ++i, ++bank) { 998 bdata = ctrl->pin_banks;
999 for (i = 0; i < ctrl->nr_banks; ++i, ++bdata, ++bank) {
1000 bank->type = bdata->type;
1001 bank->pctl_offset = bdata->pctl_offset;
1002 bank->nr_pins = bdata->nr_pins;
1003 bank->eint_func = bdata->eint_func;
1004 bank->eint_type = bdata->eint_type;
1005 bank->eint_mask = bdata->eint_mask;
1006 bank->eint_offset = bdata->eint_offset;
1007 bank->name = bdata->name;
1008
995 spin_lock_init(&bank->slock); 1009 spin_lock_init(&bank->slock);
996 bank->drvdata = d; 1010 bank->drvdata = d;
997 bank->pin_base = d->nr_pins; 1011 bank->pin_base = d->nr_pins;
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index cf2d61d0f001..ec43b7d49fb9 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -113,15 +113,39 @@ struct samsung_pin_bank_type {
113}; 113};
114 114
115/** 115/**
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
117 * @type: type of the bank (register offsets and bitfield widths)
118 * @pctl_offset: starting offset of the pin-bank registers.
119 * @nr_pins: number of pins included in this bank.
120 * @eint_func: function to set in CON register to configure pin as EINT.
121 * @eint_type: type of the external interrupt supported by the bank.
122 * @eint_mask: bit mask of pins which support EINT function.
123 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
124 * @name: name to be prefixed for each pin in this pin bank.
125 */
126struct samsung_pin_bank_data {
127 const struct samsung_pin_bank_type *type;
128 u32 pctl_offset;
129 u8 nr_pins;
130 u8 eint_func;
131 enum eint_type eint_type;
132 u32 eint_mask;
133 u32 eint_offset;
134 const char *name;
135};
136
137/**
116 * struct samsung_pin_bank: represent a controller pin-bank. 138 * struct samsung_pin_bank: represent a controller pin-bank.
117 * @type: type of the bank (register offsets and bitfield widths) 139 * @type: type of the bank (register offsets and bitfield widths)
118 * @pctl_offset: starting offset of the pin-bank registers. 140 * @pctl_offset: starting offset of the pin-bank registers.
119 * @pin_base: starting pin number of the bank.
120 * @nr_pins: number of pins included in this bank. 141 * @nr_pins: number of pins included in this bank.
121 * @eint_func: function to set in CON register to configure pin as EINT. 142 * @eint_func: function to set in CON register to configure pin as EINT.
122 * @eint_type: type of the external interrupt supported by the bank. 143 * @eint_type: type of the external interrupt supported by the bank.
123 * @eint_mask: bit mask of pins which support EINT function. 144 * @eint_mask: bit mask of pins which support EINT function.
145 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
124 * @name: name to be prefixed for each pin in this pin bank. 146 * @name: name to be prefixed for each pin in this pin bank.
147 * @pin_base: starting pin number of the bank.
148 * @soc_priv: per-bank private data for SoC-specific code.
125 * @of_node: OF node of the bank. 149 * @of_node: OF node of the bank.
126 * @drvdata: link to controller driver data 150 * @drvdata: link to controller driver data
127 * @irq_domain: IRQ domain of the bank. 151 * @irq_domain: IRQ domain of the bank.
@@ -133,13 +157,14 @@ struct samsung_pin_bank_type {
133struct samsung_pin_bank { 157struct samsung_pin_bank {
134 const struct samsung_pin_bank_type *type; 158 const struct samsung_pin_bank_type *type;
135 u32 pctl_offset; 159 u32 pctl_offset;
136 u32 pin_base;
137 u8 nr_pins; 160 u8 nr_pins;
138 u8 eint_func; 161 u8 eint_func;
139 enum eint_type eint_type; 162 enum eint_type eint_type;
140 u32 eint_mask; 163 u32 eint_mask;
141 u32 eint_offset; 164 u32 eint_offset;
142 char *name; 165 const char *name;
166
167 u32 pin_base;
143 void *soc_priv; 168 void *soc_priv;
144 struct device_node *of_node; 169 struct device_node *of_node;
145 struct samsung_pinctrl_drv_data *drvdata; 170 struct samsung_pinctrl_drv_data *drvdata;
@@ -161,7 +186,7 @@ struct samsung_pin_bank {
161 * interrupts for the controller. 186 * interrupts for the controller.
162 */ 187 */
163struct samsung_pin_ctrl { 188struct samsung_pin_ctrl {
164 struct samsung_pin_bank *pin_banks; 189 const struct samsung_pin_bank_data *pin_banks;
165 u32 nr_banks; 190 u32 nr_banks;
166 191
167 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); 192 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);