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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2011-05-17 08:51:14 -0400
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2011-05-25 11:04:35 -0400
commit7a2207a0e1142a9b214b323e43ab2ecc592e5b0e (patch)
tree5e47b1916739c2148ec8cdb9b2d9dc256fcc0a0a
parente57556e3b6dcbf9b459cd503b061457b6ed1758f (diff)
at91: drop at572d940hf support
no-one use it and it's nearly impossible get a board to work on it and the Mainline implementation was never finished Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com> Cc: Andrew Victor <linux@maxim.org.za>
Diffstat
-rw-r--r--arch/arm/configs/at572d940hfek_defconfig358
-rw-r--r--arch/arm/mach-at91/Kconfig21
-rw-r--r--arch/arm/mach-at91/Makefile4
-rw-r--r--arch/arm/mach-at91/at572d940hf.c412
-rw-r--r--arch/arm/mach-at91/at572d940hf_devices.c964
-rw-r--r--arch/arm/mach-at91/board-at572d940hf_ek.c323
-rw-r--r--arch/arm/mach-at91/clock.c2
-rw-r--r--arch/arm/mach-at91/generic.h4
-rw-r--r--arch/arm/mach-at91/include/mach/at572d940hf.h121
-rw-r--r--arch/arm/mach-at91/include/mach/at572d940hf_matrix.h123
-rw-r--r--arch/arm/mach-at91/include/mach/board.h5
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h8
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-at91/include/mach/timex.h5
14 files changed, 2 insertions, 2350 deletions
diff --git a/arch/arm/configs/at572d940hfek_defconfig b/arch/arm/configs/at572d940hfek_defconfig
deleted file mode 100644
index 1b1158ae8f82..000000000000
--- a/arch/arm/configs/at572d940hfek_defconfig
+++ /dev/null
@@ -1,358 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOCALVERSION="-AT572D940HF"
3# CONFIG_LOCALVERSION_AUTO is not set
4CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y
6CONFIG_BSD_PROCESS_ACCT=y
7CONFIG_BSD_PROCESS_ACCT_V3=y
8CONFIG_TASKSTATS=y
9CONFIG_TASK_XACCT=y
10CONFIG_TASK_IO_ACCOUNTING=y
11CONFIG_AUDIT=y
12CONFIG_CGROUPS=y
13CONFIG_CGROUP_CPUACCT=y
14CONFIG_CGROUP_SCHED=y
15CONFIG_RT_GROUP_SCHED=y
16CONFIG_SYSFS_DEPRECATED_V2=y
17CONFIG_RELAY=y
18CONFIG_BLK_DEV_INITRD=y
19# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
20CONFIG_EXPERT=y
21CONFIG_SLAB=y
22CONFIG_PROFILING=y
23CONFIG_OPROFILE=m
24CONFIG_KPROBES=y
25CONFIG_MODULES=y
26CONFIG_MODULE_UNLOAD=y
27CONFIG_MODVERSIONS=y
28CONFIG_MODULE_SRCVERSION_ALL=y
29# CONFIG_BLK_DEV_BSG is not set
30CONFIG_ARCH_AT91=y
31CONFIG_ARCH_AT572D940HF=y
32CONFIG_MACH_AT572D940HFEB=y
33CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
34CONFIG_NO_HZ=y
35CONFIG_HIGH_RES_TIMERS=y
36CONFIG_PREEMPT=y
37CONFIG_CMDLINE="mem=48M console=ttyS0 initrd=0x21100000,3145728 root=/dev/ram0 rw ip=172.16.1.181"
38CONFIG_KEXEC=y
39CONFIG_FPE_NWFPE=y
40CONFIG_FPE_NWFPE_XP=y
41CONFIG_NET=y
42CONFIG_PACKET=m
43CONFIG_UNIX=y
44CONFIG_INET=y
45# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
46# CONFIG_INET_XFRM_MODE_TUNNEL is not set
47# CONFIG_INET_XFRM_MODE_BEET is not set
48# CONFIG_INET_LRO is not set
49# CONFIG_INET_DIAG is not set
50# CONFIG_IPV6 is not set
51CONFIG_NET_PKTGEN=m
52CONFIG_NET_TCPPROBE=m
53CONFIG_CAN=m
54CONFIG_CAN_RAW=m
55CONFIG_CAN_BCM=m
56CONFIG_CAN_VCAN=m
57CONFIG_CAN_DEBUG_DEVICES=y
58CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
59CONFIG_CONNECTOR=m
60CONFIG_MTD=m
61CONFIG_MTD_DEBUG=y
62CONFIG_MTD_DEBUG_VERBOSE=1
63CONFIG_MTD_CONCAT=m
64CONFIG_MTD_PARTITIONS=y
65CONFIG_MTD_CHAR=m
66CONFIG_MTD_BLOCK=m
67CONFIG_MTD_BLOCK_RO=m
68CONFIG_FTL=m
69CONFIG_NFTL=m
70CONFIG_NFTL_RW=y
71CONFIG_INFTL=m
72CONFIG_RFD_FTL=m
73CONFIG_SSFDC=m
74CONFIG_MTD_OOPS=m
75CONFIG_MTD_CFI=m
76CONFIG_MTD_JEDECPROBE=m
77CONFIG_MTD_CFI_INTELEXT=m
78CONFIG_MTD_CFI_AMDSTD=m
79CONFIG_MTD_CFI_STAA=m
80CONFIG_MTD_ROM=m
81CONFIG_MTD_ABSENT=m
82CONFIG_MTD_COMPLEX_MAPPINGS=y
83CONFIG_MTD_PHYSMAP=m
84CONFIG_MTD_PLATRAM=m
85CONFIG_MTD_DATAFLASH=m
86CONFIG_MTD_M25P80=m
87CONFIG_MTD_SLRAM=m
88CONFIG_MTD_PHRAM=m
89CONFIG_MTD_MTDRAM=m
90CONFIG_MTD_BLOCK2MTD=m
91CONFIG_MTD_NAND=m
92CONFIG_MTD_NAND_VERIFY_WRITE=y
93CONFIG_MTD_NAND_DISKONCHIP=m
94CONFIG_MTD_NAND_NANDSIM=m
95CONFIG_MTD_NAND_PLATFORM=m
96CONFIG_MTD_ALAUDA=m
97CONFIG_MTD_UBI=m
98CONFIG_MTD_UBI_GLUEBI=m
99CONFIG_BLK_DEV_LOOP=y
100CONFIG_BLK_DEV_CRYPTOLOOP=m
101CONFIG_BLK_DEV_NBD=m
102CONFIG_BLK_DEV_RAM=y
103CONFIG_BLK_DEV_RAM_SIZE=65536
104CONFIG_ATMEL_TCLIB=y
105CONFIG_ATMEL_SSC=m
106CONFIG_SENSORS_TSL2550=m
107CONFIG_DS1682=m
108CONFIG_RAID_ATTRS=m
109CONFIG_SCSI=m
110CONFIG_SCSI_TGT=m
111# CONFIG_SCSI_PROC_FS is not set
112CONFIG_BLK_DEV_SD=m
113CONFIG_BLK_DEV_SR=m
114CONFIG_CHR_DEV_SG=m
115CONFIG_CHR_DEV_SCH=m
116CONFIG_SCSI_MULTI_LUN=y
117CONFIG_SCSI_CONSTANTS=y
118CONFIG_SCSI_LOGGING=y
119CONFIG_SCSI_SCAN_ASYNC=y
120CONFIG_SCSI_ISCSI_ATTRS=m
121CONFIG_NETDEVICES=y
122CONFIG_DUMMY=m
123CONFIG_BONDING=m
124CONFIG_MACVLAN=m
125CONFIG_EQUALIZER=m
126CONFIG_TUN=m
127CONFIG_VETH=m
128CONFIG_PHYLIB=y
129CONFIG_MARVELL_PHY=m
130CONFIG_DAVICOM_PHY=m
131CONFIG_QSEMI_PHY=m
132CONFIG_LXT_PHY=m
133CONFIG_CICADA_PHY=m
134CONFIG_VITESSE_PHY=m
135CONFIG_SMSC_PHY=m
136CONFIG_BROADCOM_PHY=m
137CONFIG_ICPLUS_PHY=m
138CONFIG_MDIO_BITBANG=m
139CONFIG_NET_ETHERNET=y
140# CONFIG_NETDEV_1000 is not set
141# CONFIG_NETDEV_10000 is not set
142CONFIG_USB_ZD1201=m
143CONFIG_HOSTAP=m
144CONFIG_HOSTAP_FIRMWARE=y
145CONFIG_HOSTAP_FIRMWARE_NVRAM=y
146CONFIG_USB_CATC=m
147CONFIG_USB_KAWETH=m
148CONFIG_USB_PEGASUS=m
149CONFIG_USB_RTL8150=m
150CONFIG_USB_USBNET=m
151CONFIG_USB_NET_DM9601=m
152CONFIG_USB_NET_GL620A=m
153CONFIG_USB_NET_PLUSB=m
154CONFIG_USB_NET_MCS7830=m
155CONFIG_USB_NET_RNDIS_HOST=m
156CONFIG_USB_ALI_M5632=y
157CONFIG_USB_AN2720=y
158CONFIG_USB_EPSON2888=y
159CONFIG_USB_KC2190=y
160# CONFIG_USB_NET_ZAURUS is not set
161CONFIG_INPUT_MOUSEDEV=m
162CONFIG_INPUT_EVDEV=m
163CONFIG_INPUT_EVBUG=m
164CONFIG_KEYBOARD_LKKBD=m
165CONFIG_KEYBOARD_GPIO=m
166CONFIG_KEYBOARD_NEWTON=m
167CONFIG_KEYBOARD_STOWAWAY=m
168CONFIG_KEYBOARD_SUNKBD=m
169CONFIG_KEYBOARD_XTKBD=m
170CONFIG_MOUSE_PS2=m
171CONFIG_MOUSE_SERIAL=m
172CONFIG_MOUSE_APPLETOUCH=m
173CONFIG_MOUSE_VSXXXAA=m
174CONFIG_MOUSE_GPIO=m
175CONFIG_INPUT_MISC=y
176CONFIG_INPUT_UINPUT=m
177CONFIG_SERIO_SERPORT=m
178CONFIG_SERIO_RAW=m
179CONFIG_VT_HW_CONSOLE_BINDING=y
180CONFIG_SERIAL_NONSTANDARD=y
181CONFIG_N_HDLC=m
182CONFIG_SPECIALIX=m
183CONFIG_STALDRV=y
184CONFIG_SERIAL_ATMEL=y
185CONFIG_SERIAL_ATMEL_CONSOLE=y
186CONFIG_IPMI_HANDLER=m
187CONFIG_IPMI_DEVICE_INTERFACE=m
188CONFIG_IPMI_SI=m
189CONFIG_IPMI_WATCHDOG=m
190CONFIG_IPMI_POWEROFF=m
191CONFIG_HW_RANDOM=y
192CONFIG_R3964=m
193CONFIG_RAW_DRIVER=m
194CONFIG_TCG_TPM=m
195CONFIG_TCG_NSC=m
196CONFIG_TCG_ATMEL=m
197CONFIG_I2C=m
198CONFIG_I2C_CHARDEV=m
199CONFIG_SPI=y
200CONFIG_SPI_ATMEL=y
201CONFIG_SPI_BITBANG=m
202CONFIG_SPI_SPIDEV=m
203# CONFIG_HWMON is not set
204# CONFIG_VGA_CONSOLE is not set
205CONFIG_SOUND=m
206CONFIG_SND=m
207CONFIG_SND_SEQUENCER=m
208CONFIG_SND_SEQ_DUMMY=m
209CONFIG_SND_MIXER_OSS=m
210CONFIG_SND_PCM_OSS=m
211# CONFIG_SND_PCM_OSS_PLUGINS is not set
212CONFIG_SND_SEQUENCER_OSS=y
213CONFIG_SND_DYNAMIC_MINORS=y
214# CONFIG_SND_VERBOSE_PROCFS is not set
215CONFIG_SND_DUMMY=m
216CONFIG_SND_VIRMIDI=m
217CONFIG_SND_USB_AUDIO=m
218CONFIG_SND_USB_CAIAQ=m
219CONFIG_SND_USB_CAIAQ_INPUT=y
220CONFIG_HID=m
221CONFIG_HIDRAW=y
222CONFIG_USB_HID=m
223CONFIG_USB_HIDDEV=y
224CONFIG_USB_KBD=m
225CONFIG_USB_MOUSE=m
226CONFIG_HID_A4TECH=m
227CONFIG_HID_APPLE=m
228CONFIG_HID_BELKIN=m
229CONFIG_HID_CHERRY=m
230CONFIG_HID_CHICONY=m
231CONFIG_HID_CYPRESS=m
232CONFIG_HID_EZKEY=m
233CONFIG_HID_GYRATION=m
234CONFIG_HID_LOGITECH=m
235CONFIG_HID_MICROSOFT=m
236CONFIG_HID_MONTEREY=m
237CONFIG_HID_PANTHERLORD=m
238CONFIG_HID_PETALYNX=m
239CONFIG_HID_SAMSUNG=m
240CONFIG_HID_SONY=m
241CONFIG_HID_SUNPLUS=m
242CONFIG_USB=y
243CONFIG_USB_DEVICEFS=y
244# CONFIG_USB_DEVICE_CLASS is not set
245CONFIG_USB_DYNAMIC_MINORS=y
246CONFIG_USB_MON=y
247CONFIG_USB_OHCI_HCD=y
248CONFIG_USB_STORAGE=m
249CONFIG_USB_STORAGE_DATAFAB=m
250CONFIG_USB_STORAGE_FREECOM=m
251CONFIG_USB_STORAGE_ISD200=m
252CONFIG_USB_STORAGE_USBAT=m
253CONFIG_USB_STORAGE_SDDR09=m
254CONFIG_USB_STORAGE_SDDR55=m
255CONFIG_USB_STORAGE_JUMPSHOT=m
256CONFIG_USB_STORAGE_ALAUDA=m
257CONFIG_USB_STORAGE_KARMA=m
258CONFIG_USB_LIBUSUAL=y
259CONFIG_USB_SERIAL=m
260CONFIG_USB_EZUSB=y
261CONFIG_USB_SERIAL_GENERIC=y
262CONFIG_USB_SERIAL_PL2303=m
263CONFIG_USB_SERIAL_SPCP8X5=m
264CONFIG_USB_SERIAL_DEBUG=m
265CONFIG_USB_EMI62=m
266CONFIG_USB_EMI26=m
267CONFIG_USB_ADUTUX=m
268CONFIG_USB_TEST=m
269CONFIG_USB_GADGET=m
270CONFIG_USB_GADGET_DEBUG_FILES=y
271CONFIG_USB_GADGET_DEBUG_FS=y
272CONFIG_USB_ZERO=m
273CONFIG_USB_ETH=m
274CONFIG_USB_GADGETFS=m
275CONFIG_USB_FILE_STORAGE=m
276CONFIG_USB_G_SERIAL=m
277CONFIG_USB_MIDI_GADGET=m
278CONFIG_MMC=y
279CONFIG_SDIO_UART=m
280CONFIG_MMC_AT91=m
281CONFIG_MMC_SPI=m
282CONFIG_NEW_LEDS=y
283CONFIG_LEDS_CLASS=m
284CONFIG_LEDS_GPIO=m
285CONFIG_LEDS_TRIGGERS=y
286CONFIG_LEDS_TRIGGER_TIMER=m
287CONFIG_LEDS_TRIGGER_HEARTBEAT=m
288CONFIG_RTC_CLASS=y
289CONFIG_RTC_INTF_DEV_UIE_EMUL=y
290CONFIG_RTC_DRV_DS1307=m
291CONFIG_RTC_DRV_DS1305=y
292CONFIG_EXT2_FS=y
293CONFIG_EXT2_FS_XATTR=y
294CONFIG_EXT2_FS_POSIX_ACL=y
295CONFIG_EXT2_FS_SECURITY=y
296CONFIG_EXT3_FS=y
297CONFIG_EXT3_FS_POSIX_ACL=y
298CONFIG_EXT3_FS_SECURITY=y
299CONFIG_JBD_DEBUG=y
300CONFIG_REISERFS_FS=m
301CONFIG_REISERFS_CHECK=y
302CONFIG_REISERFS_PROC_INFO=y
303CONFIG_REISERFS_FS_XATTR=y
304CONFIG_REISERFS_FS_POSIX_ACL=y
305CONFIG_REISERFS_FS_SECURITY=y
306CONFIG_INOTIFY=y
307CONFIG_FUSE_FS=m
308CONFIG_MSDOS_FS=m
309CONFIG_VFAT_FS=y
310CONFIG_NTFS_FS=m
311CONFIG_NTFS_RW=y
312CONFIG_TMPFS=y
313CONFIG_TMPFS_POSIX_ACL=y
314CONFIG_JFFS2_FS=m
315CONFIG_JFFS2_COMPRESSION_OPTIONS=y
316CONFIG_JFFS2_LZO=y
317CONFIG_JFFS2_CMODE_FAVOURLZO=y
318CONFIG_CRAMFS=m
319CONFIG_NFS_FS=m
320CONFIG_NFS_V3=y
321CONFIG_NFS_V3_ACL=y
322CONFIG_NFS_V4=y
323CONFIG_NFSD=m
324CONFIG_NFSD_V3_ACL=y
325CONFIG_NFSD_V4=y
326CONFIG_CIFS=m
327CONFIG_CIFS_WEAK_PW_HASH=y
328CONFIG_PARTITION_ADVANCED=y
329CONFIG_MAC_PARTITION=y
330CONFIG_BSD_DISKLABEL=y
331CONFIG_MINIX_SUBPARTITION=y
332CONFIG_SOLARIS_X86_PARTITION=y
333CONFIG_UNIXWARE_DISKLABEL=y
334CONFIG_LDM_PARTITION=y
335CONFIG_LDM_DEBUG=y
336CONFIG_SGI_PARTITION=y
337CONFIG_SUN_PARTITION=y
338CONFIG_NLS_DEFAULT="cp437"
339CONFIG_NLS_CODEPAGE_437=y
340CONFIG_NLS_CODEPAGE_850=m
341CONFIG_NLS_ASCII=y
342CONFIG_NLS_ISO8859_1=y
343CONFIG_NLS_UTF8=m
344CONFIG_DLM=m
345CONFIG_PRINTK_TIME=y
346CONFIG_MAGIC_SYSRQ=y
347CONFIG_UNUSED_SYMBOLS=y
348CONFIG_DEBUG_FS=y
349# CONFIG_RCU_CPU_STALL_DETECTOR is not set
350CONFIG_SYSCTL_SYSCALL_CHECK=y
351CONFIG_CRYPTO=y
352CONFIG_CRYPTO_GF128MUL=m
353CONFIG_CRYPTO_HMAC=y
354CONFIG_CRYPTO_MD5=y
355# CONFIG_CRYPTO_ANSI_CPRNG is not set
356# CONFIG_CRYPTO_HW is not set
357CONFIG_CRC_CCITT=m
358CONFIG_CRC16=m
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 8cbc3aae6c64..22484670e7ba 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -82,11 +82,6 @@ config ARCH_AT91CAP9
82 select HAVE_FB_ATMEL 82 select HAVE_FB_ATMEL
83 select HAVE_NET_MACB 83 select HAVE_NET_MACB
84 84
85config ARCH_AT572D940HF
86 bool "AT572D940HF"
87 select CPU_ARM926T
88 select GENERIC_CLOCKEVENTS
89
90config ARCH_AT91X40 85config ARCH_AT91X40
91 bool "AT91x40" 86 bool "AT91x40"
92 select ARCH_USES_GETTIMEOFFSET 87 select ARCH_USES_GETTIMEOFFSET
@@ -431,22 +426,6 @@ endif
431 426
432# ---------------------------------------------------------- 427# ----------------------------------------------------------
433 428
434if ARCH_AT572D940HF
435
436comment "AT572D940HF Board Type"
437
438config MACH_AT572D940HFEB
439 bool "AT572D940HF-EK"
440 depends on ARCH_AT572D940HF
441 select HAVE_AT91_DATAFLASH_CARD
442 help
443 Select this if you are using Atmel's AT572D940HF-EK evaluation kit.
444 <http://www.atmel.com/products/diopsis/default.asp>
445
446endif
447
448# ----------------------------------------------------------
449
450if ARCH_AT91X40 429if ARCH_AT91X40
451 430
452comment "AT91X40 Board Type" 431comment "AT91X40 Board Type"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index a83835e0c185..96966231920c 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devi
19obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o 19obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
20obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o 20obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
21obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o 21obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
22obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
23obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 22obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
24 23
25# AT91RM9200 board-specific support 24# AT91RM9200 board-specific support
@@ -78,9 +77,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
78# AT91CAP9 board-specific support 77# AT91CAP9 board-specific support
79obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o 78obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
80 79
81# AT572D940HF board-specific support
82obj-$(CONFIG_MACH_AT572D940HFEB) += board-at572d940hf_ek.o
83
84# AT91X40 board-specific support 80# AT91X40 board-specific support
85obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o 81obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
86 82
diff --git a/arch/arm/mach-at91/at572d940hf.c b/arch/arm/mach-at91/at572d940hf.c
deleted file mode 100644
index d06990777ffe..000000000000
--- a/arch/arm/mach-at91/at572d940hf.c
+++ /dev/null
@@ -1,412 +0,0 @@
1/*
2 * arch/arm/mach-at91/at572d940hf.c
3 *
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
6 *
7 * Copyright (C) 2005 SAN People
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/module.h>
26
27#include <asm/mach/irq.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <mach/at572d940hf.h>
31#include <mach/at91_pmc.h>
32#include <mach/at91_rstc.h>
33
34#include "generic.h"
35#include "clock.h"
36
37static struct map_desc at572d940hf_io_desc[] __initdata = {
38 {
39 .virtual = AT91_VA_BASE_SYS,
40 .pfn = __phys_to_pfn(AT91_BASE_SYS),
41 .length = SZ_16K,
42 .type = MT_DEVICE,
43 }, {
44 .virtual = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE,
45 .pfn = __phys_to_pfn(AT572D940HF_SRAM_BASE),
46 .length = AT572D940HF_SRAM_SIZE,
47 .type = MT_DEVICE,
48 },
49};
50
51/* --------------------------------------------------------------------
52 * Clocks
53 * -------------------------------------------------------------------- */
54
55/*
56 * The peripheral clocks.
57 */
58static struct clk pioA_clk = {
59 .name = "pioA_clk",
60 .pmc_mask = 1 << AT572D940HF_ID_PIOA,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk pioB_clk = {
64 .name = "pioB_clk",
65 .pmc_mask = 1 << AT572D940HF_ID_PIOB,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk pioC_clk = {
69 .name = "pioC_clk",
70 .pmc_mask = 1 << AT572D940HF_ID_PIOC,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk macb_clk = {
74 .name = "macb_clk",
75 .pmc_mask = 1 << AT572D940HF_ID_EMAC,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk usart0_clk = {
79 .name = "usart0_clk",
80 .pmc_mask = 1 << AT572D940HF_ID_US0,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk usart1_clk = {
84 .name = "usart1_clk",
85 .pmc_mask = 1 << AT572D940HF_ID_US1,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk usart2_clk = {
89 .name = "usart2_clk",
90 .pmc_mask = 1 << AT572D940HF_ID_US2,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk mmc_clk = {
94 .name = "mci_clk",
95 .pmc_mask = 1 << AT572D940HF_ID_MCI,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk udc_clk = {
99 .name = "udc_clk",
100 .pmc_mask = 1 << AT572D940HF_ID_UDP,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk twi0_clk = {
104 .name = "twi0_clk",
105 .pmc_mask = 1 << AT572D940HF_ID_TWI0,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk spi0_clk = {
109 .name = "spi0_clk",
110 .pmc_mask = 1 << AT572D940HF_ID_SPI0,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk spi1_clk = {
114 .name = "spi1_clk",
115 .pmc_mask = 1 << AT572D940HF_ID_SPI1,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk ssc0_clk = {
119 .name = "ssc0_clk",
120 .pmc_mask = 1 << AT572D940HF_ID_SSC0,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk ssc1_clk = {
124 .name = "ssc1_clk",
125 .pmc_mask = 1 << AT572D940HF_ID_SSC1,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk ssc2_clk = {
129 .name = "ssc2_clk",
130 .pmc_mask = 1 << AT572D940HF_ID_SSC2,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk tc0_clk = {
134 .name = "tc0_clk",
135 .pmc_mask = 1 << AT572D940HF_ID_TC0,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk tc1_clk = {
139 .name = "tc1_clk",
140 .pmc_mask = 1 << AT572D940HF_ID_TC1,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143static struct clk tc2_clk = {
144 .name = "tc2_clk",
145 .pmc_mask = 1 << AT572D940HF_ID_TC2,
146 .type = CLK_TYPE_PERIPHERAL,
147};
148static struct clk ohci_clk = {
149 .name = "ohci_clk",
150 .pmc_mask = 1 << AT572D940HF_ID_UHP,
151 .type = CLK_TYPE_PERIPHERAL,
152};
153static struct clk ssc3_clk = {
154 .name = "ssc3_clk",
155 .pmc_mask = 1 << AT572D940HF_ID_SSC3,
156 .type = CLK_TYPE_PERIPHERAL,
157};
158static struct clk twi1_clk = {
159 .name = "twi1_clk",
160 .pmc_mask = 1 << AT572D940HF_ID_TWI1,
161 .type = CLK_TYPE_PERIPHERAL,
162};
163static struct clk can0_clk = {
164 .name = "can0_clk",
165 .pmc_mask = 1 << AT572D940HF_ID_CAN0,
166 .type = CLK_TYPE_PERIPHERAL,
167};
168static struct clk can1_clk = {
169 .name = "can1_clk",
170 .pmc_mask = 1 << AT572D940HF_ID_CAN1,
171 .type = CLK_TYPE_PERIPHERAL,
172};
173static struct clk mAgicV_clk = {
174 .name = "mAgicV_clk",
175 .pmc_mask = 1 << AT572D940HF_ID_MSIRQ0,
176 .type = CLK_TYPE_PERIPHERAL,
177};
178
179
180static struct clk *periph_clocks[] __initdata = {
181 &pioA_clk,
182 &pioB_clk,
183 &pioC_clk,
184 &macb_clk,
185 &usart0_clk,
186 &usart1_clk,
187 &usart2_clk,
188 &mmc_clk,
189 &udc_clk,
190 &twi0_clk,
191 &spi0_clk,
192 &spi1_clk,
193 &ssc0_clk,
194 &ssc1_clk,
195 &ssc2_clk,
196 &tc0_clk,
197 &tc1_clk,
198 &tc2_clk,
199 &ohci_clk,
200 &ssc3_clk,
201 &twi1_clk,
202 &can0_clk,
203 &can1_clk,
204 &mAgicV_clk,
205 /* irq0 .. irq2 */
206};
207
208static struct clk_lookup periph_clocks_lookups[] = {
209 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
210 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
211 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
212 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
213 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
214};
215
216static struct clk_lookup usart_clocks_lookups[] = {
217 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
218 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
219 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
220 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
221};
222
223/*
224 * The five programmable clocks.
225 * You must configure pin multiplexing to bring these signals out.
226 */
227static struct clk pck0 = {
228 .name = "pck0",
229 .pmc_mask = AT91_PMC_PCK0,
230 .type = CLK_TYPE_PROGRAMMABLE,
231 .id = 0,
232};
233static struct clk pck1 = {
234 .name = "pck1",
235 .pmc_mask = AT91_PMC_PCK1,
236 .type = CLK_TYPE_PROGRAMMABLE,
237 .id = 1,
238};
239static struct clk pck2 = {
240 .name = "pck2",
241 .pmc_mask = AT91_PMC_PCK2,
242 .type = CLK_TYPE_PROGRAMMABLE,
243 .id = 2,
244};
245static struct clk pck3 = {
246 .name = "pck3",
247 .pmc_mask = AT91_PMC_PCK3,
248 .type = CLK_TYPE_PROGRAMMABLE,
249 .id = 3,
250};
251
252static struct clk mAgicV_mem_clk = {
253 .name = "mAgicV_mem_clk",
254 .pmc_mask = AT91_PMC_PCK4,
255 .type = CLK_TYPE_PROGRAMMABLE,
256 .id = 4,
257};
258
259/* HClocks */
260static struct clk hck0 = {
261 .name = "hck0",
262 .pmc_mask = AT91_PMC_HCK0,
263 .type = CLK_TYPE_SYSTEM,
264 .id = 0,
265};
266static struct clk hck1 = {
267 .name = "hck1",
268 .pmc_mask = AT91_PMC_HCK1,
269 .type = CLK_TYPE_SYSTEM,
270 .id = 1,
271};
272
273static void __init at572d940hf_register_clocks(void)
274{
275 int i;
276
277 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
278 clk_register(periph_clocks[i]);
279
280 clkdev_add_table(periph_clocks_lookups,
281 ARRAY_SIZE(periph_clocks_lookups));
282 clkdev_add_table(usart_clocks_lookups,
283 ARRAY_SIZE(usart_clocks_lookups));
284
285 clk_register(&pck0);
286 clk_register(&pck1);
287 clk_register(&pck2);
288 clk_register(&pck3);
289 clk_register(&mAgicV_mem_clk);
290
291 clk_register(&hck0);
292 clk_register(&hck1);
293}
294
295static struct clk_lookup console_clock_lookup;
296
297void __init at572d940hf_set_console_clock(int id)
298{
299 if (id >= ARRAY_SIZE(usart_clocks_lookups))
300 return;
301
302 console_clock_lookup.con_id = "usart";
303 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
304 clkdev_add(&console_clock_lookup);
305}
306
307/* --------------------------------------------------------------------
308 * GPIO
309 * -------------------------------------------------------------------- */
310
311static struct at91_gpio_bank at572d940hf_gpio[] = {
312 {
313 .id = AT572D940HF_ID_PIOA,
314 .offset = AT91_PIOA,
315 .clock = &pioA_clk,
316 }, {
317 .id = AT572D940HF_ID_PIOB,
318 .offset = AT91_PIOB,
319 .clock = &pioB_clk,
320 }, {
321 .id = AT572D940HF_ID_PIOC,
322 .offset = AT91_PIOC,
323 .clock = &pioC_clk,
324 }
325};
326
327static void at572d940hf_reset(void)
328{
329 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
330}
331
332
333/* --------------------------------------------------------------------
334 * AT572D940HF processor initialization
335 * -------------------------------------------------------------------- */
336
337void __init at572d940hf_map_io(void)
338{
339 /* Map peripherals */
340 iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));
341}
342
343void __init at572d940hf_initialize(unsigned long main_clock)
344{
345 at91_arch_reset = at572d940hf_reset;
346 at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
347 | (1 << AT572D940HF_ID_IRQ2);
348
349 /* Init clock subsystem */
350 at91_clock_init(main_clock);
351
352 /* Register the processor-specific clocks */
353 at572d940hf_register_clocks();
354
355 /* Register GPIO subsystem */
356 at91_gpio_init(at572d940hf_gpio, 3);
357}
358
359/* --------------------------------------------------------------------
360 * Interrupt initialization
361 * -------------------------------------------------------------------- */
362
363/*
364 * The default interrupt priority levels (0 = lowest, 7 = highest).
365 */
366static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = {
367 7, /* Advanced Interrupt Controller */
368 7, /* System Peripherals */
369 0, /* Parallel IO Controller A */
370 0, /* Parallel IO Controller B */
371 0, /* Parallel IO Controller C */
372 3, /* Ethernet */
373 6, /* USART 0 */
374 6, /* USART 1 */
375 6, /* USART 2 */
376 0, /* Multimedia Card Interface */
377 4, /* USB Device Port */
378 0, /* Two-Wire Interface 0 */
379 6, /* Serial Peripheral Interface 0 */
380 6, /* Serial Peripheral Interface 1 */
381 5, /* Serial Synchronous Controller 0 */
382 5, /* Serial Synchronous Controller 1 */
383 5, /* Serial Synchronous Controller 2 */
384 0, /* Timer Counter 0 */
385 0, /* Timer Counter 1 */
386 0, /* Timer Counter 2 */
387 3, /* USB Host port */
388 3, /* Serial Synchronous Controller 3 */
389 0, /* Two-Wire Interface 1 */
390 0, /* CAN Controller 0 */
391 0, /* CAN Controller 1 */
392 0, /* mAgicV HALT line */
393 0, /* mAgicV SIRQ0 line */
394 0, /* mAgicV exception line */
395 0, /* mAgicV end of DMA line */
396 0, /* Advanced Interrupt Controller */
397 0, /* Advanced Interrupt Controller */
398 0, /* Advanced Interrupt Controller */
399};
400
401void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])
402{
403 if (!priority)
404 priority = at572d940hf_default_irq_priority;
405
406 /* Initialize the AIC interrupt controller */
407 at91_aic_init(priority);
408
409 /* Enable GPIO interrupts */
410 at91_gpio_irq_setup();
411}
412
diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c
deleted file mode 100644
index 14863b8e7e6a..000000000000
--- a/arch/arm/mach-at91/at572d940hf_devices.c
+++ /dev/null
@@ -1,964 +0,0 @@
1/*
2 * arch/arm/mach-at91/at572d940hf_devices.c
3 *
4 * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
6 * Copyright (C) 2005 David Brownell
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29
30#include <mach/board.h>
31#include <mach/gpio.h>
32#include <mach/at572d940hf.h>
33#include <mach/at572d940hf_matrix.h>
34#include <mach/at91sam9_smc.h>
35
36#include "generic.h"
37#include "sam9_smc.h"
38
39
40/* --------------------------------------------------------------------
41 * USB Host
42 * -------------------------------------------------------------------- */
43
44#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
45static u64 ohci_dmamask = DMA_BIT_MASK(32);
46static struct at91_usbh_data usbh_data;
47
48static struct resource usbh_resources[] = {
49 [0] = {
50 .start = AT572D940HF_UHP_BASE,
51 .end = AT572D940HF_UHP_BASE + SZ_1M - 1,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = {
55 .start = AT572D940HF_ID_UHP,
56 .end = AT572D940HF_ID_UHP,
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61static struct platform_device at572d940hf_usbh_device = {
62 .name = "at91_ohci",
63 .id = -1,
64 .dev = {
65 .dma_mask = &ohci_dmamask,
66 .coherent_dma_mask = DMA_BIT_MASK(32),
67 .platform_data = &usbh_data,
68 },
69 .resource = usbh_resources,
70 .num_resources = ARRAY_SIZE(usbh_resources),
71};
72
73void __init at91_add_device_usbh(struct at91_usbh_data *data)
74{
75 if (!data)
76 return;
77
78 usbh_data = *data;
79 platform_device_register(&at572d940hf_usbh_device);
80
81}
82#else
83void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84#endif
85
86
87/* --------------------------------------------------------------------
88 * USB Device (Gadget)
89 * -------------------------------------------------------------------- */
90
91#ifdef CONFIG_USB_GADGET_AT91
92static struct at91_udc_data udc_data;
93
94static struct resource udc_resources[] = {
95 [0] = {
96 .start = AT572D940HF_BASE_UDP,
97 .end = AT572D940HF_BASE_UDP + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
101 .start = AT572D940HF_ID_UDP,
102 .end = AT572D940HF_ID_UDP,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device at572d940hf_udc_device = {
108 .name = "at91_udc",
109 .id = -1,
110 .dev = {
111 .platform_data = &udc_data,
112 },
113 .resource = udc_resources,
114 .num_resources = ARRAY_SIZE(udc_resources),
115};
116
117void __init at91_add_device_udc(struct at91_udc_data *data)
118{
119 if (!data)
120 return;
121
122 if (data->vbus_pin) {
123 at91_set_gpio_input(data->vbus_pin, 0);
124 at91_set_deglitch(data->vbus_pin, 1);
125 }
126
127 /* Pullup pin is handled internally */
128
129 udc_data = *data;
130 platform_device_register(&at572d940hf_udc_device);
131}
132#else
133void __init at91_add_device_udc(struct at91_udc_data *data) {}
134#endif
135
136
137/* --------------------------------------------------------------------
138 * Ethernet
139 * -------------------------------------------------------------------- */
140
141#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
142static u64 eth_dmamask = DMA_BIT_MASK(32);
143static struct at91_eth_data eth_data;
144
145static struct resource eth_resources[] = {
146 [0] = {
147 .start = AT572D940HF_BASE_EMAC,
148 .end = AT572D940HF_BASE_EMAC + SZ_16K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = AT572D940HF_ID_EMAC,
153 .end = AT572D940HF_ID_EMAC,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device at572d940hf_eth_device = {
159 .name = "macb",
160 .id = -1,
161 .dev = {
162 .dma_mask = &eth_dmamask,
163 .coherent_dma_mask = DMA_BIT_MASK(32),
164 .platform_data = &eth_data,
165 },
166 .resource = eth_resources,
167 .num_resources = ARRAY_SIZE(eth_resources),
168};
169
170void __init at91_add_device_eth(struct at91_eth_data *data)
171{
172 if (!data)
173 return;
174
175 if (data->phy_irq_pin) {
176 at91_set_gpio_input(data->phy_irq_pin, 0);
177 at91_set_deglitch(data->phy_irq_pin, 1);
178 }
179
180 /* Only RMII is supported */
181 data->is_rmii = 1;
182
183 /* Pins used for RMII */
184 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXCK_EREFCK */
185 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
186 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERX0 */
187 at91_set_A_periph(AT91_PIN_PA19, 0); /* ERX1 */
188 at91_set_A_periph(AT91_PIN_PA20, 0); /* ERXER */
189 at91_set_A_periph(AT91_PIN_PA23, 0); /* ETXEN */
190 at91_set_A_periph(AT91_PIN_PA21, 0); /* ETX0 */
191 at91_set_A_periph(AT91_PIN_PA22, 0); /* ETX1 */
192 at91_set_A_periph(AT91_PIN_PA13, 0); /* EMDIO */
193 at91_set_A_periph(AT91_PIN_PA14, 0); /* EMDC */
194
195 eth_data = *data;
196 platform_device_register(&at572d940hf_eth_device);
197}
198#else
199void __init at91_add_device_eth(struct at91_eth_data *data) {}
200#endif
201
202
203/* --------------------------------------------------------------------
204 * MMC / SD
205 * -------------------------------------------------------------------- */
206
207#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
208static u64 mmc_dmamask = DMA_BIT_MASK(32);
209static struct at91_mmc_data mmc_data;
210
211static struct resource mmc_resources[] = {
212 [0] = {
213 .start = AT572D940HF_BASE_MCI,
214 .end = AT572D940HF_BASE_MCI + SZ_16K - 1,
215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
218 .start = AT572D940HF_ID_MCI,
219 .end = AT572D940HF_ID_MCI,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device at572d940hf_mmc_device = {
225 .name = "at91_mci",
226 .id = -1,
227 .dev = {
228 .dma_mask = &mmc_dmamask,
229 .coherent_dma_mask = DMA_BIT_MASK(32),
230 .platform_data = &mmc_data,
231 },
232 .resource = mmc_resources,
233 .num_resources = ARRAY_SIZE(mmc_resources),
234};
235
236void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
237{
238 if (!data)
239 return;
240
241 /* input/irq */
242 if (data->det_pin) {
243 at91_set_gpio_input(data->det_pin, 1);
244 at91_set_deglitch(data->det_pin, 1);
245 }
246 if (data->wp_pin)
247 at91_set_gpio_input(data->wp_pin, 1);
248 if (data->vcc_pin)
249 at91_set_gpio_output(data->vcc_pin, 0);
250
251 /* CLK */
252 at91_set_A_periph(AT91_PIN_PC22, 0);
253
254 /* CMD */
255 at91_set_A_periph(AT91_PIN_PC23, 1);
256
257 /* DAT0, maybe DAT1..DAT3 */
258 at91_set_A_periph(AT91_PIN_PC24, 1);
259 if (data->wire4) {
260 at91_set_A_periph(AT91_PIN_PC25, 1);
261 at91_set_A_periph(AT91_PIN_PC26, 1);
262 at91_set_A_periph(AT91_PIN_PC27, 1);
263 }
264
265 mmc_data = *data;
266 platform_device_register(&at572d940hf_mmc_device);
267}
268#else
269void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
270#endif
271
272
273/* --------------------------------------------------------------------
274 * NAND / SmartMedia
275 * -------------------------------------------------------------------- */
276
277#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
278static struct atmel_nand_data nand_data;
279
280#define NAND_BASE AT91_CHIPSELECT_3
281
282static struct resource nand_resources[] = {
283 {
284 .start = NAND_BASE,
285 .end = NAND_BASE + SZ_256M - 1,
286 .flags = IORESOURCE_MEM,
287 }
288};
289
290static struct platform_device at572d940hf_nand_device = {
291 .name = "atmel_nand",
292 .id = -1,
293 .dev = {
294 .platform_data = &nand_data,
295 },
296 .resource = nand_resources,
297 .num_resources = ARRAY_SIZE(nand_resources),
298};
299
300void __init at91_add_device_nand(struct atmel_nand_data *data)
301{
302 unsigned long csa;
303
304 if (!data)
305 return;
306
307 csa = at91_sys_read(AT91_MATRIX_EBICSA);
308 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
309
310 /* enable pin */
311 if (data->enable_pin)
312 at91_set_gpio_output(data->enable_pin, 1);
313
314 /* ready/busy pin */
315 if (data->rdy_pin)
316 at91_set_gpio_input(data->rdy_pin, 1);
317
318 /* card detect pin */
319 if (data->det_pin)
320 at91_set_gpio_input(data->det_pin, 1);
321
322 at91_set_A_periph(AT91_PIN_PB28, 0); /* A[22] */
323 at91_set_B_periph(AT91_PIN_PA28, 0); /* NANDOE */
324 at91_set_B_periph(AT91_PIN_PA29, 0); /* NANDWE */
325
326 nand_data = *data;
327 platform_device_register(&at572d940hf_nand_device);
328}
329
330#else
331void __init at91_add_device_nand(struct atmel_nand_data *data) {}
332#endif
333
334
335/* --------------------------------------------------------------------
336 * TWI (i2c)
337 * -------------------------------------------------------------------- */
338
339/*
340 * Prefer the GPIO code since the TWI controller isn't robust
341 * (gets overruns and underruns under load) and can only issue
342 * repeated STARTs in one scenario (the driver doesn't yet handle them).
343 */
344
345#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
346
347static struct i2c_gpio_platform_data pdata = {
348 .sda_pin = AT91_PIN_PC7,
349 .sda_is_open_drain = 1,
350 .scl_pin = AT91_PIN_PC8,
351 .scl_is_open_drain = 1,
352 .udelay = 2, /* ~100 kHz */
353};
354
355static struct platform_device at572d940hf_twi_device {
356 .name = "i2c-gpio",
357 .id = -1,
358 .dev.platform_data = &pdata,
359};
360
361void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
362{
363 at91_set_GPIO_periph(AT91_PIN_PC7, 1); /* TWD (SDA) */
364 at91_set_multi_drive(AT91_PIN_PC7, 1);
365
366 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
367 at91_set_multi_drive(AT91_PIN_PC8, 1);
368
369 i2c_register_board_info(0, devices, nr_devices);
370 platform_device_register(&at572d940hf_twi_device);
371}
372
373#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
374
375static struct resource twi0_resources[] = {
376 [0] = {
377 .start = AT572D940HF_BASE_TWI0,
378 .end = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
379 .flags = IORESOURCE_MEM,
380 },
381 [1] = {
382 .start = AT572D940HF_ID_TWI0,
383 .end = AT572D940HF_ID_TWI0,
384 .flags = IORESOURCE_IRQ,
385 },
386};
387
388static struct platform_device at572d940hf_twi0_device = {
389 .name = "at91_i2c",
390 .id = 0,
391 .resource = twi0_resources,
392 .num_resources = ARRAY_SIZE(twi0_resources),
393};
394
395static struct resource twi1_resources[] = {
396 [0] = {
397 .start = AT572D940HF_BASE_TWI1,
398 .end = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
399 .flags = IORESOURCE_MEM,
400 },
401 [1] = {
402 .start = AT572D940HF_ID_TWI1,
403 .end = AT572D940HF_ID_TWI1,
404 .flags = IORESOURCE_IRQ,
405 },
406};
407
408static struct platform_device at572d940hf_twi1_device = {
409 .name = "at91_i2c",
410 .id = 1,
411 .resource = twi1_resources,
412 .num_resources = ARRAY_SIZE(twi1_resources),
413};
414
415void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
416{
417 /* pins used for TWI0 interface */
418 at91_set_A_periph(AT91_PIN_PC7, 0); /* TWD */
419 at91_set_multi_drive(AT91_PIN_PC7, 1);
420
421 at91_set_A_periph(AT91_PIN_PC8, 0); /* TWCK */
422 at91_set_multi_drive(AT91_PIN_PC8, 1);
423
424 /* pins used for TWI1 interface */
425 at91_set_A_periph(AT91_PIN_PC20, 0); /* TWD */
426 at91_set_multi_drive(AT91_PIN_PC20, 1);
427
428 at91_set_A_periph(AT91_PIN_PC21, 0); /* TWCK */
429 at91_set_multi_drive(AT91_PIN_PC21, 1);
430
431 i2c_register_board_info(0, devices, nr_devices);
432 platform_device_register(&at572d940hf_twi0_device);
433 platform_device_register(&at572d940hf_twi1_device);
434}
435#else
436void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
437#endif
438
439
440/* --------------------------------------------------------------------
441 * SPI
442 * -------------------------------------------------------------------- */
443
444#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
445static u64 spi_dmamask = DMA_BIT_MASK(32);
446
447static struct resource spi0_resources[] = {
448 [0] = {
449 .start = AT572D940HF_BASE_SPI0,
450 .end = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
451 .flags = IORESOURCE_MEM,
452 },
453 [1] = {
454 .start = AT572D940HF_ID_SPI0,
455 .end = AT572D940HF_ID_SPI0,
456 .flags = IORESOURCE_IRQ,
457 },
458};
459
460static struct platform_device at572d940hf_spi0_device = {
461 .name = "atmel_spi",
462 .id = 0,
463 .dev = {
464 .dma_mask = &spi_dmamask,
465 .coherent_dma_mask = DMA_BIT_MASK(32),
466 },
467 .resource = spi0_resources,
468 .num_resources = ARRAY_SIZE(spi0_resources),
469};
470
471static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
472
473static struct resource spi1_resources[] = {
474 [0] = {
475 .start = AT572D940HF_BASE_SPI1,
476 .end = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
477 .flags = IORESOURCE_MEM,
478 },
479 [1] = {
480 .start = AT572D940HF_ID_SPI1,
481 .end = AT572D940HF_ID_SPI1,
482 .flags = IORESOURCE_IRQ,
483 },
484};
485
486static struct platform_device at572d940hf_spi1_device = {
487 .name = "atmel_spi",
488 .id = 1,
489 .dev = {
490 .dma_mask = &spi_dmamask,
491 .coherent_dma_mask = DMA_BIT_MASK(32),
492 },
493 .resource = spi1_resources,
494 .num_resources = ARRAY_SIZE(spi1_resources),
495};
496
497static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
498
499void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
500{
501 int i;
502 unsigned long cs_pin;
503 short enable_spi0 = 0;
504 short enable_spi1 = 0;
505
506 /* Choose SPI chip-selects */
507 for (i = 0; i < nr_devices; i++) {
508 if (devices[i].controller_data)
509 cs_pin = (unsigned long) devices[i].controller_data;
510 else if (devices[i].bus_num == 0)
511 cs_pin = spi0_standard_cs[devices[i].chip_select];
512 else
513 cs_pin = spi1_standard_cs[devices[i].chip_select];
514
515 if (devices[i].bus_num == 0)
516 enable_spi0 = 1;
517 else
518 enable_spi1 = 1;
519
520 /* enable chip-select pin */
521 at91_set_gpio_output(cs_pin, 1);
522
523 /* pass chip-select pin to driver */
524 devices[i].controller_data = (void *) cs_pin;
525 }
526
527 spi_register_board_info(devices, nr_devices);
528
529 /* Configure SPI bus(es) */
530 if (enable_spi0) {
531 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
532 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
533 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
534
535 platform_device_register(&at572d940hf_spi0_device);
536 }
537 if (enable_spi1) {
538 at91_set_A_periph(AT91_PIN_PC0, 0); /* SPI1_MISO */
539 at91_set_A_periph(AT91_PIN_PC1, 0); /* SPI1_MOSI */
540 at91_set_A_periph(AT91_PIN_PC2, 0); /* SPI1_SPCK */
541
542 platform_device_register(&at572d940hf_spi1_device);
543 }
544}
545#else
546void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
547#endif
548
549
550/* --------------------------------------------------------------------
551 * Timer/Counter blocks
552 * -------------------------------------------------------------------- */
553
554#ifdef CONFIG_ATMEL_TCLIB
555
556static struct resource tcb_resources[] = {
557 [0] = {
558 .start = AT572D940HF_BASE_TCB,
559 .end = AT572D940HF_BASE_TCB + SZ_16K - 1,
560 .flags = IORESOURCE_MEM,
561 },
562 [1] = {
563 .start = AT572D940HF_ID_TC0,
564 .end = AT572D940HF_ID_TC0,
565 .flags = IORESOURCE_IRQ,
566 },
567 [2] = {
568 .start = AT572D940HF_ID_TC1,
569 .end = AT572D940HF_ID_TC1,
570 .flags = IORESOURCE_IRQ,
571 },
572 [3] = {
573 .start = AT572D940HF_ID_TC2,
574 .end = AT572D940HF_ID_TC2,
575 .flags = IORESOURCE_IRQ,
576 },
577};
578
579static struct platform_device at572d940hf_tcb_device = {
580 .name = "atmel_tcb",
581 .id = 0,
582 .resource = tcb_resources,
583 .num_resources = ARRAY_SIZE(tcb_resources),
584};
585
586static void __init at91_add_device_tc(void)
587{
588 platform_device_register(&at572d940hf_tcb_device);
589}
590#else
591static void __init at91_add_device_tc(void) { }
592#endif
593
594
595/* --------------------------------------------------------------------
596 * RTT
597 * -------------------------------------------------------------------- */
598
599static struct resource rtt_resources[] = {
600 {
601 .start = AT91_BASE_SYS + AT91_RTT,
602 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
603 .flags = IORESOURCE_MEM,
604 }
605};
606
607static struct platform_device at572d940hf_rtt_device = {
608 .name = "at91_rtt",
609 .id = 0,
610 .resource = rtt_resources,
611 .num_resources = ARRAY_SIZE(rtt_resources),
612};
613
614static void __init at91_add_device_rtt(void)
615{
616 platform_device_register(&at572d940hf_rtt_device);
617}
618
619
620/* --------------------------------------------------------------------
621 * Watchdog
622 * -------------------------------------------------------------------- */
623
624#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
625static struct platform_device at572d940hf_wdt_device = {
626 .name = "at91_wdt",
627 .id = -1,
628 .num_resources = 0,
629};
630
631static void __init at91_add_device_watchdog(void)
632{
633 platform_device_register(&at572d940hf_wdt_device);
634}
635#else
636static void __init at91_add_device_watchdog(void) {}
637#endif
638
639
640/* --------------------------------------------------------------------
641 * UART
642 * -------------------------------------------------------------------- */
643
644#if defined(CONFIG_SERIAL_ATMEL)
645static struct resource dbgu_resources[] = {
646 [0] = {
647 .start = AT91_VA_BASE_SYS + AT91_DBGU,
648 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
649 .flags = IORESOURCE_MEM,
650 },
651 [1] = {
652 .start = AT91_ID_SYS,
653 .end = AT91_ID_SYS,
654 .flags = IORESOURCE_IRQ,
655 },
656};
657
658static struct atmel_uart_data dbgu_data = {
659 .use_dma_tx = 0,
660 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
661 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
662};
663
664static u64 dbgu_dmamask = DMA_BIT_MASK(32);
665
666static struct platform_device at572d940hf_dbgu_device = {
667 .name = "atmel_usart",
668 .id = 0,
669 .dev = {
670 .dma_mask = &dbgu_dmamask,
671 .coherent_dma_mask = DMA_BIT_MASK(32),
672 .platform_data = &dbgu_data,
673 },
674 .resource = dbgu_resources,
675 .num_resources = ARRAY_SIZE(dbgu_resources),
676};
677
678static inline void configure_dbgu_pins(void)
679{
680 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
681 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
682}
683
684static struct resource uart0_resources[] = {
685 [0] = {
686 .start = AT572D940HF_BASE_US0,
687 .end = AT572D940HF_BASE_US0 + SZ_16K - 1,
688 .flags = IORESOURCE_MEM,
689 },
690 [1] = {
691 .start = AT572D940HF_ID_US0,
692 .end = AT572D940HF_ID_US0,
693 .flags = IORESOURCE_IRQ,
694 },
695};
696
697static struct atmel_uart_data uart0_data = {
698 .use_dma_tx = 1,
699 .use_dma_rx = 1,
700};
701
702static u64 uart0_dmamask = DMA_BIT_MASK(32);
703
704static struct platform_device at572d940hf_uart0_device = {
705 .name = "atmel_usart",
706 .id = 1,
707 .dev = {
708 .dma_mask = &uart0_dmamask,
709 .coherent_dma_mask = DMA_BIT_MASK(32),
710 .platform_data = &uart0_data,
711 },
712 .resource = uart0_resources,
713 .num_resources = ARRAY_SIZE(uart0_resources),
714};
715
716static inline void configure_usart0_pins(unsigned pins)
717{
718 at91_set_A_periph(AT91_PIN_PA8, 1); /* TXD0 */
719 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
720
721 if (pins & ATMEL_UART_RTS)
722 at91_set_A_periph(AT91_PIN_PA10, 0); /* RTS0 */
723 if (pins & ATMEL_UART_CTS)
724 at91_set_A_periph(AT91_PIN_PA9, 0); /* CTS0 */
725}
726
727static struct resource uart1_resources[] = {
728 [0] = {
729 .start = AT572D940HF_BASE_US1,
730 .end = AT572D940HF_BASE_US1 + SZ_16K - 1,
731 .flags = IORESOURCE_MEM,
732 },
733 [1] = {
734 .start = AT572D940HF_ID_US1,
735 .end = AT572D940HF_ID_US1,
736 .flags = IORESOURCE_IRQ,
737 },
738};
739
740static struct atmel_uart_data uart1_data = {
741 .use_dma_tx = 1,
742 .use_dma_rx = 1,
743};
744
745static u64 uart1_dmamask = DMA_BIT_MASK(32);
746
747static struct platform_device at572d940hf_uart1_device = {
748 .name = "atmel_usart",
749 .id = 2,
750 .dev = {
751 .dma_mask = &uart1_dmamask,
752 .coherent_dma_mask = DMA_BIT_MASK(32),
753 .platform_data = &uart1_data,
754 },
755 .resource = uart1_resources,
756 .num_resources = ARRAY_SIZE(uart1_resources),
757};
758
759static inline void configure_usart1_pins(unsigned pins)
760{
761 at91_set_A_periph(AT91_PIN_PC10, 1); /* TXD1 */
762 at91_set_A_periph(AT91_PIN_PC9 , 0); /* RXD1 */
763
764 if (pins & ATMEL_UART_RTS)
765 at91_set_A_periph(AT91_PIN_PC12, 0); /* RTS1 */
766 if (pins & ATMEL_UART_CTS)
767 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS1 */
768}
769
770static struct resource uart2_resources[] = {
771 [0] = {
772 .start = AT572D940HF_BASE_US2,
773 .end = AT572D940HF_BASE_US2 + SZ_16K - 1,
774 .flags = IORESOURCE_MEM,
775 },
776 [1] = {
777 .start = AT572D940HF_ID_US2,
778 .end = AT572D940HF_ID_US2,
779 .flags = IORESOURCE_IRQ,
780 },
781};
782
783static struct atmel_uart_data uart2_data = {
784 .use_dma_tx = 1,
785 .use_dma_rx = 1,
786};
787
788static u64 uart2_dmamask = DMA_BIT_MASK(32);
789
790static struct platform_device at572d940hf_uart2_device = {
791 .name = "atmel_usart",
792 .id = 3,
793 .dev = {
794 .dma_mask = &uart2_dmamask,
795 .coherent_dma_mask = DMA_BIT_MASK(32),
796 .platform_data = &uart2_data,
797 },
798 .resource = uart2_resources,
799 .num_resources = ARRAY_SIZE(uart2_resources),
800};
801
802static inline void configure_usart2_pins(unsigned pins)
803{
804 at91_set_A_periph(AT91_PIN_PC15, 1); /* TXD2 */
805 at91_set_A_periph(AT91_PIN_PC14, 0); /* RXD2 */
806
807 if (pins & ATMEL_UART_RTS)
808 at91_set_A_periph(AT91_PIN_PC17, 0); /* RTS2 */
809 if (pins & ATMEL_UART_CTS)
810 at91_set_A_periph(AT91_PIN_PC16, 0); /* CTS2 */
811}
812
813static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
814struct platform_device *atmel_default_console_device; /* the serial console device */
815
816void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
817{
818 struct platform_device *pdev;
819 struct atmel_uart_data *pdata;
820
821 switch (id) {
822 case 0: /* DBGU */
823 pdev = &at572d940hf_dbgu_device;
824 configure_dbgu_pins();
825 break;
826 case AT572D940HF_ID_US0:
827 pdev = &at572d940hf_uart0_device;
828 configure_usart0_pins(pins);
829 break;
830 case AT572D940HF_ID_US1:
831 pdev = &at572d940hf_uart1_device;
832 configure_usart1_pins(pins);
833 break;
834 case AT572D940HF_ID_US2:
835 pdev = &at572d940hf_uart2_device;
836 configure_usart2_pins(pins);
837 break;
838 default:
839 return;
840 }
841 pdata = pdev->dev.platform_data;
842 pdata->num = portnr; /* update to mapped ID */
843
844 if (portnr < ATMEL_MAX_UART)
845 at91_uarts[portnr] = pdev;
846}
847
848void __init at91_set_serial_console(unsigned portnr)
849{
850 if (portnr < ATMEL_MAX_UART) {
851 atmel_default_console_device = at91_uarts[portnr];
852 at572d940hf_set_console_clock(portnr);
853 }
854}
855
856void __init at91_add_device_serial(void)
857{
858 int i;
859
860 for (i = 0; i < ATMEL_MAX_UART; i++) {
861 if (at91_uarts[i])
862 platform_device_register(at91_uarts[i]);
863 }
864
865 if (!atmel_default_console_device)
866 printk(KERN_INFO "AT91: No default serial console defined.\n");
867}
868
869#else
870void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
871void __init at91_set_serial_console(unsigned portnr) {}
872void __init at91_add_device_serial(void) {}
873#endif
874
875
876/* --------------------------------------------------------------------
877 * mAgic
878 * -------------------------------------------------------------------- */
879
880#ifdef CONFIG_MAGICV
881static struct resource mAgic_resources[] = {
882 {
883 .start = AT91_MAGIC_PM_BASE,
884 .end = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
885 .flags = IORESOURCE_MEM,
886 },
887 {
888 .start = AT91_MAGIC_DM_I_BASE,
889 .end = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
890 .flags = IORESOURCE_MEM,
891 },
892 {
893 .start = AT91_MAGIC_DM_F_BASE,
894 .end = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
895 .flags = IORESOURCE_MEM,
896 },
897 {
898 .start = AT91_MAGIC_DM_DB_BASE,
899 .end = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
900 .flags = IORESOURCE_MEM,
901 },
902 {
903 .start = AT91_MAGIC_REGS_BASE,
904 .end = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
905 .flags = IORESOURCE_MEM,
906 },
907 {
908 .start = AT91_MAGIC_EXTPAGE_BASE,
909 .end = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
910 .flags = IORESOURCE_MEM,
911 },
912 {
913 .start = AT572D940HF_ID_MSIRQ0,
914 .end = AT572D940HF_ID_MSIRQ0,
915 .flags = IORESOURCE_IRQ,
916 },
917 {
918 .start = AT572D940HF_ID_MHALT,
919 .end = AT572D940HF_ID_MHALT,
920 .flags = IORESOURCE_IRQ,
921 },
922 {
923 .start = AT572D940HF_ID_MEXC,
924 .end = AT572D940HF_ID_MEXC,
925 .flags = IORESOURCE_IRQ,
926 },
927 {
928 .start = AT572D940HF_ID_MEDMA,
929 .end = AT572D940HF_ID_MEDMA,
930 .flags = IORESOURCE_IRQ,
931 },
932};
933
934static struct platform_device mAgic_device = {
935 .name = "mAgic",
936 .id = -1,
937 .num_resources = ARRAY_SIZE(mAgic_resources),
938 .resource = mAgic_resources,
939};
940
941void __init at91_add_device_mAgic(void)
942{
943 platform_device_register(&mAgic_device);
944}
945#else
946void __init at91_add_device_mAgic(void) {}
947#endif
948
949
950/* -------------------------------------------------------------------- */
951
952/*
953 * These devices are always present and don't need any board-specific
954 * setup.
955 */
956static int __init at91_add_standard_devices(void)
957{
958 at91_add_device_rtt();
959 at91_add_device_watchdog();
960 at91_add_device_tc();
961 return 0;
962}
963
964arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
deleted file mode 100644
index dfa896d7d5a9..000000000000
--- a/arch/arm/mach-at91/board-at572d940hf_ek.c
+++ /dev/null
@@ -1,323 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-at572d940hf_ek.c
3 *
4 * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2005 SAN People
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/ds1305.h>
29#include <linux/irq.h>
30#include <linux/mtd/physmap.h>
31
32#include <mach/hardware.h>
33#include <asm/setup.h>
34#include <asm/mach-types.h>
35#include <asm/irq.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/board.h>
42#include <mach/gpio.h>
43#include <mach/at91sam9_smc.h>
44#include <mach/system_rev.h>
45
46#include "sam9_smc.h"
47#include "generic.h"
48
49
50static void __init eb_init_early(void)
51{
52 /* Initialize processor: 12.500 MHz crystal */
53 at572d940hf_initialize(12000000);
54
55 /* DBGU on ttyS0. (Rx & Tx only) */
56 at91_register_uart(0, 0, 0);
57
58 /* USART0 on ttyS1. (Rx & Tx only) */
59 at91_register_uart(AT572D940HF_ID_US0, 1, 0);
60
61 /* USART1 on ttyS2. (Rx & Tx only) */
62 at91_register_uart(AT572D940HF_ID_US1, 2, 0);
63
64 /* USART2 on ttyS3. (Tx & Rx only */
65 at91_register_uart(AT572D940HF_ID_US2, 3, 0);
66
67 /* set serial console to ttyS0 (ie, DBGU) */
68 at91_set_serial_console(0);
69}
70
71static void __init eb_init_irq(void)
72{
73 at572d940hf_init_interrupts(NULL);
74}
75
76
77/*
78 * USB Host Port
79 */
80static struct at91_usbh_data __initdata eb_usbh_data = {
81 .ports = 2,
82};
83
84
85/*
86 * USB Device Port
87 */
88static struct at91_udc_data __initdata eb_udc_data = {
89 .vbus_pin = 0, /* no VBUS detection,UDC always on */
90 .pullup_pin = 0, /* pull-up driven by UDC */
91};
92
93
94/*
95 * MCI (SD/MMC)
96 */
97static struct at91_mmc_data __initdata eb_mmc_data = {
98 .wire4 = 1,
99/* .det_pin = ... not connected */
100/* .wp_pin = ... not connected */
101/* .vcc_pin = ... not connected */
102};
103
104
105/*
106 * MACB Ethernet device
107 */
108static struct at91_eth_data __initdata eb_eth_data = {
109 .phy_irq_pin = AT91_PIN_PB25,
110 .is_rmii = 1,
111};
112
113/*
114 * NOR flash
115 */
116
117static struct mtd_partition eb_nor_partitions[] = {
118 {
119 .name = "Raw Environment",
120 .offset = 0,
121 .size = SZ_4M,
122 .mask_flags = 0,
123 },
124 {
125 .name = "OS FS",
126 .offset = MTDPART_OFS_APPEND,
127 .size = 3 * SZ_1M,
128 .mask_flags = 0,
129 },
130 {
131 .name = "APP FS",
132 .offset = MTDPART_OFS_APPEND,
133 .size = MTDPART_SIZ_FULL,
134 .mask_flags = 0,
135 },
136};
137
138static void nor_flash_set_vpp(struct map_info* mi, int i) {
139};
140
141static struct physmap_flash_data nor_flash_data = {
142 .width = 4,
143 .parts = eb_nor_partitions,
144 .nr_parts = ARRAY_SIZE(eb_nor_partitions),
145 .set_vpp = nor_flash_set_vpp,
146};
147
148static struct resource nor_flash_resources[] = {
149 {
150 .start = AT91_CHIPSELECT_0,
151 .end = AT91_CHIPSELECT_0 + SZ_16M - 1,
152 .flags = IORESOURCE_MEM,
153 },
154};
155
156static struct platform_device nor_flash = {
157 .name = "physmap-flash",
158 .id = 0,
159 .dev = {
160 .platform_data = &nor_flash_data,
161 },
162 .resource = nor_flash_resources,
163 .num_resources = ARRAY_SIZE(nor_flash_resources),
164};
165
166static struct sam9_smc_config __initdata eb_nor_smc_config = {
167 .ncs_read_setup = 1,
168 .nrd_setup = 1,
169 .ncs_write_setup = 1,
170 .nwe_setup = 1,
171
172 .ncs_read_pulse = 7,
173 .nrd_pulse = 7,
174 .ncs_write_pulse = 7,
175 .nwe_pulse = 7,
176
177 .read_cycle = 9,
178 .write_cycle = 9,
179
180 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_32,
181 .tdf_cycles = 1,
182};
183
184static void __init eb_add_device_nor(void)
185{
186 /* configure chip-select 0 (NOR) */
187 sam9_smc_configure(0, &eb_nor_smc_config);
188 platform_device_register(&nor_flash);
189}
190
191/*
192 * NAND flash
193 */
194static struct mtd_partition __initdata eb_nand_partition[] = {
195 {
196 .name = "Partition 1",
197 .offset = 0,
198 .size = SZ_16M,
199 },
200 {
201 .name = "Partition 2",
202 .offset = MTDPART_OFS_NXTBLK,
203 .size = MTDPART_SIZ_FULL,
204 }
205};
206
207static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
208{
209 *num_partitions = ARRAY_SIZE(eb_nand_partition);
210 return eb_nand_partition;
211}
212
213static struct atmel_nand_data __initdata eb_nand_data = {
214 .ale = 22,
215 .cle = 21,
216/* .det_pin = ... not connected */
217/* .rdy_pin = AT91_PIN_PC16, */
218 .enable_pin = AT91_PIN_PA15,
219 .partition_info = nand_partitions,
220};
221
222static struct sam9_smc_config __initdata eb_nand_smc_config = {
223 .ncs_read_setup = 0,
224 .nrd_setup = 0,
225 .ncs_write_setup = 1,
226 .nwe_setup = 1,
227
228 .ncs_read_pulse = 3,
229 .nrd_pulse = 3,
230 .ncs_write_pulse = 3,
231 .nwe_pulse = 3,
232
233 .read_cycle = 5,
234 .write_cycle = 5,
235
236 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
237 .tdf_cycles = 12,
238};
239
240static void __init eb_add_device_nand(void)
241{
242 ek_nand_data.bus_width_16 = !board_have_nand_8bit();
243 /* setup bus-width (8 or 16) */
244 if (eb_nand_data.bus_width_16)
245 eb_nand_smc_config.mode |= AT91_SMC_DBW_16;
246 else
247 eb_nand_smc_config.mode |= AT91_SMC_DBW_8;
248
249 /* configure chip-select 3 (NAND) */
250 sam9_smc_configure(3, &eb_nand_smc_config);
251
252 at91_add_device_nand(&eb_nand_data);
253}
254
255
256/*
257 * SPI devices
258 */
259static struct resource rtc_resources[] = {
260 [0] = {
261 .start = AT572D940HF_ID_IRQ1,
262 .end = AT572D940HF_ID_IRQ1,
263 .flags = IORESOURCE_IRQ,
264 },
265};
266
267static struct ds1305_platform_data ds1306_data = {
268 .is_ds1306 = true,
269 .en_1hz = false,
270};
271
272static struct spi_board_info eb_spi_devices[] = {
273 { /* RTC Dallas DS1306 */
274 .modalias = "rtc-ds1305",
275 .chip_select = 3,
276 .mode = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA,
277 .max_speed_hz = 500000,
278 .bus_num = 0,
279 .irq = AT572D940HF_ID_IRQ1,
280 .platform_data = (void *) &ds1306_data,
281 },
282#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
283 { /* Dataflash card */
284 .modalias = "mtd_dataflash",
285 .chip_select = 0,
286 .max_speed_hz = 15 * 1000 * 1000,
287 .bus_num = 0,
288 },
289#endif
290};
291
292static void __init eb_board_init(void)
293{
294 /* Serial */
295 at91_add_device_serial();
296 /* USB Host */
297 at91_add_device_usbh(&eb_usbh_data);
298 /* USB Device */
299 at91_add_device_udc(&eb_udc_data);
300 /* I2C */
301 at91_add_device_i2c(NULL, 0);
302 /* NOR */
303 eb_add_device_nor();
304 /* NAND */
305 eb_add_device_nand();
306 /* SPI */
307 at91_add_device_spi(eb_spi_devices, ARRAY_SIZE(eb_spi_devices));
308 /* MMC */
309 at91_add_device_mmc(0, &eb_mmc_data);
310 /* Ethernet */
311 at91_add_device_eth(&eb_eth_data);
312 /* mAgic */
313 at91_add_device_mAgic();
314}
315
316MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB")
317 /* Maintainer: Atmel <costa.antonior@gmail.com> */
318 .timer = &at91sam926x_timer,
319 .map_io = at572d940hf_map_io,
320 .init_early = eb_init_early,
321 .init_irq = eb_init_irq,
322 .init_machine = eb_board_init,
323MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index ac103cbdbf35..61873f3aa92d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -599,7 +599,7 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
599 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); 599 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
600 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || 600 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
601 cpu_is_at91sam9263() || cpu_is_at91sam9g20() || 601 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
602 cpu_is_at91sam9g10() || cpu_is_at572d940hf()) { 602 cpu_is_at91sam9g10()) {
603 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 603 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
604 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 604 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
605 } else if (cpu_is_at91cap9()) { 605 } else if (cpu_is_at91cap9()) {
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 5783bd1b6c40..8ff3418f3430 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -19,7 +19,6 @@ extern void __init at91sam9rl_map_io(void);
19extern void __init at91sam9g45_map_io(void); 19extern void __init at91sam9g45_map_io(void);
20extern void __init at91x40_map_io(void); 20extern void __init at91x40_map_io(void);
21extern void __init at91cap9_map_io(void); 21extern void __init at91cap9_map_io(void);
22extern void __init at572d940hf_map_io(void);
23 22
24 /* Processors */ 23 /* Processors */
25extern void __init at91rm9200_set_type(int type); 24extern void __init at91rm9200_set_type(int type);
@@ -31,7 +30,6 @@ extern void __init at91sam9rl_initialize(unsigned long main_clock);
31extern void __init at91sam9g45_initialize(unsigned long main_clock); 30extern void __init at91sam9g45_initialize(unsigned long main_clock);
32extern void __init at91x40_initialize(unsigned long main_clock); 31extern void __init at91x40_initialize(unsigned long main_clock);
33extern void __init at91cap9_initialize(unsigned long main_clock); 32extern void __init at91cap9_initialize(unsigned long main_clock);
34extern void __init at572d940hf_initialize(unsigned long main_clock);
35 33
36 /* Interrupts */ 34 /* Interrupts */
37extern void __init at91rm9200_init_interrupts(unsigned int priority[]); 35extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
@@ -42,7 +40,6 @@ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
42extern void __init at91sam9g45_init_interrupts(unsigned int priority[]); 40extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
43extern void __init at91x40_init_interrupts(unsigned int priority[]); 41extern void __init at91x40_init_interrupts(unsigned int priority[]);
44extern void __init at91cap9_init_interrupts(unsigned int priority[]); 42extern void __init at91cap9_init_interrupts(unsigned int priority[]);
45extern void __init at572d940hf_init_interrupts(unsigned int priority[]);
46extern void __init at91_aic_init(unsigned int priority[]); 43extern void __init at91_aic_init(unsigned int priority[]);
47 44
48 /* Timer */ 45 /* Timer */
@@ -65,7 +62,6 @@ extern void __init at91sam9263_set_console_clock(int id);
65extern void __init at91sam9rl_set_console_clock(int id); 62extern void __init at91sam9rl_set_console_clock(int id);
66extern void __init at91sam9g45_set_console_clock(int id); 63extern void __init at91sam9g45_set_console_clock(int id);
67extern void __init at91cap9_set_console_clock(int id); 64extern void __init at91cap9_set_console_clock(int id);
68extern void __init at572d940hf_set_console_clock(int id);
69struct device; 65struct device;
70 66
71 /* Power Management */ 67 /* Power Management */
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
deleted file mode 100644
index a738dc7e5d44..000000000000
--- a/arch/arm/mach-at91/include/mach/at572d940hf.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * include/mach/at572d940hf.h
3 *
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#ifndef AT572D940HF_H
24#define AT572D940HF_H
25
26/*
27 * Peripheral identifiers/interrupts.
28 */
29#define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */
30#define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */
31#define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */
32#define AT572D940HF_ID_EMAC 5 /* MACB ethernet controller */
33#define AT572D940HF_ID_US0 6 /* USART 0 */
34#define AT572D940HF_ID_US1 7 /* USART 1 */
35#define AT572D940HF_ID_US2 8 /* USART 2 */
36#define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */
37#define AT572D940HF_ID_UDP 10 /* USB Device Port */
38#define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface 0 */
39#define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */
40#define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */
41#define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller 0 */
42#define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller 1 */
43#define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller 2 */
44#define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */
45#define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */
46#define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */
47#define AT572D940HF_ID_UHP 20 /* USB Host port */
48#define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller 3 */
49#define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface 1 */
50#define AT572D940HF_ID_CAN0 23 /* CAN Controller 0 */
51#define AT572D940HF_ID_CAN1 24 /* CAN Controller 1 */
52#define AT572D940HF_ID_MHALT 25 /* mAgicV HALT line */
53#define AT572D940HF_ID_MSIRQ0 26 /* mAgicV SIRQ0 line */
54#define AT572D940HF_ID_MEXC 27 /* mAgicV exception line */
55#define AT572D940HF_ID_MEDMA 28 /* mAgicV end of DMA line */
56#define AT572D940HF_ID_IRQ0 29 /* External Interrupt Source (IRQ0) */
57#define AT572D940HF_ID_IRQ1 30 /* External Interrupt Source (IRQ1) */
58#define AT572D940HF_ID_IRQ2 31 /* External Interrupt Source (IRQ2) */
59
60
61/*
62 * User Peripheral physical base addresses.
63 */
64#define AT572D940HF_BASE_TCB 0xfffa0000
65#define AT572D940HF_BASE_TC0 0xfffa0000
66#define AT572D940HF_BASE_TC1 0xfffa0040
67#define AT572D940HF_BASE_TC2 0xfffa0080
68#define AT572D940HF_BASE_UDP 0xfffa4000
69#define AT572D940HF_BASE_MCI 0xfffa8000
70#define AT572D940HF_BASE_TWI0 0xfffac000
71#define AT572D940HF_BASE_US0 0xfffb0000
72#define AT572D940HF_BASE_US1 0xfffb4000
73#define AT572D940HF_BASE_US2 0xfffb8000
74#define AT572D940HF_BASE_SSC0 0xfffbc000
75#define AT572D940HF_BASE_SSC1 0xfffc0000
76#define AT572D940HF_BASE_SSC2 0xfffc4000
77#define AT572D940HF_BASE_SPI0 0xfffc8000
78#define AT572D940HF_BASE_SPI1 0xfffcc000
79#define AT572D940HF_BASE_SSC3 0xfffd0000
80#define AT572D940HF_BASE_TWI1 0xfffd4000
81#define AT572D940HF_BASE_EMAC 0xfffd8000
82#define AT572D940HF_BASE_CAN0 0xfffdc000
83#define AT572D940HF_BASE_CAN1 0xfffe0000
84#define AT91_BASE_SYS 0xffffea00
85
86
87/*
88 * System Peripherals (offset from AT91_BASE_SYS)
89 */
90#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
91#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
92#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
93#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
94#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
95#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
96#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
97#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
98#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
99#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
100#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
101#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
102#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
103
104#define AT91_USART0 AT572D940HF_ID_US0
105#define AT91_USART1 AT572D940HF_ID_US1
106#define AT91_USART2 AT572D940HF_ID_US2
107
108
109/*
110 * Internal Memory.
111 */
112#define AT572D940HF_SRAM_BASE 0x00300000 /* Internal SRAM base address */
113#define AT572D940HF_SRAM_SIZE (48 * SZ_1K) /* Internal SRAM size (48Kb) */
114
115#define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */
116#define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
117
118#define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */
119
120
121#endif
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
deleted file mode 100644
index b6751df09488..000000000000
--- a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * include/mach//at572d940hf_matrix.h
3 *
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
6 *
7 * Copyright (C) 2005 SAN People
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef AT572D940HF_MATRIX_H
25#define AT572D940HF_MATRIX_H
26
27#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
28#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
29#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
30#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
31#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
32#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
33
34#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
35#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
36#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
37#define AT91_MATRIX_ULBT_FOUR (2 << 0)
38#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
39#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
40
41#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
42#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
43#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
44#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
45#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
46#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
47#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
48#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
49#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
50#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
51#define AT91_MATRIX_FIXED_DEFMSTR (0x7 << 18) /* Fixed Index of Default Master */
52#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
53#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
54#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
55
56#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
57#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
59#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
60#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
61
62#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
63#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
64#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
65#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
66#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
67#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
68#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
69
70#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
71#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
72#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
73
74#define AT91_MATRIX_SFR0 (AT91_MATRIX + 0x110) /* Special Function Register 0 */
75#define AT91_MATRIX_SFR1 (AT91_MATRIX + 0x114) /* Special Function Register 1 */
76#define AT91_MATRIX_SFR2 (AT91_MATRIX + 0x118) /* Special Function Register 2 */
77#define AT91_MATRIX_SFR3 (AT91_MATRIX + 0x11C) /* Special Function Register 3 */
78#define AT91_MATRIX_SFR4 (AT91_MATRIX + 0x120) /* Special Function Register 4 */
79#define AT91_MATRIX_SFR5 (AT91_MATRIX + 0x124) /* Special Function Register 5 */
80#define AT91_MATRIX_SFR6 (AT91_MATRIX + 0x128) /* Special Function Register 6 */
81#define AT91_MATRIX_SFR7 (AT91_MATRIX + 0x12C) /* Special Function Register 7 */
82#define AT91_MATRIX_SFR8 (AT91_MATRIX + 0x130) /* Special Function Register 8 */
83#define AT91_MATRIX_SFR9 (AT91_MATRIX + 0x134) /* Special Function Register 9 */
84#define AT91_MATRIX_SFR10 (AT91_MATRIX + 0x138) /* Special Function Register 10 */
85#define AT91_MATRIX_SFR11 (AT91_MATRIX + 0x13C) /* Special Function Register 11 */
86#define AT91_MATRIX_SFR12 (AT91_MATRIX + 0x140) /* Special Function Register 12 */
87#define AT91_MATRIX_SFR13 (AT91_MATRIX + 0x144) /* Special Function Register 13 */
88#define AT91_MATRIX_SFR14 (AT91_MATRIX + 0x148) /* Special Function Register 14 */
89#define AT91_MATRIX_SFR15 (AT91_MATRIX + 0x14C) /* Special Function Register 15 */
90
91
92/*
93 * The following registers / bits are not defined in the Datasheet (Revision A)
94 */
95
96#define AT91_MATRIX_TCR (AT91_MATRIX + 0x100) /* TCM Configuration Register */
97#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
98#define AT91_MATRIX_ITCM_0 (0 << 0)
99#define AT91_MATRIX_ITCM_16 (5 << 0)
100#define AT91_MATRIX_ITCM_32 (6 << 0)
101#define AT91_MATRIX_ITCM_64 (7 << 0)
102#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
103#define AT91_MATRIX_DTCM_0 (0 << 4)
104#define AT91_MATRIX_DTCM_16 (5 << 4)
105#define AT91_MATRIX_DTCM_32 (6 << 4)
106#define AT91_MATRIX_DTCM_64 (7 << 4)
107
108#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
109#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
110#define AT91_MATRIX_CS1A_SMC (0 << 1)
111#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
112#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
113#define AT91_MATRIX_CS3A_SMC (0 << 3)
114#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
115#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
116#define AT91_MATRIX_CS4A_SMC (0 << 4)
117#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
118#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
119#define AT91_MATRIX_CS5A_SMC (0 << 5)
120#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
121#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
122
123#endif
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index c44e94e22857..ed544a0d5a1d 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -90,7 +90,7 @@ struct at91_eth_data {
90extern void __init at91_add_device_eth(struct at91_eth_data *data); 90extern void __init at91_add_device_eth(struct at91_eth_data *data);
91 91
92#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \ 92#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
93 || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF) 93 || defined(CONFIG_ARCH_AT91SAM9G45)
94#define eth_platform_data at91_eth_data 94#define eth_platform_data at91_eth_data
95#endif 95#endif
96 96
@@ -204,9 +204,6 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
204extern void __init at91_gpio_leds(struct gpio_led *leds, int nr); 204extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
205extern void __init at91_pwm_leds(struct gpio_led *leds, int nr); 205extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
206 206
207 /* AT572D940HF DSP */
208extern void __init at91_add_device_mAgic(void);
209
210/* FIXME: this needs a better location, but gets stuff building again */ 207/* FIXME: this needs a better location, but gets stuff building again */
211extern int at91_suspend_entering_slow_clock(void); 208extern int at91_suspend_entering_slow_clock(void);
212 209
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index ab00372ca045..df966c2bc2d4 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -34,8 +34,6 @@
34#define ARCH_ID_AT91SAM9XE256 0x329a93a0 34#define ARCH_ID_AT91SAM9XE256 0x329a93a0
35#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 35#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
36 36
37#define ARCH_ID_AT572D940HF 0x0e0303e0
38
39#define ARCH_ID_AT91M40800 0x14080044 37#define ARCH_ID_AT91M40800 0x14080044
40#define ARCH_ID_AT91R40807 0x44080746 38#define ARCH_ID_AT91R40807 0x44080746
41#define ARCH_ID_AT91M40807 0x14080745 39#define ARCH_ID_AT91M40807 0x14080745
@@ -188,12 +186,6 @@ extern int rm9200_type;
188#define cpu_is_at91cap9_revC() (0) 186#define cpu_is_at91cap9_revC() (0)
189#endif 187#endif
190 188
191#ifdef CONFIG_ARCH_AT572D940HF
192#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
193#else
194#define cpu_is_at572d940hf() (0)
195#endif
196
197/* 189/*
198 * Since this is ARM, we will never run on any AVR32 CPU. But these 190 * Since this is ARM, we will never run on any AVR32 CPU. But these
199 * definitions may reduce clutter in common drivers. 191 * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 469d3af5a551..1008b9fb5074 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,8 +32,6 @@
32#include <mach/at91cap9.h> 32#include <mach/at91cap9.h>
33#elif defined(CONFIG_ARCH_AT91X40) 33#elif defined(CONFIG_ARCH_AT91X40)
34#include <mach/at91x40.h> 34#include <mach/at91x40.h>
35#elif defined(CONFIG_ARCH_AT572D940HF)
36#include <mach/at572d940hf.h>
37#else 35#else
38#error "Unsupported AT91 processor" 36#error "Unsupported AT91 processor"
39#endif 37#endif
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 05a6e8af80c4..31ac2d97f14c 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -82,11 +82,6 @@
82#define AT91X40_MASTER_CLOCK 40000000 82#define AT91X40_MASTER_CLOCK 40000000
83#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) 83#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK)
84 84
85#elif defined(CONFIG_ARCH_AT572D940HF)
86
87#define AT572D940HF_MASTER_CLOCK 80000000
88#define CLOCK_TICK_RATE (AT572D940HF_MASTER_CLOCK/16)
89
90#endif 85#endif
91 86
92#endif 87#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 13:54:43 -0500