mfd: wm5110: Expose DRE control registers

Certain use-cases require the DRE to be disabled so expose registers
necessary to control the DRE enables.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>

2 files changed, 6 insertions, 0 deletions

diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c
index 338cfbe6727b..abd6713de7b0 100644
--- a/drivers/mfd/wm5110-tables.c
+++ b/drivers/mfd/wm5110-tables.c
@@ -601,6 +601,7 @@ static const struct reg_default wm5110_reg_default[] = {
         { 0x0000043D, 0x0180 },    /* R1085  - DAC Digital Volume 6R */
         { 0x0000043E, 0x0080 },    /* R1086  - DAC Volume Limit 6R */
         { 0x0000043F, 0x0800 },    /* R1087  - Noise Gate Select 6R */
+        { 0x00000440, 0x8FFF },    /* R1088  - DRE Enable */
         { 0x00000450, 0x0000 },    /* R1104  - DAC AEC Control 1 */
         { 0x00000458, 0x0000 },    /* R1112  - Noise Gate Control */
         { 0x00000480, 0x0040 },    /* R1152  - Class W ANC Threshold 1 */
@@ -1631,6 +1632,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
         case ARIZONA_DAC_DIGITAL_VOLUME_6R:
         case ARIZONA_DAC_VOLUME_LIMIT_6R:
         case ARIZONA_NOISE_GATE_SELECT_6R:
+        case ARIZONA_DRE_ENABLE:
         case ARIZONA_DAC_AEC_CONTROL_1:
         case ARIZONA_NOISE_GATE_CONTROL:
         case ARIZONA_PDM_SPK1_CTRL_1:
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index 89878149a43f..22916c0f1ca4 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -3207,6 +3207,10 @@
 /*
  * R1088 (0x440) - DRE Enable
  */
+#define ARIZONA_DRE3R_ENA                        0x0020  /* DRE3R_ENA */
+#define ARIZONA_DRE3R_ENA_MASK                   0x0020  /* DRE3R_ENA */
+#define ARIZONA_DRE3R_ENA_SHIFT                       5  /* DRE3R_ENA */
+#define ARIZONA_DRE3R_ENA_WIDTH                       1  /* DRE3R_ENA */
 #define ARIZONA_DRE3L_ENA                        0x0010  /* DRE3L_ENA */
 #define ARIZONA_DRE3L_ENA_MASK                   0x0010  /* DRE3L_ENA */
 #define ARIZONA_DRE3L_ENA_SHIFT                       4  /* DRE3L_ENA */