drm/radeon: use WRITE_DATA packets for vm flush on SI

This is the preferred packet for writing data to memory
or registers on SI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 36 insertions, 7 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 156c9941e6ca..916d1cb274c0 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2797,21 +2797,35 @@ void si_vm_flush(struct radeon_device *rdev, struct radeon_ib *ib)
         if (vm == NULL)
                 return;
 
+        /* write new base address */
+        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+        radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+                                 WRITE_DATA_DST_SEL(0)));
+
         if (vm->id < 8) {
-                radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
-                                                + (vm->id << 2), 0));
+                radeon_ring_write(ring,
+                                  (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
         } else {
-                radeon_ring_write(ring, PACKET0(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR
-                                                + ((vm->id - 8) << 2), 0));
+                radeon_ring_write(ring,
+                                  (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
         }
+        radeon_ring_write(ring, 0);
         radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
 
         /* flush hdp cache */
-        radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
+        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+        radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+                                 WRITE_DATA_DST_SEL(0)));
+        radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
+        radeon_ring_write(ring, 0);
         radeon_ring_write(ring, 0x1);
 
-        /* bits 0-7 are the VM contexts0-7 */
-        radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
+        /* bits 0-15 are the VM contexts0-15 */
+        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+        radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+                                 WRITE_DATA_DST_SEL(0)));
+        radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
+        radeon_ring_write(ring, 0);
         radeon_ring_write(ring, 1 << ib->vm->id);
 }
 
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index ef4815c27b1c..7d2a20e56577 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -812,6 +812,21 @@
 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT                0x36
 #define PACKET3_WRITE_DATA                              0x37
+#define         WRITE_DATA_DST_SEL(x)                   ((x) << 8)
+                /* 0 - register
+                 * 1 - memory (sync - via GRBM)
+                 * 2 - tc/l2
+                 * 3 - gds
+                 * 4 - reserved
+                 * 5 - memory (async - direct)
+                 */
+#define         WR_ONE_ADDR                             (1 << 16)
+#define         WR_CONFIRM                              (1 << 20)
+#define         WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
+                /* 0 - me
+                 * 1 - pfp
+                 * 2 - ce
+                 */
 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI               0x38
 #define PACKET3_MEM_SEMAPHORE                           0x39
 #define PACKET3_MPEG_INDEX                              0x3A