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authorJon Loeliger <jdl@freescale.com>2008-01-25 17:36:47 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 09:45:37 -0500
commit762931571edcf4067bc8f0de929752eb424b039e (patch)
treeb58aa49dc8865107cd5b7227a204f1d73e525e4f
parent6e050d4e35659d26f4ca4c63d47e606d8aea763d (diff)
[POWERPC] Convert StorCenter DTS file to /dts-v1/ format.
Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/storcenter.dts73
1 files changed, 38 insertions, 35 deletions
diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts
index 6aa1d695e644..2204874ac5f3 100644
--- a/arch/powerpc/boot/dts/storcenter.dts
+++ b/arch/powerpc/boot/dts/storcenter.dts
@@ -11,6 +11,8 @@
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14/dts-v1/;
15
14/ { 16/ {
15 model = "StorCenter"; 17 model = "StorCenter";
16 compatible = "storcenter"; 18 compatible = "storcenter";
@@ -30,19 +32,19 @@
30 PowerPC,8241@0 { 32 PowerPC,8241@0 {
31 device_type = "cpu"; 33 device_type = "cpu";
32 reg = <0>; 34 reg = <0>;
33 clock-frequency = <d# 200000000>; /* Hz */ 35 clock-frequency = <200000000>;
34 timebase-frequency = <d# 25000000>; /* Hz */ 36 timebase-frequency = <25000000>;
35 bus-frequency = <0>; /* from bootwrapper */ 37 bus-frequency = <0>; /* from bootwrapper */
36 i-cache-line-size = <d# 32>; /* bytes */ 38 i-cache-line-size = <32>;
37 d-cache-line-size = <d# 32>; /* bytes */ 39 d-cache-line-size = <32>;
38 i-cache-size = <4000>; 40 i-cache-size = <16384>;
39 d-cache-size = <4000>; 41 d-cache-size = <16384>;
40 }; 42 };
41 }; 43 };
42 44
43 memory { 45 memory {
44 device_type = "memory"; 46 device_type = "memory";
45 reg = <00000000 04000000>; /* 64MB @ 0x0 */ 47 reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
46 }; 48 };
47 49
48 soc@fc000000 { 50 soc@fc000000 {
@@ -51,15 +53,15 @@
51 device_type = "soc"; 53 device_type = "soc";
52 compatible = "fsl,mpc8241", "mpc10x"; 54 compatible = "fsl,mpc8241", "mpc10x";
53 store-gathering = <0>; /* 0 == off, !0 == on */ 55 store-gathering = <0>; /* 0 == off, !0 == on */
54 ranges = <0 fc000000 100000>; 56 ranges = <0x0 0xfc000000 0x100000>;
55 reg = <fc000000 100000>; /* EUMB */ 57 reg = <0xfc000000 0x100000>; /* EUMB */
56 bus-frequency = <0>; /* fixed by loader */ 58 bus-frequency = <0>; /* fixed by loader */
57 59
58 i2c@3000 { 60 i2c@3000 {
59 #address-cells = <1>; 61 #address-cells = <1>;
60 #size-cells = <0>; 62 #size-cells = <0>;
61 compatible = "fsl-i2c"; 63 compatible = "fsl-i2c";
62 reg = <3000 100>; 64 reg = <0x3000 0x100>;
63 interrupts = <5 2>; 65 interrupts = <5 2>;
64 interrupt-parent = <&mpic>; 66 interrupt-parent = <&mpic>;
65 67
@@ -73,9 +75,9 @@
73 cell-index = <0>; 75 cell-index = <0>;
74 device_type = "serial"; 76 device_type = "serial";
75 compatible = "ns16550"; 77 compatible = "ns16550";
76 reg = <4500 20>; 78 reg = <0x4500 0x20>;
77 clock-frequency = <d# 97553800>; /* Hz */ 79 clock-frequency = <97553800>; /* Hz */
78 current-speed = <d# 115200>; 80 current-speed = <115200>;
79 interrupts = <9 2>; 81 interrupts = <9 2>;
80 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
81 }; 83 };
@@ -84,10 +86,10 @@
84 cell-index = <1>; 86 cell-index = <1>;
85 device_type = "serial"; 87 device_type = "serial";
86 compatible = "ns16550"; 88 compatible = "ns16550";
87 reg = <4600 20>; 89 reg = <0x4600 0x20>;
88 clock-frequency = <d# 97553800>; /* Hz */ 90 clock-frequency = <97553800>; /* Hz */
89 current-speed = <d# 9600>; 91 current-speed = <9600>;
90 interrupts = <a 2>; 92 interrupts = <10 2>;
91 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
92 }; 94 };
93 95
@@ -96,7 +98,7 @@
96 device_type = "open-pic"; 98 device_type = "open-pic";
97 compatible = "chrp,open-pic"; 99 compatible = "chrp,open-pic";
98 interrupt-controller; 100 interrupt-controller;
99 reg = <40000 40000>; 101 reg = <0x40000 0x40000>;
100 }; 102 };
101 103
102 }; 104 };
@@ -107,28 +109,29 @@
107 #interrupt-cells = <1>; 109 #interrupt-cells = <1>;
108 device_type = "pci"; 110 device_type = "pci";
109 compatible = "mpc10x-pci"; 111 compatible = "mpc10x-pci";
110 reg = <fe800000 1000>; 112 reg = <0xfe800000 0x1000>;
111 ranges = <01000000 0 0 fe000000 0 00c00000 113 ranges = <0x01000000 0x0 0x0 0xfe000000 0x0 0x00c00000
112 02000000 0 80000000 80000000 0 70000000>; 114 0x02000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
113 bus-range = <0 ff>; 115 bus-range = <0 0xff>;
114 clock-frequency = <d# 97553800>; /* Hz */ 116 clock-frequency = <97553800>;
115 interrupt-parent = <&mpic>; 117 interrupt-parent = <&mpic>;
116 interrupt-map-mask = <f800 0 0 7>; 118 interrupt-map-mask = <0xf800 0 0 7>;
117 interrupt-map = < 119 interrupt-map = <
118 /* IDSEL 13 - IDE */ 120 /* IDSEL 13 - IDE */
119 6800 0 0 1 &mpic 0 1 121 0x6800 0 0 1 &mpic 0 1
120 6800 0 0 2 &mpic 0 1 122 0x6800 0 0 2 &mpic 0 1
121 6800 0 0 3 &mpic 0 1 123 0x6800 0 0 3 &mpic 0 1
124 0x6800 0 0 4 &mpic 0 1
122 /* IDSEL 14 - USB */ 125 /* IDSEL 14 - USB */
123 7000 0 0 1 &mpic 0 1 126 0x7000 0 0 1 &mpic 0 1
124 7000 0 0 2 &mpic 0 1 127 0x7000 0 0 2 &mpic 0 1
125 7000 0 0 3 &mpic 0 1 128 0x7000 0 0 3 &mpic 0 1
126 7000 0 0 4 &mpic 0 1 129 0x7000 0 0 4 &mpic 0 1
127 /* IDSEL 15 - ETH */ 130 /* IDSEL 15 - ETH */
128 7800 0 0 1 &mpic 0 1 131 0x7800 0 0 1 &mpic 0 1
129 7800 0 0 2 &mpic 0 1 132 0x7800 0 0 2 &mpic 0 1
130 7800 0 0 3 &mpic 0 1 133 0x7800 0 0 3 &mpic 0 1
131 7800 0 0 4 &mpic 0 1 134 0x7800 0 0 4 &mpic 0 1
132 >; 135 >;
133 }; 136 };
134 137
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 08:09:31 -0500