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authorOlof Johansson <olof@lixom.net>2013-08-14 03:54:46 -0400
committerOlof Johansson <olof@lixom.net>2013-08-14 03:54:46 -0400
commit74f19946976edabe6432ac0005346b0611e2f8c1 (patch)
tree9c39cba7d0dd32f67f67f82f19e385d8bd34afed
parent13b837999f5cff1b0f40842704a18a2357dc22b2 (diff)
parentf79d68da510bf1b95beff4d556b78d06801f11dc (diff)
Merge tag 'renesas-boards-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards
From Simon Horman: Renesas ARM-based SoC board updates for v3.12 * ape6evm: Add SDHI and MMCIF support * lager: Add MMCIF support * armadillo800eva: Add DMA support for MMCIF * tag 'renesas-boards-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (54 commits) ARM: shmobile: ape6evm: add SDHI interfaces ARM: shmobile: ape6evm: add MMCIF support ARM: shmobile: select the fixed regulator driver on BockW ARM: shmobile: lager: add MMCIF support ARM: shmobile: armadillo800eva: add DMA support to MMCIF ARM: shmobile: Setup r8a7790 arch timer based on MD pins ARM: shmobile: Introduce r8a7790_read_mode_pins() ARM: shmobile: r8a7740: add MMCIF DMA definitions ARM: shmobile: Disconnect EMEV2 SMP code from clocks ARM: shmobile: Make r8a73a4 Arch timer optional ARM: shmobile: Add r8a73a4 CMT10 clock event ARM: shmobile: Make r8a7790 Arch timer optional ARM: shmobile: Add r8a7790 CMT00 clock event ARM: shmobile: Sort r8a7790 MSTP entries ARM: shmobile: r8a73a4: add clocks for I2C controllers ARM: shmobile: r8a73a4: add Z2 clock support ARM: shmobile: r8a73a4: safeguard against wrong clk_set_rate() uses ARM: shmobile: r8a73a4: implement CPU clock scaling for CPUFreq ARM: shmobile: r8a73a4: wait for completion when kicking the clock ARM: shmobile: r8a7790: add thermal driver support ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d-reference.dts57
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts2
-rw-r--r--arch/arm/boot/dts/emev2.dtsi59
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts22
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi126
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi54
-rw-r--r--arch/arm/mach-shmobile/Kconfig17
-rw-r--r--arch/arm/mach-shmobile/Makefile1
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot1
-rw-r--r--arch/arm/mach-shmobile/board-ape6evm.c82
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c11
-rw-r--r--arch/arm/mach-shmobile/board-kzm9d-reference.c46
-rw-r--r--arch/arm/mach-shmobile/board-kzm9d.c4
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g-reference.c2
-rw-r--r--arch/arm/mach-shmobile/board-lager.c34
-rw-r--r--arch/arm/mach-shmobile/clock-emev2.c20
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c199
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c23
-rw-r--r--arch/arm/mach-shmobile/include/mach/dma.h1
-rw-r--r--arch/arm/mach-shmobile/include/mach/emev2.h4
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a73a4.h1
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h2
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7778.h1
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7790.h4
-rw-r--r--arch/arm/mach-shmobile/setup-emev2.c376
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c32
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c26
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c72
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c7
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c111
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c7
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c34
-rw-r--r--arch/arm/mach-shmobile/smp-emev2.c26
34 files changed, 964 insertions, 501 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 641b3c9a7028..af19e38f8e97 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -183,6 +183,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
183 ccu9540.dtb 183 ccu9540.dtb
184dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 184dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
185dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 185dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
186 emev2-kzm9d-reference.dtb \
186 r8a7740-armadillo800eva.dtb \ 187 r8a7740-armadillo800eva.dtb \
187 r8a7778-bockw.dtb \ 188 r8a7778-bockw.dtb \
188 r8a7740-armadillo800eva-reference.dtb \ 189 r8a7740-armadillo800eva-reference.dtb \
diff --git a/arch/arm/boot/dts/emev2-kzm9d-reference.dts b/arch/arm/boot/dts/emev2-kzm9d-reference.dts
new file mode 100644
index 000000000000..bed676b95c27
--- /dev/null
+++ b/arch/arm/boot/dts/emev2-kzm9d-reference.dts
@@ -0,0 +1,57 @@
1/*
2 * Device Tree Source for the KZM9D board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10/dts-v1/;
11
12/include/ "emev2.dtsi"
13
14/ {
15 model = "EMEV2 KZM9D Board";
16 compatible = "renesas,kzm9d-reference", "renesas,emev2";
17
18 memory {
19 device_type = "memory";
20 reg = <0x40000000 0x8000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096";
25 };
26
27 reg_1p8v: regulator@0 {
28 compatible = "regulator-fixed";
29 regulator-name = "fixed-1.8V";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
32 regulator-always-on;
33 regulator-boot-on;
34 };
35
36 reg_3p3v: regulator@1 {
37 compatible = "regulator-fixed";
38 regulator-name = "fixed-3.3V";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 regulator-always-on;
42 regulator-boot-on;
43 };
44
45 lan9220@20000000 {
46 compatible = "smsc,lan9220", "smsc,lan9115";
47 reg = <0x20000000 0x10000>;
48 phy-mode = "mii";
49 interrupt-parent = <&gpio0>;
50 interrupts = <1 1>; /* active high */
51 reg-io-width = <4>;
52 smsc,irq-active-high;
53 smsc,irq-push-pull;
54 vddvario-supply = <&reg_1p8v>;
55 vdd33a-supply = <&reg_3p3v>;
56 };
57};
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index b9b3241f173b..dda13bc02f9f 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -21,6 +21,6 @@
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 bootargs = "console=tty0 console=ttyS1,115200n81 earlyprintk=serial8250-em.1,115200n81 mem=128M@0x40000000 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"; 24 bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096";
25 }; 25 };
26}; 26};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index c8a8c08b48dd..99ad2b2e8e14 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -14,6 +14,14 @@
14 compatible = "renesas,emev2"; 14 compatible = "renesas,emev2";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
23 };
24
17 cpus { 25 cpus {
18 #address-cells = <1>; 26 #address-cells = <1>;
19 #size-cells = <0>; 27 #size-cells = <0>;
@@ -67,4 +75,55 @@
67 reg = <0xe1050000 0x38>; 75 reg = <0xe1050000 0x38>;
68 interrupts = <0 11 0>; 76 interrupts = <0 11 0>;
69 }; 77 };
78
79 gpio0: gpio@e0050000 {
80 compatible = "renesas,em-gio";
81 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
82 interrupts = <0 67 0>, <0 68 0>;
83 gpio-controller;
84 #gpio-cells = <2>;
85 ngpios = <32>;
86 interrupt-controller;
87 #interrupt-cells = <2>;
88 };
89 gpio1: gpio@e0050080 {
90 compatible = "renesas,em-gio";
91 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
92 interrupts = <0 69 0>, <0 70 0>;
93 gpio-controller;
94 #gpio-cells = <2>;
95 ngpios = <32>;
96 interrupt-controller;
97 #interrupt-cells = <2>;
98 };
99 gpio2: gpio@e0050100 {
100 compatible = "renesas,em-gio";
101 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
102 interrupts = <0 71 0>, <0 72 0>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 ngpios = <32>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 };
109 gpio3: gpio@e0050180 {
110 compatible = "renesas,em-gio";
111 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
112 interrupts = <0 73 0>, <0 74 0>;
113 gpio-controller;
114 #gpio-cells = <2>;
115 ngpios = <32>;
116 interrupt-controller;
117 #interrupt-cells = <2>;
118 };
119 gpio4: gpio@e0050200 {
120 compatible = "renesas,em-gio";
121 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
122 interrupts = <0 75 0>, <0 76 0>;
123 gpio-controller;
124 #gpio-cells = <2>;
125 ngpios = <31>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
128 };
70}; 129};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index f603c6946c29..e657a9db1666 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -50,3 +50,25 @@
50 }; 50 };
51 }; 51 };
52}; 52};
53
54&i2c5 {
55 vdd_dvfs: max8973@1b {
56 compatible = "maxim,max8973";
57 reg = <0x1b>;
58
59 regulator-min-microvolt = <935000>;
60 regulator-max-microvolt = <1200000>;
61 regulator-boot-on;
62 regulator-always-on;
63 };
64};
65
66&cpu0 {
67 cpu0-supply = <&vdd_dvfs>;
68 operating-points = <
69 /* kHz uV */
70 1950000 1115000
71 1462500 995000
72 >;
73 voltage-tolerance = <1>; /* 1% */
74};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 4ff2019c0e30..6ce699be6095 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -85,4 +85,130 @@
85 interrupt-parent = <&gic>; 85 interrupt-parent = <&gic>;
86 interrupts = <0 69 4>; 86 interrupts = <0 69 4>;
87 }; 87 };
88
89 i2c0: i2c@e6500000 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "renesas,rmobile-iic";
93 reg = <0 0xe6500000 0 0x428>;
94 interrupt-parent = <&gic>;
95 interrupts = <0 174 0x4>;
96 };
97
98 i2c1: i2c@e6510000 {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 compatible = "renesas,rmobile-iic";
102 reg = <0 0xe6510000 0 0x428>;
103 interrupt-parent = <&gic>;
104 interrupts = <0 175 0x4>;
105 };
106
107 i2c2: i2c@e6520000 {
108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "renesas,rmobile-iic";
111 reg = <0 0xe6520000 0 0x428>;
112 interrupt-parent = <&gic>;
113 interrupts = <0 176 0x4>;
114 };
115
116 i2c3: i2c@e6530000 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 compatible = "renesas,rmobile-iic";
120 reg = <0 0xe6530000 0 0x428>;
121 interrupt-parent = <&gic>;
122 interrupts = <0 177 0x4>;
123 };
124
125 i2c4: i2c@e6540000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "renesas,rmobile-iic";
129 reg = <0 0xe6540000 0 0x428>;
130 interrupt-parent = <&gic>;
131 interrupts = <0 178 0x4>;
132 };
133
134 i2c5: i2c@e60b0000 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "renesas,rmobile-iic";
138 reg = <0 0xe60b0000 0 0x428>;
139 interrupt-parent = <&gic>;
140 interrupts = <0 179 0x4>;
141 };
142
143 i2c6: i2c@e6550000 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 compatible = "renesas,rmobile-iic";
147 reg = <0 0xe6550000 0 0x428>;
148 interrupt-parent = <&gic>;
149 interrupts = <0 184 0x4>;
150 };
151
152 i2c7: i2c@e6560000 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "renesas,rmobile-iic";
156 reg = <0 0xe6560000 0 0x428>;
157 interrupt-parent = <&gic>;
158 interrupts = <0 185 0x4>;
159 };
160
161 i2c8: i2c@e6570000 {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "renesas,rmobile-iic";
165 reg = <0 0xe6570000 0 0x428>;
166 interrupt-parent = <&gic>;
167 interrupts = <0 173 0x4>;
168 };
169
170 mmcif0: mmcif@ee200000 {
171 compatible = "renesas,sh-mmcif";
172 reg = <0 0xee200000 0 0x80>;
173 interrupt-parent = <&gic>;
174 interrupts = <0 169 0x4>;
175 reg-io-width = <4>;
176 status = "disabled";
177 };
178
179 mmcif1: mmcif@ee220000 {
180 compatible = "renesas,sh-mmcif";
181 reg = <0 0xee220000 0 0x80>;
182 interrupt-parent = <&gic>;
183 interrupts = <0 170 0x4>;
184 reg-io-width = <4>;
185 status = "disabled";
186 };
187
188 sdhi0: sdhi@ee100000 {
189 compatible = "renesas,r8a73a4-sdhi";
190 reg = <0 0xee100000 0 0x100>;
191 interrupt-parent = <&gic>;
192 interrupts = <0 165 4>;
193 cap-sd-highspeed;
194 status = "disabled";
195 };
196
197 sdhi1: sdhi@ee120000 {
198 compatible = "renesas,r8a73a4-sdhi";
199 reg = <0 0xee120000 0 0x100>;
200 interrupt-parent = <&gic>;
201 interrupts = <0 166 4>;
202 cap-sd-highspeed;
203 status = "disabled";
204 };
205
206 sdhi2: sdhi@ee140000 {
207 compatible = "renesas,r8a73a4-sdhi";
208 reg = <0 0xee140000 0 0x100>;
209 interrupt-parent = <&gic>;
210 interrupts = <0 167 4>;
211 cap-sd-highspeed;
212 status = "disabled";
213 };
88}; 214};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 339d9b11721c..9cd882028095 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -54,4 +54,58 @@
54 interrupt-parent = <&gic>; 54 interrupt-parent = <&gic>;
55 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; 55 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
56 }; 56 };
57
58 mmcif0: mmcif@ee200000 {
59 compatible = "renesas,sh-mmcif";
60 reg = <0 0xee200000 0 0x80>;
61 interrupt-parent = <&gic>;
62 interrupts = <0 169 0x4>;
63 reg-io-width = <4>;
64 status = "disabled";
65 };
66
67 mmcif1: mmcif@ee220000 {
68 compatible = "renesas,sh-mmcif";
69 reg = <0 0xee220000 0 0x80>;
70 interrupt-parent = <&gic>;
71 interrupts = <0 170 0x4>;
72 reg-io-width = <4>;
73 status = "disabled";
74 };
75
76 sdhi0: sdhi@ee100000 {
77 compatible = "renesas,r8a7790-sdhi";
78 reg = <0 0xee100000 0 0x100>;
79 interrupt-parent = <&gic>;
80 interrupts = <0 165 4>;
81 cap-sd-highspeed;
82 status = "disabled";
83 };
84
85 sdhi1: sdhi@ee120000 {
86 compatible = "renesas,r8a7790-sdhi";
87 reg = <0 0xee120000 0 0x100>;
88 interrupt-parent = <&gic>;
89 interrupts = <0 166 4>;
90 cap-sd-highspeed;
91 status = "disabled";
92 };
93
94 sdhi2: sdhi@ee140000 {
95 compatible = "renesas,r8a7790-sdhi";
96 reg = <0 0xee140000 0 0x100>;
97 interrupt-parent = <&gic>;
98 interrupts = <0 167 4>;
99 cap-sd-highspeed;
100 status = "disabled";
101 };
102
103 sdhi3: sdhi@ee160000 {
104 compatible = "renesas,r8a7790-sdhi";
105 reg = <0 0xee160000 0 0x100>;
106 interrupt-parent = <&gic>;
107 interrupts = <0 168 4>;
108 cap-sd-highspeed;
109 status = "disabled";
110 };
57}; 111};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 3912ce91fee4..f76fca6d9375 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,9 +23,10 @@ config ARCH_R8A73A4
23 select ARCH_WANT_OPTIONAL_GPIOLIB 23 select ARCH_WANT_OPTIONAL_GPIOLIB
24 select ARM_GIC 24 select ARM_GIC
25 select CPU_V7 25 select CPU_V7
26 select HAVE_ARM_ARCH_TIMER
27 select SH_CLK_CPG 26 select SH_CLK_CPG
28 select RENESAS_IRQC 27 select RENESAS_IRQC
28 select ARCH_HAS_CPUFREQ
29 select ARCH_HAS_OPP
29 30
30config ARCH_R8A7740 31config ARCH_R8A7740
31 bool "R-Mobile A1 (R8A77400)" 32 bool "R-Mobile A1 (R8A77400)"
@@ -59,7 +60,6 @@ config ARCH_R8A7790
59 select ARCH_WANT_OPTIONAL_GPIOLIB 60 select ARCH_WANT_OPTIONAL_GPIOLIB
60 select ARM_GIC 61 select ARM_GIC
61 select CPU_V7 62 select CPU_V7
62 select HAVE_ARM_ARCH_TIMER
63 select SH_CLK_CPG 63 select SH_CLK_CPG
64 select RENESAS_IRQC 64 select RENESAS_IRQC
65 65
@@ -124,6 +124,7 @@ config MACH_BOCKW
124 depends on ARCH_R8A7778 124 depends on ARCH_R8A7778
125 select ARCH_REQUIRE_GPIOLIB 125 select ARCH_REQUIRE_GPIOLIB
126 select RENESAS_INTC_IRQPIN 126 select RENESAS_INTC_IRQPIN
127 select REGULATOR_FIXED_VOLTAGE if REGULATOR
127 select USE_OF 128 select USE_OF
128 129
129config MACH_MARZEN 130config MACH_MARZEN
@@ -156,6 +157,18 @@ config MACH_KZM9D
156 select REGULATOR_FIXED_VOLTAGE if REGULATOR 157 select REGULATOR_FIXED_VOLTAGE if REGULATOR
157 select USE_OF 158 select USE_OF
158 159
160config MACH_KZM9D_REFERENCE
161 bool "KZM9D board - Reference Device Tree Implementation"
162 depends on ARCH_EMEV2
163 select REGULATOR_FIXED_VOLTAGE if REGULATOR
164 select USE_OF
165 ---help---
166 Use reference implementation of KZM9D board support
167 which makes a greater use of device tree at the expense
168 of not supporting a number of devices.
169
170 This is intended to aid developers
171
159config MACH_KZM9G 172config MACH_KZM9G
160 bool "KZM-A9-GT board" 173 bool "KZM-A9-GT board"
161 depends on ARCH_SH73A0 174 depends on ARCH_SH73A0
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 6165a517f580..e8d0a2c904a0 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_MACH_LAGER) += board-lager.o
46obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 46obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
47obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o 47obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o
48obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o 48obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
49obj-$(CONFIG_MACH_KZM9D_REFERENCE) += board-kzm9d-reference.o
49obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 50obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
50obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o 51obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
51 52
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 84c6868580f0..7785c52b5cfd 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -7,6 +7,7 @@ loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
7loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 7loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
8loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000 8loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000
9loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 9loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
10loadaddr-$(CONFIG_MACH_KZM9D_REFERENCE) += 0x40008000
10loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 11loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
11loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 12loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
12loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 13loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 5eb0caa6a7d0..ccf8b0429083 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -20,8 +20,11 @@
20 20
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irqchip.h>
24#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/mfd/tmio.h>
25#include <linux/mmc/host.h>
26#include <linux/mmc/sh_mmcif.h>
27#include <linux/mmc/sh_mobile_sdhi.h>
25#include <linux/pinctrl/machine.h> 28#include <linux/pinctrl/machine.h>
26#include <linux/platform_device.h> 29#include <linux/platform_device.h>
27#include <linux/regulator/fixed.h> 30#include <linux/regulator/fixed.h>
@@ -55,6 +58,53 @@ static const struct smsc911x_platform_config lan9220_data = {
55 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, 58 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
56}; 59};
57 60
61/*
62 * On APE6EVM power is supplied to MMCIF by a tps80032 regulator. For now we
63 * model a VDD supply to MMCIF, using a fixed 3.3V regulator. Also use the
64 * static power supply for SDHI0 and SDHI1, whereas SDHI0's VccQ is also
65 * supplied by the same tps80032 regulator and thus can also be adjusted
66 * dynamically.
67 */
68static struct regulator_consumer_supply fixed3v3_power_consumers[] =
69{
70 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
71 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
72 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
73};
74
75/* MMCIF */
76static struct sh_mmcif_plat_data mmcif0_pdata = {
77 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
78};
79
80static struct resource mmcif0_resources[] = {
81 DEFINE_RES_MEM_NAMED(0xee200000, 0x100, "MMCIF0"),
82 DEFINE_RES_IRQ(gic_spi(169)),
83};
84
85/* SDHI0 */
86static struct sh_mobile_sdhi_info sdhi0_pdata = {
87 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
88 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
89};
90
91static struct resource sdhi0_resources[] = {
92 DEFINE_RES_MEM_NAMED(0xee100000, 0x100, "SDHI0"),
93 DEFINE_RES_IRQ(gic_spi(165)),
94};
95
96/* SDHI1 */
97static struct sh_mobile_sdhi_info sdhi1_pdata = {
98 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
99 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
100 MMC_CAP_NEEDS_POLL,
101};
102
103static struct resource sdhi1_resources[] = {
104 DEFINE_RES_MEM_NAMED(0xee120000, 0x100, "SDHI1"),
105 DEFINE_RES_IRQ(gic_spi(166)),
106};
107
58static const struct pinctrl_map ape6evm_pinctrl_map[] = { 108static const struct pinctrl_map ape6evm_pinctrl_map[] = {
59 /* SCIFA0 console */ 109 /* SCIFA0 console */
60 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", 110 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4",
@@ -62,6 +112,23 @@ static const struct pinctrl_map ape6evm_pinctrl_map[] = {
62 /* SMSC */ 112 /* SMSC */
63 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4", 113 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4",
64 "irqc_irq40", "irqc"), 114 "irqc_irq40", "irqc"),
115 /* MMCIF0 */
116 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
117 "mmc0_data8", "mmc0"),
118 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
119 "mmc0_ctrl", "mmc0"),
120 /* SDHI0: uSD: no WP */
121 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
122 "sdhi0_data4", "sdhi0"),
123 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
124 "sdhi0_ctrl", "sdhi0"),
125 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
126 "sdhi0_cd", "sdhi0"),
127 /* SDHI1 */
128 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
129 "sdhi1_data4", "sdhi1"),
130 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
131 "sdhi1_ctrl", "sdhi1"),
65}; 132};
66 133
67static void __init ape6evm_add_standard_devices(void) 134static void __init ape6evm_add_standard_devices(void)
@@ -94,6 +161,17 @@ static void __init ape6evm_add_standard_devices(void)
94 platform_device_register_resndata(&platform_bus, "smsc911x", -1, 161 platform_device_register_resndata(&platform_bus, "smsc911x", -1,
95 lan9220_res, ARRAY_SIZE(lan9220_res), 162 lan9220_res, ARRAY_SIZE(lan9220_res),
96 &lan9220_data, sizeof(lan9220_data)); 163 &lan9220_data, sizeof(lan9220_data));
164 regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
165 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
166 platform_device_register_resndata(&platform_bus, "sh_mmcif", 0,
167 mmcif0_resources, ARRAY_SIZE(mmcif0_resources),
168 &mmcif0_pdata, sizeof(mmcif0_pdata));
169 platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 0,
170 sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
171 &sdhi0_pdata, sizeof(sdhi0_pdata));
172 platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 1,
173 sdhi1_resources, ARRAY_SIZE(sdhi1_resources),
174 &sdhi1_pdata, sizeof(sdhi1_pdata));
97} 175}
98 176
99static const char *ape6evm_boards_compat_dt[] __initdata = { 177static const char *ape6evm_boards_compat_dt[] __initdata = {
@@ -102,7 +180,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
102}; 180};
103 181
104DT_MACHINE_START(APE6EVM_DT, "ape6evm") 182DT_MACHINE_START(APE6EVM_DT, "ape6evm")
105 .init_irq = irqchip_init, 183 .init_early = r8a73a4_init_delay,
106 .init_time = shmobile_timer_init, 184 .init_time = shmobile_timer_init,
107 .init_machine = ape6evm_add_standard_devices, 185 .init_machine = ape6evm_add_standard_devices,
108 .dt_compat = ape6evm_boards_compat_dt, 186 .dt_compat = ape6evm_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 9457c763b797..2412fcae2c0d 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -724,15 +724,6 @@ static struct platform_device vcc_sdhi1 = {
724}; 724};
725 725
726/* SDHI0 */ 726/* SDHI0 */
727/*
728 * FIXME
729 *
730 * It use polling mode here, since
731 * CD (= Card Detect) pin is not connected to SDHI0_CD.
732 * We can use IRQ31 as card detect irq,
733 * but it needs chattering removal operation
734 */
735#define IRQ31 irq_pin(31)
736static struct sh_mobile_sdhi_info sdhi0_info = { 727static struct sh_mobile_sdhi_info sdhi0_info = {
737 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 728 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
738 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 729 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
@@ -833,6 +824,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
833 .caps = MMC_CAP_4_BIT_DATA | 824 .caps = MMC_CAP_4_BIT_DATA |
834 MMC_CAP_8_BIT_DATA | 825 MMC_CAP_8_BIT_DATA |
835 MMC_CAP_NONREMOVABLE, 826 MMC_CAP_NONREMOVABLE,
827 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
828 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
836}; 829};
837 830
838static struct resource sh_mmcif_resources[] = { 831static struct resource sh_mmcif_resources[] = {
diff --git a/arch/arm/mach-shmobile/board-kzm9d-reference.c b/arch/arm/mach-shmobile/board-kzm9d-reference.c
new file mode 100644
index 000000000000..a7b28b24ab38
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kzm9d-reference.c
@@ -0,0 +1,46 @@
1/*
2 * kzm9d board support - Reference DT implementation
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/of_platform.h>
23#include <mach/emev2.h>
24#include <mach/common.h>
25#include <asm/mach/arch.h>
26
27static void __init kzm9d_add_standard_devices(void)
28{
29 emev2_clock_init();
30
31 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
32}
33
34static const char *kzm9d_boards_compat_dt[] __initdata = {
35 "renesas,kzm9d-reference",
36 NULL,
37};
38
39DT_MACHINE_START(KZM9D_DT, "kzm9d")
40 .smp = smp_ops(emev2_smp_ops),
41 .map_io = emev2_map_io,
42 .init_early = emev2_init_delay,
43 .init_machine = kzm9d_add_standard_devices,
44 .init_late = shmobile_init_late,
45 .dt_compat = kzm9d_boards_compat_dt,
46MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index 4368000e1127..30c2cc695b12 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -85,9 +85,7 @@ static const char *kzm9d_boards_compat_dt[] __initdata = {
85DT_MACHINE_START(KZM9D_DT, "kzm9d") 85DT_MACHINE_START(KZM9D_DT, "kzm9d")
86 .smp = smp_ops(emev2_smp_ops), 86 .smp = smp_ops(emev2_smp_ops),
87 .map_io = emev2_map_io, 87 .map_io = emev2_map_io,
88 .init_early = emev2_add_early_devices, 88 .init_early = emev2_init_delay,
89 .nr_irqs = NR_IRQS_LEGACY,
90 .init_irq = emev2_init_irq,
91 .init_machine = kzm9d_add_standard_devices, 89 .init_machine = kzm9d_add_standard_devices,
92 .init_late = shmobile_init_late, 90 .init_late = shmobile_init_late,
93 .dt_compat = kzm9d_boards_compat_dt, 91 .dt_compat = kzm9d_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 44055fe8a45c..41092bb01ee5 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -24,7 +24,6 @@
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/irq.h> 26#include <linux/irq.h>
27#include <linux/irqchip.h>
28#include <linux/input.h> 27#include <linux/input.h>
29#include <linux/of_platform.h> 28#include <linux/of_platform.h>
30#include <linux/pinctrl/machine.h> 29#include <linux/pinctrl/machine.h>
@@ -99,7 +98,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
99 .map_io = sh73a0_map_io, 98 .map_io = sh73a0_map_io,
100 .init_early = sh73a0_init_delay, 99 .init_early = sh73a0_init_delay,
101 .nr_irqs = NR_IRQS_LEGACY, 100 .nr_irqs = NR_IRQS_LEGACY,
102 .init_irq = irqchip_init,
103 .init_machine = kzm_init, 101 .init_machine = kzm_init,
104 .init_time = shmobile_timer_init, 102 .init_time = shmobile_timer_init,
105 .dt_compat = kzm9g_boards_compat_dt, 103 .dt_compat = kzm9g_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index d73e21d3ea8a..3c67b2ad4494 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -22,13 +22,17 @@
22#include <linux/gpio_keys.h> 22#include <linux/gpio_keys.h>
23#include <linux/input.h> 23#include <linux/input.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/irqchip.h>
26#include <linux/kernel.h> 25#include <linux/kernel.h>
27#include <linux/leds.h> 26#include <linux/leds.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/sh_mmcif.h>
28#include <linux/pinctrl/machine.h> 29#include <linux/pinctrl/machine.h>
29#include <linux/platform_data/gpio-rcar.h> 30#include <linux/platform_data/gpio-rcar.h>
30#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/regulator/fixed.h>
33#include <linux/regulator/machine.h>
31#include <mach/common.h> 34#include <mach/common.h>
35#include <mach/irqs.h>
32#include <mach/r8a7790.h> 36#include <mach/r8a7790.h>
33#include <asm/mach-types.h> 37#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
@@ -71,6 +75,22 @@ static __initdata struct gpio_keys_platform_data lager_keys_pdata = {
71 .nbuttons = ARRAY_SIZE(gpio_buttons), 75 .nbuttons = ARRAY_SIZE(gpio_buttons),
72}; 76};
73 77
78/* Fixed 3.3V regulator to be used by MMCIF */
79static struct regulator_consumer_supply fixed3v3_power_consumers[] =
80{
81 REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"),
82};
83
84/* MMCIF */
85static struct sh_mmcif_plat_data mmcif1_pdata = {
86 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
87};
88
89static struct resource mmcif1_resources[] = {
90 DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"),
91 DEFINE_RES_IRQ(gic_spi(170)),
92};
93
74static const struct pinctrl_map lager_pinctrl_map[] = { 94static const struct pinctrl_map lager_pinctrl_map[] = {
75 /* SCIF0 (CN19: DEBUG SERIAL0) */ 95 /* SCIF0 (CN19: DEBUG SERIAL0) */
76 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", 96 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
@@ -78,6 +98,11 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
78 /* SCIF1 (CN20: DEBUG SERIAL1) */ 98 /* SCIF1 (CN20: DEBUG SERIAL1) */
79 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790", 99 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
80 "scif1_data", "scif1"), 100 "scif1_data", "scif1"),
101 /* MMCIF1 */
102 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
103 "mmc1_data8", "mmc1"),
104 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
105 "mmc1_ctrl", "mmc1"),
81}; 106};
82 107
83static void __init lager_add_standard_devices(void) 108static void __init lager_add_standard_devices(void)
@@ -95,6 +120,11 @@ static void __init lager_add_standard_devices(void)
95 platform_device_register_data(&platform_bus, "gpio-keys", -1, 120 platform_device_register_data(&platform_bus, "gpio-keys", -1,
96 &lager_keys_pdata, 121 &lager_keys_pdata,
97 sizeof(lager_keys_pdata)); 122 sizeof(lager_keys_pdata));
123 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
124 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
125 platform_device_register_resndata(&platform_bus, "sh_mmcif", 1,
126 mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
127 &mmcif1_pdata, sizeof(mmcif1_pdata));
98} 128}
99 129
100static const char *lager_boards_compat_dt[] __initdata = { 130static const char *lager_boards_compat_dt[] __initdata = {
@@ -103,7 +133,7 @@ static const char *lager_boards_compat_dt[] __initdata = {
103}; 133};
104 134
105DT_MACHINE_START(LAGER_DT, "lager") 135DT_MACHINE_START(LAGER_DT, "lager")
106 .init_irq = irqchip_init, 136 .init_early = r8a7790_init_delay,
107 .init_time = r8a7790_timer_init, 137 .init_time = r8a7790_timer_init,
108 .init_machine = lager_add_standard_devices, 138 .init_machine = lager_add_standard_devices,
109 .dt_compat = lager_boards_compat_dt, 139 .dt_compat = lager_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c
index 4710f1847bb7..5ac13ba71d54 100644
--- a/arch/arm/mach-shmobile/clock-emev2.c
+++ b/arch/arm/mach-shmobile/clock-emev2.c
@@ -40,7 +40,6 @@
40#define USIB2SCLKDIV 0x65c 40#define USIB2SCLKDIV 0x65c
41#define USIB3SCLKDIV 0x660 41#define USIB3SCLKDIV 0x660
42#define STI_CLKSEL 0x688 42#define STI_CLKSEL 0x688
43#define SMU_GENERAL_REG0 0x7c0
44 43
45/* not pretty, but hey */ 44/* not pretty, but hey */
46static void __iomem *smu_base; 45static void __iomem *smu_base;
@@ -51,11 +50,6 @@ static void emev2_smu_write(unsigned long value, int offs)
51 iowrite32(value, smu_base + offs); 50 iowrite32(value, smu_base + offs);
52} 51}
53 52
54void emev2_set_boot_vector(unsigned long value)
55{
56 emev2_smu_write(value, SMU_GENERAL_REG0);
57}
58
59static struct clk_mapping smu_mapping = { 53static struct clk_mapping smu_mapping = {
60 .phys = EMEV2_SMU_BASE, 54 .phys = EMEV2_SMU_BASE,
61 .len = PAGE_SIZE, 55 .len = PAGE_SIZE,
@@ -205,23 +199,11 @@ static struct clk_lookup lookups[] = {
205void __init emev2_clock_init(void) 199void __init emev2_clock_init(void)
206{ 200{
207 int k, ret = 0; 201 int k, ret = 0;
208 static int is_setup;
209
210 /* yuck, this is ugly as hell, but the non-smp case of clocks
211 * code is now designed to rely on ioremap() instead of static
212 * entity maps. in the case of smp we need access to the SMU
213 * register earlier than ioremap() is actually working without
214 * any static maps. to enable SMP in ugly but with dynamic
215 * mappings we have to call emev2_clock_init() from different
216 * places depending on UP and SMP...
217 */
218 if (is_setup++)
219 return;
220 202
221 smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); 203 smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
222 BUG_ON(!smu_base); 204 BUG_ON(!smu_base);
223 205
224 /* setup STI timer to run on 37.768 kHz and deassert reset */ 206 /* setup STI timer to run on 32.768 kHz and deassert reset */
225 emev2_smu_write(0, STI_CLKSEL); 207 emev2_smu_write(0, STI_CLKSEL);
226 emev2_smu_write(1, STI_RSTCTRL); 208 emev2_smu_write(1, STI_RSTCTRL);
227 209
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 5f7fe628b8a1..8ea5ef6c79cc 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -30,10 +30,12 @@
30 30
31#define SMSTPCR2 0xe6150138 31#define SMSTPCR2 0xe6150138
32#define SMSTPCR3 0xe615013c 32#define SMSTPCR3 0xe615013c
33#define SMSTPCR4 0xe6150140
33#define SMSTPCR5 0xe6150144 34#define SMSTPCR5 0xe6150144
34 35
35#define FRQCRA 0xE6150000 36#define FRQCRA 0xE6150000
36#define FRQCRB 0xE6150004 37#define FRQCRB 0xE6150004
38#define FRQCRC 0xE61500E0
37#define VCLKCR1 0xE6150008 39#define VCLKCR1 0xE6150008
38#define VCLKCR2 0xE615000C 40#define VCLKCR2 0xE615000C
39#define VCLKCR3 0xE615001C 41#define VCLKCR3 0xE615001C
@@ -52,6 +54,7 @@
52#define HSICKCR 0xE615026C 54#define HSICKCR 0xE615026C
53#define M4CKCR 0xE6150098 55#define M4CKCR 0xE6150098
54#define PLLECR 0xE61500D0 56#define PLLECR 0xE61500D0
57#define PLL0CR 0xE61500D8
55#define PLL1CR 0xE6150028 58#define PLL1CR 0xE6150028
56#define PLL2CR 0xE615002C 59#define PLL2CR 0xE615002C
57#define PLL2SCR 0xE61501F4 60#define PLL2SCR 0xE61501F4
@@ -177,6 +180,7 @@ static struct sh_clk_ops pll_clk_ops = {
177 .mapping = &cpg_mapping, \ 180 .mapping = &cpg_mapping, \
178 } 181 }
179 182
183PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0);
180PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); 184PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
181PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); 185PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2);
182PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); 186PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
@@ -184,6 +188,157 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
184 188
185SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); 189SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
186 190
191static atomic_t frqcr_lock;
192
193/* Several clocks need to access FRQCRB, have to lock */
194static bool frqcr_kick_check(struct clk *clk)
195{
196 return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
197}
198
199static int frqcr_kick_do(struct clk *clk)
200{
201 int i;
202
203 /* set KICK bit in FRQCRB to update hardware setting, check success */
204 iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
205 for (i = 1000; i; i--)
206 if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
207 cpu_relax();
208 else
209 return 0;
210
211 return -ETIMEDOUT;
212}
213
214static int zclk_set_rate(struct clk *clk, unsigned long rate)
215{
216 void __iomem *frqcrc;
217 int ret;
218 unsigned long step, p_rate;
219 u32 val;
220
221 if (!clk->parent || !__clk_get(clk->parent))
222 return -ENODEV;
223
224 if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
225 ret = -EBUSY;
226 goto done;
227 }
228
229 /*
230 * Users are supposed to first call clk_set_rate() only with
231 * clk_round_rate() results. So, we don't fix wrong rates here, but
232 * guard against them anyway
233 */
234
235 p_rate = clk_get_rate(clk->parent);
236 if (rate == p_rate) {
237 val = 0;
238 } else {
239 step = DIV_ROUND_CLOSEST(p_rate, 32);
240
241 if (rate > p_rate || rate < step) {
242 ret = -EINVAL;
243 goto done;
244 }
245
246 val = 32 - rate / step;
247 }
248
249 frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
250
251 iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
252 (val << clk->enable_bit), frqcrc);
253
254 ret = frqcr_kick_do(clk);
255
256done:
257 atomic_dec(&frqcr_lock);
258 __clk_put(clk->parent);
259 return ret;
260}
261
262static long zclk_round_rate(struct clk *clk, unsigned long rate)
263{
264 /*
265 * theoretical rate = parent rate * multiplier / 32,
266 * where 1 <= multiplier <= 32. Therefore we should do
267 * multiplier = rate * 32 / parent rate
268 * rounded rate = parent rate * multiplier / 32.
269 * However, multiplication before division won't fit in 32 bits, so
270 * we sacrifice some precision by first dividing and then multiplying.
271 * To find the nearest divisor we calculate both and pick up the best
272 * one. This avoids 64-bit arithmetics.
273 */
274 unsigned long step, mul_min, mul_max, rate_min, rate_max;
275
276 rate_max = clk_get_rate(clk->parent);
277
278 /* output freq <= parent */
279 if (rate >= rate_max)
280 return rate_max;
281
282 step = DIV_ROUND_CLOSEST(rate_max, 32);
283 /* output freq >= parent / 32 */
284 if (step >= rate)
285 return step;
286
287 mul_min = rate / step;
288 mul_max = DIV_ROUND_UP(rate, step);
289 rate_min = step * mul_min;
290 if (mul_max == mul_min)
291 return rate_min;
292
293 rate_max = step * mul_max;
294
295 if (rate_max - rate < rate - rate_min)
296 return rate_max;
297
298 return rate_min;
299}
300
301static unsigned long zclk_recalc(struct clk *clk)
302{
303 void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
304 unsigned int max = clk->div_mask + 1;
305 unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
306 clk->div_mask);
307
308 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
309 (max - val);
310}
311
312static struct sh_clk_ops zclk_ops = {
313 .recalc = zclk_recalc,
314 .set_rate = zclk_set_rate,
315 .round_rate = zclk_round_rate,
316};
317
318static struct clk z_clk = {
319 .parent = &pll0_clk,
320 .div_mask = 0x1f,
321 .enable_bit = 8,
322 /* We'll need to access FRQCRB and FRQCRC */
323 .enable_reg = (void __iomem *)FRQCRB,
324 .ops = &zclk_ops,
325};
326
327/*
328 * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
329 * switching is only available in auto-DVFS mode
330 */
331SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
332
333static struct clk z2_clk = {
334 .parent = &pll0_div2_clk,
335 .div_mask = 0x1f,
336 .enable_bit = 0,
337 /* We'll need to access FRQCRB and FRQCRC */
338 .enable_reg = (void __iomem *)FRQCRB,
339 .ops = &zclk_ops,
340};
341
187static struct clk *main_clks[] = { 342static struct clk *main_clks[] = {
188 &extalr_clk, 343 &extalr_clk,
189 &extal1_clk, 344 &extal1_clk,
@@ -195,22 +350,23 @@ static struct clk *main_clks[] = {
195 &main_div2_clk, 350 &main_div2_clk,
196 &fsiack_clk, 351 &fsiack_clk,
197 &fsibck_clk, 352 &fsibck_clk,
353 &pll0_clk,
198 &pll1_clk, 354 &pll1_clk,
199 &pll1_div2_clk, 355 &pll1_div2_clk,
200 &pll2_clk, 356 &pll2_clk,
201 &pll2s_clk, 357 &pll2s_clk,
202 &pll2h_clk, 358 &pll2h_clk,
359 &z_clk,
360 &pll0_div2_clk,
361 &z2_clk,
203}; 362};
204 363
205/* DIV4 */ 364/* DIV4 */
206static void div4_kick(struct clk *clk) 365static void div4_kick(struct clk *clk)
207{ 366{
208 unsigned long value; 367 if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
209 368 frqcr_kick_do(clk);
210 /* set KICK bit in FRQCRB to update hardware setting */ 369 atomic_dec(&frqcr_lock);
211 value = ioread32(CPG_MAP(FRQCRB));
212 value |= (1 << 31);
213 iowrite32(value, CPG_MAP(FRQCRB));
214} 370}
215 371
216static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; 372static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
@@ -349,8 +505,10 @@ static struct clk div6_clks[DIV6_NR] = {
349/* MSTP */ 505/* MSTP */
350enum { 506enum {
351 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, 507 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
352 MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, 508 MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
353 MSTP522, 509 MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
510 MSTP411, MSTP410, MSTP409,
511 MSTP522, MSTP515,
354 MSTP_NR 512 MSTP_NR
355}; 513};
356 514
@@ -361,12 +519,22 @@ static struct clk mstp_clks[MSTP_NR] = {
361 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ 519 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
362 [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ 520 [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
363 [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ 521 [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
522 [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
364 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ 523 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
365 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ 524 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
366 [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ 525 [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
367 [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ 526 [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
368 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ 527 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
528 [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0), /* IIC6 */
529 [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */
530 [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */
531 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
532 [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
533 [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */
534 [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
535 [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
369 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ 536 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
537 [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0), /* IIC8 */
370}; 538};
371 539
372static struct clk_lookup lookups[] = { 540static struct clk_lookup lookups[] = {
@@ -386,6 +554,9 @@ static struct clk_lookup lookups[] = {
386 CLKDEV_CON_ID("pll2s", &pll2s_clk), 554 CLKDEV_CON_ID("pll2s", &pll2s_clk),
387 CLKDEV_CON_ID("pll2h", &pll2h_clk), 555 CLKDEV_CON_ID("pll2h", &pll2h_clk),
388 556
557 /* CPU clock */
558 CLKDEV_DEV_ID("cpufreq-cpu0", &z_clk),
559
389 /* DIV6 */ 560 /* DIV6 */
390 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), 561 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
391 CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), 562 CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]),
@@ -408,6 +579,7 @@ static struct clk_lookup lookups[] = {
408 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), 579 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
409 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), 580 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
410 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 581 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
582 CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
411 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), 583 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
412 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), 584 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
413 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), 585 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
@@ -418,6 +590,15 @@ static struct clk_lookup lookups[] = {
418 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), 590 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
419 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 591 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
420 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), 592 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
593 CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
594 CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
595 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
596 CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
597 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
598 CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
599 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
600 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
601 CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
421 602
422 /* for DT */ 603 /* for DT */
423 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), 604 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
@@ -429,6 +610,8 @@ void __init r8a73a4_clock_init(void)
429 int k, ret = 0; 610 int k, ret = 0;
430 u32 ckscr; 611 u32 ckscr;
431 612
613 atomic_set(&frqcr_lock, -1);
614
432 reg = ioremap_nocache(CKSCR, PAGE_SIZE); 615 reg = ioremap_nocache(CKSCR, PAGE_SIZE);
433 BUG_ON(!reg); 616 BUG_ON(!reg);
434 ckscr = ioread32(reg); 617 ckscr = ioread32(reg);
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 5d71313df52d..50d96f9cf981 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -24,6 +24,7 @@
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <mach/clock.h> 25#include <mach/clock.h>
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/r8a7790.h>
27 28
28/* 29/*
29 * MD EXTAL PLL0 PLL1 PLL3 30 * MD EXTAL PLL0 PLL1 PLL3
@@ -42,16 +43,15 @@
42 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below 43 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
43 */ 44 */
44 45
45#define MD(nr) (1 << nr)
46
47#define CPG_BASE 0xe6150000 46#define CPG_BASE 0xe6150000
48#define CPG_LEN 0x1000 47#define CPG_LEN 0x1000
49 48
49#define SMSTPCR1 0xe6150134
50#define SMSTPCR2 0xe6150138 50#define SMSTPCR2 0xe6150138
51#define SMSTPCR3 0xe615013c 51#define SMSTPCR3 0xe615013c
52#define SMSTPCR5 0xe6150144
52#define SMSTPCR7 0xe615014c 53#define SMSTPCR7 0xe615014c
53 54
54#define MODEMR 0xE6160060
55#define SDCKCR 0xE6150074 55#define SDCKCR 0xE6150074
56#define SD2CKCR 0xE6150078 56#define SD2CKCR 0xE6150078
57#define SD3CKCR 0xE615007C 57#define SD3CKCR 0xE615007C
@@ -182,14 +182,19 @@ static struct clk div6_clks[DIV6_NR] = {
182enum { 182enum {
183 MSTP721, MSTP720, 183 MSTP721, MSTP720,
184 MSTP717, MSTP716, 184 MSTP717, MSTP716,
185 MSTP522,
185 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, 186 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
186 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, 187 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
188 MSTP124,
187 MSTP_NR 189 MSTP_NR
188}; 190};
189 191
190static struct clk mstp_clks[MSTP_NR] = { 192static struct clk mstp_clks[MSTP_NR] = {
191 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 193 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
192 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 194 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
195 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
196 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
197 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
193 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ 198 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
194 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ 199 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
195 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */ 200 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
@@ -203,8 +208,7 @@ static struct clk mstp_clks[MSTP_NR] = {
203 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ 208 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
204 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ 209 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
205 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ 210 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
206 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ 211 [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
207 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
208}; 212};
209 213
210static struct clk_lookup lookups[] = { 214static struct clk_lookup lookups[] = {
@@ -254,6 +258,7 @@ static struct clk_lookup lookups[] = {
254 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), 258 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
255 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), 259 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
256 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), 260 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
261 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
257 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), 262 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
258 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 263 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
259 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), 264 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
@@ -266,6 +271,7 @@ static struct clk_lookup lookups[] = {
266 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), 271 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
267 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), 272 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
268 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), 273 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
274 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
269}; 275};
270 276
271#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 277#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
@@ -280,14 +286,9 @@ static struct clk_lookup lookups[] = {
280 286
281void __init r8a7790_clock_init(void) 287void __init r8a7790_clock_init(void)
282{ 288{
283 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); 289 u32 mode = r8a7790_read_mode_pins();
284 u32 mode;
285 int k, ret = 0; 290 int k, ret = 0;
286 291
287 BUG_ON(!modemr);
288 mode = ioread32(modemr);
289 iounmap(modemr);
290
291 switch (mode & (MD(14) | MD(13))) { 292 switch (mode & (MD(14) | MD(13))) {
292 case 0: 293 case 0:
293 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); 294 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
diff --git a/arch/arm/mach-shmobile/include/mach/dma.h b/arch/arm/mach-shmobile/include/mach/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-shmobile/include/mach/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1/* empty */
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index ac3751705cab..c2eb7568d9be 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -2,11 +2,9 @@
2#define __ASM_EMEV2_H__ 2#define __ASM_EMEV2_H__
3 3
4extern void emev2_map_io(void); 4extern void emev2_map_io(void);
5extern void emev2_init_irq(void); 5extern void emev2_init_delay(void);
6extern void emev2_add_early_devices(void);
7extern void emev2_add_standard_devices(void); 6extern void emev2_add_standard_devices(void);
8extern void emev2_clock_init(void); 7extern void emev2_clock_init(void);
9extern void emev2_set_boot_vector(unsigned long value);
10 8
11#define EMEV2_GPIO_BASE 200 9#define EMEV2_GPIO_BASE 200
12#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n)) 10#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f043103e32c9..144a85e29245 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -4,5 +4,6 @@
4void r8a73a4_add_standard_devices(void); 4void r8a73a4_add_standard_devices(void);
5void r8a73a4_clock_init(void); 5void r8a73a4_clock_init(void);
6void r8a73a4_pinmux_init(void); 6void r8a73a4_pinmux_init(void);
7void r8a73a4_init_delay(void);
7 8
8#endif /* __ASM_R8A73A4_H__ */ 9#endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index b34d19b5ca5c..56f375005fcd 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -42,6 +42,8 @@ enum {
42 SHDMA_SLAVE_FSIB_TX, 42 SHDMA_SLAVE_FSIB_TX,
43 SHDMA_SLAVE_USBHS_TX, 43 SHDMA_SLAVE_USBHS_TX,
44 SHDMA_SLAVE_USBHS_RX, 44 SHDMA_SLAVE_USBHS_RX,
45 SHDMA_SLAVE_MMCIF_TX,
46 SHDMA_SLAVE_MMCIF_RX,
45}; 47};
46 48
47extern void r8a7740_meram_workaround(void); 49extern void r8a7740_meram_workaround(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 851d027a2f06..9b561bf4229f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -33,7 +33,6 @@ extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info);
33 33
34extern void r8a7778_init_late(void); 34extern void r8a7778_init_late(void);
35extern void r8a7778_init_delay(void); 35extern void r8a7778_init_delay(void);
36extern void r8a7778_init_irq(void);
37extern void r8a7778_init_irq_dt(void); 36extern void r8a7778_init_irq_dt(void);
38extern void r8a7778_clock_init(void); 37extern void r8a7778_clock_init(void);
39extern void r8a7778_init_irq_extpin(int irlm); 38extern void r8a7778_init_irq_extpin(int irlm);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 2e919e61fa0d..7aaef409a059 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -4,6 +4,10 @@
4void r8a7790_add_standard_devices(void); 4void r8a7790_add_standard_devices(void);
5void r8a7790_clock_init(void); 5void r8a7790_clock_init(void);
6void r8a7790_pinmux_init(void); 6void r8a7790_pinmux_init(void);
7void r8a7790_init_delay(void);
7void r8a7790_timer_init(void); 8void r8a7790_timer_init(void);
8 9
10#define MD(nr) BIT(nr)
11u32 r8a7790_read_mode_pins(void);
12
9#endif /* __ASM_R8A7790_H__ */ 13#endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 1ccddd228112..19980be7d6a9 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -20,7 +20,6 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/irqchip.h>
24#include <linux/platform_device.h> 23#include <linux/platform_device.h>
25#include <linux/platform_data/gpio-em.h> 24#include <linux/platform_data/gpio-em.h>
26#include <linux/of_platform.h> 25#include <linux/of_platform.h>
@@ -39,13 +38,6 @@
39 38
40static struct map_desc emev2_io_desc[] __initdata = { 39static struct map_desc emev2_io_desc[] __initdata = {
41#ifdef CONFIG_SMP 40#ifdef CONFIG_SMP
42 /* 128K entity map for 0xe0100000 (SMU) */
43 {
44 .virtual = 0xe0100000,
45 .pfn = __phys_to_pfn(0xe0100000),
46 .length = SZ_128K,
47 .type = MT_DEVICE
48 },
49 /* 2M mapping for SCU + L2 controller */ 41 /* 2M mapping for SCU + L2 controller */
50 { 42 {
51 .virtual = 0xf0000000, 43 .virtual = 0xf0000000,
@@ -63,102 +55,40 @@ void __init emev2_map_io(void)
63 55
64/* UART */ 56/* UART */
65static struct resource uart0_resources[] = { 57static struct resource uart0_resources[] = {
66 [0] = { 58 DEFINE_RES_MEM(0xe1020000, 0x38),
67 .start = 0xe1020000, 59 DEFINE_RES_IRQ(40),
68 .end = 0xe1020037,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = 40,
73 .flags = IORESOURCE_IRQ,
74 }
75};
76
77static struct platform_device uart0_device = {
78 .name = "serial8250-em",
79 .id = 0,
80 .num_resources = ARRAY_SIZE(uart0_resources),
81 .resource = uart0_resources,
82}; 60};
83 61
84static struct resource uart1_resources[] = { 62static struct resource uart1_resources[] = {
85 [0] = { 63 DEFINE_RES_MEM(0xe1030000, 0x38),
86 .start = 0xe1030000, 64 DEFINE_RES_IRQ(41),
87 .end = 0xe1030037,
88 .flags = IORESOURCE_MEM,
89 },
90 [1] = {
91 .start = 41,
92 .flags = IORESOURCE_IRQ,
93 }
94};
95
96static struct platform_device uart1_device = {
97 .name = "serial8250-em",
98 .id = 1,
99 .num_resources = ARRAY_SIZE(uart1_resources),
100 .resource = uart1_resources,
101}; 65};
102 66
103static struct resource uart2_resources[] = { 67static struct resource uart2_resources[] = {
104 [0] = { 68 DEFINE_RES_MEM(0xe1040000, 0x38),
105 .start = 0xe1040000, 69 DEFINE_RES_IRQ(42),
106 .end = 0xe1040037,
107 .flags = IORESOURCE_MEM,
108 },
109 [1] = {
110 .start = 42,
111 .flags = IORESOURCE_IRQ,
112 }
113};
114
115static struct platform_device uart2_device = {
116 .name = "serial8250-em",
117 .id = 2,
118 .num_resources = ARRAY_SIZE(uart2_resources),
119 .resource = uart2_resources,
120}; 70};
121 71
122static struct resource uart3_resources[] = { 72static struct resource uart3_resources[] = {
123 [0] = { 73 DEFINE_RES_MEM(0xe1050000, 0x38),
124 .start = 0xe1050000, 74 DEFINE_RES_IRQ(43),
125 .end = 0xe1050037,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = 43,
130 .flags = IORESOURCE_IRQ,
131 }
132}; 75};
133 76
134static struct platform_device uart3_device = { 77#define emev2_register_uart(idx) \
135 .name = "serial8250-em", 78 platform_device_register_simple("serial8250-em", idx, \
136 .id = 3, 79 uart##idx##_resources, \
137 .num_resources = ARRAY_SIZE(uart3_resources), 80 ARRAY_SIZE(uart##idx##_resources))
138 .resource = uart3_resources,
139};
140 81
141/* STI */ 82/* STI */
142static struct resource sti_resources[] = { 83static struct resource sti_resources[] = {
143 [0] = { 84 DEFINE_RES_MEM(0xe0180000, 0x54),
144 .name = "STI", 85 DEFINE_RES_IRQ(157),
145 .start = 0xe0180000,
146 .end = 0xe0180053,
147 .flags = IORESOURCE_MEM,
148 },
149 [1] = {
150 .start = 157,
151 .flags = IORESOURCE_IRQ,
152 },
153};
154
155static struct platform_device sti_device = {
156 .name = "em_sti",
157 .id = 0,
158 .resource = sti_resources,
159 .num_resources = ARRAY_SIZE(sti_resources),
160}; 86};
161 87
88#define emev2_register_sti() \
89 platform_device_register_simple("em_sti", 0, \
90 sti_resources, \
91 ARRAY_SIZE(sti_resources))
162 92
163/* GIO */ 93/* GIO */
164static struct gpio_em_config gio0_config = { 94static struct gpio_em_config gio0_config = {
@@ -168,36 +98,10 @@ static struct gpio_em_config gio0_config = {
168}; 98};
169 99
170static struct resource gio0_resources[] = { 100static struct resource gio0_resources[] = {
171 [0] = { 101 DEFINE_RES_MEM(0xe0050000, 0x2c),
172 .name = "GIO_000", 102 DEFINE_RES_MEM(0xe0050040, 0x20),
173 .start = 0xe0050000, 103 DEFINE_RES_IRQ(99),
174 .end = 0xe005002b, 104 DEFINE_RES_IRQ(100),
175 .flags = IORESOURCE_MEM,
176 },
177 [1] = {
178 .name = "GIO_000",
179 .start = 0xe0050040,
180 .end = 0xe005005f,
181 .flags = IORESOURCE_MEM,
182 },
183 [2] = {
184 .start = 99,
185 .flags = IORESOURCE_IRQ,
186 },
187 [3] = {
188 .start = 100,
189 .flags = IORESOURCE_IRQ,
190 },
191};
192
193static struct platform_device gio0_device = {
194 .name = "em_gio",
195 .id = 0,
196 .resource = gio0_resources,
197 .num_resources = ARRAY_SIZE(gio0_resources),
198 .dev = {
199 .platform_data = &gio0_config,
200 },
201}; 105};
202 106
203static struct gpio_em_config gio1_config = { 107static struct gpio_em_config gio1_config = {
@@ -207,36 +111,10 @@ static struct gpio_em_config gio1_config = {
207}; 111};
208 112
209static struct resource gio1_resources[] = { 113static struct resource gio1_resources[] = {
210 [0] = { 114 DEFINE_RES_MEM(0xe0050080, 0x2c),
211 .name = "GIO_032", 115 DEFINE_RES_MEM(0xe00500c0, 0x20),
212 .start = 0xe0050080, 116 DEFINE_RES_IRQ(101),
213 .end = 0xe00500ab, 117 DEFINE_RES_IRQ(102),
214 .flags = IORESOURCE_MEM,
215 },
216 [1] = {
217 .name = "GIO_032",
218 .start = 0xe00500c0,
219 .end = 0xe00500df,
220 .flags = IORESOURCE_MEM,
221 },
222 [2] = {
223 .start = 101,
224 .flags = IORESOURCE_IRQ,
225 },
226 [3] = {
227 .start = 102,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device gio1_device = {
233 .name = "em_gio",
234 .id = 1,
235 .resource = gio1_resources,
236 .num_resources = ARRAY_SIZE(gio1_resources),
237 .dev = {
238 .platform_data = &gio1_config,
239 },
240}; 118};
241 119
242static struct gpio_em_config gio2_config = { 120static struct gpio_em_config gio2_config = {
@@ -246,36 +124,10 @@ static struct gpio_em_config gio2_config = {
246}; 124};
247 125
248static struct resource gio2_resources[] = { 126static struct resource gio2_resources[] = {
249 [0] = { 127 DEFINE_RES_MEM(0xe0050100, 0x2c),
250 .name = "GIO_064", 128 DEFINE_RES_MEM(0xe0050140, 0x20),
251 .start = 0xe0050100, 129 DEFINE_RES_IRQ(103),
252 .end = 0xe005012b, 130 DEFINE_RES_IRQ(104),
253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
256 .name = "GIO_064",
257 .start = 0xe0050140,
258 .end = 0xe005015f,
259 .flags = IORESOURCE_MEM,
260 },
261 [2] = {
262 .start = 103,
263 .flags = IORESOURCE_IRQ,
264 },
265 [3] = {
266 .start = 104,
267 .flags = IORESOURCE_IRQ,
268 },
269};
270
271static struct platform_device gio2_device = {
272 .name = "em_gio",
273 .id = 2,
274 .resource = gio2_resources,
275 .num_resources = ARRAY_SIZE(gio2_resources),
276 .dev = {
277 .platform_data = &gio2_config,
278 },
279}; 131};
280 132
281static struct gpio_em_config gio3_config = { 133static struct gpio_em_config gio3_config = {
@@ -285,36 +137,10 @@ static struct gpio_em_config gio3_config = {
285}; 137};
286 138
287static struct resource gio3_resources[] = { 139static struct resource gio3_resources[] = {
288 [0] = { 140 DEFINE_RES_MEM(0xe0050180, 0x2c),
289 .name = "GIO_096", 141 DEFINE_RES_MEM(0xe00501c0, 0x20),
290 .start = 0xe0050180, 142 DEFINE_RES_IRQ(105),
291 .end = 0xe00501ab, 143 DEFINE_RES_IRQ(106),
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .name = "GIO_096",
296 .start = 0xe00501c0,
297 .end = 0xe00501df,
298 .flags = IORESOURCE_MEM,
299 },
300 [2] = {
301 .start = 105,
302 .flags = IORESOURCE_IRQ,
303 },
304 [3] = {
305 .start = 106,
306 .flags = IORESOURCE_IRQ,
307 },
308};
309
310static struct platform_device gio3_device = {
311 .name = "em_gio",
312 .id = 3,
313 .resource = gio3_resources,
314 .num_resources = ARRAY_SIZE(gio3_resources),
315 .dev = {
316 .platform_data = &gio3_config,
317 },
318}; 144};
319 145
320static struct gpio_em_config gio4_config = { 146static struct gpio_em_config gio4_config = {
@@ -324,126 +150,52 @@ static struct gpio_em_config gio4_config = {
324}; 150};
325 151
326static struct resource gio4_resources[] = { 152static struct resource gio4_resources[] = {
327 [0] = { 153 DEFINE_RES_MEM(0xe0050200, 0x2c),
328 .name = "GIO_128", 154 DEFINE_RES_MEM(0xe0050240, 0x20),
329 .start = 0xe0050200, 155 DEFINE_RES_IRQ(107),
330 .end = 0xe005022b, 156 DEFINE_RES_IRQ(108),
331 .flags = IORESOURCE_MEM,
332 },
333 [1] = {
334 .name = "GIO_128",
335 .start = 0xe0050240,
336 .end = 0xe005025f,
337 .flags = IORESOURCE_MEM,
338 },
339 [2] = {
340 .start = 107,
341 .flags = IORESOURCE_IRQ,
342 },
343 [3] = {
344 .start = 108,
345 .flags = IORESOURCE_IRQ,
346 },
347}; 157};
348 158
349static struct platform_device gio4_device = { 159#define emev2_register_gio(idx) \
350 .name = "em_gio", 160 platform_device_register_resndata(&platform_bus, "em_gio", \
351 .id = 4, 161 idx, gio##idx##_resources, \
352 .resource = gio4_resources, 162 ARRAY_SIZE(gio##idx##_resources), \
353 .num_resources = ARRAY_SIZE(gio4_resources), 163 &gio##idx##_config, \
354 .dev = { 164 sizeof(struct gpio_em_config))
355 .platform_data = &gio4_config,
356 },
357};
358 165
359static struct resource pmu_resources[] = { 166static struct resource pmu_resources[] = {
360 [0] = { 167 DEFINE_RES_IRQ(152),
361 .start = 152, 168 DEFINE_RES_IRQ(153),
362 .end = 152,
363 .flags = IORESOURCE_IRQ,
364 },
365 [1] = {
366 .start = 153,
367 .end = 153,
368 .flags = IORESOURCE_IRQ,
369 },
370}; 169};
371 170
372static struct platform_device pmu_device = { 171#define emev2_register_pmu() \
373 .name = "arm-pmu", 172 platform_device_register_simple("arm-pmu", -1, \
374 .id = -1, 173 pmu_resources, \
375 .num_resources = ARRAY_SIZE(pmu_resources), 174 ARRAY_SIZE(pmu_resources))
376 .resource = pmu_resources,
377};
378
379static struct platform_device *emev2_early_devices[] __initdata = {
380 &uart0_device,
381 &uart1_device,
382 &uart2_device,
383 &uart3_device,
384};
385
386static struct platform_device *emev2_late_devices[] __initdata = {
387 &sti_device,
388 &gio0_device,
389 &gio1_device,
390 &gio2_device,
391 &gio3_device,
392 &gio4_device,
393 &pmu_device,
394};
395 175
396void __init emev2_add_standard_devices(void) 176void __init emev2_add_standard_devices(void)
397{ 177{
398 emev2_clock_init(); 178 emev2_clock_init();
399 179
400 platform_add_devices(emev2_early_devices, 180 emev2_register_uart(0);
401 ARRAY_SIZE(emev2_early_devices)); 181 emev2_register_uart(1);
402 182 emev2_register_uart(2);
403 platform_add_devices(emev2_late_devices, 183 emev2_register_uart(3);
404 ARRAY_SIZE(emev2_late_devices)); 184 emev2_register_sti();
185 emev2_register_gio(0);
186 emev2_register_gio(1);
187 emev2_register_gio(2);
188 emev2_register_gio(3);
189 emev2_register_gio(4);
190 emev2_register_pmu();
405} 191}
406 192
407static void __init emev2_init_delay(void) 193void __init emev2_init_delay(void)
408{ 194{
409 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ 195 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
410} 196}
411 197
412void __init emev2_add_early_devices(void)
413{
414 emev2_init_delay();
415
416 early_platform_add_devices(emev2_early_devices,
417 ARRAY_SIZE(emev2_early_devices));
418
419 /* setup early console here as well */
420 shmobile_setup_console();
421}
422
423void __init emev2_init_irq(void)
424{
425 void __iomem *gic_dist_base;
426 void __iomem *gic_cpu_base;
427
428 /* Static mappings, never released */
429 gic_dist_base = ioremap(0xe0028000, PAGE_SIZE);
430 gic_cpu_base = ioremap(0xe0020000, PAGE_SIZE);
431 BUG_ON(!gic_dist_base || !gic_cpu_base);
432
433 /* Use GIC to handle interrupts */
434 gic_init(0, 29, gic_dist_base, gic_cpu_base);
435}
436
437#ifdef CONFIG_USE_OF 198#ifdef CONFIG_USE_OF
438static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
439 { }
440};
441
442static void __init emev2_add_standard_devices_dt(void)
443{
444 of_platform_populate(NULL, of_default_bus_match_table,
445 emev2_auxdata_lookup, NULL);
446}
447 199
448static const char *emev2_boards_compat_dt[] __initdata = { 200static const char *emev2_boards_compat_dt[] __initdata = {
449 "renesas,emev2", 201 "renesas,emev2",
@@ -452,10 +204,8 @@ static const char *emev2_boards_compat_dt[] __initdata = {
452 204
453DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") 205DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
454 .smp = smp_ops(emev2_smp_ops), 206 .smp = smp_ops(emev2_smp_ops),
207 .map_io = emev2_map_io,
455 .init_early = emev2_init_delay, 208 .init_early = emev2_init_delay,
456 .nr_irqs = NR_IRQS_LEGACY,
457 .init_irq = irqchip_init,
458 .init_machine = emev2_add_standard_devices_dt,
459 .dt_compat = emev2_boards_compat_dt, 209 .dt_compat = emev2_boards_compat_dt,
460MACHINE_END 210MACHINE_END
461 211
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 7f45c2edbca9..d533bd23865c 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -18,11 +18,11 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/irqchip.h>
22#include <linux/kernel.h> 21#include <linux/kernel.h>
23#include <linux/of_platform.h> 22#include <linux/of_platform.h>
24#include <linux/platform_data/irq-renesas-irqc.h> 23#include <linux/platform_data/irq-renesas-irqc.h>
25#include <linux/serial_sci.h> 24#include <linux/serial_sci.h>
25#include <linux/sh_timer.h>
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/irqs.h> 27#include <mach/irqs.h>
28#include <mach/r8a73a4.h> 28#include <mach/r8a73a4.h>
@@ -169,6 +169,25 @@ static const struct resource thermal0_resources[] = {
169 thermal0_resources, \ 169 thermal0_resources, \
170 ARRAY_SIZE(thermal0_resources)) 170 ARRAY_SIZE(thermal0_resources))
171 171
172static struct sh_timer_config cmt10_platform_data = {
173 .name = "CMT10",
174 .timer_bit = 0,
175 .clockevent_rating = 80,
176};
177
178static struct resource cmt10_resources[] = {
179 DEFINE_RES_MEM(0xe6130010, 0x0c),
180 DEFINE_RES_MEM(0xe6130000, 0x04),
181 DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
182};
183
184#define r8a7790_register_cmt(idx) \
185 platform_device_register_resndata(&platform_bus, "sh_cmt", \
186 idx, cmt##idx##_resources, \
187 ARRAY_SIZE(cmt##idx##_resources), \
188 &cmt##idx##_platform_data, \
189 sizeof(struct sh_timer_config))
190
172void __init r8a73a4_add_standard_devices(void) 191void __init r8a73a4_add_standard_devices(void)
173{ 192{
174 r8a73a4_register_scif(SCIFA0); 193 r8a73a4_register_scif(SCIFA0);
@@ -180,11 +199,20 @@ void __init r8a73a4_add_standard_devices(void)
180 r8a73a4_register_irqc(0); 199 r8a73a4_register_irqc(0);
181 r8a73a4_register_irqc(1); 200 r8a73a4_register_irqc(1);
182 r8a73a4_register_thermal(); 201 r8a73a4_register_thermal();
202 r8a7790_register_cmt(10);
203}
204
205void __init r8a73a4_init_delay(void)
206{
207#ifndef CONFIG_ARM_ARCH_TIMER
208 shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
209#endif
183} 210}
184 211
185#ifdef CONFIG_USE_OF 212#ifdef CONFIG_USE_OF
186void __init r8a73a4_add_standard_devices_dt(void) 213void __init r8a73a4_add_standard_devices_dt(void)
187{ 214{
215 platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
188 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 216 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
189} 217}
190 218
@@ -194,7 +222,7 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
194}; 222};
195 223
196DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") 224DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
197 .init_irq = irqchip_init, 225 .init_early = r8a73a4_init_delay,
198 .init_machine = r8a73a4_add_standard_devices_dt, 226 .init_machine = r8a73a4_add_standard_devices_dt,
199 .init_time = shmobile_timer_init, 227 .init_time = shmobile_timer_init,
200 .dt_compat = r8a73a4_boards_compat_dt, 228 .dt_compat = r8a73a4_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 00c5a707238b..84c5bb6d9725 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -588,6 +588,16 @@ static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
588 .addr = 0xfe1f0064, 588 .addr = 0xfe1f0064,
589 .chcr = CHCR_TX(XMIT_SZ_32BIT), 589 .chcr = CHCR_TX(XMIT_SZ_32BIT),
590 .mid_rid = 0xb5, 590 .mid_rid = 0xb5,
591 }, {
592 .slave_id = SHDMA_SLAVE_MMCIF_TX,
593 .addr = 0xe6bd0034,
594 .chcr = CHCR_TX(XMIT_SZ_32BIT),
595 .mid_rid = 0xd1,
596 }, {
597 .slave_id = SHDMA_SLAVE_MMCIF_RX,
598 .addr = 0xe6bd0034,
599 .chcr = CHCR_RX(XMIT_SZ_32BIT),
600 .mid_rid = 0xd2,
591 }, 601 },
592}; 602};
593 603
@@ -986,16 +996,22 @@ void __init r8a7740_add_early_devices(void)
986 996
987#ifdef CONFIG_USE_OF 997#ifdef CONFIG_USE_OF
988 998
989static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = { 999void __init r8a7740_add_early_devices_dt(void)
990 { } 1000{
991}; 1001 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
1002
1003 early_platform_add_devices(r8a7740_early_devices,
1004 ARRAY_SIZE(r8a7740_early_devices));
1005
1006 /* setup early console here as well */
1007 shmobile_setup_console();
1008}
992 1009
993void __init r8a7740_add_standard_devices_dt(void) 1010void __init r8a7740_add_standard_devices_dt(void)
994{ 1011{
995 platform_add_devices(r8a7740_devices_dt, 1012 platform_add_devices(r8a7740_devices_dt,
996 ARRAY_SIZE(r8a7740_devices_dt)); 1013 ARRAY_SIZE(r8a7740_devices_dt));
997 of_platform_populate(NULL, of_default_bus_match_table, 1014 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
998 r8a7740_auxdata_lookup, NULL);
999} 1015}
1000 1016
1001void __init r8a7740_init_delay(void) 1017void __init r8a7740_init_delay(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 80c20392ad7c..a3a2e37b03f3 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -53,7 +53,7 @@
53 .irqs = SCIx_IRQ_MUXED(irq), \ 53 .irqs = SCIx_IRQ_MUXED(irq), \
54} 54}
55 55
56static struct plat_sci_port scif_platform_data[] = { 56static struct plat_sci_port scif_platform_data[] __initdata = {
57 SCIF_INFO(0xffe40000, gic_iid(0x66)), 57 SCIF_INFO(0xffe40000, gic_iid(0x66)),
58 SCIF_INFO(0xffe41000, gic_iid(0x67)), 58 SCIF_INFO(0xffe41000, gic_iid(0x67)),
59 SCIF_INFO(0xffe42000, gic_iid(0x68)), 59 SCIF_INFO(0xffe42000, gic_iid(0x68)),
@@ -63,24 +63,24 @@ static struct plat_sci_port scif_platform_data[] = {
63}; 63};
64 64
65/* TMU */ 65/* TMU */
66static struct resource sh_tmu0_resources[] = { 66static struct resource sh_tmu0_resources[] __initdata = {
67 DEFINE_RES_MEM(0xffd80008, 12), 67 DEFINE_RES_MEM(0xffd80008, 12),
68 DEFINE_RES_IRQ(gic_iid(0x40)), 68 DEFINE_RES_IRQ(gic_iid(0x40)),
69}; 69};
70 70
71static struct sh_timer_config sh_tmu0_platform_data = { 71static struct sh_timer_config sh_tmu0_platform_data __initdata = {
72 .name = "TMU00", 72 .name = "TMU00",
73 .channel_offset = 0x4, 73 .channel_offset = 0x4,
74 .timer_bit = 0, 74 .timer_bit = 0,
75 .clockevent_rating = 200, 75 .clockevent_rating = 200,
76}; 76};
77 77
78static struct resource sh_tmu1_resources[] = { 78static struct resource sh_tmu1_resources[] __initdata = {
79 DEFINE_RES_MEM(0xffd80014, 12), 79 DEFINE_RES_MEM(0xffd80014, 12),
80 DEFINE_RES_IRQ(gic_iid(0x41)), 80 DEFINE_RES_IRQ(gic_iid(0x41)),
81}; 81};
82 82
83static struct sh_timer_config sh_tmu1_platform_data = { 83static struct sh_timer_config sh_tmu1_platform_data __initdata = {
84 .name = "TMU01", 84 .name = "TMU01",
85 .channel_offset = 0x10, 85 .channel_offset = 0x10,
86 .timer_bit = 1, 86 .timer_bit = 1,
@@ -189,7 +189,7 @@ USB_PLATFORM_INFO(ehci);
189USB_PLATFORM_INFO(ohci); 189USB_PLATFORM_INFO(ohci);
190 190
191/* Ether */ 191/* Ether */
192static struct resource ether_resources[] = { 192static struct resource ether_resources[] __initdata = {
193 DEFINE_RES_MEM(0xfde00000, 0x400), 193 DEFINE_RES_MEM(0xfde00000, 0x400),
194 DEFINE_RES_IRQ(gic_iid(0x89)), 194 DEFINE_RES_IRQ(gic_iid(0x89)),
195}; 195};
@@ -203,17 +203,17 @@ void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
203} 203}
204 204
205/* PFC/GPIO */ 205/* PFC/GPIO */
206static struct resource pfc_resources[] = { 206static struct resource pfc_resources[] __initdata = {
207 DEFINE_RES_MEM(0xfffc0000, 0x118), 207 DEFINE_RES_MEM(0xfffc0000, 0x118),
208}; 208};
209 209
210#define R8A7778_GPIO(idx) \ 210#define R8A7778_GPIO(idx) \
211static struct resource r8a7778_gpio##idx##_resources[] = { \ 211static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \
212 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 212 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \
213 DEFINE_RES_IRQ(gic_iid(0x87)), \ 213 DEFINE_RES_IRQ(gic_iid(0x87)), \
214}; \ 214}; \
215 \ 215 \
216static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \ 216static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
217 .gpio_base = 32 * (idx), \ 217 .gpio_base = 32 * (idx), \
218 .irq_base = GPIO_IRQ_BASE(idx), \ 218 .irq_base = GPIO_IRQ_BASE(idx), \
219 .number_of_pins = 32, \ 219 .number_of_pins = 32, \
@@ -249,7 +249,7 @@ void __init r8a7778_pinmux_init(void)
249}; 249};
250 250
251/* SDHI */ 251/* SDHI */
252static struct resource sdhi_resources[] = { 252static struct resource sdhi_resources[] __initdata = {
253 /* SDHI0 */ 253 /* SDHI0 */
254 DEFINE_RES_MEM(0xFFE4C000, 0x100), 254 DEFINE_RES_MEM(0xFFE4C000, 0x100),
255 DEFINE_RES_IRQ(gic_iid(0x77)), 255 DEFINE_RES_IRQ(gic_iid(0x77)),
@@ -365,12 +365,12 @@ void __init r8a7778_init_late(void)
365 platform_device_register_full(&ohci_info); 365 platform_device_register_full(&ohci_info);
366} 366}
367 367
368static struct renesas_intc_irqpin_config irqpin_platform_data = { 368static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
369 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 369 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
370 .sense_bitfield_width = 2, 370 .sense_bitfield_width = 2,
371}; 371};
372 372
373static struct resource irqpin_resources[] = { 373static struct resource irqpin_resources[] __initdata = {
374 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 374 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
375 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 375 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
376 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 376 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
@@ -408,17 +408,25 @@ void __init r8a7778_init_irq_extpin(int irlm)
408 &irqpin_platform_data, sizeof(irqpin_platform_data)); 408 &irqpin_platform_data, sizeof(irqpin_platform_data));
409} 409}
410 410
411void __init r8a7778_init_delay(void)
412{
413 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
414}
415
416#ifdef CONFIG_USE_OF
411#define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 417#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
412#define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 418#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
413 419
414#define INT2NTSR0 0x00018 /* 0xfe700018 */ 420#define INT2NTSR0 0x00018 /* 0xfe700018 */
415#define INT2NTSR1 0x0002c /* 0xfe70002c */ 421#define INT2NTSR1 0x0002c /* 0xfe70002c */
416static void __init r8a7778_init_irq_common(void) 422void __init r8a7778_init_irq_dt(void)
417{ 423{
418 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 424 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
419 425
420 BUG_ON(!base); 426 BUG_ON(!base);
421 427
428 irqchip_init();
429
422 /* route all interrupts to ARM */ 430 /* route all interrupts to ARM */
423 __raw_writel(0x73ffffff, base + INT2NTSR0); 431 __raw_writel(0x73ffffff, base + INT2NTSR0);
424 __raw_writel(0xffffffff, base + INT2NTSR1); 432 __raw_writel(0xffffffff, base + INT2NTSR1);
@@ -430,43 +438,6 @@ static void __init r8a7778_init_irq_common(void)
430 iounmap(base); 438 iounmap(base);
431} 439}
432 440
433void __init r8a7778_init_irq(void)
434{
435 void __iomem *gic_dist_base;
436 void __iomem *gic_cpu_base;
437
438 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
439 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
440 BUG_ON(!gic_dist_base || !gic_cpu_base);
441
442 /* use GIC to handle interrupts */
443 gic_init(0, 29, gic_dist_base, gic_cpu_base);
444
445 r8a7778_init_irq_common();
446}
447
448void __init r8a7778_init_delay(void)
449{
450 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
451}
452
453#ifdef CONFIG_USE_OF
454void __init r8a7778_init_irq_dt(void)
455{
456 irqchip_init();
457 r8a7778_init_irq_common();
458}
459
460static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
461 {},
462};
463
464void __init r8a7778_add_standard_devices_dt(void)
465{
466 of_platform_populate(NULL, of_default_bus_match_table,
467 r8a7778_auxdata_lookup, NULL);
468}
469
470static const char *r8a7778_compat_dt[] __initdata = { 441static const char *r8a7778_compat_dt[] __initdata = {
471 "renesas,r8a7778", 442 "renesas,r8a7778",
472 NULL, 443 NULL,
@@ -475,7 +446,6 @@ static const char *r8a7778_compat_dt[] __initdata = {
475DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 446DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
476 .init_early = r8a7778_init_delay, 447 .init_early = r8a7778_init_delay,
477 .init_irq = r8a7778_init_irq_dt, 448 .init_irq = r8a7778_init_irq_dt,
478 .init_machine = r8a7778_add_standard_devices_dt,
479 .init_time = shmobile_timer_init, 449 .init_time = shmobile_timer_init,
480 .dt_compat = r8a7778_compat_dt, 450 .dt_compat = r8a7778_compat_dt,
481 .init_late = r8a7778_init_late, 451 .init_late = r8a7778_init_late,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 398687761f50..66d38261ecaa 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -665,10 +665,6 @@ void __init r8a7779_init_delay(void)
665 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ 665 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
666} 666}
667 667
668static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
669 {},
670};
671
672void __init r8a7779_add_standard_devices_dt(void) 668void __init r8a7779_add_standard_devices_dt(void)
673{ 669{
674 /* clocks are setup late during boot in the case of DT */ 670 /* clocks are setup late during boot in the case of DT */
@@ -676,8 +672,7 @@ void __init r8a7779_add_standard_devices_dt(void)
676 672
677 platform_add_devices(r8a7779_devices_dt, 673 platform_add_devices(r8a7779_devices_dt,
678 ARRAY_SIZE(r8a7779_devices_dt)); 674 ARRAY_SIZE(r8a7779_devices_dt));
679 of_platform_populate(NULL, of_default_bus_match_table, 675 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
680 r8a7779_auxdata_lookup, NULL);
681} 676}
682 677
683static const char *r8a7779_compat_dt[] __initdata = { 678static const char *r8a7779_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 28f94752b8ff..4c96dad21195 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -19,12 +19,12 @@
19 */ 19 */
20 20
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/irqchip.h>
23#include <linux/kernel.h> 22#include <linux/kernel.h>
24#include <linux/of_platform.h> 23#include <linux/of_platform.h>
25#include <linux/serial_sci.h>
26#include <linux/platform_data/gpio-rcar.h> 24#include <linux/platform_data/gpio-rcar.h>
27#include <linux/platform_data/irq-renesas-irqc.h> 25#include <linux/platform_data/irq-renesas-irqc.h>
26#include <linux/serial_sci.h>
27#include <linux/sh_timer.h>
28#include <mach/common.h> 28#include <mach/common.h>
29#include <mach/irqs.h> 29#include <mach/irqs.h>
30#include <mach/r8a7790.h> 30#include <mach/r8a7790.h>
@@ -149,6 +149,36 @@ static struct resource irqc0_resources[] __initdata = {
149 &irqc##idx##_data, \ 149 &irqc##idx##_data, \
150 sizeof(struct renesas_irqc_config)) 150 sizeof(struct renesas_irqc_config))
151 151
152static struct resource thermal_resources[] __initdata = {
153 DEFINE_RES_MEM(0xe61f0000, 0x14),
154 DEFINE_RES_MEM(0xe61f0100, 0x38),
155 DEFINE_RES_IRQ(gic_spi(69)),
156};
157
158#define r8a7790_register_thermal() \
159 platform_device_register_simple("rcar_thermal", -1, \
160 thermal_resources, \
161 ARRAY_SIZE(thermal_resources))
162
163static struct sh_timer_config cmt00_platform_data = {
164 .name = "CMT00",
165 .timer_bit = 0,
166 .clockevent_rating = 80,
167};
168
169static struct resource cmt00_resources[] = {
170 DEFINE_RES_MEM(0xffca0510, 0x0c),
171 DEFINE_RES_MEM(0xffca0500, 0x04),
172 DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
173};
174
175#define r8a7790_register_cmt(idx) \
176 platform_device_register_resndata(&platform_bus, "sh_cmt", \
177 idx, cmt##idx##_resources, \
178 ARRAY_SIZE(cmt##idx##_resources), \
179 &cmt##idx##_platform_data, \
180 sizeof(struct sh_timer_config))
181
152void __init r8a7790_add_standard_devices(void) 182void __init r8a7790_add_standard_devices(void)
153{ 183{
154 r8a7790_register_scif(SCIFA0); 184 r8a7790_register_scif(SCIFA0);
@@ -162,34 +192,91 @@ void __init r8a7790_add_standard_devices(void)
162 r8a7790_register_scif(HSCIF0); 192 r8a7790_register_scif(HSCIF0);
163 r8a7790_register_scif(HSCIF1); 193 r8a7790_register_scif(HSCIF1);
164 r8a7790_register_irqc(0); 194 r8a7790_register_irqc(0);
195 r8a7790_register_thermal();
196 r8a7790_register_cmt(00);
165} 197}
166 198
199#define MODEMR 0xe6160060
200
201u32 __init r8a7790_read_mode_pins(void)
202{
203 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
204 u32 mode;
205
206 BUG_ON(!modemr);
207 mode = ioread32(modemr);
208 iounmap(modemr);
209
210 return mode;
211}
212
213#define CNTCR 0
214#define CNTFID0 0x20
215
167void __init r8a7790_timer_init(void) 216void __init r8a7790_timer_init(void)
168{ 217{
169 void __iomem *cntcr; 218#ifdef CONFIG_ARM_ARCH_TIMER
219 u32 mode = r8a7790_read_mode_pins();
220 void __iomem *base;
221 int extal_mhz = 0;
222 u32 freq;
223
224 /* At Linux boot time the r8a7790 arch timer comes up
225 * with the counter disabled. Moreover, it may also report
226 * a potentially incorrect fixed 13 MHz frequency. To be
227 * correct these registers need to be updated to use the
228 * frequency EXTAL / 2 which can be determined by the MD pins.
229 */
230
231 switch (mode & (MD(14) | MD(13))) {
232 case 0:
233 extal_mhz = 15;
234 break;
235 case MD(13):
236 extal_mhz = 20;
237 break;
238 case MD(14):
239 extal_mhz = 26;
240 break;
241 case MD(13) | MD(14):
242 extal_mhz = 30;
243 break;
244 }
170 245
171 /* make sure arch timer is started by setting bit 0 of CNTCT */ 246 /* The arch timer frequency equals EXTAL / 2 */
172 cntcr = ioremap(0xe6080000, PAGE_SIZE); 247 freq = extal_mhz * (1000000 / 2);
173 iowrite32(1, cntcr); 248
174 iounmap(cntcr); 249 /* Remap "armgcnt address map" space */
250 base = ioremap(0xe6080000, PAGE_SIZE);
251
252 /* Update registers with correct frequency */
253 iowrite32(freq, base + CNTFID0);
254 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
255
256 /* make sure arch timer is started by setting bit 0 of CNTCR */
257 iowrite32(1, base + CNTCR);
258 iounmap(base);
259#endif /* CONFIG_ARM_ARCH_TIMER */
175 260
176 shmobile_timer_init(); 261 shmobile_timer_init();
177} 262}
178 263
179#ifdef CONFIG_USE_OF 264void __init r8a7790_init_delay(void)
180void __init r8a7790_add_standard_devices_dt(void)
181{ 265{
182 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 266#ifndef CONFIG_ARM_ARCH_TIMER
267 shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
268#endif
183} 269}
184 270
271#ifdef CONFIG_USE_OF
272
185static const char *r8a7790_boards_compat_dt[] __initdata = { 273static const char *r8a7790_boards_compat_dt[] __initdata = {
186 "renesas,r8a7790", 274 "renesas,r8a7790",
187 NULL, 275 NULL,
188}; 276};
189 277
190DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") 278DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
191 .init_irq = irqchip_init, 279 .init_early = r8a7790_init_delay,
192 .init_machine = r8a7790_add_standard_devices_dt,
193 .init_time = r8a7790_timer_init, 280 .init_time = r8a7790_timer_init,
194 .dt_compat = r8a7790_boards_compat_dt, 281 .dt_compat = r8a7790_boards_compat_dt,
195MACHINE_END 282MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 5502d624aca6..13e6fdbde0a5 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -1147,10 +1147,6 @@ void __init sh7372_add_early_devices_dt(void)
1147 shmobile_setup_console(); 1147 shmobile_setup_console();
1148} 1148}
1149 1149
1150static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1151 { }
1152};
1153
1154void __init sh7372_add_standard_devices_dt(void) 1150void __init sh7372_add_standard_devices_dt(void)
1155{ 1151{
1156 /* clocks are setup late during boot in the case of DT */ 1152 /* clocks are setup late during boot in the case of DT */
@@ -1159,8 +1155,7 @@ void __init sh7372_add_standard_devices_dt(void)
1159 platform_add_devices(sh7372_early_devices, 1155 platform_add_devices(sh7372_early_devices,
1160 ARRAY_SIZE(sh7372_early_devices)); 1156 ARRAY_SIZE(sh7372_early_devices));
1161 1157
1162 of_platform_populate(NULL, of_default_bus_match_table, 1158 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1163 sh7372_auxdata_lookup, NULL);
1164} 1159}
1165 1160
1166static const char *sh7372_boards_compat_dt[] __initdata = { 1161static const char *sh7372_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 96e7ca1e4e11..516c2391b47a 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,7 +22,6 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/irqchip.h>
26#include <linux/platform_device.h> 25#include <linux/platform_device.h>
27#include <linux/of_platform.h> 26#include <linux/of_platform.h>
28#include <linux/delay.h> 27#include <linux/delay.h>
@@ -61,29 +60,16 @@ void __init sh73a0_map_io(void)
61 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); 60 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
62} 61}
63 62
64static struct resource sh73a0_pfc_resources[] = { 63/* PFC */
65 [0] = { 64static struct resource pfc_resources[] __initdata = {
66 .start = 0xe6050000, 65 DEFINE_RES_MEM(0xe6050000, 0x8000),
67 .end = 0xe6057fff, 66 DEFINE_RES_MEM(0xe605801c, 0x000c),
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = 0xe605801c,
72 .end = 0xe6058027,
73 .flags = IORESOURCE_MEM,
74 }
75};
76
77static struct platform_device sh73a0_pfc_device = {
78 .name = "pfc-sh73a0",
79 .id = -1,
80 .resource = sh73a0_pfc_resources,
81 .num_resources = ARRAY_SIZE(sh73a0_pfc_resources),
82}; 67};
83 68
84void __init sh73a0_pinmux_init(void) 69void __init sh73a0_pinmux_init(void)
85{ 70{
86 platform_device_register(&sh73a0_pfc_device); 71 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
72 ARRAY_SIZE(pfc_resources));
87} 73}
88 74
89static struct plat_sci_port scif0_platform_data = { 75static struct plat_sci_port scif0_platform_data = {
@@ -958,10 +944,6 @@ void __init sh73a0_add_early_devices(void)
958 944
959#ifdef CONFIG_USE_OF 945#ifdef CONFIG_USE_OF
960 946
961static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
962 {},
963};
964
965void __init sh73a0_add_standard_devices_dt(void) 947void __init sh73a0_add_standard_devices_dt(void)
966{ 948{
967 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; 949 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
@@ -971,8 +953,7 @@ void __init sh73a0_add_standard_devices_dt(void)
971 953
972 platform_add_devices(sh73a0_devices_dt, 954 platform_add_devices(sh73a0_devices_dt,
973 ARRAY_SIZE(sh73a0_devices_dt)); 955 ARRAY_SIZE(sh73a0_devices_dt));
974 of_platform_populate(NULL, of_default_bus_match_table, 956 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
975 sh73a0_auxdata_lookup, NULL);
976 957
977 /* Instantiate cpufreq-cpu0 */ 958 /* Instantiate cpufreq-cpu0 */
978 platform_device_register_full(&devinfo); 959 platform_device_register_full(&devinfo);
@@ -988,7 +969,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
988 .map_io = sh73a0_map_io, 969 .map_io = sh73a0_map_io,
989 .init_early = sh73a0_init_delay, 970 .init_early = sh73a0_init_delay,
990 .nr_irqs = NR_IRQS_LEGACY, 971 .nr_irqs = NR_IRQS_LEGACY,
991 .init_irq = irqchip_init,
992 .init_machine = sh73a0_add_standard_devices_dt, 972 .init_machine = sh73a0_add_standard_devices_dt,
993 .dt_compat = sh73a0_boards_compat_dt, 973 .dt_compat = sh73a0_boards_compat_dt,
994MACHINE_END 974MACHINE_END
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 22a05a869d25..78e84c582453 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -29,6 +29,8 @@
29#include <asm/smp_scu.h> 29#include <asm/smp_scu.h>
30 30
31#define EMEV2_SCU_BASE 0x1e000000 31#define EMEV2_SCU_BASE 0x1e000000
32#define EMEV2_SMU_BASE 0xe0110000
33#define SMU_GENERAL_REG0 0x7c0
32 34
33static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) 35static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
34{ 36{
@@ -38,10 +40,18 @@ static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
38 40
39static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) 41static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
40{ 42{
43 void __iomem *smu;
44
45 /* setup EMEV2 specific SCU base, enable */
46 shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
41 scu_enable(shmobile_scu_base); 47 scu_enable(shmobile_scu_base);
42 48
43 /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */ 49 /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */
44 emev2_set_boot_vector(__pa(shmobile_boot_vector)); 50 smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
51 if (smu) {
52 iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0);
53 iounmap(smu);
54 }
45 shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); 55 shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
46 shmobile_boot_arg = (unsigned long)shmobile_scu_base; 56 shmobile_boot_arg = (unsigned long)shmobile_scu_base;
47 57
@@ -49,21 +59,7 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
49 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); 59 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
50} 60}
51 61
52static void __init emev2_smp_init_cpus(void)
53{
54 unsigned int ncores;
55
56 /* setup EMEV2 specific SCU base */
57 shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
58 emev2_clock_init(); /* need ioremapped SMU */
59
60 ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
61
62 shmobile_smp_init_cpus(ncores);
63}
64
65struct smp_operations emev2_smp_ops __initdata = { 62struct smp_operations emev2_smp_ops __initdata = {
66 .smp_init_cpus = emev2_smp_init_cpus,
67 .smp_prepare_cpus = emev2_smp_prepare_cpus, 63 .smp_prepare_cpus = emev2_smp_prepare_cpus,
68 .smp_boot_secondary = emev2_boot_secondary, 64 .smp_boot_secondary = emev2_boot_secondary,
69}; 65};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 02:00:41 -0400