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authorAntoine Ténart <antoine.tenart@free-electrons.com>2014-07-30 14:13:59 -0400
committerTejun Heo <tj@kernel.org>2014-07-30 15:39:47 -0400
commit724f24ee651c59aa3f42a8ea2d441cfac5015013 (patch)
treea9163170a73e950fae2dc08777b7569e8d2bbd98
parent30f3c73c9b526a88920d098dcb331319e284e1b3 (diff)
Documentation: bindings: document the sub-nodes AHCI bindings
The libahci now allows to use multiple PHYs and to represent each port as a sub-node. Add these bindings to the documentation. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Tejun Heo <tj@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/ata/ahci-platform.txt41
1 files changed, 41 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 549ceb8cb93b..4ab09f2202d4 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -3,6 +3,10 @@
3SATA nodes are defined to describe on-chip Serial ATA controllers. 3SATA nodes are defined to describe on-chip Serial ATA controllers.
4Each SATA controller should have its own node. 4Each SATA controller should have its own node.
5 5
6It is possible, but not required, to represent each port as a sub-node.
7It allows to enable each port independently when dealing with multiple
8PHYs.
9
6Required properties: 10Required properties:
7- compatible : compatible string, one of: 11- compatible : compatible string, one of:
8 - "allwinner,sun4i-a10-ahci" 12 - "allwinner,sun4i-a10-ahci"
@@ -12,13 +16,30 @@ Required properties:
12 - "snps,dwc-ahci" 16 - "snps,dwc-ahci"
13 - "snps,exynos5440-ahci" 17 - "snps,exynos5440-ahci"
14 - "snps,spear-ahci" 18 - "snps,spear-ahci"
19 - "generic-ahci"
15- interrupts : <interrupt mapping for SATA IRQ> 20- interrupts : <interrupt mapping for SATA IRQ>
16- reg : <registers mapping> 21- reg : <registers mapping>
17 22
23Please note that when using "generic-ahci" you must also specify a SoC specific
24compatible:
25 compatible = "manufacturer,soc-model-ahci", "generic-ahci";
26
18Optional properties: 27Optional properties:
19- dma-coherent : Present if dma operations are coherent 28- dma-coherent : Present if dma operations are coherent
20- clocks : a list of phandle + clock specifier pairs 29- clocks : a list of phandle + clock specifier pairs
21- target-supply : regulator for SATA target power 30- target-supply : regulator for SATA target power
31- phys : reference to the SATA PHY node
32- phy-names : must be "sata-phy"
33
34Required properties when using sub-nodes:
35- #address-cells : number of cells to encode an address
36- #size-cells : number of cells representing the size of an address
37
38
39Sub-nodes required properties:
40- reg : the port number
41- phys : reference to the SATA PHY node
42
22 43
23Examples: 44Examples:
24 sata@ffe08000 { 45 sata@ffe08000 {
@@ -34,3 +55,23 @@ Examples:
34 clocks = <&pll6 0>, <&ahb_gates 25>; 55 clocks = <&pll6 0>, <&ahb_gates 25>;
35 target-supply = <&reg_ahci_5v>; 56 target-supply = <&reg_ahci_5v>;
36 }; 57 };
58
59With sub-nodes:
60 sata@f7e90000 {
61 compatible = "marvell,berlin2q-achi", "generic-ahci";
62 reg = <0xe90000 0x1000>;
63 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&chip CLKID_SATA>;
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 sata0: sata-port@0 {
69 reg = <0>;
70 phys = <&sata_phy 0>;
71 };
72
73 sata1: sata-port@1 {
74 reg = <1>;
75 phys = <&sata_phy 1>;
76 };
77 };