diff options
author | Anson Huang <b20788@freescale.com> | 2014-09-10 23:29:40 -0400 |
---|---|---|
committer | Shawn Guo <shawn.guo@freescale.com> | 2014-09-15 22:09:40 -0400 |
commit | 6f11c69d35d5b1db0ec4cfccd0188b00eada3ad3 (patch) | |
tree | b75a890fac85b11840e5bb4cf3df7d72bd2deb67 | |
parent | 69d9a3fe06ed4bdb69f0a20cfa031dbcb0ee8dc3 (diff) |
ARM: imx: add gpt_3m clk for i.mx6qdl
Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.
i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
-rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 8 | ||||
-rw-r--r-- | include/dt-bindings/clock/imx6qdl-clock.h | 3 |
2 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 4f8ce60a2e90..1412daf4a714 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
@@ -245,6 +245,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
245 | clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); | 245 | clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); |
246 | clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); | 246 | clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); |
247 | clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); | 247 | clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); |
248 | clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); | ||
248 | if (cpu_is_imx6dl()) { | 249 | if (cpu_is_imx6dl()) { |
249 | clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); | 250 | clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); |
250 | clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); | 251 | clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); |
@@ -461,6 +462,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
461 | clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); | 462 | clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); |
462 | clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); | 463 | clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); |
463 | 464 | ||
465 | /* | ||
466 | * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it | ||
467 | * to clock gpt_ipg_per to ease the gpt driver code. | ||
468 | */ | ||
469 | if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) | ||
470 | clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER]; | ||
471 | |||
464 | imx_check_clocks(clk, ARRAY_SIZE(clk)); | 472 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
465 | 473 | ||
466 | clk_data.clks = clk; | 474 | clk_data.clks = clk; |
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index c0d88ab013b4..ddaef8620b2c 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h | |||
@@ -247,6 +247,7 @@ | |||
247 | #define IMX6QDL_PLL5_BYPASS 234 | 247 | #define IMX6QDL_PLL5_BYPASS 234 |
248 | #define IMX6QDL_PLL6_BYPASS 235 | 248 | #define IMX6QDL_PLL6_BYPASS 235 |
249 | #define IMX6QDL_PLL7_BYPASS 236 | 249 | #define IMX6QDL_PLL7_BYPASS 236 |
250 | #define IMX6QDL_CLK_END 237 | 250 | #define IMX6QDL_CLK_GPT_3M 237 |
251 | #define IMX6QDL_CLK_END 238 | ||
251 | 252 | ||
252 | #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ | 253 | #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ |