drm/radeon/cik: use hw defaults for TC_CFG registers

Use the hw power up values rather than 0.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 0 insertions, 14 deletions

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e8ec15dfe5f8..6ffe824624fb 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5353,20 +5353,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
                                 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
 
-        /* TC cache setup ??? */
-        WREG32(TC_CFG_L1_LOAD_POLICY0, 0);
-        WREG32(TC_CFG_L1_LOAD_POLICY1, 0);
-        WREG32(TC_CFG_L1_STORE_POLICY, 0);
-
-        WREG32(TC_CFG_L2_LOAD_POLICY0, 0);
-        WREG32(TC_CFG_L2_LOAD_POLICY1, 0);
-        WREG32(TC_CFG_L2_STORE_POLICY0, 0);
-        WREG32(TC_CFG_L2_STORE_POLICY1, 0);
-        WREG32(TC_CFG_L2_ATOMIC_POLICY, 0);
-
-        WREG32(TC_CFG_L1_VOLATILE, 0);
-        WREG32(TC_CFG_L2_VOLATILE, 0);
-
         if (rdev->family == CHIP_KAVERI) {
                 u32 tmp = RREG32(CHUB_CONTROL);
                 tmp &= ~BYPASS_VM;