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authorStephen Warren <swarren@nvidia.com>2013-10-29 15:47:21 -0400
committerStephen Warren <swarren@nvidia.com>2013-12-04 14:25:25 -0500
commit6dee8200b794a83c0fb144878fdf0ac52af28835 (patch)
tree5f8c36c441ff5d2fd3a5fb2f6315b897e58e3552
parent2f1d70af28a94988c1e8fba2ae03d4c7e68e690b (diff)
ARM: tegra: use section-sized static mappings for LPAE too
The static mappings for Tegra's PPSB and APB regions were sized at 1MB in order to allow mapping via sections in order to avoid burning RAM for PTEs. On LPAE, sections are 2MB, so the static mappings need to be larger in order to gain the same benefit. Set IO_{PPSB,APB}_SIZE to SECTION_SIZE so this adjusts automatically. While we're fiddling with iomap.h, compress IO_{IRAM,CPU}_VIRT together to save virtual address space in the vmalloc region; these two regions are mapped using PTEs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/iomap.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 26b1c2ad0ceb..ee79808e93a3 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -19,6 +19,7 @@
19#ifndef __MACH_TEGRA_IOMAP_H 19#ifndef __MACH_TEGRA_IOMAP_H
20#define __MACH_TEGRA_IOMAP_H 20#define __MACH_TEGRA_IOMAP_H
21 21
22#include <asm/pgtable.h>
22#include <asm/sizes.h> 23#include <asm/sizes.h>
23 24
24#define TEGRA_IRAM_BASE 0x40000000 25#define TEGRA_IRAM_BASE 0x40000000
@@ -115,27 +116,26 @@
115 * two 256MB io windows (that actually only use about 64KB 116 * two 256MB io windows (that actually only use about 64KB
116 * at the start of each). 117 * at the start of each).
117 * 118 *
118 * We will just map the first 1MB of each window (to minimize 119 * We will just map the first MMU section of each window (to minimize
119 * pt entries needed) and provide a macro to transform physical 120 * pt entries needed) and provide a macro to transform physical
120 * io addresses to an appropriate void __iomem *. 121 * io addresses to an appropriate void __iomem *.
121 *
122 */ 122 */
123 123
124#define IO_IRAM_PHYS 0x40000000 124#define IO_IRAM_PHYS 0x40000000
125#define IO_IRAM_VIRT IOMEM(0xFE400000) 125#define IO_IRAM_VIRT IOMEM(0xFE400000)
126#define IO_IRAM_SIZE SZ_256K 126#define IO_IRAM_SIZE SZ_256K
127 127
128#define IO_CPU_PHYS 0x50040000 128#define IO_CPU_PHYS 0x50040000
129#define IO_CPU_VIRT IOMEM(0xFE000000) 129#define IO_CPU_VIRT IOMEM(0xFE440000)
130#define IO_CPU_SIZE SZ_16K 130#define IO_CPU_SIZE SZ_16K
131 131
132#define IO_PPSB_PHYS 0x60000000 132#define IO_PPSB_PHYS 0x60000000
133#define IO_PPSB_VIRT IOMEM(0xFE200000) 133#define IO_PPSB_VIRT IOMEM(0xFE200000)
134#define IO_PPSB_SIZE SZ_1M 134#define IO_PPSB_SIZE SECTION_SIZE
135 135
136#define IO_APB_PHYS 0x70000000 136#define IO_APB_PHYS 0x70000000
137#define IO_APB_VIRT IOMEM(0xFE300000) 137#define IO_APB_VIRT IOMEM(0xFE000000)
138#define IO_APB_SIZE SZ_1M 138#define IO_APB_SIZE SECTION_SIZE
139 139
140#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 140#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
141#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) 141#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))