drm/i915: hw state readout support for pixel_multiplier

Incomplete since ilk+ support needs proper pch dpll tracking first.
SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
to actually work.

v2: Make sure that we call encoder->get_config _after_ we
get_pipe_config to be consistent in both setup_hw_state and the
modeset state checker. Otherwise the clever trick with handling the
pixel mutliplier on i915G/GM where the encoder overrides the default
value of 1 from the crtc get_pipe_config function doesn't work.
Spotted by Imre Deak.

v3: Actually cross-check the pixel mutliplier (but not on pch split
platforms for now). Now actually also tested on a i915G with a sdvo
encoder plugged in.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 66 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0e1f82810f58..421b7e2ece3b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5001,6 +5001,23 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 
         i9xx_get_pfit_config(crtc, pipe_config);
 
+        if (INTEL_INFO(dev)->gen >= 4) {
+                tmp = I915_READ(DPLL_MD(crtc->pipe));
+                pipe_config->pixel_multiplier =
+                        ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
+                         >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
+        } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
+                tmp = I915_READ(DPLL(crtc->pipe));
+                pipe_config->pixel_multiplier =
+                        ((tmp & SDVO_MULTIPLIER_MASK)
+                         >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
+        } else {
+                /* Note that on i915G/GM the pixel multiplier is in the sdvo
+                 * port and will be fixed up in the encoder->get_config
+                 * function. */
+                pipe_config->pixel_multiplier = 1;
+        }
+
         return true;
 }
 
@@ -5864,6 +5881,12 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
 
                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
+
+                /* XXX: Can't properly read out the pch dpll pixel multiplier
+                 * since we don't have state tracking for pch clocks yet. */
+                pipe_config->pixel_multiplier = 1;
+        } else {
+                pipe_config->pixel_multiplier = 1;
         }
 
         intel_get_pipe_timings(crtc, pipe_config);
@@ -5998,6 +6021,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
 
+        pipe_config->pixel_multiplier = 1;
+
         return true;
 }
 
@@ -8090,6 +8115,9 @@ intel_pipe_config_compare(struct drm_device *dev,
         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
 
+        if (!HAS_PCH_SPLIT(dev))
+                PIPE_CONF_CHECK_I(pixel_multiplier);
+
         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
                               DRM_MODE_FLAG_INTERLACE);
 
@@ -8211,9 +8239,8 @@ intel_modeset_check_state(struct drm_device *dev)
                         enabled = true;
                         if (encoder->connectors_active)
                                 active = true;
-                        if (encoder->get_config)
-                                encoder->get_config(encoder, &pipe_config);
                 }
+
                 WARN(active != crtc->active,
                      "crtc's computed active state doesn't match tracked active state "
                      "(expected %i, found %i)\n", active, crtc->active);
@@ -8223,6 +8250,14 @@ intel_modeset_check_state(struct drm_device *dev)
 
                 active = dev_priv->display.get_pipe_config(crtc,
                                                            &pipe_config);
+                list_for_each_entry(encoder, &dev->mode_config.encoder_list,
+                                    base.head) {
+                        if (encoder->base.crtc != &crtc->base)
+                                continue;
+                        if (encoder->get_config)
+                                encoder->get_config(encoder, &pipe_config);
+                }
+
                 WARN(crtc->active != active,
                      "crtc active state doesn't match with hw state "
                      "(expected %i, found %i)\n", crtc->active, active);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index f4588a2c65ac..5c816dd75bec 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1313,9 +1313,13 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
 static void intel_sdvo_get_config(struct intel_encoder *encoder,
                                   struct intel_crtc_config *pipe_config)
 {
+        struct drm_device *dev = encoder->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
         struct intel_sdvo_dtd dtd;
-        u32 flags = 0;
+        int encoder_pixel_multiplier = 0;
+        u32 flags = 0, sdvox;
+        u8 val;
         bool ret;
 
         ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
@@ -1335,6 +1339,30 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
                 flags |= DRM_MODE_FLAG_NVSYNC;
 
         pipe_config->adjusted_mode.flags |= flags;
+
+        if (IS_I915G(dev) || IS_I915GM(dev)) {
+                sdvox = I915_READ(intel_sdvo->sdvo_reg);
+                pipe_config->pixel_multiplier =
+                        ((sdvox & SDVO_PORT_MULTIPLY_MASK)
+                         >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
+        }
+
+        /* Cross check the port pixel multiplier with the sdvo encoder state. */
+        intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
+        switch (val) {
+        case SDVO_CLOCK_RATE_MULT_1X:
+                encoder_pixel_multiplier = 1;
+                break;
+        case SDVO_CLOCK_RATE_MULT_2X:
+                encoder_pixel_multiplier = 2;
+                break;
+        case SDVO_CLOCK_RATE_MULT_4X:
+                encoder_pixel_multiplier = 4;
+                break;
+        }
+        WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
+             "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
+             pipe_config->pixel_multiplier, encoder_pixel_multiplier);
 }
 
 static void intel_disable_sdvo(struct intel_encoder *encoder)