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authorLinus Torvalds <torvalds@linux-foundation.org>2013-11-15 17:27:22 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-11-15 17:27:22 -0500
commit6c0514ddd973ff13c3d2b2e7ac1422c982afb8eb (patch)
treebeccc0d9aa9df71f4af081736e8c0b007dfcb603
parent98d38dd2ee30322fc9934d7490be3c5bee80950e (diff)
parent36855dcfc980f247909b8f63776664c6ccb6f183 (diff)
Merge tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux
Pull blackfin updates from Steven Miao: "Blackfin gpio changes, add adi pinctrl driver, and bug fixes" * tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux: blackfin: fix build warning for unused variable smp: bf561: and smb_wmb()/smp_rmb() at ipi send/receive pm: use GFP_ATOMIC when pm core call this function blackfin: serial: Add serial port_fer and port_mux early platform resources. blackfin: pinctrl-adi2: code cleanup after using pinctrl-adi2 blackfin: adi gpio driver and pinctrl driver support bf609: update default config for spi Blackfin: bfin_gpio: Use proper mask for comparing pfunc
Diffstat
-rw-r--r--arch/blackfin/configs/BF609-EZKIT_defconfig2
-rw-r--r--arch/blackfin/include/asm/irq.h3
-rw-r--r--arch/blackfin/include/asm/irq_handler.h6
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c159
-rw-r--r--arch/blackfin/mach-bf548/Kconfig34
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c538
-rw-r--r--arch/blackfin/mach-bf548/include/mach/gpio.h8
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf609/Kconfig42
-rw-r--r--arch/blackfin/mach-bf609/boards/ezkit.c472
-rw-r--r--arch/blackfin/mach-bf609/include/mach/gpio.h8
-rw-r--r--arch/blackfin/mach-bf609/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf609/include/mach/portmux.h4
-rw-r--r--arch/blackfin/mach-common/ints-priority.c421
-rw-r--r--arch/blackfin/mach-common/pm.c22
-rw-r--r--arch/blackfin/mach-common/smp.c12
16 files changed, 1025 insertions, 710 deletions
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig
index 13eb73231a9a..4ca39ab6b2bf 100644
--- a/arch/blackfin/configs/BF609-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF609-EZKIT_defconfig
@@ -102,7 +102,7 @@ CONFIG_I2C_CHARDEV=y
102CONFIG_I2C_BLACKFIN_TWI=y 102CONFIG_I2C_BLACKFIN_TWI=y
103CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 103CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
104CONFIG_SPI=y 104CONFIG_SPI=y
105CONFIG_SPI_BFIN6XX=y 105CONFIG_SPI_BFIN_V3=y
106CONFIG_GPIOLIB=y 106CONFIG_GPIOLIB=y
107CONFIG_GPIO_SYSFS=y 107CONFIG_GPIO_SYSFS=y
108# CONFIG_HWMON is not set 108# CONFIG_HWMON is not set
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 4ae1144a4578..2fd04f10cc26 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -23,8 +23,7 @@
23/* 23/*
24 * pm save bfin pint registers 24 * pm save bfin pint registers
25 */ 25 */
26struct bfin_pm_pint_save { 26struct adi_pm_pint_save {
27 u32 mask_set;
28 u32 assign; 27 u32 assign;
29 u32 edge_set; 28 u32 edge_set;
30 u32 invert_set; 29 u32 invert_set;
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
index 4fbf83575db1..4b2a992794d7 100644
--- a/arch/blackfin/include/asm/irq_handler.h
+++ b/arch/blackfin/include/asm/irq_handler.h
@@ -12,11 +12,11 @@
12#include <mach/irq.h> 12#include <mach/irq.h>
13 13
14/* init functions only */ 14/* init functions only */
15extern int __init init_arch_irq(void); 15extern int init_arch_irq(void);
16extern void init_exception_vectors(void); 16extern void init_exception_vectors(void);
17extern void __init program_IAR(void); 17extern void program_IAR(void);
18#ifdef init_mach_irq 18#ifdef init_mach_irq
19extern void __init init_mach_irq(void); 19extern void init_mach_irq(void);
20#else 20#else
21# define init_mach_irq() 21# define init_mach_irq()
22#endif 22#endif
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index ed978f1c5cb9..a017359c1826 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -11,11 +11,8 @@
11#include <linux/err.h> 11#include <linux/err.h>
12#include <linux/proc_fs.h> 12#include <linux/proc_fs.h>
13#include <linux/seq_file.h> 13#include <linux/seq_file.h>
14#include <asm/blackfin.h> 14#include <linux/gpio.h>
15#include <asm/gpio.h>
16#include <asm/portmux.h>
17#include <linux/irq.h> 15#include <linux/irq.h>
18#include <asm/irq_handler.h>
19 16
20#if ANOMALY_05000311 || ANOMALY_05000323 17#if ANOMALY_05000311 || ANOMALY_05000323
21enum { 18enum {
@@ -58,19 +55,6 @@ static struct gpio_port_t * const gpio_array[] = {
58 (struct gpio_port_t *) FIO0_FLAG_D, 55 (struct gpio_port_t *) FIO0_FLAG_D,
59 (struct gpio_port_t *) FIO1_FLAG_D, 56 (struct gpio_port_t *) FIO1_FLAG_D,
60 (struct gpio_port_t *) FIO2_FLAG_D, 57 (struct gpio_port_t *) FIO2_FLAG_D,
61#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
62 (struct gpio_port_t *)PORTA_FER,
63 (struct gpio_port_t *)PORTB_FER,
64 (struct gpio_port_t *)PORTC_FER,
65 (struct gpio_port_t *)PORTD_FER,
66 (struct gpio_port_t *)PORTE_FER,
67 (struct gpio_port_t *)PORTF_FER,
68 (struct gpio_port_t *)PORTG_FER,
69# if defined(CONFIG_BF54x)
70 (struct gpio_port_t *)PORTH_FER,
71 (struct gpio_port_t *)PORTI_FER,
72 (struct gpio_port_t *)PORTJ_FER,
73# endif
74#else 58#else
75# error no gpio arrays defined 59# error no gpio arrays defined
76#endif 60#endif
@@ -169,12 +153,6 @@ DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
169 153
170inline int check_gpio(unsigned gpio) 154inline int check_gpio(unsigned gpio)
171{ 155{
172#if defined(CONFIG_BF54x)
173 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
174 || gpio == GPIO_PH14 || gpio == GPIO_PH15
175 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
176 return -EINVAL;
177#endif
178 if (gpio >= MAX_BLACKFIN_GPIOS) 156 if (gpio >= MAX_BLACKFIN_GPIOS)
179 return -EINVAL; 157 return -EINVAL;
180 return 0; 158 return 0;
@@ -212,12 +190,6 @@ static void port_setup(unsigned gpio, unsigned short usage)
212 else 190 else
213 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); 191 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
214 SSYNC(); 192 SSYNC();
215#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
216 if (usage == GPIO_USAGE)
217 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
218 else
219 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
220 SSYNC();
221#endif 193#endif
222} 194}
223 195
@@ -255,7 +227,7 @@ static int portmux_group_check(unsigned short per)
255 u16 ident = P_IDENT(per); 227 u16 ident = P_IDENT(per);
256 u16 function = P_FUNCT2MUX(per); 228 u16 function = P_FUNCT2MUX(per);
257 s8 offset = port_mux[ident]; 229 s8 offset = port_mux[ident];
258 u16 m, pmux, pfunc; 230 u16 m, pmux, pfunc, mask;
259 231
260 if (offset < 0) 232 if (offset < 0)
261 return 0; 233 return 0;
@@ -270,10 +242,12 @@ static int portmux_group_check(unsigned short per)
270 continue; 242 continue;
271 243
272 if (offset == 1) 244 if (offset == 1)
273 pfunc = (pmux >> offset) & 3; 245 mask = 3;
274 else 246 else
275 pfunc = (pmux >> offset) & 1; 247 mask = 1;
276 if (pfunc != function) { 248
249 pfunc = (pmux >> offset) & mask;
250 if (pfunc != (function & mask)) {
277 pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n", 251 pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
278 ident, function, m, pfunc); 252 ident, function, m, pfunc);
279 return -EINVAL; 253 return -EINVAL;
@@ -288,43 +262,21 @@ static void portmux_setup(unsigned short per)
288 u16 ident = P_IDENT(per); 262 u16 ident = P_IDENT(per);
289 u16 function = P_FUNCT2MUX(per); 263 u16 function = P_FUNCT2MUX(per);
290 s8 offset = port_mux[ident]; 264 s8 offset = port_mux[ident];
291 u16 pmux; 265 u16 pmux, mask;
292 266
293 if (offset == -1) 267 if (offset == -1)
294 return; 268 return;
295 269
296 pmux = bfin_read_PORT_MUX(); 270 pmux = bfin_read_PORT_MUX();
297 if (offset != 1) 271 if (offset == 1)
298 pmux &= ~(1 << offset); 272 mask = 3;
299 else 273 else
300 pmux &= ~(3 << 1); 274 mask = 1;
301 pmux |= (function << offset);
302 bfin_write_PORT_MUX(pmux);
303}
304#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
305inline void portmux_setup(unsigned short per)
306{
307 u16 ident = P_IDENT(per);
308 u16 function = P_FUNCT2MUX(per);
309 u32 pmux;
310 275
311 pmux = gpio_array[gpio_bank(ident)]->port_mux; 276 pmux &= ~(mask << offset);
277 pmux |= ((function & mask) << offset);
312 278
313 pmux &= ~(0x3 << (2 * gpio_sub_n(ident))); 279 bfin_write_PORT_MUX(pmux);
314 pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
315
316 gpio_array[gpio_bank(ident)]->port_mux = pmux;
317}
318
319inline u16 get_portmux(unsigned short per)
320{
321 u16 ident = P_IDENT(per);
322 u32 pmux = gpio_array[gpio_bank(ident)]->port_mux;
323 return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
324}
325static int portmux_group_check(unsigned short per)
326{
327 return 0;
328} 280}
329#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) 281#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
330static int portmux_group_check(unsigned short per) 282static int portmux_group_check(unsigned short per)
@@ -379,7 +331,6 @@ static int portmux_group_check(unsigned short per)
379} 331}
380#endif 332#endif
381 333
382#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
383/*********************************************************** 334/***********************************************************
384* 335*
385* FUNCTIONS: Blackfin General Purpose Ports Access Functions 336* FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -572,7 +523,7 @@ static const unsigned int sic_iwr_irqs[] = {
572************************************************************* 523*************************************************************
573* MODIFICATION HISTORY : 524* MODIFICATION HISTORY :
574**************************************************************/ 525**************************************************************/
575int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl) 526int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
576{ 527{
577 unsigned long flags; 528 unsigned long flags;
578 529
@@ -591,7 +542,7 @@ int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
591 return 0; 542 return 0;
592} 543}
593 544
594int bfin_pm_standby_ctrl(unsigned ctrl) 545int bfin_gpio_pm_standby_ctrl(unsigned ctrl)
595{ 546{
596 u16 bank, mask, i; 547 u16 bank, mask, i;
597 548
@@ -682,53 +633,6 @@ void bfin_gpio_pm_hibernate_restore(void)
682 633
683 634
684#endif 635#endif
685#else /* CONFIG_BF54x || CONFIG_BF60x */
686#ifdef CONFIG_PM
687
688int bfin_pm_standby_ctrl(unsigned ctrl)
689{
690 return 0;
691}
692
693void bfin_gpio_pm_hibernate_suspend(void)
694{
695 int i, bank;
696
697 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
698 bank = gpio_bank(i);
699
700 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
701 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
702 gpio_bank_saved[bank].data = gpio_array[bank]->data;
703 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
704 gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set;
705 }
706}
707
708void bfin_gpio_pm_hibernate_restore(void)
709{
710 int i, bank;
711
712 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
713 bank = gpio_bank(i);
714
715 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
716 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
717 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
718 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
719 & gpio_bank_saved[bank].dir;
720 gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
721 }
722}
723#endif
724
725unsigned short get_gpio_dir(unsigned gpio)
726{
727 return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
728}
729EXPORT_SYMBOL(get_gpio_dir);
730
731#endif /* CONFIG_BF54x || CONFIG_BF60x */
732 636
733/*********************************************************** 637/***********************************************************
734* 638*
@@ -785,11 +689,7 @@ int peripheral_request(unsigned short per, const char *label)
785 * be requested and used by several drivers 689 * be requested and used by several drivers
786 */ 690 */
787 691
788#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
789 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
790#else
791 if (!(per & P_MAYSHARE)) { 692 if (!(per & P_MAYSHARE)) {
792#endif
793 /* 693 /*
794 * Allow that the identical pin function can 694 * Allow that the identical pin function can
795 * be requested from the same driver twice 695 * be requested from the same driver twice
@@ -938,12 +838,9 @@ int bfin_gpio_request(unsigned gpio, const char *label)
938 if (unlikely(is_reserved(gpio_irq, gpio, 1))) { 838 if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
939 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!" 839 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
940 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio); 840 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
941 } 841 } else { /* Reset POLAR setting when acquiring a gpio for the first time */
942#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
943 else { /* Reset POLAR setting when acquiring a gpio for the first time */
944 set_gpio_polar(gpio, 0); 842 set_gpio_polar(gpio, 0);
945 } 843 }
946#endif
947 844
948 reserve(gpio, gpio); 845 reserve(gpio, gpio);
949 set_label(gpio, label); 846 set_label(gpio, label);
@@ -1112,11 +1009,7 @@ void bfin_gpio_irq_free(unsigned gpio)
1112 1009
1113static inline void __bfin_gpio_direction_input(unsigned gpio) 1010static inline void __bfin_gpio_direction_input(unsigned gpio)
1114{ 1011{
1115#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1116 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
1117#else
1118 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); 1012 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1119#endif
1120 gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio); 1013 gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1121} 1014}
1122 1015
@@ -1140,17 +1033,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_input);
1140 1033
1141void bfin_gpio_irq_prepare(unsigned gpio) 1034void bfin_gpio_irq_prepare(unsigned gpio)
1142{ 1035{
1143#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1144 unsigned long flags;
1145#endif
1146
1147 port_setup(gpio, GPIO_USAGE); 1036 port_setup(gpio, GPIO_USAGE);
1148
1149#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1150 flags = hard_local_irq_save();
1151 __bfin_gpio_direction_input(gpio);
1152 hard_local_irq_restore(flags);
1153#endif
1154} 1037}
1155 1038
1156void bfin_gpio_set_value(unsigned gpio, int arg) 1039void bfin_gpio_set_value(unsigned gpio, int arg)
@@ -1175,11 +1058,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
1175 1058
1176 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); 1059 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1177 gpio_set_value(gpio, value); 1060 gpio_set_value(gpio, value);
1178#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1179 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
1180#else
1181 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio); 1061 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1182#endif
1183 1062
1184 AWA_DUMMY_READ(dir); 1063 AWA_DUMMY_READ(dir);
1185 hard_local_irq_restore(flags); 1064 hard_local_irq_restore(flags);
@@ -1190,9 +1069,6 @@ EXPORT_SYMBOL(bfin_gpio_direction_output);
1190 1069
1191int bfin_gpio_get_value(unsigned gpio) 1070int bfin_gpio_get_value(unsigned gpio)
1192{ 1071{
1193#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1194 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
1195#else
1196 unsigned long flags; 1072 unsigned long flags;
1197 1073
1198 if (unlikely(get_gpio_edge(gpio))) { 1074 if (unlikely(get_gpio_edge(gpio))) {
@@ -1205,7 +1081,6 @@ int bfin_gpio_get_value(unsigned gpio)
1205 return ret; 1081 return ret;
1206 } else 1082 } else
1207 return get_gpio_data(gpio); 1083 return get_gpio_data(gpio);
1208#endif
1209} 1084}
1210EXPORT_SYMBOL(bfin_gpio_get_value); 1085EXPORT_SYMBOL(bfin_gpio_get_value);
1211 1086
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index 94acb586832e..334ec7b12188 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -377,40 +377,6 @@ config IRQ_PINT3
377 377
378endmenu 378endmenu
379 379
380comment "Pin Interrupt to Port Assignment"
381menu "Assignment"
382
383config PINTx_REASSIGN
384 bool "Reprogram PINT Assignment"
385 default y
386 help
387 The interrupt assignment registers controls the pin-to-interrupt
388 assignment in a byte-wide manner. Each option allows you to select
389 a set of pins (High/Low Byte) of an specific Port being mapped
390 to one of the four PIN Interrupts IRQ_PINTx.
391
392 You shouldn't change any of these unless you know exactly what you're doing.
393 Please consult the Blackfin BF54x Processor Hardware Reference Manual.
394
395config PINT0_ASSIGN
396 hex "PINT0_ASSIGN"
397 depends on PINTx_REASSIGN
398 default 0x00000101
399config PINT1_ASSIGN
400 hex "PINT1_ASSIGN"
401 depends on PINTx_REASSIGN
402 default 0x01010000
403config PINT2_ASSIGN
404 hex "PINT2_ASSIGN"
405 depends on PINTx_REASSIGN
406 default 0x07000101
407config PINT3_ASSIGN
408 hex "PINT3_ASSIGN"
409 depends on PINTx_REASSIGN
410 default 0x02020303
411
412endmenu
413
414endmenu 380endmenu
415 381
416endif 382endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 372eb54944ef..d495000b81a0 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -17,6 +17,9 @@
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/usb/musb.h> 19#include <linux/usb/musb.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/platform_data/pinctrl-adi2.h>
20#include <asm/bfin5xx_spi.h> 23#include <asm/bfin5xx_spi.h>
21#include <asm/dma.h> 24#include <asm/dma.h>
22#include <asm/gpio.h> 25#include <asm/gpio.h>
@@ -241,6 +244,13 @@ static struct resource bfin_uart0_resources[] = {
241 .end = UART0_RBR+2, 244 .end = UART0_RBR+2,
242 .flags = IORESOURCE_MEM, 245 .flags = IORESOURCE_MEM,
243 }, 246 },
247#ifdef CONFIG_EARLY_PRINTK
248 {
249 .start = PORTE_FER,
250 .end = PORTE_FER+2,
251 .flags = IORESOURCE_REG,
252 },
253#endif
244 { 254 {
245 .start = IRQ_UART0_TX, 255 .start = IRQ_UART0_TX,
246 .end = IRQ_UART0_TX, 256 .end = IRQ_UART0_TX,
@@ -289,6 +299,13 @@ static struct resource bfin_uart1_resources[] = {
289 .end = UART1_RBR+2, 299 .end = UART1_RBR+2,
290 .flags = IORESOURCE_MEM, 300 .flags = IORESOURCE_MEM,
291 }, 301 },
302#ifdef CONFIG_EARLY_PRINTK
303 {
304 .start = PORTH_FER,
305 .end = PORTH_FER+2,
306 .flags = IORESOURCE_REG,
307 },
308#endif
292 { 309 {
293 .start = IRQ_UART1_TX, 310 .start = IRQ_UART1_TX,
294 .end = IRQ_UART1_TX, 311 .end = IRQ_UART1_TX,
@@ -353,6 +370,13 @@ static struct resource bfin_uart2_resources[] = {
353 .end = UART2_RBR+2, 370 .end = UART2_RBR+2,
354 .flags = IORESOURCE_MEM, 371 .flags = IORESOURCE_MEM,
355 }, 372 },
373#ifdef CONFIG_EARLY_PRINTK
374 {
375 .start = PORTB_FER,
376 .end = PORTB_FER+2,
377 .flags = IORESOURCE_REG,
378 },
379#endif
356 { 380 {
357 .start = IRQ_UART2_TX, 381 .start = IRQ_UART2_TX,
358 .end = IRQ_UART2_TX, 382 .end = IRQ_UART2_TX,
@@ -401,6 +425,13 @@ static struct resource bfin_uart3_resources[] = {
401 .end = UART3_RBR+2, 425 .end = UART3_RBR+2,
402 .flags = IORESOURCE_MEM, 426 .flags = IORESOURCE_MEM,
403 }, 427 },
428#ifdef CONFIG_EARLY_PRINTK
429 {
430 .start = PORTB_FER,
431 .end = PORTB_FER+2,
432 .flags = IORESOURCE_REG,
433 },
434#endif
404 { 435 {
405 .start = IRQ_UART3_TX, 436 .start = IRQ_UART3_TX,
406 .end = IRQ_UART3_TX, 437 .end = IRQ_UART3_TX,
@@ -1058,6 +1089,411 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1058}; 1089};
1059#endif 1090#endif
1060 1091
1092#ifdef CONFIG_PINCTRL_ADI2
1093
1094# define ADI_PINT_DEVNAME "adi-gpio-pint"
1095# define ADI_GPIO_DEVNAME "adi-gpio"
1096# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1097
1098static struct platform_device bfin_pinctrl_device = {
1099 .name = ADI_PINCTRL_DEVNAME,
1100 .id = 0,
1101};
1102
1103static struct resource bfin_pint0_resources[] = {
1104 {
1105 .start = PINT0_MASK_SET,
1106 .end = PINT0_LATCH + 3,
1107 .flags = IORESOURCE_MEM,
1108 },
1109 {
1110 .start = IRQ_PINT0,
1111 .end = IRQ_PINT0,
1112 .flags = IORESOURCE_IRQ,
1113 },
1114};
1115
1116static struct platform_device bfin_pint0_device = {
1117 .name = ADI_PINT_DEVNAME,
1118 .id = 0,
1119 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1120 .resource = bfin_pint0_resources,
1121};
1122
1123static struct resource bfin_pint1_resources[] = {
1124 {
1125 .start = PINT1_MASK_SET,
1126 .end = PINT1_LATCH + 3,
1127 .flags = IORESOURCE_MEM,
1128 },
1129 {
1130 .start = IRQ_PINT1,
1131 .end = IRQ_PINT1,
1132 .flags = IORESOURCE_IRQ,
1133 },
1134};
1135
1136static struct platform_device bfin_pint1_device = {
1137 .name = ADI_PINT_DEVNAME,
1138 .id = 1,
1139 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1140 .resource = bfin_pint1_resources,
1141};
1142
1143static struct resource bfin_pint2_resources[] = {
1144 {
1145 .start = PINT2_MASK_SET,
1146 .end = PINT2_LATCH + 3,
1147 .flags = IORESOURCE_MEM,
1148 },
1149 {
1150 .start = IRQ_PINT2,
1151 .end = IRQ_PINT2,
1152 .flags = IORESOURCE_IRQ,
1153 },
1154};
1155
1156static struct platform_device bfin_pint2_device = {
1157 .name = ADI_PINT_DEVNAME,
1158 .id = 2,
1159 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1160 .resource = bfin_pint2_resources,
1161};
1162
1163static struct resource bfin_pint3_resources[] = {
1164 {
1165 .start = PINT3_MASK_SET,
1166 .end = PINT3_LATCH + 3,
1167 .flags = IORESOURCE_MEM,
1168 },
1169 {
1170 .start = IRQ_PINT3,
1171 .end = IRQ_PINT3,
1172 .flags = IORESOURCE_IRQ,
1173 },
1174};
1175
1176static struct platform_device bfin_pint3_device = {
1177 .name = ADI_PINT_DEVNAME,
1178 .id = 3,
1179 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1180 .resource = bfin_pint3_resources,
1181};
1182
1183static struct resource bfin_gpa_resources[] = {
1184 {
1185 .start = PORTA_FER,
1186 .end = PORTA_MUX + 3,
1187 .flags = IORESOURCE_MEM,
1188 },
1189 { /* optional */
1190 .start = IRQ_PA0,
1191 .end = IRQ_PA0,
1192 .flags = IORESOURCE_IRQ,
1193 },
1194};
1195
1196static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1197 .port_gpio_base = GPIO_PA0, /* Optional */
1198 .port_pin_base = GPIO_PA0,
1199 .port_width = GPIO_BANKSIZE,
1200 .pint_id = 0, /* PINT0 */
1201 .pint_assign = true, /* PINT upper 16 bit */
1202 .pint_map = 0, /* mapping mask in PINT */
1203};
1204
1205static struct platform_device bfin_gpa_device = {
1206 .name = ADI_GPIO_DEVNAME,
1207 .id = 0,
1208 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1209 .resource = bfin_gpa_resources,
1210 .dev = {
1211 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1212 },
1213};
1214
1215static struct resource bfin_gpb_resources[] = {
1216 {
1217 .start = PORTB_FER,
1218 .end = PORTB_MUX + 3,
1219 .flags = IORESOURCE_MEM,
1220 },
1221 {
1222 .start = IRQ_PB0,
1223 .end = IRQ_PB0,
1224 .flags = IORESOURCE_IRQ,
1225 },
1226};
1227
1228static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1229 .port_gpio_base = GPIO_PB0,
1230 .port_pin_base = GPIO_PB0,
1231 .port_width = 15,
1232 .pint_id = 0,
1233 .pint_assign = true,
1234 .pint_map = 1,
1235};
1236
1237static struct platform_device bfin_gpb_device = {
1238 .name = ADI_GPIO_DEVNAME,
1239 .id = 1,
1240 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1241 .resource = bfin_gpb_resources,
1242 .dev = {
1243 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1244 },
1245};
1246
1247static struct resource bfin_gpc_resources[] = {
1248 {
1249 .start = PORTC_FER,
1250 .end = PORTC_MUX + 3,
1251 .flags = IORESOURCE_MEM,
1252 },
1253 {
1254 .start = IRQ_PC0,
1255 .end = IRQ_PC0,
1256 .flags = IORESOURCE_IRQ,
1257 },
1258};
1259
1260static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1261 .port_gpio_base = GPIO_PC0,
1262 .port_pin_base = GPIO_PC0,
1263 .port_width = 14,
1264 .pint_id = 2,
1265 .pint_assign = true,
1266 .pint_map = 0,
1267};
1268
1269static struct platform_device bfin_gpc_device = {
1270 .name = ADI_GPIO_DEVNAME,
1271 .id = 2,
1272 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1273 .resource = bfin_gpc_resources,
1274 .dev = {
1275 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1276 },
1277};
1278
1279static struct resource bfin_gpd_resources[] = {
1280 {
1281 .start = PORTD_FER,
1282 .end = PORTD_MUX + 3,
1283 .flags = IORESOURCE_MEM,
1284 },
1285 {
1286 .start = IRQ_PD0,
1287 .end = IRQ_PD0,
1288 .flags = IORESOURCE_IRQ,
1289 },
1290};
1291
1292static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1293 .port_gpio_base = GPIO_PD0,
1294 .port_pin_base = GPIO_PD0,
1295 .port_width = GPIO_BANKSIZE,
1296 .pint_id = 2,
1297 .pint_assign = false,
1298 .pint_map = 1,
1299};
1300
1301static struct platform_device bfin_gpd_device = {
1302 .name = ADI_GPIO_DEVNAME,
1303 .id = 3,
1304 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1305 .resource = bfin_gpd_resources,
1306 .dev = {
1307 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1308 },
1309};
1310
1311static struct resource bfin_gpe_resources[] = {
1312 {
1313 .start = PORTE_FER,
1314 .end = PORTE_MUX + 3,
1315 .flags = IORESOURCE_MEM,
1316 },
1317 {
1318 .start = IRQ_PE0,
1319 .end = IRQ_PE0,
1320 .flags = IORESOURCE_IRQ,
1321 },
1322};
1323
1324static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1325 .port_gpio_base = GPIO_PE0,
1326 .port_pin_base = GPIO_PE0,
1327 .port_width = GPIO_BANKSIZE,
1328 .pint_id = 3,
1329 .pint_assign = true,
1330 .pint_map = 2,
1331};
1332
1333static struct platform_device bfin_gpe_device = {
1334 .name = ADI_GPIO_DEVNAME,
1335 .id = 4,
1336 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1337 .resource = bfin_gpe_resources,
1338 .dev = {
1339 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1340 },
1341};
1342
1343static struct resource bfin_gpf_resources[] = {
1344 {
1345 .start = PORTF_FER,
1346 .end = PORTF_MUX + 3,
1347 .flags = IORESOURCE_MEM,
1348 },
1349 {
1350 .start = IRQ_PF0,
1351 .end = IRQ_PF0,
1352 .flags = IORESOURCE_IRQ,
1353 },
1354};
1355
1356static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1357 .port_gpio_base = GPIO_PF0,
1358 .port_pin_base = GPIO_PF0,
1359 .port_width = GPIO_BANKSIZE,
1360 .pint_id = 3,
1361 .pint_assign = false,
1362 .pint_map = 3,
1363};
1364
1365static struct platform_device bfin_gpf_device = {
1366 .name = ADI_GPIO_DEVNAME,
1367 .id = 5,
1368 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1369 .resource = bfin_gpf_resources,
1370 .dev = {
1371 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1372 },
1373};
1374
1375static struct resource bfin_gpg_resources[] = {
1376 {
1377 .start = PORTG_FER,
1378 .end = PORTG_MUX + 3,
1379 .flags = IORESOURCE_MEM,
1380 },
1381 {
1382 .start = IRQ_PG0,
1383 .end = IRQ_PG0,
1384 .flags = IORESOURCE_IRQ,
1385 },
1386};
1387
1388static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1389 .port_gpio_base = GPIO_PG0,
1390 .port_pin_base = GPIO_PG0,
1391 .port_width = GPIO_BANKSIZE,
1392 .pint_id = -1,
1393};
1394
1395static struct platform_device bfin_gpg_device = {
1396 .name = ADI_GPIO_DEVNAME,
1397 .id = 6,
1398 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1399 .resource = bfin_gpg_resources,
1400 .dev = {
1401 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1402 },
1403};
1404
1405static struct resource bfin_gph_resources[] = {
1406 {
1407 .start = PORTH_FER,
1408 .end = PORTH_MUX + 3,
1409 .flags = IORESOURCE_MEM,
1410 },
1411 {
1412 .start = IRQ_PH0,
1413 .end = IRQ_PH0,
1414 .flags = IORESOURCE_IRQ,
1415 },
1416};
1417
1418static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = {
1419 .port_gpio_base = GPIO_PH0,
1420 .port_pin_base = GPIO_PH0,
1421 .port_width = 14,
1422 .pint_id = -1,
1423};
1424
1425static struct platform_device bfin_gph_device = {
1426 .name = ADI_GPIO_DEVNAME,
1427 .id = 7,
1428 .num_resources = ARRAY_SIZE(bfin_gph_resources),
1429 .resource = bfin_gph_resources,
1430 .dev = {
1431 .platform_data = &bfin_gph_pdata, /* Passed to driver */
1432 },
1433};
1434
1435static struct resource bfin_gpi_resources[] = {
1436 {
1437 .start = PORTI_FER,
1438 .end = PORTI_MUX + 3,
1439 .flags = IORESOURCE_MEM,
1440 },
1441 {
1442 .start = IRQ_PI0,
1443 .end = IRQ_PI0,
1444 .flags = IORESOURCE_IRQ,
1445 },
1446};
1447
1448static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = {
1449 .port_gpio_base = GPIO_PI0,
1450 .port_pin_base = GPIO_PI0,
1451 .port_width = GPIO_BANKSIZE,
1452 .pint_id = -1,
1453};
1454
1455static struct platform_device bfin_gpi_device = {
1456 .name = ADI_GPIO_DEVNAME,
1457 .id = 8,
1458 .num_resources = ARRAY_SIZE(bfin_gpi_resources),
1459 .resource = bfin_gpi_resources,
1460 .dev = {
1461 .platform_data = &bfin_gpi_pdata, /* Passed to driver */
1462 },
1463};
1464
1465static struct resource bfin_gpj_resources[] = {
1466 {
1467 .start = PORTJ_FER,
1468 .end = PORTJ_MUX + 3,
1469 .flags = IORESOURCE_MEM,
1470 },
1471 {
1472 .start = IRQ_PJ0,
1473 .end = IRQ_PJ0,
1474 .flags = IORESOURCE_IRQ,
1475 },
1476};
1477
1478static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = {
1479 .port_gpio_base = GPIO_PJ0,
1480 .port_pin_base = GPIO_PJ0,
1481 .port_width = 14,
1482 .pint_id = -1,
1483};
1484
1485static struct platform_device bfin_gpj_device = {
1486 .name = ADI_GPIO_DEVNAME,
1487 .id = 9,
1488 .num_resources = ARRAY_SIZE(bfin_gpj_resources),
1489 .resource = bfin_gpj_resources,
1490 .dev = {
1491 .platform_data = &bfin_gpj_pdata, /* Passed to driver */
1492 },
1493};
1494
1495#endif
1496
1061static struct spi_board_info bfin_spi_board_info[] __initdata = { 1497static struct spi_board_info bfin_spi_board_info[] __initdata = {
1062#if defined(CONFIG_MTD_M25P80) \ 1498#if defined(CONFIG_MTD_M25P80) \
1063 || defined(CONFIG_MTD_M25P80_MODULE) 1499 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -1066,7 +1502,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1066 .modalias = "m25p80", /* Name of spi_driver for this device */ 1502 .modalias = "m25p80", /* Name of spi_driver for this device */
1067 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 1503 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1068 .bus_num = 0, /* Framework bus number */ 1504 .bus_num = 0, /* Framework bus number */
1069 .chip_select = 1, /* SPI_SSEL1*/ 1505 .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/
1070 .platform_data = &bfin_spi_flash_data, 1506 .platform_data = &bfin_spi_flash_data,
1071 .controller_data = &spi_flash_chip_info, 1507 .controller_data = &spi_flash_chip_info,
1072 .mode = SPI_MODE_3, 1508 .mode = SPI_MODE_3,
@@ -1078,7 +1514,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1078 .modalias = "ad183x", 1514 .modalias = "ad183x",
1079 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1515 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1080 .bus_num = 1, 1516 .bus_num = 1,
1081 .chip_select = 4, 1517 .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
1082 }, 1518 },
1083#endif 1519#endif
1084#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 1520#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
@@ -1088,7 +1524,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1088 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ 1524 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
1089 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 1525 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1090 .bus_num = 0, 1526 .bus_num = 0,
1091 .chip_select = 2, 1527 .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */
1092 }, 1528 },
1093#endif 1529#endif
1094#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 1530#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1096,7 +1532,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1096 .modalias = "spidev", 1532 .modalias = "spidev",
1097 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1533 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1098 .bus_num = 0, 1534 .bus_num = 0,
1099 .chip_select = 1, 1535 .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */
1100 }, 1536 },
1101#endif 1537#endif
1102#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) 1538#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
@@ -1106,7 +1542,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1106 .irq = IRQ_PC5, 1542 .irq = IRQ_PC5,
1107 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 1543 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1108 .bus_num = 1, 1544 .bus_num = 1,
1109 .chip_select = 2, 1545 .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
1110 .mode = SPI_MODE_3, 1546 .mode = SPI_MODE_3,
1111 }, 1547 },
1112#endif 1548#endif
@@ -1152,7 +1588,7 @@ static struct resource bfin_spi1_resource[] = {
1152 1588
1153/* SPI controller data */ 1589/* SPI controller data */
1154static struct bfin5xx_spi_master bf54x_spi_master_info0 = { 1590static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
1155 .num_chipselect = 4, 1591 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1156 .enable_dma = 1, /* master has the ability to do dma transfer */ 1592 .enable_dma = 1, /* master has the ability to do dma transfer */
1157 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 1593 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1158}; 1594};
@@ -1168,7 +1604,7 @@ static struct platform_device bf54x_spi_master0 = {
1168}; 1604};
1169 1605
1170static struct bfin5xx_spi_master bf54x_spi_master_info1 = { 1606static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
1171 .num_chipselect = 4, 1607 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1172 .enable_dma = 1, /* master has the ability to do dma transfer */ 1608 .enable_dma = 1, /* master has the ability to do dma transfer */
1173 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, 1609 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1174}; 1610};
@@ -1508,6 +1944,23 @@ static struct platform_device bfin_ac97 = {
1508static struct platform_device *ezkit_devices[] __initdata = { 1944static struct platform_device *ezkit_devices[] __initdata = {
1509 1945
1510 &bfin_dpmc, 1946 &bfin_dpmc,
1947#if defined(CONFIG_PINCTRL_ADI2)
1948 &bfin_pinctrl_device,
1949 &bfin_pint0_device,
1950 &bfin_pint1_device,
1951 &bfin_pint2_device,
1952 &bfin_pint3_device,
1953 &bfin_gpa_device,
1954 &bfin_gpb_device,
1955 &bfin_gpc_device,
1956 &bfin_gpd_device,
1957 &bfin_gpe_device,
1958 &bfin_gpf_device,
1959 &bfin_gpg_device,
1960 &bfin_gph_device,
1961 &bfin_gpi_device,
1962 &bfin_gpj_device,
1963#endif
1511 1964
1512#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 1965#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1513 &rtc_device, 1966 &rtc_device,
@@ -1644,10 +2097,66 @@ static struct platform_device *ezkit_devices[] __initdata = {
1644#endif 2097#endif
1645}; 2098};
1646 2099
2100/* Pin control settings */
2101static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2102 /* per-device maps */
2103 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2104 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2105#ifdef CONFIG_BFIN_UART1_CTSRTS
2106 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
2107#endif
2108 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"),
2109 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"),
2110#ifdef CONFIG_BFIN_UART3_CTSRTS
2111 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"),
2112#endif
2113 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2114 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2115 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"),
2116 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"),
2117 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2118 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"),
2119 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"),
2120 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2121#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
2122 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2123#endif
2124 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2125 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2126 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"),
2127 PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2128 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2129 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2130 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"),
2131 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2132 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2133 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"),
2134 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2135 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2136 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"),
2137 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"),
2138 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"),
2139 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"),
2140 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"),
2141 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"),
2142 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"),
2143 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"),
2144 PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"),
2145#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
2146 PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"),
2147#endif
2148 PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"),
2149 PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", NULL, "keys_4x4"),
2150};
2151
1647static int __init ezkit_init(void) 2152static int __init ezkit_init(void)
1648{ 2153{
1649 printk(KERN_INFO "%s(): registering device resources\n", __func__); 2154 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1650 2155
2156 /* Initialize pinmuxing */
2157 pinctrl_register_mappings(bfin_pinmux_map,
2158 ARRAY_SIZE(bfin_pinmux_map));
2159
1651 i2c_register_board_info(0, bfin_i2c_board_info0, 2160 i2c_register_board_info(0, bfin_i2c_board_info0,
1652 ARRAY_SIZE(bfin_i2c_board_info0)); 2161 ARRAY_SIZE(bfin_i2c_board_info0));
1653#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 2162#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
@@ -1679,21 +2188,6 @@ static struct platform_device *ezkit_early_devices[] __initdata = {
1679 &bfin_uart3_device, 2188 &bfin_uart3_device,
1680#endif 2189#endif
1681#endif 2190#endif
1682
1683#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1684#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1685 &bfin_sport0_uart_device,
1686#endif
1687#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1688 &bfin_sport1_uart_device,
1689#endif
1690#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1691 &bfin_sport2_uart_device,
1692#endif
1693#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1694 &bfin_sport3_uart_device,
1695#endif
1696#endif
1697}; 2191};
1698 2192
1699void __init native_machine_early_platform_add_devices(void) 2193void __init native_machine_early_platform_add_devices(void)
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index be9edb28f96b..006da1edcf84 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -194,14 +194,6 @@ struct gpio_port_t {
194 unsigned int port_mux; 194 unsigned int port_mux;
195}; 195};
196 196
197struct gpio_port_s {
198 unsigned short fer;
199 unsigned short data;
200 unsigned short dir;
201 unsigned short inen;
202 unsigned int mux;
203};
204
205#endif 197#endif
206 198
207#include <mach-common/ports-a.h> 199#include <mach-common/ports-a.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 10dc142c518d..cf7cb725cfa2 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -433,7 +433,7 @@
433#include <linux/types.h> 433#include <linux/types.h>
434 434
435/* 435/*
436 * bfin pint registers layout 436 * gpio pint registers layout
437 */ 437 */
438struct bfin_pint_regs { 438struct bfin_pint_regs {
439 u32 mask_set; 439 u32 mask_set;
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
index 2bcbf94b1edf..b0fca44110b0 100644
--- a/arch/blackfin/mach-bf609/Kconfig
+++ b/arch/blackfin/mach-bf609/Kconfig
@@ -9,48 +9,6 @@ source "arch/blackfin/mach-bf609/boards/Kconfig"
9 9
10menu "BF609 Specific Configuration" 10menu "BF609 Specific Configuration"
11 11
12comment "Pin Interrupt to Port Assignment"
13menu "Assignment"
14
15config PINTx_REASSIGN
16 bool "Reprogram PINT Assignment"
17 default y
18 help
19 The interrupt assignment registers controls the pin-to-interrupt
20 assignment in a byte-wide manner. Each option allows you to select
21 a set of pins (High/Low Byte) of an specific Port being mapped
22 to one of the four PIN Interrupts IRQ_PINTx.
23
24 You shouldn't change any of these unless you know exactly what you're doing.
25 Please consult the Blackfin BF60x Processor Hardware Reference Manual.
26
27config PINT0_ASSIGN
28 hex "PINT0_ASSIGN"
29 depends on PINTx_REASSIGN
30 default 0x00000101
31config PINT1_ASSIGN
32 hex "PINT1_ASSIGN"
33 depends on PINTx_REASSIGN
34 default 0x00000101
35config PINT2_ASSIGN
36 hex "PINT2_ASSIGN"
37 depends on PINTx_REASSIGN
38 default 0x00000101
39config PINT3_ASSIGN
40 hex "PINT3_ASSIGN"
41 depends on PINTx_REASSIGN
42 default 0x00000101
43config PINT4_ASSIGN
44 hex "PINT3_ASSIGN"
45 depends on PINTx_REASSIGN
46 default 0x00000101
47config PINT5_ASSIGN
48 hex "PINT3_ASSIGN"
49 depends on PINTx_REASSIGN
50 default 0x00000101
51
52endmenu
53
54config SEC_IRQ_PRIORITY_LEVELS 12config SEC_IRQ_PRIORITY_LEVELS
55 int "SEC interrupt priority levels" 13 int "SEC interrupt priority levels"
56 default 7 14 default 7
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index d56a55ad83a7..82beedd953f6 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -17,6 +17,9 @@
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/usb/musb.h> 19#include <linux/usb/musb.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/platform_data/pinctrl-adi2.h>
20#include <asm/bfin_spi3.h> 23#include <asm/bfin_spi3.h>
21#include <asm/dma.h> 24#include <asm/dma.h>
22#include <asm/gpio.h> 25#include <asm/gpio.h>
@@ -106,8 +109,6 @@ static struct platform_device bfin_rotary_device = {
106#include <linux/stmmac.h> 109#include <linux/stmmac.h>
107#include <linux/phy.h> 110#include <linux/phy.h>
108 111
109static unsigned short pins[] = P_RMII0;
110
111static struct stmmac_mdio_bus_data phy_private_data = { 112static struct stmmac_mdio_bus_data phy_private_data = {
112 .phy_mask = 1, 113 .phy_mask = 1,
113}; 114};
@@ -212,6 +213,18 @@ static struct resource bfin_uart0_resources[] = {
212 .end = UART0_RXDIV+4, 213 .end = UART0_RXDIV+4,
213 .flags = IORESOURCE_MEM, 214 .flags = IORESOURCE_MEM,
214 }, 215 },
216#ifdef CONFIG_EARLY_PRINTK
217 {
218 .start = PORTD_FER,
219 .end = PORTD_FER+2,
220 .flags = IORESOURCE_REG,
221 },
222 {
223 .start = PORTD_MUX,
224 .end = PORTD_MUX+3,
225 .flags = IORESOURCE_REG,
226 },
227#endif
215 { 228 {
216 .start = IRQ_UART0_TX, 229 .start = IRQ_UART0_TX,
217 .end = IRQ_UART0_TX, 230 .end = IRQ_UART0_TX,
@@ -276,6 +289,13 @@ static struct resource bfin_uart1_resources[] = {
276 .end = UART1_RXDIV+4, 289 .end = UART1_RXDIV+4,
277 .flags = IORESOURCE_MEM, 290 .flags = IORESOURCE_MEM,
278 }, 291 },
292#ifdef CONFIG_EARLY_PRINTK
293 {
294 .start = PORTG_FER_SET,
295 .end = PORTG_FER_SET+2,
296 .flags = IORESOURCE_REG,
297 },
298#endif
279 { 299 {
280 .start = IRQ_UART1_TX, 300 .start = IRQ_UART1_TX,
281 .end = IRQ_UART1_TX, 301 .end = IRQ_UART1_TX,
@@ -674,17 +694,12 @@ static struct mtd_partition ezkit_partitions[] = {
674 }, 694 },
675}; 695};
676 696
677int bf609_nor_flash_init(struct platform_device *dev) 697int bf609_nor_flash_init(struct platform_device *pdev)
678{ 698{
679#define CONFIG_SMC_GCTL_VAL 0x00000010 699#define CONFIG_SMC_GCTL_VAL 0x00000010
680 const unsigned short pins[] = {
681 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
682 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
683 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
684 };
685
686 peripheral_request_list(pins, "smc0");
687 700
701 if (!devm_pinctrl_get_select_default(&pdev->dev))
702 return -EBUSY;
688 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL); 703 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
689 bfin_write32(SMC_B0CTL, 0x01002011); 704 bfin_write32(SMC_B0CTL, 0x01002011);
690 bfin_write32(SMC_B0TIM, 0x08170977); 705 bfin_write32(SMC_B0TIM, 0x08170977);
@@ -692,16 +707,9 @@ int bf609_nor_flash_init(struct platform_device *dev)
692 return 0; 707 return 0;
693} 708}
694 709
695void bf609_nor_flash_exit(struct platform_device *dev) 710void bf609_nor_flash_exit(struct platform_device *pdev)
696{ 711{
697 const unsigned short pins[] = { 712 devm_pinctrl_put(pdev->dev.pins->p);
698 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
699 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
700 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
701 };
702
703 peripheral_free_list(pins);
704
705 bfin_write32(SMC_GCTL, 0); 713 bfin_write32(SMC_GCTL, 0);
706} 714}
707 715
@@ -1319,6 +1327,356 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1319}; 1327};
1320#endif 1328#endif
1321 1329
1330#ifdef CONFIG_PINCTRL_ADI2
1331
1332# define ADI_PINT_DEVNAME "adi-gpio-pint"
1333# define ADI_GPIO_DEVNAME "adi-gpio"
1334# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1335
1336static struct platform_device bfin_pinctrl_device = {
1337 .name = ADI_PINCTRL_DEVNAME,
1338 .id = 0,
1339};
1340
1341static struct resource bfin_pint0_resources[] = {
1342 {
1343 .start = PINT0_MASK_SET,
1344 .end = PINT0_LATCH + 3,
1345 .flags = IORESOURCE_MEM,
1346 },
1347 {
1348 .start = IRQ_PINT0,
1349 .end = IRQ_PINT0,
1350 .flags = IORESOURCE_IRQ,
1351 },
1352};
1353
1354static struct platform_device bfin_pint0_device = {
1355 .name = ADI_PINT_DEVNAME,
1356 .id = 0,
1357 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1358 .resource = bfin_pint0_resources,
1359};
1360
1361static struct resource bfin_pint1_resources[] = {
1362 {
1363 .start = PINT1_MASK_SET,
1364 .end = PINT1_LATCH + 3,
1365 .flags = IORESOURCE_MEM,
1366 },
1367 {
1368 .start = IRQ_PINT1,
1369 .end = IRQ_PINT1,
1370 .flags = IORESOURCE_IRQ,
1371 },
1372};
1373
1374static struct platform_device bfin_pint1_device = {
1375 .name = ADI_PINT_DEVNAME,
1376 .id = 1,
1377 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1378 .resource = bfin_pint1_resources,
1379};
1380
1381static struct resource bfin_pint2_resources[] = {
1382 {
1383 .start = PINT2_MASK_SET,
1384 .end = PINT2_LATCH + 3,
1385 .flags = IORESOURCE_MEM,
1386 },
1387 {
1388 .start = IRQ_PINT2,
1389 .end = IRQ_PINT2,
1390 .flags = IORESOURCE_IRQ,
1391 },
1392};
1393
1394static struct platform_device bfin_pint2_device = {
1395 .name = ADI_PINT_DEVNAME,
1396 .id = 2,
1397 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1398 .resource = bfin_pint2_resources,
1399};
1400
1401static struct resource bfin_pint3_resources[] = {
1402 {
1403 .start = PINT3_MASK_SET,
1404 .end = PINT3_LATCH + 3,
1405 .flags = IORESOURCE_MEM,
1406 },
1407 {
1408 .start = IRQ_PINT3,
1409 .end = IRQ_PINT3,
1410 .flags = IORESOURCE_IRQ,
1411 },
1412};
1413
1414static struct platform_device bfin_pint3_device = {
1415 .name = ADI_PINT_DEVNAME,
1416 .id = 3,
1417 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1418 .resource = bfin_pint3_resources,
1419};
1420
1421static struct resource bfin_pint4_resources[] = {
1422 {
1423 .start = PINT4_MASK_SET,
1424 .end = PINT4_LATCH + 3,
1425 .flags = IORESOURCE_MEM,
1426 },
1427 {
1428 .start = IRQ_PINT4,
1429 .end = IRQ_PINT4,
1430 .flags = IORESOURCE_IRQ,
1431 },
1432};
1433
1434static struct platform_device bfin_pint4_device = {
1435 .name = ADI_PINT_DEVNAME,
1436 .id = 4,
1437 .num_resources = ARRAY_SIZE(bfin_pint4_resources),
1438 .resource = bfin_pint4_resources,
1439};
1440
1441static struct resource bfin_pint5_resources[] = {
1442 {
1443 .start = PINT5_MASK_SET,
1444 .end = PINT5_LATCH + 3,
1445 .flags = IORESOURCE_MEM,
1446 },
1447 {
1448 .start = IRQ_PINT5,
1449 .end = IRQ_PINT5,
1450 .flags = IORESOURCE_IRQ,
1451 },
1452};
1453
1454static struct platform_device bfin_pint5_device = {
1455 .name = ADI_PINT_DEVNAME,
1456 .id = 5,
1457 .num_resources = ARRAY_SIZE(bfin_pint5_resources),
1458 .resource = bfin_pint5_resources,
1459};
1460
1461static struct resource bfin_gpa_resources[] = {
1462 {
1463 .start = PORTA_FER,
1464 .end = PORTA_MUX + 3,
1465 .flags = IORESOURCE_MEM,
1466 },
1467 { /* optional */
1468 .start = IRQ_PA0,
1469 .end = IRQ_PA0,
1470 .flags = IORESOURCE_IRQ,
1471 },
1472};
1473
1474static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1475 .port_pin_base = GPIO_PA0,
1476 .port_width = GPIO_BANKSIZE,
1477 .pint_id = 0, /* PINT0 */
1478 .pint_assign = true, /* PINT upper 16 bit */
1479 .pint_map = 0, /* mapping mask in PINT */
1480};
1481
1482static struct platform_device bfin_gpa_device = {
1483 .name = ADI_GPIO_DEVNAME,
1484 .id = 0,
1485 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1486 .resource = bfin_gpa_resources,
1487 .dev = {
1488 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1489 },
1490};
1491
1492static struct resource bfin_gpb_resources[] = {
1493 {
1494 .start = PORTB_FER,
1495 .end = PORTB_MUX + 3,
1496 .flags = IORESOURCE_MEM,
1497 },
1498 {
1499 .start = IRQ_PB0,
1500 .end = IRQ_PB0,
1501 .flags = IORESOURCE_IRQ,
1502 },
1503};
1504
1505static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1506 .port_pin_base = GPIO_PB0,
1507 .port_width = GPIO_BANKSIZE,
1508 .pint_id = 0,
1509 .pint_assign = false,
1510 .pint_map = 1,
1511};
1512
1513static struct platform_device bfin_gpb_device = {
1514 .name = ADI_GPIO_DEVNAME,
1515 .id = 1,
1516 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1517 .resource = bfin_gpb_resources,
1518 .dev = {
1519 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1520 },
1521};
1522
1523static struct resource bfin_gpc_resources[] = {
1524 {
1525 .start = PORTC_FER,
1526 .end = PORTC_MUX + 3,
1527 .flags = IORESOURCE_MEM,
1528 },
1529 {
1530 .start = IRQ_PC0,
1531 .end = IRQ_PC0,
1532 .flags = IORESOURCE_IRQ,
1533 },
1534};
1535
1536static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1537 .port_pin_base = GPIO_PC0,
1538 .port_width = GPIO_BANKSIZE,
1539 .pint_id = 1,
1540 .pint_assign = false,
1541 .pint_map = 1,
1542};
1543
1544static struct platform_device bfin_gpc_device = {
1545 .name = ADI_GPIO_DEVNAME,
1546 .id = 2,
1547 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1548 .resource = bfin_gpc_resources,
1549 .dev = {
1550 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1551 },
1552};
1553
1554static struct resource bfin_gpd_resources[] = {
1555 {
1556 .start = PORTD_FER,
1557 .end = PORTD_MUX + 3,
1558 .flags = IORESOURCE_MEM,
1559 },
1560 {
1561 .start = IRQ_PD0,
1562 .end = IRQ_PD0,
1563 .flags = IORESOURCE_IRQ,
1564 },
1565};
1566
1567static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1568 .port_pin_base = GPIO_PD0,
1569 .port_width = GPIO_BANKSIZE,
1570 .pint_id = 2,
1571 .pint_assign = false,
1572 .pint_map = 1,
1573};
1574
1575static struct platform_device bfin_gpd_device = {
1576 .name = ADI_GPIO_DEVNAME,
1577 .id = 3,
1578 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1579 .resource = bfin_gpd_resources,
1580 .dev = {
1581 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1582 },
1583};
1584
1585static struct resource bfin_gpe_resources[] = {
1586 {
1587 .start = PORTE_FER,
1588 .end = PORTE_MUX + 3,
1589 .flags = IORESOURCE_MEM,
1590 },
1591 {
1592 .start = IRQ_PE0,
1593 .end = IRQ_PE0,
1594 .flags = IORESOURCE_IRQ,
1595 },
1596};
1597
1598static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1599 .port_pin_base = GPIO_PE0,
1600 .port_width = GPIO_BANKSIZE,
1601 .pint_id = 3,
1602 .pint_assign = false,
1603 .pint_map = 1,
1604};
1605
1606static struct platform_device bfin_gpe_device = {
1607 .name = ADI_GPIO_DEVNAME,
1608 .id = 4,
1609 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1610 .resource = bfin_gpe_resources,
1611 .dev = {
1612 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1613 },
1614};
1615
1616static struct resource bfin_gpf_resources[] = {
1617 {
1618 .start = PORTF_FER,
1619 .end = PORTF_MUX + 3,
1620 .flags = IORESOURCE_MEM,
1621 },
1622 {
1623 .start = IRQ_PF0,
1624 .end = IRQ_PF0,
1625 .flags = IORESOURCE_IRQ,
1626 },
1627};
1628
1629static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1630 .port_pin_base = GPIO_PF0,
1631 .port_width = GPIO_BANKSIZE,
1632 .pint_id = 4,
1633 .pint_assign = false,
1634 .pint_map = 1,
1635};
1636
1637static struct platform_device bfin_gpf_device = {
1638 .name = ADI_GPIO_DEVNAME,
1639 .id = 5,
1640 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1641 .resource = bfin_gpf_resources,
1642 .dev = {
1643 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1644 },
1645};
1646
1647static struct resource bfin_gpg_resources[] = {
1648 {
1649 .start = PORTG_FER,
1650 .end = PORTG_MUX + 3,
1651 .flags = IORESOURCE_MEM,
1652 },
1653 {
1654 .start = IRQ_PG0,
1655 .end = IRQ_PG0,
1656 .flags = IORESOURCE_IRQ,
1657 },
1658};
1659
1660static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1661 .port_pin_base = GPIO_PG0,
1662 .port_width = GPIO_BANKSIZE,
1663 .pint_id = 5,
1664 .pint_assign = false,
1665 .pint_map = 1,
1666};
1667
1668static struct platform_device bfin_gpg_device = {
1669 .name = ADI_GPIO_DEVNAME,
1670 .id = 6,
1671 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1672 .resource = bfin_gpg_resources,
1673 .dev = {
1674 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1675 },
1676};
1677
1678#endif
1679
1322#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 1680#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1323#include <linux/input.h> 1681#include <linux/input.h>
1324#include <linux/gpio_keys.h> 1682#include <linux/gpio_keys.h>
@@ -1349,7 +1707,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1349 .modalias = "m25p80", /* Name of spi_driver for this device */ 1707 .modalias = "m25p80", /* Name of spi_driver for this device */
1350 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 1708 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1351 .bus_num = 0, /* Framework bus number */ 1709 .bus_num = 0, /* Framework bus number */
1352 .chip_select = 1, /* SPI_SSEL1*/ 1710 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1353 .platform_data = &bfin_spi_flash_data, 1711 .platform_data = &bfin_spi_flash_data,
1354 .controller_data = &spi_flash_chip_info, 1712 .controller_data = &spi_flash_chip_info,
1355 .mode = SPI_MODE_3, 1713 .mode = SPI_MODE_3,
@@ -1362,7 +1720,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1362 .irq = IRQ_PD9, 1720 .irq = IRQ_PD9,
1363 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 1721 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1364 .bus_num = 0, 1722 .bus_num = 0,
1365 .chip_select = 4, 1723 .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
1366 }, 1724 },
1367#endif 1725#endif
1368#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 1726#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1370,7 +1728,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1370 .modalias = "spidev", 1728 .modalias = "spidev",
1371 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1729 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1372 .bus_num = 0, 1730 .bus_num = 0,
1373 .chip_select = 1, 1731 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1374 .controller_data = &spidev_chip_info, 1732 .controller_data = &spidev_chip_info,
1375 }, 1733 },
1376#endif 1734#endif
@@ -1565,6 +1923,22 @@ static struct platform_device bfin_dpmc = {
1565static struct platform_device *ezkit_devices[] __initdata = { 1923static struct platform_device *ezkit_devices[] __initdata = {
1566 1924
1567 &bfin_dpmc, 1925 &bfin_dpmc,
1926#if defined(CONFIG_PINCTRL_ADI2)
1927 &bfin_pinctrl_device,
1928 &bfin_pint0_device,
1929 &bfin_pint1_device,
1930 &bfin_pint2_device,
1931 &bfin_pint3_device,
1932 &bfin_pint4_device,
1933 &bfin_pint5_device,
1934 &bfin_gpa_device,
1935 &bfin_gpb_device,
1936 &bfin_gpc_device,
1937 &bfin_gpd_device,
1938 &bfin_gpe_device,
1939 &bfin_gpf_device,
1940 &bfin_gpg_device,
1941#endif
1568 1942
1569#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 1943#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1570 &rtc_device, 1944 &rtc_device,
@@ -1681,20 +2055,52 @@ static struct platform_device *ezkit_devices[] __initdata = {
1681 2055
1682}; 2056};
1683 2057
2058/* Pin control settings */
2059static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2060 /* per-device maps */
2061 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2062 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2063 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2064 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2065 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2066 PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
2067 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
2068 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
2069 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2070 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2071 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2072 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2073 PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
2074 PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2075 PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2076#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
2077 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
2078#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
2079 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2080#else
2081 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2082#endif
2083 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2084 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2085 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2086 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2087 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2088 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2089};
2090
1684static int __init ezkit_init(void) 2091static int __init ezkit_init(void)
1685{ 2092{
1686 printk(KERN_INFO "%s(): registering device resources\n", __func__); 2093 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1687 2094
2095 /* Initialize pinmuxing */
2096 pinctrl_register_mappings(bfin_pinmux_map,
2097 ARRAY_SIZE(bfin_pinmux_map));
2098
1688 i2c_register_board_info(0, bfin_i2c_board_info0, 2099 i2c_register_board_info(0, bfin_i2c_board_info0,
1689 ARRAY_SIZE(bfin_i2c_board_info0)); 2100 ARRAY_SIZE(bfin_i2c_board_info0));
1690 i2c_register_board_info(1, bfin_i2c_board_info1, 2101 i2c_register_board_info(1, bfin_i2c_board_info1,
1691 ARRAY_SIZE(bfin_i2c_board_info1)); 2102 ARRAY_SIZE(bfin_i2c_board_info1));
1692 2103
1693#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1694 if (!peripheral_request_list(pins, "emac0"))
1695 printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
1696#endif
1697
1698 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); 2104 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
1699 2105
1700 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 2106 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
@@ -1713,18 +2119,6 @@ static struct platform_device *ezkit_early_devices[] __initdata = {
1713 &bfin_uart1_device, 2119 &bfin_uart1_device,
1714#endif 2120#endif
1715#endif 2121#endif
1716
1717#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1718#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1719 &bfin_sport0_uart_device,
1720#endif
1721#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1722 &bfin_sport1_uart_device,
1723#endif
1724#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1725 &bfin_sport2_uart_device,
1726#endif
1727#endif
1728}; 2122};
1729 2123
1730void __init native_machine_early_platform_add_devices(void) 2124void __init native_machine_early_platform_add_devices(void)
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
index c32c8cc8db2e..07182513e794 100644
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf609/include/mach/gpio.h
@@ -152,14 +152,6 @@ struct gpio_port_t {
152 unsigned long revid; 152 unsigned long revid;
153}; 153};
154 154
155struct gpio_port_s {
156 unsigned short fer;
157 unsigned short data;
158 unsigned short dir;
159 unsigned short inen;
160 unsigned int mux;
161};
162
163#endif 155#endif
164 156
165#include <mach-common/ports-a.h> 157#include <mach-common/ports-a.h>
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
index fa0843d5d77a..d1cb6a86f80a 100644
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ b/arch/blackfin/mach-bf609/include/mach/irq.h
@@ -298,7 +298,7 @@
298extern u8 sec_int_priority[]; 298extern u8 sec_int_priority[];
299 299
300/* 300/*
301 * bfin pint registers layout 301 * gpio pint registers layout
302 */ 302 */
303struct bfin_pint_regs { 303struct bfin_pint_regs {
304 u32 mask_set; 304 u32 mask_set;
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
index fe34191eef0b..c48bb71a55ce 100644
--- a/arch/blackfin/mach-bf609/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf609/include/mach/portmux.h
@@ -19,6 +19,7 @@
19#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) 19#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
20#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) 20#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
21#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) 21#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
22#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
22 23
23#define P_RMII0 {\ 24#define P_RMII0 {\
24 P_MII0_ETxD0, \ 25 P_MII0_ETxD0, \
@@ -30,6 +31,7 @@
30 P_MII0_TxCLK, \ 31 P_MII0_TxCLK, \
31 P_MII0_PHYINT, \ 32 P_MII0_PHYINT, \
32 P_MII0_CRS, \ 33 P_MII0_CRS, \
34 P_MII0_PTPPPS, \
33 P_MII0_MDC, \ 35 P_MII0_MDC, \
34 P_MII0_MDIO, 0} 36 P_MII0_MDIO, 0}
35 37
@@ -44,6 +46,7 @@
44#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) 46#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
45#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) 47#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
46#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) 48#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
49#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
47 50
48#define P_RMII1 {\ 51#define P_RMII1 {\
49 P_MII1_ETxD0, \ 52 P_MII1_ETxD0, \
@@ -55,6 +58,7 @@
55 P_MII1_TxCLK, \ 58 P_MII1_TxCLK, \
56 P_MII1_PHYINT, \ 59 P_MII1_PHYINT, \
57 P_MII1_CRS, \ 60 P_MII1_CRS, \
61 P_MII1_PTPPPS, \
58 P_MII1_MDC, \ 62 P_MII1_MDC, \
59 P_MII1_MDIO, 0} 63 P_MII1_MDIO, 0}
60 64
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index d143fd8d2bc5..ca75613231c8 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -704,10 +704,9 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
704 __irq_set_handler_locked(irq, handle); 704 __irq_set_handler_locked(irq, handle);
705} 705}
706 706
707static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); 707#ifdef CONFIG_GPIO_ADI
708extern void bfin_gpio_irq_prepare(unsigned gpio);
709 708
710#if !BFIN_GPIO_PINT 709static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
711 710
712static void bfin_gpio_ack_irq(struct irq_data *d) 711static void bfin_gpio_ack_irq(struct irq_data *d)
713{ 712{
@@ -821,15 +820,6 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
821 return 0; 820 return 0;
822} 821}
823 822
824#ifdef CONFIG_PM
825static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
826{
827 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
828}
829#else
830# define bfin_gpio_set_wake NULL
831#endif
832
833static void bfin_demux_gpio_block(unsigned int irq) 823static void bfin_demux_gpio_block(unsigned int irq)
834{ 824{
835 unsigned int gpio, mask; 825 unsigned int gpio, mask;
@@ -896,279 +886,40 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
896 bfin_demux_gpio_block(irq); 886 bfin_demux_gpio_block(irq);
897} 887}
898 888
899#else
900
901#define NR_PINT_BITS 32
902#define IRQ_NOT_AVAIL 0xFF
903
904#define PINT_2_BANK(x) ((x) >> 5)
905#define PINT_2_BIT(x) ((x) & 0x1F)
906#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
907
908static unsigned char irq2pint_lut[NR_PINTS];
909static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
910
911static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
912 (struct bfin_pint_regs *)PINT0_MASK_SET,
913 (struct bfin_pint_regs *)PINT1_MASK_SET,
914 (struct bfin_pint_regs *)PINT2_MASK_SET,
915 (struct bfin_pint_regs *)PINT3_MASK_SET,
916#ifdef CONFIG_BF60x
917 (struct bfin_pint_regs *)PINT4_MASK_SET,
918 (struct bfin_pint_regs *)PINT5_MASK_SET,
919#endif
920};
921
922inline unsigned int get_irq_base(u32 bank, u8 bmap)
923{
924 unsigned int irq_base;
925
926#ifndef CONFIG_BF60x
927 if (bank < 2) { /*PA-PB */
928 irq_base = IRQ_PA0 + bmap * 16;
929 } else { /*PC-PJ */
930 irq_base = IRQ_PC0 + bmap * 16;
931 }
932#else
933 irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
934#endif
935 return irq_base;
936}
937
938 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
939void init_pint_lut(void)
940{
941 u16 bank, bit, irq_base, bit_pos;
942 u32 pint_assign;
943 u8 bmap;
944
945 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
946
947 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
948
949 pint_assign = pint[bank]->assign;
950
951 for (bit = 0; bit < NR_PINT_BITS; bit++) {
952
953 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
954
955 irq_base = get_irq_base(bank, bmap);
956
957 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
958 bit_pos = bit + bank * NR_PINT_BITS;
959
960 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
961 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
962 }
963 }
964}
965
966static void bfin_gpio_ack_irq(struct irq_data *d)
967{
968 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
969 u32 pintbit = PINT_BIT(pint_val);
970 u32 bank = PINT_2_BANK(pint_val);
971
972 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
973 if (pint[bank]->invert_set & pintbit)
974 pint[bank]->invert_clear = pintbit;
975 else
976 pint[bank]->invert_set = pintbit;
977 }
978 pint[bank]->request = pintbit;
979
980}
981
982static void bfin_gpio_mask_ack_irq(struct irq_data *d)
983{
984 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
985 u32 pintbit = PINT_BIT(pint_val);
986 u32 bank = PINT_2_BANK(pint_val);
987
988 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
989 if (pint[bank]->invert_set & pintbit)
990 pint[bank]->invert_clear = pintbit;
991 else
992 pint[bank]->invert_set = pintbit;
993 }
994
995 pint[bank]->request = pintbit;
996 pint[bank]->mask_clear = pintbit;
997}
998
999static void bfin_gpio_mask_irq(struct irq_data *d)
1000{
1001 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1002
1003 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
1004}
1005
1006static void bfin_gpio_unmask_irq(struct irq_data *d)
1007{
1008 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1009 u32 pintbit = PINT_BIT(pint_val);
1010 u32 bank = PINT_2_BANK(pint_val);
1011
1012 pint[bank]->mask_set = pintbit;
1013}
1014
1015static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
1016{
1017 unsigned int irq = d->irq;
1018 u32 gpionr = irq_to_gpio(irq);
1019 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1020
1021 if (pint_val == IRQ_NOT_AVAIL) {
1022 printk(KERN_ERR
1023 "GPIO IRQ %d :Not in PINT Assign table "
1024 "Reconfigure Interrupt to Port Assignemt\n", irq);
1025 return -ENODEV;
1026 }
1027
1028 if (__test_and_set_bit(gpionr, gpio_enabled))
1029 bfin_gpio_irq_prepare(gpionr);
1030
1031 bfin_gpio_unmask_irq(d);
1032
1033 return 0;
1034}
1035
1036static void bfin_gpio_irq_shutdown(struct irq_data *d)
1037{
1038 u32 gpionr = irq_to_gpio(d->irq);
1039
1040 bfin_gpio_mask_irq(d);
1041 __clear_bit(gpionr, gpio_enabled);
1042 bfin_gpio_irq_free(gpionr);
1043}
1044
1045static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
1046{
1047 unsigned int irq = d->irq;
1048 int ret;
1049 char buf[16];
1050 u32 gpionr = irq_to_gpio(irq);
1051 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1052 u32 pintbit = PINT_BIT(pint_val);
1053 u32 bank = PINT_2_BANK(pint_val);
1054
1055 if (pint_val == IRQ_NOT_AVAIL)
1056 return -ENODEV;
1057
1058 if (type == IRQ_TYPE_PROBE) {
1059 /* only probe unenabled GPIO interrupt lines */
1060 if (test_bit(gpionr, gpio_enabled))
1061 return 0;
1062 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1063 }
1064
1065 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
1066 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1067
1068 snprintf(buf, 16, "gpio-irq%d", irq);
1069 ret = bfin_gpio_irq_request(gpionr, buf);
1070 if (ret)
1071 return ret;
1072
1073 if (__test_and_set_bit(gpionr, gpio_enabled))
1074 bfin_gpio_irq_prepare(gpionr);
1075
1076 } else {
1077 __clear_bit(gpionr, gpio_enabled);
1078 return 0;
1079 }
1080
1081 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
1082 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
1083 else
1084 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
1085
1086 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1087 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1088 if (gpio_get_value(gpionr))
1089 pint[bank]->invert_set = pintbit;
1090 else
1091 pint[bank]->invert_clear = pintbit;
1092 }
1093
1094 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1095 pint[bank]->edge_set = pintbit;
1096 bfin_set_irq_handler(irq, handle_edge_irq);
1097 } else {
1098 pint[bank]->edge_clear = pintbit;
1099 bfin_set_irq_handler(irq, handle_level_irq);
1100 }
1101
1102 return 0;
1103}
1104
1105#ifdef CONFIG_PM 889#ifdef CONFIG_PM
1106static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
1107static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
1108 890
1109static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) 891static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1110{ 892{
1111 u32 pint_irq; 893 return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
1112 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; 894}
1113 u32 bank = PINT_2_BANK(pint_val);
1114
1115 switch (bank) {
1116 case 0:
1117 pint_irq = IRQ_PINT0;
1118 break;
1119 case 2:
1120 pint_irq = IRQ_PINT2;
1121 break;
1122 case 3:
1123 pint_irq = IRQ_PINT3;
1124 break;
1125 case 1:
1126 pint_irq = IRQ_PINT1;
1127 break;
1128#ifdef CONFIG_BF60x
1129 case 4:
1130 pint_irq = IRQ_PINT4;
1131 break;
1132 case 5:
1133 pint_irq = IRQ_PINT5;
1134 break;
1135#endif
1136 default:
1137 return -EINVAL;
1138 }
1139 895
1140#ifndef SEC_GCTL 896#else
1141 bfin_internal_set_wake(pint_irq, state);
1142#endif
1143 897
1144 return 0; 898# define bfin_gpio_set_wake NULL
1145}
1146 899
1147void bfin_pint_suspend(void) 900#endif
1148{
1149 u32 bank;
1150 901
1151 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { 902static struct irq_chip bfin_gpio_irqchip = {
1152 save_pint_reg[bank].mask_set = pint[bank]->mask_set; 903 .name = "GPIO",
1153 save_pint_reg[bank].assign = pint[bank]->assign; 904 .irq_ack = bfin_gpio_ack_irq,
1154 save_pint_reg[bank].edge_set = pint[bank]->edge_set; 905 .irq_mask = bfin_gpio_mask_irq,
1155 save_pint_reg[bank].invert_set = pint[bank]->invert_set; 906 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1156 } 907 .irq_unmask = bfin_gpio_unmask_irq,
1157} 908 .irq_disable = bfin_gpio_mask_irq,
909 .irq_enable = bfin_gpio_unmask_irq,
910 .irq_set_type = bfin_gpio_irq_type,
911 .irq_startup = bfin_gpio_irq_startup,
912 .irq_shutdown = bfin_gpio_irq_shutdown,
913 .irq_set_wake = bfin_gpio_set_wake,
914};
1158 915
1159void bfin_pint_resume(void) 916#endif
1160{
1161 u32 bank;
1162 917
1163 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { 918#ifdef CONFIG_PM
1164 pint[bank]->mask_set = save_pint_reg[bank].mask_set;
1165 pint[bank]->assign = save_pint_reg[bank].assign;
1166 pint[bank]->edge_set = save_pint_reg[bank].edge_set;
1167 pint[bank]->invert_set = save_pint_reg[bank].invert_set;
1168 }
1169}
1170 919
1171#ifdef SEC_GCTL 920#ifdef SEC_GCTL
921static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
922
1172static int sec_suspend(void) 923static int sec_suspend(void)
1173{ 924{
1174 u32 bank; 925 u32 bank;
@@ -1195,92 +946,10 @@ static struct syscore_ops sec_pm_syscore_ops = {
1195 .suspend = sec_suspend, 946 .suspend = sec_suspend,
1196 .resume = sec_resume, 947 .resume = sec_resume,
1197}; 948};
1198
1199#endif
1200#else
1201# define bfin_gpio_set_wake NULL
1202#endif
1203
1204void bfin_demux_gpio_irq(unsigned int inta_irq,
1205 struct irq_desc *desc)
1206{
1207 u32 bank, pint_val;
1208 u32 request, irq;
1209 u32 level_mask;
1210 int umask = 0;
1211 struct irq_chip *chip = irq_desc_get_chip(desc);
1212
1213 if (chip->irq_mask_ack) {
1214 chip->irq_mask_ack(&desc->irq_data);
1215 } else {
1216 chip->irq_mask(&desc->irq_data);
1217 if (chip->irq_ack)
1218 chip->irq_ack(&desc->irq_data);
1219 }
1220
1221 switch (inta_irq) {
1222 case IRQ_PINT0:
1223 bank = 0;
1224 break;
1225 case IRQ_PINT2:
1226 bank = 2;
1227 break;
1228 case IRQ_PINT3:
1229 bank = 3;
1230 break;
1231 case IRQ_PINT1:
1232 bank = 1;
1233 break;
1234#ifdef CONFIG_BF60x
1235 case IRQ_PINT4:
1236 bank = 4;
1237 break;
1238 case IRQ_PINT5:
1239 bank = 5;
1240 break;
1241#endif 949#endif
1242 default:
1243 return;
1244 }
1245
1246 pint_val = bank * NR_PINT_BITS;
1247
1248 request = pint[bank]->request;
1249
1250 level_mask = pint[bank]->edge_set & request;
1251
1252 while (request) {
1253 if (request & 1) {
1254 irq = pint2irq_lut[pint_val] + SYS_IRQS;
1255 if (level_mask & PINT_BIT(pint_val)) {
1256 umask = 1;
1257 chip->irq_unmask(&desc->irq_data);
1258 }
1259 bfin_handle_irq(irq);
1260 }
1261 pint_val++;
1262 request >>= 1;
1263 }
1264 950
1265 if (!umask)
1266 chip->irq_unmask(&desc->irq_data);
1267}
1268#endif 951#endif
1269 952
1270static struct irq_chip bfin_gpio_irqchip = {
1271 .name = "GPIO",
1272 .irq_ack = bfin_gpio_ack_irq,
1273 .irq_mask = bfin_gpio_mask_irq,
1274 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1275 .irq_unmask = bfin_gpio_unmask_irq,
1276 .irq_disable = bfin_gpio_mask_irq,
1277 .irq_enable = bfin_gpio_unmask_irq,
1278 .irq_set_type = bfin_gpio_irq_type,
1279 .irq_startup = bfin_gpio_irq_startup,
1280 .irq_shutdown = bfin_gpio_irq_shutdown,
1281 .irq_set_wake = bfin_gpio_set_wake,
1282};
1283
1284void init_exception_vectors(void) 953void init_exception_vectors(void)
1285{ 954{
1286 /* cannot program in software: 955 /* cannot program in software:
@@ -1331,17 +1000,6 @@ int __init init_arch_irq(void)
1331 1000
1332 local_irq_disable(); 1001 local_irq_disable();
1333 1002
1334#if BFIN_GPIO_PINT
1335# ifdef CONFIG_PINTx_REASSIGN
1336 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1337 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1338 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1339 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1340# endif
1341 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1342 init_pint_lut();
1343#endif
1344
1345 for (irq = 0; irq <= SYS_IRQS; irq++) { 1003 for (irq = 0; irq <= SYS_IRQS; irq++) {
1346 if (irq <= IRQ_CORETMR) 1004 if (irq <= IRQ_CORETMR)
1347 irq_set_chip(irq, &bfin_core_irqchip); 1005 irq_set_chip(irq, &bfin_core_irqchip);
@@ -1349,12 +1007,8 @@ int __init init_arch_irq(void)
1349 irq_set_chip(irq, &bfin_internal_irqchip); 1007 irq_set_chip(irq, &bfin_internal_irqchip);
1350 1008
1351 switch (irq) { 1009 switch (irq) {
1352#if BFIN_GPIO_PINT 1010#if !BFIN_GPIO_PINT
1353 case IRQ_PINT0: 1011#if defined(BF537_FAMILY)
1354 case IRQ_PINT1:
1355 case IRQ_PINT2:
1356 case IRQ_PINT3:
1357#elif defined(BF537_FAMILY)
1358 case IRQ_PH_INTA_MAC_RX: 1012 case IRQ_PH_INTA_MAC_RX:
1359 case IRQ_PF_INTA_PG_INTA: 1013 case IRQ_PF_INTA_PG_INTA:
1360#elif defined(BF533_FAMILY) 1014#elif defined(BF533_FAMILY)
@@ -1372,6 +1026,7 @@ int __init init_arch_irq(void)
1372#endif 1026#endif
1373 irq_set_chained_handler(irq, bfin_demux_gpio_irq); 1027 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1374 break; 1028 break;
1029#endif
1375#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1030#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1376 case IRQ_MAC_ERROR: 1031 case IRQ_MAC_ERROR:
1377 irq_set_chained_handler(irq, 1032 irq_set_chained_handler(irq,
@@ -1419,10 +1074,12 @@ int __init init_arch_irq(void)
1419 handle_level_irq); 1074 handle_level_irq);
1420#endif 1075#endif
1421 /* if configured as edge, then will be changed to do_edge_IRQ */ 1076 /* if configured as edge, then will be changed to do_edge_IRQ */
1077#ifdef CONFIG_GPIO_ADI
1422 for (irq = GPIO_IRQ_BASE; 1078 for (irq = GPIO_IRQ_BASE;
1423 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) 1079 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1424 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, 1080 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1425 handle_level_irq); 1081 handle_level_irq);
1082#endif
1426 bfin_write_IMASK(0); 1083 bfin_write_IMASK(0);
1427 CSYNC(); 1084 CSYNC();
1428 ilat = bfin_read_ILAT(); 1085 ilat = bfin_read_ILAT();
@@ -1525,19 +1182,6 @@ int __init init_arch_irq(void)
1525 1182
1526 local_irq_disable(); 1183 local_irq_disable();
1527 1184
1528#if BFIN_GPIO_PINT
1529# ifdef CONFIG_PINTx_REASSIGN
1530 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1531 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1532 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1533 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1534 pint[4]->assign = CONFIG_PINT4_ASSIGN;
1535 pint[5]->assign = CONFIG_PINT5_ASSIGN;
1536# endif
1537 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1538 init_pint_lut();
1539#endif
1540
1541 for (irq = 0; irq <= SYS_IRQS; irq++) { 1185 for (irq = 0; irq <= SYS_IRQS; irq++) {
1542 if (irq <= IRQ_CORETMR) { 1186 if (irq <= IRQ_CORETMR) {
1543 irq_set_chip_and_handler(irq, &bfin_core_irqchip, 1187 irq_set_chip_and_handler(irq, &bfin_core_irqchip,
@@ -1546,9 +1190,6 @@ int __init init_arch_irq(void)
1546 if (irq == IRQ_CORETMR) 1190 if (irq == IRQ_CORETMR)
1547 irq_set_handler(irq, handle_percpu_irq); 1191 irq_set_handler(irq, handle_percpu_irq);
1548#endif 1192#endif
1549 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1550 irq_set_chip(irq, &bfin_sec_irqchip);
1551 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1552 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { 1193 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1553 irq_set_chip_and_handler(irq, &bfin_sec_irqchip, 1194 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1554 handle_percpu_irq); 1195 handle_percpu_irq);
@@ -1563,10 +1204,6 @@ int __init init_arch_irq(void)
1563 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); 1204 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1564 } 1205 }
1565 } 1206 }
1566 for (irq = GPIO_IRQ_BASE;
1567 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1568 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1569 handle_level_irq);
1570 1207
1571 bfin_write_IMASK(0); 1208 bfin_write_IMASK(0);
1572 CSYNC(); 1209 CSYNC();
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 87bfe549ad3f..1387a94bcfd5 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -27,7 +27,7 @@ struct bfin_cpu_pm_fns *bfin_cpu_pm;
27 27
28void bfin_pm_suspend_standby_enter(void) 28void bfin_pm_suspend_standby_enter(void)
29{ 29{
30#ifndef CONFIG_BF60x 30#if !BFIN_GPIO_PINT
31 bfin_pm_standby_setup(); 31 bfin_pm_standby_setup();
32#endif 32#endif
33 33
@@ -41,7 +41,7 @@ void bfin_pm_suspend_standby_enter(void)
41# endif 41# endif
42#endif 42#endif
43 43
44#ifndef CONFIG_BF60x 44#if !BFIN_GPIO_PINT
45 bfin_pm_standby_restore(); 45 bfin_pm_standby_restore();
46#endif 46#endif
47 47
@@ -128,6 +128,7 @@ static void flushinv_all_dcache(void)
128 if ((status & 0x3) != 0x3) 128 if ((status & 0x3) != 0x3)
129 continue; 129 continue;
130 130
131
131 /* construct the address using the tag */ 132 /* construct the address using the tag */
132 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5); 133 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
133 134
@@ -140,11 +141,14 @@ static void flushinv_all_dcache(void)
140 141
141int bfin_pm_suspend_mem_enter(void) 142int bfin_pm_suspend_mem_enter(void)
142{ 143{
143 int wakeup, ret; 144 int ret;
145#ifndef CONFIG_BF60x
146 int wakeup;
147#endif
144 148
145 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH 149 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
146 + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH, 150 + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
147 GFP_KERNEL); 151 GFP_ATOMIC);
148 152
149 if (memptr == NULL) { 153 if (memptr == NULL) {
150 panic("bf53x_suspend_l1_mem malloc failed"); 154 panic("bf53x_suspend_l1_mem malloc failed");
@@ -170,10 +174,8 @@ int bfin_pm_suspend_mem_enter(void)
170 return ret; 174 return ret;
171 } 175 }
172 176
177#ifdef CONFIG_GPIO_ADI
173 bfin_gpio_pm_hibernate_suspend(); 178 bfin_gpio_pm_hibernate_suspend();
174
175#if BFIN_GPIO_PINT
176 bfin_pint_suspend();
177#endif 179#endif
178 180
179#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) 181#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
@@ -194,11 +196,9 @@ int bfin_pm_suspend_mem_enter(void)
194 _enable_icplb(); 196 _enable_icplb();
195 _enable_dcplb(); 197 _enable_dcplb();
196 198
197#if BFIN_GPIO_PINT 199#ifdef CONFIG_GPIO_ADI
198 bfin_pint_resume();
199#endif
200
201 bfin_gpio_pm_hibernate_restore(); 200 bfin_gpio_pm_hibernate_restore();
201#endif
202 blackfin_dma_resume(); 202 blackfin_dma_resume();
203 203
204 kfree(memptr); 204 kfree(memptr);
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 82f301c117a5..2bbae0783819 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -146,6 +146,7 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
146 146
147 platform_clear_ipi(cpu, IRQ_SUPPLE_1); 147 platform_clear_ipi(cpu, IRQ_SUPPLE_1);
148 148
149 smp_rmb();
149 bfin_ipi_data = &__get_cpu_var(bfin_ipi); 150 bfin_ipi_data = &__get_cpu_var(bfin_ipi);
150 while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) { 151 while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
151 msg = 0; 152 msg = 0;
@@ -161,18 +162,20 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
161 case BFIN_IPI_CALL_FUNC: 162 case BFIN_IPI_CALL_FUNC:
162 generic_smp_call_function_interrupt(); 163 generic_smp_call_function_interrupt();
163 break; 164 break;
164
165 case BFIN_IPI_CALL_FUNC_SINGLE: 165 case BFIN_IPI_CALL_FUNC_SINGLE:
166 generic_smp_call_function_single_interrupt(); 166 generic_smp_call_function_single_interrupt();
167 break; 167 break;
168
169 case BFIN_IPI_CPU_STOP: 168 case BFIN_IPI_CPU_STOP:
170 ipi_cpu_stop(cpu); 169 ipi_cpu_stop(cpu);
171 break; 170 break;
171 default:
172 goto out;
172 } 173 }
173 atomic_dec(&bfin_ipi_data->count); 174 atomic_dec(&bfin_ipi_data->count);
174 } while (msg < BITS_PER_LONG); 175 } while (msg < BITS_PER_LONG);
176
175 } 177 }
178out:
176 return IRQ_HANDLED; 179 return IRQ_HANDLED;
177} 180}
178 181
@@ -198,10 +201,11 @@ void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
198 bfin_ipi_data = &per_cpu(bfin_ipi, cpu); 201 bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
199 atomic_set_mask((1 << msg), &bfin_ipi_data->bits); 202 atomic_set_mask((1 << msg), &bfin_ipi_data->bits);
200 atomic_inc(&bfin_ipi_data->count); 203 atomic_inc(&bfin_ipi_data->count);
201 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
202 } 204 }
203
204 local_irq_restore(flags); 205 local_irq_restore(flags);
206 smp_wmb();
207 for_each_cpu(cpu, cpumask)
208 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
205} 209}
206 210
207void arch_send_call_function_single_ipi(int cpu) 211void arch_send_call_function_single_ipi(int cpu)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-21 22:51:03 -0400