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authorArnd Bergmann <arnd@arndb.de>2014-11-28 09:01:57 -0500
committerArnd Bergmann <arnd@arndb.de>2014-11-28 09:01:57 -0500
commit6b7f0570b1f0a7f65d90d6b5d4ddf84c2a13e91b (patch)
treef685bc0bda07a9036f76c4e9c342eacb6354fe8a
parentea4409cc44e8f0f36182fcc22eb48b15ed61dd16 (diff)
parent96acf9dfe1ba59e99eafcf26478118edd195d924 (diff)
Merge tag 'imx-dt-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Pull "The i.MX device tree changes for 3.19" from Shawn Guo: - Device additions for board vf610-colibri, pwm, backlight, I2C, RTC, ADC etc. - Update i.MX6 phyFLEX board to include PCIe, CAN and audio support - Improve SSI clocks description for i.MX5 platforms - Add ENET2 support for imx6sx-sdb board - Add device tree source for LS1021A SoC, board QDS and TWR - Enable cpufreq support for i.MX53 - Enable VPU device support for i.MX6QDL - Enable poweroff support for i.MX6 SoCs - Add support for TBS2910 Matrix ARM mini PC which is built on i.MX6Q - Create generic base device trees for Vybrid and add support for Colibri VF50 Note: the change set is built on top of imx-soc-3.19 to resolve the dependency that "ARM: dts: imx53: add cpufreq-dt support" uses the clock define IMX5_CLK_ARM that is added by "ARM: imx53: clk: add ARM clock". * tag 'imx-dt-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (51 commits) ARM: dts: imx6q-tbs2910: Enable snvs-poweroff ARM: dts: imx6: add pm_power_off support for i.mx6 chips ARM: dts: vf-colibri: add USB regulators ARM: dts: imx6: phyFLEX: Add CAN support ARM: dts: imx6: phyFLEX: Add PCIe ARM: dts: imx6: phyFLEX: Set correct interrupt for pmic ARM: dts: imx6: phyFLEX: Enable gpmi in module file ARM: dts: imx6: phyFLEX: set nodes in alphabetical order ARM: dts: vf-colibri-eval-v3.dts: Enable ST-M41T0M6 RTC ARM: dts: vf-colibri: Add I2C support ARM: dts: imx6qdl: Enable CODA960 VPU ARM: dts: imx6q-tbs2910: Remove unneeded 'fsl,mode' property ARM: dts: vf610: enable USB misc/phy nodes where necessary ARM: dts: vf610: use new GPIO support ARM: dts: pbab01: enable I2S audio on phyFLEX-i.MX6 boards ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02 ARM: dts: vf500-colibri: add Colibri VF50 support ARM: dts: vf610: create generic base device trees ARM: dts: vf610: assign oscillator to clock module dt-bindings: arm: add Freescale LS1021A SoC device tree binding ... Signed-off-by; Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt38
-rw-r--r--Documentation/devicetree/bindings/clock/vf610-clock.txt15
-rw-r--r--Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt23
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt1
-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/imx51.dtsi12
-rw-r--r--arch/arm/boot/dts/imx53.dtsi25
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6q-tbs2910.dts432
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi131
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi97
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi14
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts4
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi6
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts66
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi8
-rw-r--r--arch/arm/boot/dts/ls1021a-qds.dts240
-rw-r--r--arch/arm/boot/dts/ls1021a-twr.dts127
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi408
-rw-r--r--arch/arm/boot/dts/vf-colibri-eval-v3.dtsi96
-rw-r--r--arch/arm/boot/dts/vf-colibri.dtsi186
-rw-r--r--arch/arm/boot/dts/vf500-colibri-eval-v3.dts17
-rw-r--r--arch/arm/boot/dts/vf500-colibri.dtsi20
-rw-r--r--arch/arm/boot/dts/vf500.dtsi171
-rw-r--r--arch/arm/boot/dts/vf610-colibri-eval-v3.dts33
-rw-r--r--arch/arm/boot/dts/vf610-colibri.dtsi100
-rw-r--r--arch/arm/boot/dts/vf610-cosmic.dts14
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts46
-rw-r--r--arch/arm/boot/dts/vf610.dtsi486
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi437
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig1
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig1
-rw-r--r--arch/arm/mach-imx/Kconfig31
-rw-r--r--arch/arm/mach-imx/Makefile6
-rw-r--r--arch/arm/mach-imx/anatop.c34
-rw-r--r--arch/arm/mach-imx/clk-cpu.c107
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c14
-rw-r--r--arch/arm/mach-imx/clk-vf610.c153
-rw-r--r--arch/arm/mach-imx/clk.h4
-rw-r--r--arch/arm/mach-imx/common.h2
-rw-r--r--arch/arm/mach-imx/mach-imx53.c2
-rw-r--r--arch/arm/mach-imx/mach-imx6sx.c51
-rw-r--r--arch/arm/mach-imx/mach-ls1021a.c22
-rw-r--r--arch/arm/mach-imx/mmdc.c17
-rw-r--r--arch/arm/mach-imx/mxc.h2
-rw-r--r--arch/arm/mach-imx/platsmp.c33
-rw-r--r--arch/arm/mach-imx/pm-imx6.c10
-rw-r--r--arch/arm/mach-imx/suspend-imx6.S14
-rw-r--r--drivers/power/reset/Kconfig9
-rw-r--r--drivers/power/reset/Makefile1
-rw-r--r--drivers/power/reset/imx-snvs-poweroff.c66
-rw-r--r--include/dt-bindings/clock/imx5-clock.h5
-rw-r--r--include/dt-bindings/clock/vf610-clock.h39
-rw-r--r--include/linux/mfd/syscon/imx6q-iomuxc-gpr.h39
56 files changed, 3190 insertions, 746 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index e935d7d4ac43..4e8b7df7fc62 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -74,3 +74,41 @@ Required root node properties:
74i.MX6q generic board 74i.MX6q generic board
75Required root node properties: 75Required root node properties:
76 - compatible = "fsl,imx6q"; 76 - compatible = "fsl,imx6q";
77
78
79Freescale LS1021A Platform Device Tree Bindings
80------------------------------------------------
81
82Required root node compatible properties:
83 - compatible = "fsl,ls1021a";
84
85Freescale LS1021A SoC-specific Device Tree Bindings
86-------------------------------------------
87
88Freescale SCFG
89 SCFG is the supplemental configuration unit, that provides SoC specific
90configuration and status registers for the chip. Such as getting PEX port
91status.
92 Required properties:
93 - compatible: should be "fsl,ls1021a-scfg"
94 - reg: should contain base address and length of SCFG memory-mapped registers
95
96Example:
97 scfg: scfg@1570000 {
98 compatible = "fsl,ls1021a-scfg";
99 reg = <0x0 0x1570000 0x0 0x10000>;
100 };
101
102Freescale DCFG
103 DCFG is the device configuration unit, that provides general purpose
104configuration and status for the device. Such as setting the secondary
105core start address and release the secondary core from holdoff and startup.
106 Required properties:
107 - compatible: should be "fsl,ls1021a-dcfg"
108 - reg : should contain base address and length of DCFG memory-mapped registers
109
110Example:
111 dcfg: dcfg@1ee0000 {
112 compatible = "fsl,ls1021a-dcfg";
113 reg = <0x0 0x1ee0000 0x0 0x10000>;
114 };
diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt
index c80863d344ac..63f9f1ac3439 100644
--- a/Documentation/devicetree/bindings/clock/vf610-clock.txt
+++ b/Documentation/devicetree/bindings/clock/vf610-clock.txt
@@ -5,6 +5,19 @@ Required properties:
5- reg: Address and length of the register set 5- reg: Address and length of the register set
6- #clock-cells: Should be <1> 6- #clock-cells: Should be <1>
7 7
8Optional properties:
9- clocks: list of clock identifiers which are external input clocks to the
10 given clock controller. Please refer the next section to find
11 the input clocks for a given controller.
12- clock-names: list of names of clocks which are exteral input clocks to the
13 given clock controller.
14
15Input clocks for top clock controller:
16 - sxosc (external crystal oscillator 32KHz, recommended)
17 - fxosc (external crystal oscillator 24MHz, recommended)
18 - audio_ext
19 - enet_ext
20
8The clock consumer should specify the desired clock by having the clock 21The clock consumer should specify the desired clock by having the clock
9ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h 22ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
10for the full list of VF610 clock IDs. 23for the full list of VF610 clock IDs.
@@ -15,6 +28,8 @@ clks: ccm@4006b000 {
15 compatible = "fsl,vf610-ccm"; 28 compatible = "fsl,vf610-ccm";
16 reg = <0x4006b000 0x1000>; 29 reg = <0x4006b000 0x1000>;
17 #clock-cells = <1>; 30 #clock-cells = <1>;
31 clocks = <&sxosc>, <&fxosc>;
32 clock-names = "sxosc", "fxosc";
18}; 33};
19 34
20uart1: serial@40028000 { 35uart1: serial@40028000 {
diff --git a/Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt b/Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt
new file mode 100644
index 000000000000..dc7c9bad63ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt
@@ -0,0 +1,23 @@
1i.mx6 Poweroff Driver
2
3SNVS_LPCR in SNVS module can power off the whole system by pull
4PMIC_ON_REQ low if PMIC_ON_REQ is connected with external PMIC.
5If you don't want to use PMIC_ON_REQ as power on/off control,
6please set status='disabled' to disable this driver.
7
8Required Properties:
9-compatible: "fsl,sec-v4.0-poweroff"
10-reg: Specifies the physical address of the SNVS_LPCR register
11
12Example:
13 snvs@020cc000 {
14 compatible = "fsl,sec-v4.0-mon", "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges = <0 0x020cc000 0x4000>;
18 .....
19 snvs_poweroff: snvs-poweroff@38 {
20 compatible = "fsl,sec-v4.0-poweroff";
21 reg = <0x38 0x4>;
22 };
23 }
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index bfbd93e06bae..8c4a0db062cd 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -147,6 +147,7 @@ st STMicroelectronics
147ste ST-Ericsson 147ste ST-Ericsson
148stericsson ST-Ericsson 148stericsson ST-Ericsson
149synology Synology, Inc. 149synology Synology, Inc.
150tbs TBS Technologies
150thine THine Electronics, Inc. 151thine THine Electronics, Inc.
151ti Texas Instruments 152ti Texas Instruments
152tlm Trusted Logic Mobility 153tlm Trusted Logic Mobility
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f8d11c74440d..cd24e2bc3f5d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -248,6 +248,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
248 imx6q-sabrelite.dtb \ 248 imx6q-sabrelite.dtb \
249 imx6q-sabresd.dtb \ 249 imx6q-sabresd.dtb \
250 imx6q-sbc6x.dtb \ 250 imx6q-sbc6x.dtb \
251 imx6q-tbs2910.dtb \
251 imx6q-udoo.dtb \ 252 imx6q-udoo.dtb \
252 imx6q-wandboard.dtb \ 253 imx6q-wandboard.dtb \
253 imx6q-wandboard-revb1.dtb \ 254 imx6q-wandboard-revb1.dtb \
@@ -258,6 +259,9 @@ dtb-$(CONFIG_ARCH_MXC) += \
258 imx6q-tx6q-1110.dtb \ 259 imx6q-tx6q-1110.dtb \
259 imx6sl-evk.dtb \ 260 imx6sl-evk.dtb \
260 imx6sx-sdb.dtb \ 261 imx6sx-sdb.dtb \
262 ls1021a-qds.dtb \
263 ls1021a-twr.dtb \
264 vf500-colibri-eval-v3.dtb \
261 vf610-colibri-eval-v3.dtb \ 265 vf610-colibri-eval-v3.dtb \
262 vf610-cosmic.dtb \ 266 vf610-cosmic.dtb \
263 vf610-twr.dtb 267 vf610-twr.dtb
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 92660e1fe1fc..c0116cffc513 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -214,7 +214,9 @@
214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
215 reg = <0x70014000 0x4000>; 215 reg = <0x70014000 0x4000>;
216 interrupts = <30>; 216 interrupts = <30>;
217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; 217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
218 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
219 clock-names = "ipg", "baud";
218 dmas = <&sdma 24 1 0>, 220 dmas = <&sdma 24 1 0>,
219 <&sdma 25 1 0>; 221 <&sdma 25 1 0>;
220 dma-names = "rx", "tx"; 222 dma-names = "rx", "tx";
@@ -504,7 +506,9 @@
504 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 506 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
505 reg = <0x83fcc000 0x4000>; 507 reg = <0x83fcc000 0x4000>;
506 interrupts = <29>; 508 interrupts = <29>;
507 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; 509 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
510 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
511 clock-names = "ipg", "baud";
508 dmas = <&sdma 28 0 0>, 512 dmas = <&sdma 28 0 0>,
509 <&sdma 29 0 0>; 513 <&sdma 29 0 0>;
510 dma-names = "rx", "tx"; 514 dma-names = "rx", "tx";
@@ -560,7 +564,9 @@
560 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 564 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
561 reg = <0x83fe8000 0x4000>; 565 reg = <0x83fe8000 0x4000>;
562 interrupts = <96>; 566 interrupts = <96>;
563 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; 567 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
568 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
569 clock-names = "ipg", "baud";
564 dmas = <&sdma 46 0 0>, 570 dmas = <&sdma 46 0 0>,
565 <&sdma 47 0 0>; 571 <&sdma 47 0 0>;
566 dma-names = "rx", "tx"; 572 dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index f91725b2e8ab..a30bddfdbdb6 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -46,10 +46,21 @@
46 cpus { 46 cpus {
47 #address-cells = <1>; 47 #address-cells = <1>;
48 #size-cells = <0>; 48 #size-cells = <0>;
49 cpu@0 { 49 cpu0: cpu@0 {
50 device_type = "cpu"; 50 device_type = "cpu";
51 compatible = "arm,cortex-a8"; 51 compatible = "arm,cortex-a8";
52 reg = <0x0>; 52 reg = <0x0>;
53 clocks = <&clks IMX5_CLK_ARM>;
54 clock-latency = <61036>;
55 voltage-tolerance = <5>;
56 operating-points = <
57 /* kHz */
58 166666 850000
59 400000 900000
60 800000 1050000
61 1000000 1200000
62 1200000 1300000
63 >;
53 }; 64 };
54 }; 65 };
55 66
@@ -227,7 +238,9 @@
227 "fsl,imx21-ssi"; 238 "fsl,imx21-ssi";
228 reg = <0x50014000 0x4000>; 239 reg = <0x50014000 0x4000>;
229 interrupts = <30>; 240 interrupts = <30>;
230 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; 241 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
242 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
243 clock-names = "ipg", "baud";
231 dmas = <&sdma 24 1 0>, 244 dmas = <&sdma 24 1 0>,
232 <&sdma 25 1 0>; 245 <&sdma 25 1 0>;
233 dma-names = "rx", "tx"; 246 dma-names = "rx", "tx";
@@ -675,7 +688,9 @@
675 "fsl,imx21-ssi"; 688 "fsl,imx21-ssi";
676 reg = <0x63fcc000 0x4000>; 689 reg = <0x63fcc000 0x4000>;
677 interrupts = <29>; 690 interrupts = <29>;
678 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; 691 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
692 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
693 clock-names = "ipg", "baud";
679 dmas = <&sdma 28 0 0>, 694 dmas = <&sdma 28 0 0>,
680 <&sdma 29 0 0>; 695 <&sdma 29 0 0>;
681 dma-names = "rx", "tx"; 696 dma-names = "rx", "tx";
@@ -703,7 +718,9 @@
703 "fsl,imx21-ssi"; 718 "fsl,imx21-ssi";
704 reg = <0x63fe8000 0x4000>; 719 reg = <0x63fe8000 0x4000>;
705 interrupts = <96>; 720 interrupts = <96>;
706 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; 721 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
722 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
723 clock-names = "ipg", "baud";
707 dmas = <&sdma 46 0 0>, 724 dmas = <&sdma 46 0 0>,
708 <&sdma 47 0 0>; 725 <&sdma 47 0 0>;
709 dma-names = "rx", "tx"; 726 dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index b453e0e28aee..1ac2fe732867 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -13,6 +13,10 @@
13#include "imx6qdl.dtsi" 13#include "imx6qdl.dtsi"
14 14
15/ { 15/ {
16 aliases {
17 i2c3 = &i2c4;
18 };
19
16 cpus { 20 cpus {
17 #address-cells = <1>; 21 #address-cells = <1>;
18 #size-cells = <0>; 22 #size-cells = <0>;
@@ -114,3 +118,7 @@
114 "di0_sel", "di1_sel", 118 "di0_sel", "di1_sel",
115 "di0", "di1"; 119 "di0", "di1";
116}; 120};
121
122&vpu {
123 compatible = "fsl,imx6dl-vpu", "cnm,coda960";
124};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
new file mode 100644
index 000000000000..a43abfa21e33
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -0,0 +1,432 @@
1/*
2 * Copyright 2014 Soeren Moch <smoch@web.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49
50#include "imx6q.dtsi"
51#include <dt-bindings/gpio/gpio.h>
52#include <dt-bindings/input/input.h>
53
54/ {
55 model = "TBS2910 Matrix ARM mini PC";
56 compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
57
58 chosen {
59 stdout-path = &uart1;
60 };
61
62 memory {
63 reg = <0x10000000 0x80000000>;
64 };
65
66 fan {
67 compatible = "gpio-fan";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_gpio_fan>;
70 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
71 gpio-fan,speed-map = <0 0
72 3000 1>;
73 };
74
75 ir_recv {
76 compatible = "gpio-ir-receiver";
77 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_ir>;
80 };
81
82 leds {
83 compatible = "gpio-leds";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_gpio_leds>;
86
87 blue {
88 label = "blue_status_led";
89 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
90 default-state = "keep";
91 };
92 };
93
94 regulators {
95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 reg_2p5v: regulator@0 {
100 compatible = "regulator-fixed";
101 reg = <0>;
102 regulator-name = "2P5V";
103 regulator-min-microvolt = <2500000>;
104 regulator-max-microvolt = <2500000>;
105 };
106
107 reg_3p3v: regulator@1 {
108 compatible = "regulator-fixed";
109 reg = <1>;
110 regulator-name = "3P3V";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 };
114
115 reg_5p0v: regulator@2 {
116 compatible = "regulator-fixed";
117 reg = <2>;
118 regulator-name = "5P0V";
119 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>;
121 };
122 };
123
124 sound-sgtl5000 {
125 audio-codec = <&sgtl5000>;
126 audio-routing =
127 "MIC_IN", "Mic Jack",
128 "Mic Jack", "Mic Bias",
129 "Headphone Jack", "HP_OUT";
130 compatible = "fsl,imx-audio-sgtl5000";
131 model = "On-board Codec";
132 mux-ext-port = <3>;
133 mux-int-port = <1>;
134 ssi-controller = <&ssi1>;
135 };
136
137 sound-spdif {
138 compatible = "fsl,imx-audio-spdif";
139 model = "On-board SPDIF";
140 spdif-controller = <&spdif>;
141 spdif-out;
142 };
143};
144
145&audmux {
146 status = "okay";
147};
148
149&fec {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_enet>;
152 phy-mode = "rgmii";
153 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
154 status = "okay";
155};
156
157&hdmi {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_hdmi>;
160 ddc-i2c-bus = <&i2c2>;
161 status = "okay";
162};
163
164&i2c1 {
165 clock-frequency = <100000>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c1>;
168 status = "okay";
169
170 sgtl5000: sgtl5000@0a {
171 clocks = <&clks 201>;
172 compatible = "fsl,sgtl5000";
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_sgtl5000>;
175 reg = <0x0a>;
176 VDDA-supply = <&reg_2p5v>;
177 VDDIO-supply = <&reg_3p3v>;
178 };
179};
180
181&i2c2 {
182 clock-frequency = <100000>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c2>;
185 status = "okay";
186};
187
188&i2c3 {
189 clock-frequency = <100000>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_i2c3>;
192 status = "okay";
193
194 rtc: ds1307@68 {
195 compatible = "dallas,ds1307";
196 reg = <0x68>;
197 };
198};
199
200&pcie {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_pcie>;
203 reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
204 status = "okay";
205};
206
207&sata {
208 status = "okay";
209};
210
211&snvs_poweroff {
212 status = "okay";
213};
214
215&spdif {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_spdif>;
218 status = "okay";
219};
220
221&ssi1 {
222 status = "okay";
223};
224
225&uart1 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_uart1>;
228 status = "okay";
229};
230
231&uart2 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart2>;
234 status = "okay";
235};
236
237&usbh1 {
238 vbus-supply = <&reg_5p0v>;
239 status = "okay";
240};
241
242&usbotg {
243 vbus-supply = <&reg_5p0v>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_usbotg>;
246 disable-over-current;
247 status = "okay";
248};
249
250&usdhc2 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_usdhc2>;
253 bus-width = <4>;
254 cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
255 vmmc-supply = <&reg_3p3v>;
256 status = "okay";
257};
258
259&usdhc3 {
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_usdhc3>;
262 bus-width = <4>;
263 cd-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
264 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
265 vmmc-supply = <&reg_3p3v>;
266 status = "okay";
267};
268
269&usdhc4 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_usdhc4>;
272 bus-width = <8>;
273 non-removable;
274 no-1-8-v;
275 status = "okay";
276};
277
278&iomuxc {
279 imx6q-tbs2910 {
280 pinctrl_enet: enetgrp {
281 fsl,pins = <
282 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
283 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
284 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
285 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
286 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
287 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
288 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
289 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
290 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
291 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
292 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
293 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
294 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
295 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
296 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
297 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
298 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
299 >;
300 };
301
302 pinctrl_hdmi: hdmigrp {
303 fsl,pins = <
304 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
305 >;
306 };
307
308 pinctrl_i2c1: i2c1grp {
309 fsl,pins = <
310 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
311 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
312 >;
313 };
314
315 pinctrl_i2c2: i2c2grp {
316 fsl,pins = <
317 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
318 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
319 >;
320 };
321
322 pinctrl_i2c3: i2c3grp {
323 fsl,pins = <
324 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
325 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
326 >;
327 };
328
329 pinctrl_ir: irgrp {
330 fsl,pins = <
331 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059
332 >;
333 };
334
335 pinctrl_pcie: pciegrp {
336 fsl,pins = <
337 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059
338 >;
339 };
340
341 pinctrl_sgtl5000: sgtl5000grp {
342 fsl,pins = <
343 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
344 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
345 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
346 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
347 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
348 >;
349 };
350
351 pinctrl_spdif: spdifgrp {
352 fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
353 >;
354 };
355
356 pinctrl_uart1: uart1grp {
357 fsl,pins = <
358 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
359 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
360 >;
361 };
362
363 pinctrl_uart2: uart2grp {
364 fsl,pins = <
365 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
366 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
367 >;
368 };
369
370 pinctrl_usbotg: usbotggrp {
371 fsl,pins = <
372 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
373 >;
374 };
375
376 pinctrl_usdhc2: usdhc2grp {
377 fsl,pins = <
378 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
379 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
380 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
381 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
382 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
383 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
384 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059
385 >;
386 };
387
388 pinctrl_usdhc3: usdhc3grp {
389 fsl,pins = <
390 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
391 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
392 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
393 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
394 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
395 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
396 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059
397 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059
398 >;
399 };
400
401 pinctrl_usdhc4: usdhc4grp {
402 fsl,pins = <
403 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
404 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
405 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
406 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
407 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
408 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
409 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
410 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
411 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
412 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
413 >;
414 };
415 };
416
417 gpio_fan {
418 pinctrl_gpio_fan: gpiofangrp {
419 fsl,pins = <
420 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1
421 >;
422 };
423 };
424
425 gpio_leds {
426 pinctrl_gpio_leds: gpioledsgrp {
427 fsl,pins = <
428 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1
429 >;
430 };
431 };
432};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9f3646d1760..85f72e6b5bad 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -308,3 +308,7 @@
308 }; 308 };
309 }; 309 };
310}; 310};
311
312&vpu {
313 compatible = "fsl,imx6q-vpu", "cnm,coda960";
314};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 584721264121..585b4f6986c1 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -9,17 +9,103 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/sound/fsl-imx-audmux.h>
13
12/ { 14/ {
13 chosen { 15 chosen {
14 linux,stdout-path = &uart4; 16 linux,stdout-path = &uart4;
15 }; 17 };
18
19 regulators {
20 sound_1v8: regulator@2 {
21 compatible = "regulator-fixed";
22 reg = <2>;
23 regulator-name = "i2s-audio-1v8";
24 regulator-min-microvolt = <1800000>;
25 regulator-max-microvolt = <1800000>;
26 };
27
28 sound_3v3: regulator@3 {
29 compatible = "regulator-fixed";
30 reg = <3>;
31 regulator-name = "i2s-audio-3v3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 };
35 };
36
37 tlv320_mclk: oscillator {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <19200000>;
41 clock-output-names = "tlv320-mclk";
42 };
43
44 sound {
45 compatible = "simple-audio-card";
46 simple-audio-card,name = "OnboardTLV320AIC3007";
47 simple-audio-card,format = "i2s";
48 simple-audio-card,bitclock-master = <&dailink_master>;
49 simple-audio-card,frame-master = <&dailink_master>;
50 simple-audio-card,widgets =
51 "Microphone", "Mic Jack",
52 "Line", "Line In",
53 "Line", "Line Out",
54 "Speaker", "Speaker",
55 "Headphone", "Headphone Jack";
56 simple-audio-card,routing =
57 "Line Out", "LLOUT",
58 "Line Out", "RLOUT",
59 "Speaker", "SPOP",
60 "Speaker", "SPOM",
61 "Headphone Jack", "HPLOUT",
62 "Headphone Jack", "HPROUT",
63 "MIC3L", "Mic Jack",
64 "MIC3R", "Mic Jack",
65 "Mic Jack", "Mic Bias",
66 "LINE1L", "Line In",
67 "LINE1R", "Line In";
68
69 simple-audio-card,cpu {
70 sound-dai = <&ssi2>;
71 };
72
73 dailink_master: simple-audio-card,codec {
74 sound-dai = <&codec>;
75 clocks = <&tlv320_mclk>;
76 };
77 };
78
16}; 79};
17 80
18&fec { 81&audmux {
19 status = "okay"; 82 status = "okay";
83
84 ssi2 {
85 fsl,audmux-port = <1>;
86 fsl,port-config = <
87 (IMX_AUDMUX_V2_PTCR_TFSDIR |
88 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
89 IMX_AUDMUX_V2_PTCR_TCLKDIR |
90 IMX_AUDMUX_V2_PTCR_TCSEL(4))
91 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
92 >;
93 };
94
95 pins5 {
96 fsl,audmux-port = <4>;
97 fsl,port-config = <
98 0x00000000
99 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
100 >;
101 };
20}; 102};
21 103
22&gpmi { 104&can1 {
105 status = "okay";
106};
107
108&fec {
23 status = "okay"; 109 status = "okay";
24}; 110};
25 111
@@ -28,14 +114,18 @@
28}; 114};
29 115
30&i2c2 { 116&i2c2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_i2c2>;
33 clock-frequency = <100000>;
34 status = "okay"; 117 status = "okay";
35 118
36 tlv320@18 { 119 codec: tlv320@18 {
37 compatible = "ti,tlv320aic3x"; 120 compatible = "ti,tlv320aic3007";
121 #sound-dai-cells = <0>;
38 reg = <0x18>; 122 reg = <0x18>;
123 ai3x-micbias-vg = <2>;
124
125 AVDD-supply = <&sound_3v3>;
126 IOVDD-supply = <&sound_3v3>;
127 DRVDD-supply = <&sound_3v3>;
128 DVDD-supply = <&sound_1v8>;
39 }; 129 };
40 130
41 stmpe@41 { 131 stmpe@41 {
@@ -55,9 +145,14 @@
55}; 145};
56 146
57&i2c3 { 147&i2c3 {
58 pinctrl-names = "default"; 148 status = "okay";
59 pinctrl-0 = <&pinctrl_i2c3>; 149};
60 clock-frequency = <100000>; 150
151&pcie {
152 status = "okay";
153};
154
155&ssi2 {
61 status = "okay"; 156 status = "okay";
62}; 157};
63 158
@@ -84,19 +179,3 @@
84&usdhc3 { 179&usdhc3 {
85 status = "okay"; 180 status = "okay";
86}; 181};
87
88&iomuxc {
89 pinctrl_i2c2: i2c2grp {
90 fsl,pins = <
91 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
92 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
93 >;
94 };
95
96 pinctrl_i2c3: i2c3grp {
97 fsl,pins = <
98 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
99 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
100 >;
101 };
102};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 0e50bb0a6b94..19cc269a08d4 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -58,6 +58,18 @@
58 }; 58 };
59}; 59};
60 60
61&audmux {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_audmux>;
64 status = "disabled";
65};
66
67&can1 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_flexcan1>;
70 status = "disabled";
71};
72
61&ecspi3 { 73&ecspi3 {
62 pinctrl-names = "default"; 74 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_ecspi3>; 75 pinctrl-0 = <&pinctrl_ecspi3>;
@@ -72,6 +84,22 @@
72 }; 84 };
73}; 85};
74 86
87&fec {
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_enet>;
90 phy-mode = "rgmii";
91 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
92 phy-supply = <&vdd_eth_io_reg>;
93 status = "disabled";
94};
95
96&gpmi {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_gpmi_nand>;
99 nand-on-flash-bbt;
100 status = "okay";
101};
102
75&i2c1 { 103&i2c1 {
76 pinctrl-names = "default"; 104 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_i2c1>; 105 pinctrl-0 = <&pinctrl_i2c1>;
@@ -85,8 +113,8 @@
85 pmic@58 { 113 pmic@58 {
86 compatible = "dlg,da9063"; 114 compatible = "dlg,da9063";
87 reg = <0x58>; 115 reg = <0x58>;
88 interrupt-parent = <&gpio4>; 116 interrupt-parent = <&gpio2>;
89 interrupts = <17 0x8>; /* active-low GPIO4_17 */ 117 interrupts = <9 0x8>; /* active-low GPIO2_9 */
90 118
91 regulators { 119 regulators {
92 vddcore_reg: bcore1 { 120 vddcore_reg: bcore1 {
@@ -162,6 +190,18 @@
162 }; 190 };
163}; 191};
164 192
193&i2c2 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_i2c2>;
196 clock-frequency = <100000>;
197};
198
199&i2c3 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c3>;
202 clock-frequency = <100000>;
203};
204
165&iomuxc { 205&iomuxc {
166 pinctrl-names = "default"; 206 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_hog>; 207 pinctrl-0 = <&pinctrl_hog>;
@@ -171,7 +211,7 @@
171 fsl,pins = < 211 fsl,pins = <
172 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 212 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
173 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ 213 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
174 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ 214 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */
175 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ 215 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
176 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ 216 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
177 >; 217 >;
@@ -206,6 +246,13 @@
206 >; 246 >;
207 }; 247 };
208 248
249 pinctrl_flexcan1: flexcan1grp {
250 fsl,pins = <
251 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
252 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
253 >;
254 };
255
209 pinctrl_gpmi_nand: gpminandgrp { 256 pinctrl_gpmi_nand: gpminandgrp {
210 fsl,pins = < 257 fsl,pins = <
211 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 258 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
@@ -235,6 +282,24 @@
235 >; 282 >;
236 }; 283 };
237 284
285 pinctrl_i2c2: i2c2grp {
286 fsl,pins = <
287 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
288 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
289 >;
290 };
291
292 pinctrl_i2c3: i2c3grp {
293 fsl,pins = <
294 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
295 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
296 >;
297 };
298
299 pinctrl_pcie: pciegrp {
300 fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
301 };
302
238 pinctrl_uart3: uart3grp { 303 pinctrl_uart3: uart3grp {
239 fsl,pins = < 304 fsl,pins = <
240 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 305 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
@@ -293,22 +358,22 @@
293 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 358 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
294 >; 359 >;
295 }; 360 };
296 };
297};
298 361
299&fec { 362 pinctrl_audmux: audmuxgrp {
300 pinctrl-names = "default"; 363 fsl,pins = <
301 pinctrl-0 = <&pinctrl_enet>; 364 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
302 phy-mode = "rgmii"; 365 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
303 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 366 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
304 phy-supply = <&vdd_eth_io_reg>; 367 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
305 status = "disabled"; 368 >;
369 };
370 };
306}; 371};
307 372
308&gpmi { 373&pcie {
309 pinctrl-names = "default"; 374 pinctrl-name = "default";
310 pinctrl-0 = <&pinctrl_gpmi_nand>; 375 pinctrl-0 = <&pinctrl_pcie>;
311 nand-on-flash-bbt; 376 reset-gpio = <&gpio4 17 0>;
312 status = "disabled"; 377 status = "disabled";
313}; 378};
314 379
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index baf2f00d519a..05f5ff75c0ea 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -531,6 +531,10 @@
531 status = "okay"; 531 status = "okay";
532}; 532};
533 533
534&snvs_poweroff {
535 status = "okay";
536};
537
534&ssi2 { 538&ssi2 {
535 status = "okay"; 539 status = "okay";
536}; 540};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9596ed5867e6..4fc03b7f1cee 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -333,9 +333,17 @@
333 }; 333 };
334 334
335 vpu: vpu@02040000 { 335 vpu: vpu@02040000 {
336 compatible = "cnm,coda960";
336 reg = <0x02040000 0x3c000>; 337 reg = <0x02040000 0x3c000>;
337 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, 338 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
338 <0 12 IRQ_TYPE_LEVEL_HIGH>; 339 <0 12 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "bit", "jpeg";
341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
343 <&clks IMX6QDL_CLK_OCRAM>;
344 clock-names = "per", "ahb", "ocram";
345 resets = <&src 1>;
346 iram = <&ocram>;
339 }; 347 };
340 348
341 aipstz@0207c000 { /* AIPSTZ1 */ 349 aipstz@0207c000 { /* AIPSTZ1 */
@@ -657,6 +665,12 @@
657 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 665 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
658 <0 20 IRQ_TYPE_LEVEL_HIGH>; 666 <0 20 IRQ_TYPE_LEVEL_HIGH>;
659 }; 667 };
668
669 snvs_poweroff: snvs-poweroff@38 {
670 compatible = "fsl,sec-v4.0-poweroff";
671 reg = <0x38 0x4>;
672 status = "disabled";
673 };
660 }; 674 };
661 675
662 epit1: epit@020d0000 { /* EPIT1 */ 676 epit1: epit@020d0000 { /* EPIT1 */
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 898d14fd765f..fda4932faefd 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -580,6 +580,10 @@
580 status = "okay"; 580 status = "okay";
581}; 581};
582 582
583&snvs_poweroff {
584 status = "okay";
585};
586
583&ssi2 { 587&ssi2 {
584 status = "okay"; 588 status = "okay";
585}; 589};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index dfd83e6d8087..36ab8e054cee 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -574,6 +574,12 @@
574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
575 <0 20 IRQ_TYPE_LEVEL_HIGH>; 575 <0 20 IRQ_TYPE_LEVEL_HIGH>;
576 }; 576 };
577
578 snvs_poweroff: snvs-poweroff@38 {
579 compatible = "fsl,sec-v4.0-poweroff";
580 reg = <0x38 0x4>;
581 status = "disabled";
582 };
577 }; 583 };
578 584
579 epit1: epit@020d0000 { 585 epit1: epit@020d0000 {
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 82d6b34527b7..1e6e5cc1c14c 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -105,6 +105,30 @@
105 gpio = <&gpio3 27 0>; 105 gpio = <&gpio3 27 0>;
106 enable-active-high; 106 enable-active-high;
107 }; 107 };
108
109 reg_peri_3v3: regulator@5 {
110 compatible = "regulator-fixed";
111 reg = <5>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_peri_3v3>;
114 regulator-name = "peri_3v3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
118 enable-active-high;
119 regulator-always-on;
120 };
121
122 reg_enet_3v3: regulator@6 {
123 compatible = "regulator-fixed";
124 reg = <6>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_enet_3v3>;
127 regulator-name = "enet_3v3";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
131 };
108 }; 132 };
109 133
110 sound { 134 sound {
@@ -133,6 +157,14 @@
133&fec1 { 157&fec1 {
134 pinctrl-names = "default"; 158 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_enet1>; 159 pinctrl-0 = <&pinctrl_enet1>;
160 phy-supply = <&reg_enet_3v3>;
161 phy-mode = "rgmii";
162 status = "okay";
163};
164
165&fec2 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_enet2>;
136 phy-mode = "rgmii"; 168 phy-mode = "rgmii";
137 status = "okay"; 169 status = "okay";
138}; 170};
@@ -304,6 +336,10 @@
304 status = "okay"; 336 status = "okay";
305}; 337};
306 338
339&snvs_poweroff {
340 status = "okay";
341};
342
307&ssi2 { 343&ssi2 {
308 status = "okay"; 344 status = "okay";
309}; 345};
@@ -394,6 +430,30 @@
394 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 430 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
395 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 431 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
396 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 432 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
433 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
434 >;
435 };
436
437 pinctrl_enet_3v3: enet3v3grp {
438 fsl,pins = <
439 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
440 >;
441 };
442
443 pinctrl_enet2: enet2grp {
444 fsl,pins = <
445 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
446 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
447 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
448 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
449 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
450 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
451 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
452 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
453 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
454 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
455 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
456 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
397 >; 457 >;
398 }; 458 };
399 459
@@ -452,6 +512,12 @@
452 >; 512 >;
453 }; 513 };
454 514
515 pinctrl_peri_3v3: peri3v3grp {
516 fsl,pins = <
517 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
518 >;
519 };
520
455 pinctrl_pwm3: pwm3grp-1 { 521 pinctrl_pwm3: pwm3grp-1 {
456 fsl,pins = < 522 fsl,pins = <
457 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 523 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index f3e88c03b1e4..7a24fee1e7ae 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -671,6 +671,12 @@
671 reg = <0x34 0x58>; 671 reg = <0x34 0x58>;
672 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 672 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
673 }; 673 };
674
675 snvs_poweroff: snvs-poweroff@38 {
676 compatible = "fsl,sec-v4.0-poweroff";
677 reg = <0x38 0x4>;
678 status = "disabled";
679 };
674 }; 680 };
675 681
676 epit1: epit@020d0000 { 682 epit1: epit@020d0000 {
@@ -877,7 +883,7 @@
877 }; 883 };
878 884
879 fec2: ethernet@021b4000 { 885 fec2: ethernet@021b4000 {
880 compatible = "fsl,imx6sx-fec"; 886 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
881 reg = <0x021b4000 0x4000>; 887 reg = <0x021b4000 0x4000>;
882 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 888 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 889 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
new file mode 100644
index 000000000000..9c5e16ba8c95
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -0,0 +1,240 @@
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "ls1021a.dtsi"
50
51/ {
52 model = "LS1021A QDS Board";
53
54 aliases {
55 enet0_rgmii_phy = &rgmii_phy1;
56 enet1_rgmii_phy = &rgmii_phy2;
57 enet2_rgmii_phy = &rgmii_phy3;
58 enet0_sgmii_phy = &sgmii_phy1c;
59 enet1_sgmii_phy = &sgmii_phy1d;
60 };
61};
62
63&dspi0 {
64 bus-num = <0>;
65 status = "okay";
66
67 dspiflash: at45db021d@0 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
71 spi-max-frequency = <16000000>;
72 spi-cpol;
73 spi-cpha;
74 reg = <0>;
75 };
76};
77
78&i2c0 {
79 status = "okay";
80
81 pca9547: mux@77 {
82 reg = <0x77>;
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 i2c@0 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 reg = <0x0>;
90
91 ds3232: rtc@68 {
92 compatible = "dallas,ds3232";
93 reg = <0x68>;
94 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
95 };
96 };
97
98 i2c@2 {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 reg = <0x2>;
102
103 ina220@40 {
104 compatible = "ti,ina220";
105 reg = <0x40>;
106 shunt-resistor = <1000>;
107 };
108
109 ina220@41 {
110 compatible = "ti,ina220";
111 reg = <0x41>;
112 shunt-resistor = <1000>;
113 };
114 };
115
116 i2c@3 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 reg = <0x3>;
120
121 eeprom@56 {
122 compatible = "atmel,24c512";
123 reg = <0x56>;
124 };
125
126 eeprom@57 {
127 compatible = "atmel,24c512";
128 reg = <0x57>;
129 };
130
131 adt7461a@4c {
132 compatible = "adi,adt7461a";
133 reg = <0x4c>;
134 };
135 };
136 };
137};
138
139&ifc {
140 #address-cells = <2>;
141 #size-cells = <1>;
142 /* NOR, NAND Flashes and FPGA on board */
143 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
144 0x2 0x0 0x0 0x7e800000 0x00010000
145 0x3 0x0 0x0 0x7fb00000 0x00000100>;
146 status = "okay";
147
148 nor@0,0 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "cfi-flash";
152 reg = <0x0 0x0 0x8000000>;
153 bank-width = <2>;
154 device-width = <1>;
155 };
156
157 fpga: board-control@3,0 {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "simple-bus";
161 reg = <0x3 0x0 0x0000100>;
162 bank-width = <1>;
163 device-width = <1>;
164 ranges = <0 3 0 0x100>;
165
166 mdio-mux-emi1 {
167 compatible = "mdio-mux-mmioreg";
168 mdio-parent-bus = <&mdio0>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171 reg = <0x54 1>; /* BRDCFG4 */
172 mux-mask = <0xe0>; /* EMI1[2:0] */
173
174 /* Onboard PHYs */
175 ls1021amdio0: mdio@0 {
176 reg = <0>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 rgmii_phy1: ethernet-phy@1 {
180 reg = <0x1>;
181 };
182 };
183
184 ls1021amdio1: mdio@20 {
185 reg = <0x20>;
186 #address-cells = <1>;
187 #size-cells = <0>;
188 rgmii_phy2: ethernet-phy@2 {
189 reg = <0x2>;
190 };
191 };
192
193 ls1021amdio2: mdio@40 {
194 reg = <0x40>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 rgmii_phy3: ethernet-phy@3 {
198 reg = <0x3>;
199 };
200 };
201
202 ls1021amdio3: mdio@60 {
203 reg = <0x60>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 sgmii_phy1c: ethernet-phy@1c {
207 reg = <0x1c>;
208 };
209 };
210
211 ls1021amdio4: mdio@80 {
212 reg = <0x80>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 sgmii_phy1d: ethernet-phy@1d {
216 reg = <0x1d>;
217 };
218 };
219 };
220 };
221};
222
223&lpuart0 {
224 status = "okay";
225};
226
227&mdio0 {
228 tbi0: tbi-phy@8 {
229 reg = <0x8>;
230 device_type = "tbi-phy";
231 };
232};
233
234&uart0 {
235 status = "okay";
236};
237
238&uart1 {
239 status = "okay";
240};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
new file mode 100644
index 000000000000..a2c591e2d918
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -0,0 +1,127 @@
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "ls1021a.dtsi"
50
51/ {
52 model = "LS1021A TWR Board";
53
54 aliases {
55 enet2_rgmii_phy = &rgmii_phy1;
56 enet0_sgmii_phy = &sgmii_phy2;
57 enet1_sgmii_phy = &sgmii_phy0;
58 };
59};
60
61&dspi1 {
62 bus-num = <0>;
63 status = "okay";
64
65 dspiflash: s25fl064k@0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "spansion,s25fl064k";
69 spi-max-frequency = <16000000>;
70 spi-cpol;
71 spi-cpha;
72 reg = <0>;
73 };
74};
75
76&i2c0 {
77 status = "okay";
78};
79
80&i2c1 {
81 status = "okay";
82};
83
84&ifc {
85 #address-cells = <2>;
86 #size-cells = <1>;
87 /* NOR Flash on board */
88 ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
89 status = "okay";
90
91 nor@0,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "cfi-flash";
95 reg = <0x0 0x0 0x8000000>;
96 bank-width = <2>;
97 device-width = <1>;
98 };
99};
100
101&lpuart0 {
102 status = "okay";
103};
104
105&mdio0 {
106 sgmii_phy0: ethernet-phy@0 {
107 reg = <0x0>;
108 };
109 rgmii_phy1: ethernet-phy@1 {
110 reg = <0x1>;
111 };
112 sgmii_phy2: ethernet-phy@2 {
113 reg = <0x2>;
114 };
115 tbi1: tbi-phy@1f {
116 reg = <0x1f>;
117 device_type = "tbi-phy";
118 };
119};
120
121&uart0 {
122 status = "okay";
123};
124
125&uart1 {
126 status = "okay";
127};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
new file mode 100644
index 000000000000..657da14cb4b5
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -0,0 +1,408 @@
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "skeleton64.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
50
51/ {
52 compatible = "fsl,ls1021a";
53 interrupt-parent = <&gic>;
54
55 aliases {
56 serial0 = &lpuart0;
57 serial1 = &lpuart1;
58 serial2 = &lpuart2;
59 serial3 = &lpuart3;
60 serial4 = &lpuart4;
61 serial5 = &lpuart5;
62 sysclk = &sysclk;
63 };
64
65 cpus {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 cpu@f00 {
70 compatible = "arm,cortex-a7";
71 device_type = "cpu";
72 reg = <0xf00>;
73 clocks = <&cluster1_clk>;
74 };
75
76 cpu@f01 {
77 compatible = "arm,cortex-a7";
78 device_type = "cpu";
79 reg = <0xf01>;
80 clocks = <&cluster1_clk>;
81 };
82 };
83
84 timer {
85 compatible = "arm,armv7-timer";
86 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
88 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
90 };
91
92 pmu {
93 compatible = "arm,cortex-a7-pmu";
94 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
96 };
97
98 soc {
99 compatible = "simple-bus";
100 #address-cells = <2>;
101 #size-cells = <2>;
102 device_type = "soc";
103 interrupt-parent = <&gic>;
104 ranges;
105
106 gic: interrupt-controller@1400000 {
107 compatible = "arm,cortex-a7-gic";
108 #interrupt-cells = <3>;
109 interrupt-controller;
110 reg = <0x0 0x1401000 0x0 0x1000>,
111 <0x0 0x1402000 0x0 0x1000>,
112 <0x0 0x1404000 0x0 0x2000>,
113 <0x0 0x1406000 0x0 0x2000>;
114 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
115
116 };
117
118 ifc: ifc@1530000 {
119 compatible = "fsl,ifc", "simple-bus";
120 reg = <0x0 0x1530000 0x0 0x10000>;
121 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
122 };
123
124 dcfg: dcfg@1ee0000 {
125 compatible = "fsl,ls1021a-dcfg", "syscon";
126 reg = <0x0 0x1ee0000 0x0 0x10000>;
127 big-endian;
128 };
129
130 esdhc: esdhc@1560000 {
131 compatible = "fsl,esdhc";
132 reg = <0x0 0x1560000 0x0 0x10000>;
133 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
134 clock-frequency = <0>;
135 voltage-ranges = <1800 1800 3300 3300>;
136 sdhci,auto-cmd12;
137 big-endian;
138 bus-width = <4>;
139 status = "disabled";
140 };
141
142 scfg: scfg@1570000 {
143 compatible = "fsl,ls1021a-scfg", "syscon";
144 reg = <0x0 0x1570000 0x0 0x10000>;
145 };
146
147 clockgen: clocking@1ee1000 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0x0 0x0 0x1ee1000 0x10000>;
151
152 sysclk: sysclk {
153 compatible = "fixed-clock";
154 #clock-cells = <0>;
155 clock-output-names = "sysclk";
156 };
157
158 cga_pll1: pll@800 {
159 compatible = "fsl,qoriq-core-pll-2.0";
160 #clock-cells = <1>;
161 reg = <0x800 0x10>;
162 clocks = <&sysclk>;
163 clock-output-names = "cga-pll1", "cga-pll1-div2",
164 "cga-pll1-div4";
165 };
166
167 platform_clk: pll@c00 {
168 compatible = "fsl,qoriq-core-pll-2.0";
169 #clock-cells = <1>;
170 reg = <0xc00 0x10>;
171 clocks = <&sysclk>;
172 clock-output-names = "platform-clk", "platform-clk-div2";
173 };
174
175 cluster1_clk: clk0c0@0 {
176 compatible = "fsl,qoriq-core-mux-2.0";
177 #clock-cells = <0>;
178 reg = <0x0 0x10>;
179 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
180 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
181 clock-output-names = "cluster1-clk";
182 };
183 };
184
185 dspi0: dspi@2100000 {
186 compatible = "fsl,vf610-dspi";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 reg = <0x0 0x2100000 0x0 0x10000>;
190 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
191 clock-names = "dspi";
192 clocks = <&platform_clk 1>;
193 spi-num-chipselects = <5>;
194 big-endian;
195 status = "disabled";
196 };
197
198 dspi1: dspi@2110000 {
199 compatible = "fsl,vf610-dspi";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <0x0 0x2110000 0x0 0x10000>;
203 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
204 clock-names = "dspi";
205 clocks = <&platform_clk 1>;
206 spi-num-chipselects = <5>;
207 big-endian;
208 status = "disabled";
209 };
210
211 i2c0: i2c@2180000 {
212 compatible = "fsl,vf610-i2c";
213 #address-cells = <1>;
214 #size-cells = <0>;
215 reg = <0x0 0x2180000 0x0 0x10000>;
216 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
217 clock-names = "i2c";
218 clocks = <&platform_clk 1>;
219 status = "disabled";
220 };
221
222 i2c1: i2c@2190000 {
223 compatible = "fsl,vf610-i2c";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <0x0 0x2190000 0x0 0x10000>;
227 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
228 clock-names = "i2c";
229 clocks = <&platform_clk 1>;
230 status = "disabled";
231 };
232
233 i2c2: i2c@21a0000 {
234 compatible = "fsl,vf610-i2c";
235 #address-cells = <1>;
236 #size-cells = <0>;
237 reg = <0x0 0x21a0000 0x0 0x10000>;
238 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
239 clock-names = "i2c";
240 clocks = <&platform_clk 1>;
241 status = "disabled";
242 };
243
244 uart0: serial@21c0500 {
245 compatible = "fsl,16550-FIFO64", "ns16550a";
246 reg = <0x0 0x21c0500 0x0 0x100>;
247 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
248 clock-frequency = <0>;
249 fifo-size = <15>;
250 status = "disabled";
251 };
252
253 uart1: serial@21c0600 {
254 compatible = "fsl,16550-FIFO64", "ns16550a";
255 reg = <0x0 0x21c0600 0x0 0x100>;
256 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
257 clock-frequency = <0>;
258 fifo-size = <15>;
259 status = "disabled";
260 };
261
262 uart2: serial@21d0500 {
263 compatible = "fsl,16550-FIFO64", "ns16550a";
264 reg = <0x0 0x21d0500 0x0 0x100>;
265 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
266 clock-frequency = <0>;
267 fifo-size = <15>;
268 status = "disabled";
269 };
270
271 uart3: serial@21d0600 {
272 compatible = "fsl,16550-FIFO64", "ns16550a";
273 reg = <0x0 0x21d0600 0x0 0x100>;
274 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
275 clock-frequency = <0>;
276 fifo-size = <15>;
277 status = "disabled";
278 };
279
280 lpuart0: serial@2950000 {
281 compatible = "fsl,ls1021a-lpuart";
282 reg = <0x0 0x2950000 0x0 0x1000>;
283 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&sysclk>;
285 clock-names = "ipg";
286 status = "disabled";
287 };
288
289 lpuart1: serial@2960000 {
290 compatible = "fsl,ls1021a-lpuart";
291 reg = <0x0 0x2960000 0x0 0x1000>;
292 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&platform_clk 1>;
294 clock-names = "ipg";
295 status = "disabled";
296 };
297
298 lpuart2: serial@2970000 {
299 compatible = "fsl,ls1021a-lpuart";
300 reg = <0x0 0x2970000 0x0 0x1000>;
301 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&platform_clk 1>;
303 clock-names = "ipg";
304 status = "disabled";
305 };
306
307 lpuart3: serial@2980000 {
308 compatible = "fsl,ls1021a-lpuart";
309 reg = <0x0 0x2980000 0x0 0x1000>;
310 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&platform_clk 1>;
312 clock-names = "ipg";
313 status = "disabled";
314 };
315
316 lpuart4: serial@2990000 {
317 compatible = "fsl,ls1021a-lpuart";
318 reg = <0x0 0x2990000 0x0 0x1000>;
319 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&platform_clk 1>;
321 clock-names = "ipg";
322 status = "disabled";
323 };
324
325 lpuart5: serial@29a0000 {
326 compatible = "fsl,ls1021a-lpuart";
327 reg = <0x0 0x29a0000 0x0 0x1000>;
328 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&platform_clk 1>;
330 clock-names = "ipg";
331 status = "disabled";
332 };
333
334 wdog0: watchdog@2ad0000 {
335 compatible = "fsl,imx21-wdt";
336 reg = <0x0 0x2ad0000 0x0 0x10000>;
337 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&platform_clk 1>;
339 clock-names = "wdog-en";
340 big-endian;
341 };
342
343 sai1: sai@2b50000 {
344 compatible = "fsl,vf610-sai";
345 reg = <0x0 0x2b50000 0x0 0x10000>;
346 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&platform_clk 1>;
348 clock-names = "sai";
349 dma-names = "tx", "rx";
350 dmas = <&edma0 1 47>,
351 <&edma0 1 46>;
352 big-endian;
353 status = "disabled";
354 };
355
356 sai2: sai@2b60000 {
357 compatible = "fsl,vf610-sai";
358 reg = <0x0 0x2b60000 0x0 0x10000>;
359 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&platform_clk 1>;
361 clock-names = "sai";
362 dma-names = "tx", "rx";
363 dmas = <&edma0 1 45>,
364 <&edma0 1 44>;
365 big-endian;
366 status = "disabled";
367 };
368
369 edma0: edma@2c00000 {
370 #dma-cells = <2>;
371 compatible = "fsl,vf610-edma";
372 reg = <0x0 0x2c00000 0x0 0x10000>,
373 <0x0 0x2c10000 0x0 0x10000>,
374 <0x0 0x2c20000 0x0 0x10000>;
375 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
377 interrupt-names = "edma-tx", "edma-err";
378 dma-channels = <32>;
379 big-endian;
380 clock-names = "dmamux0", "dmamux1";
381 clocks = <&platform_clk 1>,
382 <&platform_clk 1>;
383 };
384
385 mdio0: mdio@2d24000 {
386 compatible = "gianfar";
387 device_type = "mdio";
388 #address-cells = <1>;
389 #size-cells = <0>;
390 reg = <0x0 0x2d24000 0x0 0x4000>;
391 };
392
393 usb@8600000 {
394 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
395 reg = <0x0 0x8600000 0x0 0x1000>;
396 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
397 dr_mode = "host";
398 phy_type = "ulpi";
399 };
400
401 usb3@3100000 {
402 compatible = "snps,dwc3";
403 reg = <0x0 0x3100000 0x0 0x10000>;
404 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
405 dr_mode = "host";
406 };
407 };
408};
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
new file mode 100644
index 000000000000..56a452bc326c
--- /dev/null
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -0,0 +1,96 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/ {
11 chosen {
12 bootargs = "console=ttyLP0,115200";
13 };
14
15 regulators {
16 compatible = "simple-bus";
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 sys_5v0_reg: regulator@0 {
21 compatible = "regulator-fixed";
22 reg = <0>;
23 regulator-name = "5v0";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 regulator-always-on;
27 };
28
29 /* USBH_PEN */
30 usbh_vbus_reg: regulator@1 {
31 compatible = "regulator-fixed";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_usbh1_reg>;
34 reg = <1>;
35 regulator-name = "usbh_vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
39 vin-supply = <&sys_5v0_reg>;
40 };
41 };
42};
43
44&bl {
45 brightness-levels = <0 4 8 16 32 64 128 255>;
46 default-brightness-level = <6>;
47 status = "okay";
48};
49
50&esdhc1 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_esdhc1>;
53 bus-width = <4>;
54 status = "okay";
55};
56
57&fec1 {
58 phy-mode = "rmii";
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_fec1>;
61 status = "okay";
62};
63
64&i2c0 {
65 status = "okay";
66
67 /* M41T0M6 real time clock on carrier board */
68 rtc: m41t0m6@68 {
69 compatible = "st,m41t00";
70 reg = <0x68>;
71 };
72};
73
74&pwm0 {
75 status = "okay";
76};
77
78&pwm1 {
79 status = "okay";
80};
81
82&uart0 {
83 status = "okay";
84};
85
86&uart1 {
87 status = "okay";
88};
89
90&uart2 {
91 status = "okay";
92};
93
94&usbh1 {
95 vbus-supply = <&usbh_vbus_reg>;
96};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
new file mode 100644
index 000000000000..82f5728be5c9
--- /dev/null
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -0,0 +1,186 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/ {
11 bl: backlight {
12 compatible = "pwm-backlight";
13 pwms = <&pwm0 0 5000000 0>;
14 status = "disabled";
15 };
16};
17
18&adc0 {
19 status = "okay";
20};
21
22&adc1 {
23 status = "okay";
24};
25
26&edma0 {
27 status = "okay";
28};
29
30&esdhc1 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_esdhc1>;
33 bus-width = <4>;
34 cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
35};
36
37&fec1 {
38 phy-mode = "rmii";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_fec1>;
41};
42
43&i2c0 {
44 clock-frequency = <400000>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_i2c0>;
47};
48
49&pwm0 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_pwm0>;
52};
53
54&pwm1 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_pwm1>;
57};
58
59&uart0 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_uart0>;
62};
63
64&uart1 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_uart1>;
67};
68
69&uart2 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_uart2>;
72};
73
74&usbdev0 {
75 disable-over-current;
76 status = "okay";
77};
78
79&usbh1 {
80 disable-over-current;
81 status = "okay";
82};
83
84&usbmisc0 {
85 status = "okay";
86};
87
88&usbmisc1 {
89 status = "okay";
90};
91
92&usbphy0 {
93 status = "okay";
94};
95
96&usbphy1 {
97 status = "okay";
98};
99
100&iomuxc {
101 vf610-colibri {
102 pinctrl_gpio_ext: gpio_ext {
103 fsl,pins = <
104 VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
105 VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
106 VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
107 >;
108 };
109
110 pinctrl_esdhc1: esdhc1grp {
111 fsl,pins = <
112 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
113 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
114 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
115 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
116 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
117 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
118 VF610_PAD_PTB20__GPIO_42 0x219d
119 >;
120 };
121
122 pinctrl_fec1: fec1grp {
123 fsl,pins = <
124 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
125 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
126 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
127 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
128 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
129 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
130 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
131 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
132 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
133 >;
134 };
135
136 pinctrl_i2c0: i2c0grp {
137 fsl,pins = <
138 VF610_PAD_PTB14__I2C0_SCL 0x37ff
139 VF610_PAD_PTB15__I2C0_SDA 0x37ff
140 >;
141 };
142
143 pinctrl_pwm0: pwm0grp {
144 fsl,pins = <
145 VF610_PAD_PTB0__FTM0_CH0 0x1182
146 VF610_PAD_PTB1__FTM0_CH1 0x1182
147 >;
148 };
149
150 pinctrl_pwm1: pwm1grp {
151 fsl,pins = <
152 VF610_PAD_PTB8__FTM1_CH0 0x1182
153 VF610_PAD_PTB9__FTM1_CH1 0x1182
154 >;
155 };
156
157 pinctrl_uart0: uart0grp {
158 fsl,pins = <
159 VF610_PAD_PTB10__UART0_TX 0x21a2
160 VF610_PAD_PTB11__UART0_RX 0x21a1
161 >;
162 };
163
164 pinctrl_uart1: uart1grp {
165 fsl,pins = <
166 VF610_PAD_PTB4__UART1_TX 0x21a2
167 VF610_PAD_PTB5__UART1_RX 0x21a1
168 >;
169 };
170
171 pinctrl_uart2: uart2grp {
172 fsl,pins = <
173 VF610_PAD_PTD0__UART2_TX 0x21a2
174 VF610_PAD_PTD1__UART2_RX 0x21a1
175 VF610_PAD_PTD2__UART2_RTS 0x21a2
176 VF610_PAD_PTD3__UART2_CTS 0x21a1
177 >;
178 };
179
180 pinctrl_usbh1_reg: gpio_usb_vbus {
181 fsl,pins = <
182 VF610_PAD_PTD4__GPIO_83 0x22ed
183 >;
184 };
185 };
186};
diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
new file mode 100644
index 000000000000..7fc782c4fc52
--- /dev/null
+++ b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
@@ -0,0 +1,17 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/dts-v1/;
11#include "vf500-colibri.dtsi"
12#include "vf-colibri-eval-v3.dtsi"
13
14/ {
15 model = "Toradex Colibri VF50 on Colibri Evaluation Board";
16 compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500";
17};
diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi
new file mode 100644
index 000000000000..cee34a32f25b
--- /dev/null
+++ b/arch/arm/boot/dts/vf500-colibri.dtsi
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "vf500.dtsi"
11#include "vf-colibri.dtsi"
12
13/ {
14 model = "Toradex Colibri VF50 COM";
15 compatible = "toradex,vf610-colibri_vf50", "fsl,vf500";
16
17 memory {
18 reg = <0x80000000 0x8000000>;
19 };
20};
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
new file mode 100644
index 000000000000..de6700542714
--- /dev/null
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -0,0 +1,171 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "skeleton.dtsi"
11#include "vfxxx.dtsi"
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 a5_cpu: cpu@0 {
20 compatible = "arm,cortex-a5";
21 device_type = "cpu";
22 reg = <0x0>;
23 };
24 };
25
26 soc {
27 interrupt-parent = <&intc>;
28
29 aips-bus@40000000 {
30
31 intc: interrupt-controller@40002000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 interrupt-controller;
35 reg = <0x40003000 0x1000>,
36 <0x40002100 0x100>;
37 };
38
39 global_timer: timer@40002200 {
40 compatible = "arm,cortex-a9-global-timer";
41 reg = <0x40002200 0x20>;
42 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&clks VF610_CLK_PLATFORM_BUS>;
44 };
45 };
46 };
47};
48
49&adc0 {
50 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
51};
52
53&adc1 {
54 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
55};
56
57&can0 {
58 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
59};
60
61&can1 {
62 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
63};
64
65&dspi0 {
66 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
67};
68
69&edma0 {
70 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
72 interrupt-names = "edma-tx", "edma-err";
73};
74
75&edma1 {
76 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-names = "edma-tx", "edma-err";
79};
80
81&esdhc1 {
82 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
83};
84
85&fec0 {
86 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
87};
88
89&fec1 {
90 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
91};
92
93&ftm {
94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
95};
96
97&gpio1 {
98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
99};
100
101&gpio2 {
102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
103};
104
105&gpio3 {
106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
107};
108
109&gpio4 {
110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
111};
112
113&gpio5 {
114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
115};
116
117&i2c0 {
118 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
119};
120
121&pit {
122 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
123};
124
125&qspi0 {
126 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
127};
128
129&sai2 {
130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
131};
132
133&uart0 {
134 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
135};
136
137&uart1 {
138 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
139};
140
141&uart2 {
142 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
143};
144
145&uart3 {
146 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
147};
148
149&uart4 {
150 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
151};
152
153&uart5 {
154 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
155};
156
157&usbdev0 {
158 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
159};
160
161&usbh1 {
162 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
163};
164
165&usbphy0 {
166 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
167};
168
169&usbphy1 {
170 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
171};
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
index 7fb306679341..10ebe99e2751 100644
--- a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
@@ -9,38 +9,9 @@
9 9
10/dts-v1/; 10/dts-v1/;
11#include "vf610-colibri.dtsi" 11#include "vf610-colibri.dtsi"
12#include "vf-colibri-eval-v3.dtsi"
12 13
13/ { 14/ {
14 model = "Toradex Colibri VF61 on Colibri Evaluation Board"; 15 model = "Toradex Colibri VF61 on Colibri Evaluation Board";
15 compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; 16 compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
16 17}; \ No newline at end of file
17 chosen {
18 bootargs = "console=ttyLP0,115200";
19 };
20};
21
22&esdhc1 {
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_esdhc1>;
25 bus-width = <4>;
26 status = "okay";
27};
28
29&fec1 {
30 phy-mode = "rmii";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_fec1>;
33 status = "okay";
34};
35
36&uart0 {
37 status = "okay";
38};
39
40&uart1 {
41 status = "okay";
42};
43
44&uart2 {
45 status = "okay";
46};
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi
index 0cd83434b073..19fe045b8334 100644
--- a/arch/arm/boot/dts/vf610-colibri.dtsi
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -8,6 +8,7 @@
8 */ 8 */
9 9
10#include "vf610.dtsi" 10#include "vf610.dtsi"
11#include "vf-colibri.dtsi"
11 12
12/ { 13/ {
13 model = "Toradex Colibri VF61 COM"; 14 model = "Toradex Colibri VF61 COM";
@@ -16,108 +17,9 @@
16 memory { 17 memory {
17 reg = <0x80000000 0x10000000>; 18 reg = <0x80000000 0x10000000>;
18 }; 19 };
19
20 clocks {
21 enet_ext {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <50000000>;
25 };
26 };
27
28};
29
30&esdhc1 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_esdhc1>;
33 bus-width = <4>;
34};
35
36&fec1 {
37 phy-mode = "rmii";
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_fec1>;
40}; 20};
41 21
42&L2 { 22&L2 {
43 arm,data-latency = <2 1 2>; 23 arm,data-latency = <2 1 2>;
44 arm,tag-latency = <3 2 3>; 24 arm,tag-latency = <3 2 3>;
45}; 25};
46
47&uart0 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_uart0>;
50};
51
52&uart1 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_uart1>;
55};
56
57&uart2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_uart2>;
60};
61
62&usbdev0 {
63 disable-over-current;
64 status = "okay";
65};
66
67&usbh1 {
68 disable-over-current;
69 status = "okay";
70};
71
72&iomuxc {
73 vf610-colibri {
74 pinctrl_esdhc1: esdhc1grp {
75 fsl,pins = <
76 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
77 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
78 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
79 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
80 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
81 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
82 VF610_PAD_PTB20__GPIO_42 0x219d
83 >;
84 };
85
86 pinctrl_fec1: fec1grp {
87 fsl,pins = <
88 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
89 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
90 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
91 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
92 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
93 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
94 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
95 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
96 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
97 >;
98 };
99
100 pinctrl_uart0: uart0grp {
101 fsl,pins = <
102 VF610_PAD_PTB10__UART0_TX 0x21a2
103 VF610_PAD_PTB11__UART0_RX 0x21a1
104 >;
105 };
106
107 pinctrl_uart1: uart1grp {
108 fsl,pins = <
109 VF610_PAD_PTB4__UART1_TX 0x21a2
110 VF610_PAD_PTB5__UART1_RX 0x21a1
111 >;
112 };
113
114 pinctrl_uart2: uart2grp {
115 fsl,pins = <
116 VF610_PAD_PTD0__UART2_TX 0x21a2
117 VF610_PAD_PTD1__UART2_RX 0x21a1
118 VF610_PAD_PTD2__UART2_RTS 0x21a2
119 VF610_PAD_PTD3__UART2_CTS 0x21a1
120 >;
121 };
122 };
123};
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index 3fd1b74e1216..b0ce8b8b2e0e 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -23,14 +23,16 @@
23 reg = <0x80000000 0x10000000>; 23 reg = <0x80000000 0x10000000>;
24 }; 24 };
25 25
26 clocks { 26 enet_ext: enet_ext {
27 enet_ext { 27 compatible = "fixed-clock";
28 compatible = "fixed-clock"; 28 #clock-cells = <0>;
29 #clock-cells = <0>; 29 clock-frequency = <50000000>;
30 clock-frequency = <50000000>;
31 };
32 }; 30 };
31};
33 32
33&clks {
34 clocks = <&sxosc>, <&fxosc>, <&enet_ext>;
35 clock-names = "sxosc", "fxosc", "enet_ext";
34}; 36};
35 37
36&fec1 { 38&fec1 {
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 189b6975fe7d..a0f762159cb2 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -22,18 +22,16 @@
22 reg = <0x80000000 0x8000000>; 22 reg = <0x80000000 0x8000000>;
23 }; 23 };
24 24
25 clocks { 25 audio_ext: mclk_osc {
26 audio_ext { 26 compatible = "fixed-clock";
27 compatible = "fixed-clock"; 27 #clock-cells = <0>;
28 #clock-cells = <0>; 28 clock-frequency = <24576000>;
29 clock-frequency = <24576000>; 29 };
30 };
31 30
32 enet_ext { 31 enet_ext: eth_osc {
33 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
34 #clock-cells = <0>; 33 #clock-cells = <0>;
35 clock-frequency = <50000000>; 34 clock-frequency = <50000000>;
36 };
37 }; 35 };
38 36
39 regulators { 37 regulators {
@@ -95,6 +93,11 @@
95 status = "okay"; 93 status = "okay";
96}; 94};
97 95
96&clks {
97 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
98 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
99};
100
98&dspi0 { 101&dspi0 {
99 bus-num = <0>; 102 bus-num = <0>;
100 pinctrl-names = "default"; 103 pinctrl-names = "default";
@@ -112,10 +115,15 @@
112 }; 115 };
113}; 116};
114 117
118&edma0 {
119 status = "okay";
120};
121
115&esdhc1 { 122&esdhc1 {
116 pinctrl-names = "default"; 123 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_esdhc1>; 124 pinctrl-0 = <&pinctrl_esdhc1>;
118 bus-width = <4>; 125 bus-width = <4>;
126 cd-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
119 status = "okay"; 127 status = "okay";
120}; 128};
121 129
@@ -285,3 +293,19 @@
285 disable-over-current; 293 disable-over-current;
286 status = "okay"; 294 status = "okay";
287}; 295};
296
297&usbmisc0 {
298 status = "okay";
299};
300
301&usbmisc1 {
302 status = "okay";
303};
304
305&usbphy0 {
306 status = "okay";
307};
308
309&usbphy1 {
310 status = "okay";
311};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 4d2ec32de96f..5f8eb1bd782b 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -7,481 +7,19 @@
7 * (at your option) any later version. 7 * (at your option) any later version.
8 */ 8 */
9 9
10#include "skeleton.dtsi" 10#include "vf500.dtsi"
11#include "vf610-pinfunc.h"
12#include <dt-bindings/clock/vf610-clock.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14 11
15/ { 12&a5_cpu {
16 aliases { 13 next-level-cache = <&L2>;
17 can0 = &can0; 14};
18 can1 = &can1;
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 serial4 = &uart4;
24 serial5 = &uart5;
25 gpio0 = &gpio1;
26 gpio1 = &gpio2;
27 gpio2 = &gpio3;
28 gpio3 = &gpio4;
29 gpio4 = &gpio5;
30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 compatible = "arm,cortex-a5";
40 device_type = "cpu";
41 reg = <0x0>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 clocks {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 sxosc {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <32768>;
54 };
55
56 fxosc {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <24000000>;
60 };
61 };
62
63 soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 interrupt-parent = <&intc>;
68 ranges;
69
70 aips0: aips-bus@40000000 {
71 compatible = "fsl,aips-bus", "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 interrupt-parent = <&intc>;
75 reg = <0x40000000 0x70000>;
76 ranges;
77
78 intc: interrupt-controller@40002000 {
79 compatible = "arm,cortex-a9-gic";
80 #interrupt-cells = <3>;
81 interrupt-controller;
82 reg = <0x40003000 0x1000>,
83 <0x40002100 0x100>;
84 };
85
86 L2: l2-cache@40006000 {
87 compatible = "arm,pl310-cache";
88 reg = <0x40006000 0x1000>;
89 cache-unified;
90 cache-level = <2>;
91 arm,data-latency = <1 1 1>;
92 arm,tag-latency = <2 2 2>;
93 };
94
95 edma0: dma-controller@40018000 {
96 #dma-cells = <2>;
97 compatible = "fsl,vf610-edma";
98 reg = <0x40018000 0x2000>,
99 <0x40024000 0x1000>,
100 <0x40025000 0x1000>;
101 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
102 <0 9 IRQ_TYPE_LEVEL_HIGH>;
103 interrupt-names = "edma-tx", "edma-err";
104 dma-channels = <32>;
105 clock-names = "dmamux0", "dmamux1";
106 clocks = <&clks VF610_CLK_DMAMUX0>,
107 <&clks VF610_CLK_DMAMUX1>;
108 };
109
110 can0: flexcan@40020000 {
111 compatible = "fsl,vf610-flexcan";
112 reg = <0x40020000 0x4000>;
113 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&clks VF610_CLK_FLEXCAN0>,
115 <&clks VF610_CLK_FLEXCAN0>;
116 clock-names = "ipg", "per";
117 status = "disabled";
118 };
119
120 uart0: serial@40027000 {
121 compatible = "fsl,vf610-lpuart";
122 reg = <0x40027000 0x1000>;
123 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&clks VF610_CLK_UART0>;
125 clock-names = "ipg";
126 dmas = <&edma0 0 2>,
127 <&edma0 0 3>;
128 dma-names = "rx","tx";
129 status = "disabled";
130 };
131
132 uart1: serial@40028000 {
133 compatible = "fsl,vf610-lpuart";
134 reg = <0x40028000 0x1000>;
135 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clks VF610_CLK_UART1>;
137 clock-names = "ipg";
138 dmas = <&edma0 0 4>,
139 <&edma0 0 5>;
140 dma-names = "rx","tx";
141 status = "disabled";
142 };
143
144 uart2: serial@40029000 {
145 compatible = "fsl,vf610-lpuart";
146 reg = <0x40029000 0x1000>;
147 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&clks VF610_CLK_UART2>;
149 clock-names = "ipg";
150 dmas = <&edma0 0 6>,
151 <&edma0 0 7>;
152 dma-names = "rx","tx";
153 status = "disabled";
154 };
155
156 uart3: serial@4002a000 {
157 compatible = "fsl,vf610-lpuart";
158 reg = <0x4002a000 0x1000>;
159 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clks VF610_CLK_UART3>;
161 clock-names = "ipg";
162 dmas = <&edma0 0 8>,
163 <&edma0 0 9>;
164 dma-names = "rx","tx";
165 status = "disabled";
166 };
167
168 dspi0: dspi0@4002c000 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 compatible = "fsl,vf610-dspi";
172 reg = <0x4002c000 0x1000>;
173 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&clks VF610_CLK_DSPI0>;
175 clock-names = "dspi";
176 spi-num-chipselects = <5>;
177 status = "disabled";
178 };
179
180 sai2: sai@40031000 {
181 compatible = "fsl,vf610-sai";
182 reg = <0x40031000 0x1000>;
183 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&clks VF610_CLK_SAI2>;
185 clock-names = "sai";
186 dma-names = "tx", "rx";
187 dmas = <&edma0 0 21>,
188 <&edma0 0 20>;
189 status = "disabled";
190 };
191
192 pit: pit@40037000 {
193 compatible = "fsl,vf610-pit";
194 reg = <0x40037000 0x1000>;
195 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&clks VF610_CLK_PIT>;
197 clock-names = "pit";
198 };
199
200 pwm0: pwm@40038000 {
201 compatible = "fsl,vf610-ftm-pwm";
202 #pwm-cells = <3>;
203 reg = <0x40038000 0x1000>;
204 clock-names = "ftm_sys", "ftm_ext",
205 "ftm_fix", "ftm_cnt_clk_en";
206 clocks = <&clks VF610_CLK_FTM0>,
207 <&clks VF610_CLK_FTM0_EXT_SEL>,
208 <&clks VF610_CLK_FTM0_FIX_SEL>,
209 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
210 status = "disabled";
211 };
212
213 adc0: adc@4003b000 {
214 compatible = "fsl,vf610-adc";
215 reg = <0x4003b000 0x1000>;
216 interrupts = <0 53 0x04>;
217 clocks = <&clks VF610_CLK_ADC0>;
218 clock-names = "adc";
219 status = "disabled";
220 };
221
222 wdog@4003e000 {
223 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
224 reg = <0x4003e000 0x1000>;
225 clocks = <&clks VF610_CLK_WDT>;
226 clock-names = "wdog";
227 };
228
229 qspi0: quadspi@40044000 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,vf610-qspi";
233 reg = <0x40044000 0x1000>;
234 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clks VF610_CLK_QSPI0_EN>,
236 <&clks VF610_CLK_QSPI0>;
237 clock-names = "qspi_en", "qspi";
238 status = "disabled";
239 };
240
241 iomuxc: iomuxc@40048000 {
242 compatible = "fsl,vf610-iomuxc";
243 reg = <0x40048000 0x1000>;
244 #gpio-range-cells = <3>;
245 };
246
247 gpio1: gpio@40049000 {
248 compatible = "fsl,vf610-gpio";
249 reg = <0x40049000 0x1000 0x400ff000 0x40>;
250 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
251 gpio-controller;
252 #gpio-cells = <2>;
253 interrupt-controller;
254 #interrupt-cells = <2>;
255 gpio-ranges = <&iomuxc 0 0 32>;
256 };
257
258 gpio2: gpio@4004a000 {
259 compatible = "fsl,vf610-gpio";
260 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
261 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 gpio-ranges = <&iomuxc 0 32 32>;
267 };
268
269 gpio3: gpio@4004b000 {
270 compatible = "fsl,vf610-gpio";
271 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
272 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 gpio-ranges = <&iomuxc 0 64 32>;
278 };
279
280 gpio4: gpio@4004c000 {
281 compatible = "fsl,vf610-gpio";
282 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
283 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
284 gpio-controller;
285 #gpio-cells = <2>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 gpio-ranges = <&iomuxc 0 96 32>;
289 };
290
291 gpio5: gpio@4004d000 {
292 compatible = "fsl,vf610-gpio";
293 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
294 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 gpio-ranges = <&iomuxc 0 128 7>;
300 };
301
302 anatop: anatop@40050000 {
303 compatible = "fsl,vf610-anatop", "syscon";
304 reg = <0x40050000 0x400>;
305 };
306
307 usbphy0: usbphy@40050800 {
308 compatible = "fsl,vf610-usbphy";
309 reg = <0x40050800 0x400>;
310 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clks VF610_CLK_USBPHY0>;
312 fsl,anatop = <&anatop>;
313 };
314
315 usbphy1: usbphy@40050c00 {
316 compatible = "fsl,vf610-usbphy";
317 reg = <0x40050c00 0x400>;
318 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks VF610_CLK_USBPHY1>;
320 fsl,anatop = <&anatop>;
321 };
322
323 i2c0: i2c@40066000 {
324 #address-cells = <1>;
325 #size-cells = <0>;
326 compatible = "fsl,vf610-i2c";
327 reg = <0x40066000 0x1000>;
328 interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clks VF610_CLK_I2C0>;
330 clock-names = "ipg";
331 dmas = <&edma0 0 50>,
332 <&edma0 0 51>;
333 dma-names = "rx","tx";
334 status = "disabled";
335 };
336
337 clks: ccm@4006b000 {
338 compatible = "fsl,vf610-ccm";
339 reg = <0x4006b000 0x1000>;
340 #clock-cells = <1>;
341 };
342
343 usbdev0: usb@40034000 {
344 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
345 reg = <0x40034000 0x800>;
346 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks VF610_CLK_USBC0>;
348 fsl,usbphy = <&usbphy0>;
349 fsl,usbmisc = <&usbmisc0 0>;
350 dr_mode = "peripheral";
351 status = "disabled";
352 };
353
354 usbmisc0: usb@40034800 {
355 #index-cells = <1>;
356 compatible = "fsl,vf610-usbmisc";
357 reg = <0x40034800 0x200>;
358 clocks = <&clks VF610_CLK_USBC0>;
359 };
360 };
361
362 aips1: aips-bus@40080000 {
363 compatible = "fsl,aips-bus", "simple-bus";
364 #address-cells = <1>;
365 #size-cells = <1>;
366 reg = <0x40080000 0x80000>;
367 ranges;
368
369 edma1: dma-controller@40098000 {
370 #dma-cells = <2>;
371 compatible = "fsl,vf610-edma";
372 reg = <0x40098000 0x2000>,
373 <0x400a1000 0x1000>,
374 <0x400a2000 0x1000>;
375 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
376 <0 11 IRQ_TYPE_LEVEL_HIGH>;
377 interrupt-names = "edma-tx", "edma-err";
378 dma-channels = <32>;
379 clock-names = "dmamux0", "dmamux1";
380 clocks = <&clks VF610_CLK_DMAMUX2>,
381 <&clks VF610_CLK_DMAMUX3>;
382 };
383
384 uart4: serial@400a9000 {
385 compatible = "fsl,vf610-lpuart";
386 reg = <0x400a9000 0x1000>;
387 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks VF610_CLK_UART4>;
389 clock-names = "ipg";
390 status = "disabled";
391 };
392
393 uart5: serial@400aa000 {
394 compatible = "fsl,vf610-lpuart";
395 reg = <0x400aa000 0x1000>;
396 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clks VF610_CLK_UART5>;
398 clock-names = "ipg";
399 status = "disabled";
400 };
401
402 adc1: adc@400bb000 {
403 compatible = "fsl,vf610-adc";
404 reg = <0x400bb000 0x1000>;
405 interrupts = <0 54 0x04>;
406 clocks = <&clks VF610_CLK_ADC1>;
407 clock-names = "adc";
408 status = "disabled";
409 };
410
411 esdhc1: esdhc@400b2000 {
412 compatible = "fsl,imx53-esdhc";
413 reg = <0x400b2000 0x1000>;
414 interrupts = <0 28 0x04>;
415 clocks = <&clks VF610_CLK_IPG_BUS>,
416 <&clks VF610_CLK_PLATFORM_BUS>,
417 <&clks VF610_CLK_ESDHC1>;
418 clock-names = "ipg", "ahb", "per";
419 status = "disabled";
420 };
421
422 usbh1: usb@400b4000 {
423 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
424 reg = <0x400b4000 0x800>;
425 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks VF610_CLK_USBC1>;
427 fsl,usbphy = <&usbphy1>;
428 fsl,usbmisc = <&usbmisc1 0>;
429 dr_mode = "host";
430 status = "disabled";
431 };
432
433 usbmisc1: usb@400b4800 {
434 #index-cells = <1>;
435 compatible = "fsl,vf610-usbmisc";
436 reg = <0x400b4800 0x200>;
437 clocks = <&clks VF610_CLK_USBC1>;
438 };
439
440 ftm: ftm@400b8000 {
441 compatible = "fsl,ftm-timer";
442 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
443 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
444 clock-names = "ftm-evt", "ftm-src",
445 "ftm-evt-counter-en", "ftm-src-counter-en";
446 clocks = <&clks VF610_CLK_FTM2>,
447 <&clks VF610_CLK_FTM3>,
448 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
449 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
450 status = "disabled";
451 };
452
453 fec0: ethernet@400d0000 {
454 compatible = "fsl,mvf600-fec";
455 reg = <0x400d0000 0x1000>;
456 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clks VF610_CLK_ENET0>,
458 <&clks VF610_CLK_ENET0>,
459 <&clks VF610_CLK_ENET>;
460 clock-names = "ipg", "ahb", "ptp";
461 status = "disabled";
462 };
463
464 fec1: ethernet@400d1000 {
465 compatible = "fsl,mvf600-fec";
466 reg = <0x400d1000 0x1000>;
467 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&clks VF610_CLK_ENET1>,
469 <&clks VF610_CLK_ENET1>,
470 <&clks VF610_CLK_ENET>;
471 clock-names = "ipg", "ahb", "ptp";
472 status = "disabled";
473 };
474
475 can1: flexcan@400d4000 {
476 compatible = "fsl,vf610-flexcan";
477 reg = <0x400d4000 0x4000>;
478 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clks VF610_CLK_FLEXCAN1>,
480 <&clks VF610_CLK_FLEXCAN1>;
481 clock-names = "ipg", "per";
482 status = "disabled";
483 };
484 15
485 }; 16&aips0 {
17 L2: l2-cache@40006000 {
18 compatible = "arm,pl310-cache";
19 reg = <0x40006000 0x1000>;
20 cache-unified;
21 cache-level = <2>;
22 arm,data-latency = <1 1 1>;
23 arm,tag-latency = <2 2 2>;
486 }; 24 };
487}; 25};
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
new file mode 100644
index 000000000000..505969ae8093
--- /dev/null
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -0,0 +1,437 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "vf610-pinfunc.h"
11#include <dt-bindings/clock/vf610-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 aliases {
17 can0 = &can0;
18 can1 = &can1;
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 serial4 = &uart4;
24 serial5 = &uart5;
25 gpio0 = &gpio1;
26 gpio1 = &gpio2;
27 gpio2 = &gpio3;
28 gpio3 = &gpio4;
29 gpio4 = &gpio5;
30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1;
32 };
33
34 fxosc: fxosc {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <24000000>;
38 };
39
40 sxosc: sxosc {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32768>;
44 };
45
46 soc {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "simple-bus";
50 ranges;
51
52 aips0: aips-bus@40000000 {
53 compatible = "fsl,aips-bus", "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges;
57
58 edma0: dma-controller@40018000 {
59 #dma-cells = <2>;
60 compatible = "fsl,vf610-edma";
61 reg = <0x40018000 0x2000>,
62 <0x40024000 0x1000>,
63 <0x40025000 0x1000>;
64 dma-channels = <32>;
65 clock-names = "dmamux0", "dmamux1";
66 clocks = <&clks VF610_CLK_DMAMUX0>,
67 <&clks VF610_CLK_DMAMUX1>;
68 status = "disabled";
69 };
70
71 can0: flexcan@40020000 {
72 compatible = "fsl,vf610-flexcan";
73 reg = <0x40020000 0x4000>;
74 clocks = <&clks VF610_CLK_FLEXCAN0>,
75 <&clks VF610_CLK_FLEXCAN0>;
76 clock-names = "ipg", "per";
77 status = "disabled";
78 };
79
80 uart0: serial@40027000 {
81 compatible = "fsl,vf610-lpuart";
82 reg = <0x40027000 0x1000>;
83 clocks = <&clks VF610_CLK_UART0>;
84 clock-names = "ipg";
85 dmas = <&edma0 0 2>,
86 <&edma0 0 3>;
87 dma-names = "rx","tx";
88 status = "disabled";
89 };
90
91 uart1: serial@40028000 {
92 compatible = "fsl,vf610-lpuart";
93 reg = <0x40028000 0x1000>;
94 clocks = <&clks VF610_CLK_UART1>;
95 clock-names = "ipg";
96 dmas = <&edma0 0 4>,
97 <&edma0 0 5>;
98 dma-names = "rx","tx";
99 status = "disabled";
100 };
101
102 uart2: serial@40029000 {
103 compatible = "fsl,vf610-lpuart";
104 reg = <0x40029000 0x1000>;
105 clocks = <&clks VF610_CLK_UART2>;
106 clock-names = "ipg";
107 dmas = <&edma0 0 6>,
108 <&edma0 0 7>;
109 dma-names = "rx","tx";
110 status = "disabled";
111 };
112
113 uart3: serial@4002a000 {
114 compatible = "fsl,vf610-lpuart";
115 reg = <0x4002a000 0x1000>;
116 clocks = <&clks VF610_CLK_UART3>;
117 clock-names = "ipg";
118 dmas = <&edma0 0 8>,
119 <&edma0 0 9>;
120 dma-names = "rx","tx";
121 status = "disabled";
122 };
123
124 dspi0: dspi0@4002c000 {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 compatible = "fsl,vf610-dspi";
128 reg = <0x4002c000 0x1000>;
129 clocks = <&clks VF610_CLK_DSPI0>;
130 clock-names = "dspi";
131 spi-num-chipselects = <5>;
132 status = "disabled";
133 };
134
135 sai2: sai@40031000 {
136 compatible = "fsl,vf610-sai";
137 reg = <0x40031000 0x1000>;
138 clocks = <&clks VF610_CLK_SAI2>;
139 clock-names = "sai";
140 dma-names = "tx", "rx";
141 dmas = <&edma0 0 21>,
142 <&edma0 0 20>;
143 status = "disabled";
144 };
145
146 pit: pit@40037000 {
147 compatible = "fsl,vf610-pit";
148 reg = <0x40037000 0x1000>;
149 clocks = <&clks VF610_CLK_PIT>;
150 clock-names = "pit";
151 };
152
153 pwm0: pwm@40038000 {
154 compatible = "fsl,vf610-ftm-pwm";
155 #pwm-cells = <3>;
156 reg = <0x40038000 0x1000>;
157 clock-names = "ftm_sys", "ftm_ext",
158 "ftm_fix", "ftm_cnt_clk_en";
159 clocks = <&clks VF610_CLK_FTM0>,
160 <&clks VF610_CLK_FTM0_EXT_SEL>,
161 <&clks VF610_CLK_FTM0_FIX_SEL>,
162 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
163 status = "disabled";
164 };
165
166 pwm1: pwm@40039000 {
167 compatible = "fsl,vf610-ftm-pwm";
168 #pwm-cells = <3>;
169 reg = <0x40039000 0x1000>;
170 clock-names = "ftm_sys", "ftm_ext",
171 "ftm_fix", "ftm_cnt_clk_en";
172 clocks = <&clks VF610_CLK_FTM1>,
173 <&clks VF610_CLK_FTM1_EXT_SEL>,
174 <&clks VF610_CLK_FTM1_FIX_SEL>,
175 <&clks VF610_CLK_FTM1_EXT_FIX_EN>;
176 status = "disabled";
177 };
178
179 adc0: adc@4003b000 {
180 compatible = "fsl,vf610-adc";
181 reg = <0x4003b000 0x1000>;
182 clocks = <&clks VF610_CLK_ADC0>;
183 clock-names = "adc";
184 status = "disabled";
185 };
186
187 wdog@4003e000 {
188 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
189 reg = <0x4003e000 0x1000>;
190 clocks = <&clks VF610_CLK_WDT>;
191 clock-names = "wdog";
192 status = "disabled";
193 };
194
195 qspi0: quadspi@40044000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "fsl,vf610-qspi";
199 reg = <0x40044000 0x1000>;
200 clocks = <&clks VF610_CLK_QSPI0_EN>,
201 <&clks VF610_CLK_QSPI0>;
202 clock-names = "qspi_en", "qspi";
203 status = "disabled";
204 };
205
206 iomuxc: iomuxc@40048000 {
207 compatible = "fsl,vf610-iomuxc";
208 reg = <0x40048000 0x1000>;
209 #gpio-range-cells = <3>;
210 };
211
212 gpio1: gpio@40049000 {
213 compatible = "fsl,vf610-gpio";
214 reg = <0x40049000 0x1000 0x400ff000 0x40>;
215 gpio-controller;
216 #gpio-cells = <2>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 gpio-ranges = <&iomuxc 0 0 32>;
220 };
221
222 gpio2: gpio@4004a000 {
223 compatible = "fsl,vf610-gpio";
224 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
229 gpio-ranges = <&iomuxc 0 32 32>;
230 };
231
232 gpio3: gpio@4004b000 {
233 compatible = "fsl,vf610-gpio";
234 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 gpio-ranges = <&iomuxc 0 64 32>;
240 };
241
242 gpio4: gpio@4004c000 {
243 compatible = "fsl,vf610-gpio";
244 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 gpio-ranges = <&iomuxc 0 96 32>;
250 };
251
252 gpio5: gpio@4004d000 {
253 compatible = "fsl,vf610-gpio";
254 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 gpio-ranges = <&iomuxc 0 128 7>;
260 };
261
262 anatop: anatop@40050000 {
263 compatible = "fsl,vf610-anatop", "syscon";
264 reg = <0x40050000 0x400>;
265 };
266
267 usbphy0: usbphy@40050800 {
268 compatible = "fsl,vf610-usbphy";
269 reg = <0x40050800 0x400>;
270 clocks = <&clks VF610_CLK_USBPHY0>;
271 fsl,anatop = <&anatop>;
272 status = "disabled";
273 };
274
275 usbphy1: usbphy@40050c00 {
276 compatible = "fsl,vf610-usbphy";
277 reg = <0x40050c00 0x400>;
278 clocks = <&clks VF610_CLK_USBPHY1>;
279 fsl,anatop = <&anatop>;
280 status = "disabled";
281 };
282
283 i2c0: i2c@40066000 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "fsl,vf610-i2c";
287 reg = <0x40066000 0x1000>;
288 clocks = <&clks VF610_CLK_I2C0>;
289 clock-names = "ipg";
290 dmas = <&edma0 0 50>,
291 <&edma0 0 51>;
292 dma-names = "rx","tx";
293 status = "disabled";
294 };
295
296 clks: ccm@4006b000 {
297 compatible = "fsl,vf610-ccm";
298 reg = <0x4006b000 0x1000>;
299 clocks = <&sxosc>, <&fxosc>;
300 clock-names = "sxosc", "fxosc";
301 #clock-cells = <1>;
302 };
303
304 usbdev0: usb@40034000 {
305 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
306 reg = <0x40034000 0x800>;
307 clocks = <&clks VF610_CLK_USBC0>;
308 fsl,usbphy = <&usbphy0>;
309 fsl,usbmisc = <&usbmisc0 0>;
310 dr_mode = "peripheral";
311 status = "disabled";
312 };
313
314 usbmisc0: usb@40034800 {
315 #index-cells = <1>;
316 compatible = "fsl,vf610-usbmisc";
317 reg = <0x40034800 0x200>;
318 clocks = <&clks VF610_CLK_USBC0>;
319 status = "disabled";
320 };
321 };
322
323 aips1: aips-bus@40080000 {
324 compatible = "fsl,aips-bus", "simple-bus";
325 #address-cells = <1>;
326 #size-cells = <1>;
327 ranges;
328
329 edma1: dma-controller@40098000 {
330 #dma-cells = <2>;
331 compatible = "fsl,vf610-edma";
332 reg = <0x40098000 0x2000>,
333 <0x400a1000 0x1000>,
334 <0x400a2000 0x1000>;
335 dma-channels = <32>;
336 clock-names = "dmamux0", "dmamux1";
337 clocks = <&clks VF610_CLK_DMAMUX2>,
338 <&clks VF610_CLK_DMAMUX3>;
339 status = "disabled";
340 };
341
342 uart4: serial@400a9000 {
343 compatible = "fsl,vf610-lpuart";
344 reg = <0x400a9000 0x1000>;
345 clocks = <&clks VF610_CLK_UART4>;
346 clock-names = "ipg";
347 status = "disabled";
348 };
349
350 uart5: serial@400aa000 {
351 compatible = "fsl,vf610-lpuart";
352 reg = <0x400aa000 0x1000>;
353 clocks = <&clks VF610_CLK_UART5>;
354 clock-names = "ipg";
355 status = "disabled";
356 };
357
358 adc1: adc@400bb000 {
359 compatible = "fsl,vf610-adc";
360 reg = <0x400bb000 0x1000>;
361 clocks = <&clks VF610_CLK_ADC1>;
362 clock-names = "adc";
363 status = "disabled";
364 };
365
366 esdhc1: esdhc@400b2000 {
367 compatible = "fsl,imx53-esdhc";
368 reg = <0x400b2000 0x1000>;
369 clocks = <&clks VF610_CLK_IPG_BUS>,
370 <&clks VF610_CLK_PLATFORM_BUS>,
371 <&clks VF610_CLK_ESDHC1>;
372 clock-names = "ipg", "ahb", "per";
373 status = "disabled";
374 };
375
376 usbh1: usb@400b4000 {
377 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
378 reg = <0x400b4000 0x800>;
379 clocks = <&clks VF610_CLK_USBC1>;
380 fsl,usbphy = <&usbphy1>;
381 fsl,usbmisc = <&usbmisc1 0>;
382 dr_mode = "host";
383 status = "disabled";
384 };
385
386 usbmisc1: usb@400b4800 {
387 #index-cells = <1>;
388 compatible = "fsl,vf610-usbmisc";
389 reg = <0x400b4800 0x200>;
390 clocks = <&clks VF610_CLK_USBC1>;
391 status = "disabled";
392 };
393
394 ftm: ftm@400b8000 {
395 compatible = "fsl,ftm-timer";
396 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
397 clock-names = "ftm-evt", "ftm-src",
398 "ftm-evt-counter-en", "ftm-src-counter-en";
399 clocks = <&clks VF610_CLK_FTM2>,
400 <&clks VF610_CLK_FTM3>,
401 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
402 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
403 status = "disabled";
404 };
405
406 fec0: ethernet@400d0000 {
407 compatible = "fsl,mvf600-fec";
408 reg = <0x400d0000 0x1000>;
409 clocks = <&clks VF610_CLK_ENET0>,
410 <&clks VF610_CLK_ENET0>,
411 <&clks VF610_CLK_ENET>;
412 clock-names = "ipg", "ahb", "ptp";
413 status = "disabled";
414 };
415
416 fec1: ethernet@400d1000 {
417 compatible = "fsl,mvf600-fec";
418 reg = <0x400d1000 0x1000>;
419 clocks = <&clks VF610_CLK_ENET1>,
420 <&clks VF610_CLK_ENET1>,
421 <&clks VF610_CLK_ENET>;
422 clock-names = "ipg", "ahb", "ptp";
423 status = "disabled";
424 };
425
426 can1: flexcan@400d4000 {
427 compatible = "fsl,vf610-flexcan";
428 reg = <0x400d4000 0x4000>;
429 clocks = <&clks VF610_CLK_FLEXCAN1>,
430 <&clks VF610_CLK_FLEXCAN1>;
431 clock-names = "ipg", "per";
432 status = "disabled";
433 };
434
435 };
436 };
437};
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index e688741c89aa..e6b0007355f8 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -97,6 +97,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y
97# CONFIG_HW_RANDOM is not set 97# CONFIG_HW_RANDOM is not set
98CONFIG_I2C_CHARDEV=y 98CONFIG_I2C_CHARDEV=y
99CONFIG_I2C_IMX=y 99CONFIG_I2C_IMX=y
100CONFIG_SPI=y
100CONFIG_SPI_IMX=y 101CONFIG_SPI_IMX=y
101CONFIG_SPI_SPIDEV=y 102CONFIG_SPI_SPIDEV=y
102CONFIG_GPIO_SYSFS=y 103CONFIG_GPIO_SYSFS=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 8fca6e276b69..6790f1b3f3a1 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -158,6 +158,7 @@ CONFIG_I2C_CHARDEV=y
158CONFIG_I2C_ALGOPCF=m 158CONFIG_I2C_ALGOPCF=m
159CONFIG_I2C_ALGOPCA=m 159CONFIG_I2C_ALGOPCA=m
160CONFIG_I2C_IMX=y 160CONFIG_I2C_IMX=y
161CONFIG_SPI=y
161CONFIG_SPI_IMX=y 162CONFIG_SPI_IMX=y
162CONFIG_GPIO_SYSFS=y 163CONFIG_GPIO_SYSFS=y
163CONFIG_GPIO_MC9S08DZ60=y 164CONFIG_GPIO_MC9S08DZ60=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 11b2957f792b..e8627e04e1e6 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -633,12 +633,41 @@ config SOC_VF610
633 bool "Vybrid Family VF610 support" 633 bool "Vybrid Family VF610 support"
634 select ARM_GIC 634 select ARM_GIC
635 select PINCTRL_VF610 635 select PINCTRL_VF610
636 select VF_PIT_TIMER
637 select PL310_ERRATA_769419 if CACHE_L2X0 636 select PL310_ERRATA_769419 if CACHE_L2X0
638 637
639 help 638 help
640 This enable support for Freescale Vybrid VF610 processor. 639 This enable support for Freescale Vybrid VF610 processor.
641 640
641choice
642 prompt "Clocksource for scheduler clock"
643 depends on SOC_VF610
644 default VF_USE_ARM_GLOBAL_TIMER
645
646 config VF_USE_ARM_GLOBAL_TIMER
647 bool "Use ARM Global Timer"
648 select ARM_GLOBAL_TIMER
649 select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
650 help
651 Use the ARM Global Timer as clocksource
652
653 config VF_USE_PIT_TIMER
654 bool "Use PIT timer"
655 select VF_PIT_TIMER
656 help
657 Use SoC Periodic Interrupt Timer (PIT) as clocksource
658
659endchoice
660
661config SOC_LS1021A
662 bool "Freescale LS1021A support"
663 select ARM_GIC
664 select HAVE_ARM_ARCH_TIMER
665 select PCI_DOMAINS if PCI
666 select ZONE_DMA if ARM_LPAE
667
668 help
669 This enable support for Freescale LS1021A processor.
670
642endif 671endif
643 672
644source "arch/arm/mach-imx/devices/Kconfig" 673source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 6e4fcd8339cd..f5ac685a29fc 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
12obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o 12obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
13 13
14imx5-pm-$(CONFIG_PM) += pm-imx5.o 14imx5-pm-$(CONFIG_PM) += pm-imx5.o
15obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y) 15obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o clk-cpu.o $(imx5-pm-y)
16 16
17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ 17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
18 clk-pfd.o clk-busy.o clk.o \ 18 clk-pfd.o clk-busy.o clk.o \
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
89obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o 89obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
90obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o 90obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
91obj-$(CONFIG_HAVE_IMX_SRC) += src.o 91obj-$(CONFIG_HAVE_IMX_SRC) += src.o
92ifdef CONFIG_SOC_IMX6 92ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
93AFLAGS_headsmp.o :=-Wa,-march=armv7-a 93AFLAGS_headsmp.o :=-Wa,-march=armv7-a
94obj-$(CONFIG_SMP) += headsmp.o platsmp.o 94obj-$(CONFIG_SMP) += headsmp.o platsmp.o
95obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 95obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
@@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
110 110
111obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o 111obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
112 112
113obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
114
113obj-y += devices/ 115obj-y += devices/
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 8259a625a920..7f262fe4ba77 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -30,8 +30,11 @@
30#define ANADIG_DIGPROG_IMX6SL 0x280 30#define ANADIG_DIGPROG_IMX6SL 0x280
31 31
32#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 32#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
33#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
33#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 34#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
34#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000 35#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
36/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
37#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
35#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000 38#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
36#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000 39#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
37 40
@@ -56,16 +59,43 @@ static void imx_anatop_enable_fet_odrive(bool enable)
56 BM_ANADIG_REG_CORE_FET_ODRIVE); 59 BM_ANADIG_REG_CORE_FET_ODRIVE);
57} 60}
58 61
62static inline void imx_anatop_enable_2p5_pulldown(bool enable)
63{
64 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
65 BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
66}
67
68static inline void imx_anatop_disconnect_high_snvs(bool enable)
69{
70 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
71 BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
72}
73
59void imx_anatop_pre_suspend(void) 74void imx_anatop_pre_suspend(void)
60{ 75{
61 imx_anatop_enable_weak2p5(true); 76 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
77 imx_anatop_enable_2p5_pulldown(true);
78 else
79 imx_anatop_enable_weak2p5(true);
80
62 imx_anatop_enable_fet_odrive(true); 81 imx_anatop_enable_fet_odrive(true);
82
83 if (cpu_is_imx6sl())
84 imx_anatop_disconnect_high_snvs(true);
63} 85}
64 86
65void imx_anatop_post_resume(void) 87void imx_anatop_post_resume(void)
66{ 88{
89 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
90 imx_anatop_enable_2p5_pulldown(false);
91 else
92 imx_anatop_enable_weak2p5(false);
93
67 imx_anatop_enable_fet_odrive(false); 94 imx_anatop_enable_fet_odrive(false);
68 imx_anatop_enable_weak2p5(false); 95
96 if (cpu_is_imx6sl())
97 imx_anatop_disconnect_high_snvs(false);
98
69} 99}
70 100
71static void imx_anatop_usb_chrg_detect_disable(void) 101static void imx_anatop_usb_chrg_detect_disable(void)
diff --git a/arch/arm/mach-imx/clk-cpu.c b/arch/arm/mach-imx/clk-cpu.c
new file mode 100644
index 000000000000..aa1c345e2a19
--- /dev/null
+++ b/arch/arm/mach-imx/clk-cpu.c
@@ -0,0 +1,107 @@
1/*
2 * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
14#include <linux/slab.h>
15
16struct clk_cpu {
17 struct clk_hw hw;
18 struct clk *div;
19 struct clk *mux;
20 struct clk *pll;
21 struct clk *step;
22};
23
24static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
25{
26 return container_of(hw, struct clk_cpu, hw);
27}
28
29static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
30 unsigned long parent_rate)
31{
32 struct clk_cpu *cpu = to_clk_cpu(hw);
33
34 return clk_get_rate(cpu->div);
35}
36
37static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
38 unsigned long *prate)
39{
40 struct clk_cpu *cpu = to_clk_cpu(hw);
41
42 return clk_round_rate(cpu->pll, rate);
43}
44
45static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
46 unsigned long parent_rate)
47{
48 struct clk_cpu *cpu = to_clk_cpu(hw);
49 int ret;
50
51 /* switch to PLL bypass clock */
52 ret = clk_set_parent(cpu->mux, cpu->step);
53 if (ret)
54 return ret;
55
56 /* reprogram PLL */
57 ret = clk_set_rate(cpu->pll, rate);
58 if (ret) {
59 clk_set_parent(cpu->mux, cpu->pll);
60 return ret;
61 }
62 /* switch back to PLL clock */
63 clk_set_parent(cpu->mux, cpu->pll);
64
65 /* Ensure the divider is what we expect */
66 clk_set_rate(cpu->div, rate);
67
68 return 0;
69}
70
71static const struct clk_ops clk_cpu_ops = {
72 .recalc_rate = clk_cpu_recalc_rate,
73 .round_rate = clk_cpu_round_rate,
74 .set_rate = clk_cpu_set_rate,
75};
76
77struct clk *imx_clk_cpu(const char *name, const char *parent_name,
78 struct clk *div, struct clk *mux, struct clk *pll,
79 struct clk *step)
80{
81 struct clk_cpu *cpu;
82 struct clk *clk;
83 struct clk_init_data init;
84
85 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
86 if (!cpu)
87 return ERR_PTR(-ENOMEM);
88
89 cpu->div = div;
90 cpu->mux = mux;
91 cpu->pll = pll;
92 cpu->step = step;
93
94 init.name = name;
95 init.ops = &clk_cpu_ops;
96 init.flags = 0;
97 init.parent_names = &parent_name;
98 init.num_parents = 1;
99
100 cpu->hw.init = &init;
101
102 clk = clk_register(NULL, &cpu->hw);
103 if (IS_ERR(clk))
104 kfree(cpu);
105
106 return clk;
107}
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 72d65214223e..0f7e536147cb 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -125,6 +125,8 @@ static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw",
125static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", }; 125static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
126static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; 126static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
127static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; 127static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
128static const char *step_sels[] = { "lp_apm", };
129static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
128 130
129static struct clk *clk[IMX5_CLK_END]; 131static struct clk *clk[IMX5_CLK_END];
130static struct clk_onecell_data clk_data; 132static struct clk_onecell_data clk_data;
@@ -193,7 +195,9 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
193 clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); 195 clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
194 clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, 196 clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
195 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); 197 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
196 clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3); 198 clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
199 clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
200 clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
197 clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); 201 clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
198 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); 202 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
199 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); 203 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
@@ -537,6 +541,11 @@ static void __init mx53_clocks_init(struct device_node *np)
537 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); 541 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
538 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, 542 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
539 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); 543 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
544 clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf",
545 clk[IMX5_CLK_CPU_PODF],
546 clk[IMX5_CLK_CPU_PODF_SEL],
547 clk[IMX5_CLK_PLL1_SW],
548 clk[IMX5_CLK_STEP_SEL]);
540 549
541 imx_check_clocks(clk, ARRAY_SIZE(clk)); 550 imx_check_clocks(clk, ARRAY_SIZE(clk));
542 551
@@ -551,6 +560,9 @@ static void __init mx53_clocks_init(struct device_node *np)
551 /* move can bus clk to 24MHz */ 560 /* move can bus clk to 24MHz */
552 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); 561 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
553 562
563 /* make sure step clock is running from 24MHz */
564 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
565
554 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); 566 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
555 imx_print_silicon_rev("i.MX53", mx53_revision()); 567 imx_print_silicon_rev("i.MX53", mx53_revision());
556 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); 568 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index a17818475050..5937ddee1a99 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -58,8 +58,14 @@
58#define PFD_PLL1_BASE (anatop_base + 0x2b0) 58#define PFD_PLL1_BASE (anatop_base + 0x2b0)
59#define PFD_PLL2_BASE (anatop_base + 0x100) 59#define PFD_PLL2_BASE (anatop_base + 0x100)
60#define PFD_PLL3_BASE (anatop_base + 0xf0) 60#define PFD_PLL3_BASE (anatop_base + 0xf0)
61#define PLL1_CTRL (anatop_base + 0x270)
62#define PLL2_CTRL (anatop_base + 0x30)
61#define PLL3_CTRL (anatop_base + 0x10) 63#define PLL3_CTRL (anatop_base + 0x10)
64#define PLL4_CTRL (anatop_base + 0x70)
65#define PLL5_CTRL (anatop_base + 0xe0)
66#define PLL6_CTRL (anatop_base + 0xa0)
62#define PLL7_CTRL (anatop_base + 0x20) 67#define PLL7_CTRL (anatop_base + 0x20)
68#define ANA_MISC1 (anatop_base + 0x160)
63 69
64static void __iomem *anatop_base; 70static void __iomem *anatop_base;
65static void __iomem *ccm_base; 71static void __iomem *ccm_base;
@@ -67,25 +73,34 @@ static void __iomem *ccm_base;
67/* sources for multiplexer clocks, this is used multiple times */ 73/* sources for multiplexer clocks, this is used multiple times */
68static const char *fast_sels[] = { "firc", "fxosc", }; 74static const char *fast_sels[] = { "firc", "fxosc", };
69static const char *slow_sels[] = { "sirc_32k", "sxosc", }; 75static const char *slow_sels[] = { "sirc_32k", "sxosc", };
70static const char *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; 76static const char *pll1_sels[] = { "pll1_sys", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
71static const char *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; 77static const char *pll2_sels[] = { "pll2_bus", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
72static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; 78static const char *pll_bypass_src_sels[] = { "fast_clk_sel", "lvds1_in", };
79static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
80static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
81static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
82static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
83static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
84static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
85static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
86static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_bus", "pll1_pfd_sel", "pll3_usb_otg", };
73static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; 87static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", };
74static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; 88static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
75static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; 89static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
76static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; 90static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", };
77static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; 91static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", };
78static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; 92static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
79static const char *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; 93static const char *qspi_sels[] = { "pll3_usb_otg", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
80static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; 94static const char *esdhc_sels[] = { "pll3_usb_otg", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
81static const char *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; 95static const char *dcu_sels[] = { "pll1_pfd2", "pll3_usb_otg", };
82static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; 96static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", };
83static const char *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; 97static const char *vadc_sels[] = { "pll6_video_div", "pll3_usb_otg_div", "pll3_usb_otg", };
84/* FTM counter clock source, not module clock */ 98/* FTM counter clock source, not module clock */
85static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; 99static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
86static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; 100static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
87 101
88static struct clk_div_table pll4_main_div_table[] = { 102
103static struct clk_div_table pll4_audio_div_table[] = {
89 { .val = 0, .div = 1 }, 104 { .val = 0, .div = 1 },
90 { .val = 1, .div = 2 }, 105 { .val = 1, .div = 2 },
91 { .val = 2, .div = 6 }, 106 { .val = 2, .div = 6 },
@@ -105,6 +120,17 @@ static unsigned int const clks_init_on[] __initconst = {
105 VF610_CLK_DDR_SEL, 120 VF610_CLK_DDR_SEL,
106}; 121};
107 122
123static struct clk * __init vf610_get_fixed_clock(
124 struct device_node *ccm_node, const char *name)
125{
126 struct clk *clk = of_clk_get_by_name(ccm_node, name);
127
128 /* Backward compatibility if device tree is missing clks assignments */
129 if (IS_ERR(clk))
130 clk = imx_obtain_fixed_clock(name, 0);
131 return clk;
132};
133
108static void __init vf610_clocks_init(struct device_node *ccm_node) 134static void __init vf610_clocks_init(struct device_node *ccm_node)
109{ 135{
110 struct device_node *np; 136 struct device_node *np;
@@ -115,10 +141,13 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
115 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); 141 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
116 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); 142 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
117 143
118 clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0); 144 clk[VF610_CLK_SXOSC] = vf610_get_fixed_clock(ccm_node, "sxosc");
119 clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0); 145 clk[VF610_CLK_FXOSC] = vf610_get_fixed_clock(ccm_node, "fxosc");
120 clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0); 146 clk[VF610_CLK_AUDIO_EXT] = vf610_get_fixed_clock(ccm_node, "audio_ext");
121 clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0); 147 clk[VF610_CLK_ENET_EXT] = vf610_get_fixed_clock(ccm_node, "enet_ext");
148
149 /* Clock source from external clock via LVDs PAD */
150 clk[VF610_CLK_ANACLK1] = vf610_get_fixed_clock(ccm_node, "anaclk1");
122 151
123 clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); 152 clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
124 153
@@ -133,31 +162,63 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
133 clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); 162 clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
134 clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); 163 clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
135 164
136 clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1); 165 clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
137 clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0); 166 clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
138 clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1); 167 clk[VF610_CLK_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", PLL3_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
139 clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2); 168 clk[VF610_CLK_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", PLL4_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
140 clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3); 169 clk[VF610_CLK_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", PLL5_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
141 170 clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
142 clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1); 171 clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
143 clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0); 172
144 clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1); 173 clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);
145 clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2); 174 clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);
146 clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3); 175 clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1);
147 176 clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);
148 clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1); 177 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);
149 clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0); 178 clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f);
150 clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1); 179 clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1);
151 clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2); 180
152 clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3); 181 clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
153 182 clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
154 clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1); 183 clk[VF610_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
155 /* Enet pll: fixed 50Mhz */ 184 clk[VF610_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
156 clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); 185 clk[VF610_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
157 /* pll6: default 960Mhz */ 186 clk[VF610_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
158 clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); 187 clk[VF610_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
159 /* pll7: USB1 PLL at 480MHz */ 188
160 clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2); 189 /* Do not bypass PLLs initially */
190 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]);
191 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]);
192 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]);
193 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]);
194 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]);
195 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]);
196 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]);
197
198 clk[VF610_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", PLL1_CTRL, 13);
199 clk[VF610_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", PLL2_CTRL, 13);
200 clk[VF610_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", PLL3_CTRL, 13);
201 clk[VF610_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", PLL4_CTRL, 13);
202 clk[VF610_CLK_PLL5_ENET] = imx_clk_gate("pll5_enet", "pll5_bypass", PLL5_CTRL, 13);
203 clk[VF610_CLK_PLL6_VIDEO] = imx_clk_gate("pll6_video", "pll6_bypass", PLL6_CTRL, 13);
204 clk[VF610_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", PLL7_CTRL, 13);
205
206 clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10));
207
208 clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_sys", PFD_PLL1_BASE, 0);
209 clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_sys", PFD_PLL1_BASE, 1);
210 clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_sys", PFD_PLL1_BASE, 2);
211 clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_sys", PFD_PLL1_BASE, 3);
212
213 clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", PFD_PLL2_BASE, 0);
214 clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", PFD_PLL2_BASE, 1);
215 clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_bus", PFD_PLL2_BASE, 2);
216 clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_bus", PFD_PLL2_BASE, 3);
217
218 clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", PFD_PLL3_BASE, 0);
219 clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", PFD_PLL3_BASE, 1);
220 clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", PFD_PLL3_BASE, 2);
221 clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_usb_otg", PFD_PLL3_BASE, 3);
161 222
162 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); 223 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
163 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); 224 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
@@ -167,12 +228,12 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
167 clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); 228 clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
168 clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); 229 clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
169 230
170 clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1); 231 clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_usb_otg_div", "pll3_usb_otg", CCM_CACRR, 20, 1);
171 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); 232 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock);
172 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); 233 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1);
173 234
174 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6); 235 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6);
175 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6); 236 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6);
176 237
177 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4)); 238 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
178 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4)); 239 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
@@ -191,8 +252,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
191 clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); 252 clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
192 clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); 253 clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
193 254
194 clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10); 255 clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_enet", 1, 10);
195 clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20); 256 clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_enet", 1, 20);
196 clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); 257 clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
197 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); 258 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
198 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); 259 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 4cdf8b6a74e8..5ef82e2f8fc5 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -131,4 +131,8 @@ static inline struct clk *imx_clk_fixed_factor(const char *name,
131 CLK_SET_RATE_PARENT, mult, div); 131 CLK_SET_RATE_PARENT, mult, div);
132} 132}
133 133
134struct clk *imx_clk_cpu(const char *name, const char *parent_name,
135 struct clk *div, struct clk *mux, struct clk *pll,
136 struct clk *step);
137
134#endif 138#endif
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 1dabf435c592..fe9a908da3ed 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -116,6 +116,7 @@ void imx_anatop_post_resume(void);
116int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); 116int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
117void imx6q_set_int_mem_clk_lpm(bool enable); 117void imx6q_set_int_mem_clk_lpm(bool enable);
118void imx6sl_set_wait_clk(bool enter); 118void imx6sl_set_wait_clk(bool enter);
119int imx_mmdc_get_ddr_type(void);
119 120
120void imx_cpu_die(unsigned int cpu); 121void imx_cpu_die(unsigned int cpu);
121int imx_cpu_kill(unsigned int cpu); 122int imx_cpu_kill(unsigned int cpu);
@@ -157,5 +158,6 @@ static inline void imx_init_l2cache(void) {}
157#endif 158#endif
158 159
159extern struct smp_operations imx_smp_ops; 160extern struct smp_operations imx_smp_ops;
161extern struct smp_operations ls1021a_smp_ops;
160 162
161#endif 163#endif
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 03dd6ea13acc..7587cf0cba3e 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -41,6 +41,8 @@ static void __init imx53_dt_init(void)
41static void __init imx53_init_late(void) 41static void __init imx53_init_late(void)
42{ 42{
43 imx53_pm_init(); 43 imx53_pm_init();
44
45 platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
44} 46}
45 47
46static const char * const imx53_dt_board_compat[] __initconst = { 48static const char * const imx53_dt_board_compat[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 3de3b7369aef..982224922fb1 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -8,12 +8,62 @@
8 8
9#include <linux/irqchip.h> 9#include <linux/irqchip.h>
10#include <linux/of_platform.h> 10#include <linux/of_platform.h>
11#include <linux/phy.h>
12#include <linux/regmap.h>
13#include <linux/mfd/syscon.h>
14#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
11#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
12#include <asm/mach/map.h> 16#include <asm/mach/map.h>
13 17
14#include "common.h" 18#include "common.h"
15#include "cpuidle.h" 19#include "cpuidle.h"
16 20
21static int ar8031_phy_fixup(struct phy_device *dev)
22{
23 u16 val;
24
25 /* Set RGMII IO voltage to 1.8V */
26 phy_write(dev, 0x1d, 0x1f);
27 phy_write(dev, 0x1e, 0x8);
28
29 /* introduce tx clock delay */
30 phy_write(dev, 0x1d, 0x5);
31 val = phy_read(dev, 0x1e);
32 val |= 0x0100;
33 phy_write(dev, 0x1e, val);
34
35 return 0;
36}
37
38#define PHY_ID_AR8031 0x004dd074
39static void __init imx6sx_enet_phy_init(void)
40{
41 if (IS_BUILTIN(CONFIG_PHYLIB))
42 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
43 ar8031_phy_fixup);
44}
45
46static void __init imx6sx_enet_clk_sel(void)
47{
48 struct regmap *gpr;
49
50 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
51 if (!IS_ERR(gpr)) {
52 regmap_update_bits(gpr, IOMUXC_GPR1,
53 IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
54 regmap_update_bits(gpr, IOMUXC_GPR1,
55 IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
56 } else {
57 pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
58 }
59}
60
61static inline void imx6sx_enet_init(void)
62{
63 imx6sx_enet_phy_init();
64 imx6sx_enet_clk_sel();
65}
66
17static void __init imx6sx_init_machine(void) 67static void __init imx6sx_init_machine(void)
18{ 68{
19 struct device *parent; 69 struct device *parent;
@@ -26,6 +76,7 @@ static void __init imx6sx_init_machine(void)
26 76
27 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); 77 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
28 78
79 imx6sx_enet_init();
29 imx_anatop_init(); 80 imx_anatop_init();
30 imx6sx_pm_init(); 81 imx6sx_pm_init();
31} 82}
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
new file mode 100644
index 000000000000..b89c858ebfd6
--- /dev/null
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <asm/mach/arch.h>
11
12#include "common.h"
13
14static const char * const ls1021a_dt_compat[] __initconst = {
15 "fsl,ls1021a",
16 NULL,
17};
18
19DT_MACHINE_START(LS1021A, "Freescale LS1021A")
20 .smp = smp_ops(ls1021a_smp_ops),
21 .dt_compat = ls1021a_dt_compat,
22MACHINE_END
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index 7a9686ad994c..3729d90cfa46 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -21,6 +21,12 @@
21#define BP_MMDC_MAPSR_PSD 0 21#define BP_MMDC_MAPSR_PSD 0
22#define BP_MMDC_MAPSR_PSS 4 22#define BP_MMDC_MAPSR_PSS 4
23 23
24#define MMDC_MDMISC 0x18
25#define BM_MMDC_MDMISC_DDR_TYPE 0x18
26#define BP_MMDC_MDMISC_DDR_TYPE 0x3
27
28static int ddr_type;
29
24static int imx_mmdc_probe(struct platform_device *pdev) 30static int imx_mmdc_probe(struct platform_device *pdev)
25{ 31{
26 struct device_node *np = pdev->dev.of_node; 32 struct device_node *np = pdev->dev.of_node;
@@ -31,6 +37,12 @@ static int imx_mmdc_probe(struct platform_device *pdev)
31 mmdc_base = of_iomap(np, 0); 37 mmdc_base = of_iomap(np, 0);
32 WARN_ON(!mmdc_base); 38 WARN_ON(!mmdc_base);
33 39
40 reg = mmdc_base + MMDC_MDMISC;
41 /* Get ddr type */
42 val = readl_relaxed(reg);
43 ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >>
44 BP_MMDC_MDMISC_DDR_TYPE;
45
34 reg = mmdc_base + MMDC_MAPSR; 46 reg = mmdc_base + MMDC_MAPSR;
35 47
36 /* Enable automatic power saving */ 48 /* Enable automatic power saving */
@@ -51,6 +63,11 @@ static int imx_mmdc_probe(struct platform_device *pdev)
51 return 0; 63 return 0;
52} 64}
53 65
66int imx_mmdc_get_ddr_type(void)
67{
68 return ddr_type;
69}
70
54static struct of_device_id imx_mmdc_dt_ids[] = { 71static struct of_device_id imx_mmdc_dt_ids[] = {
55 { .compatible = "fsl,imx6q-mmdc", }, 72 { .compatible = "fsl,imx6q-mmdc", },
56 { /* sentinel */ } 73 { /* sentinel */ }
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 17a41ca65acf..4c1343df2ba4 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -55,6 +55,8 @@
55#define IMX_CHIP_REVISION_3_3 0x33 55#define IMX_CHIP_REVISION_3_3 0x33
56#define IMX_CHIP_REVISION_UNKNOWN 0xff 56#define IMX_CHIP_REVISION_UNKNOWN 0xff
57 57
58#define IMX_DDR_TYPE_LPDDR2 1
59
58#ifndef __ASSEMBLY__ 60#ifndef __ASSEMBLY__
59extern unsigned int __mxc_cpu_type; 61extern unsigned int __mxc_cpu_type;
60#endif 62#endif
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 771bd25c1025..7f270015fe58 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -11,7 +11,10 @@
11 */ 11 */
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/of_address.h>
15#include <linux/of.h>
14#include <linux/smp.h> 16#include <linux/smp.h>
17
15#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
16#include <asm/page.h> 19#include <asm/page.h>
17#include <asm/smp_scu.h> 20#include <asm/smp_scu.h>
@@ -94,3 +97,33 @@ struct smp_operations imx_smp_ops __initdata = {
94 .cpu_kill = imx_cpu_kill, 97 .cpu_kill = imx_cpu_kill,
95#endif 98#endif
96}; 99};
100
101#define DCFG_CCSR_SCRATCHRW1 0x200
102
103static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
104{
105 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
106
107 return 0;
108}
109
110static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
111{
112 struct device_node *np;
113 void __iomem *dcfg_base;
114 unsigned long paddr;
115
116 np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
117 dcfg_base = of_iomap(np, 0);
118 BUG_ON(!dcfg_base);
119
120 paddr = virt_to_phys(secondary_startup);
121 writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
122
123 iounmap(dcfg_base);
124}
125
126struct smp_operations ls1021a_smp_ops __initdata = {
127 .smp_prepare_cpus = ls1021a_smp_prepare_cpus,
128 .smp_boot_secondary = ls1021a_boot_secondary,
129};
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 5c3af8f993d0..c653dd4c9103 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -88,7 +88,7 @@ struct imx6_pm_base {
88}; 88};
89 89
90struct imx6_pm_socdata { 90struct imx6_pm_socdata {
91 u32 cpu_type; 91 u32 ddr_type;
92 const char *mmdc_compat; 92 const char *mmdc_compat;
93 const char *src_compat; 93 const char *src_compat;
94 const char *iomuxc_compat; 94 const char *iomuxc_compat;
@@ -138,7 +138,6 @@ static const u32 imx6sx_mmdc_io_offset[] __initconst = {
138}; 138};
139 139
140static const struct imx6_pm_socdata imx6q_pm_data __initconst = { 140static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
141 .cpu_type = MXC_CPU_IMX6Q,
142 .mmdc_compat = "fsl,imx6q-mmdc", 141 .mmdc_compat = "fsl,imx6q-mmdc",
143 .src_compat = "fsl,imx6q-src", 142 .src_compat = "fsl,imx6q-src",
144 .iomuxc_compat = "fsl,imx6q-iomuxc", 143 .iomuxc_compat = "fsl,imx6q-iomuxc",
@@ -148,7 +147,6 @@ static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
148}; 147};
149 148
150static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { 149static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
151 .cpu_type = MXC_CPU_IMX6DL,
152 .mmdc_compat = "fsl,imx6q-mmdc", 150 .mmdc_compat = "fsl,imx6q-mmdc",
153 .src_compat = "fsl,imx6q-src", 151 .src_compat = "fsl,imx6q-src",
154 .iomuxc_compat = "fsl,imx6dl-iomuxc", 152 .iomuxc_compat = "fsl,imx6dl-iomuxc",
@@ -158,7 +156,6 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
158}; 156};
159 157
160static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { 158static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
161 .cpu_type = MXC_CPU_IMX6SL,
162 .mmdc_compat = "fsl,imx6sl-mmdc", 159 .mmdc_compat = "fsl,imx6sl-mmdc",
163 .src_compat = "fsl,imx6sl-src", 160 .src_compat = "fsl,imx6sl-src",
164 .iomuxc_compat = "fsl,imx6sl-iomuxc", 161 .iomuxc_compat = "fsl,imx6sl-iomuxc",
@@ -168,7 +165,6 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
168}; 165};
169 166
170static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { 167static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
171 .cpu_type = MXC_CPU_IMX6SX,
172 .mmdc_compat = "fsl,imx6sx-mmdc", 168 .mmdc_compat = "fsl,imx6sx-mmdc",
173 .src_compat = "fsl,imx6sx-src", 169 .src_compat = "fsl,imx6sx-src",
174 .iomuxc_compat = "fsl,imx6sx-iomuxc", 170 .iomuxc_compat = "fsl,imx6sx-iomuxc",
@@ -187,7 +183,7 @@ static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
187struct imx6_cpu_pm_info { 183struct imx6_cpu_pm_info {
188 phys_addr_t pbase; /* The physical address of pm_info. */ 184 phys_addr_t pbase; /* The physical address of pm_info. */
189 phys_addr_t resume_addr; /* The physical resume address for asm code */ 185 phys_addr_t resume_addr; /* The physical resume address for asm code */
190 u32 cpu_type; 186 u32 ddr_type;
191 u32 pm_info_size; /* Size of pm_info. */ 187 u32 pm_info_size; /* Size of pm_info. */
192 struct imx6_pm_base mmdc_base; 188 struct imx6_pm_base mmdc_base;
193 struct imx6_pm_base src_base; 189 struct imx6_pm_base src_base;
@@ -522,7 +518,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
522 goto pl310_cache_map_failed; 518 goto pl310_cache_map_failed;
523 } 519 }
524 520
525 pm_info->cpu_type = socdata->cpu_type; 521 pm_info->ddr_type = imx_mmdc_get_ddr_type();
526 pm_info->mmdc_io_num = socdata->mmdc_io_num; 522 pm_info->mmdc_io_num = socdata->mmdc_io_num;
527 mmdc_offset_array = socdata->mmdc_io_offset; 523 mmdc_offset_array = socdata->mmdc_io_offset;
528 524
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index ca4ea2daf25b..b99987b023fa 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -45,7 +45,7 @@
45 */ 45 */
46#define PM_INFO_PBASE_OFFSET 0x0 46#define PM_INFO_PBASE_OFFSET 0x0
47#define PM_INFO_RESUME_ADDR_OFFSET 0x4 47#define PM_INFO_RESUME_ADDR_OFFSET 0x4
48#define PM_INFO_CPU_TYPE_OFFSET 0x8 48#define PM_INFO_DDR_TYPE_OFFSET 0x8
49#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC 49#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC
50#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 50#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10
51#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 51#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14
@@ -110,7 +110,7 @@
110 ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] 110 ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
111 ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] 111 ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
112 112
113 cmp r3, #MXC_CPU_IMX6SL 113 cmp r3, #IMX_DDR_TYPE_LPDDR2
114 bne 4f 114 bne 4f
115 115
116 /* reset read FIFO, RST_RD_FIFO */ 116 /* reset read FIFO, RST_RD_FIFO */
@@ -151,7 +151,7 @@
151ENTRY(imx6_suspend) 151ENTRY(imx6_suspend)
152 ldr r1, [r0, #PM_INFO_PBASE_OFFSET] 152 ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
153 ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] 153 ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
154 ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET] 154 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
155 ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] 155 ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
156 156
157 /* 157 /*
@@ -209,8 +209,8 @@ poll_dvfs_set:
209 ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] 209 ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
210 ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET 210 ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
211 add r8, r8, r0 211 add r8, r8, r0
212 /* i.MX6SL's last 3 IOs need special setting */ 212 /* LPDDR2's last 3 IOs need special setting */
213 cmp r3, #MXC_CPU_IMX6SL 213 cmp r3, #IMX_DDR_TYPE_LPDDR2
214 subeq r7, r7, #0x3 214 subeq r7, r7, #0x3
215set_mmdc_io_lpm: 215set_mmdc_io_lpm:
216 ldr r9, [r8], #0x8 216 ldr r9, [r8], #0x8
@@ -218,7 +218,7 @@ set_mmdc_io_lpm:
218 subs r7, r7, #0x1 218 subs r7, r7, #0x1
219 bne set_mmdc_io_lpm 219 bne set_mmdc_io_lpm
220 220
221 cmp r3, #MXC_CPU_IMX6SL 221 cmp r3, #IMX_DDR_TYPE_LPDDR2
222 bne set_mmdc_io_lpm_done 222 bne set_mmdc_io_lpm_done
223 ldr r6, =0x1000 223 ldr r6, =0x1000
224 ldr r9, [r8], #0x8 224 ldr r9, [r8], #0x8
@@ -324,7 +324,7 @@ resume:
324 str r7, [r11, #MX6Q_SRC_GPR1] 324 str r7, [r11, #MX6Q_SRC_GPR1]
325 str r7, [r11, #MX6Q_SRC_GPR2] 325 str r7, [r11, #MX6Q_SRC_GPR2]
326 326
327 ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET] 327 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
328 mov r5, #0x1 328 mov r5, #0x1
329 resume_mmdc 329 resume_mmdc
330 330
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index f65ff49bb275..028e76504519 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -71,6 +71,15 @@ config POWER_RESET_HISI
71 help 71 help
72 Reboot support for Hisilicon boards. 72 Reboot support for Hisilicon boards.
73 73
74config POWER_RESET_IMX
75 bool "IMX6 power-off driver"
76 depends on POWER_RESET && SOC_IMX6
77 help
78 This driver support power off external PMIC by PMIC_ON_REQ on i.mx6
79 boards.If you want to use other pin to control external power,please
80 say N here or disable in dts to make sure pm_power_off never be
81 overwrote wrongly by this driver.
82
74config POWER_RESET_MSM 83config POWER_RESET_MSM
75 bool "Qualcomm MSM power-off driver" 84 bool "Qualcomm MSM power-off driver"
76 depends on ARCH_QCOM 85 depends on ARCH_QCOM
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 76ce1c59469b..1d4804d6b323 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_POWER_RESET_BRCMSTB) += brcmstb-reboot.o
6obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o 6obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
7obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o 7obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o
8obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o 8obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
9obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o
9obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o 10obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
10obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o 11obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
11obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o 12obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
diff --git a/drivers/power/reset/imx-snvs-poweroff.c b/drivers/power/reset/imx-snvs-poweroff.c
new file mode 100644
index 000000000000..ad6ce5020ea7
--- /dev/null
+++ b/drivers/power/reset/imx-snvs-poweroff.c
@@ -0,0 +1,66 @@
1/* Power off driver for i.mx6
2 * Copyright (c) 2014, FREESCALE CORPORATION. All rights reserved.
3 *
4 * based on msm-poweroff.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/err.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/platform_device.h>
25
26static void __iomem *snvs_base;
27
28static void do_imx_poweroff(void)
29{
30 u32 value = readl(snvs_base);
31
32 /* set TOP and DP_EN bit */
33 writel(value | 0x60, snvs_base);
34}
35
36static int imx_poweroff_probe(struct platform_device *pdev)
37{
38 snvs_base = of_iomap(pdev->dev.of_node, 0);
39 if (!snvs_base) {
40 dev_err(&pdev->dev, "failed to get memory\n");
41 return -ENODEV;
42 }
43
44 pm_power_off = do_imx_poweroff;
45 return 0;
46}
47
48static const struct of_device_id of_imx_poweroff_match[] = {
49 { .compatible = "fsl,sec-v4.0-poweroff", },
50 {},
51};
52MODULE_DEVICE_TABLE(of, of_imx_poweroff_match);
53
54static struct platform_driver imx_poweroff_driver = {
55 .probe = imx_poweroff_probe,
56 .driver = {
57 .name = "imx-snvs-poweroff",
58 .of_match_table = of_match_ptr(of_imx_poweroff_match),
59 },
60};
61
62static int __init imx_poweroff_init(void)
63{
64 return platform_driver_register(&imx_poweroff_driver);
65}
66device_initcall(imx_poweroff_init);
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
index 5f2667ecd98e..f4b7478e23c8 100644
--- a/include/dt-bindings/clock/imx5-clock.h
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -198,6 +198,9 @@
198#define IMX5_CLK_OCRAM 186 198#define IMX5_CLK_OCRAM 186
199#define IMX5_CLK_SAHARA_IPG_GATE 187 199#define IMX5_CLK_SAHARA_IPG_GATE 187
200#define IMX5_CLK_SATA_REF 188 200#define IMX5_CLK_SATA_REF 188
201#define IMX5_CLK_END 189 201#define IMX5_CLK_STEP_SEL 189
202#define IMX5_CLK_CPU_PODF_SEL 190
203#define IMX5_CLK_ARM 191
204#define IMX5_CLK_END 192
202 205
203#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ 206#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index d6b56b21539b..801c0ac50c47 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -21,24 +21,24 @@
21#define VF610_CLK_FASK_CLK_SEL 8 21#define VF610_CLK_FASK_CLK_SEL 8
22#define VF610_CLK_AUDIO_EXT 9 22#define VF610_CLK_AUDIO_EXT 9
23#define VF610_CLK_ENET_EXT 10 23#define VF610_CLK_ENET_EXT 10
24#define VF610_CLK_PLL1_MAIN 11 24#define VF610_CLK_PLL1_SYS 11
25#define VF610_CLK_PLL1_PFD1 12 25#define VF610_CLK_PLL1_PFD1 12
26#define VF610_CLK_PLL1_PFD2 13 26#define VF610_CLK_PLL1_PFD2 13
27#define VF610_CLK_PLL1_PFD3 14 27#define VF610_CLK_PLL1_PFD3 14
28#define VF610_CLK_PLL1_PFD4 15 28#define VF610_CLK_PLL1_PFD4 15
29#define VF610_CLK_PLL2_MAIN 16 29#define VF610_CLK_PLL2_BUS 16
30#define VF610_CLK_PLL2_PFD1 17 30#define VF610_CLK_PLL2_PFD1 17
31#define VF610_CLK_PLL2_PFD2 18 31#define VF610_CLK_PLL2_PFD2 18
32#define VF610_CLK_PLL2_PFD3 19 32#define VF610_CLK_PLL2_PFD3 19
33#define VF610_CLK_PLL2_PFD4 20 33#define VF610_CLK_PLL2_PFD4 20
34#define VF610_CLK_PLL3_MAIN 21 34#define VF610_CLK_PLL3_USB_OTG 21
35#define VF610_CLK_PLL3_PFD1 22 35#define VF610_CLK_PLL3_PFD1 22
36#define VF610_CLK_PLL3_PFD2 23 36#define VF610_CLK_PLL3_PFD2 23
37#define VF610_CLK_PLL3_PFD3 24 37#define VF610_CLK_PLL3_PFD3 24
38#define VF610_CLK_PLL3_PFD4 25 38#define VF610_CLK_PLL3_PFD4 25
39#define VF610_CLK_PLL4_MAIN 26 39#define VF610_CLK_PLL4_AUDIO 26
40#define VF610_CLK_PLL5_MAIN 27 40#define VF610_CLK_PLL5_ENET 27
41#define VF610_CLK_PLL6_MAIN 28 41#define VF610_CLK_PLL6_VIDEO 28
42#define VF610_CLK_PLL3_MAIN_DIV 29 42#define VF610_CLK_PLL3_MAIN_DIV 29
43#define VF610_CLK_PLL4_MAIN_DIV 30 43#define VF610_CLK_PLL4_MAIN_DIV 30
44#define VF610_CLK_PLL6_MAIN_DIV 31 44#define VF610_CLK_PLL6_MAIN_DIV 31
@@ -166,9 +166,32 @@
166#define VF610_CLK_DMAMUX3 153 166#define VF610_CLK_DMAMUX3 153
167#define VF610_CLK_FLEXCAN0_EN 154 167#define VF610_CLK_FLEXCAN0_EN 154
168#define VF610_CLK_FLEXCAN1_EN 155 168#define VF610_CLK_FLEXCAN1_EN 155
169#define VF610_CLK_PLL7_MAIN 156 169#define VF610_CLK_PLL7_USB_HOST 156
170#define VF610_CLK_USBPHY0 157 170#define VF610_CLK_USBPHY0 157
171#define VF610_CLK_USBPHY1 158 171#define VF610_CLK_USBPHY1 158
172#define VF610_CLK_END 159 172#define VF610_CLK_LVDS1_IN 159
173#define VF610_CLK_ANACLK1 160
174#define VF610_CLK_PLL1_BYPASS_SRC 161
175#define VF610_CLK_PLL2_BYPASS_SRC 162
176#define VF610_CLK_PLL3_BYPASS_SRC 163
177#define VF610_CLK_PLL4_BYPASS_SRC 164
178#define VF610_CLK_PLL5_BYPASS_SRC 165
179#define VF610_CLK_PLL6_BYPASS_SRC 166
180#define VF610_CLK_PLL7_BYPASS_SRC 167
181#define VF610_CLK_PLL1 168
182#define VF610_CLK_PLL2 169
183#define VF610_CLK_PLL3 170
184#define VF610_CLK_PLL4 171
185#define VF610_CLK_PLL5 172
186#define VF610_CLK_PLL6 173
187#define VF610_CLK_PLL7 174
188#define VF610_PLL1_BYPASS 175
189#define VF610_PLL2_BYPASS 176
190#define VF610_PLL3_BYPASS 177
191#define VF610_PLL4_BYPASS 178
192#define VF610_PLL5_BYPASS 179
193#define VF610_PLL6_BYPASS 180
194#define VF610_PLL7_BYPASS 181
195#define VF610_CLK_END 182
173 196
174#endif /* __DT_BINDINGS_CLOCK_VF610_H */ 197#endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374a1a4e..c877cad61a13 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -395,4 +395,43 @@
395#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) 395#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
396#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) 396#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
397 397
398/* For imx6sx iomux gpr register field define */
399#define IMX6SX_GPR1_VDEC_SW_RST_MASK (0x1 << 20)
400#define IMX6SX_GPR1_VDEC_SW_RST_RESET (0x1 << 20)
401#define IMX6SX_GPR1_VDEC_SW_RST_RELEASE (0x0 << 20)
402#define IMX6SX_GPR1_VADC_SW_RST_MASK (0x1 << 19)
403#define IMX6SX_GPR1_VADC_SW_RST_RESET (0x1 << 19)
404#define IMX6SX_GPR1_VADC_SW_RST_RELEASE (0x0 << 19)
405#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK (0x3 << 13)
406#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17)
407#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13)
408
409#define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3)
410#define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4)
411
412#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3)
413#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3)
414#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3)
415
416#define IMX6SX_GPR5_CSI2_MUX_CTRL_MASK (0x3 << 27)
417#define IMX6SX_GPR5_CSI2_MUX_CTRL_EXT_PIN (0x0 << 27)
418#define IMX6SX_GPR5_CSI2_MUX_CTRL_CVD (0x1 << 27)
419#define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI (0x2 << 27)
420#define IMX6SX_GPR5_CSI2_MUX_CTRL_GND (0x3 << 27)
421#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26)
422#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26)
423#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26)
424#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4)
425#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4)
426#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4)
427#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4)
428#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4)
429
430#define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2 (0x0 << 2)
431#define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS (0x1 << 2)
432#define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK (0x1 << 2)
433#define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1 (0x0 << 1)
434#define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1)
435#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1)
436
398#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ 437#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 16:58:36 -0400