Merge tag 'sunxi-dt-for-3.14-2' of https://github.com/mripard/linux into next/dt

From Maxime Ripard:
Second round of DT additions for 3.14

Mostly:
  - Addition of the missing PLLs and module clocks
  - Addition of the external clocks
  - Addition of the touchscreen controler
  - I2C nodes of the Cubietruck

* tag 'sunxi-dt-for-3.14-2' of https://github.com/mripard/linux:
  arm: sun7i: cubietruck: Enable the i2c controllers
  ARM: dts: sun7i: external clock outputs
  ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style
  ARM: dts: sun7i: Add pin muxing options for clock outputs
  ARM: dts: sun7i: Add rtp controller node
  ARM: dts: sun5i: Add rtp controller node
  ARM: dts: sun4i: Add rtp controller node
  ARM: sun4i: dt: Remove chosen nodes
  ARM: sun4i: dt: Move the aliases to the DTSI
  ARM: sunxi: dt: add nodes for the mbus clock
  ARM: sun7i: dt: mod0 clocks
  ARM: sun5i: dt: mod0 clocks
  ARM: sun4i: dt: mod0 clocks
  ARM: sunxi: add PLL5 and PLL6 support
  ARM: sunxi: add PLL4 support

Signed-off-by: Kevin Hilman <khilman@linaro.org>

10 files changed, 622 insertions, 43 deletions

diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index eb4d73b6a090..d4b081d6a167 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -18,10 +18,6 @@
         model = "Mele A1000";
         compatible = "mele,a1000", "allwinner,sun4i-a10";
 
-        aliases {
-                serial0 = &uart0;
-        };
-
         soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 425a7db898c5..b139ee6bcf99 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -17,15 +17,6 @@
         model = "Cubietech Cubieboard";
         compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
 
-        aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-        };
-
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index b3ae51fa9372..3a1595f67823 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -18,10 +18,6 @@
         model = "Miniand Hackberry";
         compatible = "miniand,hackberry", "allwinner,sun4i-a10";
 
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 0c1447c68059..70b3323caf1a 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -18,10 +18,6 @@
         model = "PineRiver Mini X-Plus";
         compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
 
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 uart0: serial@01c28000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 0bf70ee041ed..040bb0eba152 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -17,6 +17,8 @@
 
         aliases {
                 ethernet0 = &emac;
+                serial0 = &uart0;
+                serial1 = &uart1;
         };
 
         cpus {
@@ -70,6 +72,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -135,12 +160,11 @@
                                 "apb0_ir1", "apb0_keypad";
                 };
 
-                /* dummy is pll62 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -162,6 +186,126 @@
                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
                                 "apb1_uart7";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                mmc3_clk: clk@01c20094 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20094 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc3";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                pata_clk: clk@01c200ac {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200ac 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "pata";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                ir1_clk: clk@01c200b4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir1";
+                };
+
+                spi3_clk: clk@01c200d4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200d4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi3";
+                };
         };
 
         soc@01c00000 {
@@ -281,6 +425,12 @@
                         reg = <0x01c23800 0x10>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <29>;
+                };
+
                 uart0: serial@01c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index b4764be10a60..9bb3a0d493de 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -67,6 +67,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -127,12 +150,11 @@
                                 "apb0_ir", "apb0_keypad";
                 };
 
-                /* dummy is pll62 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -151,6 +173,102 @@
                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
                                 "apb1_uart2", "apb1_uart3";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
         };
 
         soc@01c00000 {
@@ -264,6 +382,12 @@
                         reg = <0x01c23800 0x10>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <29>;
+                };
+
                 uart0: serial@01c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 9e508dcc4245..a4ba5ff010cf 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -18,10 +18,6 @@
         model = "Olimex A13-Olinuxino";
         compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
 
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 pinctrl@01c20800 {
                         led_pins_olinuxino: led_pins@0 {
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index ce8ef2a45be0..4dee9716deb4 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -67,6 +67,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -125,12 +148,11 @@
                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                 };
 
-                /* dummy is pll6 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -148,6 +170,102 @@
                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
         };
 
         soc@01c00000 {
@@ -227,6 +345,12 @@
                         reg = <0x01c23800 0x10>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <29>;
+                };
+
                 uart1: serial@01c28400 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28400 0x400>;
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 8a1009d6c829..f9dcb61a5305 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -33,6 +33,24 @@
                         pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 74bf906ef786..0d5499808b3a 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -53,10 +53,11 @@
                         clock-frequency = <24000000>;
                 };
 
-                osc32k: osc32k {
+                osc32k: clk@0 {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
                         clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
                 };
 
                 pll1: pll1@01c20000 {
@@ -66,23 +67,34 @@
                         clocks = <&osc24M>;
                 };
 
-                /*
-                 * This is a dummy clock, to be used as placeholder on
-                 * other mux clocks when a specific parent clock is not
-                 * yet implemented. It should be dropped when the driver
-                 * is complete.
-                 */
-                pll6: pll6 {
+                pll4: pll4@01c20018 {
                         #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
                 };
 
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-cpu-clk";
                         reg = <0x01c20054 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
                 };
 
                 axi: axi@01c20054 {
@@ -141,7 +153,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&pll6>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -163,6 +175,162 @@
                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                mmc3_clk: clk@01c20094 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20094 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc3";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                pata_clk: clk@01c200ac {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200ac 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "pata";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                ir1_clk: clk@01c200b4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir1";
+                };
+
+                spi3_clk: clk@01c200d4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200d4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi3";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
+
+                /*
+                 * Dummy clock used by output clocks
+                 */
+                osc24M_32k: clk@1 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <750>;
+                        clock-mult = <1>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "osc24M_32k";
+                };
+
+                clk_out_a: clk@01c201f0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun7i-a20-out-clk";
+                        reg = <0x01c201f0 0x4>;
+                        clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+                        clock-output-names = "clk_out_a";
+                };
+
+                clk_out_b: clk@01c201f4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun7i-a20-out-clk";
+                        reg = <0x01c201f4 0x4>;
+                        clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+                        clock-output-names = "clk_out_b";
+                };
         };
 
         soc@01c00000 {
@@ -250,6 +418,20 @@
                                 allwinner,drive = <0>;
                                 allwinner,pull = <0>;
                         };
+
+                        clk_out_a_pins_a: clk_out_a@0 {
+                                allwinner,pins = "PI12";
+                                allwinner,function = "clk_out_a";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        clk_out_b_pins_a: clk_out_b@0 {
+                                allwinner,pins = "PI13";
+                                allwinner,function = "clk_out_b";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 timer@01c20c00 {
@@ -280,6 +462,12 @@
                         reg = <0x01c23800 0x200>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <0 29 4>;
+                };
+
                 uart0: serial@01c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;