staging: comedi: s626: remove 'allocatedBuf' from private data

This variable is only used to count the number of dma buffers allocated during the attach. If an allocation fails, the attach function exits with -ENOMEM. When this variable is checked later it will always be == 2. Just remove the variable and the check. This allows bringing the code back an indent level in s626_initialize(). Note, coding style issues in this function are not addressed yet. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
author: H Hartley Sweeten <hartleys@visionengravers.com> 2012-09-24 16:37:36 -0400
committer: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2012-09-26 12:37:31 -0400
commit: 68ad0ae0eac07911e6749e28da75d77d25524864 (patch)
tree: b4f15cefa8216fb1ee33d63e99f0e53fba612021
parent: f996ab29e9dd1ed607ea9ba708dff6fa4d253859 (diff)
1 files changed, 194 insertions, 205 deletions
diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c
index 07ff93b996c0..cd09c37570bc 100644
--- a/drivers/staging/comedi/drivers/s626.c
+++ b/drivers/staging/comedi/drivers/s626.c
@@ -80,7 +80,6 @@ INSN_CONFIG instructions:
 struct s626_private {
        void __iomem *base_addr;
-        short allocatedBuf;
        uint8_t ai_cmd_running; /*  ai_cmd is running */
        uint8_t ai_continous;   /*  continous acquisition */
        int ai_sample_count;    /*  number of samples to acquire */
@@ -2443,24 +2442,18 @@ static int s626_allocate_dma_buffers(struct comedi_device *dev)
        void *addr;
        dma_addr_t appdma;
-        devpriv->allocatedBuf = 0;
        addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
        if (!addr)
                return -ENOMEM;
        devpriv->ANABuf.LogicalBase = addr;
        devpriv->ANABuf.PhysicalBase = appdma;
-        devpriv->allocatedBuf++;
        addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
        if (!addr)
                return -ENOMEM;
        devpriv->RPSBuf.LogicalBase = addr;
        devpriv->RPSBuf.PhysicalBase = appdma;
-        devpriv->allocatedBuf++;
        return 0;
 }
@@ -2471,117 +2464,116 @@ static void s626_initialize(struct comedi_device *dev)
 /*   uint16_t   StartVal; */
 /*   uint16_t   index; */
 /*   unsigned int data[16]; */
+        dma_addr_t pPhysBuf;
+        uint16_t chan;
        int i;
-        if (devpriv->allocatedBuf == 2) {
-                dma_addr_t pPhysBuf;
-                uint16_t chan;
-                /*  enab DEBI and audio pins, enable I2C interface. */
-                MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
-                /*  Configure DEBI operating mode. */
-                WR7146(P_DEBICFG, DEBI_CFG_SLAVE16      /*  Local bus is 16 */
-                       /*  bits wide. */
-                       | (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
-                       /*  Declare DEBI */
-                       /*  transfer timeout */
-                       /*  interval. */
-                       |DEBI_SWAP       /*  Set up byte lane */
-                       /*  steering. */
-                       | DEBI_CFG_INTEL);       /*  Intel-compatible */
-                /*  local bus (DEBI */
-                /*  never times out). */
-                /* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
-                /* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
-                /*  Paging is disabled. */
-                WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE);  /*  Disable MMU paging. */
-                /*  Init GPIO so that ADC Start* is negated. */
-                WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
-                /* IsBoardRevA is a boolean that indicates whether the board is RevA.
-                 *
-                 * VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
-                 * EEPROM ADDRESS SELECTION.  Initialize the I2C interface, which
-                 * is used to access the onboard serial EEPROM.  The EEPROM's I2C
-                 * DeviceAddress is hardwired to a value that is dependent on the
-                 * 626 board revision.  On all board revisions, the EEPROM stores
-                 * TrimDAC calibration constants for analog I/O.  On RevB and
-                 * higher boards, the DeviceAddress is hardwired to 0 to enable
-                 * the EEPROM to also store the PCI SubVendorID and SubDeviceID;
-                 * this is the address at which the SAA7146 expects a
-                 * configuration EEPROM to reside.  On RevA boards, the EEPROM
-                 * device address, which is hardwired to 4, prevents the SAA7146
-                 * from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
-                 * default values, instead.
-                 */
-                /*     devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
+        /*  enab DEBI and audio pins, enable I2C interface. */
-                /*  DeviceType (0xA0) */
+        MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
-                /*  and DeviceAddress<<1. */
+        /*  Configure DEBI operating mode. */
+        WR7146(P_DEBICFG, DEBI_CFG_SLAVE16      /*  Local bus is 16 */
+               /*  bits wide. */
+               | (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
+               /*  Declare DEBI */
+               /*  transfer timeout */
+               /*  interval. */
+               |DEBI_SWAP       /*  Set up byte lane */
+               /*  steering. */
+               | DEBI_CFG_INTEL);       /*  Intel-compatible */
+        /*  local bus (DEBI */
+        /*  never times out). */
+        /* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
+        /* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
+        /*  Paging is disabled. */
+        WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE);  /*  Disable MMU paging. */
+        /*  Init GPIO so that ADC Start* is negated. */
+        WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
+        /* IsBoardRevA is a boolean that indicates whether the board is RevA.
+         *
+         * VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
+         * EEPROM ADDRESS SELECTION.  Initialize the I2C interface, which
+         * is used to access the onboard serial EEPROM.  The EEPROM's I2C
+         * DeviceAddress is hardwired to a value that is dependent on the
+         * 626 board revision.  On all board revisions, the EEPROM stores
+         * TrimDAC calibration constants for analog I/O.  On RevB and
+         * higher boards, the DeviceAddress is hardwired to 0 to enable
+         * the EEPROM to also store the PCI SubVendorID and SubDeviceID;
+         * this is the address at which the SAA7146 expects a
+         * configuration EEPROM to reside.  On RevA boards, the EEPROM
+         * device address, which is hardwired to 4, prevents the SAA7146
+         * from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
+         * default values, instead.
+         */
+        /*     devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
+        /*  DeviceType (0xA0) */
+        /*  and DeviceAddress<<1. */
-                devpriv->I2CAdrs = 0xA0;        /*  I2C device address for onboard */
+        devpriv->I2CAdrs = 0xA0;        /*  I2C device address for onboard */
-                /*  eeprom(revb) */
+        /*  eeprom(revb) */
-                /*  Issue an I2C ABORT command to halt any I2C operation in */
+        /*  Issue an I2C ABORT command to halt any I2C operation in */
-                /* progress and reset BUSY flag. */
+        /* progress and reset BUSY flag. */
-                WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
+        WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
-                /*  Write I2C control: abort any I2C activity. */
+        /*  Write I2C control: abort any I2C activity. */
-                MC_ENABLE(P_MC2, MC2_UPLD_IIC);
+        MC_ENABLE(P_MC2, MC2_UPLD_IIC);
-                /*  Invoke command  upload */
+        /*  Invoke command  upload */
-                while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
+        while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
+                ;
+        /*  and wait for upload to complete. */
+        /* Per SAA7146 data sheet, write to STATUS reg twice to
+         * reset all  I2C error flags. */
+        for (i = 0; i < 2; i++) {
+                WR7146(P_I2CSTAT, I2C_CLKSEL);
+                /*  Write I2C control: reset  error flags. */
+                MC_ENABLE(P_MC2, MC2_UPLD_IIC); /*  Invoke command upload */
+                while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
                        ;
-                /*  and wait for upload to complete. */
+                /* and wait for upload to complete. */
+        }
-                /* Per SAA7146 data sheet, write to STATUS reg twice to
-                 * reset all  I2C error flags. */
-                for (i = 0; i < 2; i++) {
-                        WR7146(P_I2CSTAT, I2C_CLKSEL);
-                        /*  Write I2C control: reset  error flags. */
-                        MC_ENABLE(P_MC2, MC2_UPLD_IIC); /*  Invoke command upload */
-                        while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
-                                ;
-                        /* and wait for upload to complete. */
-                }
-                /* Init audio interface functional attributes: set DAC/ADC
+        /* Init audio interface functional attributes: set DAC/ADC
-                 * serial clock rates, invert DAC serial clock so that
+         * serial clock rates, invert DAC serial clock so that
-                 * DAC data setup times are satisfied, enable DAC serial
+         * DAC data setup times are satisfied, enable DAC serial
-                 * clock out.
+         * clock out.
-                 */
+         */
-                WR7146(P_ACON2, ACON2_INIT);
+        WR7146(P_ACON2, ACON2_INIT);
-                /* Set up TSL1 slot list, which is used to control the
+        /* Set up TSL1 slot list, which is used to control the
-                 * accumulation of ADC data: RSD1 = shift data in on SD1.
+         * accumulation of ADC data: RSD1 = shift data in on SD1.
-                 * SIB_A1  = store data uint8_t at next available location in
+         * SIB_A1  = store data uint8_t at next available location in
-                 * FB BUFFER1  register. */
+         * FB BUFFER1  register. */
-                WR7146(P_TSL1, RSD1 | SIB_A1);
+        WR7146(P_TSL1, RSD1 | SIB_A1);
-                /*  Fetch ADC high data uint8_t. */
+        /*  Fetch ADC high data uint8_t. */
-                WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
+        WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
-                /*  Fetch ADC low data uint8_t; end of TSL1. */
+        /*  Fetch ADC low data uint8_t; end of TSL1. */
-                /*  enab TSL1 slot list so that it executes all the time. */
+        /*  enab TSL1 slot list so that it executes all the time. */
-                WR7146(P_ACON1, ACON1_ADCSTART);
+        WR7146(P_ACON1, ACON1_ADCSTART);
-                /*  Initialize RPS registers used for ADC. */
+        /*  Initialize RPS registers used for ADC. */
-                /* Physical start of RPS program. */
+        /* Physical start of RPS program. */
-                WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
+        WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
-                WR7146(P_RPSPAGE1, 0);
+        WR7146(P_RPSPAGE1, 0);
-                /*  RPS program performs no explicit mem writes. */
+        /*  RPS program performs no explicit mem writes. */
-                WR7146(P_RPS1_TOUT, 0); /*  Disable RPS timeouts. */
+        WR7146(P_RPS1_TOUT, 0); /*  Disable RPS timeouts. */
-                /* SAA7146 BUG WORKAROUND.  Initialize SAA7146 ADC interface
+        /* SAA7146 BUG WORKAROUND.  Initialize SAA7146 ADC interface
-                 * to a known state by invoking ADCs until FB BUFFER 1
+         * to a known state by invoking ADCs until FB BUFFER 1
-                 * register shows that it is correctly receiving ADC data.
+         * register shows that it is correctly receiving ADC data.
-                 * This is necessary because the SAA7146 ADC interface does
+         * This is necessary because the SAA7146 ADC interface does
-                 * not start up in a defined state after a PCI reset.
+         * not start up in a defined state after a PCI reset.
-                 */
+         */
 /*     PollList = EOPL;         // Create a simple polling */
 /*                              // list for analog input */
@@ -2609,124 +2601,121 @@ static void s626_initialize(struct comedi_device *dev)
 /*              break; */
 /*       } */
-                /*  end initADC */
+        /*  end initADC */
-                /*  init the DAC interface */
+        /*  init the DAC interface */
-                /* Init Audio2's output DMAC attributes: burst length = 1
+        /* Init Audio2's output DMAC attributes: burst length = 1
-                 * DWORD,  threshold = 1 DWORD.
+         * DWORD,  threshold = 1 DWORD.
-                 */
+         */
-                WR7146(P_PCI_BT_A, 0);
+        WR7146(P_PCI_BT_A, 0);
-                /* Init Audio2's output DMA physical addresses.  The protection
+        /* Init Audio2's output DMA physical addresses.  The protection
-                 * address is set to 1 DWORD past the base address so that a
+         * address is set to 1 DWORD past the base address so that a
-                 * single DWORD will be transferred each time a DMA transfer is
+         * single DWORD will be transferred each time a DMA transfer is
-                 * enabled. */
+         * enabled. */
-                pPhysBuf =
+        pPhysBuf = devpriv->ANABuf.PhysicalBase +
-                    devpriv->ANABuf.PhysicalBase +
+                   (DAC_WDMABUF_OS * sizeof(uint32_t));
-                    (DAC_WDMABUF_OS * sizeof(uint32_t));
+        WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf);      /*  Buffer base adrs. */
-                WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf);      /*  Buffer base adrs. */
+        WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /*  Protection address. */
-                WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /*  Protection address. */
+        /* Cache Audio2's output DMA buffer logical address.  This is
-                /* Cache Audio2's output DMA buffer logical address.  This is
+         * where DAC data is buffered for A2 output DMA transfers. */
-                 * where DAC data is buffered for A2 output DMA transfers. */
+        devpriv->pDacWBuf = (uint32_t *)devpriv->ANABuf.LogicalBase +
-                devpriv->pDacWBuf =
+                            DAC_WDMABUF_OS;
-                    (uint32_t *) devpriv->ANABuf.LogicalBase + DAC_WDMABUF_OS;
+        /* Audio2's output channels does not use paging.  The protection
-                /* Audio2's output channels does not use paging.  The protection
+         * violation handling bit is set so that the DMAC will
-                 * violation handling bit is set so that the DMAC will
+         * automatically halt and its PCI address pointer will be reset
-                 * automatically halt and its PCI address pointer will be reset
+         * when the protection address is reached. */
-                 * when the protection address is reached. */
+        WR7146(P_PAGEA2_OUT, 8);
-                WR7146(P_PAGEA2_OUT, 8);
+        /* Initialize time slot list 2 (TSL2), which is used to control
-                /* Initialize time slot list 2 (TSL2), which is used to control
+         * the clock generation for and serialization of data to be sent
-                 * the clock generation for and serialization of data to be sent
+         * to the DAC devices.  Slot 0 is a NOP that is used to trap TSL
-                 * to the DAC devices.  Slot 0 is a NOP that is used to trap TSL
+         * execution; this permits other slots to be safely modified
-                 * execution; this permits other slots to be safely modified
+         * without first turning off the TSL sequencer (which is
-                 * without first turning off the TSL sequencer (which is
+         * apparently impossible to do).  Also, SD3 (which is driven by a
-                 * apparently impossible to do).  Also, SD3 (which is driven by a
+         * pull-up resistor) is shifted in and stored to the MSB of
-                 * pull-up resistor) is shifted in and stored to the MSB of
+         * FB_BUFFER2 to be used as evidence that the slot sequence has
-                 * FB_BUFFER2 to be used as evidence that the slot sequence has
+         * not yet finished executing.
-                 * not yet finished executing.
+         */
-                 */
-                SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
+        SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
-                /*  Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
+        /*  Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
-                /* Initialize slot 1, which is constant.  Slot 1 causes a
+        /* Initialize slot 1, which is constant.  Slot 1 causes a
-                 * DWORD to be transferred from audio channel 2's output FIFO
+         * DWORD to be transferred from audio channel 2's output FIFO
-                 * to the FIFO's output buffer so that it can be serialized
+         * to the FIFO's output buffer so that it can be serialized
-                 * and sent to the DAC during subsequent slots.  All remaining
+         * and sent to the DAC during subsequent slots.  All remaining
-                 * slots are dynamically populated as required by the target
+         * slots are dynamically populated as required by the target
-                 * DAC device.
+         * DAC device.
-                 */
+         */
-                SETVECT(1, LF_A2);
+        SETVECT(1, LF_A2);
-                /*  Slot 1: Fetch DWORD from Audio2's output FIFO. */
+        /*  Slot 1: Fetch DWORD from Audio2's output FIFO. */
-                /*  Start DAC's audio interface (TSL2) running. */
+        /*  Start DAC's audio interface (TSL2) running. */
-                WR7146(P_ACON1, ACON1_DACSTART);
+        WR7146(P_ACON1, ACON1_DACSTART);
-                /* end init DAC interface */
+        /* end init DAC interface */
-                /* Init Trim DACs to calibrated values.  Do it twice because the
+        /* Init Trim DACs to calibrated values.  Do it twice because the
-                 * SAA7146 audio channel does not always reset properly and
+         * SAA7146 audio channel does not always reset properly and
-                 * sometimes causes the first few TrimDAC writes to malfunction.
+         * sometimes causes the first few TrimDAC writes to malfunction.
-                 */
+         */
-                LoadTrimDACs(dev);
+        LoadTrimDACs(dev);
-                LoadTrimDACs(dev);      /*  Insurance. */
+        LoadTrimDACs(dev);      /*  Insurance. */
-                /* Manually init all gate array hardware in case this is a soft
+        /* Manually init all gate array hardware in case this is a soft
-                 * reset (we have no way of determining whether this is a warm
+         * reset (we have no way of determining whether this is a warm
-                 * or cold start).  This is necessary because the gate array will
+         * or cold start).  This is necessary because the gate array will
-                 * reset only in response to a PCI hard reset; there is no soft
+         * reset only in response to a PCI hard reset; there is no soft
-                 * reset function. */
+         * reset function. */
-                /* Init all DAC outputs to 0V and init all DAC setpoint and
+        /* Init all DAC outputs to 0V and init all DAC setpoint and
-                 * polarity images.
+         * polarity images.
-                 */
+         */
-                for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
+        for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
-                        SetDAC(dev, chan, 0);
+                SetDAC(dev, chan, 0);
-                /* Init image of WRMISC2 Battery Charger Enabled control bit.
+        /* Init image of WRMISC2 Battery Charger Enabled control bit.
-                 * This image is used when the state of the charger control bit,
+         * This image is used when the state of the charger control bit,
-                 * which has no direct hardware readback mechanism, is queried.
+         * which has no direct hardware readback mechanism, is queried.
-                 */
+         */
-                devpriv->ChargeEnabled = 0;
+        devpriv->ChargeEnabled = 0;
-                /* Init image of watchdog timer interval in WRMISC2.  This image
+        /* Init image of watchdog timer interval in WRMISC2.  This image
-                 * maintains the value of the control bits of MISC2 are
+         * maintains the value of the control bits of MISC2 are
-                 * continuously reset to zero as long as the WD timer is disabled.
+         * continuously reset to zero as long as the WD timer is disabled.
-                 */
+         */
-                devpriv->WDInterval = 0;
+        devpriv->WDInterval = 0;
-                /* Init Counter Interrupt enab mask for RDMISC2.  This mask is
+        /* Init Counter Interrupt enab mask for RDMISC2.  This mask is
-                 * applied against MISC2 when testing to determine which timer
+         * applied against MISC2 when testing to determine which timer
-                 * events are requesting interrupt service.
+         * events are requesting interrupt service.
-                 */
+         */
-                devpriv->CounterIntEnabs = 0;
+        devpriv->CounterIntEnabs = 0;
-                /*  Init counters. */
+        /*  Init counters. */
-                CountersInit(dev);
+        CountersInit(dev);
-                /* Without modifying the state of the Battery Backup enab, disable
+        /* Without modifying the state of the Battery Backup enab, disable
-                 * the watchdog timer, set DIO channels 0-5 to operate in the
+         * the watchdog timer, set DIO channels 0-5 to operate in the
-                 * standard DIO (vs. counter overflow) mode, disable the battery
+         * standard DIO (vs. counter overflow) mode, disable the battery
-                 * charger, and reset the watchdog interval selector to zero.
+         * charger, and reset the watchdog interval selector to zero.
-                 */
+         */
-                WriteMISC2(dev, (uint16_t) (DEBIread(dev,
+        WriteMISC2(dev, (uint16_t)(DEBIread(dev, LP_RDMISC2) &
-                                                     LP_RDMISC2) &
+                                   MISC2_BATT_ENABLE));
-                                            MISC2_BATT_ENABLE));
-                /*  Initialize the digital I/O subsystem. */
+        /*  Initialize the digital I/O subsystem. */
-                s626_dio_init(dev);
+        s626_dio_init(dev);
-                /* enable interrupt test */
+        /* enable interrupt test */
-                /*  writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
+        /*  writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
-        }
 }
 static int s626_attach_pci(struct comedi_device *dev, struct pci_dev *pcidev)
author	H Hartley Sweeten <hartleys@visionengravers.com>	2012-09-24 16:37:36 -0400
committer	Greg Kroah-Hartman <gregkh@linuxfoundation.org>	2012-09-26 12:37:31 -0400
commit	68ad0ae0eac07911e6749e28da75d77d25524864 (patch)
tree	b4f15cefa8216fb1ee33d63e99f0e53fba612021
parent	f996ab29e9dd1ed607ea9ba708dff6fa4d253859 (diff)

diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c index 07ff93b996c0..cd09c37570bc 100644 --- a/drivers/staging/comedi/drivers/s626.c +++ b/drivers/staging/comedi/drivers/s626.c
@@ -80,7 +80,6 @@ INSN_CONFIG instructions:
80		80
81	struct s626_private {	81	struct s626_private {
82	void __iomem *base_addr;	82	void __iomem *base_addr;
83	short allocatedBuf;
84	uint8_t ai_cmd_running; /* ai_cmd is running */	83	uint8_t ai_cmd_running; /* ai_cmd is running */
85	uint8_t ai_continous; /* continous acquisition */	84	uint8_t ai_continous; /* continous acquisition */
86	int ai_sample_count; /* number of samples to acquire */	85	int ai_sample_count; /* number of samples to acquire */
@@ -2443,24 +2442,18 @@ static int s626_allocate_dma_buffers(struct comedi_device *dev)
2443	void *addr;	2442	void *addr;
2444	dma_addr_t appdma;	2443	dma_addr_t appdma;
2445		2444
2446	devpriv->allocatedBuf = 0;
2447
2448	addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);	2445	addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
2449	if (!addr)	2446	if (!addr)
2450	return -ENOMEM;	2447	return -ENOMEM;
2451	devpriv->ANABuf.LogicalBase = addr;	2448	devpriv->ANABuf.LogicalBase = addr;
2452	devpriv->ANABuf.PhysicalBase = appdma;	2449	devpriv->ANABuf.PhysicalBase = appdma;
2453		2450
2454	devpriv->allocatedBuf++;
2455
2456	addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);	2451	addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
2457	if (!addr)	2452	if (!addr)
2458	return -ENOMEM;	2453	return -ENOMEM;
2459	devpriv->RPSBuf.LogicalBase = addr;	2454	devpriv->RPSBuf.LogicalBase = addr;
2460	devpriv->RPSBuf.PhysicalBase = appdma;	2455	devpriv->RPSBuf.PhysicalBase = appdma;
2461		2456
2462	devpriv->allocatedBuf++;
2463
2464	return 0;	2457	return 0;
2465	}	2458	}
2466		2459
@@ -2471,117 +2464,116 @@ static void s626_initialize(struct comedi_device *dev)
2471	/* uint16_t StartVal; */	2464	/* uint16_t StartVal; */
2472	/* uint16_t index; */	2465	/* uint16_t index; */
2473	/* unsigned int data[16]; */	2466	/* unsigned int data[16]; */
		2467	dma_addr_t pPhysBuf;
		2468	uint16_t chan;
2474	int i;	2469	int i;
2475		2470
2476	if (devpriv->allocatedBuf == 2) {
2477	dma_addr_t pPhysBuf;
2478	uint16_t chan;
2479
2480	/* enab DEBI and audio pins, enable I2C interface. */
2481	MC_ENABLE(P_MC1, MC1_DEBI \| MC1_AUDIO \| MC1_I2C);
2482	/* Configure DEBI operating mode. */
2483	WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
2484	/* bits wide. */
2485	\| (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
2486
2487	/* Declare DEBI */
2488	/* transfer timeout */
2489	/* interval. */
2490	\|DEBI_SWAP /* Set up byte lane */
2491	/* steering. */
2492	\| DEBI_CFG_INTEL); /* Intel-compatible */
2493	/* local bus (DEBI */
2494	/* never times out). */
2495
2496	/* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL \| DEBI_CFG_TOQ */
2497	/* \| DEBI_CFG_INCQ\| DEBI_CFG_16Q); //end */
2498
2499	/* Paging is disabled. */
2500	WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
2501
2502	/* Init GPIO so that ADC Start* is negated. */
2503	WR7146(P_GPIO, GPIO_BASE \| GPIO1_HI);
2504
2505	/* IsBoardRevA is a boolean that indicates whether the board is RevA.
2506	*
2507	* VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
2508	* EEPROM ADDRESS SELECTION. Initialize the I2C interface, which
2509	* is used to access the onboard serial EEPROM. The EEPROM's I2C
2510	* DeviceAddress is hardwired to a value that is dependent on the
2511	* 626 board revision. On all board revisions, the EEPROM stores
2512	* TrimDAC calibration constants for analog I/O. On RevB and
2513	* higher boards, the DeviceAddress is hardwired to 0 to enable
2514	* the EEPROM to also store the PCI SubVendorID and SubDeviceID;
2515	* this is the address at which the SAA7146 expects a
2516	* configuration EEPROM to reside. On RevA boards, the EEPROM
2517	* device address, which is hardwired to 4, prevents the SAA7146
2518	* from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
2519	* default values, instead.
2520	*/
2521		2471
2522	/* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */	2472	/* enab DEBI and audio pins, enable I2C interface. */
2523	/* DeviceType (0xA0) */	2473	MC_ENABLE(P_MC1, MC1_DEBI \| MC1_AUDIO \| MC1_I2C);
2524	/* and DeviceAddress<<1. */	2474	/* Configure DEBI operating mode. */
		2475	WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
		2476	/* bits wide. */
		2477	\| (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
		2478
		2479	/* Declare DEBI */
		2480	/* transfer timeout */
		2481	/* interval. */
		2482	\|DEBI_SWAP /* Set up byte lane */
		2483	/* steering. */
		2484	\| DEBI_CFG_INTEL); /* Intel-compatible */
		2485	/* local bus (DEBI */
		2486	/* never times out). */
		2487
		2488	/* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL \| DEBI_CFG_TOQ */
		2489	/* \| DEBI_CFG_INCQ\| DEBI_CFG_16Q); //end */
		2490
		2491	/* Paging is disabled. */
		2492	WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
		2493
		2494	/* Init GPIO so that ADC Start* is negated. */
		2495	WR7146(P_GPIO, GPIO_BASE \| GPIO1_HI);
		2496
		2497	/* IsBoardRevA is a boolean that indicates whether the board is RevA.
		2498	*
		2499	* VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
		2500	* EEPROM ADDRESS SELECTION. Initialize the I2C interface, which
		2501	* is used to access the onboard serial EEPROM. The EEPROM's I2C
		2502	* DeviceAddress is hardwired to a value that is dependent on the
		2503	* 626 board revision. On all board revisions, the EEPROM stores
		2504	* TrimDAC calibration constants for analog I/O. On RevB and
		2505	* higher boards, the DeviceAddress is hardwired to 0 to enable
		2506	* the EEPROM to also store the PCI SubVendorID and SubDeviceID;
		2507	* this is the address at which the SAA7146 expects a
		2508	* configuration EEPROM to reside. On RevA boards, the EEPROM
		2509	* device address, which is hardwired to 4, prevents the SAA7146
		2510	* from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
		2511	* default values, instead.
		2512	*/
		2513
		2514	/* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
		2515	/* DeviceType (0xA0) */
		2516	/* and DeviceAddress<<1. */
2525		2517
2526	devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */	2518	devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */
2527	/* eeprom(revb) */	2519	/* eeprom(revb) */
2528		2520
2529	/* Issue an I2C ABORT command to halt any I2C operation in */	2521	/* Issue an I2C ABORT command to halt any I2C operation in */
2530	/* progress and reset BUSY flag. */	2522	/* progress and reset BUSY flag. */
2531	WR7146(P_I2CSTAT, I2C_CLKSEL \| I2C_ABORT);	2523	WR7146(P_I2CSTAT, I2C_CLKSEL \| I2C_ABORT);
2532	/* Write I2C control: abort any I2C activity. */	2524	/* Write I2C control: abort any I2C activity. */
2533	MC_ENABLE(P_MC2, MC2_UPLD_IIC);	2525	MC_ENABLE(P_MC2, MC2_UPLD_IIC);
2534	/* Invoke command upload */	2526	/* Invoke command upload */
2535	while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)	2527	while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
		2528	;
		2529	/* and wait for upload to complete. */
		2530
		2531	/* Per SAA7146 data sheet, write to STATUS reg twice to
		2532	* reset all I2C error flags. */
		2533	for (i = 0; i < 2; i++) {
		2534	WR7146(P_I2CSTAT, I2C_CLKSEL);
		2535	/* Write I2C control: reset error flags. */
		2536	MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
		2537	while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
2536	;	2538	;
2537	/* and wait for upload to complete. */	2539	/* and wait for upload to complete. */
2538		2540	}
2539	/* Per SAA7146 data sheet, write to STATUS reg twice to
2540	* reset all I2C error flags. */
2541	for (i = 0; i < 2; i++) {
2542	WR7146(P_I2CSTAT, I2C_CLKSEL);
2543	/* Write I2C control: reset error flags. */
2544	MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
2545	while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
2546	;
2547	/* and wait for upload to complete. */
2548	}
2549		2541
2550	/* Init audio interface functional attributes: set DAC/ADC	2542	/* Init audio interface functional attributes: set DAC/ADC
2551	* serial clock rates, invert DAC serial clock so that	2543	* serial clock rates, invert DAC serial clock so that
2552	* DAC data setup times are satisfied, enable DAC serial	2544	* DAC data setup times are satisfied, enable DAC serial
2553	* clock out.	2545	* clock out.
2554	*/	2546	*/
2555		2547
2556	WR7146(P_ACON2, ACON2_INIT);	2548	WR7146(P_ACON2, ACON2_INIT);
2557		2549
2558	/* Set up TSL1 slot list, which is used to control the	2550	/* Set up TSL1 slot list, which is used to control the
2559	* accumulation of ADC data: RSD1 = shift data in on SD1.	2551	* accumulation of ADC data: RSD1 = shift data in on SD1.
2560	* SIB_A1 = store data uint8_t at next available location in	2552	* SIB_A1 = store data uint8_t at next available location in
2561	* FB BUFFER1 register. */	2553	* FB BUFFER1 register. */
2562	WR7146(P_TSL1, RSD1 \| SIB_A1);	2554	WR7146(P_TSL1, RSD1 \| SIB_A1);
2563	/* Fetch ADC high data uint8_t. */	2555	/* Fetch ADC high data uint8_t. */
2564	WR7146(P_TSL1 + 4, RSD1 \| SIB_A1 \| EOS);	2556	WR7146(P_TSL1 + 4, RSD1 \| SIB_A1 \| EOS);
2565	/* Fetch ADC low data uint8_t; end of TSL1. */	2557	/* Fetch ADC low data uint8_t; end of TSL1. */
2566		2558
2567	/* enab TSL1 slot list so that it executes all the time. */	2559	/* enab TSL1 slot list so that it executes all the time. */
2568	WR7146(P_ACON1, ACON1_ADCSTART);	2560	WR7146(P_ACON1, ACON1_ADCSTART);
2569		2561
2570	/* Initialize RPS registers used for ADC. */	2562	/* Initialize RPS registers used for ADC. */
2571		2563
2572	/* Physical start of RPS program. */	2564	/* Physical start of RPS program. */
2573	WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);	2565	WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
2574		2566
2575	WR7146(P_RPSPAGE1, 0);	2567	WR7146(P_RPSPAGE1, 0);
2576	/* RPS program performs no explicit mem writes. */	2568	/* RPS program performs no explicit mem writes. */
2577	WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */	2569	WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */
2578		2570
2579	/* SAA7146 BUG WORKAROUND. Initialize SAA7146 ADC interface	2571	/* SAA7146 BUG WORKAROUND. Initialize SAA7146 ADC interface
2580	* to a known state by invoking ADCs until FB BUFFER 1	2572	* to a known state by invoking ADCs until FB BUFFER 1
2581	* register shows that it is correctly receiving ADC data.	2573	* register shows that it is correctly receiving ADC data.
2582	* This is necessary because the SAA7146 ADC interface does	2574	* This is necessary because the SAA7146 ADC interface does
2583	* not start up in a defined state after a PCI reset.	2575	* not start up in a defined state after a PCI reset.
2584	*/	2576	*/
2585		2577
2586	/* PollList = EOPL; // Create a simple polling */	2578	/* PollList = EOPL; // Create a simple polling */
2587	/* // list for analog input */	2579	/* // list for analog input */
@@ -2609,124 +2601,121 @@ static void s626_initialize(struct comedi_device *dev)
2609	/* break; */	2601	/* break; */
2610	/* } */	2602	/* } */
2611		2603
2612	/* end initADC */	2604	/* end initADC */
2613		2605
2614	/* init the DAC interface */	2606	/* init the DAC interface */
2615		2607
2616	/* Init Audio2's output DMAC attributes: burst length = 1	2608	/* Init Audio2's output DMAC attributes: burst length = 1
2617	* DWORD, threshold = 1 DWORD.	2609	* DWORD, threshold = 1 DWORD.
2618	*/	2610	*/
2619	WR7146(P_PCI_BT_A, 0);	2611	WR7146(P_PCI_BT_A, 0);
2620		2612
2621	/* Init Audio2's output DMA physical addresses. The protection	2613	/* Init Audio2's output DMA physical addresses. The protection
2622	* address is set to 1 DWORD past the base address so that a	2614	* address is set to 1 DWORD past the base address so that a
2623	* single DWORD will be transferred each time a DMA transfer is	2615	* single DWORD will be transferred each time a DMA transfer is
2624	* enabled. */	2616	* enabled. */
2625		2617
2626	pPhysBuf =	2618	pPhysBuf = devpriv->ANABuf.PhysicalBase +
2627	devpriv->ANABuf.PhysicalBase +	2619	(DAC_WDMABUF_OS * sizeof(uint32_t));
2628	(DAC_WDMABUF_OS * sizeof(uint32_t));	2620
2629		2621	WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */
2630	WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */	2622	WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */
2631	WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */	2623
2632		2624	/* Cache Audio2's output DMA buffer logical address. This is
2633	/* Cache Audio2's output DMA buffer logical address. This is	2625	* where DAC data is buffered for A2 output DMA transfers. */
2634	* where DAC data is buffered for A2 output DMA transfers. */	2626	devpriv->pDacWBuf = (uint32_t *)devpriv->ANABuf.LogicalBase +
2635	devpriv->pDacWBuf =	2627	DAC_WDMABUF_OS;
2636	(uint32_t *) devpriv->ANABuf.LogicalBase + DAC_WDMABUF_OS;	2628
2637		2629	/* Audio2's output channels does not use paging. The protection
2638	/* Audio2's output channels does not use paging. The protection	2630	* violation handling bit is set so that the DMAC will
2639	* violation handling bit is set so that the DMAC will	2631	* automatically halt and its PCI address pointer will be reset
2640	* automatically halt and its PCI address pointer will be reset	2632	* when the protection address is reached. */
2641	* when the protection address is reached. */	2633
2642		2634	WR7146(P_PAGEA2_OUT, 8);
2643	WR7146(P_PAGEA2_OUT, 8);	2635
2644		2636	/* Initialize time slot list 2 (TSL2), which is used to control
2645	/* Initialize time slot list 2 (TSL2), which is used to control	2637	* the clock generation for and serialization of data to be sent
2646	* the clock generation for and serialization of data to be sent	2638	* to the DAC devices. Slot 0 is a NOP that is used to trap TSL
2647	* to the DAC devices. Slot 0 is a NOP that is used to trap TSL	2639	* execution; this permits other slots to be safely modified
2648	* execution; this permits other slots to be safely modified	2640	* without first turning off the TSL sequencer (which is
2649	* without first turning off the TSL sequencer (which is	2641	* apparently impossible to do). Also, SD3 (which is driven by a
2650	* apparently impossible to do). Also, SD3 (which is driven by a	2642	* pull-up resistor) is shifted in and stored to the MSB of
2651	* pull-up resistor) is shifted in and stored to the MSB of	2643	* FB_BUFFER2 to be used as evidence that the slot sequence has
2652	* FB_BUFFER2 to be used as evidence that the slot sequence has	2644	* not yet finished executing.
2653	* not yet finished executing.	2645	*/
2654	*/
2655		2646
2656	SETVECT(0, XSD2 \| RSD3 \| SIB_A2 \| EOS);	2647	SETVECT(0, XSD2 \| RSD3 \| SIB_A2 \| EOS);
2657	/* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */	2648	/* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
2658		2649
2659	/* Initialize slot 1, which is constant. Slot 1 causes a	2650	/* Initialize slot 1, which is constant. Slot 1 causes a
2660	* DWORD to be transferred from audio channel 2's output FIFO	2651	* DWORD to be transferred from audio channel 2's output FIFO
2661	* to the FIFO's output buffer so that it can be serialized	2652	* to the FIFO's output buffer so that it can be serialized
2662	* and sent to the DAC during subsequent slots. All remaining	2653	* and sent to the DAC during subsequent slots. All remaining
2663	* slots are dynamically populated as required by the target	2654	* slots are dynamically populated as required by the target
2664	* DAC device.	2655	* DAC device.
2665	*/	2656	*/
2666	SETVECT(1, LF_A2);	2657	SETVECT(1, LF_A2);
2667	/* Slot 1: Fetch DWORD from Audio2's output FIFO. */	2658	/* Slot 1: Fetch DWORD from Audio2's output FIFO. */
2668		2659
2669	/* Start DAC's audio interface (TSL2) running. */	2660	/* Start DAC's audio interface (TSL2) running. */
2670	WR7146(P_ACON1, ACON1_DACSTART);	2661	WR7146(P_ACON1, ACON1_DACSTART);
2671		2662
2672	/* end init DAC interface */	2663	/* end init DAC interface */
2673		2664
2674	/* Init Trim DACs to calibrated values. Do it twice because the	2665	/* Init Trim DACs to calibrated values. Do it twice because the
2675	* SAA7146 audio channel does not always reset properly and	2666	* SAA7146 audio channel does not always reset properly and
2676	* sometimes causes the first few TrimDAC writes to malfunction.	2667	* sometimes causes the first few TrimDAC writes to malfunction.
2677	*/	2668	*/
2678		2669
2679	LoadTrimDACs(dev);	2670	LoadTrimDACs(dev);
2680	LoadTrimDACs(dev); /* Insurance. */	2671	LoadTrimDACs(dev); /* Insurance. */
2681		2672
2682	/* Manually init all gate array hardware in case this is a soft	2673	/* Manually init all gate array hardware in case this is a soft
2683	* reset (we have no way of determining whether this is a warm	2674	* reset (we have no way of determining whether this is a warm
2684	* or cold start). This is necessary because the gate array will	2675	* or cold start). This is necessary because the gate array will
2685	* reset only in response to a PCI hard reset; there is no soft	2676	* reset only in response to a PCI hard reset; there is no soft
2686	* reset function. */	2677	* reset function. */
2687		2678
2688	/* Init all DAC outputs to 0V and init all DAC setpoint and	2679	/* Init all DAC outputs to 0V and init all DAC setpoint and
2689	* polarity images.	2680	* polarity images.
2690	*/	2681	*/
2691	for (chan = 0; chan < S626_DAC_CHANNELS; chan++)	2682	for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
2692	SetDAC(dev, chan, 0);	2683	SetDAC(dev, chan, 0);
2693		2684
2694	/* Init image of WRMISC2 Battery Charger Enabled control bit.	2685	/* Init image of WRMISC2 Battery Charger Enabled control bit.
2695	* This image is used when the state of the charger control bit,	2686	* This image is used when the state of the charger control bit,
2696	* which has no direct hardware readback mechanism, is queried.	2687	* which has no direct hardware readback mechanism, is queried.
2697	*/	2688	*/
2698	devpriv->ChargeEnabled = 0;	2689	devpriv->ChargeEnabled = 0;
2699		2690
2700	/* Init image of watchdog timer interval in WRMISC2. This image	2691	/* Init image of watchdog timer interval in WRMISC2. This image
2701	* maintains the value of the control bits of MISC2 are	2692	* maintains the value of the control bits of MISC2 are
2702	* continuously reset to zero as long as the WD timer is disabled.	2693	* continuously reset to zero as long as the WD timer is disabled.
2703	*/	2694	*/
2704	devpriv->WDInterval = 0;	2695	devpriv->WDInterval = 0;
2705		2696
2706	/* Init Counter Interrupt enab mask for RDMISC2. This mask is	2697	/* Init Counter Interrupt enab mask for RDMISC2. This mask is
2707	* applied against MISC2 when testing to determine which timer	2698	* applied against MISC2 when testing to determine which timer
2708	* events are requesting interrupt service.	2699	* events are requesting interrupt service.
2709	*/	2700	*/
2710	devpriv->CounterIntEnabs = 0;	2701	devpriv->CounterIntEnabs = 0;
2711		2702
2712	/* Init counters. */	2703	/* Init counters. */
2713	CountersInit(dev);	2704	CountersInit(dev);
2714		2705
2715	/* Without modifying the state of the Battery Backup enab, disable	2706	/* Without modifying the state of the Battery Backup enab, disable
2716	* the watchdog timer, set DIO channels 0-5 to operate in the	2707	* the watchdog timer, set DIO channels 0-5 to operate in the
2717	* standard DIO (vs. counter overflow) mode, disable the battery	2708	* standard DIO (vs. counter overflow) mode, disable the battery
2718	* charger, and reset the watchdog interval selector to zero.	2709	* charger, and reset the watchdog interval selector to zero.
2719	*/	2710	*/
2720	WriteMISC2(dev, (uint16_t) (DEBIread(dev,	2711	WriteMISC2(dev, (uint16_t)(DEBIread(dev, LP_RDMISC2) &
2721	LP_RDMISC2) &	2712	MISC2_BATT_ENABLE));
2722	MISC2_BATT_ENABLE));
2723		2713
2724	/* Initialize the digital I/O subsystem. */	2714	/* Initialize the digital I/O subsystem. */
2725	s626_dio_init(dev);	2715	s626_dio_init(dev);
2726		2716
2727	/* enable interrupt test */	2717	/* enable interrupt test */
2728	/* writel(IRQ_GPIO3 \| IRQ_RPS1,devpriv->base_addr+P_IER); */	2718	/* writel(IRQ_GPIO3 \| IRQ_RPS1,devpriv->base_addr+P_IER); */
2729	}
2730	}	2719	}
2731		2720
2732	static int s626_attach_pci(struct comedi_device dev, struct pci_dev pcidev)	2721	static int s626_attach_pci(struct comedi_device dev, struct pci_dev pcidev)