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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-09-02 08:12:17 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-09-29 10:53:36 -0400
commit67956867aa07c59d6d83628bbc9ee4bd9799a1e1 (patch)
treebf051149c71e52291497e8ec41188dce5ddc3941
parentc479f4383ea8940dd6f88da61798ad31feb33e51 (diff)
drm/i915: Don't spam dmesg with rps messages on vlv/chv
If the GPU frequency isn't going to change don't spam dmesg with debug messages about it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 45f2aa0b8fe5..c27b6140bfd1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3491,17 +3491,18 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
3491 WARN_ON(val > dev_priv->rps.max_freq_softlimit); 3491 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3492 WARN_ON(val < dev_priv->rps.min_freq_softlimit); 3492 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3493 3493
3494 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3495 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3496 dev_priv->rps.cur_freq,
3497 vlv_gpu_freq(dev_priv, val), val);
3498
3499 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), 3494 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3500 "Odd GPU freq value\n")) 3495 "Odd GPU freq value\n"))
3501 val &= ~1; 3496 val &= ~1;
3502 3497
3503 if (val != dev_priv->rps.cur_freq) 3498 if (val != dev_priv->rps.cur_freq) {
3499 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3500 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3501 dev_priv->rps.cur_freq,
3502 vlv_gpu_freq(dev_priv, val), val);
3503
3504 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); 3504 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3505 }
3505 3506
3506 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 3507 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3507 3508