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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2013-12-06 04:59:46 -0500
committerSimon Horman <horms+renesas@verge.net.au>2013-12-24 07:09:18 -0500
commit6319ea5089a267b3a1cbd1d745ecc7cdae9a0a7e (patch)
treed9601489fa5f22388b1ace895a64fc5f86109242
parent52613951a600207df9d75185b677d91bbde44a9e (diff)
ARM: shmobile: r8a7790: Don't set plat_sci_port scbrr_algo_id field
The field will be removed from the sh-sci driver. Don't set it and let the driver handle baud rate calculation internally. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 8bfdc3627971..66476d21544d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -100,11 +100,10 @@ void __init r8a7790_pinmux_init(void)
100 r8a7790_register_i2c(3); 100 r8a7790_register_i2c(3);
101} 101}
102 102
103#define __R8A7790_SCIF(scif_type, _scscr, algo, index, baseaddr, irq) \ 103#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
104static struct plat_sci_port scif##index##_platform_data = { \ 104static struct plat_sci_port scif##index##_platform_data = { \
105 .type = scif_type, \ 105 .type = scif_type, \
106 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 106 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
107 .scbrr_algo_id = algo, \
108 .scscr = _scscr, \ 107 .scscr = _scscr, \
109}; \ 108}; \
110 \ 109 \
@@ -115,19 +114,19 @@ static struct resource scif##index##_resources[] = { \
115 114
116#define R8A7790_SCIF(index, baseaddr, irq) \ 115#define R8A7790_SCIF(index, baseaddr, irq) \
117 __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \ 116 __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
118 SCBRR_ALGO_2, index, baseaddr, irq) 117 index, baseaddr, irq)
119 118
120#define R8A7790_SCIFA(index, baseaddr, irq) \ 119#define R8A7790_SCIFA(index, baseaddr, irq) \
121 __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ 120 __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
122 SCBRR_ALGO_4, index, baseaddr, irq) 121 index, baseaddr, irq)
123 122
124#define R8A7790_SCIFB(index, baseaddr, irq) \ 123#define R8A7790_SCIFB(index, baseaddr, irq) \
125 __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ 124 __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
126 SCBRR_ALGO_4, index, baseaddr, irq) 125 index, baseaddr, irq)
127 126
128#define R8A7790_HSCIF(index, baseaddr, irq) \ 127#define R8A7790_HSCIF(index, baseaddr, irq) \
129 __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \ 128 __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
130 SCBRR_ALGO_6, index, baseaddr, irq) 129 index, baseaddr, irq)
131 130
132R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ 131R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
133R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ 132R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */