diff options
author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-12-05 05:44:07 -0500 |
---|---|---|
committer | Stephen Warren <swarren@nvidia.com> | 2013-12-16 16:09:20 -0500 |
commit | 5fc6b0dd319c5b726b4cad379bea6ddd3b4a380f (patch) | |
tree | f7fc452d901e95740bd593b250883e14494599e7 | |
parent | b758df2e2af6bbd100fad85473dcf49c2f31d39a (diff) |
ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl defines
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra114 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r-- | arch/arm/boot/dts/tegra114-dalmore.dts | 548 | ||||
-rw-r--r-- | arch/arm/boot/dts/tegra114.dtsi | 1 |
2 files changed, 275 insertions, 274 deletions
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 5d2d6f6387e8..88be40cf8845 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts | |||
@@ -19,41 +19,41 @@ | |||
19 | clk1_out_pw4 { | 19 | clk1_out_pw4 { |
20 | nvidia,pins = "clk1_out_pw4"; | 20 | nvidia,pins = "clk1_out_pw4"; |
21 | nvidia,function = "extperiph1"; | 21 | nvidia,function = "extperiph1"; |
22 | nvidia,pull = <0>; | 22 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
23 | nvidia,tristate = <0>; | 23 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
24 | nvidia,enable-input = <0>; | 24 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
25 | }; | 25 | }; |
26 | dap1_din_pn1 { | 26 | dap1_din_pn1 { |
27 | nvidia,pins = "dap1_din_pn1"; | 27 | nvidia,pins = "dap1_din_pn1"; |
28 | nvidia,function = "i2s0"; | 28 | nvidia,function = "i2s0"; |
29 | nvidia,pull = <0>; | 29 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
30 | nvidia,tristate = <1>; | 30 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
31 | nvidia,enable-input = <1>; | 31 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
32 | }; | 32 | }; |
33 | dap1_dout_pn2 { | 33 | dap1_dout_pn2 { |
34 | nvidia,pins = "dap1_dout_pn2", | 34 | nvidia,pins = "dap1_dout_pn2", |
35 | "dap1_fs_pn0", | 35 | "dap1_fs_pn0", |
36 | "dap1_sclk_pn3"; | 36 | "dap1_sclk_pn3"; |
37 | nvidia,function = "i2s0"; | 37 | nvidia,function = "i2s0"; |
38 | nvidia,pull = <0>; | 38 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
39 | nvidia,tristate = <0>; | 39 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
40 | nvidia,enable-input = <1>; | 40 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
41 | }; | 41 | }; |
42 | dap2_din_pa4 { | 42 | dap2_din_pa4 { |
43 | nvidia,pins = "dap2_din_pa4"; | 43 | nvidia,pins = "dap2_din_pa4"; |
44 | nvidia,function = "i2s1"; | 44 | nvidia,function = "i2s1"; |
45 | nvidia,pull = <0>; | 45 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
46 | nvidia,tristate = <1>; | 46 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
47 | nvidia,enable-input = <1>; | 47 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
48 | }; | 48 | }; |
49 | dap2_dout_pa5 { | 49 | dap2_dout_pa5 { |
50 | nvidia,pins = "dap2_dout_pa5", | 50 | nvidia,pins = "dap2_dout_pa5", |
51 | "dap2_fs_pa2", | 51 | "dap2_fs_pa2", |
52 | "dap2_sclk_pa3"; | 52 | "dap2_sclk_pa3"; |
53 | nvidia,function = "i2s1"; | 53 | nvidia,function = "i2s1"; |
54 | nvidia,pull = <0>; | 54 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
55 | nvidia,tristate = <0>; | 55 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
56 | nvidia,enable-input = <1>; | 56 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
57 | }; | 57 | }; |
58 | dap4_din_pp5 { | 58 | dap4_din_pp5 { |
59 | nvidia,pins = "dap4_din_pp5", | 59 | nvidia,pins = "dap4_din_pp5", |
@@ -61,17 +61,17 @@ | |||
61 | "dap4_fs_pp4", | 61 | "dap4_fs_pp4", |
62 | "dap4_sclk_pp7"; | 62 | "dap4_sclk_pp7"; |
63 | nvidia,function = "i2s3"; | 63 | nvidia,function = "i2s3"; |
64 | nvidia,pull = <0>; | 64 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
65 | nvidia,tristate = <0>; | 65 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
66 | nvidia,enable-input = <1>; | 66 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
67 | }; | 67 | }; |
68 | dvfs_pwm_px0 { | 68 | dvfs_pwm_px0 { |
69 | nvidia,pins = "dvfs_pwm_px0", | 69 | nvidia,pins = "dvfs_pwm_px0", |
70 | "dvfs_clk_px2"; | 70 | "dvfs_clk_px2"; |
71 | nvidia,function = "cldvfs"; | 71 | nvidia,function = "cldvfs"; |
72 | nvidia,pull = <0>; | 72 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
73 | nvidia,tristate = <0>; | 73 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
74 | nvidia,enable-input = <0>; | 74 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
75 | }; | 75 | }; |
76 | ulpi_clk_py0 { | 76 | ulpi_clk_py0 { |
77 | nvidia,pins = "ulpi_clk_py0", | 77 | nvidia,pins = "ulpi_clk_py0", |
@@ -84,128 +84,128 @@ | |||
84 | "ulpi_data6_po7", | 84 | "ulpi_data6_po7", |
85 | "ulpi_data7_po0"; | 85 | "ulpi_data7_po0"; |
86 | nvidia,function = "ulpi"; | 86 | nvidia,function = "ulpi"; |
87 | nvidia,pull = <0>; | 87 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
88 | nvidia,tristate = <0>; | 88 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
89 | nvidia,enable-input = <1>; | 89 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
90 | }; | 90 | }; |
91 | ulpi_dir_py1 { | 91 | ulpi_dir_py1 { |
92 | nvidia,pins = "ulpi_dir_py1", | 92 | nvidia,pins = "ulpi_dir_py1", |
93 | "ulpi_nxt_py2"; | 93 | "ulpi_nxt_py2"; |
94 | nvidia,function = "ulpi"; | 94 | nvidia,function = "ulpi"; |
95 | nvidia,pull = <0>; | 95 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
96 | nvidia,tristate = <1>; | 96 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
97 | nvidia,enable-input = <1>; | 97 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
98 | }; | 98 | }; |
99 | ulpi_stp_py3 { | 99 | ulpi_stp_py3 { |
100 | nvidia,pins = "ulpi_stp_py3"; | 100 | nvidia,pins = "ulpi_stp_py3"; |
101 | nvidia,function = "ulpi"; | 101 | nvidia,function = "ulpi"; |
102 | nvidia,pull = <0>; | 102 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
103 | nvidia,tristate = <0>; | 103 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
104 | nvidia,enable-input = <0>; | 104 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
105 | }; | 105 | }; |
106 | cam_i2c_scl_pbb1 { | 106 | cam_i2c_scl_pbb1 { |
107 | nvidia,pins = "cam_i2c_scl_pbb1", | 107 | nvidia,pins = "cam_i2c_scl_pbb1", |
108 | "cam_i2c_sda_pbb2"; | 108 | "cam_i2c_sda_pbb2"; |
109 | nvidia,function = "i2c3"; | 109 | nvidia,function = "i2c3"; |
110 | nvidia,pull = <0>; | 110 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
111 | nvidia,tristate = <0>; | 111 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
112 | nvidia,enable-input = <1>; | 112 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
113 | nvidia,lock = <0>; | 113 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
114 | nvidia,open-drain = <0>; | 114 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
115 | }; | 115 | }; |
116 | cam_mclk_pcc0 { | 116 | cam_mclk_pcc0 { |
117 | nvidia,pins = "cam_mclk_pcc0", | 117 | nvidia,pins = "cam_mclk_pcc0", |
118 | "pbb0"; | 118 | "pbb0"; |
119 | nvidia,function = "vi_alt3"; | 119 | nvidia,function = "vi_alt3"; |
120 | nvidia,pull = <0>; | 120 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
121 | nvidia,tristate = <0>; | 121 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
122 | nvidia,enable-input = <0>; | 122 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
123 | nvidia,lock = <0>; | 123 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
124 | }; | 124 | }; |
125 | gen2_i2c_scl_pt5 { | 125 | gen2_i2c_scl_pt5 { |
126 | nvidia,pins = "gen2_i2c_scl_pt5", | 126 | nvidia,pins = "gen2_i2c_scl_pt5", |
127 | "gen2_i2c_sda_pt6"; | 127 | "gen2_i2c_sda_pt6"; |
128 | nvidia,function = "i2c2"; | 128 | nvidia,function = "i2c2"; |
129 | nvidia,pull = <0>; | 129 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
130 | nvidia,tristate = <0>; | 130 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
131 | nvidia,enable-input = <1>; | 131 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
132 | nvidia,lock = <0>; | 132 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
133 | nvidia,open-drain = <0>; | 133 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
134 | }; | 134 | }; |
135 | gmi_a16_pj7 { | 135 | gmi_a16_pj7 { |
136 | nvidia,pins = "gmi_a16_pj7"; | 136 | nvidia,pins = "gmi_a16_pj7"; |
137 | nvidia,function = "uartd"; | 137 | nvidia,function = "uartd"; |
138 | nvidia,pull = <0>; | 138 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
139 | nvidia,tristate = <0>; | 139 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
140 | nvidia,enable-input = <0>; | 140 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
141 | }; | 141 | }; |
142 | gmi_a17_pb0 { | 142 | gmi_a17_pb0 { |
143 | nvidia,pins = "gmi_a17_pb0", | 143 | nvidia,pins = "gmi_a17_pb0", |
144 | "gmi_a18_pb1"; | 144 | "gmi_a18_pb1"; |
145 | nvidia,function = "uartd"; | 145 | nvidia,function = "uartd"; |
146 | nvidia,pull = <0>; | 146 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
147 | nvidia,tristate = <1>; | 147 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
148 | nvidia,enable-input = <1>; | 148 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
149 | }; | 149 | }; |
150 | gmi_a19_pk7 { | 150 | gmi_a19_pk7 { |
151 | nvidia,pins = "gmi_a19_pk7"; | 151 | nvidia,pins = "gmi_a19_pk7"; |
152 | nvidia,function = "uartd"; | 152 | nvidia,function = "uartd"; |
153 | nvidia,pull = <0>; | 153 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
154 | nvidia,tristate = <0>; | 154 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
155 | nvidia,enable-input = <0>; | 155 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
156 | }; | 156 | }; |
157 | gmi_ad5_pg5 { | 157 | gmi_ad5_pg5 { |
158 | nvidia,pins = "gmi_ad5_pg5", | 158 | nvidia,pins = "gmi_ad5_pg5", |
159 | "gmi_cs6_n_pi3", | 159 | "gmi_cs6_n_pi3", |
160 | "gmi_wr_n_pi0"; | 160 | "gmi_wr_n_pi0"; |
161 | nvidia,function = "spi4"; | 161 | nvidia,function = "spi4"; |
162 | nvidia,pull = <0>; | 162 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
163 | nvidia,tristate = <0>; | 163 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
164 | nvidia,enable-input = <1>; | 164 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
165 | }; | 165 | }; |
166 | gmi_ad6_pg6 { | 166 | gmi_ad6_pg6 { |
167 | nvidia,pins = "gmi_ad6_pg6", | 167 | nvidia,pins = "gmi_ad6_pg6", |
168 | "gmi_ad7_pg7"; | 168 | "gmi_ad7_pg7"; |
169 | nvidia,function = "spi4"; | 169 | nvidia,function = "spi4"; |
170 | nvidia,pull = <2>; | 170 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
171 | nvidia,tristate = <0>; | 171 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
172 | nvidia,enable-input = <1>; | 172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
173 | }; | 173 | }; |
174 | gmi_ad12_ph4 { | 174 | gmi_ad12_ph4 { |
175 | nvidia,pins = "gmi_ad12_ph4"; | 175 | nvidia,pins = "gmi_ad12_ph4"; |
176 | nvidia,function = "rsvd4"; | 176 | nvidia,function = "rsvd4"; |
177 | nvidia,pull = <0>; | 177 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
178 | nvidia,tristate = <0>; | 178 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
179 | nvidia,enable-input = <0>; | 179 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
180 | }; | 180 | }; |
181 | gmi_ad9_ph1 { | 181 | gmi_ad9_ph1 { |
182 | nvidia,pins = "gmi_ad9_ph1"; | 182 | nvidia,pins = "gmi_ad9_ph1"; |
183 | nvidia,function = "pwm1"; | 183 | nvidia,function = "pwm1"; |
184 | nvidia,pull = <0>; | 184 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
185 | nvidia,tristate = <0>; | 185 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
186 | nvidia,enable-input = <0>; | 186 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
187 | }; | 187 | }; |
188 | gmi_cs1_n_pj2 { | 188 | gmi_cs1_n_pj2 { |
189 | nvidia,pins = "gmi_cs1_n_pj2", | 189 | nvidia,pins = "gmi_cs1_n_pj2", |
190 | "gmi_oe_n_pi1"; | 190 | "gmi_oe_n_pi1"; |
191 | nvidia,function = "soc"; | 191 | nvidia,function = "soc"; |
192 | nvidia,pull = <0>; | 192 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
193 | nvidia,tristate = <1>; | 193 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
194 | nvidia,enable-input = <1>; | 194 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
195 | }; | 195 | }; |
196 | clk2_out_pw5 { | 196 | clk2_out_pw5 { |
197 | nvidia,pins = "clk2_out_pw5"; | 197 | nvidia,pins = "clk2_out_pw5"; |
198 | nvidia,function = "extperiph2"; | 198 | nvidia,function = "extperiph2"; |
199 | nvidia,pull = <0>; | 199 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
200 | nvidia,tristate = <0>; | 200 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
201 | nvidia,enable-input = <0>; | 201 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
202 | }; | 202 | }; |
203 | sdmmc1_clk_pz0 { | 203 | sdmmc1_clk_pz0 { |
204 | nvidia,pins = "sdmmc1_clk_pz0"; | 204 | nvidia,pins = "sdmmc1_clk_pz0"; |
205 | nvidia,function = "sdmmc1"; | 205 | nvidia,function = "sdmmc1"; |
206 | nvidia,pull = <0>; | 206 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
207 | nvidia,tristate = <0>; | 207 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
208 | nvidia,enable-input = <1>; | 208 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
209 | }; | 209 | }; |
210 | sdmmc1_cmd_pz1 { | 210 | sdmmc1_cmd_pz1 { |
211 | nvidia,pins = "sdmmc1_cmd_pz1", | 211 | nvidia,pins = "sdmmc1_cmd_pz1", |
@@ -214,23 +214,23 @@ | |||
214 | "sdmmc1_dat2_py5", | 214 | "sdmmc1_dat2_py5", |
215 | "sdmmc1_dat3_py4"; | 215 | "sdmmc1_dat3_py4"; |
216 | nvidia,function = "sdmmc1"; | 216 | nvidia,function = "sdmmc1"; |
217 | nvidia,pull = <2>; | 217 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
218 | nvidia,tristate = <0>; | 218 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
219 | nvidia,enable-input = <1>; | 219 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
220 | }; | 220 | }; |
221 | sdmmc1_wp_n_pv3 { | 221 | sdmmc1_wp_n_pv3 { |
222 | nvidia,pins = "sdmmc1_wp_n_pv3"; | 222 | nvidia,pins = "sdmmc1_wp_n_pv3"; |
223 | nvidia,function = "spi4"; | 223 | nvidia,function = "spi4"; |
224 | nvidia,pull = <2>; | 224 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
225 | nvidia,tristate = <0>; | 225 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
226 | nvidia,enable-input = <0>; | 226 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
227 | }; | 227 | }; |
228 | sdmmc3_clk_pa6 { | 228 | sdmmc3_clk_pa6 { |
229 | nvidia,pins = "sdmmc3_clk_pa6"; | 229 | nvidia,pins = "sdmmc3_clk_pa6"; |
230 | nvidia,function = "sdmmc3"; | 230 | nvidia,function = "sdmmc3"; |
231 | nvidia,pull = <0>; | 231 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
232 | nvidia,tristate = <0>; | 232 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
233 | nvidia,enable-input = <1>; | 233 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
234 | }; | 234 | }; |
235 | sdmmc3_cmd_pa7 { | 235 | sdmmc3_cmd_pa7 { |
236 | nvidia,pins = "sdmmc3_cmd_pa7", | 236 | nvidia,pins = "sdmmc3_cmd_pa7", |
@@ -242,16 +242,16 @@ | |||
242 | "sdmmc3_clk_lb_out_pee4", | 242 | "sdmmc3_clk_lb_out_pee4", |
243 | "sdmmc3_clk_lb_in_pee5"; | 243 | "sdmmc3_clk_lb_in_pee5"; |
244 | nvidia,function = "sdmmc3"; | 244 | nvidia,function = "sdmmc3"; |
245 | nvidia,pull = <2>; | 245 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
246 | nvidia,tristate = <0>; | 246 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
247 | nvidia,enable-input = <1>; | 247 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
248 | }; | 248 | }; |
249 | sdmmc4_clk_pcc4 { | 249 | sdmmc4_clk_pcc4 { |
250 | nvidia,pins = "sdmmc4_clk_pcc4"; | 250 | nvidia,pins = "sdmmc4_clk_pcc4"; |
251 | nvidia,function = "sdmmc4"; | 251 | nvidia,function = "sdmmc4"; |
252 | nvidia,pull = <0>; | 252 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
253 | nvidia,tristate = <0>; | 253 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
254 | nvidia,enable-input = <1>; | 254 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
255 | }; | 255 | }; |
256 | sdmmc4_cmd_pt7 { | 256 | sdmmc4_cmd_pt7 { |
257 | nvidia,pins = "sdmmc4_cmd_pt7", | 257 | nvidia,pins = "sdmmc4_cmd_pt7", |
@@ -264,16 +264,16 @@ | |||
264 | "sdmmc4_dat6_paa6", | 264 | "sdmmc4_dat6_paa6", |
265 | "sdmmc4_dat7_paa7"; | 265 | "sdmmc4_dat7_paa7"; |
266 | nvidia,function = "sdmmc4"; | 266 | nvidia,function = "sdmmc4"; |
267 | nvidia,pull = <2>; | 267 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
268 | nvidia,tristate = <0>; | 268 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
269 | nvidia,enable-input = <1>; | 269 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
270 | }; | 270 | }; |
271 | clk_32k_out_pa0 { | 271 | clk_32k_out_pa0 { |
272 | nvidia,pins = "clk_32k_out_pa0"; | 272 | nvidia,pins = "clk_32k_out_pa0"; |
273 | nvidia,function = "blink"; | 273 | nvidia,function = "blink"; |
274 | nvidia,pull = <0>; | 274 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
275 | nvidia,tristate = <0>; | 275 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
276 | nvidia,enable-input = <0>; | 276 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
277 | }; | 277 | }; |
278 | kb_col0_pq0 { | 278 | kb_col0_pq0 { |
279 | nvidia,pins = "kb_col0_pq0", | 279 | nvidia,pins = "kb_col0_pq0", |
@@ -283,265 +283,265 @@ | |||
283 | "kb_row1_pr1", | 283 | "kb_row1_pr1", |
284 | "kb_row2_pr2"; | 284 | "kb_row2_pr2"; |
285 | nvidia,function = "kbc"; | 285 | nvidia,function = "kbc"; |
286 | nvidia,pull = <2>; | 286 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
287 | nvidia,tristate = <0>; | 287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
288 | nvidia,enable-input = <1>; | 288 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
289 | }; | 289 | }; |
290 | dap3_din_pp1 { | 290 | dap3_din_pp1 { |
291 | nvidia,pins = "dap3_din_pp1", | 291 | nvidia,pins = "dap3_din_pp1", |
292 | "dap3_sclk_pp3"; | 292 | "dap3_sclk_pp3"; |
293 | nvidia,function = "displayb"; | 293 | nvidia,function = "displayb"; |
294 | nvidia,pull = <0>; | 294 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
295 | nvidia,tristate = <1>; | 295 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
296 | nvidia,enable-input = <0>; | 296 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
297 | }; | 297 | }; |
298 | pv0 { | 298 | pv0 { |
299 | nvidia,pins = "pv0"; | 299 | nvidia,pins = "pv0"; |
300 | nvidia,function = "rsvd4"; | 300 | nvidia,function = "rsvd4"; |
301 | nvidia,pull = <0>; | 301 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
302 | nvidia,tristate = <1>; | 302 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
303 | nvidia,enable-input = <0>; | 303 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
304 | }; | 304 | }; |
305 | kb_row7_pr7 { | 305 | kb_row7_pr7 { |
306 | nvidia,pins = "kb_row7_pr7"; | 306 | nvidia,pins = "kb_row7_pr7"; |
307 | nvidia,function = "rsvd2"; | 307 | nvidia,function = "rsvd2"; |
308 | nvidia,pull = <2>; | 308 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
309 | nvidia,tristate = <0>; | 309 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
310 | nvidia,enable-input = <1>; | 310 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
311 | }; | 311 | }; |
312 | kb_row10_ps2 { | 312 | kb_row10_ps2 { |
313 | nvidia,pins = "kb_row10_ps2"; | 313 | nvidia,pins = "kb_row10_ps2"; |
314 | nvidia,function = "uarta"; | 314 | nvidia,function = "uarta"; |
315 | nvidia,pull = <0>; | 315 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
316 | nvidia,tristate = <1>; | 316 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
317 | nvidia,enable-input = <1>; | 317 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
318 | }; | 318 | }; |
319 | kb_row9_ps1 { | 319 | kb_row9_ps1 { |
320 | nvidia,pins = "kb_row9_ps1"; | 320 | nvidia,pins = "kb_row9_ps1"; |
321 | nvidia,function = "uarta"; | 321 | nvidia,function = "uarta"; |
322 | nvidia,pull = <0>; | 322 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
323 | nvidia,tristate = <0>; | 323 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
324 | nvidia,enable-input = <0>; | 324 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
325 | }; | 325 | }; |
326 | pwr_i2c_scl_pz6 { | 326 | pwr_i2c_scl_pz6 { |
327 | nvidia,pins = "pwr_i2c_scl_pz6", | 327 | nvidia,pins = "pwr_i2c_scl_pz6", |
328 | "pwr_i2c_sda_pz7"; | 328 | "pwr_i2c_sda_pz7"; |
329 | nvidia,function = "i2cpwr"; | 329 | nvidia,function = "i2cpwr"; |
330 | nvidia,pull = <0>; | 330 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
331 | nvidia,tristate = <0>; | 331 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
332 | nvidia,enable-input = <1>; | 332 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
333 | nvidia,lock = <0>; | 333 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
334 | nvidia,open-drain = <0>; | 334 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
335 | }; | 335 | }; |
336 | sys_clk_req_pz5 { | 336 | sys_clk_req_pz5 { |
337 | nvidia,pins = "sys_clk_req_pz5"; | 337 | nvidia,pins = "sys_clk_req_pz5"; |
338 | nvidia,function = "sysclk"; | 338 | nvidia,function = "sysclk"; |
339 | nvidia,pull = <0>; | 339 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
340 | nvidia,tristate = <0>; | 340 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
341 | nvidia,enable-input = <0>; | 341 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
342 | }; | 342 | }; |
343 | core_pwr_req { | 343 | core_pwr_req { |
344 | nvidia,pins = "core_pwr_req"; | 344 | nvidia,pins = "core_pwr_req"; |
345 | nvidia,function = "pwron"; | 345 | nvidia,function = "pwron"; |
346 | nvidia,pull = <0>; | 346 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
347 | nvidia,tristate = <0>; | 347 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
348 | nvidia,enable-input = <0>; | 348 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
349 | }; | 349 | }; |
350 | cpu_pwr_req { | 350 | cpu_pwr_req { |
351 | nvidia,pins = "cpu_pwr_req"; | 351 | nvidia,pins = "cpu_pwr_req"; |
352 | nvidia,function = "cpu"; | 352 | nvidia,function = "cpu"; |
353 | nvidia,pull = <0>; | 353 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
354 | nvidia,tristate = <0>; | 354 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
355 | nvidia,enable-input = <0>; | 355 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
356 | }; | 356 | }; |
357 | pwr_int_n { | 357 | pwr_int_n { |
358 | nvidia,pins = "pwr_int_n"; | 358 | nvidia,pins = "pwr_int_n"; |
359 | nvidia,function = "pmi"; | 359 | nvidia,function = "pmi"; |
360 | nvidia,pull = <0>; | 360 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
361 | nvidia,tristate = <1>; | 361 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
362 | nvidia,enable-input = <1>; | 362 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
363 | }; | 363 | }; |
364 | reset_out_n { | 364 | reset_out_n { |
365 | nvidia,pins = "reset_out_n"; | 365 | nvidia,pins = "reset_out_n"; |
366 | nvidia,function = "reset_out_n"; | 366 | nvidia,function = "reset_out_n"; |
367 | nvidia,pull = <0>; | 367 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
368 | nvidia,tristate = <0>; | 368 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
369 | nvidia,enable-input = <0>; | 369 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
370 | }; | 370 | }; |
371 | clk3_out_pee0 { | 371 | clk3_out_pee0 { |
372 | nvidia,pins = "clk3_out_pee0"; | 372 | nvidia,pins = "clk3_out_pee0"; |
373 | nvidia,function = "extperiph3"; | 373 | nvidia,function = "extperiph3"; |
374 | nvidia,pull = <0>; | 374 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
375 | nvidia,tristate = <0>; | 375 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
376 | nvidia,enable-input = <0>; | 376 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
377 | }; | 377 | }; |
378 | gen1_i2c_scl_pc4 { | 378 | gen1_i2c_scl_pc4 { |
379 | nvidia,pins = "gen1_i2c_scl_pc4", | 379 | nvidia,pins = "gen1_i2c_scl_pc4", |
380 | "gen1_i2c_sda_pc5"; | 380 | "gen1_i2c_sda_pc5"; |
381 | nvidia,function = "i2c1"; | 381 | nvidia,function = "i2c1"; |
382 | nvidia,pull = <0>; | 382 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
383 | nvidia,tristate = <0>; | 383 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
384 | nvidia,enable-input = <1>; | 384 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
385 | nvidia,lock = <0>; | 385 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
386 | nvidia,open-drain = <0>; | 386 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
387 | }; | 387 | }; |
388 | uart2_cts_n_pj5 { | 388 | uart2_cts_n_pj5 { |
389 | nvidia,pins = "uart2_cts_n_pj5"; | 389 | nvidia,pins = "uart2_cts_n_pj5"; |
390 | nvidia,function = "uartb"; | 390 | nvidia,function = "uartb"; |
391 | nvidia,pull = <0>; | 391 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
392 | nvidia,tristate = <1>; | 392 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
393 | nvidia,enable-input = <1>; | 393 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
394 | }; | 394 | }; |
395 | uart2_rts_n_pj6 { | 395 | uart2_rts_n_pj6 { |
396 | nvidia,pins = "uart2_rts_n_pj6"; | 396 | nvidia,pins = "uart2_rts_n_pj6"; |
397 | nvidia,function = "uartb"; | 397 | nvidia,function = "uartb"; |
398 | nvidia,pull = <0>; | 398 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
399 | nvidia,tristate = <0>; | 399 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
400 | nvidia,enable-input = <0>; | 400 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
401 | }; | 401 | }; |
402 | uart2_rxd_pc3 { | 402 | uart2_rxd_pc3 { |
403 | nvidia,pins = "uart2_rxd_pc3"; | 403 | nvidia,pins = "uart2_rxd_pc3"; |
404 | nvidia,function = "irda"; | 404 | nvidia,function = "irda"; |
405 | nvidia,pull = <0>; | 405 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
406 | nvidia,tristate = <1>; | 406 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
407 | nvidia,enable-input = <1>; | 407 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
408 | }; | 408 | }; |
409 | uart2_txd_pc2 { | 409 | uart2_txd_pc2 { |
410 | nvidia,pins = "uart2_txd_pc2"; | 410 | nvidia,pins = "uart2_txd_pc2"; |
411 | nvidia,function = "irda"; | 411 | nvidia,function = "irda"; |
412 | nvidia,pull = <0>; | 412 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
413 | nvidia,tristate = <0>; | 413 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
414 | nvidia,enable-input = <0>; | 414 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
415 | }; | 415 | }; |
416 | uart3_cts_n_pa1 { | 416 | uart3_cts_n_pa1 { |
417 | nvidia,pins = "uart3_cts_n_pa1", | 417 | nvidia,pins = "uart3_cts_n_pa1", |
418 | "uart3_rxd_pw7"; | 418 | "uart3_rxd_pw7"; |
419 | nvidia,function = "uartc"; | 419 | nvidia,function = "uartc"; |
420 | nvidia,pull = <0>; | 420 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
421 | nvidia,tristate = <1>; | 421 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
422 | nvidia,enable-input = <1>; | 422 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
423 | }; | 423 | }; |
424 | uart3_rts_n_pc0 { | 424 | uart3_rts_n_pc0 { |
425 | nvidia,pins = "uart3_rts_n_pc0", | 425 | nvidia,pins = "uart3_rts_n_pc0", |
426 | "uart3_txd_pw6"; | 426 | "uart3_txd_pw6"; |
427 | nvidia,function = "uartc"; | 427 | nvidia,function = "uartc"; |
428 | nvidia,pull = <0>; | 428 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
429 | nvidia,tristate = <0>; | 429 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
430 | nvidia,enable-input = <0>; | 430 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
431 | }; | 431 | }; |
432 | owr { | 432 | owr { |
433 | nvidia,pins = "owr"; | 433 | nvidia,pins = "owr"; |
434 | nvidia,function = "owr"; | 434 | nvidia,function = "owr"; |
435 | nvidia,pull = <0>; | 435 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
436 | nvidia,tristate = <0>; | 436 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
437 | nvidia,enable-input = <1>; | 437 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
438 | }; | 438 | }; |
439 | hdmi_cec_pee3 { | 439 | hdmi_cec_pee3 { |
440 | nvidia,pins = "hdmi_cec_pee3"; | 440 | nvidia,pins = "hdmi_cec_pee3"; |
441 | nvidia,function = "cec"; | 441 | nvidia,function = "cec"; |
442 | nvidia,pull = <0>; | 442 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
443 | nvidia,tristate = <0>; | 443 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
444 | nvidia,enable-input = <1>; | 444 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
445 | nvidia,lock = <0>; | 445 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
446 | nvidia,open-drain = <0>; | 446 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
447 | }; | 447 | }; |
448 | ddc_scl_pv4 { | 448 | ddc_scl_pv4 { |
449 | nvidia,pins = "ddc_scl_pv4", | 449 | nvidia,pins = "ddc_scl_pv4", |
450 | "ddc_sda_pv5"; | 450 | "ddc_sda_pv5"; |
451 | nvidia,function = "i2c4"; | 451 | nvidia,function = "i2c4"; |
452 | nvidia,pull = <0>; | 452 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
453 | nvidia,tristate = <0>; | 453 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
454 | nvidia,enable-input = <1>; | 454 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
455 | nvidia,lock = <0>; | 455 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
456 | nvidia,rcv-sel = <1>; | 456 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; |
457 | }; | 457 | }; |
458 | spdif_in_pk6 { | 458 | spdif_in_pk6 { |
459 | nvidia,pins = "spdif_in_pk6"; | 459 | nvidia,pins = "spdif_in_pk6"; |
460 | nvidia,function = "usb"; | 460 | nvidia,function = "usb"; |
461 | nvidia,pull = <2>; | 461 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
462 | nvidia,tristate = <0>; | 462 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
463 | nvidia,enable-input = <1>; | 463 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
464 | nvidia,lock = <0>; | 464 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
465 | }; | 465 | }; |
466 | usb_vbus_en0_pn4 { | 466 | usb_vbus_en0_pn4 { |
467 | nvidia,pins = "usb_vbus_en0_pn4"; | 467 | nvidia,pins = "usb_vbus_en0_pn4"; |
468 | nvidia,function = "usb"; | 468 | nvidia,function = "usb"; |
469 | nvidia,pull = <2>; | 469 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
470 | nvidia,tristate = <0>; | 470 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
471 | nvidia,enable-input = <1>; | 471 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
472 | nvidia,lock = <0>; | 472 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
473 | nvidia,open-drain = <1>; | 473 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
474 | }; | 474 | }; |
475 | gpio_x6_aud_px6 { | 475 | gpio_x6_aud_px6 { |
476 | nvidia,pins = "gpio_x6_aud_px6"; | 476 | nvidia,pins = "gpio_x6_aud_px6"; |
477 | nvidia,function = "spi6"; | 477 | nvidia,function = "spi6"; |
478 | nvidia,pull = <2>; | 478 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
479 | nvidia,tristate = <1>; | 479 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
480 | nvidia,enable-input = <1>; | 480 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
481 | }; | 481 | }; |
482 | gpio_x4_aud_px4 { | 482 | gpio_x4_aud_px4 { |
483 | nvidia,pins = "gpio_x4_aud_px4", | 483 | nvidia,pins = "gpio_x4_aud_px4", |
484 | "gpio_x7_aud_px7"; | 484 | "gpio_x7_aud_px7"; |
485 | nvidia,function = "rsvd1"; | 485 | nvidia,function = "rsvd1"; |
486 | nvidia,pull = <1>; | 486 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
487 | nvidia,tristate = <0>; | 487 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
488 | nvidia,enable-input = <0>; | 488 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
489 | }; | 489 | }; |
490 | gpio_x5_aud_px5 { | 490 | gpio_x5_aud_px5 { |
491 | nvidia,pins = "gpio_x5_aud_px5"; | 491 | nvidia,pins = "gpio_x5_aud_px5"; |
492 | nvidia,function = "rsvd1"; | 492 | nvidia,function = "rsvd1"; |
493 | nvidia,pull = <2>; | 493 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
494 | nvidia,tristate = <0>; | 494 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
495 | nvidia,enable-input = <1>; | 495 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
496 | }; | 496 | }; |
497 | gpio_w2_aud_pw2 { | 497 | gpio_w2_aud_pw2 { |
498 | nvidia,pins = "gpio_w2_aud_pw2"; | 498 | nvidia,pins = "gpio_w2_aud_pw2"; |
499 | nvidia,function = "rsvd2"; | 499 | nvidia,function = "rsvd2"; |
500 | nvidia,pull = <2>; | 500 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
501 | nvidia,tristate = <0>; | 501 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
502 | nvidia,enable-input = <1>; | 502 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
503 | }; | 503 | }; |
504 | gpio_w3_aud_pw3 { | 504 | gpio_w3_aud_pw3 { |
505 | nvidia,pins = "gpio_w3_aud_pw3"; | 505 | nvidia,pins = "gpio_w3_aud_pw3"; |
506 | nvidia,function = "spi6"; | 506 | nvidia,function = "spi6"; |
507 | nvidia,pull = <2>; | 507 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
508 | nvidia,tristate = <0>; | 508 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
509 | nvidia,enable-input = <1>; | 509 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
510 | }; | 510 | }; |
511 | gpio_x1_aud_px1 { | 511 | gpio_x1_aud_px1 { |
512 | nvidia,pins = "gpio_x1_aud_px1"; | 512 | nvidia,pins = "gpio_x1_aud_px1"; |
513 | nvidia,function = "rsvd4"; | 513 | nvidia,function = "rsvd4"; |
514 | nvidia,pull = <1>; | 514 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
515 | nvidia,tristate = <0>; | 515 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
516 | nvidia,enable-input = <1>; | 516 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
517 | }; | 517 | }; |
518 | gpio_x3_aud_px3 { | 518 | gpio_x3_aud_px3 { |
519 | nvidia,pins = "gpio_x3_aud_px3"; | 519 | nvidia,pins = "gpio_x3_aud_px3"; |
520 | nvidia,function = "rsvd4"; | 520 | nvidia,function = "rsvd4"; |
521 | nvidia,pull = <2>; | 521 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
522 | nvidia,tristate = <0>; | 522 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
523 | nvidia,enable-input = <1>; | 523 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
524 | }; | 524 | }; |
525 | dap3_fs_pp0 { | 525 | dap3_fs_pp0 { |
526 | nvidia,pins = "dap3_fs_pp0"; | 526 | nvidia,pins = "dap3_fs_pp0"; |
527 | nvidia,function = "i2s2"; | 527 | nvidia,function = "i2s2"; |
528 | nvidia,pull = <1>; | 528 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
529 | nvidia,tristate = <0>; | 529 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
530 | nvidia,enable-input = <0>; | 530 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
531 | }; | 531 | }; |
532 | dap3_dout_pp2 { | 532 | dap3_dout_pp2 { |
533 | nvidia,pins = "dap3_dout_pp2"; | 533 | nvidia,pins = "dap3_dout_pp2"; |
534 | nvidia,function = "i2s2"; | 534 | nvidia,function = "i2s2"; |
535 | nvidia,pull = <1>; | 535 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
536 | nvidia,tristate = <0>; | 536 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
537 | nvidia,enable-input = <0>; | 537 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
538 | }; | 538 | }; |
539 | pv1 { | 539 | pv1 { |
540 | nvidia,pins = "pv1"; | 540 | nvidia,pins = "pv1"; |
541 | nvidia,function = "rsvd1"; | 541 | nvidia,function = "rsvd1"; |
542 | nvidia,pull = <0>; | 542 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
543 | nvidia,tristate = <0>; | 543 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
544 | nvidia,enable-input = <1>; | 544 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
545 | }; | 545 | }; |
546 | pbb3 { | 546 | pbb3 { |
547 | nvidia,pins = "pbb3", | 547 | nvidia,pins = "pbb3", |
@@ -549,25 +549,25 @@ | |||
549 | "pbb6", | 549 | "pbb6", |
550 | "pbb7"; | 550 | "pbb7"; |
551 | nvidia,function = "rsvd4"; | 551 | nvidia,function = "rsvd4"; |
552 | nvidia,pull = <1>; | 552 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
553 | nvidia,tristate = <0>; | 553 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
554 | nvidia,enable-input = <0>; | 554 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
555 | }; | 555 | }; |
556 | pcc1 { | 556 | pcc1 { |
557 | nvidia,pins = "pcc1", | 557 | nvidia,pins = "pcc1", |
558 | "pcc2"; | 558 | "pcc2"; |
559 | nvidia,function = "rsvd4"; | 559 | nvidia,function = "rsvd4"; |
560 | nvidia,pull = <1>; | 560 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
561 | nvidia,tristate = <0>; | 561 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
562 | nvidia,enable-input = <1>; | 562 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
563 | }; | 563 | }; |
564 | gmi_ad0_pg0 { | 564 | gmi_ad0_pg0 { |
565 | nvidia,pins = "gmi_ad0_pg0", | 565 | nvidia,pins = "gmi_ad0_pg0", |
566 | "gmi_ad1_pg1"; | 566 | "gmi_ad1_pg1"; |
567 | nvidia,function = "gmi"; | 567 | nvidia,function = "gmi"; |
568 | nvidia,pull = <0>; | 568 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
569 | nvidia,tristate = <0>; | 569 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
570 | nvidia,enable-input = <0>; | 570 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
571 | }; | 571 | }; |
572 | gmi_ad10_ph2 { | 572 | gmi_ad10_ph2 { |
573 | nvidia,pins = "gmi_ad10_ph2", | 573 | nvidia,pins = "gmi_ad10_ph2", |
@@ -576,17 +576,17 @@ | |||
576 | "gmi_ad8_ph0", | 576 | "gmi_ad8_ph0", |
577 | "gmi_clk_pk1"; | 577 | "gmi_clk_pk1"; |
578 | nvidia,function = "gmi"; | 578 | nvidia,function = "gmi"; |
579 | nvidia,pull = <1>; | 579 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
580 | nvidia,tristate = <0>; | 580 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
581 | nvidia,enable-input = <0>; | 581 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
582 | }; | 582 | }; |
583 | gmi_ad2_pg2 { | 583 | gmi_ad2_pg2 { |
584 | nvidia,pins = "gmi_ad2_pg2", | 584 | nvidia,pins = "gmi_ad2_pg2", |
585 | "gmi_ad3_pg3"; | 585 | "gmi_ad3_pg3"; |
586 | nvidia,function = "gmi"; | 586 | nvidia,function = "gmi"; |
587 | nvidia,pull = <0>; | 587 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
588 | nvidia,tristate = <0>; | 588 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
589 | nvidia,enable-input = <1>; | 589 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
590 | }; | 590 | }; |
591 | gmi_adv_n_pk0 { | 591 | gmi_adv_n_pk0 { |
592 | nvidia,pins = "gmi_adv_n_pk0", | 592 | nvidia,pins = "gmi_adv_n_pk0", |
@@ -598,39 +598,39 @@ | |||
598 | "gmi_iordy_pi5", | 598 | "gmi_iordy_pi5", |
599 | "gmi_wp_n_pc7"; | 599 | "gmi_wp_n_pc7"; |
600 | nvidia,function = "gmi"; | 600 | nvidia,function = "gmi"; |
601 | nvidia,pull = <2>; | 601 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
602 | nvidia,tristate = <0>; | 602 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
603 | nvidia,enable-input = <1>; | 603 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
604 | }; | 604 | }; |
605 | gmi_cs3_n_pk4 { | 605 | gmi_cs3_n_pk4 { |
606 | nvidia,pins = "gmi_cs3_n_pk4"; | 606 | nvidia,pins = "gmi_cs3_n_pk4"; |
607 | nvidia,function = "gmi"; | 607 | nvidia,function = "gmi"; |
608 | nvidia,pull = <2>; | 608 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
609 | nvidia,tristate = <0>; | 609 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
610 | nvidia,enable-input = <0>; | 610 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
611 | }; | 611 | }; |
612 | clk2_req_pcc5 { | 612 | clk2_req_pcc5 { |
613 | nvidia,pins = "clk2_req_pcc5"; | 613 | nvidia,pins = "clk2_req_pcc5"; |
614 | nvidia,function = "rsvd4"; | 614 | nvidia,function = "rsvd4"; |
615 | nvidia,pull = <0>; | 615 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
616 | nvidia,tristate = <0>; | 616 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
617 | nvidia,enable-input = <0>; | 617 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
618 | }; | 618 | }; |
619 | kb_col3_pq3 { | 619 | kb_col3_pq3 { |
620 | nvidia,pins = "kb_col3_pq3", | 620 | nvidia,pins = "kb_col3_pq3", |
621 | "kb_col6_pq6", | 621 | "kb_col6_pq6", |
622 | "kb_col7_pq7"; | 622 | "kb_col7_pq7"; |
623 | nvidia,function = "kbc"; | 623 | nvidia,function = "kbc"; |
624 | nvidia,pull = <2>; | 624 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
625 | nvidia,tristate = <0>; | 625 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
626 | nvidia,enable-input = <0>; | 626 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
627 | }; | 627 | }; |
628 | kb_col5_pq5 { | 628 | kb_col5_pq5 { |
629 | nvidia,pins = "kb_col5_pq5"; | 629 | nvidia,pins = "kb_col5_pq5"; |
630 | nvidia,function = "kbc"; | 630 | nvidia,function = "kbc"; |
631 | nvidia,pull = <2>; | 631 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
632 | nvidia,tristate = <0>; | 632 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
633 | nvidia,enable-input = <1>; | 633 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
634 | }; | 634 | }; |
635 | kb_row3_pr3 { | 635 | kb_row3_pr3 { |
636 | nvidia,pins = "kb_row3_pr3", | 636 | nvidia,pins = "kb_row3_pr3", |
@@ -638,77 +638,77 @@ | |||
638 | "kb_row6_pr6", | 638 | "kb_row6_pr6", |
639 | "kb_row8_ps0"; | 639 | "kb_row8_ps0"; |
640 | nvidia,function = "kbc"; | 640 | nvidia,function = "kbc"; |
641 | nvidia,pull = <1>; | 641 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
642 | nvidia,tristate = <0>; | 642 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
643 | nvidia,enable-input = <1>; | 643 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
644 | }; | 644 | }; |
645 | clk3_req_pee1 { | 645 | clk3_req_pee1 { |
646 | nvidia,pins = "clk3_req_pee1"; | 646 | nvidia,pins = "clk3_req_pee1"; |
647 | nvidia,function = "rsvd4"; | 647 | nvidia,function = "rsvd4"; |
648 | nvidia,pull = <0>; | 648 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
649 | nvidia,tristate = <0>; | 649 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
650 | nvidia,enable-input = <0>; | 650 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
651 | }; | 651 | }; |
652 | pu4 { | 652 | pu4 { |
653 | nvidia,pins = "pu4"; | 653 | nvidia,pins = "pu4"; |
654 | nvidia,function = "displayb"; | 654 | nvidia,function = "displayb"; |
655 | nvidia,pull = <0>; | 655 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
656 | nvidia,tristate = <0>; | 656 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
657 | nvidia,enable-input = <0>; | 657 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
658 | }; | 658 | }; |
659 | pu5 { | 659 | pu5 { |
660 | nvidia,pins = "pu5", | 660 | nvidia,pins = "pu5", |
661 | "pu6"; | 661 | "pu6"; |
662 | nvidia,function = "displayb"; | 662 | nvidia,function = "displayb"; |
663 | nvidia,pull = <0>; | 663 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
664 | nvidia,tristate = <0>; | 664 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
665 | nvidia,enable-input = <1>; | 665 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
666 | }; | 666 | }; |
667 | hdmi_int_pn7 { | 667 | hdmi_int_pn7 { |
668 | nvidia,pins = "hdmi_int_pn7"; | 668 | nvidia,pins = "hdmi_int_pn7"; |
669 | nvidia,function = "rsvd1"; | 669 | nvidia,function = "rsvd1"; |
670 | nvidia,pull = <1>; | 670 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
671 | nvidia,tristate = <0>; | 671 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
672 | nvidia,enable-input = <1>; | 672 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
673 | }; | 673 | }; |
674 | clk1_req_pee2 { | 674 | clk1_req_pee2 { |
675 | nvidia,pins = "clk1_req_pee2", | 675 | nvidia,pins = "clk1_req_pee2", |
676 | "usb_vbus_en1_pn5"; | 676 | "usb_vbus_en1_pn5"; |
677 | nvidia,function = "rsvd4"; | 677 | nvidia,function = "rsvd4"; |
678 | nvidia,pull = <1>; | 678 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
679 | nvidia,tristate = <1>; | 679 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
680 | nvidia,enable-input = <0>; | 680 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
681 | }; | 681 | }; |
682 | 682 | ||
683 | drive_sdio1 { | 683 | drive_sdio1 { |
684 | nvidia,pins = "drive_sdio1"; | 684 | nvidia,pins = "drive_sdio1"; |
685 | nvidia,high-speed-mode = <1>; | 685 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
686 | nvidia,schmitt = <0>; | 686 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
687 | nvidia,low-power-mode = <3>; | 687 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
688 | nvidia,pull-down-strength = <36>; | 688 | nvidia,pull-down-strength = <36>; |
689 | nvidia,pull-up-strength = <20>; | 689 | nvidia,pull-up-strength = <20>; |
690 | nvidia,slew-rate-rising = <2>; | 690 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; |
691 | nvidia,slew-rate-falling = <2>; | 691 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; |
692 | }; | 692 | }; |
693 | drive_sdio3 { | 693 | drive_sdio3 { |
694 | nvidia,pins = "drive_sdio3"; | 694 | nvidia,pins = "drive_sdio3"; |
695 | nvidia,high-speed-mode = <1>; | 695 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
696 | nvidia,schmitt = <0>; | 696 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
697 | nvidia,low-power-mode = <3>; | 697 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
698 | nvidia,pull-down-strength = <22>; | 698 | nvidia,pull-down-strength = <22>; |
699 | nvidia,pull-up-strength = <36>; | 699 | nvidia,pull-up-strength = <36>; |
700 | nvidia,slew-rate-rising = <0>; | 700 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
701 | nvidia,slew-rate-falling = <0>; | 701 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
702 | }; | 702 | }; |
703 | drive_gma { | 703 | drive_gma { |
704 | nvidia,pins = "drive_gma"; | 704 | nvidia,pins = "drive_gma"; |
705 | nvidia,high-speed-mode = <1>; | 705 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
706 | nvidia,schmitt = <0>; | 706 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
707 | nvidia,low-power-mode = <3>; | 707 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
708 | nvidia,pull-down-strength = <2>; | 708 | nvidia,pull-down-strength = <2>; |
709 | nvidia,pull-up-strength = <1>; | 709 | nvidia,pull-up-strength = <1>; |
710 | nvidia,slew-rate-rising = <0>; | 710 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
711 | nvidia,slew-rate-falling = <0>; | 711 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
712 | nvidia,drive-type = <1>; | 712 | nvidia,drive-type = <1>; |
713 | }; | 713 | }; |
714 | }; | 714 | }; |
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 8fdf8d5cff09..ae855ec60bbd 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi | |||
@@ -1,5 +1,6 @@ | |||
1 | #include <dt-bindings/clock/tegra114-car.h> | 1 | #include <dt-bindings/clock/tegra114-car.h> |
2 | #include <dt-bindings/gpio/tegra-gpio.h> | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> | ||
3 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
4 | 5 | ||
5 | #include "skeleton.dtsi" | 6 | #include "skeleton.dtsi" |