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authorLuis R. Rodriguez <lrodriguez@atheros.com>2009-01-22 18:16:48 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-01-29 16:01:20 -0500
commit5f8e077c0adc0dc7cfad64cdc05276e1961a1394 (patch)
treedc918d9eacab12998d8e67f259de32dbbb409e81
parent24ed1da1337b92e3b0a89f2c2b7cd33b9a8fcb62 (diff)
ath9k: simplify regulatory code
Now that cfg80211 has its own regulatory infrastructure we can condense ath9k's regulatory code considerably. We only keep data we need to provide our own regulatory_hint(), reg_notifier() and information necessary for calibration. Atheros hardware supports 12 world regulatory domains, since these are custom we apply them through the the new wiphy_apply_custom_regulatory(). Although we have 12 we can consolidate these into 5 structures based on frequency and apply a different set of flags that differentiate them on a case by case basis through the reg_notifier(). If CRDA is not found our own custom world regulatory domain is applied, this is identical to cfg80211's except we enable passive scan on most frequencies. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h44
-rw-r--r--drivers/net/wireless/ath9k/calib.c41
-rw-r--r--drivers/net/wireless/ath9k/core.h1
-rw-r--r--drivers/net/wireless/ath9k/hw.c63
-rw-r--r--drivers/net/wireless/ath9k/main.c263
-rw-r--r--drivers/net/wireless/ath9k/regd.c1188
-rw-r--r--drivers/net/wireless/ath9k/regd.h181
-rw-r--r--drivers/net/wireless/ath9k/regd_common.h2058
8 files changed, 809 insertions, 3030 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index 0b305b832a8c..f158cba01407 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -457,22 +457,12 @@ struct ath9k_channel {
457 struct ieee80211_channel *chan; 457 struct ieee80211_channel *chan;
458 u16 channel; 458 u16 channel;
459 u32 channelFlags; 459 u32 channelFlags;
460 u8 privFlags;
461 int8_t maxRegTxPower;
462 int8_t maxTxPower;
463 int8_t minTxPower;
464 u32 chanmode; 460 u32 chanmode;
465 int32_t CalValid; 461 int32_t CalValid;
466 bool oneTimeCalsDone; 462 bool oneTimeCalsDone;
467 int8_t iCoff; 463 int8_t iCoff;
468 int8_t qCoff; 464 int8_t qCoff;
469 int16_t rawNoiseFloor; 465 int16_t rawNoiseFloor;
470 int8_t antennaMax;
471 u32 regDmnFlags;
472 u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
473#ifdef ATH_NF_PER_CHAN
474 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
475#endif
476}; 466};
477 467
478#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ 468#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
@@ -500,7 +490,6 @@ struct ath9k_channel {
500 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 490 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
501#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 491#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
502 492
503#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
504#define IS_CHAN_A_5MHZ_SPACED(_c) \ 493#define IS_CHAN_A_5MHZ_SPACED(_c) \
505 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 494 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
506 (((_c)->channel % 20) != 0) && \ 495 (((_c)->channel % 20) != 0) && \
@@ -790,15 +779,13 @@ struct ath_hal {
790 u16 ah_currentRD; 779 u16 ah_currentRD;
791 u16 ah_currentRDExt; 780 u16 ah_currentRDExt;
792 u16 ah_currentRDInUse; 781 u16 ah_currentRDInUse;
793 u16 ah_currentRD5G; 782 char alpha2[2];
794 u16 ah_currentRD2G; 783 struct reg_dmn_pair_mapping *regpair;
795 char ah_iso[4];
796 enum ath9k_power_mode ah_power_mode; 784 enum ath9k_power_mode ah_power_mode;
797 enum ath9k_power_mode ah_restore_mode; 785 enum ath9k_power_mode ah_restore_mode;
798 786
799 struct ath9k_channel ah_channels[150]; 787 struct ath9k_channel ah_channels[38];
800 struct ath9k_channel *ah_curchan; 788 struct ath9k_channel *ah_curchan;
801 u32 ah_nchan;
802 789
803 bool ah_isPciExpress; 790 bool ah_isPciExpress;
804 u16 ah_txTrigLevel; 791 u16 ah_txTrigLevel;
@@ -807,10 +794,7 @@ struct ath_hal {
807 u32 ah_rfkill_polarity; 794 u32 ah_rfkill_polarity;
808 u32 ah_btactive_gpio; 795 u32 ah_btactive_gpio;
809 u32 ah_wlanactive_gpio; 796 u32 ah_wlanactive_gpio;
810
811#ifndef ATH_NF_PER_CHAN
812 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 797 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
813#endif
814 798
815 bool sw_mgmt_crypto; 799 bool sw_mgmt_crypto;
816}; 800};
@@ -825,8 +809,6 @@ struct ath_rate_table;
825 809
826/* Helpers */ 810/* Helpers */
827 811
828enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
829 const struct ath9k_channel *chan);
830bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); 812bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val);
831u32 ath9k_hw_reverse_bits(u32 val, u32 n); 813u32 ath9k_hw_reverse_bits(u32 val, u32 n);
832bool ath9k_get_channel_edges(struct ath_hal *ah, 814bool ath9k_get_channel_edges(struct ath_hal *ah,
@@ -836,7 +818,6 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah,
836 struct ath_rate_table *rates, 818 struct ath_rate_table *rates,
837 u32 frameLen, u16 rateix, 819 u32 frameLen, u16 rateix,
838 bool shortPreamble); 820 bool shortPreamble);
839u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
840void ath9k_hw_get_channel_centers(struct ath_hal *ah, 821void ath9k_hw_get_channel_centers(struct ath_hal *ah,
841 struct ath9k_channel *chan, 822 struct ath9k_channel *chan,
842 struct chan_centers *centers); 823 struct chan_centers *centers);
@@ -924,17 +905,18 @@ bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
924void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); 905void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
925 906
926/* Regulatory */ 907/* Regulatory */
908u16 ath9k_regd_get_rd(struct ath_hal *ah);
909bool ath9k_is_world_regd(struct ath_hal *ah);
910const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah);
911const struct ieee80211_regdomain *ath9k_default_world_regdomain(void);
912
913void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby);
914void ath9k_reg_apply_radar_flags(struct wiphy *wiphy);
927 915
928bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah); 916int ath9k_regd_init(struct ath_hal *ah);
929struct ath9k_channel* ath9k_regd_check_channel(struct ath_hal *ah, 917bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah);
930 const struct ath9k_channel *c);
931u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); 918u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
932u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah, 919int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
933 struct ath9k_channel *chan);
934bool ath9k_regd_init_channels(struct ath_hal *ah,
935 u32 maxchans, u32 *nchans, u8 *regclassids,
936 u32 maxregids, u32 *nregids, u16 cc,
937 bool enableOutdoor, bool enableExtendedChannels);
938 920
939/* ANI */ 921/* ANI */
940 922
diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
index 8e073d6513d5..d16f9fe48a9f 100644
--- a/drivers/net/wireless/ath9k/calib.c
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -625,11 +625,7 @@ void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
625 else 625 else
626 chainmask = 0x3F; 626 chainmask = 0x3F;
627 627
628#ifdef ATH_NF_PER_CHAN
629 h = chan->nfCalHist;
630#else
631 h = ah->nfCalHist; 628 h = ah->nfCalHist;
632#endif
633 629
634 for (i = 0; i < NUM_NF_READINGS; i++) { 630 for (i = 0; i < NUM_NF_READINGS; i++) {
635 if (chainmask & (1 << i)) { 631 if (chainmask & (1 << i)) {
@@ -697,11 +693,7 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah,
697 } 693 }
698 } 694 }
699 695
700#ifdef ATH_NF_PER_CHAN
701 h = chan->nfCalHist;
702#else
703 h = ah->nfCalHist; 696 h = ah->nfCalHist;
704#endif
705 697
706 ath9k_hw_update_nfcal_hist_buffer(h, nfarray); 698 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
707 chan->rawNoiseFloor = h[0].privNF; 699 chan->rawNoiseFloor = h[0].privNF;
@@ -728,20 +720,12 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
728 720
729s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) 721s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
730{ 722{
731 struct ath9k_channel *ichan;
732 s16 nf; 723 s16 nf;
733 724
734 ichan = ath9k_regd_check_channel(ah, chan); 725 if (chan->rawNoiseFloor == 0)
735 if (ichan == NULL) {
736 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
737 "invalid channel %u/0x%x; no mapping\n",
738 chan->channel, chan->channelFlags);
739 return ATH_DEFAULT_NOISE_FLOOR;
740 }
741 if (ichan->rawNoiseFloor == 0)
742 nf = -96; 726 nf = -96;
743 else 727 else
744 nf = ichan->rawNoiseFloor; 728 nf = chan->rawNoiseFloor;
745 729
746 if (!ath9k_hw_nf_in_range(ah, nf)) 730 if (!ath9k_hw_nf_in_range(ah, nf))
747 nf = ATH_DEFAULT_NOISE_FLOOR; 731 nf = ATH_DEFAULT_NOISE_FLOOR;
@@ -755,21 +739,13 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
755{ 739{
756 struct ath_hal_5416 *ahp = AH5416(ah); 740 struct ath_hal_5416 *ahp = AH5416(ah);
757 struct hal_cal_list *currCal = ahp->ah_cal_list_curr; 741 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
758 struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
759 742
760 *isCalDone = true; 743 *isCalDone = true;
761 744
762 if (ichan == NULL) {
763 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
764 "invalid channel %u/0x%x; no mapping\n",
765 chan->channel, chan->channelFlags);
766 return false;
767 }
768
769 if (currCal && 745 if (currCal &&
770 (currCal->calState == CAL_RUNNING || 746 (currCal->calState == CAL_RUNNING ||
771 currCal->calState == CAL_WAITING)) { 747 currCal->calState == CAL_WAITING)) {
772 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal, 748 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
773 isCalDone); 749 isCalDone);
774 if (*isCalDone) { 750 if (*isCalDone) {
775 ahp->ah_cal_list_curr = currCal = currCal->calNext; 751 ahp->ah_cal_list_curr = currCal = currCal->calNext;
@@ -782,14 +758,12 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
782 } 758 }
783 759
784 if (longcal) { 760 if (longcal) {
785 ath9k_hw_getnf(ah, ichan); 761 ath9k_hw_getnf(ah, chan);
786 ath9k_hw_loadnf(ah, ah->ah_curchan); 762 ath9k_hw_loadnf(ah, ah->ah_curchan);
787 ath9k_hw_start_nfcal(ah); 763 ath9k_hw_start_nfcal(ah);
788 764
789 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) { 765 if (chan->channelFlags & CHANNEL_CW_INT)
790 chan->channelFlags |= CHANNEL_CW_INT; 766 chan->channelFlags &= ~CHANNEL_CW_INT;
791 ichan->channelFlags &= ~CHANNEL_CW_INT;
792 }
793 } 767 }
794 768
795 return true; 769 return true;
@@ -894,7 +868,6 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
894 struct ath9k_channel *chan) 868 struct ath9k_channel *chan)
895{ 869{
896 struct ath_hal_5416 *ahp = AH5416(ah); 870 struct ath_hal_5416 *ahp = AH5416(ah);
897 struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
898 871
899 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 872 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
900 REG_READ(ah, AR_PHY_AGC_CONTROL) | 873 REG_READ(ah, AR_PHY_AGC_CONTROL) |
@@ -942,7 +915,7 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
942 ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr); 915 ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr);
943 } 916 }
944 917
945 ichan->CalValid = 0; 918 chan->CalValid = 0;
946 919
947 return true; 920 return true;
948} 921}
diff --git a/drivers/net/wireless/ath9k/core.h b/drivers/net/wireless/ath9k/core.h
index 0f50767712a6..29251f8dabb0 100644
--- a/drivers/net/wireless/ath9k/core.h
+++ b/drivers/net/wireless/ath9k/core.h
@@ -724,7 +724,6 @@ struct ath_softc {
724 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; 724 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
725 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; 725 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
726 struct ath_rate_table *cur_rate_table; 726 struct ath_rate_table *cur_rate_table;
727 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
728 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 727 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
729 struct ath_led radio_led; 728 struct ath_led radio_led;
730 struct ath_led assoc_led; 729 struct ath_led assoc_led;
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 65e0d80f3b4d..f2922bab7761 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -187,46 +187,6 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah,
187 return txTime; 187 return txTime;
188} 188}
189 189
190u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
191{
192 if (flags & CHANNEL_2GHZ) {
193 if (freq == 2484)
194 return 14;
195 if (freq < 2484)
196 return (freq - 2407) / 5;
197 else
198 return 15 + ((freq - 2512) / 20);
199 } else if (flags & CHANNEL_5GHZ) {
200 if (ath9k_regd_is_public_safety_sku(ah) &&
201 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
202 return ((freq * 10) +
203 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
204 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
205 return (freq - 4000) / 5;
206 } else {
207 return (freq - 5000) / 5;
208 }
209 } else {
210 if (freq == 2484)
211 return 14;
212 if (freq < 2484)
213 return (freq - 2407) / 5;
214 if (freq < 5000) {
215 if (ath9k_regd_is_public_safety_sku(ah)
216 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
217 return ((freq * 10) +
218 (((freq % 5) ==
219 2) ? 5 : 0) - 49400) / 5;
220 } else if (freq > 4900) {
221 return (freq - 4000) / 5;
222 } else {
223 return 15 + ((freq - 2512) / 20);
224 }
225 }
226 return (freq - 5000) / 5;
227 }
228}
229
230void ath9k_hw_get_channel_centers(struct ath_hal *ah, 190void ath9k_hw_get_channel_centers(struct ath_hal *ah,
231 struct ath9k_channel *chan, 191 struct ath9k_channel *chan,
232 struct chan_centers *centers) 192 struct chan_centers *centers)
@@ -1270,6 +1230,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1270{ 1230{
1271 int i, regWrites = 0; 1231 int i, regWrites = 0;
1272 struct ath_hal_5416 *ahp = AH5416(ah); 1232 struct ath_hal_5416 *ahp = AH5416(ah);
1233 struct ieee80211_channel *channel = chan->chan;
1273 u32 modesIndex, freqIndex; 1234 u32 modesIndex, freqIndex;
1274 int status; 1235 int status;
1275 1236
@@ -1374,9 +1335,8 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1374 1335
1375 status = ath9k_hw_set_txpower(ah, chan, 1336 status = ath9k_hw_set_txpower(ah, chan,
1376 ath9k_regd_get_ctl(ah, chan), 1337 ath9k_regd_get_ctl(ah, chan),
1377 ath9k_regd_get_antenna_allowed(ah, 1338 channel->max_antenna_gain * 2,
1378 chan), 1339 channel->max_power * 2,
1379 chan->maxRegTxPower * 2,
1380 min((u32) MAX_RATE_POWER, 1340 min((u32) MAX_RATE_POWER,
1381 (u32) ah->ah_powerLimit)); 1341 (u32) ah->ah_powerLimit));
1382 if (status != 0) { 1342 if (status != 0) {
@@ -1669,6 +1629,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1669 struct ath9k_channel *chan, 1629 struct ath9k_channel *chan,
1670 enum ath9k_ht_macmode macmode) 1630 enum ath9k_ht_macmode macmode)
1671{ 1631{
1632 struct ieee80211_channel *channel = chan->chan;
1672 u32 synthDelay, qnum; 1633 u32 synthDelay, qnum;
1673 1634
1674 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1635 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
@@ -1705,8 +1666,8 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1705 1666
1706 if (ath9k_hw_set_txpower(ah, chan, 1667 if (ath9k_hw_set_txpower(ah, chan,
1707 ath9k_regd_get_ctl(ah, chan), 1668 ath9k_regd_get_ctl(ah, chan),
1708 ath9k_regd_get_antenna_allowed(ah, chan), 1669 channel->max_antenna_gain * 2,
1709 chan->maxRegTxPower * 2, 1670 channel->max_power * 2,
1710 min((u32) MAX_RATE_POWER, 1671 min((u32) MAX_RATE_POWER,
1711 (u32) ah->ah_powerLimit)) != 0) { 1672 (u32) ah->ah_powerLimit)) != 0) {
1712 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1673 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
@@ -2209,13 +2170,6 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2209 ahp->ah_rxchainmask &= 0x3; 2170 ahp->ah_rxchainmask &= 0x3;
2210 } 2171 }
2211 2172
2212 if (ath9k_regd_check_channel(ah, chan) == NULL) {
2213 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2214 "invalid channel %u/0x%x; no mapping\n",
2215 chan->channel, chan->channelFlags);
2216 return -EINVAL;
2217 }
2218
2219 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2173 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2220 return -EIO; 2174 return -EIO;
2221 2175
@@ -3718,13 +3672,14 @@ bool ath9k_hw_disable(struct ath_hal *ah)
3718bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) 3672bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3719{ 3673{
3720 struct ath9k_channel *chan = ah->ah_curchan; 3674 struct ath9k_channel *chan = ah->ah_curchan;
3675 struct ieee80211_channel *channel = chan->chan;
3721 3676
3722 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER); 3677 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3723 3678
3724 if (ath9k_hw_set_txpower(ah, chan, 3679 if (ath9k_hw_set_txpower(ah, chan,
3725 ath9k_regd_get_ctl(ah, chan), 3680 ath9k_regd_get_ctl(ah, chan),
3726 ath9k_regd_get_antenna_allowed(ah, chan), 3681 channel->max_antenna_gain * 2,
3727 chan->maxRegTxPower * 2, 3682 channel->max_power * 2,
3728 min((u32) MAX_RATE_POWER, 3683 min((u32) MAX_RATE_POWER,
3729 (u32) ah->ah_powerLimit)) != 0) 3684 (u32) ah->ah_powerLimit)) != 0)
3730 return false; 3685 return false;
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index b494a0d7e8b5..561a2c3adbbe 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -28,6 +28,77 @@ MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL"); 29MODULE_LICENSE("Dual BSD/GPL");
30 30
31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
36 .max_power = 30, \
37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
43 .max_power = 30, \
44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101
31static void ath_cache_conf_rate(struct ath_softc *sc, 102static void ath_cache_conf_rate(struct ath_softc *sc,
32 struct ieee80211_conf *conf) 103 struct ieee80211_conf *conf)
33{ 104{
@@ -152,75 +223,6 @@ static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
152 } 223 }
153} 224}
154 225
155static int ath_setup_channels(struct ath_softc *sc)
156{
157 struct ath_hal *ah = sc->sc_ah;
158 int nchan, i, a = 0, b = 0;
159 u8 regclassids[ATH_REGCLASSIDS_MAX];
160 u32 nregclass = 0;
161 struct ieee80211_supported_band *band_2ghz;
162 struct ieee80211_supported_band *band_5ghz;
163 struct ieee80211_channel *chan_2ghz;
164 struct ieee80211_channel *chan_5ghz;
165 struct ath9k_channel *c;
166
167 /* Fill in ah->ah_channels */
168 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
169 regclassids, ATH_REGCLASSIDS_MAX,
170 &nregclass, CTRY_DEFAULT, false, 1)) {
171 u32 rd = ah->ah_currentRD;
172 DPRINTF(sc, ATH_DBG_FATAL,
173 "Unable to collect channel list; "
174 "regdomain likely %u country code %u\n",
175 rd, CTRY_DEFAULT);
176 return -EINVAL;
177 }
178
179 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
180 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
181 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
182 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
183
184 for (i = 0; i < nchan; i++) {
185 c = &ah->ah_channels[i];
186 if (IS_CHAN_2GHZ(c)) {
187 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
188 chan_2ghz[a].center_freq = c->channel;
189 chan_2ghz[a].max_power = c->maxTxPower;
190 c->chan = &chan_2ghz[a];
191
192 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
193 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
194 if (c->channelFlags & CHANNEL_PASSIVE)
195 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
196
197 band_2ghz->n_channels = ++a;
198
199 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
200 "channelFlags: 0x%x\n",
201 c->channel, c->channelFlags);
202 } else if (IS_CHAN_5GHZ(c)) {
203 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
204 chan_5ghz[b].center_freq = c->channel;
205 chan_5ghz[b].max_power = c->maxTxPower;
206 c->chan = &chan_5ghz[a];
207
208 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
209 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
210 if (c->channelFlags & CHANNEL_PASSIVE)
211 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
212
213 band_5ghz->n_channels = ++b;
214
215 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
216 "channelFlags: 0x%x\n",
217 c->channel, c->channelFlags);
218 }
219 }
220
221 return 0;
222}
223
224/* 226/*
225 * Set/change channels. If the channel is really being changed, it's done 227 * Set/change channels. If the channel is really being changed, it's done
226 * by reseting the chip. To accomplish this we must first cleanup any pending 228 * by reseting the chip. To accomplish this we must first cleanup any pending
@@ -582,19 +584,6 @@ irqreturn_t ath_isr(int irq, void *dev)
582 return IRQ_HANDLED; 584 return IRQ_HANDLED;
583} 585}
584 586
585static int ath_get_channel(struct ath_softc *sc,
586 struct ieee80211_channel *chan)
587{
588 int i;
589
590 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
591 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
592 return i;
593 }
594
595 return -1;
596}
597
598static u32 ath_get_extchanmode(struct ath_softc *sc, 587static u32 ath_get_extchanmode(struct ath_softc *sc,
599 struct ieee80211_channel *chan, 588 struct ieee80211_channel *chan,
600 enum nl80211_channel_type channel_type) 589 enum nl80211_channel_type channel_type)
@@ -1349,16 +1338,12 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1349 for (i = 0; i < sc->sc_keymax; i++) 1338 for (i = 0; i < sc->sc_keymax; i++)
1350 ath9k_hw_keyreset(ah, (u16) i); 1339 ath9k_hw_keyreset(ah, (u16) i);
1351 1340
1352 /* Collect the channel list using the default country code */ 1341 if (ath9k_regd_init(sc->sc_ah))
1353
1354 error = ath_setup_channels(sc);
1355 if (error)
1356 goto bad; 1342 goto bad;
1357 1343
1358 /* default to MONITOR mode */ 1344 /* default to MONITOR mode */
1359 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR; 1345 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1360 1346
1361
1362 /* Setup rate tables */ 1347 /* Setup rate tables */
1363 1348
1364 ath_rate_attach(sc); 1349 ath_rate_attach(sc);
@@ -1490,18 +1475,20 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1490 1475
1491 /* setup channels and rates */ 1476 /* setup channels and rates */
1492 1477
1493 sc->sbands[IEEE80211_BAND_2GHZ].channels = 1478 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1494 sc->channels[IEEE80211_BAND_2GHZ];
1495 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = 1479 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1496 sc->rates[IEEE80211_BAND_2GHZ]; 1480 sc->rates[IEEE80211_BAND_2GHZ];
1497 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 1481 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1482 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1483 ARRAY_SIZE(ath9k_2ghz_chantable);
1498 1484
1499 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) { 1485 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1500 sc->sbands[IEEE80211_BAND_5GHZ].channels = 1486 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1501 sc->channels[IEEE80211_BAND_5GHZ];
1502 sc->sbands[IEEE80211_BAND_5GHZ].bitrates = 1487 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1503 sc->rates[IEEE80211_BAND_5GHZ]; 1488 sc->rates[IEEE80211_BAND_5GHZ];
1504 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; 1489 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1490 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1491 ARRAY_SIZE(ath9k_5ghz_chantable);
1505 } 1492 }
1506 1493
1507 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX) 1494 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
@@ -1550,6 +1537,9 @@ int ath_attach(u16 devid, struct ath_softc *sc)
1550 BIT(NL80211_IFTYPE_STATION) | 1537 BIT(NL80211_IFTYPE_STATION) |
1551 BIT(NL80211_IFTYPE_ADHOC); 1538 BIT(NL80211_IFTYPE_ADHOC);
1552 1539
1540 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1541 hw->wiphy->strict_regulatory = true;
1542
1553 hw->queues = 4; 1543 hw->queues = 4;
1554 hw->max_rates = 4; 1544 hw->max_rates = 4;
1555 hw->max_rate_tries = ATH_11N_TXMAXTRY; 1545 hw->max_rate_tries = ATH_11N_TXMAXTRY;
@@ -1588,11 +1578,36 @@ int ath_attach(u16 devid, struct ath_softc *sc)
1588 goto detach; 1578 goto detach;
1589#endif 1579#endif
1590 1580
1581 if (ath9k_is_world_regd(sc->sc_ah)) {
1582 /* Anything applied here (prior to wiphy registratoin) gets
1583 * saved on the wiphy orig_* parameters */
1584 const struct ieee80211_regdomain *regd =
1585 ath9k_world_regdomain(sc->sc_ah);
1586 hw->wiphy->custom_regulatory = true;
1587 hw->wiphy->strict_regulatory = false;
1588 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1589 ath9k_reg_apply_radar_flags(hw->wiphy);
1590 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1591 } else {
1592 /* This gets applied in the case of the absense of CRDA,
1593 * its our own custom world regulatory domain, similar to
1594 * cfg80211's but we enable passive scanning */
1595 const struct ieee80211_regdomain *regd =
1596 ath9k_default_world_regdomain();
1597 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1598 ath9k_reg_apply_radar_flags(hw->wiphy);
1599 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1600 }
1601
1591 error = ieee80211_register_hw(hw); 1602 error = ieee80211_register_hw(hw);
1592 1603
1604 if (!ath9k_is_world_regd(sc->sc_ah))
1605 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1606
1593 /* Initialize LED control */ 1607 /* Initialize LED control */
1594 ath_init_leds(sc); 1608 ath_init_leds(sc);
1595 1609
1610
1596 return 0; 1611 return 0;
1597detach: 1612detach:
1598 ath_detach(sc); 1613 ath_detach(sc);
@@ -1818,6 +1833,37 @@ int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1818 return qnum; 1833 return qnum;
1819} 1834}
1820 1835
1836/* XXX: Remove me once we don't depend on ath9k_channel for all
1837 * this redundant data */
1838static void ath9k_update_ichannel(struct ath_softc *sc,
1839 struct ath9k_channel *ichan)
1840{
1841 struct ieee80211_hw *hw = sc->hw;
1842 struct ieee80211_channel *chan = hw->conf.channel;
1843 struct ieee80211_conf *conf = &hw->conf;
1844
1845 ichan->channel = chan->center_freq;
1846 ichan->chan = chan;
1847
1848 if (chan->band == IEEE80211_BAND_2GHZ) {
1849 ichan->chanmode = CHANNEL_G;
1850 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1851 } else {
1852 ichan->chanmode = CHANNEL_A;
1853 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1854 }
1855
1856 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1857
1858 if (conf_is_ht(conf)) {
1859 if (conf_is_ht40(conf))
1860 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1861
1862 ichan->chanmode = ath_get_extchanmode(sc, chan,
1863 conf->channel_type);
1864 }
1865}
1866
1821/**********************/ 1867/**********************/
1822/* mac80211 callbacks */ 1868/* mac80211 callbacks */
1823/**********************/ 1869/**********************/
@@ -1834,16 +1880,10 @@ static int ath9k_start(struct ieee80211_hw *hw)
1834 1880
1835 /* setup initial channel */ 1881 /* setup initial channel */
1836 1882
1837 pos = ath_get_channel(sc, curchan); 1883 pos = curchan->hw_value;
1838 if (pos == -1) {
1839 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1840 return -EINVAL;
1841 }
1842 1884
1843 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1844 sc->sc_ah->ah_channels[pos].chanmode =
1845 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1846 init_channel = &sc->sc_ah->ah_channels[pos]; 1885 init_channel = &sc->sc_ah->ah_channels[pos];
1886 ath9k_update_ichannel(sc, init_channel);
1847 1887
1848 /* Reset SERDES registers */ 1888 /* Reset SERDES registers */
1849 ath9k_hw_configpcipowersave(sc->sc_ah, 0); 1889 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
@@ -2127,32 +2167,13 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2127 2167
2128 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 2168 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2129 struct ieee80211_channel *curchan = hw->conf.channel; 2169 struct ieee80211_channel *curchan = hw->conf.channel;
2130 int pos; 2170 int pos = curchan->hw_value;
2131 2171
2132 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n", 2172 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2133 curchan->center_freq); 2173 curchan->center_freq);
2134 2174
2135 pos = ath_get_channel(sc, curchan); 2175 /* XXX: remove me eventualy */
2136 if (pos == -1) { 2176 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
2137 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2138 curchan->center_freq);
2139 mutex_unlock(&sc->mutex);
2140 return -EINVAL;
2141 }
2142
2143 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2144 sc->sc_ah->ah_channels[pos].chanmode =
2145 (curchan->band == IEEE80211_BAND_2GHZ) ?
2146 CHANNEL_G : CHANNEL_A;
2147
2148 if (conf_is_ht(conf)) {
2149 if (conf_is_ht40(conf))
2150 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2151
2152 sc->sc_ah->ah_channels[pos].chanmode =
2153 ath_get_extchanmode(sc, curchan,
2154 conf->channel_type);
2155 }
2156 2177
2157 ath_update_chainmask(sc, conf_is_ht(conf)); 2178 ath_update_chainmask(sc, conf_is_ht(conf));
2158 2179
diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c
index 64043e99facf..90f0c982430c 100644
--- a/drivers/net/wireless/ath9k/regd.c
+++ b/drivers/net/wireless/ath9k/regd.c
@@ -21,174 +21,323 @@
21#include "regd.h" 21#include "regd.h"
22#include "regd_common.h" 22#include "regd_common.h"
23 23
24static int ath9k_regd_chansort(const void *a, const void *b) 24/*
25{ 25 * This is a set of common rules used by our world regulatory domains.
26 const struct ath9k_channel *ca = a; 26 * We have 12 world regulatory domains. To save space we consolidate
27 const struct ath9k_channel *cb = b; 27 * the regulatory domains in 5 structures by frequency and change
28 28 * the flags on our reg_notifier() on a case by case basis.
29 return (ca->channel == cb->channel) ? 29 */
30 (ca->channelFlags & CHAN_FLAGS) -
31 (cb->channelFlags & CHAN_FLAGS) : ca->channel - cb->channel;
32}
33 30
34static void 31/* Only these channels all allow active scan on all world regulatory domains */
35ath9k_regd_sort(void *a, u32 n, u32 size, ath_hal_cmp_t *cmp) 32#define ATH9K_2GHZ_CH01_11 REG_RULE(2412-10, 2462+10, 40, 0, 20, 0)
36{ 33
37 u8 *aa = a; 34/* We enable active scan on these a case by case basis by regulatory domain */
38 u8 *ai, *t; 35#define ATH9K_2GHZ_CH12_13 REG_RULE(2467-10, 2472+10, 40, 0, 20,\
39 36 NL80211_RRF_PASSIVE_SCAN)
40 for (ai = aa + size; --n >= 1; ai += size) 37#define ATH9K_2GHZ_CH14 REG_RULE(2484-10, 2484+10, 40, 0, 20,\
41 for (t = ai; t > aa; t -= size) { 38 NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)
42 u8 *u = t - size; 39
43 if (cmp(u, t) <= 0) 40/* We allow IBSS on these on a case by case basis by regulatory domain */
44 break; 41#define ATH9K_5GHZ_5150_5350 REG_RULE(5150-10, 5350+10, 40, 0, 30,\
45 swap_array(u, t, size); 42 NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
46 } 43#define ATH9K_5GHZ_5470_5850 REG_RULE(5470-10, 5850+10, 40, 0, 30,\
47} 44 NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
45#define ATH9K_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 40, 0, 30,\
46 NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
47
48#define ATH9K_2GHZ_ALL ATH9K_2GHZ_CH01_11, \
49 ATH9K_2GHZ_CH12_13, \
50 ATH9K_2GHZ_CH14
51
52#define ATH9K_5GHZ_ALL ATH9K_5GHZ_5150_5350, \
53 ATH9K_5GHZ_5470_5850
54/* This one skips what we call "mid band" */
55#define ATH9K_5GHZ_NO_MIDBAND ATH9K_5GHZ_5150_5350, \
56 ATH9K_5GHZ_5725_5850
57
58/* Can be used for:
59 * 0x60, 0x61, 0x62 */
60static const struct ieee80211_regdomain ath9k_world_regdom_60_61_62 = {
61 .n_reg_rules = 5,
62 .alpha2 = "99",
63 .reg_rules = {
64 ATH9K_2GHZ_ALL,
65 ATH9K_5GHZ_ALL,
66 }
67};
68
69/* Can be used by 0x63 and 0x65 */
70static const struct ieee80211_regdomain ath9k_world_regdom_63_65 = {
71 .n_reg_rules = 4,
72 .alpha2 = "99",
73 .reg_rules = {
74 ATH9K_2GHZ_CH01_11,
75 ATH9K_2GHZ_CH12_13,
76 ATH9K_5GHZ_NO_MIDBAND,
77 }
78};
79
80/* Can be used by 0x64 only */
81static const struct ieee80211_regdomain ath9k_world_regdom_64 = {
82 .n_reg_rules = 3,
83 .alpha2 = "99",
84 .reg_rules = {
85 ATH9K_2GHZ_CH01_11,
86 ATH9K_5GHZ_NO_MIDBAND,
87 }
88};
89
90/* Can be used by 0x66 and 0x69 */
91static const struct ieee80211_regdomain ath9k_world_regdom_66_69 = {
92 .n_reg_rules = 3,
93 .alpha2 = "99",
94 .reg_rules = {
95 ATH9K_2GHZ_CH01_11,
96 ATH9K_5GHZ_ALL,
97 }
98};
99
100/* Can be used by 0x67, 0x6A and 0x68 */
101static const struct ieee80211_regdomain ath9k_world_regdom_67_68_6A = {
102 .n_reg_rules = 4,
103 .alpha2 = "99",
104 .reg_rules = {
105 ATH9K_2GHZ_CH01_11,
106 ATH9K_2GHZ_CH12_13,
107 ATH9K_5GHZ_ALL,
108 }
109};
48 110
49static u16 ath9k_regd_get_eepromRD(struct ath_hal *ah) 111static u16 ath9k_regd_get_eepromRD(struct ath_hal *ah)
50{ 112{
51 return ah->ah_currentRD & ~WORLDWIDE_ROAMING_FLAG; 113 return ah->ah_currentRD & ~WORLDWIDE_ROAMING_FLAG;
52} 114}
53 115
54static bool ath9k_regd_is_chan_bm_zero(u64 *bitmask) 116u16 ath9k_regd_get_rd(struct ath_hal *ah)
55{ 117{
56 int i; 118 return ath9k_regd_get_eepromRD(ah);
119}
57 120
58 for (i = 0; i < BMLEN; i++) { 121bool ath9k_is_world_regd(struct ath_hal *ah)
59 if (bitmask[i] != 0) 122{
60 return false; 123 return isWwrSKU(ah);
61 }
62 return true;
63} 124}
64 125
65static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah) 126const struct ieee80211_regdomain *ath9k_default_world_regdomain(void)
66{ 127{
67 u16 rd = ath9k_regd_get_eepromRD(ah); 128 /* this is the most restrictive */
68 int i; 129 return &ath9k_world_regdom_64;
130}
69 131
70 if (rd & COUNTRY_ERD_FLAG) { 132const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah)
71 u16 cc = rd & ~COUNTRY_ERD_FLAG; 133{
72 for (i = 0; i < ARRAY_SIZE(allCountries); i++) 134 switch (ah->regpair->regDmnEnum) {
73 if (allCountries[i].countryCode == cc) 135 case 0x60:
74 return true; 136 case 0x61:
75 } else { 137 case 0x62:
76 for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) 138 return &ath9k_world_regdom_60_61_62;
77 if (regDomainPairs[i].regDmnEnum == rd) 139 case 0x63:
78 return true; 140 case 0x65:
141 return &ath9k_world_regdom_63_65;
142 case 0x64:
143 return &ath9k_world_regdom_64;
144 case 0x66:
145 case 0x69:
146 return &ath9k_world_regdom_66_69;
147 case 0x67:
148 case 0x68:
149 case 0x6A:
150 return &ath9k_world_regdom_67_68_6A;
151 default:
152 WARN_ON(1);
153 return ath9k_default_world_regdomain();
79 } 154 }
80 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
81 "invalid regulatory domain/country code 0x%x\n", rd);
82 return false;
83} 155}
84 156
85static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah) 157/* Enable adhoc on 5 GHz if allowed by 11d */
158static void ath9k_reg_apply_5ghz_adhoc_flags(struct wiphy *wiphy,
159 enum reg_set_by setby)
86{ 160{
87 u32 regcap; 161 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
88 162 struct ath_softc *sc = hw->priv;
89 regcap = ah->ah_caps.reg_cap; 163 struct ieee80211_supported_band *sband;
164 const struct ieee80211_reg_rule *reg_rule;
165 struct ieee80211_channel *ch;
166 unsigned int i;
167 u32 bandwidth = 0;
168 int r;
169
170 if (setby != REGDOM_SET_BY_COUNTRY_IE)
171 return;
172 if (!test_bit(ATH9K_MODE_11A,
173 sc->sc_ah->ah_caps.wireless_modes))
174 return;
90 175
91 if (regcap & AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND) 176 sband = wiphy->bands[IEEE80211_BAND_5GHZ];
92 return true; 177 for (i = 0; i < sband->n_channels; i++) {
93 else 178 ch = &sband->channels[i];
94 return false; 179 r = freq_reg_info(wiphy, ch->center_freq,
180 &bandwidth, &reg_rule);
181 if (r)
182 continue;
183 /* If 11d had a rule for this channel ensure we enable adhoc
184 * if it allows us to use it. Note that we would have disabled
185 * it by applying our static world regdomain by default during
186 * probe */
187 if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
188 ch->flags &= ~NL80211_RRF_NO_IBSS;
189 }
95} 190}
96 191
97static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah, 192/* Allows active scan scan on Ch 12 and 13 */
98 u16 cc) 193static void ath9k_reg_apply_active_scan_flags(struct wiphy *wiphy,
194 enum reg_set_by setby)
99{ 195{
100 u16 rd; 196 struct ieee80211_supported_band *sband;
101 int i; 197 struct ieee80211_channel *ch;
102 198 const struct ieee80211_reg_rule *reg_rule;
103 if (cc == CTRY_DEFAULT) 199 u32 bandwidth = 0;
104 return true; 200 int r;
105 if (cc == CTRY_DEBUG) 201
106 return true; 202 /* Force passive scan on Channels 12-13 */
203 sband = wiphy->bands[IEEE80211_BAND_2GHZ];
204
205 /* If no country IE has been received always enable active scan
206 * on these channels */
207 if (setby != REGDOM_SET_BY_COUNTRY_IE) {
208 ch = &sband->channels[11]; /* CH 12 */
209 if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
210 ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
211 ch = &sband->channels[12]; /* CH 13 */
212 if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
213 ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
214 return;
215 }
107 216
108 rd = ath9k_regd_get_eepromRD(ah); 217 /* If a country IE has been recieved check its rule for this
109 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "EEPROM regdomain 0x%x\n", rd); 218 * channel first before enabling active scan. The passive scan
219 * would have been enforced by the initial probe processing on
220 * our custom regulatory domain. */
110 221
111 if (rd & COUNTRY_ERD_FLAG) { 222 ch = &sband->channels[11]; /* CH 12 */
112 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 223 r = freq_reg_info(wiphy, ch->center_freq, &bandwidth, &reg_rule);
113 "EEPROM setting is country code %u\n", 224 if (!r) {
114 rd & ~COUNTRY_ERD_FLAG); 225 if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
115 return cc == (rd & ~COUNTRY_ERD_FLAG); 226 if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
227 ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
116 } 228 }
117 229
118 for (i = 0; i < ARRAY_SIZE(allCountries); i++) { 230 ch = &sband->channels[12]; /* CH 13 */
119 if (cc == allCountries[i].countryCode) { 231 r = freq_reg_info(wiphy, ch->center_freq, &bandwidth, &reg_rule);
120#ifdef AH_SUPPORT_11D 232 if (!r) {
121 if ((rd & WORLD_SKU_MASK) == WORLD_SKU_PREFIX) 233 if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
122 return true; 234 if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
123#endif 235 ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
124 if (allCountries[i].regDmnEnum == rd ||
125 rd == DEBUG_REG_DMN || rd == NO_ENUMRD)
126 return true;
127 }
128 } 236 }
129 return false;
130} 237}
131 238
132static void 239/* Always apply Radar/DFS rules on freq range 5260 MHz - 5700 MHz */
133ath9k_regd_get_wmodes_nreg(struct ath_hal *ah, 240void ath9k_reg_apply_radar_flags(struct wiphy *wiphy)
134 struct country_code_to_enum_rd *country,
135 struct regDomain *rd5GHz,
136 unsigned long *modes_allowed)
137{ 241{
138 bitmap_copy(modes_allowed, ah->ah_caps.wireless_modes, ATH9K_MODE_MAX); 242 struct ieee80211_supported_band *sband;
243 struct ieee80211_channel *ch;
244 unsigned int i;
139 245
140 if (test_bit(ATH9K_MODE_11G, ah->ah_caps.wireless_modes) && 246 if (!wiphy->bands[IEEE80211_BAND_5GHZ])
141 (!country->allow11g)) 247 return;
142 clear_bit(ATH9K_MODE_11G, modes_allowed);
143 248
144 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes) && 249 sband = wiphy->bands[IEEE80211_BAND_5GHZ];
145 (ath9k_regd_is_chan_bm_zero(rd5GHz->chan11a)))
146 clear_bit(ATH9K_MODE_11A, modes_allowed);
147 250
148 if (test_bit(ATH9K_MODE_11NG_HT20, ah->ah_caps.wireless_modes) 251 for (i = 0; i < sband->n_channels; i++) {
149 && (!country->allow11ng20)) 252 ch = &sband->channels[i];
150 clear_bit(ATH9K_MODE_11NG_HT20, modes_allowed); 253 if (ch->center_freq < 5260)
254 continue;
255 if (ch->center_freq > 5700)
256 continue;
257 /* We always enable radar detection/DFS on this
258 * frequency range. Additionally we also apply on
259 * this frequency range:
260 * - If STA mode does not yet have DFS supports disable
261 * active scanning
262 * - If adhoc mode does not support DFS yet then
263 * disable adhoc in the frequency.
264 * - If AP mode does not yet support radar detection/DFS
265 * do not allow AP mode
266 */
267 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
268 ch->flags |= IEEE80211_CHAN_RADAR |
269 IEEE80211_CHAN_NO_IBSS |
270 IEEE80211_CHAN_PASSIVE_SCAN;
271 }
272}
151 273
152 if (test_bit(ATH9K_MODE_11NA_HT20, ah->ah_caps.wireless_modes) 274void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby)
153 && (!country->allow11na20)) 275{
154 clear_bit(ATH9K_MODE_11NA_HT20, modes_allowed); 276 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
277 struct ath_softc *sc = hw->priv;
278 struct ath_hal *ah = sc->sc_ah;
279
280 switch (ah->regpair->regDmnEnum) {
281 case 0x60:
282 case 0x63:
283 case 0x66:
284 case 0x67:
285 ath9k_reg_apply_5ghz_adhoc_flags(wiphy, setby);
286 break;
287 case 0x68:
288 ath9k_reg_apply_5ghz_adhoc_flags(wiphy, setby);
289 ath9k_reg_apply_active_scan_flags(wiphy, setby);
290 break;
291 }
292 return;
293}
155 294
156 if (test_bit(ATH9K_MODE_11NG_HT40PLUS, ah->ah_caps.wireless_modes) && 295int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
157 (!country->allow11ng40)) 296{
158 clear_bit(ATH9K_MODE_11NG_HT40PLUS, modes_allowed); 297 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
298 struct ath_softc *sc = hw->priv;
159 299
160 if (test_bit(ATH9K_MODE_11NG_HT40MINUS, ah->ah_caps.wireless_modes) && 300 /* We always apply this */
161 (!country->allow11ng40)) 301 ath9k_reg_apply_radar_flags(wiphy);
162 clear_bit(ATH9K_MODE_11NG_HT40MINUS, modes_allowed);
163 302
164 if (test_bit(ATH9K_MODE_11NA_HT40PLUS, ah->ah_caps.wireless_modes) && 303 switch (request->initiator) {
165 (!country->allow11na40)) 304 case REGDOM_SET_BY_DRIVER:
166 clear_bit(ATH9K_MODE_11NA_HT40PLUS, modes_allowed); 305 case REGDOM_SET_BY_INIT:
306 case REGDOM_SET_BY_CORE:
307 case REGDOM_SET_BY_USER:
308 break;
309 case REGDOM_SET_BY_COUNTRY_IE:
310 if (ath9k_is_world_regd(sc->sc_ah))
311 ath9k_reg_apply_world_flags(wiphy, request->initiator);
312 break;
313 }
167 314
168 if (test_bit(ATH9K_MODE_11NA_HT40MINUS, ah->ah_caps.wireless_modes) && 315 return 0;
169 (!country->allow11na40))
170 clear_bit(ATH9K_MODE_11NA_HT40MINUS, modes_allowed);
171} 316}
172 317
173bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah) 318bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
174{ 319{
175 u16 rd; 320 u16 rd = ath9k_regd_get_eepromRD(ah);
176 321 int i;
177 rd = ath9k_regd_get_eepromRD(ah);
178 322
179 switch (rd) { 323 if (rd & COUNTRY_ERD_FLAG) {
180 case FCC4_FCCA: 324 /* EEPROM value is a country code */
181 case (CTRY_UNITED_STATES_FCC49 | COUNTRY_ERD_FLAG): 325 u16 cc = rd & ~COUNTRY_ERD_FLAG;
182 return true; 326 for (i = 0; i < ARRAY_SIZE(allCountries); i++)
183 case DEBUG_REG_DMN: 327 if (allCountries[i].countryCode == cc)
184 case NO_ENUMRD: 328 return true;
185 if (ah->ah_countryCode == CTRY_UNITED_STATES_FCC49) 329 } else {
186 return true; 330 /* EEPROM value is a regpair value */
187 break; 331 for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++)
332 if (regDomainPairs[i].regDmnEnum == rd)
333 return true;
188 } 334 }
335 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
336 "invalid regulatory domain/country code 0x%x\n", rd);
189 return false; 337 return false;
190} 338}
191 339
340/* EEPROM country code to regpair mapping */
192static struct country_code_to_enum_rd* 341static struct country_code_to_enum_rd*
193ath9k_regd_find_country(u16 countryCode) 342ath9k_regd_find_country(u16 countryCode)
194{ 343{
@@ -201,10 +350,23 @@ ath9k_regd_find_country(u16 countryCode)
201 return NULL; 350 return NULL;
202} 351}
203 352
353/* EEPROM rd code to regpair mapping */
354static struct country_code_to_enum_rd*
355ath9k_regd_find_country_by_rd(int regdmn)
356{
357 int i;
358
359 for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
360 if (allCountries[i].regDmnEnum == regdmn)
361 return &allCountries[i];
362 }
363 return NULL;
364}
365
366/* Returns the map of the EEPROM set RD to a country code */
204static u16 ath9k_regd_get_default_country(struct ath_hal *ah) 367static u16 ath9k_regd_get_default_country(struct ath_hal *ah)
205{ 368{
206 u16 rd; 369 u16 rd;
207 int i;
208 370
209 rd = ath9k_regd_get_eepromRD(ah); 371 rd = ath9k_regd_get_eepromRD(ah);
210 if (rd & COUNTRY_ERD_FLAG) { 372 if (rd & COUNTRY_ERD_FLAG) {
@@ -216,798 +378,104 @@ static u16 ath9k_regd_get_default_country(struct ath_hal *ah)
216 return cc; 378 return cc;
217 } 379 }
218 380
219 for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++)
220 if (regDomainPairs[i].regDmnEnum == rd) {
221 if (regDomainPairs[i].singleCC != 0)
222 return regDomainPairs[i].singleCC;
223 else
224 i = ARRAY_SIZE(regDomainPairs);
225 }
226 return CTRY_DEFAULT; 381 return CTRY_DEFAULT;
227} 382}
228 383
229static bool ath9k_regd_is_valid_reg_domain(int regDmn, 384static struct reg_dmn_pair_mapping*
230 struct regDomain *rd) 385ath9k_get_regpair(int regdmn)
231{
232 int i;
233
234 for (i = 0; i < ARRAY_SIZE(regDomains); i++) {
235 if (regDomains[i].regDmnEnum == regDmn) {
236 if (rd != NULL) {
237 memcpy(rd, &regDomains[i],
238 sizeof(struct regDomain));
239 }
240 return true;
241 }
242 }
243 return false;
244}
245
246static bool ath9k_regd_is_valid_reg_domainPair(int regDmnPair)
247{ 386{
248 int i; 387 int i;
249 388
250 if (regDmnPair == NO_ENUMRD) 389 if (regdmn == NO_ENUMRD)
251 return false; 390 return NULL;
252 for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) { 391 for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) {
253 if (regDomainPairs[i].regDmnEnum == regDmnPair) 392 if (regDomainPairs[i].regDmnEnum == regdmn)
254 return true; 393 return &regDomainPairs[i];
255 } 394 }
256 return false; 395 return NULL;
257}
258
259static bool
260ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
261 u16 channelFlag, struct regDomain *rd)
262{
263 int i, found;
264 u64 flags = NO_REQ;
265 struct reg_dmn_pair_mapping *regPair = NULL;
266 int regOrg;
267
268 regOrg = regDmn;
269 if (regDmn == CTRY_DEFAULT) {
270 u16 rdnum;
271 rdnum = ath9k_regd_get_eepromRD(ah);
272
273 if (!(rdnum & COUNTRY_ERD_FLAG)) {
274 if (ath9k_regd_is_valid_reg_domain(rdnum, NULL) ||
275 ath9k_regd_is_valid_reg_domainPair(rdnum)) {
276 regDmn = rdnum;
277 }
278 }
279 }
280
281 if ((regDmn & MULTI_DOMAIN_MASK) == 0) {
282 for (i = 0, found = 0;
283 (i < ARRAY_SIZE(regDomainPairs)) && (!found); i++) {
284 if (regDomainPairs[i].regDmnEnum == regDmn) {
285 regPair = &regDomainPairs[i];
286 found = 1;
287 }
288 }
289 if (!found) {
290 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
291 "Failed to find reg domain pair %u\n", regDmn);
292 return false;
293 }
294 if (!(channelFlag & CHANNEL_2GHZ)) {
295 regDmn = regPair->regDmn5GHz;
296 flags = regPair->flags5GHz;
297 }
298 if (channelFlag & CHANNEL_2GHZ) {
299 regDmn = regPair->regDmn2GHz;
300 flags = regPair->flags2GHz;
301 }
302 }
303
304 found = ath9k_regd_is_valid_reg_domain(regDmn, rd);
305 if (!found) {
306 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
307 "Failed to find unitary reg domain %u\n", regDmn);
308 return false;
309 } else {
310 rd->pscan &= regPair->pscanMask;
311 if (((regOrg & MULTI_DOMAIN_MASK) == 0) &&
312 (flags != NO_REQ)) {
313 rd->flags = flags;
314 }
315
316 rd->flags &= (channelFlag & CHANNEL_2GHZ) ?
317 REG_DOMAIN_2GHZ_MASK : REG_DOMAIN_5GHZ_MASK;
318 return true;
319 }
320}
321
322static bool ath9k_regd_is_bit_set(int bit, u64 *bitmask)
323{
324 int byteOffset, bitnum;
325 u64 val;
326
327 byteOffset = bit / 64;
328 bitnum = bit - byteOffset * 64;
329 val = ((u64) 1) << bitnum;
330 if (bitmask[byteOffset] & val)
331 return true;
332 else
333 return false;
334}
335
336static void
337ath9k_regd_add_reg_classid(u8 *regclassids, u32 maxregids,
338 u32 *nregids, u8 regclassid)
339{
340 int i;
341
342 if (regclassid == 0)
343 return;
344
345 for (i = 0; i < maxregids; i++) {
346 if (regclassids[i] == regclassid)
347 return;
348 if (regclassids[i] == 0)
349 break;
350 }
351
352 if (i == maxregids)
353 return;
354 else {
355 regclassids[i] = regclassid;
356 *nregids += 1;
357 }
358
359 return;
360}
361
362static bool
363ath9k_regd_get_eeprom_reg_ext_bits(struct ath_hal *ah,
364 enum reg_ext_bitmap bit)
365{
366 return (ah->ah_currentRDExt & (1 << bit)) ? true : false;
367}
368
369#ifdef ATH_NF_PER_CHAN
370
371static void ath9k_regd_init_rf_buffer(struct ath9k_channel *ichans,
372 int nchans)
373{
374 int i, j, next;
375
376 for (next = 0; next < nchans; next++) {
377 for (i = 0; i < NUM_NF_READINGS; i++) {
378 ichans[next].nfCalHist[i].currIndex = 0;
379 ichans[next].nfCalHist[i].privNF =
380 AR_PHY_CCA_MAX_GOOD_VALUE;
381 ichans[next].nfCalHist[i].invalidNFcount =
382 AR_PHY_CCA_FILTERWINDOW_LENGTH;
383 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
384 ichans[next].nfCalHist[i].nfCalBuffer[j] =
385 AR_PHY_CCA_MAX_GOOD_VALUE;
386 }
387 }
388 }
389}
390#endif
391
392static int ath9k_regd_is_chan_present(struct ath_hal *ah,
393 u16 c)
394{
395 int i;
396
397 for (i = 0; i < 150; i++) {
398 if (!ah->ah_channels[i].channel)
399 return -1;
400 else if (ah->ah_channels[i].channel == c)
401 return i;
402 }
403
404 return -1;
405}
406
407static bool
408ath9k_regd_add_channel(struct ath_hal *ah,
409 u16 c,
410 u16 c_lo,
411 u16 c_hi,
412 u16 maxChan,
413 u8 ctl,
414 int pos,
415 struct regDomain rd5GHz,
416 struct RegDmnFreqBand *fband,
417 struct regDomain *rd,
418 const struct cmode *cm,
419 struct ath9k_channel *ichans,
420 bool enableExtendedChannels)
421{
422 struct ath9k_channel *chan;
423 int ret;
424 u32 channelFlags = 0;
425 u8 privFlags = 0;
426
427 if (!(c_lo <= c && c <= c_hi)) {
428 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
429 "c %u out of range [%u..%u]\n",
430 c, c_lo, c_hi);
431 return false;
432 }
433 if ((fband->channelBW == CHANNEL_HALF_BW) &&
434 !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_HALFRATE)) {
435 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
436 "Skipping %u half rate channel\n", c);
437 return false;
438 }
439
440 if ((fband->channelBW == CHANNEL_QUARTER_BW) &&
441 !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_QUARTERRATE)) {
442 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
443 "Skipping %u quarter rate channel\n", c);
444 return false;
445 }
446
447 if (((c + fband->channelSep) / 2) > (maxChan + HALF_MAXCHANBW)) {
448 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
449 "c %u > maxChan %u\n", c, maxChan);
450 return false;
451 }
452
453 if ((fband->usePassScan & IS_ECM_CHAN) && !enableExtendedChannels) {
454 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
455 "Skipping ecm channel\n");
456 return false;
457 }
458
459 if ((rd->flags & NO_HOSTAP) && (ah->ah_opmode == NL80211_IFTYPE_AP)) {
460 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
461 "Skipping HOSTAP channel\n");
462 return false;
463 }
464
465 if (IS_HT40_MODE(cm->mode) &&
466 !(ath9k_regd_get_eeprom_reg_ext_bits(ah, REG_EXT_FCC_DFS_HT40)) &&
467 (fband->useDfs) &&
468 (rd->conformanceTestLimit != MKK)) {
469 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
470 "Skipping HT40 channel (en_fcc_dfs_ht40 = 0)\n");
471 return false;
472 }
473
474 if (IS_HT40_MODE(cm->mode) &&
475 !(ath9k_regd_get_eeprom_reg_ext_bits(ah,
476 REG_EXT_JAPAN_NONDFS_HT40)) &&
477 !(fband->useDfs) && (rd->conformanceTestLimit == MKK)) {
478 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
479 "Skipping HT40 channel (en_jap_ht40 = 0)\n");
480 return false;
481 }
482
483 if (IS_HT40_MODE(cm->mode) &&
484 !(ath9k_regd_get_eeprom_reg_ext_bits(ah, REG_EXT_JAPAN_DFS_HT40)) &&
485 (fband->useDfs) &&
486 (rd->conformanceTestLimit == MKK)) {
487 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
488 "Skipping HT40 channel (en_jap_dfs_ht40 = 0)\n");
489 return false;
490 }
491
492 /* Calculate channel flags */
493
494 channelFlags = cm->flags;
495
496 switch (fband->channelBW) {
497 case CHANNEL_HALF_BW:
498 channelFlags |= CHANNEL_HALF;
499 break;
500 case CHANNEL_QUARTER_BW:
501 channelFlags |= CHANNEL_QUARTER;
502 break;
503 }
504
505 if (fband->usePassScan & rd->pscan)
506 channelFlags |= CHANNEL_PASSIVE;
507 else
508 channelFlags &= ~CHANNEL_PASSIVE;
509 if (fband->useDfs & rd->dfsMask)
510 privFlags = CHANNEL_DFS;
511 else
512 privFlags = 0;
513 if (rd->flags & LIMIT_FRAME_4MS)
514 privFlags |= CHANNEL_4MS_LIMIT;
515 if (privFlags & CHANNEL_DFS)
516 privFlags |= CHANNEL_DISALLOW_ADHOC;
517 if (rd->flags & ADHOC_PER_11D)
518 privFlags |= CHANNEL_PER_11D_ADHOC;
519
520 if (channelFlags & CHANNEL_PASSIVE) {
521 if ((c < 2412) || (c > 2462)) {
522 if (rd5GHz.regDmnEnum == MKK1 ||
523 rd5GHz.regDmnEnum == MKK2) {
524 u32 regcap = ah->ah_caps.reg_cap;
525 if (!(regcap &
526 (AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
527 AR_EEPROM_EEREGCAP_EN_KK_U2 |
528 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) &&
529 isUNII1OddChan(c)) {
530 channelFlags &= ~CHANNEL_PASSIVE;
531 } else {
532 privFlags |= CHANNEL_DISALLOW_ADHOC;
533 }
534 } else {
535 privFlags |= CHANNEL_DISALLOW_ADHOC;
536 }
537 }
538 }
539
540 if ((cm->mode == ATH9K_MODE_11A) ||
541 (cm->mode == ATH9K_MODE_11NA_HT20) ||
542 (cm->mode == ATH9K_MODE_11NA_HT40PLUS) ||
543 (cm->mode == ATH9K_MODE_11NA_HT40MINUS)) {
544 if (rd->flags & (ADHOC_NO_11A | DISALLOW_ADHOC_11A))
545 privFlags |= CHANNEL_DISALLOW_ADHOC;
546 }
547
548 /* Fill in channel details */
549
550 ret = ath9k_regd_is_chan_present(ah, c);
551 if (ret == -1) {
552 chan = &ah->ah_channels[pos];
553 chan->channel = c;
554 chan->maxRegTxPower = fband->powerDfs;
555 chan->antennaMax = fband->antennaMax;
556 chan->regDmnFlags = rd->flags;
557 chan->maxTxPower = AR5416_MAX_RATE_POWER;
558 chan->minTxPower = AR5416_MAX_RATE_POWER;
559 chan->channelFlags = channelFlags;
560 chan->privFlags = privFlags;
561 } else {
562 chan = &ah->ah_channels[ret];
563 chan->channelFlags |= channelFlags;
564 chan->privFlags |= privFlags;
565 }
566
567 /* Set CTLs */
568
569 if ((cm->flags & CHANNEL_ALL) == CHANNEL_A)
570 chan->conformanceTestLimit[0] = ctl;
571 else if ((cm->flags & CHANNEL_ALL) == CHANNEL_B)
572 chan->conformanceTestLimit[1] = ctl;
573 else if ((cm->flags & CHANNEL_ALL) == CHANNEL_G)
574 chan->conformanceTestLimit[2] = ctl;
575
576 return (ret == -1) ? true : false;
577}
578
579static bool ath9k_regd_japan_check(struct ath_hal *ah,
580 int b,
581 struct regDomain *rd5GHz)
582{
583 bool skipband = false;
584 int i;
585 u32 regcap;
586
587 for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) {
588 if (j_bandcheck[i].freqbandbit == b) {
589 regcap = ah->ah_caps.reg_cap;
590 if ((j_bandcheck[i].eepromflagtocheck & regcap) == 0) {
591 skipband = true;
592 } else if ((regcap & AR_EEPROM_EEREGCAP_EN_KK_U2) ||
593 (regcap & AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) {
594 rd5GHz->dfsMask |= DFS_MKK4;
595 rd5GHz->pscan |= PSCAN_MKK3;
596 }
597 break;
598 }
599 }
600
601 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
602 "Skipping %d freq band\n", j_bandcheck[i].freqbandbit);
603
604 return skipband;
605} 396}
606 397
607bool 398int ath9k_regd_init(struct ath_hal *ah)
608ath9k_regd_init_channels(struct ath_hal *ah,
609 u32 maxchans,
610 u32 *nchans, u8 *regclassids,
611 u32 maxregids, u32 *nregids, u16 cc,
612 bool enableOutdoor,
613 bool enableExtendedChannels)
614{ 399{
615 u16 maxChan = 7000;
616 struct country_code_to_enum_rd *country = NULL; 400 struct country_code_to_enum_rd *country = NULL;
617 struct regDomain rd5GHz, rd2GHz;
618 const struct cmode *cm;
619 struct ath9k_channel *ichans = &ah->ah_channels[0];
620 int next = 0, b;
621 u8 ctl;
622 int regdmn; 401 int regdmn;
623 u16 chanSep;
624 unsigned long *modes_avail;
625 DECLARE_BITMAP(modes_allowed, ATH9K_MODE_MAX);
626
627 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "cc %u %s %s\n", cc,
628 enableOutdoor ? "Enable outdoor" : "",
629 enableExtendedChannels ? "Enable ecm" : "");
630
631 if (!ath9k_regd_is_ccode_valid(ah, cc)) {
632 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
633 "Invalid country code %d\n", cc);
634 return false;
635 }
636 402
637 if (!ath9k_regd_is_eeprom_valid(ah)) { 403 if (!ath9k_regd_is_eeprom_valid(ah)) {
638 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 404 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
639 "Invalid EEPROM contents\n"); 405 "Invalid EEPROM contents\n");
640 return false; 406 return -EINVAL;
641 } 407 }
642 408
643 ah->ah_countryCode = ath9k_regd_get_default_country(ah); 409 ah->ah_countryCode = ath9k_regd_get_default_country(ah);
644 410
645 if (ah->ah_countryCode == CTRY_DEFAULT) { 411 if (ah->ah_countryCode == CTRY_DEFAULT &&
646 ah->ah_countryCode = cc & COUNTRY_CODE_MASK; 412 ath9k_regd_get_eepromRD(ah) == CTRY_DEFAULT)
647 if ((ah->ah_countryCode == CTRY_DEFAULT) && 413 ah->ah_countryCode = CTRY_UNITED_STATES;
648 (ath9k_regd_get_eepromRD(ah) == CTRY_DEFAULT)) {
649 ah->ah_countryCode = CTRY_UNITED_STATES;
650 }
651 }
652 414
653#ifdef AH_SUPPORT_11D
654 if (ah->ah_countryCode == CTRY_DEFAULT) { 415 if (ah->ah_countryCode == CTRY_DEFAULT) {
655 regdmn = ath9k_regd_get_eepromRD(ah); 416 regdmn = ath9k_regd_get_eepromRD(ah);
656 country = NULL; 417 country = NULL;
657 } else { 418 } else {
658#endif
659 country = ath9k_regd_find_country(ah->ah_countryCode); 419 country = ath9k_regd_find_country(ah->ah_countryCode);
660 if (country == NULL) { 420 if (country == NULL) {
661 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 421 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
662 "Country is NULL!!!!, cc= %d\n", 422 "Country is NULL!!!!, cc= %d\n",
663 ah->ah_countryCode); 423 ah->ah_countryCode);
664 return false; 424 return -EINVAL;
665 } else { 425 } else
666 regdmn = country->regDmnEnum; 426 regdmn = country->regDmnEnum;
667#ifdef AH_SUPPORT_11D
668 if (((ath9k_regd_get_eepromRD(ah) &
669 WORLD_SKU_MASK) == WORLD_SKU_PREFIX) &&
670 (cc == CTRY_UNITED_STATES)) {
671 if (!isWwrSKU_NoMidband(ah)
672 && ath9k_regd_is_fcc_midband_supported(ah))
673 regdmn = FCC3_FCCA;
674 else
675 regdmn = FCC1_FCCA;
676 }
677#endif
678 }
679#ifdef AH_SUPPORT_11D
680 }
681#endif
682 if (!ath9k_regd_get_wmode_regdomain(ah,
683 regdmn,
684 ~CHANNEL_2GHZ,
685 &rd5GHz)) {
686 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
687 "Couldn't find unitary "
688 "5GHz reg domain for country %u\n",
689 ah->ah_countryCode);
690 return false;
691 }
692 if (!ath9k_regd_get_wmode_regdomain(ah,
693 regdmn,
694 CHANNEL_2GHZ,
695 &rd2GHz)) {
696 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
697 "Couldn't find unitary 2GHz "
698 "reg domain for country %u\n",
699 ah->ah_countryCode);
700 return false;
701 } 427 }
702 428
703 if (!isWwrSKU(ah) && ((rd5GHz.regDmnEnum == FCC1) || 429 ah->ah_currentRDInUse = regdmn;
704 (rd5GHz.regDmnEnum == FCC2))) { 430 ah->regpair = ath9k_get_regpair(regdmn);
705 if (ath9k_regd_is_fcc_midband_supported(ah)) {
706 if (!ath9k_regd_get_wmode_regdomain(ah,
707 FCC3_FCCA,
708 ~CHANNEL_2GHZ,
709 &rd5GHz)) {
710 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
711 "Couldn't find unitary 5GHz "
712 "reg domain for country %u\n",
713 ah->ah_countryCode);
714 return false;
715 }
716 }
717 }
718
719 if (country == NULL) {
720 modes_avail = ah->ah_caps.wireless_modes;
721 } else {
722 ath9k_regd_get_wmodes_nreg(ah, country, &rd5GHz, modes_allowed);
723 modes_avail = modes_allowed;
724
725 if (!enableOutdoor)
726 maxChan = country->outdoorChanStart;
727 }
728
729 next = 0;
730
731 if (maxchans > ARRAY_SIZE(ah->ah_channels))
732 maxchans = ARRAY_SIZE(ah->ah_channels);
733
734 for (cm = modes; cm < &modes[ARRAY_SIZE(modes)]; cm++) {
735 u16 c, c_hi, c_lo;
736 u64 *channelBM = NULL;
737 struct regDomain *rd = NULL;
738 struct RegDmnFreqBand *fband = NULL, *freqs;
739 int8_t low_adj = 0, hi_adj = 0;
740
741 if (!test_bit(cm->mode, modes_avail)) {
742 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
743 "!avail mode %d flags 0x%x\n",
744 cm->mode, cm->flags);
745 continue;
746 }
747 if (!ath9k_get_channel_edges(ah, cm->flags, &c_lo, &c_hi)) {
748 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
749 "channels 0x%x not supported "
750 "by hardware\n", cm->flags);
751 continue;
752 }
753
754 switch (cm->mode) {
755 case ATH9K_MODE_11A:
756 case ATH9K_MODE_11NA_HT20:
757 case ATH9K_MODE_11NA_HT40PLUS:
758 case ATH9K_MODE_11NA_HT40MINUS:
759 rd = &rd5GHz;
760 channelBM = rd->chan11a;
761 freqs = &regDmn5GhzFreq[0];
762 ctl = rd->conformanceTestLimit;
763 break;
764 case ATH9K_MODE_11B:
765 rd = &rd2GHz;
766 channelBM = rd->chan11b;
767 freqs = &regDmn2GhzFreq[0];
768 ctl = rd->conformanceTestLimit | CTL_11B;
769 break;
770 case ATH9K_MODE_11G:
771 case ATH9K_MODE_11NG_HT20:
772 case ATH9K_MODE_11NG_HT40PLUS:
773 case ATH9K_MODE_11NG_HT40MINUS:
774 rd = &rd2GHz;
775 channelBM = rd->chan11g;
776 freqs = &regDmn2Ghz11gFreq[0];
777 ctl = rd->conformanceTestLimit | CTL_11G;
778 break;
779 default:
780 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
781 "Unknown HAL mode 0x%x\n", cm->mode);
782 continue;
783 }
784
785 if (ath9k_regd_is_chan_bm_zero(channelBM))
786 continue;
787
788 if ((cm->mode == ATH9K_MODE_11NA_HT40PLUS) ||
789 (cm->mode == ATH9K_MODE_11NG_HT40PLUS)) {
790 hi_adj = -20;
791 }
792
793 if ((cm->mode == ATH9K_MODE_11NA_HT40MINUS) ||
794 (cm->mode == ATH9K_MODE_11NG_HT40MINUS)) {
795 low_adj = 20;
796 }
797
798 /* XXX: Add a helper here instead */
799 for (b = 0; b < 64 * BMLEN; b++) {
800 if (ath9k_regd_is_bit_set(b, channelBM)) {
801 fband = &freqs[b];
802 if (rd5GHz.regDmnEnum == MKK1
803 || rd5GHz.regDmnEnum == MKK2) {
804 if (ath9k_regd_japan_check(ah,
805 b,
806 &rd5GHz))
807 continue;
808 }
809
810 ath9k_regd_add_reg_classid(regclassids,
811 maxregids,
812 nregids,
813 fband->
814 regClassId);
815
816 if (IS_HT40_MODE(cm->mode) && (rd == &rd5GHz)) {
817 chanSep = 40;
818 if (fband->lowChannel == 5280)
819 low_adj += 20;
820
821 if (fband->lowChannel == 5170)
822 continue;
823 } else
824 chanSep = fband->channelSep;
825
826 for (c = fband->lowChannel + low_adj;
827 ((c <= (fband->highChannel + hi_adj)) &&
828 (c >= (fband->lowChannel + low_adj)));
829 c += chanSep) {
830 if (next >= maxchans) {
831 DPRINTF(ah->ah_sc,
832 ATH_DBG_REGULATORY,
833 "too many channels "
834 "for channel table\n");
835 goto done;
836 }
837 if (ath9k_regd_add_channel(ah,
838 c, c_lo, c_hi,
839 maxChan, ctl,
840 next,
841 rd5GHz,
842 fband, rd, cm,
843 ichans,
844 enableExtendedChannels))
845 next++;
846 }
847 if (IS_HT40_MODE(cm->mode) &&
848 (fband->lowChannel == 5280)) {
849 low_adj -= 20;
850 }
851 }
852 }
853 }
854done:
855 if (next != 0) {
856 int i;
857 431
858 if (next > ARRAY_SIZE(ah->ah_channels)) { 432 if (!ah->regpair) {
859 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 433 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
860 "too many channels %u; truncating to %u\n", 434 "No regulatory domain pair found, cannot continue\n");
861 next, (int) ARRAY_SIZE(ah->ah_channels)); 435 return -EINVAL;
862 next = ARRAY_SIZE(ah->ah_channels);
863 }
864#ifdef ATH_NF_PER_CHAN
865 ath9k_regd_init_rf_buffer(ichans, next);
866#endif
867 ath9k_regd_sort(ichans, next,
868 sizeof(struct ath9k_channel),
869 ath9k_regd_chansort);
870
871 ah->ah_nchan = next;
872
873 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "Channel list:\n");
874 for (i = 0; i < next; i++) {
875 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
876 "chan: %d flags: 0x%x\n",
877 ah->ah_channels[i].channel,
878 ah->ah_channels[i].channelFlags);
879 }
880 } 436 }
881 *nchans = next;
882 437
883 ah->ah_countryCode = ah->ah_countryCode; 438 if (!country)
439 country = ath9k_regd_find_country_by_rd(regdmn);
884 440
885 ah->ah_currentRDInUse = regdmn; 441 if (country) {
886 ah->ah_currentRD5G = rd5GHz.regDmnEnum; 442 ah->alpha2[0] = country->isoName[0];
887 ah->ah_currentRD2G = rd2GHz.regDmnEnum; 443 ah->alpha2[1] = country->isoName[1];
888 if (country == NULL) {
889 ah->ah_iso[0] = 0;
890 ah->ah_iso[1] = 0;
891 } else { 444 } else {
892 ah->ah_iso[0] = country->isoName[0]; 445 ah->alpha2[0] = '0';
893 ah->ah_iso[1] = country->isoName[1]; 446 ah->alpha2[1] = '0';
894 } 447 }
895 448
896 return next != 0;
897}
898
899struct ath9k_channel*
900ath9k_regd_check_channel(struct ath_hal *ah,
901 const struct ath9k_channel *c)
902{
903 struct ath9k_channel *base, *cc;
904
905 int flags = c->channelFlags & CHAN_FLAGS;
906 int n, lim;
907
908 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 449 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
909 "channel %u/0x%x (0x%x) requested\n", 450 "Country alpha2 being used: %c%c\n",
910 c->channel, c->channelFlags, flags); 451 "Regpair detected: 0x%0x\n",
911 452 ah->alpha2[0], ah->alpha2[1],
912 cc = ah->ah_curchan; 453 ah->regpair->regDmnEnum);
913 if (cc != NULL && cc->channel == c->channel &&
914 (cc->channelFlags & CHAN_FLAGS) == flags) {
915 if ((cc->privFlags & CHANNEL_INTERFERENCE) &&
916 (cc->privFlags & CHANNEL_DFS))
917 return NULL;
918 else
919 return cc;
920 }
921 454
922 base = ah->ah_channels; 455 return 0;
923 n = ah->ah_nchan;
924
925 for (lim = n; lim != 0; lim >>= 1) {
926 int d;
927 cc = &base[lim >> 1];
928 d = c->channel - cc->channel;
929 if (d == 0) {
930 if ((cc->channelFlags & CHAN_FLAGS) == flags) {
931 if ((cc->privFlags & CHANNEL_INTERFERENCE) &&
932 (cc->privFlags & CHANNEL_DFS))
933 return NULL;
934 else
935 return cc;
936 }
937 d = flags - (cc->channelFlags & CHAN_FLAGS);
938 }
939 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
940 "channel %u/0x%x d %d\n",
941 cc->channel, cc->channelFlags, d);
942 if (d > 0) {
943 base = cc + 1;
944 lim--;
945 }
946 }
947 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "no match for %u/0x%x\n",
948 c->channel, c->channelFlags);
949 return NULL;
950}
951
952u32
953ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
954 struct ath9k_channel *chan)
955{
956 struct ath9k_channel *ichan = NULL;
957
958 ichan = ath9k_regd_check_channel(ah, chan);
959 if (!ichan)
960 return 0;
961
962 return ichan->antennaMax;
963} 456}
964 457
965u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan) 458u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan)
966{ 459{
967 u32 ctl = NO_CTL; 460 u32 ctl = NO_CTL;
968 struct ath9k_channel *ichan;
969 461
970 if (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) { 462 if (!ah->regpair ||
463 (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah))) {
971 if (IS_CHAN_B(chan)) 464 if (IS_CHAN_B(chan))
972 ctl = SD_NO_CTL | CTL_11B; 465 ctl = SD_NO_CTL | CTL_11B;
973 else if (IS_CHAN_G(chan)) 466 else if (IS_CHAN_G(chan))
974 ctl = SD_NO_CTL | CTL_11G; 467 ctl = SD_NO_CTL | CTL_11G;
975 else 468 else
976 ctl = SD_NO_CTL | CTL_11A; 469 ctl = SD_NO_CTL | CTL_11A;
977 } else { 470 return ctl;
978 ichan = ath9k_regd_check_channel(ah, chan);
979 if (ichan != NULL) {
980 /* FIXME */
981 if (IS_CHAN_A(ichan))
982 ctl = ichan->conformanceTestLimit[0];
983 else if (IS_CHAN_B(ichan))
984 ctl = ichan->conformanceTestLimit[1];
985 else if (IS_CHAN_G(ichan))
986 ctl = ichan->conformanceTestLimit[2];
987
988 if (IS_CHAN_G(chan) && (ctl & 0xf) == CTL_11B)
989 ctl = (ctl & ~0xf) | CTL_11G;
990 }
991 } 471 }
992 return ctl;
993}
994 472
995void ath9k_regd_get_current_country(struct ath_hal *ah, 473 if (IS_CHAN_B(chan))
996 struct ath9k_country_entry *ctry) 474 ctl = ah->regpair->reg_2ghz_ctl | CTL_11B;
997{ 475 else if (IS_CHAN_G(chan))
998 u16 rd = ath9k_regd_get_eepromRD(ah); 476 ctl = ah->regpair->reg_5ghz_ctl | CTL_11G;
477 else
478 ctl = ah->regpair->reg_5ghz_ctl | CTL_11A;
999 479
1000 ctry->isMultidomain = false; 480 return ctl;
1001 if (rd == CTRY_DEFAULT)
1002 ctry->isMultidomain = true;
1003 else if (!(rd & COUNTRY_ERD_FLAG))
1004 ctry->isMultidomain = isWwrSKU(ah);
1005
1006 ctry->countryCode = ah->ah_countryCode;
1007 ctry->regDmnEnum = ah->ah_currentRD;
1008 ctry->regDmn5G = ah->ah_currentRD5G;
1009 ctry->regDmn2G = ah->ah_currentRD2G;
1010 ctry->iso[0] = ah->ah_iso[0];
1011 ctry->iso[1] = ah->ah_iso[1];
1012 ctry->iso[2] = ah->ah_iso[2];
1013} 481}
diff --git a/drivers/net/wireless/ath9k/regd.h b/drivers/net/wireless/ath9k/regd.h
index 512d990aa7ea..ba2d2dfb0d1f 100644
--- a/drivers/net/wireless/ath9k/regd.h
+++ b/drivers/net/wireless/ath9k/regd.h
@@ -19,126 +19,14 @@
19 19
20#include "ath9k.h" 20#include "ath9k.h"
21 21
22#define BMLEN 2
23#define BMZERO {(u64) 0, (u64) 0}
24
25#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
26 {((((_fa >= 0) && (_fa < 64)) ? \
27 (((u64) 1) << _fa) : (u64) 0) | \
28 (((_fb >= 0) && (_fb < 64)) ? \
29 (((u64) 1) << _fb) : (u64) 0) | \
30 (((_fc >= 0) && (_fc < 64)) ? \
31 (((u64) 1) << _fc) : (u64) 0) | \
32 (((_fd >= 0) && (_fd < 64)) ? \
33 (((u64) 1) << _fd) : (u64) 0) | \
34 (((_fe >= 0) && (_fe < 64)) ? \
35 (((u64) 1) << _fe) : (u64) 0) | \
36 (((_ff >= 0) && (_ff < 64)) ? \
37 (((u64) 1) << _ff) : (u64) 0) | \
38 (((_fg >= 0) && (_fg < 64)) ? \
39 (((u64) 1) << _fg) : (u64) 0) | \
40 (((_fh >= 0) && (_fh < 64)) ? \
41 (((u64) 1) << _fh) : (u64) 0) | \
42 (((_fi >= 0) && (_fi < 64)) ? \
43 (((u64) 1) << _fi) : (u64) 0) | \
44 (((_fj >= 0) && (_fj < 64)) ? \
45 (((u64) 1) << _fj) : (u64) 0) | \
46 (((_fk >= 0) && (_fk < 64)) ? \
47 (((u64) 1) << _fk) : (u64) 0) | \
48 (((_fl >= 0) && (_fl < 64)) ? \
49 (((u64) 1) << _fl) : (u64) 0) | \
50 ((((_fa > 63) && (_fa < 128)) ? \
51 (((u64) 1) << (_fa - 64)) : (u64) 0) | \
52 (((_fb > 63) && (_fb < 128)) ? \
53 (((u64) 1) << (_fb - 64)) : (u64) 0) | \
54 (((_fc > 63) && (_fc < 128)) ? \
55 (((u64) 1) << (_fc - 64)) : (u64) 0) | \
56 (((_fd > 63) && (_fd < 128)) ? \
57 (((u64) 1) << (_fd - 64)) : (u64) 0) | \
58 (((_fe > 63) && (_fe < 128)) ? \
59 (((u64) 1) << (_fe - 64)) : (u64) 0) | \
60 (((_ff > 63) && (_ff < 128)) ? \
61 (((u64) 1) << (_ff - 64)) : (u64) 0) | \
62 (((_fg > 63) && (_fg < 128)) ? \
63 (((u64) 1) << (_fg - 64)) : (u64) 0) | \
64 (((_fh > 63) && (_fh < 128)) ? \
65 (((u64) 1) << (_fh - 64)) : (u64) 0) | \
66 (((_fi > 63) && (_fi < 128)) ? \
67 (((u64) 1) << (_fi - 64)) : (u64) 0) | \
68 (((_fj > 63) && (_fj < 128)) ? \
69 (((u64) 1) << (_fj - 64)) : (u64) 0) | \
70 (((_fk > 63) && (_fk < 128)) ? \
71 (((u64) 1) << (_fk - 64)) : (u64) 0) | \
72 (((_fl > 63) && (_fl < 128)) ? \
73 (((u64) 1) << (_fl - 64)) : (u64) 0)))}
74
75#define DEF_REGDMN FCC1_FCCA
76#define DEF_DMN_5 FCC1
77#define DEF_DMN_2 FCCA
78#define COUNTRY_ERD_FLAG 0x8000 22#define COUNTRY_ERD_FLAG 0x8000
79#define WORLDWIDE_ROAMING_FLAG 0x4000 23#define WORLDWIDE_ROAMING_FLAG 0x4000
80#define SUPER_DOMAIN_MASK 0x0fff
81#define COUNTRY_CODE_MASK 0x3fff
82#define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT)
83#define CHANNEL_14 (2484)
84#define IS_11G_CH14(_ch,_cf) \
85 (((_ch) == CHANNEL_14) && ((_cf) == CHANNEL_G))
86
87#define NO_PSCAN 0x0ULL
88#define PSCAN_FCC 0x0000000000000001ULL
89#define PSCAN_FCC_T 0x0000000000000002ULL
90#define PSCAN_ETSI 0x0000000000000004ULL
91#define PSCAN_MKK1 0x0000000000000008ULL
92#define PSCAN_MKK2 0x0000000000000010ULL
93#define PSCAN_MKKA 0x0000000000000020ULL
94#define PSCAN_MKKA_G 0x0000000000000040ULL
95#define PSCAN_ETSIA 0x0000000000000080ULL
96#define PSCAN_ETSIB 0x0000000000000100ULL
97#define PSCAN_ETSIC 0x0000000000000200ULL
98#define PSCAN_WWR 0x0000000000000400ULL
99#define PSCAN_MKKA1 0x0000000000000800ULL
100#define PSCAN_MKKA1_G 0x0000000000001000ULL
101#define PSCAN_MKKA2 0x0000000000002000ULL
102#define PSCAN_MKKA2_G 0x0000000000004000ULL
103#define PSCAN_MKK3 0x0000000000008000ULL
104#define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL
105#define IS_ECM_CHAN 0x8000000000000000ULL
106 24
107#define isWwrSKU(_ah) \ 25#define isWwrSKU(_ah) \
108 (((ath9k_regd_get_eepromRD((_ah)) & WORLD_SKU_MASK) == \ 26 (((ath9k_regd_get_eepromRD((_ah)) & WORLD_SKU_MASK) == \
109 WORLD_SKU_PREFIX) || \ 27 WORLD_SKU_PREFIX) || \
110 (ath9k_regd_get_eepromRD(_ah) == WORLD)) 28 (ath9k_regd_get_eepromRD(_ah) == WORLD))
111 29
112#define isWwrSKU_NoMidband(_ah) \
113 ((ath9k_regd_get_eepromRD((_ah)) == WOR3_WORLD) || \
114 (ath9k_regd_get_eepromRD(_ah) == WOR4_WORLD) || \
115 (ath9k_regd_get_eepromRD(_ah) == WOR5_ETSIC))
116
117#define isUNII1OddChan(ch) \
118 ((ch == 5170) || (ch == 5190) || (ch == 5210) || (ch == 5230))
119
120#define IS_HT40_MODE(_mode) \
121 (((_mode == ATH9K_MODE_11NA_HT40PLUS || \
122 _mode == ATH9K_MODE_11NG_HT40PLUS || \
123 _mode == ATH9K_MODE_11NA_HT40MINUS || \
124 _mode == ATH9K_MODE_11NG_HT40MINUS) ? true : false))
125
126#define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
127
128#define swap_array(_a, _b, _size) { \
129 u8 *s = _b; \
130 int i = _size; \
131 do { \
132 u8 tmp = *_a; \
133 *_a++ = *s; \
134 *s++ = tmp; \
135 } while (--i); \
136 _a -= _size; \
137}
138
139
140#define HALF_MAXCHANBW 10
141
142#define MULTI_DOMAIN_MASK 0xFF00 30#define MULTI_DOMAIN_MASK 0xFF00
143 31
144#define WORLD_SKU_MASK 0x00F0 32#define WORLD_SKU_MASK 0x00F0
@@ -147,81 +35,16 @@
147#define CHANNEL_HALF_BW 10 35#define CHANNEL_HALF_BW 10
148#define CHANNEL_QUARTER_BW 5 36#define CHANNEL_QUARTER_BW 5
149 37
150typedef int ath_hal_cmp_t(const void *, const void *);
151
152struct reg_dmn_pair_mapping { 38struct reg_dmn_pair_mapping {
153 u16 regDmnEnum; 39 u16 regDmnEnum;
154 u16 regDmn5GHz; 40 u16 reg_5ghz_ctl;
155 u16 regDmn2GHz; 41 u16 reg_2ghz_ctl;
156 u32 flags5GHz;
157 u32 flags2GHz;
158 u64 pscanMask;
159 u16 singleCC;
160};
161
162struct ccmap {
163 char isoName[3];
164 u16 countryCode;
165}; 42};
166 43
167struct country_code_to_enum_rd { 44struct country_code_to_enum_rd {
168 u16 countryCode; 45 u16 countryCode;
169 u16 regDmnEnum; 46 u16 regDmnEnum;
170 const char *isoName; 47 const char *isoName;
171 const char *name;
172 bool allow11g;
173 bool allow11aTurbo;
174 bool allow11gTurbo;
175 bool allow11ng20;
176 bool allow11ng40;
177 bool allow11na20;
178 bool allow11na40;
179 u16 outdoorChanStart;
180};
181
182struct RegDmnFreqBand {
183 u16 lowChannel;
184 u16 highChannel;
185 u8 powerDfs;
186 u8 antennaMax;
187 u8 channelBW;
188 u8 channelSep;
189 u64 useDfs;
190 u64 usePassScan;
191 u8 regClassId;
192};
193
194struct regDomain {
195 u16 regDmnEnum;
196 u8 conformanceTestLimit;
197 u64 dfsMask;
198 u64 pscan;
199 u32 flags;
200 u64 chan11a[BMLEN];
201 u64 chan11a_turbo[BMLEN];
202 u64 chan11a_dyn_turbo[BMLEN];
203 u64 chan11b[BMLEN];
204 u64 chan11g[BMLEN];
205 u64 chan11g_turbo[BMLEN];
206};
207
208struct cmode {
209 u32 mode;
210 u32 flags;
211};
212
213#define YES true
214#define NO false
215
216struct japan_bandcheck {
217 u16 freqbandbit;
218 u32 eepromflagtocheck;
219};
220
221struct common_mode_power {
222 u16 lchan;
223 u16 hchan;
224 u8 pwrlvl;
225}; 48};
226 49
227enum CountryCode { 50enum CountryCode {
diff --git a/drivers/net/wireless/ath9k/regd_common.h b/drivers/net/wireless/ath9k/regd_common.h
index 6df1b3b77c25..b41d0002f3fe 100644
--- a/drivers/net/wireless/ath9k/regd_common.h
+++ b/drivers/net/wireless/ath9k/regd_common.h
@@ -150,1766 +150,324 @@ enum EnumRd {
150 MKK9_MKKC = 0xFE, 150 MKK9_MKKC = 0xFE,
151 MKK9_MKKA2 = 0xFF, 151 MKK9_MKKA2 = 0xFF,
152 152
153 APL1 = 0x0150,
154 APL2 = 0x0250,
155 APL3 = 0x0350,
156 APL4 = 0x0450,
157 APL5 = 0x0550,
158 APL6 = 0x0650,
159 APL7 = 0x0750,
160 APL8 = 0x0850,
161 APL9 = 0x0950,
162 APL10 = 0x1050,
163
164 ETSI1 = 0x0130,
165 ETSI2 = 0x0230,
166 ETSI3 = 0x0330,
167 ETSI4 = 0x0430,
168 ETSI5 = 0x0530,
169 ETSI6 = 0x0630,
170 ETSIA = 0x0A30,
171 ETSIB = 0x0B30,
172 ETSIC = 0x0C30,
173
174 FCC1 = 0x0110,
175 FCC2 = 0x0120,
176 FCC3 = 0x0160,
177 FCC4 = 0x0165,
178 FCC5 = 0x0510,
179 FCC6 = 0x0610,
180 FCCA = 0x0A10,
181
182 APLD = 0x0D50,
183
184 MKK1 = 0x0140,
185 MKK2 = 0x0240,
186 MKK3 = 0x0340,
187 MKK4 = 0x0440,
188 MKK5 = 0x0540,
189 MKK6 = 0x0640,
190 MKK7 = 0x0740,
191 MKK8 = 0x0840,
192 MKK9 = 0x0940,
193 MKK10 = 0x0B40,
194 MKK11 = 0x1140,
195 MKK12 = 0x1240,
196 MKK13 = 0x0C40,
197 MKK14 = 0x1440,
198 MKK15 = 0x1540,
199 MKKA = 0x0A40,
200 MKKC = 0x0A50,
201
202 NULL1 = 0x0198,
203 WORLD = 0x0199, 153 WORLD = 0x0199,
204 DEBUG_REG_DMN = 0x01ff, 154 DEBUG_REG_DMN = 0x01ff,
205}; 155};
206 156
207enum { 157enum ctl_group {
208 FCC = 0x10, 158 CTL_FCC = 0x10,
209 MKK = 0x40, 159 CTL_MKK = 0x40,
210 ETSI = 0x30, 160 CTL_ETSI = 0x30,
211};
212
213enum {
214 NO_REQ = 0x00000000,
215 DISALLOW_ADHOC_11A = 0x00000001,
216 DISALLOW_ADHOC_11A_TURB = 0x00000002,
217 NEED_NFC = 0x00000004,
218
219 ADHOC_PER_11D = 0x00000008,
220 ADHOC_NO_11A = 0x00000010,
221
222 PUBLIC_SAFETY_DOMAIN = 0x00000020,
223 LIMIT_FRAME_4MS = 0x00000040,
224
225 NO_HOSTAP = 0x00000080,
226
227 REQ_MASK = 0x000000FF,
228}; 161};
229 162
230#define REG_DOMAIN_2GHZ_MASK (REQ_MASK & \ 163/* Regpair to CTL band mapping */
231 (~(ADHOC_NO_11A | DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB)))
232#define REG_DOMAIN_5GHZ_MASK REQ_MASK
233
234static struct reg_dmn_pair_mapping regDomainPairs[] = { 164static struct reg_dmn_pair_mapping regDomainPairs[] = {
235 {NO_ENUMRD, DEBUG_REG_DMN, DEBUG_REG_DMN, NO_REQ, NO_REQ, 165 /* regpair, 5 GHz CTL, 2 GHz CTL */
236 PSCAN_DEFER, 0}, 166 {NO_ENUMRD, DEBUG_REG_DMN, DEBUG_REG_DMN},
237 {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 167 {NULL1_WORLD, NO_CTL, CTL_ETSI},
238 {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 168 {NULL1_ETSIB, NO_CTL, CTL_ETSI},
239 {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 169 {NULL1_ETSIC, NO_CTL, CTL_ETSI},
240 170
241 {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 171 {FCC2_FCCA, CTL_FCC, CTL_FCC},
242 {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 172 {FCC2_WORLD, CTL_FCC, CTL_ETSI},
243 {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 173 {FCC2_ETSIC, CTL_FCC, CTL_ETSI},
244 {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 174 {FCC3_FCCA, CTL_FCC, CTL_FCC},
245 {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 175 {FCC3_WORLD, CTL_FCC, CTL_ETSI},
246 {FCC4_FCCA, FCC4, FCCA, 176 {FCC4_FCCA, CTL_FCC, CTL_FCC},
247 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 177 {FCC5_FCCA, CTL_FCC, CTL_FCC},
248 0}, 178 {FCC6_FCCA, CTL_FCC, CTL_FCC},
249 {FCC5_FCCA, FCC5, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 179 {FCC6_WORLD, CTL_FCC, CTL_ETSI},
250 {FCC6_FCCA, FCC6, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 180
251 {FCC6_WORLD, FCC6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 181 {ETSI1_WORLD, CTL_ETSI, CTL_ETSI},
252 182 {ETSI2_WORLD, CTL_ETSI, CTL_ETSI},
253 {ETSI1_WORLD, ETSI1, WORLD, 183 {ETSI3_WORLD, CTL_ETSI, CTL_ETSI},
254 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 184 {ETSI4_WORLD, CTL_ETSI, CTL_ETSI},
255 0}, 185 {ETSI5_WORLD, CTL_ETSI, CTL_ETSI},
256 {ETSI2_WORLD, ETSI2, WORLD, 186 {ETSI6_WORLD, CTL_ETSI, CTL_ETSI},
257 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 187
258 0}, 188 /* XXX: For ETSI3_ETSIA, Was NO_CTL meant for the 2 GHz band ? */
259 {ETSI3_WORLD, ETSI3, WORLD, 189 {ETSI3_ETSIA, CTL_ETSI, CTL_ETSI},
260 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 190 {FRANCE_RES, CTL_ETSI, CTL_ETSI},
261 0}, 191
262 {ETSI4_WORLD, ETSI4, WORLD, 192 {FCC1_WORLD, CTL_FCC, CTL_ETSI},
263 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 193 {FCC1_FCCA, CTL_FCC, CTL_FCC},
264 0}, 194 {APL1_WORLD, CTL_FCC, CTL_ETSI},
265 {ETSI5_WORLD, ETSI5, WORLD, 195 {APL2_WORLD, CTL_FCC, CTL_ETSI},
266 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 196 {APL3_WORLD, CTL_FCC, CTL_ETSI},
267 0}, 197 {APL4_WORLD, CTL_FCC, CTL_ETSI},
268 {ETSI6_WORLD, ETSI6, WORLD, 198 {APL5_WORLD, CTL_FCC, CTL_ETSI},
269 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 199 {APL6_WORLD, CTL_ETSI, CTL_ETSI},
270 0}, 200 {APL8_WORLD, CTL_ETSI, CTL_ETSI},
271 201 {APL9_WORLD, CTL_ETSI, CTL_ETSI},
272 {ETSI3_ETSIA, ETSI3, WORLD, 202
273 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 203 {APL3_FCCA, CTL_FCC, CTL_FCC},
274 0}, 204 {APL1_ETSIC, CTL_FCC, CTL_ETSI},
275 {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 205 {APL2_ETSIC, CTL_FCC, CTL_ETSI},
276 206 {APL2_APLD, CTL_FCC, NO_CTL},
277 {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 207
278 {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 208 {MKK1_MKKA, CTL_MKK, CTL_MKK},
279 {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 209 {MKK1_MKKB, CTL_MKK, CTL_MKK},
280 {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 210 {MKK1_FCCA, CTL_MKK, CTL_FCC},
281 {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 211 {MKK1_MKKA1, CTL_MKK, CTL_MKK},
282 {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 212 {MKK1_MKKA2, CTL_MKK, CTL_MKK},
283 {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 213 {MKK1_MKKC, CTL_MKK, CTL_MKK},
284 {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 214
285 {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 215 {MKK2_MKKA, CTL_MKK, CTL_MKK},
286 {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 216 {MKK3_MKKA, CTL_MKK, CTL_MKK},
287 217 {MKK3_MKKB, CTL_MKK, CTL_MKK},
288 {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 218 {MKK3_MKKA1, CTL_MKK, CTL_MKK},
289 {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 219 {MKK3_MKKA2, CTL_MKK, CTL_MKK},
290 {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 220 {MKK3_MKKC, CTL_MKK, CTL_MKK},
291 {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER,}, 221 {MKK3_FCCA, CTL_MKK, CTL_FCC},
292 222
293 {MKK1_MKKA, MKK1, MKKA, 223 {MKK4_MKKA, CTL_MKK, CTL_MKK},
294 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 224 {MKK4_MKKB, CTL_MKK, CTL_MKK},
295 PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN}, 225 {MKK4_MKKA1, CTL_MKK, CTL_MKK},
296 {MKK1_MKKB, MKK1, MKKA, 226 {MKK4_MKKA2, CTL_MKK, CTL_MKK},
297 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | 227 {MKK4_MKKC, CTL_MKK, CTL_MKK},
298 LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, 228 {MKK4_FCCA, CTL_MKK, CTL_FCC},
299 CTRY_JAPAN1}, 229
300 {MKK1_FCCA, MKK1, FCCA, 230 {MKK5_MKKB, CTL_MKK, CTL_MKK},
301 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 231 {MKK5_MKKA2, CTL_MKK, CTL_MKK},
302 PSCAN_MKK1, CTRY_JAPAN2}, 232 {MKK5_MKKC, CTL_MKK, CTL_MKK},
303 {MKK1_MKKA1, MKK1, MKKA, 233
304 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 234 {MKK6_MKKB, CTL_MKK, CTL_MKK},
305 PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4}, 235 {MKK6_MKKA1, CTL_MKK, CTL_MKK},
306 {MKK1_MKKA2, MKK1, MKKA, 236 {MKK6_MKKA2, CTL_MKK, CTL_MKK},
307 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 237 {MKK6_MKKC, CTL_MKK, CTL_MKK},
308 PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5}, 238 {MKK6_FCCA, CTL_MKK, CTL_FCC},
309 {MKK1_MKKC, MKK1, MKKC, 239
310 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 240 {MKK7_MKKB, CTL_MKK, CTL_MKK},
311 PSCAN_MKK1, CTRY_JAPAN6}, 241 {MKK7_MKKA1, CTL_MKK, CTL_MKK},
312 242 {MKK7_MKKA2, CTL_MKK, CTL_MKK},
313 {MKK2_MKKA, MKK2, MKKA, 243 {MKK7_MKKC, CTL_MKK, CTL_MKK},
314 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | 244 {MKK7_FCCA, CTL_MKK, CTL_FCC},
315 LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, 245
316 CTRY_JAPAN3}, 246 {MKK8_MKKB, CTL_MKK, CTL_MKK},
317 247 {MKK8_MKKA2, CTL_MKK, CTL_MKK},
318 {MKK3_MKKA, MKK3, MKKA, 248 {MKK8_MKKC, CTL_MKK, CTL_MKK},
319 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 249
320 PSCAN_MKKA, CTRY_JAPAN25}, 250 {MKK9_MKKA, CTL_MKK, CTL_MKK},
321 {MKK3_MKKB, MKK3, MKKA, 251 {MKK9_FCCA, CTL_MKK, CTL_FCC},
322 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | 252 {MKK9_MKKA1, CTL_MKK, CTL_MKK},
323 LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, 253 {MKK9_MKKA2, CTL_MKK, CTL_MKK},
324 CTRY_JAPAN7}, 254 {MKK9_MKKC, CTL_MKK, CTL_MKK},
325 {MKK3_MKKA1, MKK3, MKKA, 255
326 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 256 {MKK10_MKKA, CTL_MKK, CTL_MKK},
327 PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN26}, 257 {MKK10_FCCA, CTL_MKK, CTL_FCC},
328 {MKK3_MKKA2, MKK3, MKKA, 258 {MKK10_MKKA1, CTL_MKK, CTL_MKK},
329 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 259 {MKK10_MKKA2, CTL_MKK, CTL_MKK},
330 PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8}, 260 {MKK10_MKKC, CTL_MKK, CTL_MKK},
331 {MKK3_MKKC, MKK3, MKKC, 261
332 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 262 {MKK11_MKKA, CTL_MKK, CTL_MKK},
333 NO_PSCAN, CTRY_JAPAN9}, 263 {MKK11_FCCA, CTL_MKK, CTL_FCC},
334 {MKK3_FCCA, MKK3, FCCA, 264 {MKK11_MKKA1, CTL_MKK, CTL_MKK},
335 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 265 {MKK11_MKKA2, CTL_MKK, CTL_MKK},
336 NO_PSCAN, CTRY_JAPAN27}, 266 {MKK11_MKKC, CTL_MKK, CTL_MKK},
337 267
338 {MKK4_MKKA, MKK4, MKKA, 268 {MKK12_MKKA, CTL_MKK, CTL_MKK},
339 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 269 {MKK12_FCCA, CTL_MKK, CTL_FCC},
340 PSCAN_MKK3, CTRY_JAPAN36}, 270 {MKK12_MKKA1, CTL_MKK, CTL_MKK},
341 {MKK4_MKKB, MKK4, MKKA, 271 {MKK12_MKKA2, CTL_MKK, CTL_MKK},
342 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | 272 {MKK12_MKKC, CTL_MKK, CTL_MKK},
343 LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, 273
344 CTRY_JAPAN10}, 274 {MKK13_MKKB, CTL_MKK, CTL_MKK},
345 {MKK4_MKKA1, MKK4, MKKA, 275 {MKK14_MKKA1, CTL_MKK, CTL_MKK},
346 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 276 {MKK15_MKKA1, CTL_MKK, CTL_MKK},
347 PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN28}, 277
348 {MKK4_MKKA2, MKK4, MKKA, 278 {WOR0_WORLD, NO_CTL, NO_CTL},
349 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 279 {WOR1_WORLD, NO_CTL, NO_CTL},
350 PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11}, 280 {WOR2_WORLD, NO_CTL, NO_CTL},
351 {MKK4_MKKC, MKK4, MKKC, 281 {WOR3_WORLD, NO_CTL, NO_CTL},
352 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 282 {WOR4_WORLD, NO_CTL, NO_CTL},
353 PSCAN_MKK3, CTRY_JAPAN12}, 283 {WOR5_ETSIC, NO_CTL, NO_CTL},
354 {MKK4_FCCA, MKK4, FCCA, 284 {WOR01_WORLD, NO_CTL, NO_CTL},
355 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, 285 {WOR02_WORLD, NO_CTL, NO_CTL},
356 PSCAN_MKK3, CTRY_JAPAN29}, 286 {EU1_WORLD, NO_CTL, NO_CTL},
357 287 {WOR9_WORLD, NO_CTL, NO_CTL},
358 {MKK5_MKKB, MKK5, MKKA, 288 {WORA_WORLD, NO_CTL, NO_CTL},
359 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | 289 {WORB_WORLD, NO_CTL, NO_CTL},
360 LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G,
361 CTRY_JAPAN13},
362 {MKK5_MKKA2, MKK5, MKKA,
363 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
364 PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14},
365 {MKK5_MKKC, MKK5, MKKC,
366 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
367 PSCAN_MKK3, CTRY_JAPAN15},
368
369 {MKK6_MKKB, MKK6, MKKA,
370 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
371 PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16},
372 {MKK6_MKKA1, MKK6, MKKA,
373 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
374 PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN30},
375 {MKK6_MKKA2, MKK6, MKKA,
376 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
377 PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17},
378 {MKK6_MKKC, MKK6, MKKC,
379 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
380 PSCAN_MKK1, CTRY_JAPAN18},
381 {MKK6_FCCA, MKK6, FCCA,
382 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
383 NO_PSCAN, CTRY_JAPAN31},
384
385 {MKK7_MKKB, MKK7, MKKA,
386 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
387 PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G,
388 CTRY_JAPAN19},
389 {MKK7_MKKA1, MKK7, MKKA,
390 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
391 PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN32},
392 {MKK7_MKKA2, MKK7, MKKA,
393 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
394 PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G,
395 CTRY_JAPAN20},
396 {MKK7_MKKC, MKK7, MKKC,
397 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
398 PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21},
399 {MKK7_FCCA, MKK7, FCCA,
400 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
401 PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN33},
402
403 {MKK8_MKKB, MKK8, MKKA,
404 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
405 PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G,
406 CTRY_JAPAN22},
407 {MKK8_MKKA2, MKK8, MKKA,
408 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
409 PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G,
410 CTRY_JAPAN23},
411 {MKK8_MKKC, MKK8, MKKC,
412 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
413 PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN24},
414
415 {MKK9_MKKA, MKK9, MKKA,
416 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC |
417 LIMIT_FRAME_4MS, NEED_NFC,
418 PSCAN_MKK2 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G,
419 CTRY_JAPAN34},
420 {MKK9_FCCA, MKK9, FCCA,
421 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
422 NO_PSCAN, CTRY_JAPAN37},
423 {MKK9_MKKA1, MKK9, MKKA,
424 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
425 PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN38},
426 {MKK9_MKKA2, MKK9, MKKA,
427 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
428 PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN40},
429 {MKK9_MKKC, MKK9, MKKC,
430 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
431 NO_PSCAN, CTRY_JAPAN39},
432
433 {MKK10_MKKA, MKK10, MKKA,
434 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC |
435 LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKK3, CTRY_JAPAN35},
436 {MKK10_FCCA, MKK10, FCCA,
437 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
438 NO_PSCAN, CTRY_JAPAN41},
439 {MKK10_MKKA1, MKK10, MKKA,
440 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
441 PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN42},
442 {MKK10_MKKA2, MKK10, MKKA,
443 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
444 PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN44},
445 {MKK10_MKKC, MKK10, MKKC,
446 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
447 NO_PSCAN, CTRY_JAPAN43},
448
449 {MKK11_MKKA, MKK11, MKKA,
450 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
451 PSCAN_MKK3, CTRY_JAPAN45},
452 {MKK11_FCCA, MKK11, FCCA,
453 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
454 PSCAN_MKK3, CTRY_JAPAN46},
455 {MKK11_MKKA1, MKK11, MKKA,
456 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
457 PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN47},
458 {MKK11_MKKA2, MKK11, MKKA,
459 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
460 PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN49},
461 {MKK11_MKKC, MKK11, MKKC,
462 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
463 PSCAN_MKK3, CTRY_JAPAN48},
464
465 {MKK12_MKKA, MKK12, MKKA,
466 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
467 PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN50},
468 {MKK12_FCCA, MKK12, FCCA,
469 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
470 PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN51},
471 {MKK12_MKKA1, MKK12, MKKA,
472 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
473 PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G,
474 CTRY_JAPAN52},
475 {MKK12_MKKA2, MKK12, MKKA,
476 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
477 PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G,
478 CTRY_JAPAN54},
479 {MKK12_MKKC, MKK12, MKKC,
480 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
481 PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN53},
482
483 {MKK13_MKKB, MKK13, MKKA,
484 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC |
485 LIMIT_FRAME_4MS, NEED_NFC,
486 PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G,
487 CTRY_JAPAN57},
488
489 {MKK14_MKKA1, MKK14, MKKA,
490 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
491 PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN58},
492 {MKK15_MKKA1, MKK15, MKKA,
493 DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC,
494 PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN59},
495
496 {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER,
497 0},
498 {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD,
499 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER,
500 0},
501 {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB,
502 NO_REQ, PSCAN_DEFER, 0},
503 {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER,
504 0},
505 {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD,
506 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER,
507 0},
508 {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC,
509 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER,
510 0},
511 {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ,
512 PSCAN_DEFER, 0},
513 {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ,
514 PSCAN_DEFER, 0},
515 {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0},
516 {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD,
517 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER,
518 0},
519 {WORA_WORLD, WORA_WORLD, WORA_WORLD,
520 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER,
521 0},
522 {WORB_WORLD, WORB_WORLD, WORB_WORLD,
523 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER,
524 0},
525}; 290};
526 291
527#define NO_INTERSECT_REQ 0xFFFFFFFF
528#define NO_UNION_REQ 0
529
530static struct country_code_to_enum_rd allCountries[] = { 292static struct country_code_to_enum_rd allCountries[] = {
531 {CTRY_DEBUG, NO_ENUMRD, "DB", "DEBUG", YES, YES, YES, YES, YES, 293 {CTRY_DEBUG, NO_ENUMRD, "DB"},
532 YES, YES, 7000}, 294 {CTRY_DEFAULT, FCC1_FCCA, "CO"},
533 {CTRY_DEFAULT, DEF_REGDMN, "NA", "NO_COUNTRY_SET", YES, YES, YES, 295 {CTRY_ALBANIA, NULL1_WORLD, "AL"},
534 YES, YES, YES, YES, 7000}, 296 {CTRY_ALGERIA, NULL1_WORLD, "DZ"},
535 {CTRY_ALBANIA, NULL1_WORLD, "AL", "ALBANIA", YES, NO, YES, YES, NO, 297 {CTRY_ARGENTINA, APL3_WORLD, "AR"},
536 NO, NO, 7000}, 298 {CTRY_ARMENIA, ETSI4_WORLD, "AM"},
537 {CTRY_ALGERIA, NULL1_WORLD, "DZ", "ALGERIA", YES, NO, YES, YES, NO, 299 {CTRY_AUSTRALIA, FCC2_WORLD, "AU"},
538 NO, NO, 7000}, 300 {CTRY_AUSTRALIA2, FCC6_WORLD, "AU"},
539 {CTRY_ARGENTINA, APL3_WORLD, "AR", "ARGENTINA", YES, NO, NO, YES, 301 {CTRY_AUSTRIA, ETSI1_WORLD, "AT"},
540 NO, YES, NO, 7000}, 302 {CTRY_AZERBAIJAN, ETSI4_WORLD, "AZ"},
541 {CTRY_ARMENIA, ETSI4_WORLD, "AM", "ARMENIA", YES, NO, YES, YES, 303 {CTRY_BAHRAIN, APL6_WORLD, "BH"},
542 YES, NO, NO, 7000}, 304 {CTRY_BELARUS, ETSI1_WORLD, "BY"},
543 {CTRY_AUSTRALIA, FCC2_WORLD, "AU", "AUSTRALIA", YES, YES, YES, YES, 305 {CTRY_BELGIUM, ETSI1_WORLD, "BE"},
544 YES, YES, YES, 7000}, 306 {CTRY_BELGIUM2, ETSI4_WORLD, "BL"},
545 {CTRY_AUSTRALIA2, FCC6_WORLD, "AU", "AUSTRALIA2", YES, YES, YES, 307 {CTRY_BELIZE, APL1_ETSIC, "BZ"},
546 YES, YES, YES, YES, 7000}, 308 {CTRY_BOLIVIA, APL1_ETSIC, "BO"},
547 {CTRY_AUSTRIA, ETSI1_WORLD, "AT", "AUSTRIA", YES, NO, YES, YES, 309 {CTRY_BOSNIA_HERZ, ETSI1_WORLD, "BA"},
548 YES, YES, YES, 7000}, 310 {CTRY_BRAZIL, FCC3_WORLD, "BR"},
549 {CTRY_AZERBAIJAN, ETSI4_WORLD, "AZ", "AZERBAIJAN", YES, YES, YES, 311 {CTRY_BRUNEI_DARUSSALAM, APL1_WORLD, "BN"},
550 YES, YES, YES, YES, 7000}, 312 {CTRY_BULGARIA, ETSI6_WORLD, "BG"},
551 {CTRY_BAHRAIN, APL6_WORLD, "BH", "BAHRAIN", YES, NO, YES, YES, YES, 313 {CTRY_CANADA, FCC2_FCCA, "CA"},
552 YES, NO, 7000}, 314 {CTRY_CANADA2, FCC6_FCCA, "CA"},
553 {CTRY_BELARUS, ETSI1_WORLD, "BY", "BELARUS", YES, NO, YES, YES, 315 {CTRY_CHILE, APL6_WORLD, "CL"},
554 YES, YES, YES, 7000}, 316 {CTRY_CHINA, APL1_WORLD, "CN"},
555 {CTRY_BELGIUM, ETSI1_WORLD, "BE", "BELGIUM", YES, NO, YES, YES, 317 {CTRY_COLOMBIA, FCC1_FCCA, "CO"},
556 YES, YES, YES, 7000}, 318 {CTRY_COSTA_RICA, FCC1_WORLD, "CR"},
557 {CTRY_BELGIUM2, ETSI4_WORLD, "BL", "BELGIUM", YES, NO, YES, YES, 319 {CTRY_CROATIA, ETSI3_WORLD, "HR"},
558 YES, YES, YES, 7000}, 320 {CTRY_CYPRUS, ETSI1_WORLD, "CY"},
559 {CTRY_BELIZE, APL1_ETSIC, "BZ", "BELIZE", YES, YES, YES, YES, YES, 321 {CTRY_CZECH, ETSI3_WORLD, "CZ"},
560 YES, YES, 7000}, 322 {CTRY_DENMARK, ETSI1_WORLD, "DK"},
561 {CTRY_BOLIVIA, APL1_ETSIC, "BO", "BOLVIA", YES, YES, YES, YES, YES, 323 {CTRY_DOMINICAN_REPUBLIC, FCC1_FCCA, "DO"},
562 YES, YES, 7000}, 324 {CTRY_ECUADOR, FCC1_WORLD, "EC"},
563 {CTRY_BOSNIA_HERZ, ETSI1_WORLD, "BA", "BOSNIA_HERZGOWINA", YES, NO, 325 {CTRY_EGYPT, ETSI3_WORLD, "EG"},
564 YES, YES, YES, YES, NO, 7000}, 326 {CTRY_EL_SALVADOR, FCC1_WORLD, "SV"},
565 {CTRY_BRAZIL, FCC3_WORLD, "BR", "BRAZIL", YES, NO, NO, YES, NO, 327 {CTRY_ESTONIA, ETSI1_WORLD, "EE"},
566 YES, NO, 7000}, 328 {CTRY_FINLAND, ETSI1_WORLD, "FI"},
567 {CTRY_BRUNEI_DARUSSALAM, APL1_WORLD, "BN", "BRUNEI DARUSSALAM", 329 {CTRY_FRANCE, ETSI1_WORLD, "FR"},
568 YES, YES, YES, YES, YES, YES, YES, 7000}, 330 {CTRY_GEORGIA, ETSI4_WORLD, "GE"},
569 {CTRY_BULGARIA, ETSI6_WORLD, "BG", "BULGARIA", YES, NO, YES, YES, 331 {CTRY_GERMANY, ETSI1_WORLD, "DE"},
570 YES, YES, YES, 7000}, 332 {CTRY_GREECE, ETSI1_WORLD, "GR"},
571 {CTRY_CANADA, FCC2_FCCA, "CA", "CANADA", YES, YES, YES, YES, YES, 333 {CTRY_GUATEMALA, FCC1_FCCA, "GT"},
572 YES, YES, 7000}, 334 {CTRY_HONDURAS, NULL1_WORLD, "HN"},
573 {CTRY_CANADA2, FCC6_FCCA, "CA", "CANADA2", YES, YES, YES, YES, YES, 335 {CTRY_HONG_KONG, FCC2_WORLD, "HK"},
574 YES, YES, 7000}, 336 {CTRY_HUNGARY, ETSI1_WORLD, "HU"},
575 {CTRY_CHILE, APL6_WORLD, "CL", "CHILE", YES, YES, YES, YES, YES, 337 {CTRY_ICELAND, ETSI1_WORLD, "IS"},
576 YES, YES, 7000}, 338 {CTRY_INDIA, APL6_WORLD, "IN"},
577 {CTRY_CHINA, APL1_WORLD, "CN", "CHINA", YES, YES, YES, YES, YES, 339 {CTRY_INDONESIA, APL1_WORLD, "ID"},
578 YES, YES, 7000}, 340 {CTRY_IRAN, APL1_WORLD, "IR"},
579 {CTRY_COLOMBIA, FCC1_FCCA, "CO", "COLOMBIA", YES, NO, YES, YES, 341 {CTRY_IRELAND, ETSI1_WORLD, "IE"},
580 YES, YES, NO, 7000}, 342 {CTRY_ISRAEL, NULL1_WORLD, "IL"},
581 {CTRY_COSTA_RICA, FCC1_WORLD, "CR", "COSTA RICA", YES, NO, YES, 343 {CTRY_ITALY, ETSI1_WORLD, "IT"},
582 YES, YES, YES, NO, 7000}, 344 {CTRY_JAMAICA, ETSI1_WORLD, "JM"},
583 {CTRY_CROATIA, ETSI3_WORLD, "HR", "CROATIA", YES, NO, YES, YES, 345
584 YES, YES, NO, 7000}, 346 {CTRY_JAPAN, MKK1_MKKA, "JP"},
585 {CTRY_CYPRUS, ETSI1_WORLD, "CY", "CYPRUS", YES, YES, YES, YES, YES, 347 {CTRY_JAPAN1, MKK1_MKKB, "JP"},
586 YES, YES, 7000}, 348 {CTRY_JAPAN2, MKK1_FCCA, "JP"},
587 {CTRY_CZECH, ETSI3_WORLD, "CZ", "CZECH REPUBLIC", YES, NO, YES, 349 {CTRY_JAPAN3, MKK2_MKKA, "JP"},
588 YES, YES, YES, YES, 7000}, 350 {CTRY_JAPAN4, MKK1_MKKA1, "JP"},
589 {CTRY_DENMARK, ETSI1_WORLD, "DK", "DENMARK", YES, NO, YES, YES, 351 {CTRY_JAPAN5, MKK1_MKKA2, "JP"},
590 YES, YES, YES, 7000}, 352 {CTRY_JAPAN6, MKK1_MKKC, "JP"},
591 {CTRY_DOMINICAN_REPUBLIC, FCC1_FCCA, "DO", "DOMINICAN REPUBLIC", 353 {CTRY_JAPAN7, MKK3_MKKB, "JP"},
592 YES, YES, YES, YES, YES, YES, YES, 7000}, 354 {CTRY_JAPAN8, MKK3_MKKA2, "JP"},
593 {CTRY_ECUADOR, FCC1_WORLD, "EC", "ECUADOR", YES, NO, NO, YES, YES, 355 {CTRY_JAPAN9, MKK3_MKKC, "JP"},
594 YES, NO, 7000}, 356 {CTRY_JAPAN10, MKK4_MKKB, "JP"},
595 {CTRY_EGYPT, ETSI3_WORLD, "EG", "EGYPT", YES, NO, YES, YES, YES, 357 {CTRY_JAPAN11, MKK4_MKKA2, "JP"},
596 YES, NO, 7000}, 358 {CTRY_JAPAN12, MKK4_MKKC, "JP"},
597 {CTRY_EL_SALVADOR, FCC1_WORLD, "SV", "EL SALVADOR", YES, NO, YES, 359 {CTRY_JAPAN13, MKK5_MKKB, "JP"},
598 YES, YES, YES, NO, 7000}, 360 {CTRY_JAPAN14, MKK5_MKKA2, "JP"},
599 {CTRY_ESTONIA, ETSI1_WORLD, "EE", "ESTONIA", YES, NO, YES, YES, 361 {CTRY_JAPAN15, MKK5_MKKC, "JP"},
600 YES, YES, YES, 7000}, 362 {CTRY_JAPAN16, MKK6_MKKB, "JP"},
601 {CTRY_FINLAND, ETSI1_WORLD, "FI", "FINLAND", YES, NO, YES, YES, 363 {CTRY_JAPAN17, MKK6_MKKA2, "JP"},
602 YES, YES, YES, 7000}, 364 {CTRY_JAPAN18, MKK6_MKKC, "JP"},
603 {CTRY_FRANCE, ETSI1_WORLD, "FR", "FRANCE", YES, NO, YES, YES, YES, 365 {CTRY_JAPAN19, MKK7_MKKB, "JP"},
604 YES, YES, 7000}, 366 {CTRY_JAPAN20, MKK7_MKKA2, "JP"},
605 {CTRY_GEORGIA, ETSI4_WORLD, "GE", "GEORGIA", YES, YES, YES, YES, 367 {CTRY_JAPAN21, MKK7_MKKC, "JP"},
606 YES, YES, YES, 7000}, 368 {CTRY_JAPAN22, MKK8_MKKB, "JP"},
607 {CTRY_GERMANY, ETSI1_WORLD, "DE", "GERMANY", YES, NO, YES, YES, 369 {CTRY_JAPAN23, MKK8_MKKA2, "JP"},
608 YES, YES, YES, 7000}, 370 {CTRY_JAPAN24, MKK8_MKKC, "JP"},
609 {CTRY_GREECE, ETSI1_WORLD, "GR", "GREECE", YES, NO, YES, YES, YES, 371 {CTRY_JAPAN25, MKK3_MKKA, "JP"},
610 YES, YES, 7000}, 372 {CTRY_JAPAN26, MKK3_MKKA1, "JP"},
611 {CTRY_GUATEMALA, FCC1_FCCA, "GT", "GUATEMALA", YES, YES, YES, YES, 373 {CTRY_JAPAN27, MKK3_FCCA, "JP"},
612 YES, YES, YES, 7000}, 374 {CTRY_JAPAN28, MKK4_MKKA1, "JP"},
613 {CTRY_HONDURAS, NULL1_WORLD, "HN", "HONDURAS", YES, NO, YES, YES, 375 {CTRY_JAPAN29, MKK4_FCCA, "JP"},
614 YES, NO, NO, 7000}, 376 {CTRY_JAPAN30, MKK6_MKKA1, "JP"},
615 {CTRY_HONG_KONG, FCC2_WORLD, "HK", "HONG KONG", YES, YES, YES, YES, 377 {CTRY_JAPAN31, MKK6_FCCA, "JP"},
616 YES, YES, YES, 7000}, 378 {CTRY_JAPAN32, MKK7_MKKA1, "JP"},
617 {CTRY_HUNGARY, ETSI1_WORLD, "HU", "HUNGARY", YES, NO, YES, YES, 379 {CTRY_JAPAN33, MKK7_FCCA, "JP"},
618 YES, YES, YES, 7000}, 380 {CTRY_JAPAN34, MKK9_MKKA, "JP"},
619 {CTRY_ICELAND, ETSI1_WORLD, "IS", "ICELAND", YES, NO, YES, YES, 381 {CTRY_JAPAN35, MKK10_MKKA, "JP"},
620 YES, YES, YES, 7000}, 382 {CTRY_JAPAN36, MKK4_MKKA, "JP"},
621 {CTRY_INDIA, APL6_WORLD, "IN", "INDIA", YES, NO, YES, YES, YES, 383 {CTRY_JAPAN37, MKK9_FCCA, "JP"},
622 YES, NO, 7000}, 384 {CTRY_JAPAN38, MKK9_MKKA1, "JP"},
623 {CTRY_INDONESIA, APL1_WORLD, "ID", "INDONESIA", YES, NO, YES, YES, 385 {CTRY_JAPAN39, MKK9_MKKC, "JP"},
624 YES, YES, NO, 7000}, 386 {CTRY_JAPAN40, MKK9_MKKA2, "JP"},
625 {CTRY_IRAN, APL1_WORLD, "IR", "IRAN", YES, YES, YES, YES, YES, YES, 387 {CTRY_JAPAN41, MKK10_FCCA, "JP"},
626 YES, 7000}, 388 {CTRY_JAPAN42, MKK10_MKKA1, "JP"},
627 {CTRY_IRELAND, ETSI1_WORLD, "IE", "IRELAND", YES, NO, YES, YES, 389 {CTRY_JAPAN43, MKK10_MKKC, "JP"},
628 YES, YES, YES, 7000}, 390 {CTRY_JAPAN44, MKK10_MKKA2, "JP"},
629 {CTRY_ISRAEL, NULL1_WORLD, "IL", "ISRAEL", YES, NO, YES, YES, YES, 391 {CTRY_JAPAN45, MKK11_MKKA, "JP"},
630 NO, NO, 7000}, 392 {CTRY_JAPAN46, MKK11_FCCA, "JP"},
631 {CTRY_ITALY, ETSI1_WORLD, "IT", "ITALY", YES, NO, YES, YES, YES, 393 {CTRY_JAPAN47, MKK11_MKKA1, "JP"},
632 YES, YES, 7000}, 394 {CTRY_JAPAN48, MKK11_MKKC, "JP"},
633 {CTRY_JAMAICA, ETSI1_WORLD, "JM", "JAMAICA", YES, NO, YES, YES, 395 {CTRY_JAPAN49, MKK11_MKKA2, "JP"},
634 YES, YES, YES, 7000}, 396 {CTRY_JAPAN50, MKK12_MKKA, "JP"},
635 397 {CTRY_JAPAN51, MKK12_FCCA, "JP"},
636 {CTRY_JAPAN, MKK1_MKKA, "JP", "JAPAN", YES, NO, NO, YES, YES, YES, 398 {CTRY_JAPAN52, MKK12_MKKA1, "JP"},
637 YES, 7000}, 399 {CTRY_JAPAN53, MKK12_MKKC, "JP"},
638 {CTRY_JAPAN1, MKK1_MKKB, "JP", "JAPAN1", YES, NO, NO, YES, YES, 400 {CTRY_JAPAN54, MKK12_MKKA2, "JP"},
639 YES, YES, 7000}, 401 {CTRY_JAPAN57, MKK13_MKKB, "JP"},
640 {CTRY_JAPAN2, MKK1_FCCA, "JP", "JAPAN2", YES, NO, NO, YES, YES, 402 {CTRY_JAPAN58, MKK14_MKKA1, "JP"},
641 YES, YES, 7000}, 403 {CTRY_JAPAN59, MKK15_MKKA1, "JP"},
642 {CTRY_JAPAN3, MKK2_MKKA, "JP", "JAPAN3", YES, NO, NO, YES, YES, 404
643 YES, YES, 7000}, 405 {CTRY_JORDAN, ETSI2_WORLD, "JO"},
644 {CTRY_JAPAN4, MKK1_MKKA1, "JP", "JAPAN4", YES, NO, NO, YES, YES, 406 {CTRY_KAZAKHSTAN, NULL1_WORLD, "KZ"},
645 YES, YES, 7000}, 407 {CTRY_KOREA_NORTH, APL9_WORLD, "KP"},
646 {CTRY_JAPAN5, MKK1_MKKA2, "JP", "JAPAN5", YES, NO, NO, YES, YES, 408 {CTRY_KOREA_ROC, APL9_WORLD, "KR"},
647 YES, YES, 7000}, 409 {CTRY_KOREA_ROC2, APL2_WORLD, "K2"},
648 {CTRY_JAPAN6, MKK1_MKKC, "JP", "JAPAN6", YES, NO, NO, YES, YES, 410 {CTRY_KOREA_ROC3, APL9_WORLD, "K3"},
649 YES, YES, 7000}, 411 {CTRY_KUWAIT, NULL1_WORLD, "KW"},
650 412 {CTRY_LATVIA, ETSI1_WORLD, "LV"},
651 {CTRY_JAPAN7, MKK3_MKKB, "JP", "JAPAN7", YES, NO, NO, YES, YES, 413 {CTRY_LEBANON, NULL1_WORLD, "LB"},
652 YES, YES, 7000}, 414 {CTRY_LIECHTENSTEIN, ETSI1_WORLD, "LI"},
653 {CTRY_JAPAN8, MKK3_MKKA2, "JP", "JAPAN8", YES, NO, NO, YES, YES, 415 {CTRY_LITHUANIA, ETSI1_WORLD, "LT"},
654 YES, YES, 7000}, 416 {CTRY_LUXEMBOURG, ETSI1_WORLD, "LU"},
655 {CTRY_JAPAN9, MKK3_MKKC, "JP", "JAPAN9", YES, NO, NO, YES, YES, 417 {CTRY_MACAU, FCC2_WORLD, "MO"},
656 YES, YES, 7000}, 418 {CTRY_MACEDONIA, NULL1_WORLD, "MK"},
657 419 {CTRY_MALAYSIA, APL8_WORLD, "MY"},
658 {CTRY_JAPAN10, MKK4_MKKB, "JP", "JAPAN10", YES, NO, NO, YES, YES, 420 {CTRY_MALTA, ETSI1_WORLD, "MT"},
659 YES, YES, 7000}, 421 {CTRY_MEXICO, FCC1_FCCA, "MX"},
660 {CTRY_JAPAN11, MKK4_MKKA2, "JP", "JAPAN11", YES, NO, NO, YES, YES, 422 {CTRY_MONACO, ETSI4_WORLD, "MC"},
661 YES, YES, 7000}, 423 {CTRY_MOROCCO, NULL1_WORLD, "MA"},
662 {CTRY_JAPAN12, MKK4_MKKC, "JP", "JAPAN12", YES, NO, NO, YES, YES, 424 {CTRY_NEPAL, APL1_WORLD, "NP"},
663 YES, YES, 7000}, 425 {CTRY_NETHERLANDS, ETSI1_WORLD, "NL"},
664 426 {CTRY_NETHERLANDS_ANTILLES, ETSI1_WORLD, "AN"},
665 {CTRY_JAPAN13, MKK5_MKKB, "JP", "JAPAN13", YES, NO, NO, YES, YES, 427 {CTRY_NEW_ZEALAND, FCC2_ETSIC, "NZ"},
666 YES, YES, 7000}, 428 {CTRY_NORWAY, ETSI1_WORLD, "NO"},
667 {CTRY_JAPAN14, MKK5_MKKA2, "JP", "JAPAN14", YES, NO, NO, YES, YES, 429 {CTRY_OMAN, APL6_WORLD, "OM"},
668 YES, YES, 7000}, 430 {CTRY_PAKISTAN, NULL1_WORLD, "PK"},
669 {CTRY_JAPAN15, MKK5_MKKC, "JP", "JAPAN15", YES, NO, NO, YES, YES, 431 {CTRY_PANAMA, FCC1_FCCA, "PA"},
670 YES, YES, 7000}, 432 {CTRY_PAPUA_NEW_GUINEA, FCC1_WORLD, "PG"},
671 433 {CTRY_PERU, APL1_WORLD, "PE"},
672 {CTRY_JAPAN16, MKK6_MKKB, "JP", "JAPAN16", YES, NO, NO, YES, YES, 434 {CTRY_PHILIPPINES, APL1_WORLD, "PH"},
673 YES, YES, 7000}, 435 {CTRY_POLAND, ETSI1_WORLD, "PL"},
674 {CTRY_JAPAN17, MKK6_MKKA2, "JP", "JAPAN17", YES, NO, NO, YES, YES, 436 {CTRY_PORTUGAL, ETSI1_WORLD, "PT"},
675 YES, YES, 7000}, 437 {CTRY_PUERTO_RICO, FCC1_FCCA, "PR"},
676 {CTRY_JAPAN18, MKK6_MKKC, "JP", "JAPAN18", YES, NO, NO, YES, YES, 438 {CTRY_QATAR, NULL1_WORLD, "QA"},
677 YES, YES, 7000}, 439 {CTRY_ROMANIA, NULL1_WORLD, "RO"},
678 440 {CTRY_RUSSIA, NULL1_WORLD, "RU"},
679 {CTRY_JAPAN19, MKK7_MKKB, "JP", "JAPAN19", YES, NO, NO, YES, YES, 441 {CTRY_SAUDI_ARABIA, NULL1_WORLD, "SA"},
680 YES, YES, 7000}, 442 {CTRY_SERBIA_MONTENEGRO, ETSI1_WORLD, "CS"},
681 {CTRY_JAPAN20, MKK7_MKKA2, "JP", "JAPAN20", YES, NO, NO, YES, YES, 443 {CTRY_SINGAPORE, APL6_WORLD, "SG"},
682 YES, YES, 7000}, 444 {CTRY_SLOVAKIA, ETSI1_WORLD, "SK"},
683 {CTRY_JAPAN21, MKK7_MKKC, "JP", "JAPAN21", YES, NO, NO, YES, YES, 445 {CTRY_SLOVENIA, ETSI1_WORLD, "SI"},
684 YES, YES, 7000}, 446 {CTRY_SOUTH_AFRICA, FCC3_WORLD, "ZA"},
685 447 {CTRY_SPAIN, ETSI1_WORLD, "ES"},
686 {CTRY_JAPAN22, MKK8_MKKB, "JP", "JAPAN22", YES, NO, NO, YES, YES, 448 {CTRY_SRI_LANKA, FCC3_WORLD, "LK"},
687 YES, YES, 7000}, 449 {CTRY_SWEDEN, ETSI1_WORLD, "SE"},
688 {CTRY_JAPAN23, MKK8_MKKA2, "JP", "JAPAN23", YES, NO, NO, YES, YES, 450 {CTRY_SWITZERLAND, ETSI1_WORLD, "CH"},
689 YES, YES, 7000}, 451 {CTRY_SYRIA, NULL1_WORLD, "SY"},
690 {CTRY_JAPAN24, MKK8_MKKC, "JP", "JAPAN24", YES, NO, NO, YES, YES, 452 {CTRY_TAIWAN, APL3_FCCA, "TW"},
691 YES, YES, 7000}, 453 {CTRY_THAILAND, NULL1_WORLD, "TH"},
692 454 {CTRY_TRINIDAD_Y_TOBAGO, ETSI4_WORLD, "TT"},
693 {CTRY_JAPAN25, MKK3_MKKA, "JP", "JAPAN25", YES, NO, NO, YES, YES, 455 {CTRY_TUNISIA, ETSI3_WORLD, "TN"},
694 YES, YES, 7000}, 456 {CTRY_TURKEY, ETSI3_WORLD, "TR"},
695 {CTRY_JAPAN26, MKK3_MKKA1, "JP", "JAPAN26", YES, NO, NO, YES, YES, 457 {CTRY_UKRAINE, NULL1_WORLD, "UA"},
696 YES, YES, 7000}, 458 {CTRY_UAE, NULL1_WORLD, "AE"},
697 {CTRY_JAPAN27, MKK3_FCCA, "JP", "JAPAN27", YES, NO, NO, YES, YES, 459 {CTRY_UNITED_KINGDOM, ETSI1_WORLD, "GB"},
698 YES, YES, 7000}, 460 {CTRY_UNITED_STATES, FCC3_FCCA, "US"},
699 {CTRY_JAPAN28, MKK4_MKKA1, "JP", "JAPAN28", YES, NO, NO, YES, YES, 461 /* This "PS" is for US public safety actually... to support this we
700 YES, YES, 7000}, 462 * would need to assign new special alpha2 to CRDA db as with the world
701 {CTRY_JAPAN29, MKK4_FCCA, "JP", "JAPAN29", YES, NO, NO, YES, YES, 463 * regdomain and use another alpha2 */
702 YES, YES, 7000}, 464 {CTRY_UNITED_STATES_FCC49, FCC4_FCCA, "PS"},
703 {CTRY_JAPAN30, MKK6_MKKA1, "JP", "JAPAN30", YES, NO, NO, YES, YES, 465 {CTRY_URUGUAY, APL2_WORLD, "UY"},
704 YES, YES, 7000}, 466 {CTRY_UZBEKISTAN, FCC3_FCCA, "UZ"},
705 {CTRY_JAPAN31, MKK6_FCCA, "JP", "JAPAN31", YES, NO, NO, YES, YES, 467 {CTRY_VENEZUELA, APL2_ETSIC, "VE"},
706 YES, YES, 7000}, 468 {CTRY_VIET_NAM, NULL1_WORLD, "VN"},
707 {CTRY_JAPAN32, MKK7_MKKA1, "JP", "JAPAN32", YES, NO, NO, YES, YES, 469 {CTRY_YEMEN, NULL1_WORLD, "YE"},
708 YES, YES, 7000}, 470 {CTRY_ZIMBABWE, NULL1_WORLD, "ZW"},
709 {CTRY_JAPAN33, MKK7_FCCA, "JP", "JAPAN33", YES, NO, NO, YES, YES,
710 YES, YES, 7000},
711 {CTRY_JAPAN34, MKK9_MKKA, "JP", "JAPAN34", YES, NO, NO, YES, YES,
712 YES, YES, 7000},
713 {CTRY_JAPAN35, MKK10_MKKA, "JP", "JAPAN35", YES, NO, NO, YES, YES,
714 YES, YES, 7000},
715 {CTRY_JAPAN36, MKK4_MKKA, "JP", "JAPAN36", YES, NO, NO, YES, YES,
716 YES, YES, 7000},
717 {CTRY_JAPAN37, MKK9_FCCA, "JP", "JAPAN37", YES, NO, NO, YES, YES,
718 YES, YES, 7000},
719 {CTRY_JAPAN38, MKK9_MKKA1, "JP", "JAPAN38", YES, NO, NO, YES, YES,
720 YES, YES, 7000},
721 {CTRY_JAPAN39, MKK9_MKKC, "JP", "JAPAN39", YES, NO, NO, YES, YES,
722 YES, YES, 7000},
723 {CTRY_JAPAN40, MKK9_MKKA2, "JP", "JAPAN40", YES, NO, NO, YES, YES,
724 YES, YES, 7000},
725 {CTRY_JAPAN41, MKK10_FCCA, "JP", "JAPAN41", YES, NO, NO, YES, YES,
726 YES, YES, 7000},
727 {CTRY_JAPAN42, MKK10_MKKA1, "JP", "JAPAN42", YES, NO, NO, YES, YES,
728 YES, YES, 7000},
729 {CTRY_JAPAN43, MKK10_MKKC, "JP", "JAPAN43", YES, NO, NO, YES, YES,
730 YES, YES, 7000},
731 {CTRY_JAPAN44, MKK10_MKKA2, "JP", "JAPAN44", YES, NO, NO, YES, YES,
732 YES, YES, 7000},
733 {CTRY_JAPAN45, MKK11_MKKA, "JP", "JAPAN45", YES, NO, NO, YES, YES,
734 YES, YES, 7000},
735 {CTRY_JAPAN46, MKK11_FCCA, "JP", "JAPAN46", YES, NO, NO, YES, YES,
736 YES, YES, 7000},
737 {CTRY_JAPAN47, MKK11_MKKA1, "JP", "JAPAN47", YES, NO, NO, YES, YES,
738 YES, YES, 7000},
739 {CTRY_JAPAN48, MKK11_MKKC, "JP", "JAPAN48", YES, NO, NO, YES, YES,
740 YES, YES, 7000},
741 {CTRY_JAPAN49, MKK11_MKKA2, "JP", "JAPAN49", YES, NO, NO, YES, YES,
742 YES, YES, 7000},
743 {CTRY_JAPAN50, MKK12_MKKA, "JP", "JAPAN50", YES, NO, NO, YES, YES,
744 YES, YES, 7000},
745 {CTRY_JAPAN51, MKK12_FCCA, "JP", "JAPAN51", YES, NO, NO, YES, YES,
746 YES, YES, 7000},
747 {CTRY_JAPAN52, MKK12_MKKA1, "JP", "JAPAN52", YES, NO, NO, YES, YES,
748 YES, YES, 7000},
749 {CTRY_JAPAN53, MKK12_MKKC, "JP", "JAPAN53", YES, NO, NO, YES, YES,
750 YES, YES, 7000},
751 {CTRY_JAPAN54, MKK12_MKKA2, "JP", "JAPAN54", YES, NO, NO, YES, YES,
752 YES, YES, 7000},
753
754 {CTRY_JAPAN57, MKK13_MKKB, "JP", "JAPAN57", YES, NO, NO, YES, YES,
755 YES, YES, 7000},
756 {CTRY_JAPAN58, MKK14_MKKA1, "JP", "JAPAN58", YES, NO, NO, YES, YES,
757 YES, YES, 7000},
758 {CTRY_JAPAN59, MKK15_MKKA1, "JP", "JAPAN59", YES, NO, NO, YES, YES,
759 YES, YES, 7000},
760
761 {CTRY_JORDAN, ETSI2_WORLD, "JO", "JORDAN", YES, NO, YES, YES, YES,
762 YES, NO, 7000},
763 {CTRY_KAZAKHSTAN, NULL1_WORLD, "KZ", "KAZAKHSTAN", YES, NO, YES,
764 YES, YES, NO, NO, 7000},
765 {CTRY_KOREA_NORTH, APL9_WORLD, "KP", "NORTH KOREA", YES, NO, NO,
766 YES, YES, YES, YES, 7000},
767 {CTRY_KOREA_ROC, APL9_WORLD, "KR", "KOREA REPUBLIC", YES, NO, NO,
768 YES, NO, YES, NO, 7000},
769 {CTRY_KOREA_ROC2, APL2_WORLD, "K2", "KOREA REPUBLIC2", YES, NO, NO,
770 YES, NO, YES, NO, 7000},
771 {CTRY_KOREA_ROC3, APL9_WORLD, "K3", "KOREA REPUBLIC3", YES, NO, NO,
772 YES, NO, YES, NO, 7000},
773 {CTRY_KUWAIT, NULL1_WORLD, "KW", "KUWAIT", YES, NO, YES, YES, YES,
774 NO, NO, 7000},
775 {CTRY_LATVIA, ETSI1_WORLD, "LV", "LATVIA", YES, NO, YES, YES, YES,
776 YES, YES, 7000},
777 {CTRY_LEBANON, NULL1_WORLD, "LB", "LEBANON", YES, NO, YES, YES,
778 YES, NO, NO, 7000},
779 {CTRY_LIECHTENSTEIN, ETSI1_WORLD, "LI", "LIECHTENSTEIN", YES, NO,
780 YES, YES, YES, YES, YES, 7000},
781 {CTRY_LITHUANIA, ETSI1_WORLD, "LT", "LITHUANIA", YES, NO, YES, YES,
782 YES, YES, YES, 7000},
783 {CTRY_LUXEMBOURG, ETSI1_WORLD, "LU", "LUXEMBOURG", YES, NO, YES,
784 YES, YES, YES, YES, 7000},
785 {CTRY_MACAU, FCC2_WORLD, "MO", "MACAU", YES, YES, YES, YES, YES,
786 YES, YES, 7000},
787 {CTRY_MACEDONIA, NULL1_WORLD, "MK", "MACEDONIA", YES, NO, YES, YES,
788 YES, NO, NO, 7000},
789 {CTRY_MALAYSIA, APL8_WORLD, "MY", "MALAYSIA", YES, NO, NO, YES, NO,
790 YES, NO, 7000},
791 {CTRY_MALTA, ETSI1_WORLD, "MT", "MALTA", YES, NO, YES, YES, YES,
792 YES, YES, 7000},
793 {CTRY_MEXICO, FCC1_FCCA, "MX", "MEXICO", YES, YES, YES, YES, YES,
794 YES, YES, 7000},
795 {CTRY_MONACO, ETSI4_WORLD, "MC", "MONACO", YES, YES, YES, YES, YES,
796 YES, YES, 7000},
797 {CTRY_MOROCCO, NULL1_WORLD, "MA", "MOROCCO", YES, NO, YES, YES,
798 YES, NO, NO, 7000},
799 {CTRY_NEPAL, APL1_WORLD, "NP", "NEPAL", YES, NO, YES, YES, YES,
800 YES, YES, 7000},
801 {CTRY_NETHERLANDS, ETSI1_WORLD, "NL", "NETHERLANDS", YES, NO, YES,
802 YES, YES, YES, YES, 7000},
803 {CTRY_NETHERLANDS_ANTILLES, ETSI1_WORLD, "AN",
804 "NETHERLANDS-ANTILLES", YES, NO, YES, YES, YES, YES, YES, 7000},
805 {CTRY_NEW_ZEALAND, FCC2_ETSIC, "NZ", "NEW ZEALAND", YES, NO, YES,
806 YES, YES, YES, NO, 7000},
807 {CTRY_NORWAY, ETSI1_WORLD, "NO", "NORWAY", YES, NO, YES, YES, YES,
808 YES, YES, 7000},
809 {CTRY_OMAN, APL6_WORLD, "OM", "OMAN", YES, NO, YES, YES, YES, YES,
810 NO, 7000},
811 {CTRY_PAKISTAN, NULL1_WORLD, "PK", "PAKISTAN", YES, NO, YES, YES,
812 YES, NO, NO, 7000},
813 {CTRY_PANAMA, FCC1_FCCA, "PA", "PANAMA", YES, YES, YES, YES, YES,
814 YES, YES, 7000},
815 {CTRY_PAPUA_NEW_GUINEA, FCC1_WORLD, "PG", "PAPUA NEW GUINEA", YES,
816 YES, YES, YES, YES, YES, YES, 7000},
817 {CTRY_PERU, APL1_WORLD, "PE", "PERU", YES, NO, YES, YES, YES, YES,
818 NO, 7000},
819 {CTRY_PHILIPPINES, APL1_WORLD, "PH", "PHILIPPINES", YES, YES, YES,
820 YES, YES, YES, YES, 7000},
821 {CTRY_POLAND, ETSI1_WORLD, "PL", "POLAND", YES, NO, YES, YES, YES,
822 YES, YES, 7000},
823 {CTRY_PORTUGAL, ETSI1_WORLD, "PT", "PORTUGAL", YES, NO, YES, YES,
824 YES, YES, YES, 7000},
825 {CTRY_PUERTO_RICO, FCC1_FCCA, "PR", "PUERTO RICO", YES, YES, YES,
826 YES, YES, YES, YES, 7000},
827 {CTRY_QATAR, NULL1_WORLD, "QA", "QATAR", YES, NO, YES, YES, YES,
828 NO, NO, 7000},
829 {CTRY_ROMANIA, NULL1_WORLD, "RO", "ROMANIA", YES, NO, YES, YES,
830 YES, NO, NO, 7000},
831 {CTRY_RUSSIA, NULL1_WORLD, "RU", "RUSSIA", YES, NO, YES, YES, YES,
832 NO, NO, 7000},
833 {CTRY_SAUDI_ARABIA, NULL1_WORLD, "SA", "SAUDI ARABIA", YES, NO,
834 YES, YES, YES, NO, NO, 7000},
835 {CTRY_SERBIA_MONTENEGRO, ETSI1_WORLD, "CS", "SERBIA & MONTENEGRO",
836 YES, NO, YES, YES, YES, YES, YES, 7000},
837 {CTRY_SINGAPORE, APL6_WORLD, "SG", "SINGAPORE", YES, YES, YES, YES,
838 YES, YES, YES, 7000},
839 {CTRY_SLOVAKIA, ETSI1_WORLD, "SK", "SLOVAK REPUBLIC", YES, NO, YES,
840 YES, YES, YES, YES, 7000},
841 {CTRY_SLOVENIA, ETSI1_WORLD, "SI", "SLOVENIA", YES, NO, YES, YES,
842 YES, YES, YES, 7000},
843 {CTRY_SOUTH_AFRICA, FCC3_WORLD, "ZA", "SOUTH AFRICA", YES, NO, YES,
844 YES, YES, YES, NO, 7000},
845 {CTRY_SPAIN, ETSI1_WORLD, "ES", "SPAIN", YES, NO, YES, YES, YES,
846 YES, YES, 7000},
847 {CTRY_SRI_LANKA, FCC3_WORLD, "LK", "SRI LANKA", YES, NO, YES, YES,
848 YES, YES, NO, 7000},
849 {CTRY_SWEDEN, ETSI1_WORLD, "SE", "SWEDEN", YES, NO, YES, YES, YES,
850 YES, YES, 7000},
851 {CTRY_SWITZERLAND, ETSI1_WORLD, "CH", "SWITZERLAND", YES, NO, YES,
852 YES, YES, YES, YES, 7000},
853 {CTRY_SYRIA, NULL1_WORLD, "SY", "SYRIA", YES, NO, YES, YES, YES,
854 NO, NO, 7000},
855 {CTRY_TAIWAN, APL3_FCCA, "TW", "TAIWAN", YES, YES, YES, YES, YES,
856 YES, YES, 7000},
857 {CTRY_THAILAND, NULL1_WORLD, "TH", "THAILAND", YES, NO, YES, YES,
858 YES, NO, NO, 7000},
859 {CTRY_TRINIDAD_Y_TOBAGO, ETSI4_WORLD, "TT", "TRINIDAD & TOBAGO",
860 YES, NO, YES, YES, YES, YES, NO, 7000},
861 {CTRY_TUNISIA, ETSI3_WORLD, "TN", "TUNISIA", YES, NO, YES, YES,
862 YES, YES, NO, 7000},
863 {CTRY_TURKEY, ETSI3_WORLD, "TR", "TURKEY", YES, NO, YES, YES, YES,
864 YES, NO, 7000},
865 {CTRY_UKRAINE, NULL1_WORLD, "UA", "UKRAINE", YES, NO, YES, YES,
866 YES, NO, NO, 7000},
867 {CTRY_UAE, NULL1_WORLD, "AE", "UNITED ARAB EMIRATES", YES, NO, YES,
868 YES, YES, NO, NO, 7000},
869 {CTRY_UNITED_KINGDOM, ETSI1_WORLD, "GB", "UNITED KINGDOM", YES, NO,
870 YES, YES, YES, YES, YES, 7000},
871 {CTRY_UNITED_STATES, FCC3_FCCA, "US", "UNITED STATES", YES, YES,
872 YES, YES, YES, YES, YES, 5825},
873 {CTRY_UNITED_STATES_FCC49, FCC4_FCCA, "PS",
874 "UNITED STATES (PUBLIC SAFETY)", YES, YES, YES, YES, YES, YES,
875 YES, 7000},
876 {CTRY_URUGUAY, APL2_WORLD, "UY", "URUGUAY", YES, NO, YES, YES, YES,
877 YES, NO, 7000},
878 {CTRY_UZBEKISTAN, FCC3_FCCA, "UZ", "UZBEKISTAN", YES, YES, YES,
879 YES, YES, YES, YES, 7000},
880 {CTRY_VENEZUELA, APL2_ETSIC, "VE", "VENEZUELA", YES, NO, YES, YES,
881 YES, YES, NO, 7000},
882 {CTRY_VIET_NAM, NULL1_WORLD, "VN", "VIET NAM", YES, NO, YES, YES,
883 YES, NO, NO, 7000},
884 {CTRY_YEMEN, NULL1_WORLD, "YE", "YEMEN", YES, NO, YES, YES, YES,
885 NO, NO, 7000},
886 {CTRY_ZIMBABWE, NULL1_WORLD, "ZW", "ZIMBABWE", YES, NO, YES, YES,
887 YES, NO, NO, 7000}
888};
889
890enum {
891 NO_DFS = 0x0000000000000000ULL,
892 DFS_FCC3 = 0x0000000000000001ULL,
893 DFS_ETSI = 0x0000000000000002ULL,
894 DFS_MKK4 = 0x0000000000000004ULL,
895};
896
897enum {
898 F1_4915_4925,
899 F1_4935_4945,
900 F1_4920_4980,
901 F1_4942_4987,
902 F1_4945_4985,
903 F1_4950_4980,
904 F1_5035_5040,
905 F1_5040_5080,
906 F1_5055_5055,
907
908 F1_5120_5240,
909
910 F1_5170_5230,
911 F2_5170_5230,
912
913 F1_5180_5240,
914 F2_5180_5240,
915 F3_5180_5240,
916 F4_5180_5240,
917 F5_5180_5240,
918 F6_5180_5240,
919 F7_5180_5240,
920 F8_5180_5240,
921
922 F1_5180_5320,
923
924 F1_5240_5280,
925
926 F1_5260_5280,
927
928 F1_5260_5320,
929 F2_5260_5320,
930 F3_5260_5320,
931 F4_5260_5320,
932 F5_5260_5320,
933 F6_5260_5320,
934
935 F1_5260_5700,
936
937 F1_5280_5320,
938
939 F1_5500_5580,
940
941 F1_5500_5620,
942
943 F1_5500_5700,
944 F2_5500_5700,
945 F3_5500_5700,
946 F4_5500_5700,
947 F5_5500_5700,
948
949 F1_5660_5700,
950
951 F1_5745_5805,
952 F2_5745_5805,
953 F3_5745_5805,
954
955 F1_5745_5825,
956 F2_5745_5825,
957 F3_5745_5825,
958 F4_5745_5825,
959 F5_5745_5825,
960 F6_5745_5825,
961
962 W1_4920_4980,
963 W1_5040_5080,
964 W1_5170_5230,
965 W1_5180_5240,
966 W1_5260_5320,
967 W1_5745_5825,
968 W1_5500_5700,
969 A_DEMO_ALL_CHANNELS
970};
971
972static struct RegDmnFreqBand regDmn5GhzFreq[] = {
973 {4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16},
974 {4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16},
975 {4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7},
976 {4942, 4987, 27, 6, 5, 5, NO_DFS, PSCAN_FCC, 0},
977 {4945, 4985, 30, 6, 10, 5, NO_DFS, PSCAN_FCC, 0},
978 {4950, 4980, 33, 6, 20, 5, NO_DFS, PSCAN_FCC, 0},
979 {5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12},
980 {5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2},
981 {5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12},
982
983 {5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0},
984
985 {5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1},
986 {5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1},
987
988 {5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0},
989 {5180, 5240, 17, 6, 20, 20, NO_DFS, NO_PSCAN, 1},
990 {5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0},
991 {5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0},
992 {5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0},
993 {5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0},
994 {5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK3, 0},
995 {5180, 5240, 23, 6, 20, 20, NO_DFS, NO_PSCAN, 0},
996
997 {5180, 5320, 20, 6, 20, 20, NO_DFS, PSCAN_ETSI, 0},
998
999 {5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0},
1000
1001 {5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI,
1002 PSCAN_FCC | PSCAN_ETSI, 0},
1003
1004 {5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI,
1005 PSCAN_FCC | PSCAN_ETSI, 0},
1006
1007 {5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4,
1008 PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3, 0},
1009
1010
1011 {5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI,
1012 PSCAN_FCC | PSCAN_ETSI, 2},
1013 {5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2},
1014 {5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0},
1015 {5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0},
1016
1017 {5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0},
1018
1019 {5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0},
1020
1021 {5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0},
1022
1023 {5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0},
1024
1025 {5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4},
1026 {5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI,
1027 PSCAN_FCC | PSCAN_ETSI, 0},
1028 {5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI,
1029 PSCAN_FCC | PSCAN_ETSI, 0},
1030 {5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4,
1031 PSCAN_MKK3 | PSCAN_FCC, 0},
1032 {5500, 5700, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0},
1033
1034 {5660, 5700, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0},
1035
1036 {5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0},
1037 {5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0},
1038 {5745, 5805, 30, 6, 20, 20, NO_DFS, PSCAN_ETSI, 0},
1039 {5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0},
1040 {5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0},
1041 {5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 0},
1042 {5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0},
1043 {5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3},
1044 {5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0},
1045
1046
1047 {4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0},
1048 {5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0},
1049 {5170, 5230, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0},
1050 {5180, 5240, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0},
1051 {5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
1052 {5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0},
1053 {5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
1054 {4920, 6100, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0},
1055};
1056
1057enum {
1058 T1_5130_5650,
1059 T1_5150_5670,
1060
1061 T1_5200_5200,
1062 T2_5200_5200,
1063 T3_5200_5200,
1064 T4_5200_5200,
1065 T5_5200_5200,
1066 T6_5200_5200,
1067 T7_5200_5200,
1068 T8_5200_5200,
1069
1070 T1_5200_5280,
1071 T2_5200_5280,
1072 T3_5200_5280,
1073 T4_5200_5280,
1074 T5_5200_5280,
1075 T6_5200_5280,
1076
1077 T1_5200_5240,
1078 T1_5210_5210,
1079 T2_5210_5210,
1080 T3_5210_5210,
1081 T4_5210_5210,
1082 T5_5210_5210,
1083 T6_5210_5210,
1084 T7_5210_5210,
1085 T8_5210_5210,
1086 T9_5210_5210,
1087 T10_5210_5210,
1088 T1_5240_5240,
1089
1090 T1_5210_5250,
1091 T1_5210_5290,
1092 T2_5210_5290,
1093 T3_5210_5290,
1094
1095 T1_5280_5280,
1096 T2_5280_5280,
1097 T1_5290_5290,
1098 T2_5290_5290,
1099 T3_5290_5290,
1100 T1_5250_5290,
1101 T2_5250_5290,
1102 T3_5250_5290,
1103 T4_5250_5290,
1104
1105 T1_5540_5660,
1106 T2_5540_5660,
1107 T3_5540_5660,
1108 T1_5760_5800,
1109 T2_5760_5800,
1110 T3_5760_5800,
1111 T4_5760_5800,
1112 T5_5760_5800,
1113 T6_5760_5800,
1114 T7_5760_5800,
1115
1116 T1_5765_5805,
1117 T2_5765_5805,
1118 T3_5765_5805,
1119 T4_5765_5805,
1120 T5_5765_5805,
1121 T6_5765_5805,
1122 T7_5765_5805,
1123 T8_5765_5805,
1124 T9_5765_5805,
1125
1126 WT1_5210_5250,
1127 WT1_5290_5290,
1128 WT1_5540_5660,
1129 WT1_5760_5800,
1130};
1131
1132enum {
1133 F1_2312_2372,
1134 F2_2312_2372,
1135
1136 F1_2412_2472,
1137 F2_2412_2472,
1138 F3_2412_2472,
1139
1140 F1_2412_2462,
1141 F2_2412_2462,
1142
1143 F1_2432_2442,
1144
1145 F1_2457_2472,
1146
1147 F1_2467_2472,
1148
1149 F1_2484_2484,
1150 F2_2484_2484,
1151
1152 F1_2512_2732,
1153
1154 W1_2312_2372,
1155 W1_2412_2412,
1156 W1_2417_2432,
1157 W1_2437_2442,
1158 W1_2447_2457,
1159 W1_2462_2462,
1160 W1_2467_2467,
1161 W2_2467_2467,
1162 W1_2472_2472,
1163 W2_2472_2472,
1164 W1_2484_2484,
1165 W2_2484_2484,
1166};
1167
1168static struct RegDmnFreqBand regDmn2GhzFreq[] = {
1169 {2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1170 {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1171
1172 {2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1173 {2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},
1174 {2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1175
1176 {2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1177 {2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},
1178
1179 {2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1180
1181 {2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1182
1183 {2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0},
1184
1185 {2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1186 {2484, 2484, 20, 0, 20, 5, NO_DFS,
1187 PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0},
1188
1189 {2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1190
1191 {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1192 {2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1193 {2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1194 {2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1195 {2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1196 {2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1197 {2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
1198 {2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
1199 {2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
1200 {2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
1201 {2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
1202 {2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
1203};
1204
1205enum {
1206 G1_2312_2372,
1207 G2_2312_2372,
1208
1209 G1_2412_2472,
1210 G2_2412_2472,
1211 G3_2412_2472,
1212
1213 G1_2412_2462,
1214 G2_2412_2462,
1215
1216 G1_2432_2442,
1217
1218 G1_2457_2472,
1219
1220 G1_2512_2732,
1221
1222 G1_2467_2472,
1223
1224 WG1_2312_2372,
1225 WG1_2412_2462,
1226 WG1_2467_2472,
1227 WG2_2467_2472,
1228 G_DEMO_ALL_CHANNELS
1229};
1230
1231static struct RegDmnFreqBand regDmn2Ghz11gFreq[] = {
1232 {2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1233 {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1234
1235 {2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1236 {2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0},
1237 {2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1238
1239 {2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1240 {2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0},
1241
1242 {2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1243
1244 {2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1245
1246 {2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1247
1248 {2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0},
1249
1250 {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1251 {2412, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
1252 {2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
1253 {2467, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
1254 {2312, 2732, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
1255};
1256
1257enum {
1258 T1_2312_2372,
1259 T1_2437_2437,
1260 T2_2437_2437,
1261 T3_2437_2437,
1262 T1_2512_2732
1263}; 471};
1264 472
1265static struct regDomain regDomains[] = {
1266
1267 {DEBUG_REG_DMN, FCC, DFS_FCC3, NO_PSCAN, NO_REQ,
1268 BM(A_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1269 -1),
1270 BM(T1_5130_5650, T1_5150_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1271 -1),
1272 BM(T1_5200_5240, T1_5280_5280, T1_5540_5660, T1_5765_5805, -1, -1,
1273 -1, -1, -1, -1, -1, -1),
1274 BM(F1_2312_2372, F1_2412_2472, F1_2484_2484, F1_2512_2732, -1, -1,
1275 -1, -1, -1, -1, -1, -1),
1276 BM(G_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1277 -1),
1278 BM(T1_2312_2372, T1_2437_2437, T1_2512_2732, -1, -1, -1, -1, -1,
1279 -1, -1, -1, -1)},
1280
1281 {APL1, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1282 BM(F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1283 BM(T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1284 BM(T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1285 BMZERO,
1286 BMZERO,
1287 BMZERO},
1288
1289 {APL2, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1290 BM(F1_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1291 BM(T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1292 BM(T2_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1293 BMZERO,
1294 BMZERO,
1295 BMZERO},
1296
1297 {APL3, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1298 BM(F1_5280_5320, F2_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1299 -1),
1300 BM(T1_5290_5290, T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1301 -1),
1302 BM(T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1303 BMZERO,
1304 BMZERO,
1305 BMZERO},
1306
1307 {APL4, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1308 BM(F4_5180_5240, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1309 -1),
1310 BM(T1_5210_5210, T3_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1311 -1),
1312 BM(T1_5200_5200, T3_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1313 -1),
1314 BMZERO,
1315 BMZERO,
1316 BMZERO},
1317
1318 {APL5, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1319 BM(F2_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1320 BM(T4_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1321 BM(T4_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1322 BMZERO,
1323 BMZERO,
1324 BMZERO},
1325
1326 {APL6, ETSI, DFS_ETSI, PSCAN_FCC_T | PSCAN_FCC, NO_REQ,
1327 BM(F4_5180_5240, F2_5260_5320, F3_5745_5825, -1, -1, -1, -1, -1,
1328 -1, -1, -1, -1),
1329 BM(T2_5210_5210, T1_5250_5290, T1_5760_5800, -1, -1, -1, -1, -1,
1330 -1, -1, -1, -1),
1331 BM(T1_5200_5280, T5_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1332 -1),
1333 BMZERO,
1334 BMZERO,
1335 BMZERO},
1336
1337 {APL7, ETSI, DFS_ETSI, PSCAN_ETSI, NO_REQ,
1338 BM(F1_5280_5320, F5_5500_5700, F3_5745_5805, -1, -1, -1, -1, -1,
1339 -1, -1, -1, -1),
1340 BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1341 -1),
1342 BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1343 -1),
1344 BMZERO,
1345 BMZERO,
1346 BMZERO},
1347
1348 {APL8, ETSI, NO_DFS, NO_PSCAN,
1349 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1350 BM(F6_5260_5320, F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1351 -1),
1352 BM(T2_5290_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1353 -1),
1354 BM(T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1355 -1),
1356 BMZERO,
1357 BMZERO,
1358 BMZERO},
1359
1360 {APL9, ETSI, DFS_ETSI, PSCAN_ETSI,
1361 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1362 BM(F1_5180_5320, F1_5500_5620, F3_5745_5805, -1, -1, -1, -1, -1,
1363 -1, -1, -1, -1),
1364 BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1365 -1),
1366 BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1367 -1),
1368 BMZERO,
1369 BMZERO,
1370 BMZERO},
1371
1372 {APL10, ETSI, DFS_ETSI, PSCAN_ETSI,
1373 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1374 BM(F1_5180_5320, F5_5500_5700, F3_5745_5805, -1, -1, -1, -1, -1,
1375 -1, -1, -1, -1),
1376 BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1377 -1),
1378 BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1379 -1),
1380 BMZERO,
1381 BMZERO,
1382 BMZERO},
1383
1384 {ETSI1, ETSI, DFS_ETSI, PSCAN_ETSI,
1385 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1386 BM(F4_5180_5240, F2_5260_5320, F2_5500_5700, -1, -1, -1, -1, -1,
1387 -1, -1, -1, -1),
1388 BM(T1_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1389 BM(T2_5200_5280, T2_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1390 -1),
1391 BMZERO,
1392 BMZERO,
1393 BMZERO},
1394
1395 {ETSI2, ETSI, DFS_ETSI, PSCAN_ETSI,
1396 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1397 BM(F3_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1398 BM(T3_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1399 BM(T2_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1400 BMZERO,
1401 BMZERO,
1402 BMZERO},
1403
1404 {ETSI3, ETSI, DFS_ETSI, PSCAN_ETSI,
1405 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1406 BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1407 -1),
1408 BM(T1_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1409 BM(T2_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1410 BMZERO,
1411 BMZERO,
1412 BMZERO},
1413
1414 {ETSI4, ETSI, DFS_ETSI, PSCAN_ETSI,
1415 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1416 BM(F3_5180_5240, F1_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1417 -1),
1418 BM(T2_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1419 BM(T3_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1420 BMZERO,
1421 BMZERO,
1422 BMZERO},
1423
1424 {ETSI5, ETSI, DFS_ETSI, PSCAN_ETSI,
1425 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1426 BM(F1_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1427 BM(T4_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1428 BM(T3_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1429 BMZERO,
1430 BMZERO,
1431 BMZERO},
1432
1433 {ETSI6, ETSI, DFS_ETSI, PSCAN_ETSI,
1434 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1435 BM(F5_5180_5240, F1_5260_5280, F3_5500_5700, -1, -1, -1, -1, -1,
1436 -1, -1, -1, -1),
1437 BM(T1_5210_5250, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1438 BM(T4_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1439 BMZERO,
1440 BMZERO,
1441 BMZERO},
1442
1443 {FCC1, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1444 BM(F2_5180_5240, F4_5260_5320, F5_5745_5825, -1, -1, -1, -1, -1,
1445 -1, -1, -1, -1),
1446 BM(T6_5210_5210, T2_5250_5290, T6_5760_5800, -1, -1, -1, -1, -1,
1447 -1, -1, -1, -1),
1448 BM(T1_5200_5240, T2_5280_5280, T7_5765_5805, -1, -1, -1, -1, -1,
1449 -1, -1, -1, -1),
1450 BMZERO,
1451 BMZERO,
1452 BMZERO},
1453
1454 {FCC2, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1455 BM(F6_5180_5240, F5_5260_5320, F6_5745_5825, -1, -1, -1, -1, -1,
1456 -1, -1, -1, -1),
1457 BM(T7_5210_5210, T3_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1,
1458 -1, -1, -1, -1),
1459 BM(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805, -1, -1,
1460 -1, -1, -1, -1, -1, -1),
1461 BMZERO,
1462 BMZERO,
1463 BMZERO},
1464
1465 {FCC3, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ,
1466 BM(F2_5180_5240, F3_5260_5320, F1_5500_5700, F5_5745_5825, -1, -1,
1467 -1, -1, -1, -1, -1, -1),
1468 BM(T6_5210_5210, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1469 -1),
1470 BM(T4_5200_5200, T8_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1471 -1),
1472 BMZERO,
1473 BMZERO,
1474 BMZERO},
1475
1476 {FCC4, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ,
1477 BM(F1_4942_4987, F1_4945_4985, F1_4950_4980, -1, -1, -1, -1, -1,
1478 -1, -1, -1, -1),
1479 BM(T8_5210_5210, T4_5250_5290, T7_5760_5800, -1, -1, -1, -1, -1,
1480 -1, -1, -1, -1),
1481 BM(T1_5200_5240, T1_5280_5280, T9_5765_5805, -1, -1, -1, -1, -1,
1482 -1, -1, -1, -1),
1483 BMZERO,
1484 BMZERO,
1485 BMZERO},
1486
1487 {FCC5, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1488 BM(F2_5180_5240, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1489 -1),
1490 BM(T6_5210_5210, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1491 -1),
1492 BM(T8_5200_5200, T7_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1493 -1),
1494 BMZERO,
1495 BMZERO,
1496 BMZERO},
1497
1498 {FCC6, FCC, DFS_FCC3, PSCAN_FCC, NO_REQ,
1499 BM(F8_5180_5240, F5_5260_5320, F1_5500_5580, F1_5660_5700,
1500 F6_5745_5825, -1, -1, -1, -1, -1, -1, -1),
1501 BM(T7_5210_5210, T3_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1,
1502 -1, -1, -1, -1),
1503 BM(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805, -1, -1,
1504 -1, -1, -1, -1, -1, -1),
1505 BMZERO,
1506 BMZERO,
1507 BMZERO},
1508
1509 {MKK1, MKK, NO_DFS, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB,
1510 BM(F1_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1,
1511 -1, -1, -1, -1, -1, -1),
1512 BM(T7_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1513 BM(T5_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1514 BMZERO,
1515 BMZERO,
1516 BMZERO},
1517
1518 {MKK2, MKK, NO_DFS, PSCAN_MKK2, DISALLOW_ADHOC_11A_TURB,
1519 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040,
1520 F1_5055_5055, F1_5040_5080, F1_5170_5230, F4_5180_5240,
1521 F2_5260_5320, F4_5500_5700, -1, -1),
1522 BM(T7_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1523 BM(T5_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1524 BMZERO,
1525 BMZERO,
1526 BMZERO},
1527
1528
1529 {MKK3, MKK, NO_DFS, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1530 BM(F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1531 BM(T9_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1532 BM(T1_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1533 BMZERO,
1534 BMZERO,
1535 BMZERO},
1536
1537
1538 {MKK4, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1539 BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1540 -1),
1541 BM(T10_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1542 BM(T6_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1543 BMZERO,
1544 BMZERO,
1545 BMZERO},
1546
1547
1548 {MKK5, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1549 BM(F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1,
1550 -1, -1, -1, -1),
1551 BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1552 BM(T5_5200_5280, T3_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1553 -1),
1554 BMZERO,
1555 BMZERO,
1556 BMZERO},
1557
1558
1559 {MKK6, MKK, NO_DFS, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB,
1560 BM(F2_5170_5230, F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1561 -1),
1562 BM(T3_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1563 BM(T6_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1564 BMZERO,
1565 BMZERO,
1566 BMZERO},
1567
1568
1569 {MKK7, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3,
1570 DISALLOW_ADHOC_11A_TURB,
1571 BM(F1_5170_5230, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1,
1572 -1, -1, -1, -1),
1573 BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1574 BM(T5_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1575 BMZERO,
1576 BMZERO,
1577 BMZERO},
1578
1579
1580 {MKK8, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3,
1581 DISALLOW_ADHOC_11A_TURB,
1582 BM(F1_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1,
1583 -1, -1, -1, -1, -1, -1),
1584 BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1585 BM(T5_5200_5280, T3_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1586 -1),
1587 BMZERO,
1588 BMZERO,
1589 BMZERO},
1590
1591
1592 {MKK9, MKK, NO_DFS, PSCAN_MKK2 | PSCAN_MKK3,
1593 DISALLOW_ADHOC_11A_TURB,
1594 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040,
1595 F1_5055_5055, F1_5040_5080, F4_5180_5240, -1, -1, -1, -1, -1),
1596 BM(T9_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1597 BM(T1_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1598 BMZERO,
1599 BMZERO,
1600 BMZERO},
1601
1602
1603 {MKK10, MKK, DFS_MKK4, PSCAN_MKK2 | PSCAN_MKK3,
1604 DISALLOW_ADHOC_11A_TURB,
1605 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040,
1606 F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, -1, -1,
1607 -1, -1),
1608 BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1609 BM(T1_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1610 BMZERO,
1611 BMZERO,
1612 BMZERO},
1613
1614
1615 {MKK11, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1616 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040,
1617 F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320,
1618 F4_5500_5700, -1, -1, -1),
1619 BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1620 BM(T1_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1621 BMZERO,
1622 BMZERO,
1623 BMZERO},
1624
1625
1626 {MKK12, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3,
1627 DISALLOW_ADHOC_11A_TURB,
1628 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040,
1629 F1_5055_5055, F1_5040_5080, F1_5170_5230, F4_5180_5240,
1630 F2_5260_5320, F4_5500_5700, -1, -1),
1631 BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1632 BM(T1_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1633 BMZERO,
1634 BMZERO,
1635 BMZERO},
1636
1637
1638 {MKK13, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3,
1639 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1640 BM(F1_5170_5230, F7_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1,
1641 -1, -1, -1, -1, -1, -1),
1642 BMZERO,
1643 BMZERO,
1644 BMZERO,
1645 BMZERO,
1646 BMZERO},
1647
1648
1649 {MKK14, MKK, DFS_MKK4, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB,
1650 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040,
1651 F1_5040_5080, F1_5055_5055, F1_5170_5230, F4_5180_5240, -1, -1,
1652 -1, -1),
1653 BMZERO,
1654 BMZERO,
1655 BMZERO,
1656 BMZERO,
1657 BMZERO},
1658
1659
1660 {MKK15, MKK, DFS_MKK4, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB,
1661 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040,
1662 F1_5040_5080, F1_5055_5055, F1_5170_5230, F4_5180_5240,
1663 F2_5260_5320, -1, -1, -1),
1664 BMZERO,
1665 BMZERO,
1666 BMZERO,
1667 BMZERO,
1668 BMZERO},
1669
1670
1671 {APLD, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ,
1672 BMZERO,
1673 BMZERO,
1674 BMZERO,
1675 BM(F2_2312_2372, F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1676 -1),
1677 BM(G2_2312_2372, G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1678 -1),
1679 BMZERO},
1680
1681 {ETSIA, NO_CTL, NO_DFS, PSCAN_ETSIA,
1682 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1683 BMZERO,
1684 BMZERO,
1685 BMZERO,
1686 BM(F1_2457_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1687 BM(G1_2457_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1688 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1689
1690 {ETSIB, ETSI, NO_DFS, PSCAN_ETSIB,
1691 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1692 BMZERO,
1693 BMZERO,
1694 BMZERO,
1695 BM(F1_2432_2442, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1696 BM(G1_2432_2442, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1697 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1698
1699 {ETSIC, ETSI, NO_DFS, PSCAN_ETSIC,
1700 DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1701 BMZERO,
1702 BMZERO,
1703 BMZERO,
1704 BM(F3_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1705 BM(G3_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1706 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1707
1708 {FCCA, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1709 BMZERO,
1710 BMZERO,
1711 BMZERO,
1712 BM(F1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1713 BM(G1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1714 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1715
1716 {MKKA, MKK, NO_DFS,
1717 PSCAN_MKKA | PSCAN_MKKA_G | PSCAN_MKKA1 | PSCAN_MKKA1_G |
1718 PSCAN_MKKA2 | PSCAN_MKKA2_G, DISALLOW_ADHOC_11A_TURB,
1719 BMZERO,
1720 BMZERO,
1721 BMZERO,
1722 BM(F2_2412_2462, F1_2467_2472, F2_2484_2484, -1, -1, -1, -1, -1,
1723 -1, -1, -1, -1),
1724 BM(G2_2412_2462, G1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1,
1725 -1),
1726 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1727
1728 {MKKC, MKK, NO_DFS, NO_PSCAN, NO_REQ,
1729 BMZERO,
1730 BMZERO,
1731 BMZERO,
1732 BM(F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1733 BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1734 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1735
1736 {WORLD, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
1737 BMZERO,
1738 BMZERO,
1739 BMZERO,
1740 BM(F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1741 BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1742 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1743
1744 {WOR0_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1745 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825,
1746 W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1747 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1,
1748 -1, -1, -1, -1, -1),
1749 BMZERO,
1750 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472,
1751 W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1,
1752 -1, -1),
1753 BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1,
1754 -1, -1),
1755 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1756
1757 {WOR01_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR,
1758 ADHOC_PER_11D,
1759 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825,
1760 W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1761 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1,
1762 -1, -1, -1, -1, -1),
1763 BMZERO,
1764 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432,
1765 W1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1766 BM(WG1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1767 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1768
1769 {WOR02_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR,
1770 ADHOC_PER_11D,
1771 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825,
1772 W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1773 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1,
1774 -1, -1, -1, -1, -1),
1775 BMZERO,
1776 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472,
1777 W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1778 BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1,
1779 -1, -1),
1780 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1781
1782 {EU1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1783 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825,
1784 W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1785 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1,
1786 -1, -1, -1, -1, -1),
1787 BMZERO,
1788 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W2_2472_2472,
1789 W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1),
1790 BM(WG1_2412_2462, WG2_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1,
1791 -1, -1),
1792 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1793
1794 {WOR1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1795 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825,
1796 W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1797 BMZERO,
1798 BMZERO,
1799 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472,
1800 W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1,
1801 -1, -1),
1802 BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1,
1803 -1, -1),
1804 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1805
1806 {WOR2_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1807 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825,
1808 W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1809 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1,
1810 -1, -1, -1, -1, -1),
1811 BMZERO,
1812 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472,
1813 W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1,
1814 -1, -1),
1815 BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1,
1816 -1, -1),
1817 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1818
1819 {WOR3_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1820 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, -1, -1,
1821 -1, -1, -1, -1, -1, -1),
1822 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1,
1823 -1, -1, -1, -1, -1),
1824 BMZERO,
1825 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472,
1826 W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1827 BM(WG1_2412_2462, WG2_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1,
1828 -1, -1),
1829 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1830
1831 {WOR4_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1832 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, -1, -1, -1, -1, -1,
1833 -1, -1, -1, -1),
1834 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1,
1835 -1, -1, -1, -1, -1),
1836 BMZERO,
1837 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432,
1838 W1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1839 BM(WG1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1840 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1841
1842 {WOR5_ETSIC, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1843 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, -1, -1, -1, -1, -1,
1844 -1, -1, -1, -1),
1845 BMZERO,
1846 BMZERO,
1847 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472,
1848 W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1849 BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1,
1850 -1, -1),
1851 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1852
1853 {WOR9_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1854 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1,
1855 -1, -1, -1, -1, -1, -1),
1856 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1,
1857 -1, -1, -1, -1, -1),
1858 BMZERO,
1859 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432,
1860 W1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1861 BM(WG1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1862 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1863
1864 {WORA_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1865 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1,
1866 -1, -1, -1, -1, -1, -1),
1867 BMZERO,
1868 BMZERO,
1869 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472,
1870 W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1871 BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1,
1872 -1, -1),
1873 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1874
1875 {WORB_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1876 BM(W1_5260_5320, W1_5180_5240, W1_5500_5700, -1, -1, -1, -1, -1,
1877 -1, -1, -1, -1),
1878 BMZERO,
1879 BMZERO,
1880 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472,
1881 W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1882 BM(WG1_2412_2462, WG1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1,
1883 -1, -1),
1884 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1885
1886 {NULL1, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ,
1887 BMZERO,
1888 BMZERO,
1889 BMZERO,
1890 BMZERO,
1891 BMZERO,
1892 BMZERO}
1893};
1894
1895static const struct cmode modes[] = {
1896 {ATH9K_MODE_11A, CHANNEL_A},
1897 {ATH9K_MODE_11B, CHANNEL_B},
1898 {ATH9K_MODE_11G, CHANNEL_G},
1899 {ATH9K_MODE_11NG_HT20, CHANNEL_G_HT20},
1900 {ATH9K_MODE_11NG_HT40PLUS, CHANNEL_G_HT40PLUS},
1901 {ATH9K_MODE_11NG_HT40MINUS, CHANNEL_G_HT40MINUS},
1902 {ATH9K_MODE_11NA_HT20, CHANNEL_A_HT20},
1903 {ATH9K_MODE_11NA_HT40PLUS, CHANNEL_A_HT40PLUS},
1904 {ATH9K_MODE_11NA_HT40MINUS, CHANNEL_A_HT40MINUS},
1905};
1906
1907static struct japan_bandcheck j_bandcheck[] = {
1908 {F1_5170_5230, AR_EEPROM_EEREGCAP_EN_KK_U1_ODD},
1909 {F4_5180_5240, AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN},
1910 {F2_5260_5320, AR_EEPROM_EEREGCAP_EN_KK_U2},
1911 {F4_5500_5700, AR_EEPROM_EEREGCAP_EN_KK_MIDBAND}
1912};
1913
1914
1915#endif 473#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 17:56:39 -0500