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authorBrian Norris <computersforpeace@gmail.com>2013-03-13 12:51:31 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2013-03-14 08:48:54 -0400
commit5bc7c33ca93a285dcfe7b7fd64970f6314440ad1 (patch)
tree0ce80c4e6559c939c2eaf86c76950b177c4c157a
parent91d542f4dcc231749c36114ed8e26bb27d4521e4 (diff)
mtd: nand: reintroduce NAND_NO_READRDY as NAND_NEED_READRDY
This partially reverts commit 1696e6bc2ae83734e64e206ac99766ea19e9a14e ("mtd: nand: kill NAND_NO_READRDY"). In that patch I overlooked a few things. The original documentation for NAND_NO_READRDY included "True for all large page devices, as they do not support autoincrement." I was conflating "not support autoincrement" with the NAND_NO_AUTOINCR option, which was in fact doing nothing. So, when I dropped NAND_NO_AUTOINCR, I concluded that I then could harmlessly drop NAND_NO_READRDY. But of course the fact the NAND_NO_AUTOINCR was doing nothing didn't mean NAND_NO_READRDY was doing nothing... So, NAND_NO_READRDY is re-introduced as NAND_NEED_READRDY and applied only to those few remaining small-page NAND which needed it in the first place. Cc: stable@kernel.org [3.5+] Reported-by: Alexander Shiyan <shc_work@mail.ru> Tested-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat
-rw-r--r--drivers/mtd/nand/nand_base.c16
-rw-r--r--drivers/mtd/nand/nand_ids.c80
-rw-r--r--include/linux/mtd/nand.h7
3 files changed, 64 insertions, 39 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 43214151b882..42c63927609d 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1523,6 +1523,14 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1523 oobreadlen -= toread; 1523 oobreadlen -= toread;
1524 } 1524 }
1525 } 1525 }
1526
1527 if (chip->options & NAND_NEED_READRDY) {
1528 /* Apply delay or wait for ready/busy pin */
1529 if (!chip->dev_ready)
1530 udelay(chip->chip_delay);
1531 else
1532 nand_wait_ready(mtd);
1533 }
1526 } else { 1534 } else {
1527 memcpy(buf, chip->buffers->databuf + col, bytes); 1535 memcpy(buf, chip->buffers->databuf + col, bytes);
1528 buf += bytes; 1536 buf += bytes;
@@ -1787,6 +1795,14 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1787 len = min(len, readlen); 1795 len = min(len, readlen);
1788 buf = nand_transfer_oob(chip, buf, ops, len); 1796 buf = nand_transfer_oob(chip, buf, ops, len);
1789 1797
1798 if (chip->options & NAND_NEED_READRDY) {
1799 /* Apply delay or wait for ready/busy pin */
1800 if (!chip->dev_ready)
1801 udelay(chip->chip_delay);
1802 else
1803 nand_wait_ready(mtd);
1804 }
1805
1790 readlen -= len; 1806 readlen -= len;
1791 if (!readlen) 1807 if (!readlen)
1792 break; 1808 break;
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index e3aa2748a6e7..9c612388e5de 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -22,49 +22,51 @@
22* 512 512 Byte page size 22* 512 512 Byte page size
23*/ 23*/
24struct nand_flash_dev nand_flash_ids[] = { 24struct nand_flash_dev nand_flash_ids[] = {
25#define SP_OPTIONS NAND_NEED_READRDY
26#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)
25 27
26#ifdef CONFIG_MTD_NAND_MUSEUM_IDS 28#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
27 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, 29 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, SP_OPTIONS},
28 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0}, 30 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, SP_OPTIONS},
29 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0}, 31 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, SP_OPTIONS},
30 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0}, 32 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, SP_OPTIONS},
31 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, 33 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, SP_OPTIONS},
32 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0}, 34 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, SP_OPTIONS},
33 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0}, 35 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, SP_OPTIONS},
34 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0}, 36 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, SP_OPTIONS},
35 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0}, 37 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, SP_OPTIONS},
36 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0}, 38 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, SP_OPTIONS},
37 39
38 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0}, 40 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, SP_OPTIONS},
39 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0}, 41 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, SP_OPTIONS},
40 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16}, 42 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, SP_OPTIONS16},
41 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16}, 43 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, SP_OPTIONS16},
42#endif 44#endif
43 45
44 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0}, 46 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, SP_OPTIONS},
45 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0}, 47 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, SP_OPTIONS},
46 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16}, 48 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, SP_OPTIONS16},
47 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16}, 49 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, SP_OPTIONS16},
48 50
49 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0}, 51 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, SP_OPTIONS},
50 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0}, 52 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, SP_OPTIONS},
51 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16}, 53 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, SP_OPTIONS16},
52 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16}, 54 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, SP_OPTIONS16},
53 55
54 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0}, 56 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, SP_OPTIONS},
55 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0}, 57 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, SP_OPTIONS},
56 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16}, 58 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, SP_OPTIONS16},
57 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16}, 59 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, SP_OPTIONS16},
58 60
59 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0}, 61 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, SP_OPTIONS},
60 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0}, 62 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, SP_OPTIONS},
61 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0}, 63 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, SP_OPTIONS},
62 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16}, 64 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, SP_OPTIONS16},
63 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16}, 65 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, SP_OPTIONS16},
64 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16}, 66 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, SP_OPTIONS16},
65 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16}, 67 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, SP_OPTIONS16},
66 68
67 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0}, 69 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, SP_OPTIONS},
68 70
69 /* 71 /*
70 * These are the new chips with large page size. The pagesize and the 72 * These are the new chips with large page size. The pagesize and the
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 7ccb3c59ed60..ef52d9c91459 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -187,6 +187,13 @@ typedef enum {
187 * This happens with the Renesas AG-AND chips, possibly others. 187 * This happens with the Renesas AG-AND chips, possibly others.
188 */ 188 */
189#define BBT_AUTO_REFRESH 0x00000080 189#define BBT_AUTO_REFRESH 0x00000080
190/*
191 * Chip requires ready check on read (for auto-incremented sequential read).
192 * True only for small page devices; large page devices do not support
193 * autoincrement.
194 */
195#define NAND_NEED_READRDY 0x00000100
196
190/* Chip does not allow subpage writes */ 197/* Chip does not allow subpage writes */
191#define NAND_NO_SUBPAGE_WRITE 0x00000200 198#define NAND_NO_SUBPAGE_WRITE 0x00000200
192 199
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-24 20:34:47 -0400