aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJingoo Han <jg1.han@samsung.com>2013-12-26 19:30:25 -0500
committerBjorn Helgaas <bhelgaas@google.com>2014-01-02 16:47:22 -0500
commit58275f2f0a6acd750b0acdc62d6457fb3e0f264e (patch)
treede73e1a3574887539a40df4623b1f79fb484c9af
parentfce8591f73c6a30c231f220d1092362aae0b985c (diff)
PCI: designware: Fix indent code style
Fix indent code style and replace 'MSI interrupt controller' of comment with 'MSI controller' to fix the following checkpatch issues: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line WARNING: line over 80 characters Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/pci/host/pcie-designware.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 4a08d30548ce..17ce88f79d2b 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -213,14 +213,14 @@ static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
213} 213}
214 214
215static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, 215static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
216 unsigned int nvec, unsigned int pos) 216 unsigned int nvec, unsigned int pos)
217{ 217{
218 unsigned int i, res, bit, val; 218 unsigned int i, res, bit, val;
219 219
220 for (i = 0; i < nvec; i++) { 220 for (i = 0; i < nvec; i++) {
221 irq_set_msi_desc_off(irq_base, i, NULL); 221 irq_set_msi_desc_off(irq_base, i, NULL);
222 clear_bit(pos + i, pp->msi_irq_in_use); 222 clear_bit(pos + i, pp->msi_irq_in_use);
223 /* Disable corresponding interrupt on MSI interrupt controller */ 223 /* Disable corresponding interrupt on MSI controller */
224 res = ((pos + i) / 32) * 12; 224 res = ((pos + i) / 32) * 12;
225 bit = (pos + i) % 32; 225 bit = (pos + i) % 32;
226 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); 226 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);