Merge branch 'late/kirkwood' into late/soc

Merge in the late Kirkwood branch with the OMAP late branch for upstream
submission.

Final contents described in shared tag.

Fixup remove/change conflicts in arch/arm/mach-omap2/devices.c and
drivers/spi/spi-omap2-mcspi.c.

Signed-off-by: Olof Johansson <olof@lixom.net>

1353 files changed, 29820 insertions, 31269 deletions

diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
new file mode 100644
index 000000000000..8f08a86e03b7
--- /dev/null
+++ b/Documentation/arm/Marvell/README
@@ -0,0 +1,232 @@
+ARM Marvell SoCs
+================
+
+This document lists all the ARM Marvell SoCs that are currently
+supported in mainline by the Linux kernel. As the Marvell families of
+SoCs are large and complex, it is hard to understand where the support
+for a particular SoC is available in the Linux kernel. This document
+tries to help in understanding where those SoCs are supported, and to
+match them with their corresponding public datasheet, when available.
+
+Orion family
+------------
+
+  Flavors:
+        88F5082
+        88F5181
+        88F5181L
+        88F5182
+               Datasheet               : http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
+               Programmer's User Guide : http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensource-manual.pdf
+               User Manual             : http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
+        88F5281
+               Datasheet               : http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sheet.pdf
+        88F6183
+  Core: Feroceon ARMv5 compatible
+  Linux kernel mach directory: arch/arm/mach-orion5x
+  Linux kernel plat directory: arch/arm/plat-orion
+
+Kirkwood family
+---------------
+
+  Flavors:
+        88F6282 a.k.a Armada 300
+                Product Brief  : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
+        88F6283 a.k.a Armada 310
+                Product Brief  : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
+        88F6190
+                Product Brief  : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6190-003_WEB.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F619x_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+        88F6192
+                Product Brief  : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6192-003_ver1.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F619x_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+        88F6182
+        88F6180
+                Product Brief  : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6180-003_ver1.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+        88F6281
+                Product Brief  : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6281-004_ver1.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+  Homepage: http://www.marvell.com/embedded-processors/kirkwood/
+  Core: Feroceon ARMv5 compatible
+  Linux kernel mach directory: arch/arm/mach-kirkwood
+  Linux kernel plat directory: arch/arm/plat-orion
+
+Discovery family
+----------------
+
+  Flavors:
+        MV78100
+                Product Brief  : http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV78100-003_WEB.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV78100_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
+        MV78200
+                Product Brief  : http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV78200-002_WEB.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV78200_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
+        MV76100
+                Not supported by the Linux kernel.
+
+  Core: Feroceon ARMv5 compatible
+
+  Linux kernel mach directory: arch/arm/mach-mv78xx0
+  Linux kernel plat directory: arch/arm/plat-orion
+
+EBU Armada family
+-----------------
+
+  Armada 370 Flavors:
+        88F6710
+        88F6707
+        88F6W11
+
+  Armada XP Flavors:
+        MV78230
+        MV78260
+        MV78460
+
+  Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
+  No public datasheet available.
+
+  Core: Sheeva ARMv7 compatible
+
+  Linux kernel mach directory: arch/arm/mach-mvebu
+  Linux kernel plat directory: none
+
+Avanta family
+-------------
+
+  Flavors:
+       88F6510
+       88F6530P
+       88F6550
+       88F6560
+  Homepage     : http://www.marvell.com/broadband/
+  Product Brief: http://www.marvell.com/broadband/assets/Marvell_Avanta_88F6510_305_060-001_product_brief.pdf
+  No public datasheet available.
+
+  Core: ARMv5 compatible
+
+  Linux kernel mach directory: no code in mainline yet, planned for the future
+  Linux kernel plat directory: no code in mainline yet, planned for the future
+
+Dove family (application processor)
+-----------------------------------
+
+  Flavors:
+        88AP510 a.k.a Armada 510
+                Product Brief   : http://www.marvell.com/application-processors/armada-500/assets/Marvell_Armada510_SoC.pdf
+                Hardware Spec   : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Hardware-Spec.pdf
+                Functional Spec : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Functional-Spec.pdf
+  Homepage: http://www.marvell.com/application-processors/armada-500/
+  Core: ARMv7 compatible
+  Directory: arch/arm/mach-dove
+
+PXA 2xx/3xx/93x/95x family
+--------------------------
+
+  Flavors:
+        PXA21x, PXA25x, PXA26x
+             Application processor only
+             Core: ARMv5 XScale core
+        PXA270, PXA271, PXA272
+             Product Brief         : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_pb.pdf
+             Design guide          : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_design_guide.pdf
+             Developers manual     : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_dev_man.pdf
+             Specification         : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_emts.pdf
+             Specification update  : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf
+             Application processor only
+             Core: ARMv5 XScale core
+        PXA300, PXA310, PXA320
+             PXA 300 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA300_PB_R4.pdf
+             PXA 310 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA310_PB_R4.pdf
+             PXA 320 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA320_PB_R4.pdf
+             Design guide          : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Design_Guide.pdf
+             Developers manual     : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Developers_Manual.zip
+             Specifications        : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_EMTS.pdf
+             Specification Update  : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Spec_Update.zip
+             Reference Manual      : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_TavorP_BootROM_Ref_Manual.pdf
+             Application processor only
+             Core: ARMv5 XScale core
+        PXA930, PXA935
+             Application processor with Communication processor
+             Core: ARMv5 XScale core
+        PXA955
+             Application processor with Communication processor
+             Core: ARMv7 compatible Sheeva PJ4 core
+
+   Comments:
+
+    * This line of SoCs originates from the XScale family developed by
+      Intel and acquired by Marvell in ~2006. The PXA21x, PXA25x,
+      PXA26x, PXA27x, PXA3xx and PXA93x were developed by Intel, while
+      the later PXA95x were developed by Marvell.
+
+    * Due to their XScale origin, these SoCs have virtually nothing in
+      common with the other (Kirkwood, Dove, etc.) families of Marvell
+      SoCs, except with the MMP/MMP2 family of SoCs.
+
+   Linux kernel mach directory: arch/arm/mach-pxa
+   Linux kernel plat directory: arch/arm/plat-pxa
+
+MMP/MMP2 family (communication processor)
+-----------------------------------------
+
+   Flavors:
+        PXA168, a.k.a Armada 168
+             Homepage             : http://www.marvell.com/application-processors/armada-100/armada-168.jsp
+             Product brief        : http://www.marvell.com/application-processors/armada-100/assets/pxa_168_pb.pdf
+             Hardware manual      : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_datasheet.pdf
+             Software manual      : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_software_manual.pdf
+             Specification update : http://www.marvell.com/application-processors/armada-100/assets/ARMADA16x_Spec_update.pdf
+             Boot ROM manual      : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_ref_manual.pdf
+             App node package     : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_app_note_package.pdf
+             Application processor only
+             Core: ARMv5 compatible Marvell PJ1 (Mohawk)
+        PXA910
+             Homepage             : http://www.marvell.com/communication-processors/pxa910/
+             Product Brief        : http://www.marvell.com/communication-processors/pxa910/assets/Marvell_PXA910_Platform-001_PB_final.pdf
+             Application processor with Communication processor
+             Core: ARMv5 compatible Marvell PJ1 (Mohawk)
+        MMP2, a.k.a Armada 610
+             Product Brief        : http://www.marvell.com/application-processors/armada-600/assets/armada610_pb.pdf
+             Application processor only
+             Core: ARMv7 compatible Sheeva PJ4 core
+
+   Comments:
+
+    * This line of SoCs originates from the XScale family developed by
+      Intel and acquired by Marvell in ~2006. All the processors of
+      this MMP/MMP2 family were developed by Marvell.
+
+    * Due to their XScale origin, these SoCs have virtually nothing in
+      common with the other (Kirkwood, Dove, etc.) families of Marvell
+      SoCs, except with the PXA family of SoCs listed above.
+
+   Linux kernel mach directory: arch/arm/mach-mmp
+   Linux kernel plat directory: arch/arm/plat-pxa
+
+Long-term plans
+---------------
+
+ * Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ and
+   mach-kirkwood/ into the mach-mvebu/ to support all SoCs from the
+   Marvell EBU (Engineering Business Unit) in a single mach-<foo>
+   directory. The plat-orion/ would therefore disappear.
+
+ * Unify the mach-mmp/ and mach-pxa/ into the same mach-pxa
+   directory. The plat-pxa/ would therefore disappear.
+
+Credits
+-------
+
+ Maen Suleiman <maen@marvell.com>
+ Lior Amsalem <alior@marvell.com>
+ Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ Andrew Lunn <andrew@lunn.ch>
+ Nicolas Pitre <nico@fluxnic.net>
+ Eric Miao <eric.y.miao@gmail.com>
diff --git a/Documentation/arm/Samsung-S3C24XX/GPIO.txt b/Documentation/arm/Samsung-S3C24XX/GPIO.txt
index 816d6071669e..8b46c79679c4 100644
--- a/Documentation/arm/Samsung-S3C24XX/GPIO.txt
+++ b/Documentation/arm/Samsung-S3C24XX/GPIO.txt
@@ -1,4 +1,4 @@
-                        S3C2410 GPIO Control
+                        S3C24XX GPIO Control
                         ====================
 
 Introduction
@@ -12,7 +12,7 @@ Introduction
   of the s3c2410 GPIO system, please read the Samsung provided
   data-sheet/users manual to find out the complete list.
 
-  See Documentation/arm/Samsung/GPIO.txt for the core implemetation.
+  See Documentation/arm/Samsung/GPIO.txt for the core implementation.
 
 
 GPIOLIB
@@ -41,8 +41,8 @@ GPIOLIB
 GPIOLIB conversion
 ------------------
 
-If you need to convert your board or driver to use gpiolib from the exiting
-s3c2410 api, then here are some notes on the process.
+If you need to convert your board or driver to use gpiolib from the phased
+out s3c2410 API, then here are some notes on the process.
 
 1) If your board is exclusively using an GPIO, say to control peripheral
    power, then it will require to claim the gpio with gpio_request() before
@@ -55,7 +55,7 @@ s3c2410 api, then here are some notes on the process.
    as they have the same arguments, and can either take the pin specific
    values, or the more generic special-function-number arguments.
 
-3) s3c2410_gpio_pullup() changs have the problem that whilst the 
+3) s3c2410_gpio_pullup() changes have the problem that whilst the
    s3c2410_gpio_pullup(x, 1) can be easily translated to the
    s3c_gpio_setpull(x, S3C_GPIO_PULL_NONE), the s3c2410_gpio_pullup(x, 0)
    are not so easy.
@@ -74,7 +74,7 @@ s3c2410 api, then here are some notes on the process.
    when using gpio_get_value() on an output pin (s3c2410_gpio_getpin
    would return the value the pin is supposed to be outputting).
 
-6) s3c2410_gpio_getirq() should be directly replacable with the
+6) s3c2410_gpio_getirq() should be directly replaceable with the
    gpio_to_irq() call.
 
 The s3c2410_gpio and gpio_ calls have always operated on the same gpio
@@ -105,7 +105,7 @@ PIN Numbers
 -----------
 
   Each pin has an unique number associated with it in regs-gpio.h,
-  eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
+  e.g. S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
   the GPIO functions which pin is to be used.
 
   With the conversion to gpiolib, there is no longer a direct conversion
@@ -120,31 +120,27 @@ Configuring a pin
   The following function allows the configuration of a given pin to
   be changed.
 
-    void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
+    void s3c_gpio_cfgpin(unsigned int pin, unsigned int function);
 
-  Eg:
+  e.g.:
 
-     s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
-     s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
+     s3c_gpio_cfgpin(S3C2410_GPA(0), S3C_GPIO_SFN(1));
+     s3c_gpio_cfgpin(S3C2410_GPE(8), S3C_GPIO_SFN(2));
 
    which would turn GPA(0) into the lowest Address line A0, and set
    GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line.
 
-   The s3c_gpio_cfgpin() call is a functional replacement for this call.
-
 
 Reading the current configuration
 ---------------------------------
 
-  The current configuration of a pin can be read by using:
+  The current configuration of a pin can be read by using standard
+  gpiolib function:
 
-  s3c2410_gpio_getcfg(unsigned int pin);
+  s3c_gpio_getcfg(unsigned int pin);
 
   The return value will be from the same set of values which can be
-  passed to s3c2410_gpio_cfgpin().
-
-  The s3c_gpio_getcfg() call should be a functional replacement for
-  this call.
+  passed to s3c_gpio_cfgpin().
 
 
 Configuring a pull-up resistor
@@ -154,61 +150,33 @@ Configuring a pull-up resistor
   pull-up resistors enabled. This can be configured by the following
   function:
 
-    void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-
-  Where the to value is zero to set the pull-up off, and 1 to enable
-  the specified pull-up. Any other values are currently undefined.
-
-  The s3c_gpio_setpull() offers similar functionality, but with the
-  ability to encode whether the pull is up or down. Currently there
-  is no 'just on' state, so up or down must be selected.
-
-
-Getting the state of a PIN
---------------------------
-
-  The state of a pin can be read by using the function:
-
-    unsigned int s3c2410_gpio_getpin(unsigned int pin);
+    void s3c_gpio_setpull(unsigned int pin, unsigned int to);
 
-  This will return either zero or non-zero. Do not count on this
-  function returning 1 if the pin is set.
+  Where the to value is S3C_GPIO_PULL_NONE to set the pull-up off,
+  and S3C_GPIO_PULL_UP to enable the specified pull-up. Any other
+  values are currently undefined.
 
-  This call is now implemented by the relevant gpiolib calls, convert
-  your board or driver to use gpiolib.
-
-
-Setting the state of a PIN
---------------------------
-
-  The value an pin is outputing can be modified by using the following:
 
-    void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
+Getting and setting the state of a PIN
+--------------------------------------
 
-  Which sets the given pin to the value. Use 0 to write 0, and 1 to
-  set the output to 1.
-
-  This call is now implemented by the relevant gpiolib calls, convert
+  These calls are now implemented by the relevant gpiolib calls, convert
   your board or driver to use gpiolib.
 
 
 Getting the IRQ number associated with a PIN
 --------------------------------------------
 
-  The following function can map the given pin number to an IRQ
+  A standard gpiolib function can map the given pin number to an IRQ
   number to pass to the IRQ system.
 
-   int s3c2410_gpio_getirq(unsigned int pin);
+   int gpio_to_irq(unsigned int pin);
 
   Note, not all pins have an IRQ.
 
-  This call is now implemented by the relevant gpiolib calls, convert
-  your board or driver to use gpiolib.
-
 
-Authour
+Author
 -------
 
-
 Ben Dooks, 03 October 2004
 Copyright 2004 Ben Dooks, Simtec Electronics
diff --git a/Documentation/arm/Samsung/GPIO.txt b/Documentation/arm/Samsung/GPIO.txt
index 513f2562c1a3..795adfd88081 100644
--- a/Documentation/arm/Samsung/GPIO.txt
+++ b/Documentation/arm/Samsung/GPIO.txt
@@ -5,14 +5,14 @@ Introduction
 ------------
 
 This outlines the Samsung GPIO implementation and the architecture
-specific calls provided alongisde the drivers/gpio core.
+specific calls provided alongside the drivers/gpio core.
 
 
 S3C24XX (Legacy)
 ----------------
 
 See Documentation/arm/Samsung-S3C24XX/GPIO.txt for more information
-about these devices. Their implementation is being brought into line
+about these devices. Their implementation has been brought into line
 with the core samsung implementation described in this document.
 
 
@@ -29,7 +29,7 @@ GPIO numbering is synchronised between the Samsung and gpiolib system.
 PIN configuration
 -----------------
 
-Pin configuration is specific to the Samsung architecutre, with each SoC
+Pin configuration is specific to the Samsung architecture, with each SoC
 registering the necessary information for the core gpio configuration
 implementation to configure pins as necessary.
 
@@ -38,5 +38,3 @@ driver or machine to change gpio configuration.
 
 See arch/arm/plat-samsung/include/plat/gpio-cfg.h for more information
 on these functions.
-
-
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt
index 208a2d465b92..4bfb9ffbdbc1 100644
--- a/Documentation/arm/memory.txt
+++ b/Documentation/arm/memory.txt
@@ -51,6 +51,9 @@ ffc00000	ffefffff	DMA memory mapping region.  Memory returned
 ff000000        ffbfffff        Reserved for future expansion of DMA
                                 mapping region.
 
+fee00000        feffffff        Mapping of PCI I/O space. This is a static
+                                mapping within the vmalloc space.
+
 VMALLOC_START   VMALLOC_END-1   vmalloc() / ioremap() space.
                                 Memory returned by vmalloc/ioremap will
                                 be dynamically placed in this region.
diff --git a/Documentation/devicetree/bindings/arm/bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm2835.txt
new file mode 100644
index 000000000000..ac683480c486
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm2835.txt
@@ -0,0 +1,8 @@
+Broadcom BCM2835 device tree bindings
+-------------------------------------------
+
+Boards with the BCM2835 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "brcm,bcm2835";
diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
new file mode 100644
index 000000000000..31af1cbb60bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
@@ -0,0 +1,17 @@
+* Marvell Tauros2 Cache
+
+Required properties:
+- compatible : Should be "marvell,tauros2-cache".
+- marvell,tauros2-cache-features : Specify the features supported for the
+  tauros2 cache.
+  The features including
+    CACHE_TAUROS2_PREFETCH_ON       (1 << 0)
+    CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)
+  The definition can be found at
+  arch/arm/include/asm/hardware/cache-tauros2.h
+
+Example:
+        L2: l2-cache {
+                compatible = "marvell,tauros2-cache";
+                marvell,tauros2-cache-features = <0x3>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt
new file mode 100644
index 000000000000..8c5907b9cae8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/timer.txt
@@ -0,0 +1,38 @@
+* MSM Timer
+
+Properties:
+
+- compatible : Should at least contain "qcom,msm-timer". More specific
+  properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
+  purpose timer and a debug timer respectively.
+
+- interrupts : Interrupt indicating a match event.
+
+- reg : Specifies the base address of the timer registers. The second region
+  specifies an optional register used to configure the clock divider.
+
+- clock-frequency : The frequency of the timer in Hz.
+
+Optional:
+
+- cpu-offset : per-cpu offset used when the timer is accessed without the
+  CPU remapping facilities. The offset is cpu-offset * cpu-nr.
+
+Example:
+
+       timer@200a004 {
+               compatible = "qcom,msm-gpt", "qcom,msm-timer";
+               interrupts = <1 2 0x301>;
+               reg = <0x0200a004 0x10>;
+               clock-frequency = <32768>;
+               cpu-offset = <0x40000>;
+       };
+
+       timer@200a024 {
+               compatible = "qcom,msm-dgt", "qcom,msm-timer";
+               interrupts = <1 3 0x301>;
+               reg = <0x0200a024 0x10>,
+                     <0x0200a034 0x4>;
+               clock-frequency = <6750000>;
+               cpu-offset = <0x40000>;
+       };
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index ccdd0e53451f..d0051a750587 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -36,6 +36,9 @@ Boards:
 - OMAP3 BeagleBoard : Low cost community board
   compatible = "ti,omap3-beagle", "ti,omap3"
 
+- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
+  compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
+
 - OMAP4 SDP : Software Developement Board
   compatible = "ti,omap4-sdp", "ti,omap4430"
 
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 1c044eb320cc..343781b9f246 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -7,8 +7,12 @@ representation in the device tree should be done as under:-
 Required properties:
 
 - compatible : should be one of
+        "arm,cortex-a15-pmu"
         "arm,cortex-a9-pmu"
         "arm,cortex-a8-pmu"
+        "arm,cortex-a7-pmu"
+        "arm,cortex-a5-pmu"
+        "arm,arm11mpcore-pmu"
         "arm,arm1176-pmu"
         "arm,arm1136-pmu"
 - interrupts : 1 combined interrupt or 1 per core.
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
new file mode 100644
index 000000000000..a0b867ef8d96
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -0,0 +1,76 @@
+* Clock bindings for Freescale i.MX23
+
+Required properties:
+- compatible: Should be "fsl,imx23-clkctrl"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX23
+clocks and IDs.
+
+        Clock           ID
+        ------------------
+        ref_xtal        0
+        pll             1
+        ref_cpu         2
+        ref_emi         3
+        ref_pix         4
+        ref_io          5
+        saif_sel        6
+        lcdif_sel       7
+        gpmi_sel        8
+        ssp_sel         9
+        emi_sel         10
+        cpu             11
+        etm_sel         12
+        cpu_pll         13
+        cpu_xtal        14
+        hbus            15
+        xbus            16
+        lcdif_div       17
+        ssp_div         18
+        gpmi_div        19
+        emi_pll         20
+        emi_xtal        21
+        etm_div         22
+        saif_div        23
+        clk32k_div      24
+        rtc             25
+        adc             26
+        spdif_div       27
+        clk32k          28
+        dri             29
+        pwm             30
+        filt            31
+        uart            32
+        ssp             33
+        gpmi            34
+        spdif           35
+        emi             36
+        saif            37
+        lcdif           38
+        etm             39
+        usb             40
+        usb_pwr         41
+
+Examples:
+
+clks: clkctrl@80040000 {
+        compatible = "fsl,imx23-clkctrl";
+        reg = <0x80040000 0x2000>;
+        #clock-cells = <1>;
+        clock-output-names =
+                ...
+                "uart",         /* 32 */
+                ...
+                "end_of_list";
+};
+
+auart0: serial@8006c000 {
+        compatible = "fsl,imx23-auart";
+        reg = <0x8006c000 0x2000>;
+        interrupts = <24 25 23>;
+        clocks = <&clks 32>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt
new file mode 100644
index 000000000000..aa2af2866fe8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx28-clock.txt
@@ -0,0 +1,99 @@
+* Clock bindings for Freescale i.MX28
+
+Required properties:
+- compatible: Should be "fsl,imx28-clkctrl"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX28
+clocks and IDs.
+
+        Clock           ID
+        ------------------
+        ref_xtal        0
+        pll0            1
+        pll1            2
+        pll2            3
+        ref_cpu         4
+        ref_emi         5
+        ref_io0         6
+        ref_io1         7
+        ref_pix         8
+        ref_hsadc       9
+        ref_gpmi        10
+        saif0_sel       11
+        saif1_sel       12
+        gpmi_sel        13
+        ssp0_sel        14
+        ssp1_sel        15
+        ssp2_sel        16
+        ssp3_sel        17
+        emi_sel         18
+        etm_sel         19
+        lcdif_sel       20
+        cpu             21
+        ptp_sel         22
+        cpu_pll         23
+        cpu_xtal        24
+        hbus            25
+        xbus            26
+        ssp0_div        27
+        ssp1_div        28
+        ssp2_div        29
+        ssp3_div        30
+        gpmi_div        31
+        emi_pll         32
+        emi_xtal        33
+        lcdif_div       34
+        etm_div         35
+        ptp             36
+        saif0_div       37
+        saif1_div       38
+        clk32k_div      39
+        rtc             40
+        lradc           41
+        spdif_div       42
+        clk32k          43
+        pwm             44
+        uart            45
+        ssp0            46
+        ssp1            47
+        ssp2            48
+        ssp3            49
+        gpmi            50
+        spdif           51
+        emi             52
+        saif0           53
+        saif1           54
+        lcdif           55
+        etm             56
+        fec             57
+        can0            58
+        can1            59
+        usb0            60
+        usb1            61
+        usb0_pwr        62
+        usb1_pwr        63
+        enet_out        64
+
+Examples:
+
+clks: clkctrl@80040000 {
+        compatible = "fsl,imx28-clkctrl";
+        reg = <0x80040000 0x2000>;
+        #clock-cells = <1>;
+        clock-output-names =
+                ...
+                "uart",         /* 45 */
+                ...
+                "end_of_list";
+};
+
+auart0: serial@8006a000 {
+        compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+        reg = <0x8006a000 0x2000>;
+        interrupts = <112 70 71>;
+        clocks = <&clks 45>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
new file mode 100644
index 000000000000..492bd991d52a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -0,0 +1,222 @@
+* Clock bindings for Freescale i.MX6 Quad
+
+Required properties:
+- compatible: Should be "fsl,imx6q-ccm"
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX6Q
+clocks and IDs.
+
+        Clock                   ID
+        ---------------------------
+        dummy                   0
+        ckil                    1
+        ckih                    2
+        osc                     3
+        pll2_pfd0_352m          4
+        pll2_pfd1_594m          5
+        pll2_pfd2_396m          6
+        pll3_pfd0_720m          7
+        pll3_pfd1_540m          8
+        pll3_pfd2_508m          9
+        pll3_pfd3_454m          10
+        pll2_198m               11
+        pll3_120m               12
+        pll3_80m                13
+        pll3_60m                14
+        twd                     15
+        step                    16
+        pll1_sw                 17
+        periph_pre              18
+        periph2_pre             19
+        periph_clk2_sel         20
+        periph2_clk2_sel        21
+        axi_sel                 22
+        esai_sel                23
+        asrc_sel                24
+        spdif_sel               25
+        gpu2d_axi               26
+        gpu3d_axi               27
+        gpu2d_core_sel          28
+        gpu3d_core_sel          29
+        gpu3d_shader_sel        30
+        ipu1_sel                31
+        ipu2_sel                32
+        ldb_di0_sel             33
+        ldb_di1_sel             34
+        ipu1_di0_pre_sel        35
+        ipu1_di1_pre_sel        36
+        ipu2_di0_pre_sel        37
+        ipu2_di1_pre_sel        38
+        ipu1_di0_sel            39
+        ipu1_di1_sel            40
+        ipu2_di0_sel            41
+        ipu2_di1_sel            42
+        hsi_tx_sel              43
+        pcie_axi_sel            44
+        ssi1_sel                45
+        ssi2_sel                46
+        ssi3_sel                47
+        usdhc1_sel              48
+        usdhc2_sel              49
+        usdhc3_sel              50
+        usdhc4_sel              51
+        enfc_sel                52
+        emi_sel                 53
+        emi_slow_sel            54
+        vdo_axi_sel             55
+        vpu_axi_sel             56
+        cko1_sel                57
+        periph                  58
+        periph2                 59
+        periph_clk2             60
+        periph2_clk2            61
+        ipg                     62
+        ipg_per                 63
+        esai_pred               64
+        esai_podf               65
+        asrc_pred               66
+        asrc_podf               67
+        spdif_pred              68
+        spdif_podf              69
+        can_root                70
+        ecspi_root              71
+        gpu2d_core_podf         72
+        gpu3d_core_podf         73
+        gpu3d_shader            74
+        ipu1_podf               75
+        ipu2_podf               76
+        ldb_di0_podf            77
+        ldb_di1_podf            78
+        ipu1_di0_pre            79
+        ipu1_di1_pre            80
+        ipu2_di0_pre            81
+        ipu2_di1_pre            82
+        hsi_tx_podf             83
+        ssi1_pred               84
+        ssi1_podf               85
+        ssi2_pred               86
+        ssi2_podf               87
+        ssi3_pred               88
+        ssi3_podf               89
+        uart_serial_podf        90
+        usdhc1_podf             91
+        usdhc2_podf             92
+        usdhc3_podf             93
+        usdhc4_podf             94
+        enfc_pred               95
+        enfc_podf               96
+        emi_podf                97
+        emi_slow_podf           98
+        vpu_axi_podf            99
+        cko1_podf               100
+        axi                     101
+        mmdc_ch0_axi_podf       102
+        mmdc_ch1_axi_podf       103
+        arm                     104
+        ahb                     105
+        apbh_dma                106
+        asrc                    107
+        can1_ipg                108
+        can1_serial             109
+        can2_ipg                110
+        can2_serial             111
+        ecspi1                  112
+        ecspi2                  113
+        ecspi3                  114
+        ecspi4                  115
+        ecspi5                  116
+        enet                    117
+        esai                    118
+        gpt_ipg                 119
+        gpt_ipg_per             120
+        gpu2d_core              121
+        gpu3d_core              122
+        hdmi_iahb               123
+        hdmi_isfr               124
+        i2c1                    125
+        i2c2                    126
+        i2c3                    127
+        iim                     128
+        enfc                    129
+        ipu1                    130
+        ipu1_di0                131
+        ipu1_di1                132
+        ipu2                    133
+        ipu2_di0                134
+        ldb_di0                 135
+        ldb_di1                 136
+        ipu2_di1                137
+        hsi_tx                  138
+        mlb                     139
+        mmdc_ch0_axi            140
+        mmdc_ch1_axi            141
+        ocram                   142
+        openvg_axi              143
+        pcie_axi                144
+        pwm1                    145
+        pwm2                    146
+        pwm3                    147
+        pwm4                    148
+        per1_bch                149
+        gpmi_bch_apb            150
+        gpmi_bch                151
+        gpmi_io                 152
+        gpmi_apb                153
+        sata                    154
+        sdma                    155
+        spba                    156
+        ssi1                    157
+        ssi2                    158
+        ssi3                    159
+        uart_ipg                160
+        uart_serial             161
+        usboh3                  162
+        usdhc1                  163
+        usdhc2                  164
+        usdhc3                  165
+        usdhc4                  166
+        vdo_axi                 167
+        vpu_axi                 168
+        cko1                    169
+        pll1_sys                170
+        pll2_bus                171
+        pll3_usb_otg            172
+        pll4_audio              173
+        pll5_video              174
+        pll6_mlb                175
+        pll7_usb_host           176
+        pll8_enet               177
+        ssi1_ipg                178
+        ssi2_ipg                179
+        ssi3_ipg                180
+        rom                     181
+        usbphy1                 182
+        usbphy2                 183
+        ldb_di0_div_3_5         184
+        ldb_di1_div_3_5         185
+
+Examples:
+
+clks: ccm@020c4000 {
+        compatible = "fsl,imx6q-ccm";
+        reg = <0x020c4000 0x4000>;
+        interrupts = <0 87 0x04 0 88 0x04>;
+        #clock-cells = <1>;
+        clock-output-names = ...
+                             "uart_ipg",
+                             "uart_serial",
+                             ...;
+};
+
+uart1: serial@02020000 {
+        compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+        reg = <0x02020000 0x4000>;
+        interrupts = <0 26 0x04>;
+        clocks = <&clks 160>, <&clks 161>;
+        clock-names = "ipg", "per";
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt
new file mode 100644
index 000000000000..47229b1a594b
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/mv_cesa.txt
@@ -0,0 +1,20 @@
+Marvell Cryptographic Engines And Security Accelerator
+
+Required properties:
+- compatible : should be "marvell,orion-crypto"
+- reg : base physical address of the engine and length of memory mapped
+        region, followed by base physical address of sram and its memory
+        length
+- reg-names : "regs" , "sram";
+- interrupts : interrupt number
+
+Examples:
+
+        crypto@30000 {
+                compatible = "marvell,orion-crypto";
+                reg = <0x30000 0x10000>,
+                      <0x4000000 0x800>;
+                reg-names = "regs" , "sram";
+                interrupts = <22>;
+                status = "okay";
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-fan.txt b/Documentation/devicetree/bindings/gpio/gpio-fan.txt
new file mode 100644
index 000000000000..2dd457a3469a
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-fan.txt
@@ -0,0 +1,25 @@
+Bindings for fan connected to GPIO lines
+
+Required properties:
+- compatible : "gpio-fan"
+- gpios: Specifies the pins that map to bits in the control value,
+  ordered MSB-->LSB.
+- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
+  control value that should be set to achieve them. This array
+  must have the RPM values in ascending order.
+
+Optional properties:
+- alarm-gpios: This pin going active indicates something is wrong with
+  the fan, and a udev event will be fired.
+
+Examples:
+
+        gpio_fan {
+                compatible = "gpio-fan";
+                gpios = <&gpio1 14 1
+                         &gpio1 13 1>;
+                gpio-fan,speed-map = <0    0
+                                      3000 1
+                                      6000 2>;
+                alarm-gpios = <&gpio1 15 1>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
new file mode 100644
index 000000000000..a6f3bec1da7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -0,0 +1,53 @@
+* Marvell EBU GPIO controller
+
+Required properties:
+
+- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
+  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
+  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
+  370. "marvell,mv78200-gpio" should be used for the Discovery
+  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
+  SoCs (MV78230, MV78260, MV78460).
+
+- reg: Address and length of the register set for the device. Only one
+  entry is expected, except for the "marvell,armadaxp-gpio" variant
+  for which two entries are expected: one for the general registers,
+  one for the per-cpu registers.
+
+- interrupts: The list of interrupts that are used for all the pins
+  managed by this GPIO bank. There can be more than one interrupt
+  (example: 1 interrupt per 8 pins on Armada XP, which means 4
+  interrupts per bank of 32 GPIOs).
+
+- interrupt-controller: identifies the node as an interrupt controller
+
+- #interrupt-cells: specifies the number of cells needed to encode an
+  interrupt source. Should be two.
+  The first cell is the GPIO number.
+  The second cell is used to specify flags:
+    bits[3:0] trigger type and level flags:
+      1 = low-to-high edge triggered.
+      2 = high-to-low edge triggered.
+      4 = active high level-sensitive.
+      8 = active low level-sensitive.
+
+- gpio-controller: marks the device node as a gpio controller
+
+- ngpios: number of GPIOs this controller has
+
+- #gpio-cells: Should be two. The first cell is the pin number. The
+  second cell is reserved for flags, unused at the moment.
+
+Example:
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
index 5375625e8cd2..f1e5dfecf55d 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -39,3 +39,46 @@ Example:
                 #gpio-cells = <4>;
                 gpio-controller;
         };
+
+
+Samsung S3C24XX GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
+
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+
+- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
+  should be the following with values derived from the SoC user manual.
+     <[phandle of the gpio controller node]
+      [pin number within the gpio controller]
+      [mux function]
+      [flags and pull up/down]
+
+  Values for gpio specifier:
+  - Pin number: depending on the controller a number from 0 up to 15.
+  - Mux function: Depending on the SoC and the gpio bank the gpio can be set
+                  as input, output or a special function
+  - Flags and Pull Up/Down: the values to use differ for the individual SoCs
+                    example S3C2416/S3C2450:
+                            0 - Pull Up/Down Disabled.
+                            1 - Pull Down Enabled.
+                            2 - Pull Up Enabled.
+          Bit 16 (0x00010000) - Input is active low.
+  Consult the user manual for the correct values of Mux and Pull Up/Down.
+
+- gpio-controller: Specifies that the node is a gpio controller.
+- #address-cells: should be 1.
+- #size-cells: should be 1.
+
+Example:
+
+        gpa: gpio-controller@56000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "samsung,s3c24xx-gpio";
+                reg = <0x56000000 0x10>;
+                #gpio-cells = <3>;
+                gpio-controller;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
index 16695d9cf1e8..66788fda1db3 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
@@ -11,6 +11,11 @@ Required properties:
 - interrupt-controller: Mark the device node as an interrupt controller
   The first cell is the GPIO number.
   The second cell is not used.
+- ti,use-leds : Enables LEDA and LEDB outputs if set
+- ti,debounce : if n-th bit is set, debounces GPIO-n
+- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
+- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
+- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
 
 Example:
 
@@ -20,4 +25,5 @@ twl_gpio: gpio {
     gpio-controller;
     #interrupt-cells = <2>;
     interrupt-controller;
+    ti,use-leds;
 };
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 1a85f986961b..2f5322b119eb 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -56,3 +56,4 @@ stm,m41t00		Serial Access TIMEKEEPER
 stm,m41t62              Serial real-time clock (RTC) with alarm
 stm,m41t80              M41T80 - SERIAL ACCESS RTC WITH ALARMS
 ti,tsc2003              I2C Touch-Screen Controller
+ti,tmp102               Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
new file mode 100644
index 000000000000..548892c08c59
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
@@ -0,0 +1,110 @@
+BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
+
+The BCM2835 contains a custom top-level interrupt controller, which supports
+72 interrupt sources using a 2-level register scheme. The interrupt
+controller, or the HW block containing it, is referred to occasionally
+as "armctrl" in the SoC documentation, hence naming of this binding.
+
+Required properties:
+
+- compatible : should be "brcm,bcm2835-armctrl-ic.txt"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 2.
+
+  The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
+  pending" register, or 1/2 respectively for interrupts in the "IRQ pending
+  1/2" register.
+
+  The 2nd cell contains the interrupt number within the bank. Valid values
+  are 0..7 for bank 0, and 0..31 for bank 1.
+
+The interrupt sources are as follows:
+
+Bank 0:
+0: ARM_TIMER
+1: ARM_MAILBOX
+2: ARM_DOORBELL_0
+3: ARM_DOORBELL_1
+4: VPU0_HALTED
+5: VPU1_HALTED
+6: ILLEGAL_TYPE0
+7: ILLEGAL_TYPE1
+
+Bank 1:
+0: TIMER0
+1: TIMER1
+2: TIMER2
+3: TIMER3
+4: CODEC0
+5: CODEC1
+6: CODEC2
+7: VC_JPEG
+8: ISP
+9: VC_USB
+10: VC_3D
+11: TRANSPOSER
+12: MULTICORESYNC0
+13: MULTICORESYNC1
+14: MULTICORESYNC2
+15: MULTICORESYNC3
+16: DMA0
+17: DMA1
+18: VC_DMA2
+19: VC_DMA3
+20: DMA4
+21: DMA5
+22: DMA6
+23: DMA7
+24: DMA8
+25: DMA9
+26: DMA10
+27: DMA11
+28: DMA12
+29: AUX
+30: ARM
+31: VPUDMA
+
+Bank 2:
+0: HOSTPORT
+1: VIDEOSCALER
+2: CCP2TX
+3: SDC
+4: DSI0
+5: AVE
+6: CAM0
+7: CAM1
+8: HDMI0
+9: HDMI1
+10: PIXELVALVE1
+11: I2CSPISLV
+12: DSI1
+13: PWA0
+14: PWA1
+15: CPR
+16: SMI
+17: GPIO0
+18: GPIO1
+19: GPIO2
+20: GPIO3
+21: VC_I2C
+22: VC_SPI
+23: VC_I2SPCM
+24: VC_SDIO
+25: VC_UART
+26: SLIMBUS
+27: VEC
+28: CPG
+29: RNG
+30: VC_ARASANSDIO
+31: AVSPMON
+
+Example:
+
+intc: interrupt-controller {
+        compatible = "brcm,bcm2835-armctrl-ic";
+        reg = <0x7e00b200 0x200>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
new file mode 100644
index 000000000000..9ceb19e0c7fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
@@ -0,0 +1,52 @@
+* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
+
+Required properties:
+- compatible : Should be "jedec,lpddr2-timings"
+- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
+- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
+
+Optional properties:
+
+The following properties represent AC timing parameters from the memory
+data-sheet of the device for a given speed-bin. All these properties are
+of type <u32> and the default unit is ps (pico seconds). Parameters with
+a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
+- tRCD
+- tWR
+- tRAS-min
+- tRRD
+- tWTR
+- tXP
+- tRTP
+- tDQSCK-max
+- tFAW
+- tZQCS
+- tZQinit
+- tRPab
+- tZQCL
+- tCKESR
+- tRAS-max-ns
+- tDQSCK-max-derated
+
+Example:
+
+timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+        compatible      = "jedec,lpddr2-timings";
+        min-freq        = <10000000>;
+        max-freq        = <400000000>;
+        tRPab           = <21000>;
+        tRCD            = <18000>;
+        tWR             = <15000>;
+        tRAS-min        = <42000>;
+        tRRD            = <10000>;
+        tWTR            = <7500>;
+        tXP             = <7500>;
+        tRTP            = <7500>;
+        tCKESR          = <15000>;
+        tDQSCK-max      = <5500>;
+        tFAW            = <50000>;
+        tZQCS           = <90000>;
+        tZQCL           = <360000>;
+        tZQinit         = <1000000>;
+        tRAS-max-ns     = <70000>;
+};
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
new file mode 100644
index 000000000000..58354a075e13
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
@@ -0,0 +1,102 @@
+* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
+
+Required properties:
+- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
+  "jedec,lpddr2-s4"
+
+  "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
+
+  "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
+
+  "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
+
+- density  : <u32> representing density in Mb (Mega bits)
+
+- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
+
+Optional properties:
+
+The following optional properties represent the minimum value of some AC
+timing parameters of the DDR device in terms of number of clock cycles.
+These values shall be obtained from the device data-sheet.
+- tRRD-min-tck
+- tWTR-min-tck
+- tXP-min-tck
+- tRTP-min-tck
+- tCKE-min-tck
+- tRPab-min-tck
+- tRCD-min-tck
+- tWR-min-tck
+- tRASmin-min-tck
+- tCKESR-min-tck
+- tFAW-min-tck
+
+Child nodes:
+- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
+  "lpddr2-timings" provides AC timing parameters of the device for
+  a given speed-bin. The user may provide the timings for as many
+  speed-bins as is required. Please see Documentation/devicetree/
+  bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
+
+Example:
+
+elpida_ECB240ABACN : lpddr2 {
+        compatible      = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+        density         = <2048>;
+        io-width        = <32>;
+
+        tRPab-min-tck   = <3>;
+        tRCD-min-tck    = <3>;
+        tWR-min-tck     = <3>;
+        tRASmin-min-tck = <3>;
+        tRRD-min-tck    = <2>;
+        tWTR-min-tck    = <2>;
+        tXP-min-tck     = <2>;
+        tRTP-min-tck    = <2>;
+        tCKE-min-tck    = <3>;
+        tCKESR-min-tck  = <3>;
+        tFAW-min-tck    = <8>;
+
+        timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+                compatible      = "jedec,lpddr2-timings";
+                min-freq        = <10000000>;
+                max-freq        = <400000000>;
+                tRPab           = <21000>;
+                tRCD            = <18000>;
+                tWR             = <15000>;
+                tRAS-min        = <42000>;
+                tRRD            = <10000>;
+                tWTR            = <7500>;
+                tXP             = <7500>;
+                tRTP            = <7500>;
+                tCKESR          = <15000>;
+                tDQSCK-max      = <5500>;
+                tFAW            = <50000>;
+                tZQCS           = <90000>;
+                tZQCL           = <360000>;
+                tZQinit         = <1000000>;
+                tRAS-max-ns     = <70000>;
+        };
+
+        timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+                compatible      = "jedec,lpddr2-timings";
+                min-freq        = <10000000>;
+                max-freq        = <200000000>;
+                tRPab           = <21000>;
+                tRCD            = <18000>;
+                tWR             = <15000>;
+                tRAS-min        = <42000>;
+                tRRD            = <10000>;
+                tWTR            = <10000>;
+                tXP             = <7500>;
+                tRTP            = <7500>;
+                tCKESR          = <15000>;
+                tDQSCK-max      = <5500>;
+                tFAW            = <50000>;
+                tZQCS           = <90000>;
+                tZQCL           = <360000>;
+                tZQinit         = <1000000>;
+                tRAS-max-ns     = <70000>;
+        };
+
+}
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
new file mode 100644
index 000000000000..938f8e1ba205
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -0,0 +1,55 @@
+* EMIF family of TI SDRAM controllers
+
+EMIF - External Memory Interface - is an SDRAM controller used in
+TI SoCs. EMIF supports, based on the IP revision, one or more of
+DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
+of the EMIF IP and memory parts attached to it.
+
+Required properties:
+- compatible    : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
+  is the IP revision of the specific EMIF instance.
+
+- phy-type      : <u32> indicating the DDR phy type. Following are the
+  allowed values
+  <1>   : Attila PHY
+  <2>   : Intelli PHY
+
+- device-handle : phandle to a "lpddr2" node representing the memory part
+
+- ti,hwmods     : For TI hwmods processing and omap device creation
+  the value shall be "emif<n>" where <n> is the number of the EMIF
+  instance with base 1.
+
+Optional properties:
+- cs1-used              : Have this property if CS1 of this EMIF
+  instance has a memory part attached to it. If there is a memory
+  part attached to CS1, it should be the same type as the one on CS0,
+  so there is no need to give the details of this memory part.
+
+- cal-resistor-per-cs   : Have this property if the board has one
+  calibration resistor per chip-select.
+
+- hw-caps-read-idle-ctrl: Have this property if the controller
+  supports read idle window programming
+
+- hw-caps-dll-calib-ctrl: Have this property if the controller
+  supports dll calibration control
+
+- hw-caps-ll-interface  : Have this property if the controller
+  has a low latency interface and corresponding interrupt events
+
+- hw-caps-temp-alert    : Have this property if the controller
+  has capability for generating SDRAM temperature alerts
+
+Example:
+
+emif1: emif@0x4c000000 {
+        compatible      = "ti,emif-4d";
+        ti,hwmods       = "emif2";
+        phy-type        = <1>;
+        device-handle   = <&elpida_ECB240ABACN>;
+        cs1-used;
+        hw-caps-read-idle-ctrl;
+        hw-caps-ll-interface;
+        hw-caps-temp-alert;
+};
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
new file mode 100644
index 000000000000..f1421e2bbab7
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
@@ -0,0 +1,31 @@
+PXA3xx NAND DT bindings
+
+Required properties:
+
+ - compatible:          Should be "marvell,pxa3xx-nand"
+ - reg:                 The register base for the controller
+ - interrupts:          The interrupt to map
+ - #address-cells:      Set to <1> if the node includes partitions
+
+Optional properties:
+
+ - marvell,nand-enable-arbiter: Set to enable the bus arbiter
+ - marvell,nand-keep-config:    Set to keep the NAND controller config as set
+                                by the bootloader
+ - num-cs:                      Number of chipselect lines to usw
+
+Example:
+
+        nand0: nand@43100000 {
+                compatible = "marvell,pxa3xx-nand";
+                reg = <0x43100000 90>;
+                interrupts = <45>;
+                #address-cells = <1>;
+
+                marvell,nand-enable-arbiter;
+                marvell,nand-keep-config;
+                num-cs = <1>;
+
+                /* partitions (optional) */
+        };
+
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
new file mode 100644
index 000000000000..01ef408e205f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, uart0(rxd)
+mpp1          1        gpo, uart0(txd)
+mpp2          2        gpio, i2c0(sck), uart0(txd)
+mpp3          3        gpio, i2c0(sda), uart0(rxd)
+mpp4          4        gpio, cpu_pd(vdd)
+mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+                       sata1(prsnt), spi1(cs1)
+mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+                       audio(rmclk)
+mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+                       spi0(cs2)
+mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+                       spi0(cs3)
+mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17         17       gpo, ge(mdc)
+mpp18         18       gpio, ge(mdio)
+mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20         20       gpo, ge0(txd4), ge1(txd0)
+mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
+mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31         31       gpio, tclk, ge0(txerr)
+mpp32         32       gpio, spi0(cs0)
+mpp33         33       gpio, dev(bootcs), spi0(cs0)
+mpp34         34       gpo, dev(wen0), spi0(mosi)
+mpp35         35       gpo, dev(oen), spi0(sck)
+mpp36         36       gpo, dev(a1), spi0(miso)
+mpp37         37       gpo, dev(a0), sata0(prsnt)
+mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39         39       gpo, dev(ad0), audio(spdifo)
+mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41         41       gpio, dev(ad2), uart1(rxd)
+mpp42         42       gpo, dev(ad3), uart1(txd)
+mpp43         43       gpo, dev(ad4), audio(bclk)
+mpp44         44       gpo, dev(ad5), audio(mclk)
+mpp45         45       gpo, dev(ad6), audio(lrclk)
+mpp46         46       gpo, dev(ad7), audio(sdo)
+mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+                       spi0(cs1)
+mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+                       audio(rmclk)
+mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+                       pcie(clkreq1)
+mpp54         54       gpo, dev(ad15), tdm(dtx)
+mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+                       sata0(prsnt)
+mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+                       pcie(clkreq0), spi1(cs1)
+mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+                       audio(sdo)
+mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+                       uart0(rts)
+mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+                       audio(sdi)
+mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+                       audio(mclk), uart0(cts)
+mpp63         63       gpo, spi0(sck), tclk
+mpp64         64       gpio, spi0(miso), spi0-1(cs1)
+mpp65         65       gpio, spi0(mosi), spi0-1(cs2)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
new file mode 100644
index 000000000000..bfa0a2e5e0cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+              "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, ge0(txclko), lcd(d0)
+mpp1          1        gpio, ge0(txd0), lcd(d1)
+mpp2          2        gpio, ge0(txd1), lcd(d2)
+mpp3          3        gpio, ge0(txd2), lcd(d3)
+mpp4          4        gpio, ge0(txd3), lcd(d4)
+mpp5          5        gpio, ge0(txctl), lcd(d5)
+mpp6          6        gpio, ge0(rxd0), lcd(d6)
+mpp7          7        gpio, ge0(rxd1), lcd(d7)
+mpp8          8        gpio, ge0(rxd2), lcd(d8)
+mpp9          9        gpio, ge0(rxd3), lcd(d9)
+mpp10         10       gpio, ge0(rxctl), lcd(d10)
+mpp11         11       gpio, ge0(rxclk), lcd(d11)
+mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30         30       gpio, tdm(int1), sd0(clk)
+mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36         36       gpio, spi(mosi)
+mpp37         37       gpio, spi(miso)
+mpp38         38       gpio, spi(sck)
+mpp39         39       gpio, spi(cs0)
+mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+                       pcie(clkreq0)
+mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+                       pcie(clkreq1)
+mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+                       vdd(cpu0-pd)
+mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+                       vdd(cpu2-3-pd){1}
+mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+                       mem(bat)
+mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+                       ref(clkout)
+mpp48         48       gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name          pins     functions
+================================================================================
+mpp49         49       gpio, dev(we3)
+mpp50         50       gpio, dev(we2)
+mpp51         51       gpio, dev(ad16)
+mpp52         52       gpio, dev(ad17)
+mpp53         53       gpio, dev(ad18)
+mpp54         54       gpio, dev(ad19)
+mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
+mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
+mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58         58       gpio, dev(ad23)
+mpp59         59       gpio, dev(ad24)
+mpp60         60       gpio, dev(ad25)
+mpp61         61       gpio, dev(ad26)
+mpp62         62       gpio, dev(ad27)
+mpp63         63       gpio, dev(ad28)
+mpp64         64       gpio, dev(ad29)
+mpp65         65       gpio, dev(ad30)
+mpp66         66       gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
new file mode 100644
index 000000000000..a648aaad6110
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -0,0 +1,72 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+- clocks: (optional) phandle of pdma clock
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+                       uart1(rts)
+mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+                       uart1(cts), lcd-spi(cs1)
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8          8        gpio, pmu, watchdog(rstout)
+mpp9          9        gpio, pmu, pex1(clkreq)
+mpp10         10       gpio, pmu, ssp(sclk)
+mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+                       sdio1(ledctrl), pex0(clkreq)
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+                       ssp(extclk)
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+                       ac97-1(sysclko)
+mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+                       ac97(sysclko)
+mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+                       uart1(cts), ssp(sfrm)
+mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+                       lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+                       lcd-spi(sck), ssp(sclk)
+mpp_camera    24-39    gpio, camera
+mpp_sdio0     40-45    gpio, sdio0
+mpp_sdio1     46-51    gpio, sdio1
+mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+                       ssp/twsi
+mpp_spi0      58-61    gpio, spi0
+mpp_uart1     62-63    gpio, uart1
+mpp_nand      64-71    gpo, nand
+audio0        -        i2s, ac97
+twsi          -        none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+  - gpio          : gpio on pins 52-57
+  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
+  - spdifo        : spdifo on pin 57, gpio on pins 52-55
+  - twsi          : twsi on pins 56,57, gpio on pins 52-55
+  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
+  - ssp           : ssp on pins 52-55, gpio on pins 56,57
+  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+  audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
new file mode 100644
index 000000000000..361bccb7ec89
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, mii(rxerr)
+mpp21         21       gpio, audio(spdifi)
+mpp22         22       gpio, audio(spdifo)
+mpp23         23       gpio, audio(rmclk)
+mpp24         24       gpio, audio(bclk)
+mpp25         25       gpio, audio(sdo)
+mpp26         26       gpio, audio(lrclk)
+mpp27         27       gpio, audio(mclk)
+mpp28         28       gpio, audio(sdi)
+mpp29         29       gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0)
+mpp21         21       gpio, ge1(txd1), sata0(act)
+mpp22         22       gpio, ge1(txd2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt)
+mpp24         24       gpio, ge1(rxd0)
+mpp25         25       gpio, ge1(rxd1)
+mpp26         26       gpio, ge1(rxd2)
+mpp27         27       gpio, ge1(rxd3)
+mpp28         28       gpio, ge1(col)
+mpp29         29       gpio, ge1(txclk)
+mpp30         30       gpio, ge1(rxclk)
+mpp31         31       gpio, ge1(rxclk)
+mpp32         32       gpio, ge1(txclko)
+mpp33         33       gpo, ge1(txclk)
+mpp34         34       gpio, ge1(txen)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpio, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45         45       gpio, ts(mp9), tdm(pclk)
+mpp46         46       gpio, ts(mp10), tdm(fs)
+mpp47         47       gpio, ts(mp11), tdm(drx)
+mpp48         48       gpio, ts(mp12), tdm(dtx)
+mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, spi(cs), lcd(pwm)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+                       mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+                       sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+                       audio(spdifi), audio-1(sdi)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+                       spi(cs)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act), lcd(extclk)
+mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18         18       gpo, nand(io0), pex(clkreq)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act), lcd(d0)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo), lcd(d1)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt), lcd(d2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk), lcd(d3)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+                       lcd(d4)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+                       lcd(d5)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+                       lcd(d6)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+                       lcd(d7)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+                       lcd(d8)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+                       lcd(d15)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
new file mode 100644
index 000000000000..0a26c3aa4e6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -0,0 +1,46 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing a function to mux to for all
+    marvell,pins given in this pin configuration node. The function has to be
+    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+    valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial@12100 {
+        compatible = "ns16550a";
+        reg = <0x12100 0x100>;
+        reg-shift = <2>;
+        interrupts = <7>;
+
+        pinctrl-0 = <&pmx_uart1_sw>;
+        pinctrl-names = "default";
+};
+
+pinctrl: pinctrl@d0200 {
+        compatible = "marvell,dove-pinctrl";
+        reg = <0xd0200 0x20>;
+
+        pmx_uart1_sw: pmx-uart1-sw {
+                marvell,pins = "mpp_uart1";
+                marvell,function = "uart1";
+        };
+};
diff --git a/Documentation/devicetree/bindings/regulator/tps6586x.txt b/Documentation/devicetree/bindings/regulator/tps6586x.txt
index da80c2ae0915..a2436e1edfc1 100644
--- a/Documentation/devicetree/bindings/regulator/tps6586x.txt
+++ b/Documentation/devicetree/bindings/regulator/tps6586x.txt
@@ -8,7 +8,8 @@ Required properties:
 - gpio-controller: mark the device as a GPIO controller
 - regulators: list of regulators provided by this controller, must have
   property "regulator-compatible" to match their hardware counterparts:
-  sm[0-2], ldo[0-9] and ldo_rtc
+  sys, sm[0-2], ldo[0-9] and ldo_rtc
+- sys-supply: The input supply for SYS.
 - vin-sm0-supply: The input supply for the SM0.
 - vin-sm1-supply: The input supply for the SM1.
 - vin-sm2-supply: The input supply for the SM2.
@@ -20,6 +21,9 @@ Required properties:
 
 Each regulator is defined using the standard binding for regulators.
 
+Note: LDO5 and LDO_RTC is supplied by SYS regulator internally and driver
+      take care of making proper parent child relationship.
+
 Example:
 
         pmu: tps6586x@34 {
@@ -30,6 +34,7 @@ Example:
                 #gpio-cells = <2>;
                 gpio-controller;
 
+                sys-supply = <&some_reg>;
                 vin-sm0-supply = <&some_reg>;
                 vin-sm1-supply = <&some_reg>;
                 vin-sm2-supply = <&some_reg>;
@@ -43,8 +48,16 @@ Example:
                         #address-cells = <1>;
                         #size-cells = <0>;
 
-                        sm0_reg: regulator@0 {
+                        sys_reg: regulator@0 {
                                 reg = <0>;
+                                regulator-compatible = "sys";
+                                regulator-name = "vdd_sys";
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sm0_reg: regulator@1 {
+                                reg = <1>;
                                 regulator-compatible = "sm0";
                                 regulator-min-microvolt = < 725000>;
                                 regulator-max-microvolt = <1500000>;
@@ -52,8 +65,8 @@ Example:
                                 regulator-always-on;
                         };
 
-                        sm1_reg: regulator@1 {
-                                reg = <1>;
+                        sm1_reg: regulator@2 {
+                                reg = <2>;
                                 regulator-compatible = "sm1";
                                 regulator-min-microvolt = < 725000>;
                                 regulator-max-microvolt = <1500000>;
@@ -61,8 +74,8 @@ Example:
                                 regulator-always-on;
                         };
 
-                        sm2_reg: regulator@2 {
-                                reg = <2>;
+                        sm2_reg: regulator@3 {
+                                reg = <3>;
                                 regulator-compatible = "sm2";
                                 regulator-min-microvolt = <3000000>;
                                 regulator-max-microvolt = <4550000>;
@@ -70,72 +83,72 @@ Example:
                                 regulator-always-on;
                         };
 
-                        ldo0_reg: regulator@3 {
-                                reg = <3>;
+                        ldo0_reg: regulator@4 {
+                                reg = <4>;
                                 regulator-compatible = "ldo0";
                                 regulator-name = "PCIE CLK";
                                 regulator-min-microvolt = <3300000>;
                                 regulator-max-microvolt = <3300000>;
                         };
 
-                        ldo1_reg: regulator@4 {
-                                reg = <4>;
+                        ldo1_reg: regulator@5 {
+                                reg = <5>;
                                 regulator-compatible = "ldo1";
                                 regulator-min-microvolt = < 725000>;
                                 regulator-max-microvolt = <1500000>;
                         };
 
-                        ldo2_reg: regulator@5 {
-                                reg = <5>;
+                        ldo2_reg: regulator@6 {
+                                reg = <6>;
                                 regulator-compatible = "ldo2";
                                 regulator-min-microvolt = < 725000>;
                                 regulator-max-microvolt = <1500000>;
                         };
 
-                        ldo3_reg: regulator@6 {
-                                reg = <6>;
+                        ldo3_reg: regulator@7 {
+                                reg = <7>;
                                 regulator-compatible = "ldo3";
                                 regulator-min-microvolt = <1250000>;
                                 regulator-max-microvolt = <3300000>;
                         };
 
-                        ldo4_reg: regulator@7 {
-                                reg = <7>;
+                        ldo4_reg: regulator@8 {
+                                reg = <8>;
                                 regulator-compatible = "ldo4";
                                 regulator-min-microvolt = <1700000>;
                                 regulator-max-microvolt = <2475000>;
                         };
 
-                        ldo5_reg: regulator@8 {
-                                reg = <8>;
+                        ldo5_reg: regulator@9 {
+                                reg = <9>;
                                 regulator-compatible = "ldo5";
                                 regulator-min-microvolt = <1250000>;
                                 regulator-max-microvolt = <3300000>;
                         };
 
-                        ldo6_reg: regulator@9 {
-                                reg = <9>;
+                        ldo6_reg: regulator@10 {
+                                reg = <10>;
                                 regulator-compatible = "ldo6";
                                 regulator-min-microvolt = <1250000>;
                                 regulator-max-microvolt = <3300000>;
                         };
 
-                        ldo7_reg: regulator@10 {
-                                reg = <10>;
+                        ldo7_reg: regulator@11 {
+                                reg = <11>;
                                 regulator-compatible = "ldo7";
                                 regulator-min-microvolt = <1250000>;
                                 regulator-max-microvolt = <3300000>;
                         };
 
-                        ldo8_reg: regulator@11 {
-                                reg = <11>;
+                        ldo8_reg: regulator@12 {
+                                reg = <12>;
                                 regulator-compatible = "ldo8";
                                 regulator-min-microvolt = <1250000>;
                                 regulator-max-microvolt = <3300000>;
                         };
 
-                        ldo9_reg: regulator@12 {
-                                reg = <12>;
+                        ldo9_reg: regulator@13 {
+                                reg = <13>;
                                 regulator-compatible = "ldo9";
                                 regulator-min-microvolt = <1250000>;
                                 regulator-max-microvolt = <3300000>;
diff --git a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
new file mode 100644
index 000000000000..8c6672a1b7d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
@@ -0,0 +1,14 @@
+* PXA RTC
+
+PXA specific RTC driver.
+
+Required properties:
+- compatible : Should be "marvell,pxa-rtc"
+
+Examples:
+
+rtc@40900000 {
+        compatible = "marvell,pxa-rtc";
+        reg = <0x40900000 0x3c>;
+        interrupts = <30 31>;
+};
diff --git a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt b/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
new file mode 100644
index 000000000000..2de21c2acf55
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
@@ -0,0 +1,22 @@
+BCM2835 System Timer
+
+The System Timer peripheral provides four 32-bit timer channels and a
+single 64-bit free running counter. Each channel has an output compare
+register, which is compared against the 32 least significant bits of the
+free running counter values, and generates an interrupt.
+
+Required properties:
+
+- compatible : should be "brcm,bcm2835-system-timer.txt"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 4 interrupt sinks; one per timer channel.
+- clock-frequency : The frequency of the clock that drives the counter, in Hz.
+
+Example:
+
+timer {
+        compatible = "brcm,bcm2835-system-timer";
+        reg = <0x7e003000 0x1000>;
+        interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
+        clock-frequency = <1000000>;
+};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index db4d3af3643c..4f293e5571f0 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -10,6 +10,7 @@ apm	Applied Micro Circuits Corporation (APM)
 arm     ARM Ltd.
 atmel   Atmel Corporation
 bosch   Bosch Sensortec GmbH
+brcm    Broadcom Corporation
 cavium  Cavium, Inc.
 chrp    Common Hardware Reference Platform
 cortina Cortina Systems, Inc.
diff --git a/Documentation/spi/ep93xx_spi b/Documentation/spi/ep93xx_spi
index d8eb01c15db1..832ddce6e5fb 100644
--- a/Documentation/spi/ep93xx_spi
+++ b/Documentation/spi/ep93xx_spi
@@ -26,7 +26,7 @@ arch/arm/mach-ep93xx/ts72xx.c:
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 
-#include <mach/ep93xx_spi.h>
+#include <linux/platform_data/spi-ep93xx.h>
 
 /* this is our GPIO line used for chip select */
 #define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO9
diff --git a/MAINTAINERS b/MAINTAINERS
index 53cc13c82cb1..9d3965cbf48c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -595,7 +595,6 @@ M:	Will Deacon <will.deacon@arm.com>
 S:      Maintained
 F:      arch/arm/kernel/perf_event*
 F:      arch/arm/oprofile/common.c
-F:      arch/arm/kernel/pmu.c
 F:      arch/arm/include/asm/pmu.h
 F:      arch/arm/kernel/hw_breakpoint.c
 F:      arch/arm/include/asm/hw_breakpoint.h
@@ -1613,6 +1612,16 @@ L:	netdev@vger.kernel.org
 S:      Supported
 F:      drivers/net/ethernet/broadcom/bnx2x/
 
+BROADCOM BCM2835 ARM ARCHICTURE
+M:      Stephen Warren <swarren@wwwdotorg.org>
+L:      linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
+T:      git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi.git
+S:      Maintained
+F:      arch/arm/mach-bcm2835/
+F:      arch/arm/boot/dts/bcm2835*
+F:      arch/arm/configs/bcm2835_defconfig
+F:      drivers/*/*bcm2835*
+
 BROADCOM TG3 GIGABIT ETHERNET DRIVER
 M:      Matt Carlson <mcarlson@broadcom.com>
 M:      Michael Chan <mchan@broadcom.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2f88d8d97701..70505d8f85c5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -202,6 +202,13 @@ config ARM_PATCH_PHYS_VIRT
           this feature (eg, building a kernel for a single machine) and
           you need to shrink the kernel to the minimal size.
 
+config NEED_MACH_GPIO_H
+        bool
+        help
+          Select this when mach/gpio.h is required to provide special
+          definitions for this platform. The need for mach/gpio.h should
+          be avoided when possible.
+
 config NEED_MACH_IO_H
         bool
         help
@@ -247,39 +254,29 @@ config MMU
 #
 choice
         prompt "ARM system type"
-        default ARCH_VERSATILE
+        default ARCH_MULTIPLATFORM
 
-config ARCH_SOCFPGA
-        bool "Altera SOCFPGA family"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_AMBA
-        select ARM_GIC
-        select CACHE_L2X0
-        select CLKDEV_LOOKUP
+config ARCH_MULTIPLATFORM
+        bool "Allow multiple platforms to be selected"
+        select ARM_PATCH_PHYS_VIRT
+        select AUTO_ZRELADDR
         select COMMON_CLK
-        select CPU_V7
-        select DW_APB_TIMER
-        select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
-        select GPIO_PL061 if GPIOLIB
-        select HAVE_ARM_SCU
+        select MULTI_IRQ_HANDLER
         select SPARSE_IRQ
         select USE_OF
-        help
-          This enables support for Altera SOCFPGA Cyclone V platform
+        depends on MMU
 
 config ARCH_INTEGRATOR
         bool "ARM Ltd. Integrator family"
         select ARM_AMBA
         select ARCH_HAS_CPUFREQ
         select COMMON_CLK
-        select CLK_VERSATILE
+        select COMMON_CLK_VERSATILE
         select HAVE_TCM
         select ICST
         select GENERIC_CLOCKEVENTS
         select PLAT_VERSATILE
         select PLAT_VERSATILE_FPGA_IRQ
-        select NEED_MACH_IO_H
         select NEED_MACH_MEMORY_H
         select SPARSE_IRQ
         select MULTI_IRQ_HANDLER
@@ -289,13 +286,12 @@ config ARCH_INTEGRATOR
 config ARCH_REALVIEW
         bool "ARM Ltd. RealView family"
         select ARM_AMBA
-        select CLKDEV_LOOKUP
-        select HAVE_MACH_CLKDEV
+        select COMMON_CLK
+        select COMMON_CLK_VERSATILE
         select ICST
         select GENERIC_CLOCKEVENTS
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select PLAT_VERSATILE
-        select PLAT_VERSATILE_CLOCK
         select PLAT_VERSATILE_CLCD
         select ARM_TIMER_SP804
         select GPIO_PL061 if GPIOLIB
@@ -312,7 +308,6 @@ config ARCH_VERSATILE
         select ICST
         select GENERIC_CLOCKEVENTS
         select ARCH_WANT_OPTIONAL_GPIOLIB
-        select NEED_MACH_IO_H if PCI
         select PLAT_VERSATILE
         select PLAT_VERSATILE_CLOCK
         select PLAT_VERSATILE_CLCD
@@ -321,64 +316,46 @@ config ARCH_VERSATILE
         help
           This enables support for ARM Ltd Versatile board.
 
-config ARCH_VEXPRESS
-        bool "ARM Ltd. Versatile Express family"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_AMBA
-        select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
-        select HAVE_PATA_PLATFORM
-        select ICST
-        select NO_IOPORT
-        select PLAT_VERSATILE
-        select PLAT_VERSATILE_CLCD
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        help
-          This enables support for the ARM Ltd Versatile Express boards.
-
 config ARCH_AT91
         bool "Atmel AT91"
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
         select CLKDEV_LOOKUP
         select IRQ_DOMAIN
+        select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H if PCCARD
         help
           This enables support for systems based on Atmel
           AT91RM9200 and AT91SAM9* processors.
 
-config ARCH_BCMRING
-        bool "Broadcom BCMRING"
-        depends on MMU
-        select CPU_V6
+config ARCH_BCM2835
+        bool "Broadcom BCM2835 family"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_AMBA
+        select ARM_ERRATA_411920
         select ARM_TIMER_SP804
         select CLKDEV_LOOKUP
+        select COMMON_CLK
+        select CPU_V6
         select GENERIC_CLOCKEVENTS
-        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+        select USE_OF
         help
-          Support for Broadcom's BCMRing platform.
+          This enables support for the Broadcom BCM2835 SoC. This SoC is
+          use in the Raspberry Pi, and Roku 2 devices.
 
-config ARCH_HIGHBANK
-        bool "Calxeda Highbank-based"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
+config ARCH_BCMRING
+        bool "Broadcom BCMRING"
+        depends on MMU
+        select CPU_V6
         select ARM_AMBA
-        select ARM_GIC
         select ARM_TIMER_SP804
-        select CACHE_L2X0
         select CLKDEV_LOOKUP
-        select COMMON_CLK
-        select CPU_V7
         select GENERIC_CLOCKEVENTS
-        select HAVE_ARM_SCU
-        select HAVE_SMP
-        select SPARSE_IRQ
-        select USE_OF
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         help
-          Support for the Calxeda Highbank SoC based boards.
+          Support for Broadcom's BCMRing platform.
 
 config ARCH_CLPS711X
         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
@@ -407,21 +384,19 @@ config ARCH_GEMINI
         help
           Support for the Cortina Systems Gemini family SoCs
 
-config ARCH_PRIMA2
-        bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
-        select CPU_V7
+config ARCH_SIRF
+        bool "CSR SiRF"
         select NO_IOPORT
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select CLKDEV_LOOKUP
+        select COMMON_CLK
         select GENERIC_IRQ_CHIP
         select MIGHT_HAVE_CACHE_L2X0
         select PINCTRL
         select PINCTRL_SIRF
         select USE_OF
-        select ZONE_DMA
         help
-          Support for CSR SiRFSoC ARM Cortex A9 Platform
+          Support for CSR SiRFprimaII/Marco/Polo platforms
 
 config ARCH_EBSA110
         bool "EBSA-110"
@@ -456,7 +431,7 @@ config ARCH_FOOTBRIDGE
         select FOOTBRIDGE
         select GENERIC_CLOCKEVENTS
         select HAVE_IDE
-        select NEED_MACH_IO_H
+        select NEED_MACH_IO_H if !MMU
         select NEED_MACH_MEMORY_H
         help
           Support for systems based on the DC21285 companion chip
@@ -513,7 +488,6 @@ config ARCH_IOP13XX
         select PCI
         select ARCH_SUPPORTS_MSI
         select VMSPLIT_1G
-        select NEED_MACH_IO_H
         select NEED_MACH_MEMORY_H
         select NEED_RET_TO_USER
         help
@@ -523,6 +497,7 @@ config ARCH_IOP32X
         bool "IOP32x-based"
         depends on MMU
         select CPU_XSCALE
+        select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
         select NEED_RET_TO_USER
         select PLAT_IOP
@@ -536,6 +511,7 @@ config ARCH_IOP33X
         bool "IOP33x-based"
         depends on MMU
         select CPU_XSCALE
+        select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
         select NEED_RET_TO_USER
         select PLAT_IOP
@@ -558,26 +534,14 @@ config ARCH_IXP4XX
         help
           Support for Intel's IXP4XX (XScale) family of processors.
 
-config ARCH_MVEBU
-        bool "Marvell SOCs with Device Tree support"
-        select GENERIC_CLOCKEVENTS
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
-        select CLKSRC_MMIO
-        select GENERIC_IRQ_CHIP
-        select IRQ_DOMAIN
-        select COMMON_CLK
-        help
-          Support for the Marvell SoC Family with device tree support
-
 config ARCH_DOVE
         bool "Marvell Dove"
         select CPU_V7
-        select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select NEED_MACH_IO_H
-        select PLAT_ORION
+        select MIGHT_HAVE_PCI
+        select PLAT_ORION_LEGACY
+        select USB_ARCH_HAS_EHCI
         help
           Support for the Marvell Dove SoC 88AP510
 
@@ -587,8 +551,7 @@ config ARCH_KIRKWOOD
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select NEED_MACH_IO_H
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
         help
           Support for the following Marvell Kirkwood series SoCs:
           88F6180, 88F6192 and 88F6281.
@@ -614,8 +577,7 @@ config ARCH_MV78XX0
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select NEED_MACH_IO_H
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
         help
           Support for the following Marvell MV78xx0 series SoCs:
           MV781x0, MV782x0.
@@ -627,8 +589,7 @@ config ARCH_ORION5X
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select NEED_MACH_IO_H
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
         help
           Support for the following Marvell Orion 5x series SoCs:
           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -645,6 +606,7 @@ config ARCH_MMP
         select PLAT_PXA
         select SPARSE_IRQ
         select GENERIC_ALLOCATOR
+        select NEED_MACH_GPIO_H
         help
           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 
@@ -652,8 +614,9 @@ config ARCH_KS8695
         bool "Micrel/Kendin KS8695"
         select CPU_ARM922T
         select ARCH_REQUIRE_GPIOLIB
-        select ARCH_USES_GETTIMEOFFSET
         select NEED_MACH_MEMORY_H
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
         help
           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
           System-on-Chip devices.
@@ -683,40 +646,13 @@ config ARCH_TEGRA
         select HAVE_CLK
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
-        select NEED_MACH_IO_H if PCI
         select ARCH_HAS_CPUFREQ
         select USE_OF
+        select COMMON_CLK
         help
           This enables support for NVIDIA Tegra based systems (Tegra APX,
           Tegra 6xx and Tegra 2 series).
 
-config ARCH_PICOXCELL
-        bool "Picochip picoXcell"
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_PATCH_PHYS_VIRT
-        select ARM_VIC
-        select CPU_V6K
-        select DW_APB_TIMER
-        select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
-        select HAVE_TCM
-        select NO_IOPORT
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          This enables support for systems based on the Picochip picoXcell
-          family of Femtocell devices.  The picoxcell support requires device tree
-          for all boards.
-
-config ARCH_PNX4008
-        bool "Philips Nexperia PNX4008 Mobile"
-        select CPU_ARM926T
-        select CLKDEV_LOOKUP
-        select ARCH_USES_GETTIMEOFFSET
-        help
-          This enables support for Philips PNX4008 mobile platform.
-
 config ARCH_PXA
         bool "PXA2xx/PXA3xx-based"
         depends on MMU
@@ -733,6 +669,7 @@ config ARCH_PXA
         select MULTI_IRQ_HANDLER
         select ARM_CPU_SUSPEND if PM
         select HAVE_IDE
+        select NEED_MACH_GPIO_H
         help
           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
@@ -795,6 +732,7 @@ config ARCH_SA1100
         select CLKDEV_LOOKUP
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_IDE
+        select NEED_MACH_GPIO_H
         select NEED_MACH_MEMORY_H
         select SPARSE_IRQ
         help
@@ -810,6 +748,7 @@ config ARCH_S3C24XX
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C_RTC if RTC_CLASS
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
         help
           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
@@ -837,6 +776,7 @@ config ARCH_S3C64XX
         select SAMSUNG_GPIOLIB_4BIT
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
         help
           Samsung S3C64XX series based systems
 
@@ -851,6 +791,7 @@ config ARCH_S5P64X0
         select GENERIC_CLOCKEVENTS
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C_RTC if RTC_CLASS
+        select NEED_MACH_GPIO_H
         help
           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
           SMDK6450.
@@ -865,6 +806,7 @@ config ARCH_S5PC100
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C_RTC if RTC_CLASS
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
         help
           Samsung S5PC100 series based systems
 
@@ -882,6 +824,7 @@ config ARCH_S5PV210
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C_RTC if RTC_CLASS
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
         select NEED_MACH_MEMORY_H
         help
           Samsung S5PV210/S5PC110 series based systems
@@ -899,6 +842,7 @@ config ARCH_EXYNOS
         select HAVE_S3C_RTC if RTC_CLASS
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
         select NEED_MACH_MEMORY_H
         help
           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
@@ -912,7 +856,6 @@ config ARCH_SHARK
         select PCI
         select ARCH_USES_GETTIMEOFFSET
         select NEED_MACH_MEMORY_H
-        select NEED_MACH_IO_H
         help
           Support for the StrongARM based Digital DNARD machine, also known
           as "Shark" (<http://www.shark-linux.de/shark.html>).
@@ -931,6 +874,7 @@ config ARCH_U300
         select COMMON_CLK
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
+        select SPARSE_IRQ
         help
           Support for ST-Ericsson U300 series mobile platforms.
 
@@ -971,6 +915,7 @@ config ARCH_DAVINCI
         select GENERIC_ALLOCATOR
         select GENERIC_IRQ_CHIP
         select ARCH_HAS_HOLES_MEMORYMODEL
+        select NEED_MACH_GPIO_H
         help
           Support for TI's DaVinci platform.
 
@@ -983,6 +928,7 @@ config ARCH_OMAP
         select CLKSRC_MMIO
         select GENERIC_CLOCKEVENTS
         select ARCH_HAS_HOLES_MEMORYMODEL
+        select NEED_MACH_GPIO_H
         help
           Support for TI's OMAP platform (OMAP1/2/3/4).
 
@@ -1022,6 +968,50 @@ config ARCH_ZYNQ
           Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
 
+menu "Multiple platform selection"
+        depends on ARCH_MULTIPLATFORM
+
+comment "CPU Core family selection"
+
+config ARCH_MULTI_V4
+        bool "ARMv4 based platforms (FA526, StrongARM)"
+        select ARCH_MULTI_V4_V5
+        depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V4T
+        bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
+        select ARCH_MULTI_V4_V5
+        depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V5
+        bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
+        select ARCH_MULTI_V4_V5
+        depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V4_V5
+        bool
+
+config ARCH_MULTI_V6
+        bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
+        select CPU_V6
+        select ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V7
+        bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
+        select CPU_V7
+        select ARCH_VEXPRESS
+        default y
+        select ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V6_V7
+        bool
+
+config ARCH_MULTI_CPU_AUTO
+        def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
+        select ARCH_MULTI_V5
+
+endmenu
+
 #
 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 # Kconfigs may be included either alphabetically (according to the
@@ -1049,6 +1039,8 @@ source "arch/arm/mach-gemini/Kconfig"
 
 source "arch/arm/mach-h720x/Kconfig"
 
+source "arch/arm/mach-highbank/Kconfig"
+
 source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-iop32x/Kconfig"
@@ -1084,6 +1076,8 @@ source "arch/arm/mach-omap2/Kconfig"
 
 source "arch/arm/mach-orion5x/Kconfig"
 
+source "arch/arm/mach-picoxcell/Kconfig"
+
 source "arch/arm/mach-pxa/Kconfig"
 source "arch/arm/plat-pxa/Kconfig"
 
@@ -1096,6 +1090,8 @@ source "arch/arm/mach-sa1100/Kconfig"
 source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 
+source "arch/arm/mach-socfpga/Kconfig"
+
 source "arch/arm/plat-spear/Kconfig"
 
 source "arch/arm/mach-s3c24xx/Kconfig"
@@ -1118,6 +1114,8 @@ source "arch/arm/mach-exynos/Kconfig"
 
 source "arch/arm/mach-shmobile/Kconfig"
 
+source "arch/arm/mach-prima2/Kconfig"
+
 source "arch/arm/mach-tegra/Kconfig"
 
 source "arch/arm/mach-u300/Kconfig"
@@ -1148,6 +1146,10 @@ config PLAT_ORION
         select IRQ_DOMAIN
         select COMMON_CLK
 
+config PLAT_ORION_LEGACY
+        bool
+        select PLAT_ORION
+
 config PLAT_PXA
         bool
 
@@ -1179,12 +1181,6 @@ config XSCALE_PMU
         depends on CPU_XSCALE
         default y
 
-config CPU_HAS_PMU
-        depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
-                   (!ARCH_OMAP3 || OMAP3_EMU)
-        default y
-        bool
-
 config MULTI_IRQ_HANDLER
         bool
         help
@@ -1757,7 +1753,7 @@ config HIGHPTE
 
 config HW_PERF_EVENTS
         bool "Enable hardware performance counter support for perf events"
-        depends on PERF_EVENTS && CPU_HAS_PMU
+        depends on PERF_EVENTS
         default y
         help
           Enable hardware performance counter support for perf events. If
@@ -2060,7 +2056,7 @@ endchoice
 
 config XIP_KERNEL
         bool "Kernel Execute-In-Place from ROM"
-        depends on !ZBOOT_ROM && !ARM_LPAE
+        depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
         help
           Execute-In-Place allows the kernel to run from non-volatile storage
           directly addressable by the CPU, such as NOR flash. This saves RAM
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e968a52e4881..a7eb28260b2e 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -261,6 +261,20 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to the serial port on MSM 8960 devices.
 
+        config DEBUG_MVEBU_UART
+                bool "Kernel low-level debugging messages via MVEBU UART"
+                depends on ARCH_MVEBU
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on MVEBU based platforms.
+
+        config DEBUG_PICOXCELL_UART
+                depends on ARCH_PICOXCELL
+                bool "Use PicoXcell UART for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on PicoXcell based platforms.
+
         config DEBUG_REALVIEW_STD_PORT
                 bool "RealView Default UART"
                 depends on ARCH_REALVIEW
@@ -310,6 +324,13 @@ choice
                   The uncompressor code port configuration is now handled
                   by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+        config DEBUG_SOCFPGA_UART
+                depends on ARCH_SOCFPGA
+                bool "Use SOCFPGA UART for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on SOCFPGA based platforms.
+
         config DEBUG_VEXPRESS_UART0_DETECT
                 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
                 depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -338,6 +359,7 @@ choice
 
         config DEBUG_LL_UART_NONE
                 bool "No low-level debugging UART"
+                depends on !ARCH_MULTIPLATFORM
                 help
                   Say Y here if your platform doesn't provide a UART option
                   below. This relies on your platform choosing the right UART
@@ -373,6 +395,17 @@ choice
 
 endchoice
 
+config DEBUG_LL_INCLUDE
+        string
+        default "debug/icedcc.S" if DEBUG_ICEDCC
+        default "debug/highbank.S" if DEBUG_HIGHBANK_UART
+        default "debug/mvebu.S" if DEBUG_MVEBU_UART
+        default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
+        default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+        default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
+                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+        default "mach/debug-macro.S"
+
 config EARLY_PRINTK
         bool "Early printk"
         depends on DEBUG_LL
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a051dfbdd7db..1c974cf9db1b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -135,84 +135,79 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_AT91)             := at91
-machine-$(CONFIG_ARCH_BCMRING)          := bcmring
-machine-$(CONFIG_ARCH_CLPS711X)         := clps711x
-machine-$(CONFIG_ARCH_CNS3XXX)          := cns3xxx
-machine-$(CONFIG_ARCH_DAVINCI)          := davinci
-machine-$(CONFIG_ARCH_DOVE)             := dove
-machine-$(CONFIG_ARCH_EBSA110)          := ebsa110
-machine-$(CONFIG_ARCH_EP93XX)           := ep93xx
-machine-$(CONFIG_ARCH_GEMINI)           := gemini
-machine-$(CONFIG_ARCH_H720X)            := h720x
-machine-$(CONFIG_ARCH_HIGHBANK)         := highbank
-machine-$(CONFIG_ARCH_INTEGRATOR)       := integrator
-machine-$(CONFIG_ARCH_IOP13XX)          := iop13xx
-machine-$(CONFIG_ARCH_IOP32X)           := iop32x
-machine-$(CONFIG_ARCH_IOP33X)           := iop33x
-machine-$(CONFIG_ARCH_IXP4XX)           := ixp4xx
-machine-$(CONFIG_ARCH_KIRKWOOD)         := kirkwood
-machine-$(CONFIG_ARCH_KS8695)           := ks8695
-machine-$(CONFIG_ARCH_LPC32XX)          := lpc32xx
-machine-$(CONFIG_ARCH_MMP)              := mmp
-machine-$(CONFIG_ARCH_MSM)              := msm
-machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
-machine-$(CONFIG_ARCH_IMX_V4_V5)        := imx
-machine-$(CONFIG_ARCH_IMX_V6_V7)        := imx
-machine-$(CONFIG_ARCH_MXS)              := mxs
-machine-$(CONFIG_ARCH_MVEBU)            := mvebu
-machine-$(CONFIG_ARCH_NETX)             := netx
-machine-$(CONFIG_ARCH_NOMADIK)          := nomadik
-machine-$(CONFIG_ARCH_OMAP1)            := omap1
-machine-$(CONFIG_ARCH_OMAP2PLUS)        := omap2
-machine-$(CONFIG_ARCH_ORION5X)          := orion5x
-machine-$(CONFIG_ARCH_PICOXCELL)        := picoxcell
-machine-$(CONFIG_ARCH_PNX4008)          := pnx4008
-machine-$(CONFIG_ARCH_PRIMA2)           := prima2
-machine-$(CONFIG_ARCH_PXA)              := pxa
-machine-$(CONFIG_ARCH_REALVIEW)         := realview
-machine-$(CONFIG_ARCH_RPC)              := rpc
-machine-$(CONFIG_ARCH_S3C24XX)          := s3c24xx s3c2412 s3c2440
-machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
-machine-$(CONFIG_ARCH_S5P64X0)          := s5p64x0
-machine-$(CONFIG_ARCH_S5PC100)          := s5pc100
-machine-$(CONFIG_ARCH_S5PV210)          := s5pv210
-machine-$(CONFIG_ARCH_EXYNOS4)          := exynos
-machine-$(CONFIG_ARCH_EXYNOS5)          := exynos
-machine-$(CONFIG_ARCH_SA1100)           := sa1100
-machine-$(CONFIG_ARCH_SHARK)            := shark
-machine-$(CONFIG_ARCH_SHMOBILE)         := shmobile
-machine-$(CONFIG_ARCH_TEGRA)            := tegra
-machine-$(CONFIG_ARCH_U300)             := u300
-machine-$(CONFIG_ARCH_U8500)            := ux500
-machine-$(CONFIG_ARCH_VERSATILE)        := versatile
-machine-$(CONFIG_ARCH_VEXPRESS)         := vexpress
-machine-$(CONFIG_ARCH_VT8500)           := vt8500
-machine-$(CONFIG_ARCH_W90X900)          := w90x900
-machine-$(CONFIG_FOOTBRIDGE)            := footbridge
-machine-$(CONFIG_ARCH_SOCFPGA)          := socfpga
-machine-$(CONFIG_MACH_SPEAR1310)        := spear13xx
-machine-$(CONFIG_MACH_SPEAR1340)        := spear13xx
-machine-$(CONFIG_MACH_SPEAR300)         := spear3xx
-machine-$(CONFIG_MACH_SPEAR310)         := spear3xx
-machine-$(CONFIG_MACH_SPEAR320)         := spear3xx
-machine-$(CONFIG_MACH_SPEAR600)         := spear6xx
-machine-$(CONFIG_ARCH_ZYNQ)             := zynq
+machine-$(CONFIG_ARCH_AT91)             += at91
+machine-$(CONFIG_ARCH_BCM2835)          += bcm2835
+machine-$(CONFIG_ARCH_BCMRING)          += bcmring
+machine-$(CONFIG_ARCH_CLPS711X)         += clps711x
+machine-$(CONFIG_ARCH_CNS3XXX)          += cns3xxx
+machine-$(CONFIG_ARCH_DAVINCI)          += davinci
+machine-$(CONFIG_ARCH_DOVE)             += dove
+machine-$(CONFIG_ARCH_EBSA110)          += ebsa110
+machine-$(CONFIG_ARCH_EP93XX)           += ep93xx
+machine-$(CONFIG_ARCH_GEMINI)           += gemini
+machine-$(CONFIG_ARCH_H720X)            += h720x
+machine-$(CONFIG_ARCH_HIGHBANK)         += highbank
+machine-$(CONFIG_ARCH_INTEGRATOR)       += integrator
+machine-$(CONFIG_ARCH_IOP13XX)          += iop13xx
+machine-$(CONFIG_ARCH_IOP32X)           += iop32x
+machine-$(CONFIG_ARCH_IOP33X)           += iop33x
+machine-$(CONFIG_ARCH_IXP4XX)           += ixp4xx
+machine-$(CONFIG_ARCH_KIRKWOOD)         += kirkwood
+machine-$(CONFIG_ARCH_KS8695)           += ks8695
+machine-$(CONFIG_ARCH_LPC32XX)          += lpc32xx
+machine-$(CONFIG_ARCH_MMP)              += mmp
+machine-$(CONFIG_ARCH_MSM)              += msm
+machine-$(CONFIG_ARCH_MV78XX0)          += mv78xx0
+machine-$(CONFIG_ARCH_MXC)              += imx
+machine-$(CONFIG_ARCH_MXS)              += mxs
+machine-$(CONFIG_ARCH_MVEBU)            += mvebu
+machine-$(CONFIG_ARCH_NETX)             += netx
+machine-$(CONFIG_ARCH_NOMADIK)          += nomadik
+machine-$(CONFIG_ARCH_OMAP1)            += omap1
+machine-$(CONFIG_ARCH_OMAP2PLUS)        += omap2
+machine-$(CONFIG_ARCH_ORION5X)          += orion5x
+machine-$(CONFIG_ARCH_PICOXCELL)        += picoxcell
+machine-$(CONFIG_ARCH_PRIMA2)           += prima2
+machine-$(CONFIG_ARCH_PXA)              += pxa
+machine-$(CONFIG_ARCH_REALVIEW)         += realview
+machine-$(CONFIG_ARCH_RPC)              += rpc
+machine-$(CONFIG_ARCH_S3C24XX)          += s3c24xx s3c2412 s3c2440
+machine-$(CONFIG_ARCH_S3C64XX)          += s3c64xx
+machine-$(CONFIG_ARCH_S5P64X0)          += s5p64x0
+machine-$(CONFIG_ARCH_S5PC100)          += s5pc100
+machine-$(CONFIG_ARCH_S5PV210)          += s5pv210
+machine-$(CONFIG_ARCH_EXYNOS)           += exynos
+machine-$(CONFIG_ARCH_SA1100)           += sa1100
+machine-$(CONFIG_ARCH_SHARK)            += shark
+machine-$(CONFIG_ARCH_SHMOBILE)         += shmobile
+machine-$(CONFIG_ARCH_TEGRA)            += tegra
+machine-$(CONFIG_ARCH_U300)             += u300
+machine-$(CONFIG_ARCH_U8500)            += ux500
+machine-$(CONFIG_ARCH_VERSATILE)        += versatile
+machine-$(CONFIG_ARCH_VEXPRESS)         += vexpress
+machine-$(CONFIG_ARCH_VT8500)           += vt8500
+machine-$(CONFIG_ARCH_W90X900)          += w90x900
+machine-$(CONFIG_FOOTBRIDGE)            += footbridge
+machine-$(CONFIG_ARCH_SOCFPGA)          += socfpga
+machine-$(CONFIG_ARCH_SPEAR13XX)        += spear13xx
+machine-$(CONFIG_ARCH_SPEAR3XX)         += spear3xx
+machine-$(CONFIG_MACH_SPEAR600)         += spear6xx
+machine-$(CONFIG_ARCH_ZYNQ)             += zynq
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-plat-$(CONFIG_ARCH_MXC)         := mxc
-plat-$(CONFIG_ARCH_OMAP)        := omap
-plat-$(CONFIG_ARCH_S3C64XX)     := samsung
-plat-$(CONFIG_ARCH_ZYNQ)        := versatile
-plat-$(CONFIG_PLAT_IOP)         := iop
-plat-$(CONFIG_PLAT_NOMADIK)     := nomadik
-plat-$(CONFIG_PLAT_ORION)       := orion
-plat-$(CONFIG_PLAT_PXA)         := pxa
-plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx samsung
-plat-$(CONFIG_PLAT_S5P)         := samsung
-plat-$(CONFIG_PLAT_SPEAR)       := spear
-plat-$(CONFIG_PLAT_VERSATILE)   := versatile
+plat-$(CONFIG_ARCH_MXC)         += mxc
+plat-$(CONFIG_ARCH_OMAP)        += omap
+plat-$(CONFIG_ARCH_S3C64XX)     += samsung
+plat-$(CONFIG_ARCH_ZYNQ)        += versatile
+plat-$(CONFIG_PLAT_IOP)         += iop
+plat-$(CONFIG_PLAT_NOMADIK)     += nomadik
+plat-$(CONFIG_PLAT_ORION)       += orion
+plat-$(CONFIG_PLAT_PXA)         += pxa
+plat-$(CONFIG_PLAT_S3C24XX)     += s3c24xx samsung
+plat-$(CONFIG_PLAT_S5P)         += samsung
+plat-$(CONFIG_PLAT_SPEAR)       += spear
+plat-$(CONFIG_PLAT_VERSATILE)   += versatile
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
@@ -230,15 +225,20 @@ MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
 else
 MACHINE  :=
 endif
+ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
+MACHINE  :=
+endif
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
 
+ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
 ifeq ($(KBUILD_SRC),)
 KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
 else
 KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
 endif
+endif
 
 export  TEXT_OFFSET GZFLAGS MMUEXT
 
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index c877087d2000..3fdab016aa5c 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -15,6 +15,8 @@ ifneq ($(MACHINE),)
 include $(srctree)/$(MACHINE)/Makefile.boot
 endif
 
+include $(srctree)/arch/arm/boot/dts/Makefile
+
 # Note: the following conditions must always be true:
 #   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 8e2a8fca5ed2..df899834d84e 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -25,7 +25,13 @@ unsigned int __machine_arch_type;
 static void putstr(const char *ptr);
 extern void error(char *x);
 
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+static inline void putc(int c) {}
+static inline void flush(void) {}
+static inline void arch_decomp_setup(void) {}
+#else
 #include <mach/uncompress.h>
+#endif
 
 #ifdef CONFIG_DEBUG_ICEDCC
 
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
new file mode 100644
index 000000000000..d4ad2df08920
--- /dev/null
+++ b/arch/arm/boot/dts/Makefile
@@ -0,0 +1,106 @@
+ifeq ($(CONFIG_OF),y)
+
+dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
+        at91sam9263ek.dtb \
+        at91sam9g20ek_2mmc.dtb \
+        at91sam9g20ek.dtb \
+        at91sam9g25ek.dtb \
+        at91sam9m10g45ek.dtb \
+        at91sam9n12ek.dtb \
+        ethernut5.dtb \
+        evk-pro3.dtb \
+        kizbox.dtb \
+        tny_a9260.dtb \
+        tny_a9263.dtb \
+        tny_a9g20.dtb \
+        usb_a9260.dtb \
+        usb_a9263.dtb \
+        usb_a9g20.dtb
+dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
+        dove-cubox.dtb \
+        dove-dove-db.dtb
+dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
+        exynos4210-smdkv310.dtb \
+        exynos5250-smdk5250.dtb
+dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
+dtb-$(CONFIG_ARCH_IMX5) += imx51-babbage.dtb \
+        imx53-ard.dtb \
+        imx53-evk.dtb \
+        imx53-qsb.dtb \
+        imx53-smd.dtb
+dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
+        imx6q-sabrelite.dtb \
+        imx6q-sabresd.dtb
+dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
+dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
+        kirkwood-dns325.dtb \
+        kirkwood-dockstar.dtb \
+        kirkwood-dreamplug.dtb \
+        kirkwood-goflexnet.dtb \
+        kirkwood-ib62x0.dtb \
+        kirkwood-iconnect.dtb \
+        kirkwood-iomega_ix2_200.dtb \
+        kirkwood-km_kirkwood.dtb \
+        kirkwood-lschlv2.dtb \
+        kirkwood-lsxhl.dtb \
+        kirkwood-ts219-6281.dtb \
+        kirkwood-ts219-6282.dtb
+dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
+        msm8960-cdp.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
+        armada-xp-db.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
+        imx53-ard.dtb \
+        imx53-evk.dtb \
+        imx53-qsb.dtb \
+        imx53-smd.dtb \
+        imx6q-arm2.dtb \
+        imx6q-sabrelite.dtb \
+        imx6q-sabresd.dtb
+dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
+        imx23-olinuxino.dtb \
+        imx23-stmp378x_devb.dtb \
+        imx28-apx4devkit.dtb \
+        imx28-cfa10036.dtb \
+        imx28-cfa10049.dtb \
+        imx28-evk.dtb \
+        imx28-m28evk.dtb \
+        imx28-tx28.dtb
+dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
+        omap3-beagle-xm.dtb \
+        omap3-evm.dtb \
+        omap3-tobi.dtb \
+        omap4-panda.dtb \
+        omap4-pandaES.dtb \
+        omap4-var_som.dtb \
+        omap4-sdp.dtb \
+        omap5-evm.dtb
+dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+dtb-$(CONFIG_ARCH_U8500) += snowball.dtb
+dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
+        r8a7740-armadillo800eva.dtb \
+        sh73a0-kzm9g.dtb
+dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
+        spear1340-evb.dtb
+dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
+        spear310-evb.dtb \
+        spear320-evb.dtb
+dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+        tegra20-medcom-wide.dtb \
+        tegra20-paz00.dtb \
+        tegra20-plutux.dtb \
+        tegra20-seaboard.dtb \
+        tegra20-tec.dtb \
+        tegra20-trimslice.dtb \
+        tegra20-ventana.dtb \
+        tegra20-whistler.dtb \
+        tegra30-cardhu-a02.dtb \
+        tegra30-cardhu-a04.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
+        vexpress-v2p-ca9.dtb \
+        vexpress-v2p-ca15-tc1.dtb \
+        vexpress-v2p-ca15_a7.dtb
+
+endif
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a9af4db7234c..c634f87e230e 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -17,4 +17,64 @@
                 device_type = "memory";
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
+
+        ocp {
+                uart1: serial@44e09000 {
+                        status = "okay";
+                };
+
+                i2c1: i2c@44e0b000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+
+                        tps: tps@24 {
+                                reg = <0x24>;
+                        };
+
+                };
+        };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+        regulators {
+                dcdc1_reg: regulator@0 {
+                        regulator-always-on;
+                };
+
+                dcdc2_reg: regulator@1 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1325000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                dcdc3_reg: regulator@2 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo1_reg: regulator@3 {
+                        regulator-always-on;
+                };
+
+                ldo2_reg: regulator@4 {
+                        regulator-always-on;
+                };
+
+                ldo3_reg: regulator@5 {
+                        regulator-always-on;
+                };
+
+                ldo4_reg: regulator@6 {
+                        regulator-always-on;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d6a97d9eff72..185d6325a458 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -17,4 +17,104 @@
                 device_type = "memory";
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
+
+        ocp {
+                uart1: serial@44e09000 {
+                        status = "okay";
+                };
+
+                i2c1: i2c@44e0b000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+
+                        tps: tps@2d {
+                                reg = <0x2d>;
+                        };
+                };
+        };
+
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+};
+
+/include/ "tps65910.dtsi"
+
+&tps {
+        vcc1-supply = <&vbat>;
+        vcc2-supply = <&vbat>;
+        vcc3-supply = <&vbat>;
+        vcc4-supply = <&vbat>;
+        vcc5-supply = <&vbat>;
+        vcc6-supply = <&vbat>;
+        vcc7-supply = <&vbat>;
+        vccio-supply = <&vbat>;
+
+        regulators {
+                vrtc_reg: regulator@0 {
+                        regulator-always-on;
+                };
+
+                vio_reg: regulator@1 {
+                        regulator-always-on;
+                };
+
+                vdd1_reg: regulator@2 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1312500>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vdd2_reg: regulator@3 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vdd3_reg: regulator@4 {
+                        regulator-always-on;
+                };
+
+                vdig1_reg: regulator@5 {
+                        regulator-always-on;
+                };
+
+                vdig2_reg: regulator@6 {
+                        regulator-always-on;
+                };
+
+                vpll_reg: regulator@7 {
+                        regulator-always-on;
+                };
+
+                vdac_reg: regulator@8 {
+                        regulator-always-on;
+                };
+
+                vaux1_reg: regulator@9 {
+                        regulator-always-on;
+                };
+
+                vaux2_reg: regulator@10 {
+                        regulator-always-on;
+                };
+
+                vaux33_reg: regulator@11 {
+                        regulator-always-on;
+                };
+
+                vmmc_reg: regulator@12 {
+                        regulator-always-on;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bd0cff3f808c..bb31bff01998 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -69,95 +69,146 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        reg = <0x44e07000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <96>;
                 };
 
-                gpio2: gpio@4804C000 {
+                gpio2: gpio@4804c000 {
                         compatible = "ti,omap4-gpio";
                         ti,hwmods = "gpio2";
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        reg = <0x4804c000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <98>;
                 };
 
-                gpio3: gpio@481AC000 {
+                gpio3: gpio@481ac000 {
                         compatible = "ti,omap4-gpio";
                         ti,hwmods = "gpio3";
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        reg = <0x481ac000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <32>;
                 };
 
-                gpio4: gpio@481AE000 {
+                gpio4: gpio@481ae000 {
                         compatible = "ti,omap4-gpio";
                         ti,hwmods = "gpio4";
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        reg = <0x481ae000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <62>;
                 };
 
-                uart1: serial@44E09000 {
+                uart1: serial@44e09000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
+                        reg = <0x44e09000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <72>;
+                        status = "disabled";
                 };
 
                 uart2: serial@48022000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
+                        reg = <0x48022000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <73>;
+                        status = "disabled";
                 };
 
                 uart3: serial@48024000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
+                        reg = <0x48024000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <74>;
+                        status = "disabled";
                 };
 
-                uart4: serial@481A6000 {
+                uart4: serial@481a6000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
+                        reg = <0x481a6000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <44>;
+                        status = "disabled";
                 };
 
-                uart5: serial@481A8000 {
+                uart5: serial@481a8000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
+                        reg = <0x481a8000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <45>;
+                        status = "disabled";
                 };
 
-                uart6: serial@481AA000 {
+                uart6: serial@481aa000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
+                        reg = <0x481aa000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <46>;
+                        status = "disabled";
                 };
 
-                i2c1: i2c@44E0B000 {
+                i2c1: i2c@44e0b000 {
                         compatible = "ti,omap4-i2c";
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c1";
+                        reg = <0x44e0b000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <70>;
+                        status = "disabled";
                 };
 
-                i2c2: i2c@4802A000 {
+                i2c2: i2c@4802a000 {
                         compatible = "ti,omap4-i2c";
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c2";
+                        reg = <0x4802a000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <71>;
+                        status = "disabled";
                 };
 
-                i2c3: i2c@4819C000 {
+                i2c3: i2c@4819c000 {
                         compatible = "ti,omap4-i2c";
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c3";
+                        reg = <0x4819c000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <30>;
+                        status = "disabled";
                 };
 
                 wdt2: wdt@44e35000 {
                         compatible = "ti,omap3-wdt";
                         ti,hwmods = "wd_timer2";
+                        reg = <0x44e35000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <91>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932a5a7d..16cc82cdaa81 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,11 @@
                                reg = <0xd0020300 0x30>;
                                interrupts = <37>, <38>, <39>, <40>;
                 };
+
+                addr-decoding@d0020000 {
+                        compatible = "marvell,armada-addr-decoding-controller";
+                        reg = <0xd0020000 0x258>;
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc83332..2069151afe01 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -21,6 +21,12 @@
         model = "Marvell Armada 370 family SoC";
         compatible = "marvell,armada370", "marvell,armada-370-xp";
 
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+
         mpic: interrupt-controller@d0020000 {
               reg = <0xd0020a00 0x1d0>,
                     <0xd0021870 0x58>;
@@ -31,5 +37,43 @@
                                 compatible = "marvell,armada-370-xp-system-controller";
                                 reg = <0xd0018200 0x100>;
                 };
+
+                pinctrl {
+                        compatible = "marvell,mv88f6710-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018100 0x40>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <82>, <83>, <84>, <85>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018140 0x40>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <87>, <88>, <89>, <90>;
+                };
+
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018180 0x40>;
+                        ngpios = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <91>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f97040d4258d..b1fc728515e9 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,11 +14,11 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 
 / {
         model = "Marvell Armada XP Evaluation Board";
-        compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+        compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
new file mode 100644
index 000000000000..ea355192be6f
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP MV78230 SoC";
+        compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+        };
+
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78230-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <17>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
new file mode 100644
index 000000000000..2057863f3dfa
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP MV78260 SoC";
+        compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78260-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>, <23>;
+                };
+
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018180 0x40>,
+                            <0xd0018870 0x30>;
+                        ngpios = <3>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
new file mode 100644
index 000000000000..ffac98373792
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP MV78460 SoC";
+        compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78460-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>, <23>;
+                };
+
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018180 0x40>,
+                            <0xd0018870 0x30>;
+                        ngpios = <3>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <24>;
+                };
+        };
+ };
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
new file mode 100644
index 000000000000..7dd860f83f96
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/memreserve/ 0x0c000000 0x04000000;
+/include/ "bcm2835.dtsi"
+
+/ {
+        compatible = "raspberrypi,model-b", "brcm,bcm2835";
+        model = "Raspberry Pi Model B";
+
+        memory {
+                reg = <0 0x10000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
new file mode 100644
index 000000000000..0b619398532c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -0,0 +1,39 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "brcm,bcm2835";
+        model = "BCM2835";
+        interrupt-parent = <&intc>;
+
+        chosen {
+                bootargs = "earlyprintk console=ttyAMA0";
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x7e000000 0x20000000 0x02000000>;
+
+                timer {
+                        compatible = "brcm,bcm2835-system-timer";
+                        reg = <0x7e003000 0x1000>;
+                        interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
+                        clock-frequency = <1000000>;
+                };
+
+                intc: interrupt-controller {
+                        compatible = "brcm,bcm2835-armctrl-ic";
+                        reg = <0x7e00b200 0x200>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                uart@20201000 {
+                        compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+                        reg = <0x7e201000 0x1000>;
+                        interrupts = <2 25>;
+                        clock-frequency = <3000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
new file mode 100644
index 000000000000..61a8062e56de
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+        model = "Compulab CM-A510";
+        compatible = "compulab,cm-a510", "marvell,dove";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+        status = "okay";
+
+        /* spi0.0: 4M Flash Winbond W25Q32BV */
+        spi-flash@0 {
+                compatible = "st,w25q32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+          status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
new file mode 100644
index 000000000000..0adbd5a38095
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+        model = "SolidRun CuBox";
+        compatible = "solidrun,cubox", "marvell,dove";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                power {
+                        label = "Power";
+                        gpios = <&gpio0 18 1>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
+
+&uart0 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+
+&spi0 {
+        status = "okay";
+
+        /* spi0.0: 4M Flash Winbond W25Q32BV */
+        spi-flash@0 {
+                compatible = "st,w25q32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
new file mode 100644
index 000000000000..e5a920beab45
--- /dev/null
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+        model = "Marvell DB-MV88AP510-BP Development Board";
+        compatible = "marvell,dove-db", "marvell,dove";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+        status = "okay";
+
+        /* spi0.0: 4M Flash ST-M25P32-VMF6P */
+        spi-flash@0 {
+                compatible = "st,m25p32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+          status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
new file mode 100644
index 000000000000..96fb824b5e6e
--- /dev/null
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -0,0 +1,143 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "marvell,dove";
+        model = "Marvell Armada 88AP510 SoC";
+
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller {
+                compatible = "marvell,orion-intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xf1020204 0x04>,
+                      <0xf1020214 0x04>;
+        };
+
+        mbus@f1000000 {
+                compatible = "simple-bus";
+                ranges = <0 0xf1000000 0x4000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                uart0: serial@12000 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <7>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                uart1: serial@12100 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <8>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                uart2: serial@12200 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <9>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                uart3: serial@12300 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <10>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                wdt: wdt@20300 {
+                        compatible = "marvell,orion-wdt";
+                        reg = <0x20300 0x28>;
+                };
+
+                gpio0: gpio@d0400 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xd0400 0x20>;
+                        ngpio = <32>;
+                        interrupts = <12>, <13>, <14>, <60>;
+                };
+
+                gpio1: gpio@d0420 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xd0420 0x20>;
+                        ngpio = <32>;
+                        interrupts = <61>;
+                };
+
+                gpio2: gpio@e8400 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xe8400 0x0c>;
+                        ngpio = <8>;
+                };
+
+                spi0: spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        interrupts = <6>;
+                        reg = <0x10600 0x28>;
+                        status = "disabled";
+                };
+
+                spi1: spi@14600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        interrupts = <5>;
+                        reg = <0x14600 0x28>;
+                        status = "disabled";
+                };
+
+                i2c0: i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <11>;
+                        clock-frequency = <400000>;
+                        timeout-ms = <1000>;
+                        status = "disabled";
+                };
+
+                sdio0: sdio@92000 {
+                        compatible = "marvell,dove-sdhci";
+                        reg = <0x92000 0x100>;
+                        interrupts = <35>, <37>;
+                        status = "disabled";
+                };
+
+                sdio1: sdio@90000 {
+                        compatible = "marvell,dove-sdhci";
+                        reg = <0x90000 0x100>;
+                        interrupts = <36>, <38>;
+                        status = "disabled";
+                };
+
+                sata0: sata@a0000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0xa0000 0x2400>;
+                        interrupts = <62>;
+                        nr-ports = <1>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
index d79b28d9c963..a4ba31b23c88 100644
--- a/arch/arm/boot/dts/ea3250.dts
+++ b/arch/arm/boot/dts/ea3250.dts
@@ -166,9 +166,116 @@
                 #size-cells = <0>;
                 autorepeat;
                 button@21 {
-                        label = "GPIO Key UP";
+                        label = "Interrupt Key";
                         linux,code = <103>;
                         gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
                 };
+                key1 {
+                        label = "KEY1";
+                        linux,code = <1>;
+                        gpios = <&pca9532 0 0>;
+                };
+                key2 {
+                        label = "KEY2";
+                        linux,code = <2>;
+                        gpios = <&pca9532 1 0>;
+                };
+                key3 {
+                        label = "KEY3";
+                        linux,code = <3>;
+                        gpios = <&pca9532 2 0>;
+                };
+                key4 {
+                        label = "KEY4";
+                        linux,code = <4>;
+                        gpios = <&pca9532 3 0>;
+                };
+                joy0 {
+                        label = "Joystick Key 0";
+                        linux,code = <10>;
+                        gpios = <&gpio 2 0 0>; /* P2.0 */
+                };
+                joy1 {
+                        label = "Joystick Key 1";
+                        linux,code = <11>;
+                        gpios = <&gpio 2 1 0>; /* P2.1 */
+                };
+                joy2 {
+                        label = "Joystick Key 2";
+                        linux,code = <12>;
+                        gpios = <&gpio 2 2 0>; /* P2.2 */
+                };
+                joy3 {
+                        label = "Joystick Key 3";
+                        linux,code = <13>;
+                        gpios = <&gpio 2 3 0>; /* P2.3 */
+                };
+                joy4 {
+                        label = "Joystick Key 4";
+                        linux,code = <14>;
+                        gpios = <&gpio 2 4 0>; /* P2.4 */
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                /* LEDs on OEM Board */
+
+                led1 {
+                        gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
+                        linux,default-trigger = "timer";
+                        default-state = "off";
+                };
+
+                led2 {
+                        gpios = <&gpio 2 10 1>; /* P2.10, active low */
+                        default-state = "off";
+                };
+
+                led3 {
+                        gpios = <&gpio 2 11 1>; /* P2.11, active low */
+                        default-state = "off";
+                };
+
+                led4 {
+                        gpios = <&gpio 2 12 1>; /* P2.12, active low */
+                        default-state = "off";
+                };
+
+                /* LEDs on Base Board */
+
+                lede1 {
+                        gpios = <&pca9532 8 0>;
+                        default-state = "off";
+                };
+                lede2 {
+                        gpios = <&pca9532 9 0>;
+                        default-state = "off";
+                };
+                lede3 {
+                        gpios = <&pca9532 10 0>;
+                        default-state = "off";
+                };
+                lede4 {
+                        gpios = <&pca9532 11 0>;
+                        default-state = "off";
+                };
+                lede5 {
+                        gpios = <&pca9532 12 0>;
+                        default-state = "off";
+                };
+                lede6 {
+                        gpios = <&pca9532 13 0>;
+                        default-state = "off";
+                };
+                lede7 {
+                        gpios = <&pca9532 14 0>;
+                        default-state = "off";
+                };
+                lede8 {
+                        gpios = <&pca9532 15 0>;
+                        default-state = "off";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
new file mode 100644
index 000000000000..f97f70f83374
--- /dev/null
+++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Common devices used in different OMAP boards
+ */
+
+/ {
+        elpida_ECB240ABACN: lpddr2 {
+                compatible      = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+                density         = <2048>;
+                io-width        = <32>;
+
+                tRPab-min-tck   = <3>;
+                tRCD-min-tck    = <3>;
+                tWR-min-tck     = <3>;
+                tRASmin-min-tck = <3>;
+                tRRD-min-tck    = <2>;
+                tWTR-min-tck    = <2>;
+                tXP-min-tck     = <2>;
+                tRTP-min-tck    = <2>;
+                tCKE-min-tck    = <3>;
+                tCKESR-min-tck  = <3>;
+                tFAW-min-tck    = <8>;
+
+                timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+                        compatible      = "jedec,lpddr2-timings";
+                        min-freq        = <10000000>;
+                        max-freq        = <400000000>;
+                        tRPab           = <21000>;
+                        tRCD            = <18000>;
+                        tWR             = <15000>;
+                        tRAS-min        = <42000>;
+                        tRRD            = <10000>;
+                        tWTR            = <7500>;
+                        tXP             = <7500>;
+                        tRTP            = <7500>;
+                        tCKESR          = <15000>;
+                        tDQSCK-max      = <5500>;
+                        tFAW            = <50000>;
+                        tZQCS           = <90000>;
+                        tZQCL           = <360000>;
+                        tZQinit         = <1000000>;
+                        tRAS-max-ns     = <70000>;
+                        tDQSCK-max-derated = <6000>;
+                };
+
+                timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+                        compatible      = "jedec,lpddr2-timings";
+                        min-freq        = <10000000>;
+                        max-freq        = <200000000>;
+                        tRPab           = <21000>;
+                        tRCD            = <18000>;
+                        tWR             = <15000>;
+                        tRAS-min        = <42000>;
+                        tRRD            = <10000>;
+                        tWTR            = <10000>;
+                        tXP             = <7500>;
+                        tRTP            = <7500>;
+                        tCKESR          = <15000>;
+                        tDQSCK-max      = <5500>;
+                        tFAW            = <50000>;
+                        tZQCS           = <90000>;
+                        tZQCL           = <360000>;
+                        tZQinit         = <1000000>;
+                        tRAS-max-ns     = <70000>;
+                        tDQSCK-max-derated = <6000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index e3486f486b40..035c13f9d3c0 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -42,12 +42,13 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
                                                 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
                                                 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
+                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
                                         >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 20912b1d8893..384d8b66f337 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -31,6 +31,22 @@
                                 bus-width = <4>;
                                 status = "okay";
                         };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
+                                                0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
                 };
 
                 apbx@80040000 {
@@ -39,6 +55,47 @@
                                 pinctrl-0 = <&duart_pins_a>;
                                 status = "okay";
                         };
+
+                        auart0: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_2pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
+                        gpio = <&gpio0 17 0>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "green";
+                        gpios = <&gpio2 1 0>;
+                        linux,default-trigger = "default-on";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 757a327ff3e8..85c3864b6a56 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -36,7 +36,7 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index e6138310e5ce..3f3b6fc229b3 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -52,6 +52,7 @@
                         dma-apbh@80004000 {
                                 compatible = "fsl,imx23-dma-apbh";
                                 reg = <0x80004000 0x2000>;
+                                clocks = <&clks 15>;
                         };
 
                         ecc@80008000 {
@@ -67,6 +68,7 @@
                                 reg-names = "gpmi-nand", "bch";
                                 interrupts = <13>, <56>;
                                 interrupt-names = "gpmi-dma", "bch";
+                                clocks = <&clks 34>;
                                 fsl,gpmi-dma-channel = <4>;
                                 status = "disabled";
                         };
@@ -74,6 +76,7 @@
                         ssp0: ssp@80010000 {
                                 reg = <0x80010000 0x2000>;
                                 interrupts = <15 14>;
+                                clocks = <&clks 33>;
                                 fsl,ssp-dma-channel = <1>;
                                 status = "disabled";
                         };
@@ -140,6 +143,17 @@
                                         fsl,pull-up = <0>;
                                 };
 
+                                auart0_2pins_a: auart0-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
+                                                0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                                 gpmi_pins_a: gpmi-nand@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -183,7 +197,6 @@
                                                 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
                                                 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
                                                 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
-                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
                                                 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
                                         >;
                                         fsl,drive-strength = <1>;
@@ -280,6 +293,7 @@
                         dma-apbx@80024000 {
                                 compatible = "fsl,imx23-dma-apbx";
                                 reg = <0x80024000 0x2000>;
+                                clocks = <&clks 16>;
                         };
 
                         dcp@80028000 {
@@ -306,12 +320,14 @@
                                 compatible = "fsl,imx23-lcdif";
                                 reg = <0x80030000 2000>;
                                 interrupts = <46 45>;
+                                clocks = <&clks 38>;
                                 status = "disabled";
                         };
 
                         ssp1: ssp@80034000 {
                                 reg = <0x80034000 0x2000>;
                                 interrupts = <2 20>;
+                                clocks = <&clks 33>;
                                 fsl,ssp-dma-channel = <2>;
                                 status = "disabled";
                         };
@@ -329,9 +345,10 @@
                         reg = <0x80040000 0x40000>;
                         ranges;
 
-                        clkctl@80040000 {
+                        clks: clkctrl@80040000 {
+                                compatible = "fsl,imx23-clkctrl";
                                 reg = <0x80040000 0x2000>;
-                                status = "disabled";
+                                #clock-cells = <1>;
                         };
 
                         saif0: saif@80042000 {
@@ -383,6 +400,7 @@
                         pwm: pwm@80064000 {
                                 compatible = "fsl,imx23-pwm";
                                 reg = <0x80064000 0x2000>;
+                                clocks = <&clks 30>;
                                 #pwm-cells = <2>;
                                 fsl,pwm-number = <5>;
                                 status = "disabled";
@@ -397,6 +415,7 @@
                                 compatible = "fsl,imx23-auart";
                                 reg = <0x8006c000 0x2000>;
                                 interrupts = <24 25 23>;
+                                clocks = <&clks 32>;
                                 status = "disabled";
                         };
 
@@ -404,6 +423,7 @@
                                 compatible = "fsl,imx23-auart";
                                 reg = <0x8006e000 0x2000>;
                                 interrupts = <59 60 58>;
+                                clocks = <&clks 32>;
                                 status = "disabled";
                         };
 
@@ -411,11 +431,15 @@
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x80070000 0x2000>;
                                 interrupts = <0>;
+                                clocks = <&clks 32>, <&clks 16>;
+                                clock-names = "uart", "apb_pclk";
                                 status = "disabled";
                         };
 
-                        usbphy@8007c000 {
+                        usbphy0: usbphy@8007c000 {
+                                compatible = "fsl,imx23-usbphy";
                                 reg = <0x8007c000 0x2000>;
+                                clocks = <&clks 41>;
                                 status = "disabled";
                         };
                 };
@@ -428,8 +452,12 @@
                 reg = <0x80080000 0x80000>;
                 ranges;
 
-                usbctrl@80080000 {
+                usb0: usb@80080000 {
+                        compatible = "fsl,imx23-usb", "fsl,imx27-usb";
                         reg = <0x80080000 0x40000>;
+                        interrupts = <11>;
+                        fsl,usbphy = <&usbphy0>;
+                        clocks = <&clks 40>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 2b0ff60247a4..af50469e34b2 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -23,10 +23,6 @@
         soc {
                 aipi@10000000 { /* aipi */
 
-                        wdog@10002000 {
-                                status = "okay";
-                        };
-
                         serial@1000a000 {
                                 fsl,uart-has-rtscts;
                                 status = "okay";
@@ -49,7 +45,7 @@
                         i2c@1001d000 {
                                 clock-frequency = <400000>;
                                 status = "okay";
-                                at24@4c {
+                                at24@52 {
                                         compatible = "at,24c32";
                                         pagesize = <32>;
                                         reg = <0x52>;
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 5303ab680a34..3e54f1498841 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -62,7 +62,6 @@
                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
                                 reg = <0x10002000 0x4000>;
                                 interrupts = <27>;
-                                status = "disabled";
                         };
 
                         uart1: serial@1000a000 {
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index b383417a558f..5171667a7763 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -37,7 +37,7 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
new file mode 100644
index 000000000000..05c892e931e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+
+/ {
+        model = "Crystalfontz CFA-10049 Board";
+        compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
+
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                spi3_pins_cfa10049: spi3-cfa10049@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
+                                                0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
+                                                0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
+                                                0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+                        };
+
+                        ssp3: ssp@80016000 {
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi3_pins_cfa10049>;
+                                status = "okay";
+
+                                gpio5: gpio5@0 {
+                                        compatible = "fairchild,74hc595";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <0>;
+                                        registers-number = <2>;
+                                        spi-max-frequency = <100000>;
+                                };
+
+                                gpio6: gpio6@1 {
+                                        compatible = "fairchild,74hc595";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <1>;
+                                        registers-number = <4>;
+                                        spi-max-frequency = <100000>;
+                                };
+
+                        };
+                };
+
+                apbx@80040000 {
+                        i2c1: i2c@8005a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c1_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio0 7 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 773c0e84d1fb..a0ad71ca3a44 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -46,11 +46,28 @@
                                 wp-gpios = <&gpio0 28 0>;
                         };
 
+                        ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+
+                                flash: m25p80@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "sst,sst25vf016b";
+                                        spi-max-frequency = <40000000>;
+                                        reg = <0>;
+                                };
+                        };
+
                         pinctrl@80018000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
@@ -128,6 +145,10 @@
                                 status = "okay";
                         };
 
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+
                         i2c0: i2c@80058000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&i2c0_pins_a>;
@@ -140,6 +161,12 @@
                                         VDDIO-supply = <&reg_3p3v>;
 
                                 };
+
+                                at24@51 {
+                                        compatible = "at24,24c32";
+                                        pagesize = <32>;
+                                        reg = <0x51>;
+                                };
                         };
 
                         pwm: pwm@80064000 {
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 183a3fd2d859..3bab6b00c52d 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -23,6 +23,8 @@
         apb@80000000 {
                 apbh@80000000 {
                         gpmi-nand@8000c000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
                                 status = "okay";
@@ -61,19 +63,40 @@
                                              &mmc0_cd_cfg
                                              &mmc0_sck_cfg>;
                                 bus-width = <8>;
-                                wp-gpios = <&gpio3 10 1>;
+                                wp-gpios = <&gpio3 10 0>;
+                                vmmc-supply = <&reg_vddio_sd0>;
                                 status = "okay";
                         };
 
+                        ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+
+                                flash: m25p80@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "m25p80";
+                                        spi-max-frequency = <40000000>;
+                                        reg = <0>;
+                                };
+                        };
+
                         pinctrl@80018000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
+                                                0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
                                                 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
                                                 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
+                                                0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
+                                                0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
                                         >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
@@ -129,6 +152,7 @@
                         i2c0: i2c@80058000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&i2c0_pins_a>;
+                                clock-frequency = <400000>;
                                 status = "okay";
 
                                 sgtl5000: codec@0a {
@@ -151,32 +175,51 @@
                                 };
                         };
 
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+
                         duart: serial@80074000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&duart_pins_a>;
                                 status = "okay";
                         };
 
-                        auart0: serial@8006a000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&auart0_2pins_a>;
+                        usbphy0: usbphy@8007c000 {
                                 status = "okay";
                         };
 
-                        auart3: serial@80070000 {
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&auart3_pins_a>;
+                                pinctrl-0 = <&auart0_2pins_a>;
                                 status = "okay";
                         };
                 };
         };
 
         ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usbphy0_pins_a>;
+                        status = "okay";
+                };
+
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        status = "okay";
+                };
+
                 mac0: ethernet@800f0000 {
                         phy-mode = "rmii";
                         pinctrl-names = "default";
                         pinctrl-0 = <&mac0_pins_a>;
-                        phy-reset-gpios = <&gpio3 11 0>;
                         status = "okay";
                 };
 
@@ -198,6 +241,30 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                reg_vddio_sd0: vddio-sd0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "vddio-sd0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 28 0>;
+                };
+
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 12 0>;
+                };
+
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 13 0>;
+                };
         };
 
         sound {
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 62bf767409a6..37be532f0055 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -25,7 +25,7 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
@@ -34,6 +34,24 @@
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
+
+                                mac0_pins_gpio: mac0-gpio-mode@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
+                                                0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
+                                                0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
+                                                0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
+                                                0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
+                                                0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
+                                                0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
+                                                0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
+                                                0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                         };
                 };
 
@@ -72,8 +90,9 @@
         ahb@80080000 {
                 mac0: ethernet@800f0000 {
                         phy-mode = "rmii";
-                        pinctrl-names = "default";
+                        pinctrl-names = "default", "gpio_mode";
                         pinctrl-0 = <&mac0_pins_a>;
+                        pinctrl-1 = <&mac0_pins_gpio>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 3fa6d190fab4..724147eab84b 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -27,6 +27,8 @@
                 serial2 = &auart2;
                 serial3 = &auart3;
                 serial4 = &auart4;
+                ethernet0 = &mac0;
+                ethernet1 = &mac1;
         };
 
         cpus {
@@ -65,6 +67,7 @@
                         dma-apbh@80004000 {
                                 compatible = "fsl,imx28-dma-apbh";
                                 reg = <0x80004000 0x2000>;
+                                clocks = <&clks 25>;
                         };
 
                         perfmon@80006000 {
@@ -81,34 +84,47 @@
                                 reg-names = "gpmi-nand", "bch";
                                 interrupts = <88>, <41>;
                                 interrupt-names = "gpmi-dma", "bch";
+                                clocks = <&clks 50>;
                                 fsl,gpmi-dma-channel = <4>;
                                 status = "disabled";
                         };
 
                         ssp0: ssp@80010000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0x80010000 0x2000>;
                                 interrupts = <96 82>;
+                                clocks = <&clks 46>;
                                 fsl,ssp-dma-channel = <0>;
                                 status = "disabled";
                         };
 
                         ssp1: ssp@80012000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0x80012000 0x2000>;
                                 interrupts = <97 83>;
+                                clocks = <&clks 47>;
                                 fsl,ssp-dma-channel = <1>;
                                 status = "disabled";
                         };
 
                         ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0x80014000 0x2000>;
                                 interrupts = <98 84>;
+                                clocks = <&clks 48>;
                                 fsl,ssp-dma-channel = <2>;
                                 status = "disabled";
                         };
 
                         ssp3: ssp@80016000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0x80016000 0x2000>;
                                 interrupts = <99 85>;
+                                clocks = <&clks 49>;
                                 fsl,ssp-dma-channel = <3>;
                                 status = "disabled";
                         };
@@ -410,6 +426,28 @@
                                         fsl,pull-up = <1>;
                                 };
 
+                                i2c0_pins_b: i2c0@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
+                                                0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                i2c1_pins_a: i2c1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
+                                                0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
                                 saif0_pins_a: saif0@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -453,6 +491,16 @@
                                         fsl,pull-up = <0>;
                                 };
 
+                                pwm4_pins_a: pwm4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x31d0 /* MX28_PAD_PWM4__PWM_4 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                                 lcdif_24bit_pins_a: lcdif-24bit@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -507,6 +555,49 @@
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
+
+                                spi2_pins_a: spi2@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
+                                                0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
+                                                0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
+                                                0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                usbphy0_pins_a: usbphy0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                usbphy0_pins_b: usbphy0@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                usbphy1_pins_a: usbphy1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                         };
 
                         digctl@8001c000 {
@@ -523,6 +614,7 @@
                         dma-apbx@80024000 {
                                 compatible = "fsl,imx28-dma-apbx";
                                 reg = <0x80024000 0x2000>;
+                                clocks = <&clks 26>;
                         };
 
                         dcp@80028000 {
@@ -551,6 +643,7 @@
                                 compatible = "fsl,imx28-lcdif";
                                 reg = <0x80030000 0x2000>;
                                 interrupts = <38 86>;
+                                clocks = <&clks 55>;
                                 status = "disabled";
                         };
 
@@ -558,6 +651,8 @@
                                 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
                                 reg = <0x80032000 0x2000>;
                                 interrupts = <8>;
+                                clocks = <&clks 58>, <&clks 58>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -565,6 +660,8 @@
                                 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
                                 reg = <0x80034000 0x2000>;
                                 interrupts = <9>;
+                                clocks = <&clks 59>, <&clks 59>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -611,15 +708,17 @@
                         reg = <0x80040000 0x40000>;
                         ranges;
 
-                        clkctl@80040000 {
+                        clks: clkctrl@80040000 {
+                                compatible = "fsl,imx28-clkctrl";
                                 reg = <0x80040000 0x2000>;
-                                status = "disabled";
+                                #clock-cells = <1>;
                         };
 
                         saif0: saif@80042000 {
                                 compatible = "fsl,imx28-saif";
                                 reg = <0x80042000 0x2000>;
                                 interrupts = <59 80>;
+                                clocks = <&clks 53>;
                                 fsl,saif-dma-channel = <4>;
                                 status = "disabled";
                         };
@@ -633,12 +732,16 @@
                                 compatible = "fsl,imx28-saif";
                                 reg = <0x80046000 0x2000>;
                                 interrupts = <58 81>;
+                                clocks = <&clks 54>;
                                 fsl,saif-dma-channel = <5>;
                                 status = "disabled";
                         };
 
                         lradc@80050000 {
+                                compatible = "fsl,imx28-lradc";
                                 reg = <0x80050000 0x2000>;
+                                interrupts = <10 14 15 16 17 18 19
+                                                20 21 22 23 24 25>;
                                 status = "disabled";
                         };
 
@@ -677,6 +780,7 @@
                         pwm: pwm@80064000 {
                                 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
                                 reg = <0x80064000 0x2000>;
+                                clocks = <&clks 44>;
                                 #pwm-cells = <2>;
                                 fsl,pwm-number = <8>;
                                 status = "disabled";
@@ -691,6 +795,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006a000 0x2000>;
                                 interrupts = <112 70 71>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -698,6 +803,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006c000 0x2000>;
                                 interrupts = <113 72 73>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -705,6 +811,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006e000 0x2000>;
                                 interrupts = <114 74 75>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -712,6 +819,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x80070000 0x2000>;
                                 interrupts = <115 76 77>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -719,6 +827,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x80072000 0x2000>;
                                 interrupts = <116 78 79>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -726,18 +835,22 @@
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x80074000 0x1000>;
                                 interrupts = <47>;
+                                clocks = <&clks 45>, <&clks 26>;
+                                clock-names = "uart", "apb_pclk";
                                 status = "disabled";
                         };
 
                         usbphy0: usbphy@8007c000 {
                                 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x8007c000 0x2000>;
+                                clocks = <&clks 62>;
                                 status = "disabled";
                         };
 
                         usbphy1: usbphy@8007e000 {
                                 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x8007e000 0x2000>;
+                                clocks = <&clks 63>;
                                 status = "disabled";
                         };
                 };
@@ -754,6 +867,7 @@
                         compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                         reg = <0x80080000 0x10000>;
                         interrupts = <93>;
+                        clocks = <&clks 60>;
                         fsl,usbphy = <&usbphy0>;
                         status = "disabled";
                 };
@@ -762,6 +876,7 @@
                         compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                         reg = <0x80090000 0x10000>;
                         interrupts = <92>;
+                        clocks = <&clks 61>;
                         fsl,usbphy = <&usbphy1>;
                         status = "disabled";
                 };
@@ -775,6 +890,8 @@
                         compatible = "fsl,imx28-fec";
                         reg = <0x800f0000 0x4000>;
                         interrupts = <101>;
+                        clocks = <&clks 57>, <&clks 57>;
+                        clock-names = "ipg", "ahb";
                         status = "disabled";
                 };
 
@@ -782,6 +899,8 @@
                         compatible = "fsl,imx28-fec";
                         reg = <0x800f4000 0x4000>;
                         interrupts = <102>;
+                        clocks = <&clks 57>, <&clks 57>;
+                        clock-names = "ipg", "ahb";
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 59d9789e5508..cbd2b1c7487b 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,23 +25,31 @@
                 aips@70000000 { /* aips-1 */
                         spba@70000000 {
                                 esdhc@70004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                         fsl,cd-controller;
                                         fsl,wp-controller;
                                         status = "okay";
                                 };
 
                                 esdhc@70008000 { /* ESDHC2 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc2_1>;
                                         cd-gpios = <&gpio1 6 0>;
                                         wp-gpios = <&gpio1 5 0>;
                                         status = "okay";
                                 };
 
                                 uart3: serial@7000c000 {
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_uart3_1>;
                                         fsl,uart-has-rtscts;
                                         status = "okay";
                                 };
 
                                 ecspi@70010000 { /* ECSPI1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                         fsl,spi-num-chipselects = <2>;
                                         cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
                                         status = "okay";
@@ -169,31 +177,43 @@
                                 };
                         };
 
-                        wdog@73f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@73fa8000 {
-                                compatible = "fsl,imx51-iomuxc-babbage";
-                                reg = <0x73fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        694  0x20d5     /* MX51_PAD_GPIO1_0__SD1_CD */
+                                                        697  0x20d5     /* MX51_PAD_GPIO1_1__SD1_WP */
+                                                        737  0x100      /* MX51_PAD_GPIO1_5__GPIO1_5 */
+                                                        740  0x100      /* MX51_PAD_GPIO1_6__GPIO1_6 */
+                                                        121  0x5        /* MX51_PAD_EIM_A27__GPIO2_21 */
+                                                        402  0x85       /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
+                                                        405  0x85       /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@73fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                 fsl,uart-has-rtscts;
                                 status = "okay";
                         };
 
                         uart2: serial@73fc0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart2_1>;
                                 status = "okay";
                         };
                 };
 
                 aips@80000000 { /* aips-2 */
-                        sdma@83fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
-                        };
-
                         i2c@83fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                 status = "okay";
 
                                 sgtl5000: codec@0a {
@@ -206,10 +226,14 @@
                         };
 
                         audmux@83fd0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_audmux_1>;
                                 status = "okay";
                         };
 
                         ethernet@83fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                 phy-mode = "mii";
                                 status = "okay";
                         };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aba28dc87fc8..2f71a91ca98e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -130,6 +130,34 @@
                                 };
                         };
 
+                        usb@73f80000 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80000 0x0200>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+
+                        usb@73f80200 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80200 0x0200>;
+                                interrupts = <14>;
+                                status = "disabled";
+                        };
+
+                        usb@73f80400 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80400 0x0200>;
+                                interrupts = <16>;
+                                status = "disabled";
+                        };
+
+                        usb@73f80600 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80600 0x0200>;
+                                interrupts = <17>;
+                                status = "disabled";
+                        };
+
                         gpio1: gpio@73f84000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                 reg = <0x73f84000 0x4000>;
@@ -174,7 +202,6 @@
                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                 reg = <0x73f98000 0x4000>;
                                 interrupts = <58>;
-                                status = "disabled";
                         };
 
                         wdog@73f9c000 { /* WDOG2 */
@@ -184,6 +211,122 @@
                                 status = "disabled";
                         };
 
+                        iomuxc@73fa8000 {
+                                compatible = "fsl,imx51-iomuxc";
+                                reg = <0x73fa8000 0x4000>;
+
+                                audmux {
+                                        pinctrl_audmux_1: audmuxgrp-1 {
+                                                fsl,pins = <
+                                                        384 0x80000000  /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
+                                                        386 0x80000000  /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
+                                                        389 0x80000000  /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
+                                                        391 0x80000000  /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
+                                                >;
+                                        };
+                                };
+
+                                fec {
+                                        pinctrl_fec_1: fecgrp-1 {
+                                                fsl,pins = <
+                                                        128 0x80000000  /* MX51_PAD_EIM_EB2__FEC_MDIO */
+                                                        134 0x80000000  /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
+                                                        146 0x80000000  /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
+                                                        152 0x80000000  /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
+                                                        158 0x80000000  /* MX51_PAD_EIM_CS4__FEC_RX_ER */
+                                                        165 0x80000000  /* MX51_PAD_EIM_CS5__FEC_CRS */
+                                                        206 0x80000000  /* MX51_PAD_NANDF_RB2__FEC_COL */
+                                                        213 0x80000000  /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
+                                                        293 0x80000000  /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
+                                                        298 0x80000000  /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
+                                                        225 0x80000000  /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
+                                                        231 0x80000000  /* MX51_PAD_NANDF_CS3__FEC_MDC */
+                                                        237 0x80000000  /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
+                                                        243 0x80000000  /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
+                                                        250 0x80000000  /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
+                                                        255 0x80000000  /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
+                                                        260 0x80000000  /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
+                                                >;
+                                        };
+                                };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        398 0x185       /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
+                                                        394 0x185       /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
+                                                        409 0x185       /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
+                                                >;
+                                        };
+                                };
+
+                                esdhc1 {
+                                        pinctrl_esdhc1_1: esdhc1grp-1 {
+                                                fsl,pins = <
+                                                        666 0x400020d5  /* MX51_PAD_SD1_CMD__SD1_CMD */
+                                                        669 0x20d5      /* MX51_PAD_SD1_CLK__SD1_CLK */
+                                                        672 0x20d5      /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
+                                                        678 0x20d5      /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
+                                                        684 0x20d5      /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
+                                                        691 0x20d5      /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
+                                                >;
+                                        };
+                                };
+
+                                esdhc2 {
+                                        pinctrl_esdhc2_1: esdhc2grp-1 {
+                                                fsl,pins = <
+                                                        704 0x400020d5  /* MX51_PAD_SD2_CMD__SD2_CMD */
+                                                        707 0x20d5      /* MX51_PAD_SD2_CLK__SD2_CLK */
+                                                        710 0x20d5      /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
+                                                        712 0x20d5      /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
+                                                        715 0x20d5      /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
+                                                        719 0x20d5      /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
+                                                >;
+                                        };
+                                };
+
+                                i2c2 {
+                                        pinctrl_i2c2_1: i2c2grp-1 {
+                                                fsl,pins = <
+                                                        449 0x400001ed  /* MX51_PAD_KEY_COL4__I2C2_SCL */
+                                                        454 0x400001ed  /* MX51_PAD_KEY_COL5__I2C2_SDA */
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        413 0x1c5       /* MX51_PAD_UART1_RXD__UART1_RXD */
+                                                        416 0x1c5       /* MX51_PAD_UART1_TXD__UART1_TXD */
+                                                        418 0x1c5       /* MX51_PAD_UART1_RTS__UART1_RTS */
+                                                        420 0x1c5       /* MX51_PAD_UART1_CTS__UART1_CTS */
+                                                >;
+                                        };
+                                };
+
+                                uart2 {
+                                        pinctrl_uart2_1: uart2grp-1 {
+                                                fsl,pins = <
+                                                        423 0x1c5       /* MX51_PAD_UART2_RXD__UART2_RXD */
+                                                        426 0x1c5       /* MX51_PAD_UART2_TXD__UART2_TXD */
+                                                >;
+                                        };
+                                };
+
+                                uart3 {
+                                        pinctrl_uart3_1: uart3grp-1 {
+                                                fsl,pins = <
+                                                        54 0x1c5        /* MX51_PAD_EIM_D25__UART3_RXD */
+                                                        59 0x1c5        /* MX51_PAD_EIM_D26__UART3_TXD */
+                                                        65 0x1c5        /* MX51_PAD_EIM_D27__UART3_RTS */
+                                                        49 0x1c5        /* MX51_PAD_EIM_D24__UART3_CTS */
+                                                >;
+                                        };
+                                };
+                        };
+
                         uart1: serial@73fbc000 {
                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                 reg = <0x73fbc000 0x4000>;
@@ -219,6 +362,7 @@
                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
                                 reg = <0x83fb0000 0x4000>;
                                 interrupts = <6>;
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
                         };
 
                         cspi@83fc0000 {
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index da895e93a999..4be76f223526 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -25,31 +25,66 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_2>;
                                         cd-gpios = <&gpio1 1 0>;
                                         wp-gpios = <&gpio1 9 0>;
                                         status = "okay";
                                 };
                         };
 
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-ard";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
+                                                        1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
+                                                        486  0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
+                                                        739  0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
+                                                        218  0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
+                                                        226  0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
+                                                        233  0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
+                                                        241  0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
+                                                        429  0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
+                                                        435  0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
+                                                        441  0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
+                                                        448  0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
+                                                        456  0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
+                                                        464  0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
+                                                        471  0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
+                                                        477  0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
+                                                        492  0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
+                                                        500  0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
+                                                        508  0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
+                                                        516  0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
+                                                        524  0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
+                                                        532  0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
+                                                        540  0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
+                                                        548  0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
+                                                        637  0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
+                                                        642  0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
+                                                        647  0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
+                                                        652  0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
+                                                        657  0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
+                                                        662  0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
+                                                        667  0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
+                                                        611  0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
+                                                        616  0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
+                                                        607  0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_2>;
                                 status = "okay";
                         };
                 };
-
-                aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
-                };
         };
 
         eim-cs1@f4000000 {
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 9c798034675e..a124d1e25258 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -25,12 +25,16 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                         cd-gpios = <&gpio3 13 0>;
                                         wp-gpios = <&gpio3 14 0>;
                                         status = "okay";
                                 };
 
                                 ecspi@50010000 { /* ECSPI1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                         fsl,spi-num-chipselects = <2>;
                                         cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                         status = "okay";
@@ -56,32 +60,45 @@
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
                                         cd-gpios = <&gpio3 11 0>;
                                         wp-gpios = <&gpio3 12 0>;
                                         status = "okay";
                                 };
                         };
 
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-evk";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+                                                        449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+                                                        693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+                                                        697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                                        705  0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
+                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                        873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                 status = "okay";
                         };
                 };
 
                 aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
-
                         i2c@63fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                 status = "okay";
 
                                 pmic: mc13892@08 {
@@ -96,6 +113,8 @@
                         };
 
                         ethernet@63fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                 phy-mode = "rmii";
                                 phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 2d803a9a6949..08948af86d1a 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -25,6 +25,8 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                         cd-gpios = <&gpio3 13 0>;
                                         status = "okay";
                                 };
@@ -35,32 +37,46 @@
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
                                         cd-gpios = <&gpio3 11 0>;
                                         wp-gpios = <&gpio3 12 0>;
                                         status = "okay";
                                 };
                         };
 
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-qsb";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
+                                                        1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
+                                                        982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+                                                        989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+                                                        693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+                                                        697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                        873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                 status = "okay";
                         };
                 };
 
                 aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
-
                         i2c@63fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                 status = "okay";
 
                                 sgtl5000: codec@0a {
@@ -72,6 +88,8 @@
                         };
 
                         i2c@63fc8000 { /* I2C1 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1_1>;
                                 status = "okay";
 
                                 accelerometer: mma8450@1c {
@@ -158,10 +176,14 @@
                         };
 
                         audmux@63fd0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_audmux_1>;
                                 status = "okay";
                         };
 
                         ethernet@63fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                 phy-mode = "rmii";
                                 phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 08091029168e..06c68580c842 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -25,22 +25,30 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                         cd-gpios = <&gpio3 13 0>;
                                         wp-gpios = <&gpio4 11 0>;
                                         status = "okay";
                                 };
 
                                 esdhc@50008000 { /* ESDHC2 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc2_1>;
                                         non-removable;
                                         status = "okay";
                                 };
 
                                 uart3: serial@5000c000 {
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_uart3_1>;
                                         fsl,uart-has-rtscts;
                                         status = "okay";
                                 };
 
                                 ecspi@50010000 { /* ECSPI1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                         fsl,spi-num-chipselects = <2>;
                                         cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                         status = "okay";
@@ -72,35 +80,49 @@
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
                                         non-removable;
                                         status = "okay";
                                 };
                         };
 
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-smd";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+                                                        989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+                                                        424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                                        449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+                                                        43   0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
+                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                 status = "okay";
                         };
 
                         uart2: serial@53fc0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart2_1>;
                                 status = "okay";
                         };
                 };
 
                 aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
-
                         i2c@63fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                 status = "okay";
 
                                 codec: sgtl5000@0a {
@@ -120,6 +142,8 @@
                         };
 
                         i2c@63fc8000 { /* I2C1 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1_1>;
                                 status = "okay";
 
                                 accelerometer: mma8450@1c {
@@ -139,6 +163,8 @@
                         };
 
                         ethernet@63fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                 phy-mode = "rmii";
                                 phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165edce5..221cf3321b0a 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,6 +135,34 @@
                                 };
                         };
 
+                        usb@53f80000 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80000 0x0200>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+
+                        usb@53f80200 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80200 0x0200>;
+                                interrupts = <14>;
+                                status = "disabled";
+                        };
+
+                        usb@53f80400 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80400 0x0200>;
+                                interrupts = <16>;
+                                status = "disabled";
+                        };
+
+                        usb@53f80600 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80600 0x0200>;
+                                interrupts = <17>;
+                                status = "disabled";
+                        };
+
                         gpio1: gpio@53f84000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53f84000 0x4000>;
@@ -179,7 +207,6 @@
                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
                                 reg = <0x53f98000 0x4000>;
                                 interrupts = <58>;
-                                status = "disabled";
                         };
 
                         wdog@53f9c000 { /* WDOG2 */
@@ -189,6 +216,161 @@
                                 status = "disabled";
                         };
 
+                        iomuxc@53fa8000 {
+                                compatible = "fsl,imx53-iomuxc";
+                                reg = <0x53fa8000 0x4000>;
+
+                                audmux {
+                                        pinctrl_audmux_1: audmuxgrp-1 {
+                                                fsl,pins = <
+                                                        10 0x80000000   /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
+                                                        17 0x80000000   /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
+                                                        23 0x80000000   /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
+                                                        30 0x80000000   /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
+                                                >;
+                                        };
+                                };
+
+                                fec {
+                                        pinctrl_fec_1: fecgrp-1 {
+                                                fsl,pins = <
+                                                        820 0x80000000  /* MX53_PAD_FEC_MDC__FEC_MDC */
+                                                        779 0x80000000  /* MX53_PAD_FEC_MDIO__FEC_MDIO */
+                                                        786 0x80000000  /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
+                                                        791 0x80000000  /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
+                                                        796 0x80000000  /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
+                                                        799 0x80000000  /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
+                                                        804 0x80000000  /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
+                                                        808 0x80000000  /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
+                                                        811 0x80000000  /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
+                                                        816 0x80000000  /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
+                                                >;
+                                        };
+                                };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        433 0x80000000  /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
+                                                        439 0x80000000  /* MX53_PAD_EIM_D17__ECSPI1_MISO */
+                                                        445 0x80000000  /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
+                                                >;
+                                        };
+                                };
+
+                                esdhc1 {
+                                        pinctrl_esdhc1_1: esdhc1grp-1 {
+                                                fsl,pins = <
+                                                        995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+                                                        1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+                                                        1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+                                                        1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+                                                        1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+                                                        1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+                                                >;
+                                        };
+
+                                        pinctrl_esdhc1_2: esdhc1grp-2 {
+                                                fsl,pins = <
+                                                        995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+                                                        1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+                                                        1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+                                                        1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+                                                        941  0x1d5      /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
+                                                        948  0x1d5      /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
+                                                        955  0x1d5      /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
+                                                        962  0x1d5      /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
+                                                        1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+                                                        1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+                                                >;
+                                        };
+                                };
+
+                                esdhc2 {
+                                        pinctrl_esdhc2_1: esdhc2grp-1 {
+                                                fsl,pins = <
+                                                        1038 0x1d5      /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
+                                                        1032 0x1d5      /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
+                                                        1062 0x1d5      /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
+                                                        1056 0x1d5      /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
+                                                        1050 0x1d5      /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
+                                                        1044 0x1d5      /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
+                                                >;
+                                        };
+                                };
+
+                                esdhc3 {
+                                        pinctrl_esdhc3_1: esdhc3grp-1 {
+                                                fsl,pins = <
+                                                        943 0x1d5       /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
+                                                        950 0x1d5       /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
+                                                        957 0x1d5       /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
+                                                        964 0x1d5       /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
+                                                        893 0x1d5       /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
+                                                        900 0x1d5       /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
+                                                        906 0x1d5       /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
+                                                        912 0x1d5       /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
+                                                        857 0x1d5       /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
+                                                        863 0x1d5       /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
+                                                >;
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1_1: i2c1grp-1 {
+                                                fsl,pins = <
+                                                        333 0xc0000000  /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
+                                                        341 0xc0000000  /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
+                                                >;
+                                        };
+                                };
+
+                                i2c2 {
+                                        pinctrl_i2c2_1: i2c2grp-1 {
+                                                fsl,pins = <
+                                                        61 0xc0000000   /* MX53_PAD_KEY_ROW3__I2C2_SDA */
+                                                        53 0xc0000000   /* MX53_PAD_KEY_COL3__I2C2_SCL */
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        346 0x1c5       /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
+                                                        354 0x1c5       /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
+                                                >;
+                                        };
+
+                                        pinctrl_uart1_2: uart1grp-2 {
+                                                fsl,pins = <
+                                                        828 0x1c5       /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
+                                                        832 0x1c5       /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
+                                                >;
+                                        };
+                                };
+
+                                uart2 {
+                                        pinctrl_uart2_1: uart2grp-1 {
+                                                fsl,pins = <
+                                                        841 0x1c5       /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
+                                                        836 0x1c5       /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
+                                                >;
+                                        };
+                                };
+
+                                uart3 {
+                                        pinctrl_uart3_1: uart3grp-1 {
+                                                fsl,pins = <
+                                                        884 0x1c5       /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
+                                                        888 0x1c5       /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
+                                                        875 0x1c5       /* MX53_PAD_PATA_DA_1__UART3_CTS */
+                                                        880 0x1c5       /* MX53_PAD_PATA_DA_2__UART3_RTS */
+                                                >;
+                                        };
+                                };
+                        };
+
                         uart1: serial@53fbc000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53fbc000 0x4000>;
@@ -203,6 +385,20 @@
                                 status = "disabled";
                         };
 
+                        can1: can@53fc8000 {
+                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x53fc8000 0x4000>;
+                                interrupts = <82>;
+                                status = "disabled";
+                        };
+
+                        can2: can@53fcc000 {
+                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x53fcc000 0x4000>;
+                                interrupts = <83>;
+                                status = "disabled";
+                        };
+
                         gpio5: gpio@53fdc000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53fdc000 0x4000>;
@@ -277,6 +473,7 @@
                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
                                 reg = <0x63fb0000 0x4000>;
                                 interrupts = <6>;
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
                         };
 
                         cspi@63fc0000 {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d792581672cc..15df4c105e89 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -28,8 +28,27 @@
                         status = "disabled"; /* gpmi nand conflicts with SD */
                 };
 
+                aips-bus@02000000 { /* AIPS1 */
+                        iomuxc@020e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        176  0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+                                                        1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
+                                                        1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+                                                >;
+                                        };
+                                };
+                        };
+                };
+
                 aips-bus@02100000 { /* AIPS2 */
                         ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_2>;
                                 phy-mode = "rgmii";
                                 status = "okay";
                         };
@@ -52,6 +71,8 @@
                         };
 
                         uart4: serial@021f0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart4_1>;
                                 status = "okay";
                         };
                 };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3e6171..d152328285a1 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -46,15 +46,20 @@
 
                         iomuxc@020e0000 {
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_gpio_hog>;
+                                pinctrl-0 = <&pinctrl_hog>;
 
-                                gpios {
-                                        pinctrl_gpio_hog: gpiohog {
+                                hog {
+                                        pinctrl_hog: hoggrp {
                                                 fsl,pins = <
-                                                           144  0x80000000      /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
-                                                           121  0x80000000      /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
-                                                           953  0x80000000      /* MX6Q_PAD_GPIO_0__CCM_CLKO */
-                                                           >;
+                                                        1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
+                                                        1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
+                                                        121  0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+                                                        144  0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+                                                        152  0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
+                                                        1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
+                                                        1270 0x1f0b0    /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
+                                                        953  0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+                                                >;
                                         };
                                 };
                         };
@@ -63,6 +68,9 @@
                 aips-bus@02100000 { /* AIPS2 */
                         usb@02184000 { /* USB OTG */
                                 vbus-supply = <&reg_usb_otg_vbus>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usbotg_1>;
+                                disable-over-current;
                                 status = "okay";
                         };
 
@@ -71,12 +79,16 @@
                         };
 
                         ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_1>;
                                 phy-mode = "rgmii";
                                 phy-reset-gpios = <&gpio3 23 0>;
                                 status = "okay";
                         };
 
                         usdhc@02198000 { /* uSDHC3 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc3_2>;
                                 cd-gpios = <&gpio7 0 0>;
                                 wp-gpios = <&gpio7 1 0>;
                                 vmmc-supply = <&reg_3p3v>;
@@ -84,6 +96,8 @@
                         };
 
                         usdhc@0219c000 { /* uSDHC4 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc4_2>;
                                 cd-gpios = <&gpio2 6 0>;
                                 wp-gpios = <&gpio2 7 0>;
                                 vmmc-supply = <&reg_3p3v>;
@@ -99,7 +113,7 @@
                         uart2: serial@021e8000 {
                                 status = "okay";
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_serial2_1>;
+                                pinctrl-0 = <&pinctrl_uart2_1>;
                         };
 
                         i2c@021a0000 { /* I2C1 */
@@ -111,6 +125,7 @@
                                 codec: sgtl5000@0a {
                                         compatible = "fsl,sgtl5000";
                                         reg = <0x0a>;
+                                        clocks = <&clks 169>;
                                         VDDA-supply = <&reg_2p5v>;
                                         VDDIO-supply = <&reg_3p3v>;
                                 };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 07509a181178..e596c28c214d 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -22,28 +22,51 @@
         };
 
         soc {
-
                 aips-bus@02000000 { /* AIPS1 */
                         spba-bus@02000000 {
                                 uart1: serial@02020000 {
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_uart1_1>;
                                         status = "okay";
                                 };
                         };
+
+                        iomuxc@020e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
+                                                        1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
+                                                        1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
+                                                        1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
+                                                >;
+                                        };
+                                };
+                        };
                 };
 
                 aips-bus@02100000 { /* AIPS2 */
                         ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_1>;
                                 phy-mode = "rgmii";
                                 status = "okay";
                         };
 
                         usdhc@02194000 { /* uSDHC2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc2_1>;
                                 cd-gpios = <&gpio2 2 0>;
                                 wp-gpios = <&gpio2 3 0>;
                                 status = "okay";
                         };
 
                         usdhc@02198000 { /* uSDHC3 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc3_1>;
                                 cd-gpios = <&gpio2 0 0>;
                                 wp-gpios = <&gpio2 1 0>;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079f71a9..35e5895ba3df 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -97,18 +97,23 @@
                 dma-apbh@00110000 {
                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
                         reg = <0x00110000 0x2000>;
+                        clocks = <&clks 106>;
                 };
 
                 gpmi-nand@00112000 {
-                       compatible = "fsl,imx6q-gpmi-nand";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-                       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
-                       reg-names = "gpmi-nand", "bch";
-                       interrupts = <0 13 0x04>, <0 15 0x04>;
-                       interrupt-names = "gpmi-dma", "bch";
-                       fsl,gpmi-dma-channel = <0>;
-                       status = "disabled";
+                        compatible = "fsl,imx6q-gpmi-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+                        reg-names = "gpmi-nand", "bch";
+                        interrupts = <0 13 0x04>, <0 15 0x04>;
+                        interrupt-names = "gpmi-dma", "bch";
+                        clocks = <&clks 152>, <&clks 153>, <&clks 151>,
+                                 <&clks 150>, <&clks 149>;
+                        clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+                                      "gpmi_bch_apb", "per1_bch";
+                        fsl,gpmi-dma-channel = <0>;
+                        status = "disabled";
                 };
 
                 timer@00a00600 {
@@ -150,6 +155,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x02008000 0x4000>;
                                         interrupts = <0 31 0x04>;
+                                        clocks = <&clks 112>, <&clks 112>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -159,6 +166,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x0200c000 0x4000>;
                                         interrupts = <0 32 0x04>;
+                                        clocks = <&clks 113>, <&clks 113>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -168,6 +177,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x02010000 0x4000>;
                                         interrupts = <0 33 0x04>;
+                                        clocks = <&clks 114>, <&clks 114>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -177,6 +188,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x02014000 0x4000>;
                                         interrupts = <0 34 0x04>;
+                                        clocks = <&clks 115>, <&clks 115>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -186,6 +199,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x02018000 0x4000>;
                                         interrupts = <0 35 0x04>;
+                                        clocks = <&clks 116>, <&clks 116>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -193,6 +208,8 @@
                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02020000 0x4000>;
                                         interrupts = <0 26 0x04>;
+                                        clocks = <&clks 160>, <&clks 161>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -205,6 +222,7 @@
                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                         reg = <0x02028000 0x4000>;
                                         interrupts = <0 46 0x04>;
+                                        clocks = <&clks 178>;
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <38 37>;
                                         status = "disabled";
@@ -214,6 +232,7 @@
                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                         reg = <0x0202c000 0x4000>;
                                         interrupts = <0 47 0x04>;
+                                        clocks = <&clks 179>;
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <42 41>;
                                         status = "disabled";
@@ -223,6 +242,7 @@
                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                         reg = <0x02030000 0x4000>;
                                         interrupts = <0 48 0x04>;
+                                        clocks = <&clks 180>;
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <46 45>;
                                         status = "disabled";
@@ -362,20 +382,22 @@
                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                 reg = <0x020bc000 0x4000>;
                                 interrupts = <0 80 0x04>;
-                                status = "disabled";
+                                clocks = <&clks 0>;
                         };
 
                         wdog@020c0000 { /* WDOG2 */
                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                 reg = <0x020c0000 0x4000>;
                                 interrupts = <0 81 0x04>;
+                                clocks = <&clks 0>;
                                 status = "disabled";
                         };
 
-                        ccm@020c4000 {
+                        clks: ccm@020c4000 {
                                 compatible = "fsl,imx6q-ccm";
                                 reg = <0x020c4000 0x4000>;
                                 interrupts = <0 87 0x04 0 88 0x04>;
+                                #clock-cells = <1>;
                         };
 
                         anatop@020c8000 {
@@ -472,12 +494,14 @@
                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020c9000 0x1000>;
                                 interrupts = <0 44 0x04>;
+                                clocks = <&clks 182>;
                         };
 
                         usbphy2: usbphy@020ca000 {
                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020ca000 0x1000>;
                                 interrupts = <0 45 0x04>;
+                                clocks = <&clks 183>;
                         };
 
                         snvs@020cc000 {
@@ -514,86 +538,207 @@
                                 /* shared pinctrl settings */
                                 audmux {
                                         pinctrl_audmux_1: audmux-1 {
-                                                fsl,pins = <18   0x80000000     /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
-                                                            1586 0x80000000     /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
-                                                            11   0x80000000     /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
-                                                            3    0x80000000>;   /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+                                                fsl,pins = <
+                                                        18   0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+                                                        1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+                                                        11   0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+                                                        3    0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+                                                >;
+                                        };
+                                };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        101 0x100b1     /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+                                                        109 0x100b1     /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+                                                        94  0x100b1     /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+                                                >;
+                                        };
+                                };
+
+                                enet {
+                                        pinctrl_enet_1: enetgrp-1 {
+                                                fsl,pins = <
+                                                        695 0x1b0b0     /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
+                                                        756 0x1b0b0     /* MX6Q_PAD_ENET_MDC__ENET_MDC */
+                                                        24  0x1b0b0     /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+                                                        30  0x1b0b0     /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+                                                        34  0x1b0b0     /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+                                                        39  0x1b0b0     /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+                                                        44  0x1b0b0     /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+                                                        56  0x1b0b0     /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+                                                        702 0x1b0b0     /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+                                                        74  0x1b0b0     /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+                                                        52  0x1b0b0     /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+                                                        61  0x1b0b0     /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+                                                        66  0x1b0b0     /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+                                                        70  0x1b0b0     /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+                                                        48  0x1b0b0     /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+                                                >;
+                                        };
+
+                                        pinctrl_enet_2: enetgrp-2 {
+                                                fsl,pins = <
+                                                        890 0x1b0b0     /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
+                                                        909 0x1b0b0     /* MX6Q_PAD_KEY_COL2__ENET_MDC */
+                                                        24  0x1b0b0     /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+                                                        30  0x1b0b0     /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+                                                        34  0x1b0b0     /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+                                                        39  0x1b0b0     /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+                                                        44  0x1b0b0     /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+                                                        56  0x1b0b0     /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+                                                        702 0x1b0b0     /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+                                                        74  0x1b0b0     /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+                                                        52  0x1b0b0     /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+                                                        61  0x1b0b0     /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+                                                        66  0x1b0b0     /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+                                                        70  0x1b0b0     /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+                                                        48  0x1b0b0     /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+                                                >;
                                         };
                                 };
 
                                 gpmi-nand {
                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
-                                                fsl,pins = <1328 0xb0b1         /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
-                                                            1336 0xb0b1         /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
-                                                            1344 0xb0b1         /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
-                                                            1352 0xb000         /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
-                                                            1360 0xb0b1         /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
-                                                            1365 0xb0b1         /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
-                                                            1371 0xb0b1         /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
-                                                            1378 0xb0b1         /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
-                                                            1387 0xb0b1         /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
-                                                            1393 0xb0b1         /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
-                                                            1397 0xb0b1         /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
-                                                            1405 0xb0b1         /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
-                                                            1413 0xb0b1         /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
-                                                            1421 0xb0b1         /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
-                                                            1429 0xb0b1         /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
-                                                            1437 0xb0b1         /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
-                                                            1445 0xb0b1         /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
-                                                            1453 0xb0b1         /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
-                                                            1463 0x00b1>;       /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+                                                fsl,pins = <
+                                                        1328 0xb0b1     /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+                                                        1336 0xb0b1     /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+                                                        1344 0xb0b1     /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+                                                        1352 0xb000     /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+                                                        1360 0xb0b1     /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+                                                        1365 0xb0b1     /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+                                                        1371 0xb0b1     /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+                                                        1378 0xb0b1     /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+                                                        1387 0xb0b1     /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+                                                        1393 0xb0b1     /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+                                                        1397 0xb0b1     /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+                                                        1405 0xb0b1     /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+                                                        1413 0xb0b1     /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+                                                        1421 0xb0b1     /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+                                                        1429 0xb0b1     /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+                                                        1437 0xb0b1     /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+                                                        1445 0xb0b1     /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+                                                        1453 0xb0b1     /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+                                                        1463 0x00b1     /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+                                                >;
                                         };
                                 };
 
                                 i2c1 {
                                         pinctrl_i2c1_1: i2c1grp-1 {
-                                                fsl,pins = <137 0x4001b8b1      /* MX6Q_PAD_EIM_D21__I2C1_SCL */
-                                                            196 0x4001b8b1>;    /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+                                                fsl,pins = <
+                                                        137 0x4001b8b1  /* MX6Q_PAD_EIM_D21__I2C1_SCL */
+                                                        196 0x4001b8b1  /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        1140 0x1b0b1    /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
+                                                        1148 0x1b0b1    /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
+                                                >;
                                         };
                                 };
 
-                                serial2 {
-                                        pinctrl_serial2_1: serial2grp-1 {
-                                                fsl,pins = <183 0x1b0b1         /* MX6Q_PAD_EIM_D26__UART2_TXD */
-                                                            191 0x1b0b1>;       /* MX6Q_PAD_EIM_D27__UART2_RXD */
+                                uart2 {
+                                        pinctrl_uart2_1: uart2grp-1 {
+                                                fsl,pins = <
+                                                        183 0x1b0b1     /* MX6Q_PAD_EIM_D26__UART2_TXD */
+                                                        191 0x1b0b1     /* MX6Q_PAD_EIM_D27__UART2_RXD */
+                                                >;
+                                        };
+                                };
+
+                                uart4 {
+                                        pinctrl_uart4_1: uart4grp-1 {
+                                                fsl,pins = <
+                                                        877 0x1b0b1     /* MX6Q_PAD_KEY_COL0__UART4_TXD */
+                                                        885 0x1b0b1     /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+                                                >;
+                                        };
+                                };
+
+                                usbotg {
+                                        pinctrl_usbotg_1: usbotggrp-1 {
+                                                fsl,pins = <
+                                                        1592 0x17059    /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
+                                                >;
+                                        };
+                                };
+
+                                usdhc2 {
+                                        pinctrl_usdhc2_1: usdhc2grp-1 {
+                                                fsl,pins = <
+                                                        1577 0x17059    /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
+                                                        1569 0x10059    /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
+                                                        16   0x17059    /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
+                                                        0    0x17059    /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
+                                                        8    0x17059    /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
+                                                        1583 0x17059    /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
+                                                        1430 0x17059    /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
+                                                        1438 0x17059    /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
+                                                        1446 0x17059    /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
+                                                        1454 0x17059    /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
+                                                >;
                                         };
                                 };
 
                                 usdhc3 {
                                         pinctrl_usdhc3_1: usdhc3grp-1 {
-                                                fsl,pins = <1273 0x17059        /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-                                                            1281 0x10059        /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
-                                                            1289 0x17059        /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
-                                                            1297 0x17059        /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
-                                                            1305 0x17059        /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
-                                                            1312 0x17059        /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
-                                                            1265 0x17059        /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
-                                                            1257 0x17059        /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
-                                                            1249 0x17059        /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
-                                                            1241 0x17059>;      /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+                                                fsl,pins = <
+                                                        1273 0x17059    /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+                                                        1281 0x10059    /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+                                                        1289 0x17059    /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+                                                        1297 0x17059    /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+                                                        1305 0x17059    /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+                                                        1312 0x17059    /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+                                                        1265 0x17059    /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
+                                                        1257 0x17059    /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
+                                                        1249 0x17059    /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+                                                        1241 0x17059    /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+                                                >;
+                                        };
+
+                                        pinctrl_usdhc3_2: usdhc3grp-2 {
+                                                fsl,pins = <
+                                                        1273 0x17059    /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+                                                        1281 0x10059    /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+                                                        1289 0x17059    /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+                                                        1297 0x17059    /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+                                                        1305 0x17059    /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+                                                        1312 0x17059    /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+                                                >;
                                         };
                                 };
 
                                 usdhc4 {
                                         pinctrl_usdhc4_1: usdhc4grp-1 {
-                                                fsl,pins = <1386 0x17059        /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
-                                                            1392 0x10059        /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
-                                                            1462 0x17059        /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
-                                                            1470 0x17059        /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
-                                                            1478 0x17059        /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
-                                                            1486 0x17059        /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
-                                                            1493 0x17059        /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
-                                                            1501 0x17059        /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
-                                                            1509 0x17059        /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
-                                                            1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+                                                fsl,pins = <
+                                                        1386 0x17059    /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+                                                        1392 0x10059    /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+                                                        1462 0x17059    /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+                                                        1470 0x17059    /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+                                                        1478 0x17059    /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+                                                        1486 0x17059    /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                                        1493 0x17059    /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+                                                        1501 0x17059    /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+                                                        1509 0x17059    /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+                                                        1517 0x17059    /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+                                                >;
                                         };
-                                };
 
-                                ecspi1 {
-                                        pinctrl_ecspi1_1: ecspi1grp-1 {
-                                                fsl,pins = <101 0x100b1         /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
-                                                            109 0x100b1         /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
-                                                            94  0x100b1>;       /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+                                        pinctrl_usdhc4_2: usdhc4grp-2 {
+                                                fsl,pins = <
+                                                        1386 0x17059    /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+                                                        1392 0x10059    /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+                                                        1462 0x17059    /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+                                                        1470 0x17059    /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+                                                        1478 0x17059    /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+                                                        1486 0x17059    /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                                >;
                                         };
                                 };
                         };
@@ -612,6 +757,9 @@
                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
                                 reg = <0x020ec000 0x4000>;
                                 interrupts = <0 2 0x04>;
+                                clocks = <&clks 155>, <&clks 155>;
+                                clock-names = "ipg", "ahb";
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
                         };
                 };
 
@@ -635,7 +783,9 @@
                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                 reg = <0x02184000 0x200>;
                                 interrupts = <0 43 0x04>;
+                                clocks = <&clks 162>;
                                 fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc 0>;
                                 status = "disabled";
                         };
 
@@ -643,7 +793,9 @@
                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                 reg = <0x02184200 0x200>;
                                 interrupts = <0 40 0x04>;
+                                clocks = <&clks 162>;
                                 fsl,usbphy = <&usbphy2>;
+                                fsl,usbmisc = <&usbmisc 1>;
                                 status = "disabled";
                         };
 
@@ -651,6 +803,8 @@
                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                 reg = <0x02184400 0x200>;
                                 interrupts = <0 41 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbmisc = <&usbmisc 2>;
                                 status = "disabled";
                         };
 
@@ -658,13 +812,24 @@
                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                 reg = <0x02184600 0x200>;
                                 interrupts = <0 42 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbmisc = <&usbmisc 3>;
                                 status = "disabled";
                         };
 
+                        usbmisc: usbmisc@02184800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx6q-usbmisc";
+                                reg = <0x02184800 0x200>;
+                                clocks = <&clks 162>;
+                        };
+
                         ethernet@02188000 {
                                 compatible = "fsl,imx6q-fec";
                                 reg = <0x02188000 0x4000>;
                                 interrupts = <0 118 0x04 0 119 0x04>;
+                                clocks = <&clks 117>, <&clks 117>;
+                                clock-names = "ipg", "ahb";
                                 status = "disabled";
                         };
 
@@ -677,6 +842,8 @@
                                 compatible = "fsl,imx6q-usdhc";
                                 reg = <0x02190000 0x4000>;
                                 interrupts = <0 22 0x04>;
+                                clocks = <&clks 163>, <&clks 163>, <&clks 163>;
+                                clock-names = "ipg", "ahb", "per";
                                 status = "disabled";
                         };
 
@@ -684,6 +851,8 @@
                                 compatible = "fsl,imx6q-usdhc";
                                 reg = <0x02194000 0x4000>;
                                 interrupts = <0 23 0x04>;
+                                clocks = <&clks 164>, <&clks 164>, <&clks 164>;
+                                clock-names = "ipg", "ahb", "per";
                                 status = "disabled";
                         };
 
@@ -691,6 +860,8 @@
                                 compatible = "fsl,imx6q-usdhc";
                                 reg = <0x02198000 0x4000>;
                                 interrupts = <0 24 0x04>;
+                                clocks = <&clks 165>, <&clks 165>, <&clks 165>;
+                                clock-names = "ipg", "ahb", "per";
                                 status = "disabled";
                         };
 
@@ -698,6 +869,8 @@
                                 compatible = "fsl,imx6q-usdhc";
                                 reg = <0x0219c000 0x4000>;
                                 interrupts = <0 25 0x04>;
+                                clocks = <&clks 166>, <&clks 166>, <&clks 166>;
+                                clock-names = "ipg", "ahb", "per";
                                 status = "disabled";
                         };
 
@@ -707,6 +880,7 @@
                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
                                 reg = <0x021a0000 0x4000>;
                                 interrupts = <0 36 0x04>;
+                                clocks = <&clks 125>;
                                 status = "disabled";
                         };
 
@@ -716,6 +890,7 @@
                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
                                 reg = <0x021a4000 0x4000>;
                                 interrupts = <0 37 0x04>;
+                                clocks = <&clks 126>;
                                 status = "disabled";
                         };
 
@@ -725,6 +900,7 @@
                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
                                 reg = <0x021a8000 0x4000>;
                                 interrupts = <0 38 0x04>;
+                                clocks = <&clks 127>;
                                 status = "disabled";
                         };
 
@@ -788,6 +964,8 @@
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021e8000 0x4000>;
                                 interrupts = <0 27 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -795,6 +973,8 @@
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021ec000 0x4000>;
                                 interrupts = <0 28 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -802,6 +982,8 @@
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f0000 0x4000>;
                                 interrupts = <0 29 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -809,6 +991,8 @@
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f4000 0x4000>;
                                 interrupts = <0 30 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 7408655f91b5..9b32d0272825 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -25,6 +25,16 @@
                 };
         };
 
+        gpio_fan {
+                /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
+                compatible = "gpio-fan";
+                gpios = <&gpio1 14 1
+                         &gpio1 13 1>;
+                gpio-fan,speed-map = <0    0
+                                      3000 1
+                                      6000 2>;
+        };
+
         ocp@f1000000 {
                 sata@80000 {
                         status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
new file mode 100644
index 000000000000..08a582414b88
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Seagate FreeAgent Dockstar";
+        compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x400000>;
+                        };
+
+                        partition@500000 {
+                                label = "data";
+                                reg = <0x0500000 0xfb00000>;
+                        };
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                health {
+                        label = "status:green:health";
+                        gpios = <&gpio1 14 1>;
+                        linux,default-trigger = "default-on";
+                };
+                fault {
+                        label = "status:orange:fault";
+                        gpios = <&gpio1 15 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index f8ca6fa88192..d97cd9d4753e 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -12,7 +12,7 @@
         };
 
         chosen {
-                bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
                 linux,initrd-start = <0x4500040>;
                 linux,initrd-end   = <0x4800000>;
         };
@@ -30,7 +30,37 @@
                         clock-frequency = <200000000>;
                         status = "ok";
                 };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0000000 0xc0000>;
+                        };
+
+                        partition@a0000 {
+                                label = "env";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        partition@100000 {
+                                label = "zImage";
+                                reg = <0x100000 0x300000>;
+                        };
+
+                        partition@540000 {
+                                label = "initrd";
+                                reg = <0x540000 0x300000>;
+                        };
+
+                        partition@980000 {
+                                label = "boot";
+                                reg = <0x980000 0x1f400000>;
+                        };
+                };
         };
+
         gpio-leds {
                 compatible = "gpio-leds";
 
@@ -69,4 +99,22 @@
                         gpios = <&gpio1 16 0>;
                 };
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "OTB Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 3 1>;
+                        debounce-interval = <100>;
+                };
+                button@2 {
+                        label = "Reset";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 12 1>;
+                        debounce-interval = <100>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
new file mode 100644
index 000000000000..865aeec40a26
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Iomega StorCenter ix2-200";
+        compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                i2c@11000 {
+                        status = "okay";
+
+                        lm63: lm63@4c {
+                                compatible = "national,lm63";
+                                reg = <0x4c>;
+                        };
+                };
+
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+
+                        partition@a0000 {
+                                label = "env";
+                                reg = <0xa0000 0x20000>;
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x100000 0x300000>;
+                        };
+
+                        partition@400000 {
+                                label = "uInitrd";
+                                reg = <0x540000 0x1000000>;
+                        };
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                power_led {
+                        label = "status:white:power_led";
+                        gpios = <&gpio0 16 0>;
+                        linux,default-trigger = "default-on";
+                };
+                health_led1 {
+                        label = "status:red:health_led";
+                        gpios = <&gpio1 5 0>;
+                };
+                health_led2 {
+                        label = "status:white:health_led";
+                        gpios = <&gpio1 4 0>;
+                };
+                backup_led {
+                        label = "status:blue:backup_led";
+                        gpios = <&gpio0 15 0>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                Power {
+                        label = "Power Button";
+                        linux,code = <116>;
+                        gpios = <&gpio0 14 1>;
+                };
+                Reset {
+                        label = "Reset Button";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 12 1>;
+                };
+                OTB {
+                        label = "OTB Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 3 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
new file mode 100644
index 000000000000..75bdb93fed26
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Keymile Kirkwood Reference Design";
+        compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x08000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "ok";
+                        chip-delay = <25>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index cef9616f330a..4e5b8154a5be 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -14,7 +14,8 @@
 
         ocp@f1000000 {
                 compatible = "simple-bus";
-                ranges = <0 0xf1000000 0x4000000>;
+                ranges = <0x00000000 0xf1000000 0x4000000
+                          0xf5000000 0xf5000000 0x0000400>;
                 #address-cells = <1>;
                 #size-cells = <1>;
 
@@ -105,5 +106,14 @@
                         clock-frequency = <100000>;
                         status = "disabled";
                 };
+
+                crypto@30000 {
+                        compatible = "marvell,orion-crypto";
+                        reg = <0x30000 0x10000>,
+                              <0xf5000000 0x800>;
+                        reg-names = "regs", "sram";
+                        interrupts = <22>;
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 80f74e256408..0514fb41627e 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -26,6 +26,11 @@
                 interrupt-parent = <&intc>;
                 ranges;
 
+                L2: l2-cache {
+                        compatible = "marvell,tauros2-cache";
+                        marvell,tauros2-cache-features = <0x3>;
+                };
+
                 axi@d4200000 {  /* AXI */
                         compatible = "mrvl,axi-bus", "simple-bus";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 45bc4bb04e57..31f2157cd7d7 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -7,7 +7,7 @@
         compatible = "qcom,msm8660-surf", "qcom,msm8660";
         interrupt-parent = <&intc>;
 
-        intc: interrupt-controller@02080000 {
+        intc: interrupt-controller@2080000 {
                 compatible = "qcom,msm-8660-qgic";
                 interrupt-controller;
                 #interrupt-cells = <3>;
@@ -15,6 +15,23 @@
                       < 0x02081000 0x1000 >;
         };
 
+        timer@2000004 {
+                compatible = "qcom,msm-gpt", "qcom,msm-timer";
+                interrupts = <1 1 0x301>;
+                reg = <0x02000004 0x10>;
+                clock-frequency = <32768>;
+                cpu-offset = <0x40000>;
+        };
+
+        timer@2000024 {
+                compatible = "qcom,msm-dgt", "qcom,msm-timer";
+                interrupts = <1 0 0x301>;
+                reg = <0x02000024 0x10>,
+                      <0x02000034 0x4>;
+                clock-frequency = <6750000>;
+                cpu-offset = <0x40000>;
+        };
+
         serial@19c400000 {
                 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                 reg = <0x19c40000 0x1000>,
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
new file mode 100644
index 000000000000..9e621b5ad3dd
--- /dev/null
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -0,0 +1,41 @@
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Qualcomm MSM8960 CDP";
+        compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller@2000000 {
+                compatible = "qcom,msm-qgic2";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x02000000 0x1000 >,
+                      < 0x02002000 0x1000 >;
+        };
+
+        timer@200a004 {
+                compatible = "qcom,msm-gpt", "qcom,msm-timer";
+                interrupts = <1 2 0x301>;
+                reg = <0x0200a004 0x10>;
+                clock-frequency = <32768>;
+                cpu-offset = <0x80000>;
+        };
+
+        timer@200a024 {
+                compatible = "qcom,msm-dgt", "qcom,msm-timer";
+                interrupts = <1 1 0x301>;
+                reg = <0x0200a024 0x10>,
+                      <0x0200a034 0x4>;
+                clock-frequency = <6750000>;
+                cpu-offset = <0x80000>;
+        };
+
+        serial@19c400000 {
+                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
+                reg = <0x16440000 0x1000>,
+                      <0x16400000 0x1000>;
+                interrupts = <0 154 0x0>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 25b50b759dec..77b84e17c477 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2.dtsi"
+/include/ "omap2420.dtsi"
 
 / {
         model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
new file mode 100644
index 000000000000..bfd76b4a0ddc
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -0,0 +1,48 @@
+/*
+ * Device Tree Source for OMAP2420 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+        compatible = "ti,omap2420", "ti,omap2";
+
+        ocp {
+                omap2420_pmx: pinmux@48000030 {
+                        compatible = "ti,omap2420-padconf", "pinctrl-single";
+                        reg = <0x48000030 0x0113>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <8>;
+                        pinctrl-single,function-mask = <0x3f>;
+                };
+
+                mcbsp1: mcbsp@48074000 {
+                        compatible = "ti,omap2420-mcbsp";
+                        reg = <0x48074000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <59>, /* TX interrupt */
+                                     <60>; /* RX interrupt */
+                        interrupt-names = "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@48076000 {
+                        compatible = "ti,omap2420-mcbsp";
+                        reg = <0x48076000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <62>, /* TX interrupt */
+                                     <63>; /* RX interrupt */
+                        interrupt-names = "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,hwmods = "mcbsp2";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
new file mode 100644
index 000000000000..4565d9750f4d
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Device Tree Source for OMAP243x SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+        compatible = "ti,omap2430", "ti,omap2";
+
+        ocp {
+                omap2430_pmx: pinmux@49002030 {
+                        compatible = "ti,omap2430-padconf", "pinctrl-single";
+                        reg = <0x49002030 0x0154>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <8>;
+                        pinctrl-single,function-mask = <0x3f>;
+                };
+
+                mcbsp1: mcbsp@48074000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x48074000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <64>, /* OCP compliant interrupt */
+                                     <59>, /* TX interrupt */
+                                     <60>, /* RX interrupt */
+                                     <61>; /* RX overflow interrupt */
+                        interrupt-names = "common", "tx", "rx", "rx_overflow";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@48076000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x48076000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <16>, /* OCP compliant interrupt */
+                                     <62>, /* TX interrupt */
+                                     <63>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp2";
+                };
+
+                mcbsp3: mcbsp@4808c000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x4808c000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <17>, /* OCP compliant interrupt */
+                                     <89>, /* TX interrupt */
+                                     <90>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
+
+                mcbsp4: mcbsp@4808e000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x4808e000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <18>, /* OCP compliant interrupt */
+                                     <54>, /* TX interrupt */
+                                     <55>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp4";
+                };
+
+                mcbsp5: mcbsp@48096000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x48096000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <19>, /* OCP compliant interrupt */
+                                     <81>, /* TX interrupt */
+                                     <82>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp5";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index cdcb98c7e075..c38cf76df81f 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,16 +7,44 @@
  */
 /dts-v1/;
 
-/include/ "omap3.dtsi"
+/include/ "omap36xx.dtsi"
 
 / {
-        model = "TI OMAP3 BeagleBoard";
-        compatible = "ti,omap3-beagle", "ti,omap3";
+        model = "TI OMAP3 BeagleBoard xM";
+        compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
 
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x20000000>; /* 512 MB */
         };
+
+        leds {
+                compatible = "gpio-leds";
+                pmu_stat {
+                        label = "beagleboard::pmu_stat";
+                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                };
+
+                heartbeat {
+                        label = "beagleboard::usr0";
+                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        linux,default-trigger = "heartbeat";
+                };
+
+                mmc {
+                        label = "beagleboard::usr1";
+                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        sound {
+                compatible = "ti,omap-twl4030";
+                ti,model = "omap3beagle";
+
+                ti,mcbsp = <&mcbsp2>;
+                ti,codec = <&twl_audio>;
+        };
 };
 
 &i2c1 {
@@ -27,11 +55,17 @@
                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
                 interrupt-parent = <&intc>;
 
-                vsim: regulator@10 {
+                vsim: regulator-vsim {
                         compatible = "ti,twl4030-vsim";
                         regulator-min-microvolt = <1800000>;
                         regulator-max-microvolt = <3000000>;
                 };
+
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+                        codec {
+                        };
+                };
         };
 };
 
@@ -67,3 +101,15 @@
 &mmc3 {
         status = "disabled";
 };
+
+&twl_gpio {
+        ti,use-leds;
+        /* pullups: BIT(1) */
+        ti,pullups = <0x000002>;
+        /*
+         * pulldowns:
+         * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+         * BIT(15), BIT(16), BIT(17)
+         */
+        ti,pulldowns = <0x03a1c4>;
+};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index f349ee9182ce..e8ba1c247a39 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -17,6 +17,15 @@
                 device_type = "memory";
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
+
+        leds {
+                compatible = "gpio-leds";
+                ledb {
+                        label = "omap3evm::ledb";
+                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                        linux,default-trigger = "default-on";
+                };
+        };
 };
 
 &i2c1 {
@@ -46,3 +55,7 @@
                 reg = <0x5c>;
         };
 };
+
+&twl_gpio {
+        ti,use-leds;
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
new file mode 100644
index 000000000000..89808ce01673
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * The Gumstix Overo must be combined with an expansion board.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+        leds {
+                compatible = "gpio-leds";
+                overo {
+                        label = "overo:blue:COM";
+                        gpios = <&twl_gpio 19 0>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+};
+
+&i2c1 {
+        clock-frequency = <2600000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+        };
+};
+
+/include/ "twl4030.dtsi"
+
+/* i2c2 pins are used for gpio */
+&i2c2 {
+        status = "disabled";
+};
+
+/* on board microSD slot */
+&mmc1 {
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+};
+
+/* optional on board WiFi */
+&mmc2 {
+        bus-width = <4>;
+};
+
+&twl_gpio {
+        ti,use-leds;
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
new file mode 100644
index 000000000000..a13d12de77ff
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Tobi expansion board is manufactured by Gumstix Inc.
+ */
+
+/include/ "omap3-overo.dtsi"
+
+/ {
+        model = "TI OMAP3 Gumstix Overo on Tobi";
+        compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
+
+        leds {
+                compatible = "gpio-leds";
+                heartbeat {
+                        label = "overo:red:gpio21";
+                        gpios = <&gpio1 21 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+};
+
+&mmc3 {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 810947198208..f38ea8771b44 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -17,7 +17,6 @@
                 serial0 = &uart1;
                 serial1 = &uart2;
                 serial2 = &uart3;
-                serial3 = &uart4;
         };
 
         cpus {
@@ -69,6 +68,24 @@
                         reg = <0x48200000 0x1000>;
                 };
 
+                omap3_pmx_core: pinmux@48002030 {
+                        compatible = "ti,omap3-padconf", "pinctrl-single";
+                        reg = <0x48002030 0x05cc>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
+
+                omap3_pmx_wkup: pinmux@0x48002a58 {
+                        compatible = "ti,omap3-padconf", "pinctrl-single";
+                        reg = <0x48002a58 0x5c>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
+
                 gpio1: gpio@48310000 {
                         compatible = "ti,omap3-gpio";
                         ti,hwmods = "gpio1";
@@ -141,12 +158,6 @@
                         clock-frequency = <48000000>;
                 };
 
-                uart4: serial@49042000 {
-                        compatible = "ti,omap3-uart";
-                        ti,hwmods = "uart4";
-                        clock-frequency = <48000000>;
-                };
-
                 i2c1: i2c@48070000 {
                         compatible = "ti,omap3-i2c";
                         #address-cells = <1>;
@@ -220,5 +231,74 @@
                         compatible = "ti,omap3-wdt";
                         ti,hwmods = "wd_timer2";
                 };
+
+                mcbsp1: mcbsp@48074000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x48074000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <16>, /* OCP compliant interrupt */
+                                     <59>, /* TX interrupt */
+                                     <60>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@49022000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x49022000 0xff>,
+                              <0x49028000 0xff>;
+                        reg-names = "mpu", "sidetone";
+                        interrupts = <17>, /* OCP compliant interrupt */
+                                     <62>, /* TX interrupt */
+                                     <63>, /* RX interrupt */
+                                     <4>;  /* Sidetone */
+                        interrupt-names = "common", "tx", "rx", "sidetone";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <1280>;
+                        ti,hwmods = "mcbsp2";
+                };
+
+                mcbsp3: mcbsp@49024000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x49024000 0xff>,
+                              <0x4902a000 0xff>;
+                        reg-names = "mpu", "sidetone";
+                        interrupts = <22>, /* OCP compliant interrupt */
+                                     <89>, /* TX interrupt */
+                                     <90>, /* RX interrupt */
+                                     <5>;  /* Sidetone */
+                        interrupt-names = "common", "tx", "rx", "sidetone";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
+
+                mcbsp4: mcbsp@49026000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x49026000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <23>, /* OCP compliant interrupt */
+                                     <54>, /* TX interrupt */
+                                     <55>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp4";
+                };
+
+                mcbsp5: mcbsp@48096000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x48096000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <27>, /* OCP compliant interrupt */
+                                     <81>, /* TX interrupt */
+                                     <82>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp5";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
new file mode 100644
index 000000000000..96bf0287cb9f
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source for OMAP3 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap3.dtsi"
+
+/ {
+        aliases {
+                serial3 = &uart4;
+        };
+
+        ocp {
+                uart4: serial@49042000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9880c12877b3..20b966ee1bb3 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 
 / {
         model = "TI OMAP4 PandaBoard";
@@ -126,3 +127,13 @@
         ti,non-removable;
         bus-width = <4>;
 };
+
+&emif1 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 72216e932fc0..94a23b39033d 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 
 / {
         model = "TI OMAP4 SDP board";
@@ -18,7 +19,7 @@
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
 
-        vdd_eth: fixedregulator@0 {
+        vdd_eth: fixedregulator-vdd-eth {
                 compatible = "regulator-fixed";
                 regulator-name = "VDD_ETH";
                 regulator-min-microvolt = <3300000>;
@@ -28,7 +29,7 @@
                 regulator-boot-on;
         };
 
-        vbat: fixedregulator@2 {
+        vbat: fixedregulator-vbat {
                 compatible = "regulator-fixed";
                 regulator-name = "VBAT";
                 regulator-min-microvolt = <3750000>;
@@ -115,6 +116,33 @@
         };
 };
 
+&omap4_pmx_core {
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        0xd8 0x118      /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
+                        0xda 0          /* uart2_rts.uart2_rts OUTPUT | MODE0 */
+                        0xdc 0x118      /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
+                        0xde 0          /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x100 0x118     /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
+                        0x102 0         /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
+                        0x104 0x100     /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
+                        0x106 0         /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                >;
+        };
+
+        uart4_pins: pinmux_uart4_pins {
+                pinctrl-single,pins = <
+                        0x11c 0x100     /* uart4_rx.uart4_rx INPUT | MODE0 */
+                        0x11e 0         /* uart4_tx.uart4_tx OUTPUT | MODE0 */
+                >;
+        };
+};
+
 &i2c1 {
         clock-frequency = <400000>;
 
@@ -226,3 +254,98 @@
         bus-width = <4>;
         ti,non-removable;
 };
+
+&emif1 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+
+&keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <8>;
+        linux,keymap = <0x00000012      /* KEY_E */
+                        0x00010013      /* KEY_R */
+                        0x00020014      /* KEY_T */
+                        0x00030066      /* KEY_HOME */
+                        0x0004003f      /* KEY_F5 */
+                        0x000500f0      /* KEY_UNKNOWN */
+                        0x00060017      /* KEY_I */
+                        0x0007002a      /* KEY_LEFTSHIFT */
+                        0x01000020      /* KEY_D*/
+                        0x01010021      /* KEY_F */
+                        0x01020022      /* KEY_G */
+                        0x010300e7      /* KEY_SEND */
+                        0x01040040      /* KEY_F6 */
+                        0x010500f0      /* KEY_UNKNOWN */
+                        0x01060025      /* KEY_K */
+                        0x0107001c      /* KEY_ENTER */
+                        0x0200002d      /* KEY_X */
+                        0x0201002e      /* KEY_C */
+                        0x0202002f      /* KEY_V */
+                        0x0203006b      /* KEY_END */
+                        0x02040041      /* KEY_F7 */
+                        0x020500f0      /* KEY_UNKNOWN */
+                        0x02060034      /* KEY_DOT */
+                        0x0207003a      /* KEY_CAPSLOCK */
+                        0x0300002c      /* KEY_Z */
+                        0x0301004e      /* KEY_KPLUS */
+                        0x03020030      /* KEY_B */
+                        0x0303003b      /* KEY_F1 */
+                        0x03040042      /* KEY_F8 */
+                        0x030500f0      /* KEY_UNKNOWN */
+                        0x03060018      /* KEY_O */
+                        0x03070039      /* KEY_SPACE */
+                        0x04000011      /* KEY_W */
+                        0x04010015      /* KEY_Y */
+                        0x04020016      /* KEY_U */
+                        0x0403003c      /* KEY_F2 */
+                        0x04040073      /* KEY_VOLUMEUP */
+                        0x040500f0      /* KEY_UNKNOWN */
+                        0x04060026      /* KEY_L */
+                        0x04070069      /* KEY_LEFT */
+                        0x0500001f      /* KEY_S */
+                        0x05010023      /* KEY_H */
+                        0x05020024      /* KEY_J */
+                        0x0503003d      /* KEY_F3 */
+                        0x05040043      /* KEY_F9 */
+                        0x05050072      /* KEY_VOLUMEDOWN */
+                        0x05060032      /* KEY_M */
+                        0x0507006a      /* KEY_RIGHT */
+                        0x06000010      /* KEY_Q */
+                        0x0601001e      /* KEY_A */
+                        0x06020031      /* KEY_N */
+                        0x0603009e      /* KEY_BACK */
+                        0x0604000e      /* KEY_BACKSPACE */
+                        0x060500f0      /* KEY_UNKNOWN */
+                        0x06060019      /* KEY_P */
+                        0x06070067      /* KEY_UP */
+                        0x07000094      /* KEY_PROG1 */
+                        0x07010095      /* KEY_PROG2 */
+                        0x070200ca      /* KEY_PROG3 */
+                        0x070300cb      /* KEY_PROG4 */
+                        0x0704003e      /* KEY_F4 */
+                        0x070500f0      /* KEY_UNKNOWN */
+                        0x07060160      /* KEY_OK */
+                        0x0707006c>;    /* KEY_DOWN */
+        linux,input-no-autorepeat;
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart4_pins>;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb6ff91..5d1c48459e6e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -30,12 +30,35 @@
         cpus {
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                 };
         };
 
+        gic: interrupt-controller@48241000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48241000 0x1000>,
+                      <0x48240100 0x0100>;
+        };
+
+        L2: l2-cache-controller@48242000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x48242000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+        };
+
+        local-timer@0x48240600 {
+                compatible = "arm,cortex-a9-twd-timer";
+                reg = <0x48240600 0x20>;
+                interrupts = <1 13 0x304>;
+        };
+
         /*
          * The soc node represents the soc top level view. It is uses for IPs
          * that are not memory mapped in the MPU view or for the MPU itself.
@@ -61,30 +84,6 @@
         /*
          * XXX: Use a flat representation of the OMAP4 interconnect.
          * The real OMAP interconnect network is quite complex.
-         *
-         * MPU -+-- MPU_PRIVATE - GIC, L2
-         *      |
-         *      +----------------+----------+
-         *      |                |          |
-         *      +            +- EMIF - DDR  |
-         *      |            |              |
-         *      |            +     +--------+
-         *      |            |     |
-         *      |            +- L4_ABE - AESS, MCBSP, TIMERs...
-         *      |            |
-         *      +- L3_MAIN --+- L4_CORE - IPs...
-         *                   |
-         *                   +- L4_PER - IPs...
-         *                   |
-         *                   +- L4_CFG -+- L4_WKUP - IPs...
-         *                   |          |
-         *                   |          +- IPs...
-         *                   +- IPU ----+
-         *                   |          |
-         *                   +- DSP ----+
-         *                   |          |
-         *                   +- DSS ----+
-         *
          * Since that will not bring real advantage to represent that in DT for
          * the moment, just use a fake OCP bus entry to represent the whole bus
          * hierarchy.
@@ -96,16 +95,27 @@
                 ranges;
                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 
-                gic: interrupt-controller@48241000 {
-                        compatible = "arm,cortex-a9-gic";
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        reg = <0x48241000 0x1000>,
-                              <0x48240100 0x0100>;
+                omap4_pmx_core: pinmux@4a100040 {
+                        compatible = "ti,omap4-padconf", "pinctrl-single";
+                        reg = <0x4a100040 0x0196>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
+                omap4_pmx_wkup: pinmux@4a31e040 {
+                        compatible = "ti,omap4-padconf", "pinctrl-single";
+                        reg = <0x4a31e040 0x0038>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
                 };
 
                 gpio1: gpio@4a310000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x4a310000 0x200>;
+                        interrupts = <0 29 0x4>;
                         ti,hwmods = "gpio1";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -115,6 +125,8 @@
 
                 gpio2: gpio@48055000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x48055000 0x200>;
+                        interrupts = <0 30 0x4>;
                         ti,hwmods = "gpio2";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -124,6 +136,8 @@
 
                 gpio3: gpio@48057000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x48057000 0x200>;
+                        interrupts = <0 31 0x4>;
                         ti,hwmods = "gpio3";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -133,6 +147,8 @@
 
                 gpio4: gpio@48059000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x48059000 0x200>;
+                        interrupts = <0 32 0x4>;
                         ti,hwmods = "gpio4";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -142,6 +158,8 @@
 
                 gpio5: gpio@4805b000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x4805b000 0x200>;
+                        interrupts = <0 33 0x4>;
                         ti,hwmods = "gpio5";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -151,6 +169,8 @@
 
                 gpio6: gpio@4805d000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x4805d000 0x200>;
+                        interrupts = <0 34 0x4>;
                         ti,hwmods = "gpio6";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -160,30 +180,40 @@
 
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
+                        reg = <0x4806a000 0x100>;
+                        interrupts = <0 72 0x4>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
 
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
+                        reg = <0x4806c000 0x100>;
+                        interrupts = <0 73 0x4>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
 
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
+                        reg = <0x48020000 0x100>;
+                        interrupts = <0 74 0x4>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
 
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
+                        reg = <0x4806e000 0x100>;
+                        interrupts = <0 70 0x4>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
 
                 i2c1: i2c@48070000 {
                         compatible = "ti,omap4-i2c";
+                        reg = <0x48070000 0x100>;
+                        interrupts = <0 56 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c1";
@@ -191,6 +221,8 @@
 
                 i2c2: i2c@48072000 {
                         compatible = "ti,omap4-i2c";
+                        reg = <0x48072000 0x100>;
+                        interrupts = <0 57 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c2";
@@ -198,6 +230,8 @@
 
                 i2c3: i2c@48060000 {
                         compatible = "ti,omap4-i2c";
+                        reg = <0x48060000 0x100>;
+                        interrupts = <0 61 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c3";
@@ -205,6 +239,8 @@
 
                 i2c4: i2c@48350000 {
                         compatible = "ti,omap4-i2c";
+                        reg = <0x48350000 0x100>;
+                        interrupts = <0 62 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c4";
@@ -212,6 +248,8 @@
 
                 mcspi1: spi@48098000 {
                         compatible = "ti,omap4-mcspi";
+                        reg = <0x48098000 0x200>;
+                        interrupts = <0 65 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi1";
@@ -220,6 +258,8 @@
 
                 mcspi2: spi@4809a000 {
                         compatible = "ti,omap4-mcspi";
+                        reg = <0x4809a000 0x200>;
+                        interrupts = <0 66 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi2";
@@ -228,6 +268,8 @@
 
                 mcspi3: spi@480b8000 {
                         compatible = "ti,omap4-mcspi";
+                        reg = <0x480b8000 0x200>;
+                        interrupts = <0 91 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi3";
@@ -236,6 +278,8 @@
 
                 mcspi4: spi@480ba000 {
                         compatible = "ti,omap4-mcspi";
+                        reg = <0x480ba000 0x200>;
+                        interrupts = <0 48 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi4";
@@ -244,6 +288,8 @@
 
                 mmc1: mmc@4809c000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x4809c000 0x400>;
+                        interrupts = <0 83 0x4>;
                         ti,hwmods = "mmc1";
                         ti,dual-volt;
                         ti,needs-special-reset;
@@ -251,30 +297,40 @@
 
                 mmc2: mmc@480b4000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x480b4000 0x400>;
+                        interrupts = <0 86 0x4>;
                         ti,hwmods = "mmc2";
                         ti,needs-special-reset;
                 };
 
                 mmc3: mmc@480ad000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x480ad000 0x400>;
+                        interrupts = <0 94 0x4>;
                         ti,hwmods = "mmc3";
                         ti,needs-special-reset;
                 };
 
                 mmc4: mmc@480d1000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x480d1000 0x400>;
+                        interrupts = <0 96 0x4>;
                         ti,hwmods = "mmc4";
                         ti,needs-special-reset;
                 };
 
                 mmc5: mmc@480d5000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x480d5000 0x400>;
+                        interrupts = <0 59 0x4>;
                         ti,hwmods = "mmc5";
                         ti,needs-special-reset;
                 };
 
                 wdt2: wdt@4a314000 {
                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+                        reg = <0x4a314000 0x80>;
+                        interrupts = <0 80 0x4>;
                         ti,hwmods = "wd_timer2";
                 };
 
@@ -282,6 +338,7 @@
                         compatible = "ti,omap4-mcpdm";
                         reg = <0x40132000 0x7f>, /* MPU private access */
                               <0x49032000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
                         interrupts = <0 112 0x4>;
                         interrupt-parent = <&gic>;
                         ti,hwmods = "mcpdm";
@@ -291,9 +348,87 @@
                         compatible = "ti,omap4-dmic";
                         reg = <0x4012e000 0x7f>, /* MPU private access */
                               <0x4902e000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
                         interrupts = <0 114 0x4>;
                         interrupt-parent = <&gic>;
                         ti,hwmods = "dmic";
                 };
+
+                mcbsp1: mcbsp@40122000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40122000 0xff>, /* MPU private access */
+                              <0x49022000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 17 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@40124000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40124000 0xff>, /* MPU private access */
+                              <0x49024000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 22 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp2";
+                };
+
+                mcbsp3: mcbsp@40126000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40126000 0xff>, /* MPU private access */
+                              <0x49026000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 23 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
+
+                mcbsp4: mcbsp@48096000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x48096000 0xff>; /* L4 Interconnect */
+                        reg-names = "mpu";
+                        interrupts = <0 16 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp4";
+                };
+
+                keypad: keypad@4a31c000 {
+                        compatible = "ti,omap4-keypad";
+                        reg = <0x4a31c000 0x80>;
+                        interrupts = <0 120 0x4>;
+                        reg-names = "mpu";
+                        ti,hwmods = "kbd";
+                };
+
+                emif1: emif@4c000000 {
+                        compatible = "ti,emif-4d";
+                        reg = <0x4c000000 0x100>;
+                        interrupts = <0 110 0x4>;
+                        ti,hwmods = "emif1";
+                        phy-type = <1>;
+                        hw-caps-read-idle-ctrl;
+                        hw-caps-ll-interface;
+                        hw-caps-temp-alert;
+                };
+
+                emif2: emif@4d000000 {
+                        compatible = "ti,emif-4d";
+                        reg = <0x4d000000 0x100>;
+                        interrupts = <0 111 0x4>;
+                        ti,hwmods = "emif2";
+                        phy-type = <1>;
+                        hw-caps-read-idle-ctrl;
+                        hw-caps-ll-interface;
+                        hw-caps-temp-alert;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39ad1c82..9c41a3f311aa 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,4 +17,68 @@
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
+
+        vmmcsd_fixed: fixedregulator-mmcsd {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <4>;
+};
+
+&mmc2 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        ti,non-removable;
+};
+
+&mmc3 {
+        bus-width = <4>;
+        ti,non-removable;
+};
+
+&mmc4 {
+        status = "disabled";
+};
+
+&mmc5 {
+        status = "disabled";
+};
+
+&i2c2 {
+        clock-frequency = <400000>;
+
+        /* Pressure Sensor */
+        bmp085@77 {
+                compatible = "bosch,bmp085";
+                reg = <0x77>;
+        };
+};
+
+&i2c4 {
+        clock-frequency = <400000>;
+
+        /* Temperature Sensor */
+        tmp102@48{
+                compatible = "ti,tmp102";
+                reg = <0x48>;
+        };
+};
+
+&keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <8>;
+        linux,keymap = <0x02020073      /* VOLUP */
+                        0x02030072      /* VOLDOWM */
+                        0x020400e7      /* SEND */
+                        0x02050066      /* HOME */
+                        0x0206006b      /* END */
+                        0x020700d9>;    /* SEARCH */
+        linux,input-no-autorepeat;
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e527083746..9ac75b37c992 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -145,6 +145,41 @@
                         #interrupt-cells = <1>;
                 };
 
+                i2c1: i2c@48070000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c1";
+                };
+
+                i2c2: i2c@48072000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c2";
+                };
+
+                i2c3: i2c@48060000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c3";
+                };
+
+                i2c4: i2c@4807A000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c4";
+                };
+
+                i2c5: i2c@4807C000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c5";
+                };
+
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart1";
@@ -180,5 +215,97 @@
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
                 };
+
+                mmc1: mmc@4809c000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc1";
+                        ti,dual-volt;
+                        ti,needs-special-reset;
+                };
+
+                mmc2: mmc@480b4000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc2";
+                        ti,needs-special-reset;
+                };
+
+                mmc3: mmc@480ad000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc3";
+                        ti,needs-special-reset;
+                };
+
+                mmc4: mmc@480d1000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc4";
+                        ti,needs-special-reset;
+                };
+
+                mmc5: mmc@480d5000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc5";
+                        ti,needs-special-reset;
+                };
+
+                keypad: keypad@4ae1c000 {
+                        compatible = "ti,omap4-keypad";
+                        ti,hwmods = "kbd";
+                };
+
+                mcpdm: mcpdm@40132000 {
+                        compatible = "ti,omap4-mcpdm";
+                        reg = <0x40132000 0x7f>, /* MPU private access */
+                              <0x49032000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 112 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "mcpdm";
+                };
+
+                dmic: dmic@4012e000 {
+                        compatible = "ti,omap4-dmic";
+                        reg = <0x4012e000 0x7f>, /* MPU private access */
+                              <0x4902e000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 114 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "dmic";
+                };
+
+                mcbsp1: mcbsp@40122000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40122000 0xff>, /* MPU private access */
+                              <0x49022000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 17 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@40124000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40124000 0xff>, /* MPU private access */
+                              <0x49024000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 22 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp2";
+                };
+
+                mcbsp3: mcbsp@40126000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40126000 0xff>, /* MPU private access */
+                              <0x49026000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 23 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index 802ec5b2fd00..a7ad85e4b8f9 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -135,13 +135,11 @@
                         ssp0: ssp@20084000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
-                                pl022,num-chipselects = <1>;
+                                num-cs = <1>;
                                 cs-gpios = <&gpio 3 5 0>;
 
                                 eeprom: at25@0 {
-                                        pl022,hierarchy = <0>;
                                         pl022,interface = <0>;
-                                        pl022,slave-tx-disable = <0>;
                                         pl022,com-mode = <0>;
                                         pl022,rx-level-trig = <1>;
                                         pl022,tx-level-trig = <1>;
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
deleted file mode 100644
index 34ae3a64ba25..000000000000
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ /dev/null
@@ -1,424 +0,0 @@
-/dts-v1/;
-/ {
-        model = "SiRF Prima2 eVB";
-        compatible = "sirf,prima2-cb", "sirf,prima2";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&intc>;
-
-        memory {
-                reg = <0x00000000 0x20000000>;
-        };
-
-        chosen {
-                bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
-                linux,stdout-path = &uart1;
-        };
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cpu@0 {
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <32768>;
-                        i-cache-size = <32768>;
-                        /* from bootloader */
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                };
-        };
-
-        axi {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0x40000000 0x40000000 0x80000000>;
-
-                l2-cache-controller@80040000 {
-                        compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
-                        reg = <0x80040000 0x1000>;
-                        interrupts = <59>;
-                        arm,tag-latency = <1 1 1>;
-                        arm,data-latency = <1 1 1>;
-                        arm,filter-ranges = <0 0x40000000>;
-                };
-
-                intc: interrupt-controller@80020000 {
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        compatible = "sirf,prima2-intc";
-                        reg = <0x80020000 0x1000>;
-                };
-
-                sys-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x88000000 0x88000000 0x40000>;
-
-                        clock-controller@88000000 {
-                                compatible = "sirf,prima2-clkc";
-                                reg = <0x88000000 0x1000>;
-                                interrupts = <3>;
-                        };
-
-                        reset-controller@88010000 {
-                                compatible = "sirf,prima2-rstc";
-                                reg = <0x88010000 0x1000>;
-                        };
-
-                        rsc-controller@88020000 {
-                                compatible = "sirf,prima2-rsc";
-                                reg = <0x88020000 0x1000>;
-                        };
-                };
-
-                mem-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x90000000 0x90000000 0x10000>;
-
-                        memory-controller@90000000 {
-                                compatible = "sirf,prima2-memc";
-                                reg = <0x90000000 0x10000>;
-                                interrupts = <27>;
-                        };
-                };
-
-                disp-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x90010000 0x90010000 0x30000>;
-
-                        display@90010000 {
-                                compatible = "sirf,prima2-lcd";
-                                reg = <0x90010000 0x20000>;
-                                interrupts = <30>;
-                        };
-
-                        vpp@90020000 {
-                                compatible = "sirf,prima2-vpp";
-                                reg = <0x90020000 0x10000>;
-                                interrupts = <31>;
-                        };
-                };
-
-                graphics-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x98000000 0x98000000 0x8000000>;
-
-                        graphics@98000000 {
-                                compatible = "powervr,sgx531";
-                                reg = <0x98000000 0x8000000>;
-                                interrupts = <6>;
-                        };
-                };
-
-                multimedia-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xa0000000 0xa0000000 0x8000000>;
-
-                        multimedia@a0000000 {
-                                compatible = "sirf,prima2-video-codec";
-                                reg = <0xa0000000 0x8000000>;
-                                interrupts = <5>;
-                        };
-                };
-
-                dsp-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xa8000000 0xa8000000 0x2000000>;
-
-                        dspif@a8000000 {
-                                compatible = "sirf,prima2-dspif";
-                                reg = <0xa8000000 0x10000>;
-                                interrupts = <9>;
-                        };
-
-                        gps@a8010000 {
-                                compatible = "sirf,prima2-gps";
-                                reg = <0xa8010000 0x10000>;
-                                interrupts = <7>;
-                        };
-
-                        dsp@a9000000 {
-                                compatible = "sirf,prima2-dsp";
-                                reg = <0xa9000000 0x1000000>;
-                                interrupts = <8>;
-                        };
-                };
-
-                peri-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xb0000000 0xb0000000 0x180000>;
-
-                        timer@b0020000 {
-                                compatible = "sirf,prima2-tick";
-                                reg = <0xb0020000 0x1000>;
-                                interrupts = <0>;
-                        };
-
-                        nand@b0030000 {
-                                compatible = "sirf,prima2-nand";
-                                reg = <0xb0030000 0x10000>;
-                                interrupts = <41>;
-                        };
-
-                        audio@b0040000 {
-                                compatible = "sirf,prima2-audio";
-                                reg = <0xb0040000 0x10000>;
-                                interrupts = <35>;
-                        };
-
-                        uart0: uart@b0050000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-uart";
-                                reg = <0xb0050000 0x10000>;
-                                interrupts = <17>;
-                        };
-
-                        uart1: uart@b0060000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-uart";
-                                reg = <0xb0060000 0x10000>;
-                                interrupts = <18>;
-                        };
-
-                        uart2: uart@b0070000 {
-                                cell-index = <2>;
-                                compatible = "sirf,prima2-uart";
-                                reg = <0xb0070000 0x10000>;
-                                interrupts = <19>;
-                        };
-
-                        usp0: usp@b0080000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-usp";
-                                reg = <0xb0080000 0x10000>;
-                                interrupts = <20>;
-                        };
-
-                        usp1: usp@b0090000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-usp";
-                                reg = <0xb0090000 0x10000>;
-                                interrupts = <21>;
-                        };
-
-                        usp2: usp@b00a0000 {
-                                cell-index = <2>;
-                                compatible = "sirf,prima2-usp";
-                                reg = <0xb00a0000 0x10000>;
-                                interrupts = <22>;
-                        };
-
-                        dmac0: dma-controller@b00b0000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-dmac";
-                                reg = <0xb00b0000 0x10000>;
-                                interrupts = <12>;
-                        };
-
-                        dmac1: dma-controller@b0160000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-dmac";
-                                reg = <0xb0160000 0x10000>;
-                                interrupts = <13>;
-                        };
-
-                        vip@b00C0000 {
-                                compatible = "sirf,prima2-vip";
-                                reg = <0xb00C0000 0x10000>;
-                        };
-
-                        spi0: spi@b00d0000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-spi";
-                                reg = <0xb00d0000 0x10000>;
-                                interrupts = <15>;
-                        };
-
-                        spi1: spi@b0170000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-spi";
-                                reg = <0xb0170000 0x10000>;
-                                interrupts = <16>;
-                        };
-
-                        i2c0: i2c@b00e0000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-i2c";
-                                reg = <0xb00e0000 0x10000>;
-                                interrupts = <24>;
-                        };
-
-                        i2c1: i2c@b00f0000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-i2c";
-                                reg = <0xb00f0000 0x10000>;
-                                interrupts = <25>;
-                        };
-
-                        tsc@b0110000 {
-                                compatible = "sirf,prima2-tsc";
-                                reg = <0xb0110000 0x10000>;
-                                interrupts = <33>;
-                        };
-
-                        gpio: gpio-controller@b0120000 {
-                                #gpio-cells = <2>;
-                                #interrupt-cells = <2>;
-                                compatible = "sirf,prima2-gpio-pinmux";
-                                reg = <0xb0120000 0x10000>;
-                                gpio-controller;
-                                interrupt-controller;
-                        };
-
-                        pwm@b0130000 {
-                                compatible = "sirf,prima2-pwm";
-                                reg = <0xb0130000 0x10000>;
-                        };
-
-                        efusesys@b0140000 {
-                                compatible = "sirf,prima2-efuse";
-                                reg = <0xb0140000 0x10000>;
-                        };
-
-                        pulsec@b0150000 {
-                                compatible = "sirf,prima2-pulsec";
-                                reg = <0xb0150000 0x10000>;
-                                interrupts = <48>;
-                        };
-
-                        pci-iobg {
-                                compatible = "sirf,prima2-pciiobg", "simple-bus";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                ranges = <0x56000000 0x56000000 0x1b00000>;
-
-                                sd0: sdhci@56000000 {
-                                        cell-index = <0>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56000000 0x100000>;
-                                        interrupts = <38>;
-                                };
-
-                                sd1: sdhci@56100000 {
-                                        cell-index = <1>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56100000 0x100000>;
-                                        interrupts = <38>;
-                                };
-
-                                sd2: sdhci@56200000 {
-                                        cell-index = <2>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56200000 0x100000>;
-                                        interrupts = <23>;
-                                };
-
-                                sd3: sdhci@56300000 {
-                                        cell-index = <3>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56300000 0x100000>;
-                                        interrupts = <23>;
-                                };
-
-                                sd4: sdhci@56400000 {
-                                        cell-index = <4>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56400000 0x100000>;
-                                        interrupts = <39>;
-                                };
-
-                                sd5: sdhci@56500000 {
-                                        cell-index = <5>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56500000 0x100000>;
-                                        interrupts = <39>;
-                                };
-
-                                pci-copy@57900000 {
-                                        compatible = "sirf,prima2-pcicp";
-                                        reg = <0x57900000 0x100000>;
-                                        interrupts = <40>;
-                                };
-
-                                rom-interface@57a00000 {
-                                        compatible = "sirf,prima2-romif";
-                                        reg = <0x57a00000 0x100000>;
-                                };
-                        };
-                };
-
-                rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x80030000 0x10000>;
-
-                        gpsrtc@1000 {
-                                compatible = "sirf,prima2-gpsrtc";
-                                reg = <0x1000 0x1000>;
-                                interrupts = <55 56 57>;
-                        };
-
-                        sysrtc@2000 {
-                                compatible = "sirf,prima2-sysrtc";
-                                reg = <0x2000 0x1000>;
-                                interrupts = <52 53 54>;
-                        };
-
-                        pwrc@3000 {
-                                compatible = "sirf,prima2-pwrc";
-                                reg = <0x3000 0x1000>;
-                                interrupts = <32>;
-                        };
-                };
-
-                uus-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xb8000000 0xb8000000 0x40000>;
-
-                        usb0: usb@b00e0000 {
-                                compatible = "chipidea,ci13611a-prima2";
-                                reg = <0xb8000000 0x10000>;
-                                interrupts = <10>;
-                        };
-
-                        usb1: usb@b00f0000 {
-                                compatible = "chipidea,ci13611a-prima2";
-                                reg = <0xb8010000 0x10000>;
-                                interrupts = <11>;
-                        };
-
-                        sata@b00f0000 {
-                                compatible = "synopsys,dwc-ahsata";
-                                reg = <0xb8020000 0x10000>;
-                                interrupts = <37>;
-                        };
-
-                        security@b00f0000 {
-                                compatible = "sirf,prima2-security";
-                                reg = <0xb8030000 0x10000>;
-                                interrupts = <42>;
-                        };
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts
new file mode 100644
index 000000000000..57286b4e7b87
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-evb.dts
@@ -0,0 +1,37 @@
+/*
+ * DTS file for CSR SiRFprimaII Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "prima2.dtsi"
+
+/ {
+        model = "CSR SiRFprimaII Evaluation Board";
+        compatible = "sirf,prima2", "sirf,prima2-cb";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        axi {
+                peri-iobg {
+                        uart@b0060000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart1_pins_a>;
+                        };
+                        spi@b00d0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi0_pins_a>;
+                        };
+                        spi@b0170000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi1_pins_a>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
new file mode 100644
index 000000000000..055fca542120
--- /dev/null
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -0,0 +1,640 @@
+/*
+ * DTS file for CSR SiRFprimaII SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "sirf,prima2";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&intc>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-size = <32768>;
+                        /* from bootloader */
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                };
+        };
+
+        axi {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x40000000 0x40000000 0x80000000>;
+
+                l2-cache-controller@80040000 {
+                        compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
+                        reg = <0x80040000 0x1000>;
+                        interrupts = <59>;
+                        arm,tag-latency = <1 1 1>;
+                        arm,data-latency = <1 1 1>;
+                        arm,filter-ranges = <0 0x40000000>;
+                };
+
+                intc: interrupt-controller@80020000 {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        compatible = "sirf,prima2-intc";
+                        reg = <0x80020000 0x1000>;
+                };
+
+                sys-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x88000000 0x88000000 0x40000>;
+
+                        clock-controller@88000000 {
+                                compatible = "sirf,prima2-clkc";
+                                reg = <0x88000000 0x1000>;
+                                interrupts = <3>;
+                        };
+
+                        reset-controller@88010000 {
+                                compatible = "sirf,prima2-rstc";
+                                reg = <0x88010000 0x1000>;
+                        };
+
+                        rsc-controller@88020000 {
+                                compatible = "sirf,prima2-rsc";
+                                reg = <0x88020000 0x1000>;
+                        };
+                };
+
+                mem-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90000000 0x90000000 0x10000>;
+
+                        memory-controller@90000000 {
+                                compatible = "sirf,prima2-memc";
+                                reg = <0x90000000 0x10000>;
+                                interrupts = <27>;
+                        };
+                };
+
+                disp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90010000 0x90010000 0x30000>;
+
+                        display@90010000 {
+                                compatible = "sirf,prima2-lcd";
+                                reg = <0x90010000 0x20000>;
+                                interrupts = <30>;
+                        };
+
+                        vpp@90020000 {
+                                compatible = "sirf,prima2-vpp";
+                                reg = <0x90020000 0x10000>;
+                                interrupts = <31>;
+                        };
+                };
+
+                graphics-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x98000000 0x98000000 0x8000000>;
+
+                        graphics@98000000 {
+                                compatible = "powervr,sgx531";
+                                reg = <0x98000000 0x8000000>;
+                                interrupts = <6>;
+                        };
+                };
+
+                multimedia-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa0000000 0xa0000000 0x8000000>;
+
+                        multimedia@a0000000 {
+                                compatible = "sirf,prima2-video-codec";
+                                reg = <0xa0000000 0x8000000>;
+                                interrupts = <5>;
+                        };
+                };
+
+                dsp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa8000000 0xa8000000 0x2000000>;
+
+                        dspif@a8000000 {
+                                compatible = "sirf,prima2-dspif";
+                                reg = <0xa8000000 0x10000>;
+                                interrupts = <9>;
+                        };
+
+                        gps@a8010000 {
+                                compatible = "sirf,prima2-gps";
+                                reg = <0xa8010000 0x10000>;
+                                interrupts = <7>;
+                        };
+
+                        dsp@a9000000 {
+                                compatible = "sirf,prima2-dsp";
+                                reg = <0xa9000000 0x1000000>;
+                                interrupts = <8>;
+                        };
+                };
+
+                peri-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb0000000 0xb0000000 0x180000>;
+
+                        timer@b0020000 {
+                                compatible = "sirf,prima2-tick";
+                                reg = <0xb0020000 0x1000>;
+                                interrupts = <0>;
+                        };
+
+                        nand@b0030000 {
+                                compatible = "sirf,prima2-nand";
+                                reg = <0xb0030000 0x10000>;
+                                interrupts = <41>;
+                        };
+
+                        audio@b0040000 {
+                                compatible = "sirf,prima2-audio";
+                                reg = <0xb0040000 0x10000>;
+                                interrupts = <35>;
+                        };
+
+                        uart0: uart@b0050000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0050000 0x10000>;
+                                interrupts = <17>;
+                        };
+
+                        uart1: uart@b0060000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0060000 0x10000>;
+                                interrupts = <18>;
+                        };
+
+                        uart2: uart@b0070000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0070000 0x10000>;
+                                interrupts = <19>;
+                        };
+
+                        usp0: usp@b0080000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0080000 0x10000>;
+                                interrupts = <20>;
+                        };
+
+                        usp1: usp@b0090000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0090000 0x10000>;
+                                interrupts = <21>;
+                        };
+
+                        usp2: usp@b00a0000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb00a0000 0x10000>;
+                                interrupts = <22>;
+                        };
+
+                        dmac0: dma-controller@b00b0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb00b0000 0x10000>;
+                                interrupts = <12>;
+                        };
+
+                        dmac1: dma-controller@b0160000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb0160000 0x10000>;
+                                interrupts = <13>;
+                        };
+
+                        vip@b00C0000 {
+                                compatible = "sirf,prima2-vip";
+                                reg = <0xb00C0000 0x10000>;
+                        };
+
+                        spi0: spi@b00d0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb00d0000 0x10000>;
+                                interrupts = <15>;
+                        };
+
+                        spi1: spi@b0170000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb0170000 0x10000>;
+                                interrupts = <16>;
+                        };
+
+                        i2c0: i2c@b00e0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00e0000 0x10000>;
+                                interrupts = <24>;
+                        };
+
+                        i2c1: i2c@b00f0000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00f0000 0x10000>;
+                                interrupts = <25>;
+                        };
+
+                        tsc@b0110000 {
+                                compatible = "sirf,prima2-tsc";
+                                reg = <0xb0110000 0x10000>;
+                                interrupts = <33>;
+                        };
+
+                        gpio: pinctrl@b0120000 {
+                                #gpio-cells = <2>;
+                                #interrupt-cells = <2>;
+                                compatible = "sirf,prima2-pinctrl";
+                                reg = <0xb0120000 0x10000>;
+                                interrupts = <43 44 45 46 47>;
+                                gpio-controller;
+                                interrupt-controller;
+
+                                lcd_16pins_a: lcd0@0 {
+                                        lcd {
+                                                sirf,pins = "lcd_16bitsgrp";
+                                                sirf,function = "lcd_16bits";
+                                        };
+                                };
+                                lcd_18pins_a: lcd0@1 {
+                                        lcd {
+                                                sirf,pins = "lcd_18bitsgrp";
+                                                sirf,function = "lcd_18bits";
+                                        };
+                                };
+                                lcd_24pins_a: lcd0@2 {
+                                        lcd {
+                                                sirf,pins = "lcd_24bitsgrp";
+                                                sirf,function = "lcd_24bits";
+                                        };
+                                };
+                                lcdrom_pins_a: lcdrom0@0 {
+                                        lcd {
+                                                sirf,pins = "lcdromgrp";
+                                                sirf,function = "lcdrom";
+                                        };
+                                };
+                                uart0_pins_a: uart0@0 {
+                                        uart {
+                                                sirf,pins = "uart0grp";
+                                                sirf,function = "uart0";
+                                        };
+                                };
+                                uart1_pins_a: uart1@0 {
+                                        uart {
+                                                sirf,pins = "uart1grp";
+                                                sirf,function = "uart1";
+                                        };
+                                };
+                                uart2_pins_a: uart2@0 {
+                                        uart {
+                                                sirf,pins = "uart2grp";
+                                                sirf,function = "uart2";
+                                        };
+                                };
+                                uart2_noflow_pins_a: uart2@1 {
+                                        uart {
+                                                sirf,pins = "uart2_nostreamctrlgrp";
+                                                sirf,function = "uart2_nostreamctrl";
+                                        };
+                                };
+                                spi0_pins_a: spi0@0 {
+                                        spi {
+                                                sirf,pins = "spi0grp";
+                                                sirf,function = "spi0";
+                                        };
+                                };
+                                spi1_pins_a: spi1@0 {
+                                        spi {
+                                                sirf,pins = "spi1grp";
+                                                sirf,function = "spi1";
+                                        };
+                                };
+                                i2c0_pins_a: i2c0@0 {
+                                        i2c {
+                                                sirf,pins = "i2c0grp";
+                                                sirf,function = "i2c0";
+                                        };
+                                };
+                                i2c1_pins_a: i2c1@0 {
+                                        i2c {
+                                                sirf,pins = "i2c1grp";
+                                                sirf,function = "i2c1";
+                                        };
+                                };
+                                pwm0_pins_a: pwm0@0 {
+                                        pwm {
+                                                sirf,pins = "pwm0grp";
+                                                sirf,function = "pwm0";
+                                        };
+                                };
+                                pwm1_pins_a: pwm1@0 {
+                                        pwm {
+                                                sirf,pins = "pwm1grp";
+                                                sirf,function = "pwm1";
+                                        };
+                                };
+                                pwm2_pins_a: pwm2@0 {
+                                        pwm {
+                                                sirf,pins = "pwm2grp";
+                                                sirf,function = "pwm2";
+                                        };
+                                };
+                                pwm3_pins_a: pwm3@0 {
+                                        pwm {
+                                                sirf,pins = "pwm3grp";
+                                                sirf,function = "pwm3";
+                                        };
+                                };
+                                gps_pins_a: gps@0 {
+                                        gps {
+                                                sirf,pins = "gpsgrp";
+                                                sirf,function = "gps";
+                                        };
+                                };
+                                vip_pins_a: vip@0 {
+                                        vip {
+                                                sirf,pins = "vipgrp";
+                                                sirf,function = "vip";
+                                        };
+                                };
+                                sdmmc0_pins_a: sdmmc0@0 {
+                                        sdmmc0 {
+                                                sirf,pins = "sdmmc0grp";
+                                                sirf,function = "sdmmc0";
+                                        };
+                                };
+                                sdmmc1_pins_a: sdmmc1@0 {
+                                        sdmmc1 {
+                                                sirf,pins = "sdmmc1grp";
+                                                sirf,function = "sdmmc1";
+                                        };
+                                };
+                                sdmmc2_pins_a: sdmmc2@0 {
+                                        sdmmc2 {
+                                                sirf,pins = "sdmmc2grp";
+                                                sirf,function = "sdmmc2";
+                                        };
+                                };
+                                sdmmc3_pins_a: sdmmc3@0 {
+                                        sdmmc3 {
+                                                sirf,pins = "sdmmc3grp";
+                                                sirf,function = "sdmmc3";
+                                        };
+                                };
+                                sdmmc4_pins_a: sdmmc4@0 {
+                                        sdmmc4 {
+                                                sirf,pins = "sdmmc4grp";
+                                                sirf,function = "sdmmc4";
+                                        };
+                                };
+                                sdmmc5_pins_a: sdmmc5@0 {
+                                        sdmmc5 {
+                                                sirf,pins = "sdmmc5grp";
+                                                sirf,function = "sdmmc5";
+                                        };
+                                };
+                                i2s_pins_a: i2s@0 {
+                                        i2s {
+                                                sirf,pins = "i2sgrp";
+                                                sirf,function = "i2s";
+                                        };
+                                };
+                                ac97_pins_a: ac97@0 {
+                                        ac97 {
+                                                sirf,pins = "ac97grp";
+                                                sirf,function = "ac97";
+                                        };
+                                };
+                                nand_pins_a: nand@0 {
+                                        nand {
+                                                sirf,pins = "nandgrp";
+                                                sirf,function = "nand";
+                                        };
+                                };
+                                usp0_pins_a: usp0@0 {
+                                        usp0 {
+                                                sirf,pins = "usp0grp";
+                                                sirf,function = "usp0";
+                                        };
+                                };
+                                usp1_pins_a: usp1@0 {
+                                        usp1 {
+                                                sirf,pins = "usp1grp";
+                                                sirf,function = "usp1";
+                                        };
+                                };
+                                usp2_pins_a: usp2@0 {
+                                        usp2 {
+                                                sirf,pins = "usp2grp";
+                                                sirf,function = "usp2";
+                                        };
+                                };
+                                usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
+                                        usb0_utmi_drvbus {
+                                                sirf,pins = "usb0_utmi_drvbusgrp";
+                                                sirf,function = "usb0_utmi_drvbus";
+                                        };
+                                };
+                                usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
+                                        usb1_utmi_drvbus {
+                                                sirf,pins = "usb1_utmi_drvbusgrp";
+                                                sirf,function = "usb1_utmi_drvbus";
+                                        };
+                                };
+                                warm_rst_pins_a: warm_rst@0 {
+                                        warm_rst {
+                                                sirf,pins = "warm_rstgrp";
+                                                sirf,function = "warm_rst";
+                                        };
+                                };
+                                pulse_count_pins_a: pulse_count@0 {
+                                        pulse_count {
+                                                sirf,pins = "pulse_countgrp";
+                                                sirf,function = "pulse_count";
+                                        };
+                                };
+                                cko0_rst_pins_a: cko0_rst@0 {
+                                        cko0_rst {
+                                                sirf,pins = "cko0_rstgrp";
+                                                sirf,function = "cko0_rst";
+                                        };
+                                };
+                                cko1_rst_pins_a: cko1_rst@0 {
+                                        cko1_rst {
+                                                sirf,pins = "cko1_rstgrp";
+                                                sirf,function = "cko1_rst";
+                                        };
+                                };
+                        };
+
+                        pwm@b0130000 {
+                                compatible = "sirf,prima2-pwm";
+                                reg = <0xb0130000 0x10000>;
+                        };
+
+                        efusesys@b0140000 {
+                                compatible = "sirf,prima2-efuse";
+                                reg = <0xb0140000 0x10000>;
+                        };
+
+                        pulsec@b0150000 {
+                                compatible = "sirf,prima2-pulsec";
+                                reg = <0xb0150000 0x10000>;
+                                interrupts = <48>;
+                        };
+
+                        pci-iobg {
+                                compatible = "sirf,prima2-pciiobg", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x56000000 0x56000000 0x1b00000>;
+
+                                sd0: sdhci@56000000 {
+                                        cell-index = <0>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56000000 0x100000>;
+                                        interrupts = <38>;
+                                };
+
+                                sd1: sdhci@56100000 {
+                                        cell-index = <1>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56100000 0x100000>;
+                                        interrupts = <38>;
+                                };
+
+                                sd2: sdhci@56200000 {
+                                        cell-index = <2>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56200000 0x100000>;
+                                        interrupts = <23>;
+                                };
+
+                                sd3: sdhci@56300000 {
+                                        cell-index = <3>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56300000 0x100000>;
+                                        interrupts = <23>;
+                                };
+
+                                sd4: sdhci@56400000 {
+                                        cell-index = <4>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56400000 0x100000>;
+                                        interrupts = <39>;
+                                };
+
+                                sd5: sdhci@56500000 {
+                                        cell-index = <5>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56500000 0x100000>;
+                                        interrupts = <39>;
+                                };
+
+                                pci-copy@57900000 {
+                                        compatible = "sirf,prima2-pcicp";
+                                        reg = <0x57900000 0x100000>;
+                                        interrupts = <40>;
+                                };
+
+                                rom-interface@57a00000 {
+                                        compatible = "sirf,prima2-romif";
+                                        reg = <0x57a00000 0x100000>;
+                                };
+                        };
+                };
+
+                rtc-iobg {
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x80030000 0x10000>;
+
+                        gpsrtc@1000 {
+                                compatible = "sirf,prima2-gpsrtc";
+                                reg = <0x1000 0x1000>;
+                                interrupts = <55 56 57>;
+                        };
+
+                        sysrtc@2000 {
+                                compatible = "sirf,prima2-sysrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <52 53 54>;
+                        };
+
+                        pwrc@3000 {
+                                compatible = "sirf,prima2-pwrc";
+                                reg = <0x3000 0x1000>;
+                                interrupts = <32>;
+                        };
+                };
+
+                uus-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb8000000 0xb8000000 0x40000>;
+
+                        usb0: usb@b00e0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8000000 0x10000>;
+                                interrupts = <10>;
+                        };
+
+                        usb1: usb@b00f0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8010000 0x10000>;
+                                interrupts = <11>;
+                        };
+
+                        sata@b00f0000 {
+                                compatible = "synopsys,dwc-ahsata";
+                                reg = <0xb8020000 0x10000>;
+                                interrupts = <37>;
+                        };
+
+                        security@b00f0000 {
+                                compatible = "sirf,prima2-security";
+                                reg = <0xb8030000 0x10000>;
+                                interrupts = <42>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
new file mode 100644
index 000000000000..d7c5d721a5c7
--- /dev/null
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -0,0 +1,14 @@
+/* The pxa3xx skeleton simply augments the 2xx version */
+/include/ "pxa2xx.dtsi"
+
+/ {
+        model = "Marvell PXA27x familiy SoC";
+        compatible = "marvell,pxa27x";
+
+        pxabus {
+                pxairq: interrupt-controller@40d00000 {
+                        marvell,intc-priority;
+                        marvell,intc-nr-irqs = <34>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
new file mode 100644
index 000000000000..f18aad35e8b3
--- /dev/null
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -0,0 +1,132 @@
+/*
+ * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Marvell PXA2xx family SoC";
+        compatible = "marvell,pxa2xx";
+        interrupt-parent = <&pxairq>;
+
+        aliases {
+                serial0 = &ffuart;
+                serial1 = &btuart;
+                serial2 = &stuart;
+                serial3 = &hwuart;
+                i2c0 = &pwri2c;
+                i2c1 = &pxai2c1;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,xscale";
+                };
+        };
+
+        pxabus {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                pxairq: interrupt-controller@40d00000 {
+                        #interrupt-cells = <1>;
+                        compatible = "marvell,pxa-intc";
+                        interrupt-controller;
+                        interrupt-parent;
+                        marvell,intc-nr-irqs = <32>;
+                        reg = <0x40d00000 0xd0>;
+                };
+
+                gpio: gpio@40e00000 {
+                        compatible = "mrvl,pxa-gpio";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0x40e00000 0x10000>;
+                        gpio-controller;
+                        #gpio-cells = <0x2>;
+                        interrupts = <10>;
+                        interrupt-names = "gpio_mux";
+                        interrupt-controller;
+                        #interrupt-cells = <0x2>;
+                        ranges;
+
+                        gcb0: gpio@40e00000 {
+                                reg = <0x40e00000 0x4>;
+                        };
+
+                        gcb1: gpio@40e00004 {
+                                reg = <0x40e00004 0x4>;
+                        };
+
+                        gcb2: gpio@40e00008 {
+                                reg = <0x40e00008 0x4>;
+                        };
+                        gcb3: gpio@40e0000c {
+                                reg = <0x40e0000c 0x4>;
+                        };
+                };
+
+                ffuart: uart@40100000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x40100000 0x30>;
+                        interrupts = <22>;
+                        status = "disabled";
+                };
+
+                btuart: uart@40200000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x40200000 0x30>;
+                        interrupts = <21>;
+                        status = "disabled";
+                };
+
+                stuart: uart@40700000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x40700000 0x30>;
+                        interrupts = <20>;
+                        status = "disabled";
+                };
+
+                hwuart: uart@41100000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x41100000 0x30>;
+                        interrupts = <7>;
+                        status = "disabled";
+                };
+
+                pxai2c1: i2c@40301680 {
+                        compatible = "mrvl,pxa-i2c";
+                        reg = <0x40301680 0x30>;
+                        interrupts = <18>;
+                        #address-cells = <0x1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                usb0: ohci@4c000000 {
+                        compatible = "mrvl,pxa-ohci";
+                        reg = <0x4c000000 0x10000>;
+                        interrupts = <3>;
+                        status = "disabled";
+                };
+
+                mmc0: mmc@41100000 {
+                        compatible = "mrvl,pxa-mmc";
+                        reg = <0x41100000 0x1000>;
+                        interrupts = <23>;
+                        status = "disabled";
+                };
+
+                rtc@40900000 {
+                        compatible = "marvell,pxa-rtc";
+                        reg = <0x40900000 0x3c>;
+                        interrupts = <30 31>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
new file mode 100644
index 000000000000..f9d92da86783
--- /dev/null
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -0,0 +1,32 @@
+/* The pxa3xx skeleton simply augments the 2xx version */
+/include/ "pxa2xx.dtsi"
+
+/ {
+        model = "Marvell PXA3xx familiy SoC";
+        compatible = "marvell,pxa3xx";
+
+        pxabus {
+                pwri2c: i2c@40f500c0 {
+                        compatible = "mrvl,pwri2c";
+                        reg = <0x40f500c0 0x30>;
+                        interrupts = <6>;
+                        #address-cells = <0x1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                nand0: nand@43100000 {
+                        compatible = "marvell,pxa3xx-nand";
+                        reg = <0x43100000 90>;
+                        interrupts = <45>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;      
+                        status = "disabled";
+                };
+
+                pxairq: interrupt-controller@40d00000 {
+                        marvell,intc-priority;
+                        marvell,intc-nr-irqs = <56>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index aebf32de73b4..a3be44d86bcd 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -25,6 +25,11 @@
                 interrupt-parent = <&intc>;
                 ranges;
 
+                L2: l2-cache {
+                        compatible = "marvell,tauros2-cache";
+                        marvell,tauros2-cache-features = <0x3>;
+                };
+
                 axi@d4200000 {  /* AXI */
                         compatible = "mrvl,axi-bus", "simple-bus";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index f146dbf6f7f8..c3ef1ad26b6a 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -275,6 +275,160 @@
         i2c@7000d000 {
                 status = "okay";
                 clock-frequency = <400000>;
+
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo0";
+                                        regulator-name = "vdd_ldo0,vddio_pex_clk";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
         };
 
         pmc {
@@ -310,6 +464,72 @@
                 bus-width = <8>;
         };
 
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_1v5";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        gpio = <&pmic 0 0>;
+                };
+
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_1v2";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&pmic 1 0>;
+                        enable-active-high;
+                };
+
+                regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd_1v05";
+                        regulator-min-microvolt = <1050000>;
+                        regulator-max-microvolt = <1050000>;
+                        gpio = <&pmic 2 0>;
+                        enable-active-high;
+                        /* Hack until board-harmony-pcie.c is removed */
+                        status = "disabled";
+                };
+
+                regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "vdd_pnl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        enable-active-high;
+                };
+
+                regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        enable-active-high;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-wm8903-harmony",
                              "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
new file mode 100644
index 000000000000..a2d6d6541f83
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+        model = "Avionic Design Medcom-Wide board";
+        compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
+
+        i2c@7000c000 {
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <187 0x04>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff
+                                    0xffffffff
+                                    0
+                                    0xffffffff
+                                    0xffffffff>;
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 5000000>;
+
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
+        sound {
+                compatible = "ad,tegra-audio-wm8903-medcom-wide",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "Avionic Design Medcom-Wide";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 684a9e1ff7e9..ddf287f52d49 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -272,12 +272,170 @@
                 status = "okay";
                 clock-frequency = <400000>;
 
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        sys-supply = <&p5valw_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "+1.2vs_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "+1.0vs_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "+3.7vs_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+
+                                /* LDO0 is not connected to anything */
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "+1.1vs_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "+1.2vs_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "+3.3vs_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "+2.85vs_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        /*
+                                         * Research indicates this should be
+                                         * 1.8v; other boards that use this
+                                         * rail for the same purpose need it
+                                         * set to 1.8v. The schematic signal
+                                         * name is incorrect; perhaps copied
+                                         * from an incorrect NVIDIA reference.
+                                         */
+                                        regulator-name = "+2.85vs_ldo6,avdd_vdac";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "+3.3vs_ldo7,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "+3.3vs_rtc";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+
                 adt7461@4c {
                         compatible = "adi,adt7461";
                         reg = <0x4c>;
                 };
         };
 
+        pmc {
+                nvidia,invert-interrupt;
+        };
+
         usb@c5000000 {
                 status = "okay";
         };
@@ -325,6 +483,21 @@
                 };
         };
 
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                p5valw_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "+5valw";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-alc5632-paz00",
                         "nvidia,tegra-audio-alc5632";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
new file mode 100644
index 000000000000..331a3ef24d59
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -0,0 +1,50 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+        model = "Avionic Design Plutux board";
+        compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
+
+        i2c@7000c000 {
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <187 0x04>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff
+                                    0xffffffff
+                                    0
+                                    0xffffffff
+                                    0xffffffff>;
+                };
+        };
+
+        sound {
+                compatible = "ad,tegra-audio-plutux",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "Avionic Design Plutux";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 85e621ab2968..e60dc7124e92 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -374,6 +374,154 @@
                 status = "okay";
                 clock-frequency = <400000>;
 
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sm0,vdd_core";
+                                        regulator-min-microvolt = <1300000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1125000>;
+                                        regulator-max-microvolt = <1125000>;
+                                        regulator-always-on;
+                                };
+
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+
+                                /* LDO0 is not connected to anything */
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+
                 temperature-sensor@4c {
                         compatible = "nct1008";
                         reg = <0x4c>;
@@ -387,6 +535,10 @@
                 };
         };
 
+        pmc {
+                nvidia,invert-interrupt;
+        };
+
         memory-controller@0x7000f400 {
                 emc-table@190000 {
                         reg = <190000>;
@@ -473,6 +625,40 @@
                 };
         };
 
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_1v5";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        gpio = <&pmic 0 0>;
+                };
+
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_1v2";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&pmic 1 0>;
+                        enable-active-high;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-wm8903-seaboard",
                              "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
new file mode 100644
index 000000000000..f18cec9f6a77
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -0,0 +1,449 @@
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "Avionic Design Tamonten SOM";
+        compatible = "ad,tamonten", "nvidia,tegra20";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+                                        "spia", "spib", "spic";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtd";
+                                nvidia,function = "sdio2";
+                        };
+                        dtb {
+                                nvidia,pins = "dtb", "dtc", "dte";
+                                nvidia,function = "rsvd1";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uarta";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                        "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                        "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                        "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc", "spdi", "spdo", "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "pwm";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "spdif";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+                                        "cdev1", "cdev2", "dap1", "dtb", "gma",
+                                        "gmb", "gmc", "gmd", "gme", "gpu7",
+                                        "gpv", "i2cp", "pta", "rm", "slxa",
+                                        "slxk", "spia", "spib", "uac";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_csus {
+                                nvidia,pins = "csus", "spid", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+                                        "dtc", "dte", "dtf", "gpu", "sdio1",
+                                        "slxc", "slxd", "spdi", "spdo", "spig",
+                                        "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ddc {
+                                nvidia,pins = "ddc", "dta", "dtd", "kbca",
+                                        "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+                                        "sdc";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0", "owc", "sdb";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_irrx {
+                                nvidia,pins = "irrx", "irtx", "sdd", "spic",
+                                        "spie", "spih", "uaa", "uab", "uad",
+                                        "uca", "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                        "lvs", "pmc";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
+
+        i2s@70002800 {
+                status = "okay";
+        };
+
+        serial@70006300 {
+                clock-frequency = <216000000>;
+                status = "okay";
+        };
+
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+                status = "okay";
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+                status = "okay";
+
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sys_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sys_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sys_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo0";
+                                        regulator-name = "vdd_ldo0,vddio_pex_clk";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac";
+                                        /*
+                                         * According to the Tegra 2 Automotive
+                                         * DataSheet, a typical value for this
+                                         * would be 2.8V, but the PMIC only
+                                         * supports 2.85V.
+                                         */
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
+                                        /*
+                                         * According to the Tegra 2 Automotive
+                                         * DataSheet, a typical value for this
+                                         * would be 2.8V, but the PMIC only
+                                         * supports 2.85V.
+                                         */
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
+        pmc {
+                nvidia,invert-interrupt;
+        };
+
+        usb@c5008000 {
+                status = "okay";
+        };
+
+        sdhci@c8000600 {
+                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+                bus-width = <4>;
+                status = "okay";
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
new file mode 100644
index 000000000000..9aff31b0fe4a
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -0,0 +1,53 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+        model = "Avionic Design Tamonten Evaluation Carrier";
+        compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
+
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+                status = "okay";
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <187 0x04>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff
+                                    0xffffffff
+                                    0
+                                    0xffffffff
+                                    0xffffffff>;
+                };
+        };
+
+        sound {
+                compatible = "ad,tegra-audio-wm8903-tec",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "Avionic Design TEC";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index be90544e6b59..3e5952fcfbc5 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -289,6 +289,158 @@
         i2c@7000d000 {
                 status = "okay";
                 clock-frequency = <400000>;
+
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+
+                                /* LDO0 is not connected to anything */
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
+        pmc {
+                nvidia,invert-interrupt;
         };
 
         usb@c5000000 {
@@ -317,6 +469,60 @@
                 bus-width = <8>;
         };
 
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_1v5";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        gpio = <&pmic 0 0>;
+                };
+
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_1v2";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&pmic 1 0>;
+                        enable-active-high;
+                };
+
+                regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd_pnl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        enable-active-high;
+                };
+
+                regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        enable-active-high;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-wm8903-ventana",
                              "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 6916310bf58f..c636d002d6d8 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -261,6 +261,286 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
+
+                max8907@3c {
+                        compatible = "maxim,max8907";
+                        reg = <0x3c>;
+                        interrupts = <0 86 0x4>;
+
+                        maxim,system-power-controller;
+
+                        mbatt-supply = <&usb0_vbus_reg>;
+                        in-v1-supply = <&mbatt_reg>;
+                        in-v2-supply = <&mbatt_reg>;
+                        in-v3-supply = <&mbatt_reg>;
+                        in1-supply = <&mbatt_reg>;
+                        in2-supply = <&nvvdd_sv3_reg>;
+                        in3-supply = <&mbatt_reg>;
+                        in4-supply = <&mbatt_reg>;
+                        in5-supply = <&mbatt_reg>;
+                        in6-supply = <&mbatt_reg>;
+                        in7-supply = <&mbatt_reg>;
+                        in8-supply = <&mbatt_reg>;
+                        in9-supply = <&mbatt_reg>;
+                        in10-supply = <&mbatt_reg>;
+                        in11-supply = <&mbatt_reg>;
+                        in12-supply = <&mbatt_reg>;
+                        in13-supply = <&mbatt_reg>;
+                        in14-supply = <&mbatt_reg>;
+                        in15-supply = <&mbatt_reg>;
+                        in16-supply = <&mbatt_reg>;
+                        in17-supply = <&nvvdd_sv3_reg>;
+                        in18-supply = <&nvvdd_sv3_reg>;
+                        in19-supply = <&mbatt_reg>;
+                        in20-supply = <&mbatt_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                mbatt_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "mbatt";
+                                        regulator-name = "vbat_pmu";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sd1";
+                                        regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sd2";
+                                        regulator-name = "nvvdd_sv2,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                nvvdd_sv3_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sd3";
+                                        regulator-name = "nvvdd_sv3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "nvvdd_ldo2,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "nvvdd_ldo3,vcom_1v8b";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "nvvdd_ldo4,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "nvvdd_ldo7,avddio_audio";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "nvvdd_ldo9,avdd_cam*";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo10";
+                                        regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo11";
+                                        regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@15 {
+                                        reg = <15>;
+                                        regulator-compatible = "ldo12";
+                                        regulator-name = "nvvdd_ldo12,vddio_sdio";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@16 {
+                                        reg = <16>;
+                                        regulator-compatible = "ldo13";
+                                        regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                regulator@17 {
+                                        reg = <17>;
+                                        regulator-compatible = "ldo14";
+                                        regulator-name = "nvvdd_ldo14,avdd_vdac";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                regulator@18 {
+                                        reg = <18>;
+                                        regulator-compatible = "ldo15";
+                                        regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@19 {
+                                        reg = <19>;
+                                        regulator-compatible = "ldo16";
+                                        regulator-name = "nvvdd_ldo16,vdd_dbrtr";
+                                        regulator-min-microvolt = <1300000>;
+                                        regulator-max-microvolt = <1300000>;
+                                };
+
+                                regulator@20 {
+                                        reg = <20>;
+                                        regulator-compatible = "ldo17";
+                                        regulator-name = "nvvdd_ldo17,vddio_mipi";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@21 {
+                                        reg = <21>;
+                                        regulator-compatible = "ldo18";
+                                        regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@22 {
+                                        reg = <22>;
+                                        regulator-compatible = "ldo19";
+                                        regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                regulator@23 {
+                                        reg = <23>;
+                                        regulator-compatible = "ldo20";
+                                        regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@24 {
+                                        reg = <24>;
+                                        regulator-compatible = "out5v";
+                                        regulator-name = "usb0_vbus_reg";
+                                };
+
+                                regulator@25 {
+                                        reg = <25>;
+                                        regulator-compatible = "out33v";
+                                        regulator-name = "pmu_out3v3";
+                                };
+
+                                regulator@26 {
+                                        reg = <26>;
+                                        regulator-compatible = "bbat";
+                                        regulator-name = "pmu_bbat";
+                                        regulator-min-microvolt = <2400000>;
+                                        regulator-max-microvolt = <2400000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@27 {
+                                        reg = <27>;
+                                        regulator-compatible = "sdby";
+                                        regulator-name = "vdd_aon";
+                                        regulator-always-on;
+                                };
+
+                                regulator@28 {
+                                        reg = <28>;
+                                        regulator-compatible = "vrtc";
+                                        regulator-name = "vrtc,pmu_vccadc";
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
+        pmc {
+                nvidia,invert-interrupt;
         };
 
         usb@c5000000 {
@@ -284,6 +564,21 @@
                 bus-width = <8>;
         };
 
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                usb0_vbus_reg: regulator {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-wm8753-whistler",
                              "nvidia,tegra-audio-wm8753";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 405d1673904e..67a6cd910b96 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -123,7 +123,7 @@
                 status = "disabled";
         };
 
-        pwm {
+        pwm: pwm {
                 compatible = "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
new file mode 100644
index 000000000000..dd4222f00eca
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -0,0 +1,87 @@
+/dts-v1/;
+
+/include/ "tegra30-cardhu.dtsi"
+
+/* This dts file support the cardhu A02 version of board */
+
+/ {
+        model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
+        compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ddr_reg: regulator@100 {
+                        compatible = "regulator-fixed";
+                        reg = <100>;
+                        regulator-name = "vdd_ddr";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 6 0>;
+                };
+
+                sys_3v3_reg: regulator@101 {
+                        compatible = "regulator-fixed";
+                        reg = <101>;
+                        regulator-name = "sys_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 7 0>;
+                };
+
+                usb1_vbus_reg: regulator@102 {
+                        compatible = "regulator-fixed";
+                        reg = <102>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+
+                usb3_vbus_reg: regulator@103 {
+                        compatible = "regulator-fixed";
+                        reg = <103>;
+                        regulator-name = "usb3_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+
+                vdd_5v0_reg: regulator@104 {
+                        compatible = "regulator-fixed";
+                        reg = <104>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&pmic 2 0>;
+                };
+
+                vdd_bl_reg: regulator@105 {
+                        compatible = "regulator-fixed";
+                        reg = <105>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 83 0>; /* GPIO PK3 */
+                };
+        };
+};
+
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
new file mode 100644
index 000000000000..0828f097ca86
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -0,0 +1,98 @@
+/dts-v1/;
+
+/include/ "tegra30-cardhu.dtsi"
+
+/* This dts file support the cardhu A04 and later versions of board */
+
+/ {
+        model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
+        compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ddr_reg: regulator@100 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "ddr";
+                        reg = <100>;
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 7 0>;
+                };
+
+                sys_3v3_reg: regulator@101 {
+                        compatible = "regulator-fixed";
+                        reg = <101>;
+                        regulator-name = "sys_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 6 0>;
+                };
+
+                usb1_vbus_reg: regulator@102 {
+                        compatible = "regulator-fixed";
+                        reg = <102>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 238 0>; /* GPIO PDD6 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+
+                usb3_vbus_reg: regulator@103 {
+                        compatible = "regulator-fixed";
+                        reg = <103>;
+                        regulator-name = "usb3_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 236 0>; /* GPIO PDD4 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+
+                vdd_5v0_reg: regulator@104 {
+                        compatible = "regulator-fixed";
+                        reg = <104>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&pmic 8 0>;
+                };
+
+                vdd_bl_reg: regulator@105 {
+                        compatible = "regulator-fixed";
+                        reg = <105>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 234 0>; /* GPIO PDD2 */
+                };
+
+                vdd_bl2_reg: regulator@106 {
+                        compatible = "regulator-fixed";
+                        reg = <106>;
+                        regulator-name = "vdd_bl2";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 232 0>; /* GPIO PDD0 */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts
deleted file mode 100644
index c169bced131e..000000000000
--- a/arch/arm/boot/dts/tegra30-cardhu.dts
+++ /dev/null
@@ -1,171 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra30.dtsi"
-
-/ {
-        model = "NVIDIA Tegra30 Cardhu evaluation board";
-        compatible = "nvidia,cardhu", "nvidia,tegra30";
-
-        memory {
-                reg = <0x80000000 0x40000000>;
-        };
-
-        pinmux {
-                pinctrl-names = "default";
-                pinctrl-0 = <&state_default>;
-
-                state_default: pinmux {
-                        sdmmc1_clk_pz0 {
-                                nvidia,pins = "sdmmc1_clk_pz0";
-                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc1_cmd_pz1 {
-                                nvidia,pins =   "sdmmc1_cmd_pz1",
-                                                "sdmmc1_dat0_py7",
-                                                "sdmmc1_dat1_py6",
-                                                "sdmmc1_dat2_py5",
-                                                "sdmmc1_dat3_py4";
-                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc4_clk_pcc4 {
-                                nvidia,pins =   "sdmmc4_clk_pcc4",
-                                                "sdmmc4_rst_n_pcc3";
-                                nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc4_dat0_paa0 {
-                                nvidia,pins =   "sdmmc4_dat0_paa0",
-                                                "sdmmc4_dat1_paa1",
-                                                "sdmmc4_dat2_paa2",
-                                                "sdmmc4_dat3_paa3",
-                                                "sdmmc4_dat4_paa4",
-                                                "sdmmc4_dat5_paa5",
-                                                "sdmmc4_dat6_paa6",
-                                                "sdmmc4_dat7_paa7";
-                                nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                        };
-                        dap2_fs_pa2 {
-                                nvidia,pins =   "dap2_fs_pa2",
-                                                "dap2_sclk_pa3",
-                                                "dap2_din_pa4",
-                                                "dap2_dout_pa5";
-                                nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                };
-        };
-
-        serial@70006000 {
-                status = "okay";
-                clock-frequency = <408000000>;
-        };
-
-        i2c@7000c000 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-
-        i2c@7000c400 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-
-        i2c@7000c500 {
-                status = "okay";
-                clock-frequency = <100000>;
-
-                /* ALS and Proximity sensor */
-                isl29028@44 {
-                        compatible = "isil,isl29028";
-                        reg = <0x44>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <88 0x04>; /*gpio PL0 */
-                };
-        };
-
-        i2c@7000c700 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-
-        i2c@7000d000 {
-                status = "okay";
-                clock-frequency = <100000>;
-
-                wm8903: wm8903@1a {
-                        compatible = "wlf,wm8903";
-                        reg = <0x1a>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <179 0x04>; /* gpio PW3 */
-
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        micdet-cfg = <0>;
-                        micdet-delay = <100>;
-                        gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
-                };
-
-                tps62361 {
-                        compatible = "ti,tps62361";
-                        reg = <0x60>;
-
-                        regulator-name = "tps62361-vout";
-                        regulator-min-microvolt = <500000>;
-                        regulator-max-microvolt = <1500000>;
-                        regulator-boot-on;
-                        regulator-always-on;
-                        ti,vsel0-state-high;
-                        ti,vsel1-state-high;
-                };
-        };
-
-        ahub {
-                i2s@70080400 {
-                        status = "okay";
-                };
-        };
-
-        sdhci@78000000 {
-                status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-                power-gpios = <&gpio 31 0>; /* gpio PD7 */
-                bus-width = <4>;
-        };
-
-        sdhci@78000600 {
-                status = "okay";
-                bus-width = <8>;
-        };
-
-        sound {
-                compatible = "nvidia,tegra-audio-wm8903-cardhu",
-                             "nvidia,tegra-audio-wm8903";
-                nvidia,model = "NVIDIA Tegra Cardhu";
-
-                nvidia,audio-routing =
-                        "Headphone Jack", "HPOUTR",
-                        "Headphone Jack", "HPOUTL",
-                        "Int Spk", "ROP",
-                        "Int Spk", "RON",
-                        "Int Spk", "LOP",
-                        "Int Spk", "LON",
-                        "Mic Jack", "MICBIAS",
-                        "IN1L", "Mic Jack";
-
-                nvidia,i2s-controller = <&tegra_i2s1>;
-                nvidia,audio-codec = <&wm8903>;
-
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-        };
-};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
new file mode 100644
index 000000000000..d10c9c5a3606
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -0,0 +1,475 @@
+/include/ "tegra30.dtsi"
+
+/**
+ * This file contains common DT entry for all fab version of Cardhu.
+ * There is multiple fab version of Cardhu starting from A01 to A07.
+ * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
+ * A02 will have different sets of GPIOs for fixed regulator compare to
+ * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
+ * compatible with fab version A04. Based on Cardhu fab version, the
+ * related dts file need to be chosen like for Cardhu fab version A02,
+ * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
+ * tegra30-cardhu-a04.dts.
+ * The identification of board is done in two ways, by looking the sticker
+ * on PCB and by reading board id eeprom.
+ * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
+ * number is the fab version like here it is 002 and hence fab version A02.
+ * The (downstream internal) U-Boot of Cardhu display the board-id as
+ * follows:
+ * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
+ * In this Fab version is 02 i.e. A02.
+ * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
+ * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
+ * wide.
+ */
+
+/ {
+        model = "NVIDIA Tegra30 Cardhu evaluation board";
+        compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins =   "sdmmc1_cmd_pz1",
+                                                "sdmmc1_dat0_py7",
+                                                "sdmmc1_dat1_py6",
+                                                "sdmmc1_dat2_py5",
+                                                "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins =   "dap2_fs_pa2",
+                                                "dap2_sclk_pa3",
+                                                "dap2_din_pa4",
+                                                "dap2_dout_pa5";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+
+        serial@70006000 {
+                status = "okay";
+                clock-frequency = <408000000>;
+        };
+
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c500 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                /* ALS and Proximity sensor */
+                isl29028@44 {
+                        compatible = "isil,isl29028";
+                        reg = <0x44>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <88 0x04>; /*gpio PL0 */
+                };
+        };
+
+        i2c@7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <179 0x04>; /* gpio PW3 */
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+                };
+
+                tps62361 {
+                        compatible = "ti,tps62361";
+                        reg = <0x60>;
+
+                        regulator-name = "tps62361-vout";
+                        regulator-min-microvolt = <500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        ti,vsel0-state-high;
+                        ti,vsel1-state-high;
+                };
+
+                pmic: tps65911@2d {
+                        compatible = "ti,tps65911";
+                        reg = <0x2d>;
+
+                        interrupts = <0 86 0x4>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        vcc1-supply = <&vdd_ac_bat_reg>;
+                        vcc2-supply = <&vdd_ac_bat_reg>;
+                        vcc3-supply = <&vio_reg>;
+                        vcc4-supply = <&vdd_5v0_reg>;
+                        vcc5-supply = <&vdd_ac_bat_reg>;
+                        vcc6-supply = <&vdd2_reg>;
+                        vcc7-supply = <&vdd_ac_bat_reg>;
+                        vccio-supply = <&vdd_ac_bat_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                vdd1_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "vdd1";
+                                        regulator-name = "vddio_ddr_1v2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                vdd2_reg: regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "vdd2";
+                                        regulator-name = "vdd_1v5_gen";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                };
+
+                                vddctrl_reg: regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "vddctrl";
+                                        regulator-name = "vdd_cpu,vdd_sys";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                vio_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "vio";
+                                        regulator-name = "vdd_1v8_gen";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo1_reg: regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_pexa,vdd_pexb";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                ldo2_reg: regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_sata,avdd_plle";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                /* LDO3 is not connected to anything */
+
+                                ldo4_reg: regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo5_reg: regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vddio_sdmmc,avdd_vdac";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo6_reg: regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                ldo7_reg: regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_pllm,x,u,a_p_c_s";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo8_reg: regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ddr_hs";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
+        ahub {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+
+        pmc {
+                status = "okay";
+                nvidia,invert-interrupt;
+        };
+
+        sdhci@78000000 {
+                status = "okay";
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                bus-width = <4>;
+        };
+
+        sdhci@78000600 {
+                status = "okay";
+                bus-width = <8>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_ac_bat_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_ac_bat";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                cam_1v8_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "cam_1v8";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        enable-active-high;
+                        gpio = <&gpio 220 0>; /* gpio PBB4 */
+                        vin-supply = <&vio_reg>;
+                };
+
+                cp_5v_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "cp_5v";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        enable-active-high;
+                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                };
+
+                emmc_3v3_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "emmc_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 25 0>; /* gpio PD1 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                modem_3v3_reg: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "modem_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                };
+
+                pex_hvdd_3v3_reg: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "pex_hvdd_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_cam1_ldo_reg: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "vdd_cam1_ldo";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        enable-active-high;
+                        gpio = <&gpio 142 0>; /* gpio PR6 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_cam2_ldo_reg: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "vdd_cam2_ldo";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        enable-active-high;
+                        gpio = <&gpio 143 0>; /* gpio PR7 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_cam3_ldo_reg: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "vdd_cam3_ldo";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 144 0>; /* gpio PS0 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_com_reg: regulator@9 {
+                        compatible = "regulator-fixed";
+                        reg = <9>;
+                        regulator-name = "vdd_com";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 24 0>; /* gpio PD0 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_fuse_3v3_reg: regulator@10 {
+                        compatible = "regulator-fixed";
+                        reg = <10>;
+                        regulator-name = "vdd_fuse_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 94 0>; /* gpio PL6 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_pnl1_reg: regulator@11 {
+                        compatible = "regulator-fixed";
+                        reg = <11>;
+                        regulator-name = "vdd_pnl1";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 92 0>; /* gpio PL4 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_vid_reg: regulator@12 {
+                        compatible = "regulator-fixed";
+                        reg = <12>;
+                        regulator-name = "vddio_vid";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 152 0>; /* GPIO PT0 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-cardhu",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Cardhu";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 3e4334d14efb..b1497c7d7d68 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -117,7 +117,7 @@
                 status = "disabled";
         };
 
-        pwm {
+        pwm: pwm {
                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
new file mode 100644
index 000000000000..a63272422d76
--- /dev/null
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+
+&tps {
+        compatible = "ti,tps65217";
+
+        regulators {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                dcdc1_reg: regulator@0 {
+                        reg = <0>;
+                        regulator-compatible = "dcdc1";
+                };
+
+                dcdc2_reg: regulator@1 {
+                        reg = <1>;
+                        regulator-compatible = "dcdc2";
+                };
+
+                dcdc3_reg: regulator@2 {
+                        reg = <2>;
+                        regulator-compatible = "dcdc3";
+                };
+
+                ldo1_reg: regulator@3 {
+                        reg = <3>;
+                        regulator-compatible = "ldo1";
+                };
+
+                ldo2_reg: regulator@4 {
+                        reg = <4>;
+                        regulator-compatible = "ldo2";
+                };
+
+                ldo3_reg: regulator@5 {
+                        reg = <5>;
+                        regulator-compatible = "ldo3";
+                };
+
+                ldo4_reg: regulator@6 {
+                        reg = <6>;
+                        regulator-compatible = "ldo4";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
new file mode 100644
index 000000000000..92693a89160e
--- /dev/null
+++ b/arch/arm/boot/dts/tps65910.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65910.pdf
+ */
+
+&tps {
+        compatible = "ti,tps65910";
+
+        regulators {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vrtc_reg: regulator@0 {
+                        reg = <0>;
+                        regulator-compatible = "vrtc";
+                };
+
+                vio_reg: regulator@1 {
+                        reg = <1>;
+                        regulator-compatible = "vio";
+                };
+
+                vdd1_reg: regulator@2 {
+                        reg = <2>;
+                        regulator-compatible = "vdd1";
+                };
+
+                vdd2_reg: regulator@3 {
+                        reg = <3>;
+                        regulator-compatible = "vdd2";
+                };
+
+                vdd3_reg: regulator@4 {
+                        reg = <4>;
+                        regulator-compatible = "vdd3";
+                };
+
+                vdig1_reg: regulator@5 {
+                        reg = <5>;
+                        regulator-compatible = "vdig1";
+                };
+
+                vdig2_reg: regulator@6 {
+                        reg = <6>;
+                        regulator-compatible = "vdig2";
+                };
+
+                vpll_reg: regulator@7 {
+                        reg = <7>;
+                        regulator-compatible = "vpll";
+                };
+
+                vdac_reg: regulator@8 {
+                        reg = <8>;
+                        regulator-compatible = "vdac";
+                };
+
+                vaux1_reg: regulator@9 {
+                        reg = <9>;
+                        regulator-compatible = "vaux1";
+                };
+
+                vaux2_reg: regulator@10 {
+                        reg = <10>;
+                        regulator-compatible = "vaux2";
+                };
+
+                vaux33_reg: regulator@11 {
+                        reg = <11>;
+                        regulator-compatible = "vaux33";
+                };
+
+                vmmc_reg: regulator@12 {
+                        reg = <12>;
+                        regulator-compatible = "vmmc";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 22f4d1394ed3..ff000172c93c 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -19,19 +19,19 @@
                 interrupts = <11>;
         };
 
-        vdac: regulator@0 {
+        vdac: regulator-vdac {
                 compatible = "ti,twl4030-vdac";
                 regulator-min-microvolt = <1800000>;
                 regulator-max-microvolt = <1800000>;
         };
 
-        vpll2: regulator@1 {
+        vpll2: regulator-vpll2 {
                 compatible = "ti,twl4030-vpll2";
                 regulator-min-microvolt = <1800000>;
                 regulator-max-microvolt = <1800000>;
         };
 
-        vmmc1: regulator@2 {
+        vmmc1: regulator-vmmc1 {
                 compatible = "ti,twl4030-vmmc1";
                 regulator-min-microvolt = <1850000>;
                 regulator-max-microvolt = <3150000>;
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index d351b27d7213..123e2c40218a 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -20,70 +20,70 @@
                 interrupts = <11>;
         };
 
-        vaux1: regulator@0 {
+        vaux1: regulator-vaux1 {
                 compatible = "ti,twl6030-vaux1";
                 regulator-min-microvolt = <1000000>;
                 regulator-max-microvolt = <3000000>;
         };
 
-        vaux2: regulator@1 {
+        vaux2: regulator-vaux2 {
                 compatible = "ti,twl6030-vaux2";
                 regulator-min-microvolt = <1200000>;
                 regulator-max-microvolt = <2800000>;
         };
 
-        vaux3: regulator@2 {
+        vaux3: regulator-vaux3 {
                 compatible = "ti,twl6030-vaux3";
                 regulator-min-microvolt = <1000000>;
                 regulator-max-microvolt = <3000000>;
         };
 
-        vmmc: regulator@3 {
+        vmmc: regulator-vmmc {
                 compatible = "ti,twl6030-vmmc";
                 regulator-min-microvolt = <1200000>;
                 regulator-max-microvolt = <3000000>;
         };
 
-        vpp: regulator@4 {
+        vpp: regulator-vpp {
                 compatible = "ti,twl6030-vpp";
                 regulator-min-microvolt = <1800000>;
                 regulator-max-microvolt = <2500000>;
         };
 
-        vusim: regulator@5 {
+        vusim: regulator-vusim {
                 compatible = "ti,twl6030-vusim";
                 regulator-min-microvolt = <1200000>;
                 regulator-max-microvolt = <2900000>;
         };
 
-        vdac: regulator@6 {
+        vdac: regulator-vdac {
                 compatible = "ti,twl6030-vdac";
         };
 
-        vana: regulator@7 {
+        vana: regulator-vana {
                 compatible = "ti,twl6030-vana";
         };
 
-        vcxio: regulator@8 {
+        vcxio: regulator-vcxio {
                 compatible = "ti,twl6030-vcxio";
                 regulator-always-on;
         };
 
-        vusb: regulator@9 {
+        vusb: regulator-vusb {
                 compatible = "ti,twl6030-vusb";
         };
 
-        v1v8: regulator@10 {
+        v1v8: regulator-v1v8 {
                 compatible = "ti,twl6030-v1v8";
                 regulator-always-on;
         };
 
-        v2v1: regulator@11 {
+        v2v1: regulator-v2v1 {
                 compatible = "ti,twl6030-v2v1";
                 regulator-always-on;
         };
 
-        clk32kg: regulator@12 {
+        clk32kg: regulator-clk32kg {
                 compatible = "ti,twl6030-clk32kg";
         };
 };
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
new file mode 100644
index 000000000000..7aea70253c63
--- /dev/null
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -0,0 +1,95 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_NAMESPACES=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_BLOCK is not set
+CONFIG_ARCH_BCM2835=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_COMPACTION=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_CLEANCACHE=y
+CONFIG_SECCOMP=y
+CONFIG_CC_STACKPROTECTOR=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_TTY_PRINTK=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_PROC_FS is not set
+# CONFIG_SYSFS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_SCHED_TRACER=y
+CONFIG_STACK_TRACER=y
+CONFIG_FUNCTION_PROFILER=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_KGDB=y
+CONFIG_KGDB_KDB=y
+CONFIG_TEST_KSTRTOX=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 3c9f32f9b6b4..565132d02105 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
-CONFIG_MACH_MX51_EFIKAMX=y
-CONFIG_MACH_MX51_EFIKASB=y
-CONFIG_MACH_IMX53_DT=y
+CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_MXC_PWM=y
 CONFIG_SMP=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index aeb3af541fed..74eee0c78f28 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,5 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=19
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
@@ -15,9 +17,19 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
-CONFIG_MACH_DOCKSTAR=y
+CONFIG_MACH_DREAMPLUG_DT=y
+CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_DLINK_KIRKWOOD_DT=y
+CONFIG_MACH_IB62X0_DT=y
+CONFIG_MACH_TS219_DT=y
+CONFIG_MACH_DOCKSTAR_DT=y
+CONFIG_MACH_GOFLEXNET_DT=y
+CONFIG_MACH_LSXL_DT=y
+CONFIG_MACH_IOMEGA_IX2_200_DT=y
+CONFIG_MACH_KM_KIRKWOOD_DT=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
+CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
 CONFIG_MACH_OPENRD_ULTIMATE=y
@@ -29,8 +41,6 @@ CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
@@ -47,13 +57,11 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
 CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -69,7 +77,6 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
@@ -78,22 +85,21 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-CONFIG_NET_PCI=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_MV643XX_ETH=y
-# CONFIG_NETDEV_10000 is not set
+CONFIG_MARVELL_PHY=y
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_SDIO=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
@@ -103,7 +109,8 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
 CONFIG_HID_DRAGONRISE=y
 CONFIG_HID_GYRATION=y
 CONFIG_HID_TWINHAN=y
@@ -119,10 +126,8 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_PRINTER=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DATAFAB=y
@@ -148,7 +153,6 @@ CONFIG_MV_XOR=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -158,7 +162,6 @@ CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -171,11 +174,8 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_CRYPTO_CBC=m
 CONFIG_CRYPTO_PCBC=m
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 26146ffea1a5..8c49df66cac3 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -8,6 +8,7 @@ CONFIG_LOG_BUF_SHIFT=16
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 2388c8610627..5d0c66708960 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -14,6 +14,7 @@ CONFIG_NAMESPACES=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2e86b31c33cf..7bcf850eddcd 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 4edcfb4e4dee..36d60dda310c 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -23,12 +23,6 @@ CONFIG_BLK_DEV_INTEGRITY=y
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_MXS=y
 CONFIG_MACH_MXS_DT=y
-CONFIG_MACH_MX23EVK=y
-CONFIG_MACH_MX28EVK=y
-CONFIG_MACH_STMP378X_DEVB=y
-CONFIG_MACH_TX28=y
-CONFIG_MACH_M28EVK=y
-CONFIG_MACH_APX4DEVKIT=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index e58edc36b406..62303043db9c 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -123,6 +123,7 @@ CONFIG_HW_RANDOM=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_SPI=y
 CONFIG_SPI_OMAP24XX=y
+CONFIG_PINCTRL_SINGLE=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_TWL4030=y
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
deleted file mode 100644
index 35a31ccacc32..000000000000
--- a/arch/arm/configs/pnx4008_defconfig
+++ /dev/null
@@ -1,472 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_AUDIT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_ARCH_PNX4008=y
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-CONFIG_IP_VS=m
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_DECNET_NF_GRABULATOR=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_IP_SCTP=m
-CONFIG_ATM=y
-CONFIG_ATM_CLIP=y
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_DECNET=m
-CONFIG_LLC2=m
-CONFIG_IPX=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
-CONFIG_WAN_ROUTER=m
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_PKTGEN=m
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTD_DOC2000=m
-CONFIG_MTD_DOC2001=m
-CONFIG_MTD_DOC2001PLUS=m
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_DEBUG=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_DLCI=m
-CONFIG_WAN_ROUTER_DRIVERS=m
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_ATM_TCP=m
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_PPPOATM=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=y
-CONFIG_JOYSTICK_IFORCE_232=y
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_RAW=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_USBPCWATCHDOG=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SOUND_PRIME=m
-CONFIG_USB_HID=m
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_TEST=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_TMPFS=y
-CONFIG_ADFS_FS=m
-CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_CRAMFS=y
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_ROMFS_FS=m
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V4=y
-CONFIG_RPCSEC_GSS_SPKM3=m
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_NCP_FS=m
-CONFIG_NCPFS_PACKET_SIGNING=y
-CONFIG_NCPFS_IOCTL_LOCKING=y
-CONFIG_NCPFS_STRONG=y
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-CONFIG_NCPFS_NLS=y
-CONFIG_NCPFS_EXTRAS=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC16=m
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index c328ac65479a..807d4e2acb17 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -1,4 +1,6 @@
 CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
@@ -8,9 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_ARCH_PRIMA2=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_SIRF=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_KEXEC=y
@@ -36,7 +36,6 @@ CONFIG_SPI=y
 CONFIG_SPI_SIRF=y
 CONFIG_SPI_SPIDEV=y
 # CONFIG_HWMON is not set
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB_GADGET=y
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_MASS_STORAGE=m
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index db2245353f0f..0d6bb738c6de 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -145,6 +145,8 @@ CONFIG_MMC_SDHCI_TEGRA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_TEGRA=y
+CONFIG_DMADEVICES=y
+CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index c402e9b31f4c..477e0206e016 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -6,7 +6,9 @@
 #endif
 
 /* not all ARM platforms necessarily support this API ... */
+#ifdef CONFIG_NEED_MACH_GPIO_H
 #include <mach/gpio.h>
+#endif
 
 #ifndef __ARM_GPIOLIB_COMPLEX
 /* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
index 538f17ca905b..295e2e40151b 100644
--- a/arch/arm/include/asm/hardware/cache-tauros2.h
+++ b/arch/arm/include/asm/hardware/cache-tauros2.h
@@ -8,4 +8,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-extern void __init tauros2_init(void);
+#define CACHE_TAUROS2_PREFETCH_ON       (1 << 0)
+#define CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)
+
+extern void __init tauros2_init(unsigned int features);
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 2ff2c75a4639..02fe2fbe2477 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -217,18 +217,8 @@ extern int iop3xx_get_init_atu(void);
 #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
 #define IOP3XX_PCI_MEM_WINDOW_SIZE      0x08000000
 
-#define IOP3XX_PCI_IO_WINDOW_SIZE       0x00010000
 #define IOP3XX_PCI_LOWER_IO_PA          0x90000000
-#define IOP3XX_PCI_LOWER_IO_VA          0xfe000000
-#define IOP3XX_PCI_LOWER_IO_BA          0x90000000
-#define IOP3XX_PCI_UPPER_IO_PA          (IOP3XX_PCI_LOWER_IO_PA +\
-                                        IOP3XX_PCI_IO_WINDOW_SIZE - 1)
-#define IOP3XX_PCI_UPPER_IO_VA          (IOP3XX_PCI_LOWER_IO_VA +\
-                                        IOP3XX_PCI_IO_WINDOW_SIZE - 1)
-#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\
-                                        IOP3XX_PCI_LOWER_IO_PA) +\
-                                        IOP3XX_PCI_LOWER_IO_VA)
-
+#define IOP3XX_PCI_LOWER_IO_BA          0x00000000
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 815c669fec0a..8f4db67533e5 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -113,11 +113,19 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 #define __iowmb()               do { } while (0)
 #endif
 
+/* PCI fixed i/o mapping */
+#define PCI_IO_VIRT_BASE        0xfee00000
+
+extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
+
 /*
  * Now, pick up the machine-defined IO definitions
  */
 #ifdef CONFIG_NEED_MACH_IO_H
 #include <mach/io.h>
+#elif defined(CONFIG_PCI)
+#define IO_SPACE_LIMIT  ((resource_size_t)0xfffff)
+#define __io(a)         __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
 #else
 #define __io(a)         __typesafe_io((a) & IO_SPACE_LIMIT)
 #endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 0b1c94b8c652..917d4fcfd9b4 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -14,6 +14,12 @@ struct tag;
 struct meminfo;
 struct sys_timer;
 struct pt_regs;
+struct smp_operations;
+#ifdef CONFIG_SMP
+#define smp_ops(ops) (&(ops))
+#else
+#define smp_ops(ops) (struct smp_operations *)NULL
+#endif
 
 struct machine_desc {
         unsigned int            nr;             /* architecture number  */
@@ -35,6 +41,7 @@ struct machine_desc {
         unsigned char           reserve_lp1 :1; /* never has lp1        */
         unsigned char           reserve_lp2 :1; /* never has lp2        */
         char                    restart_mode;   /* default restart mode */
+        struct smp_operations   *smp;           /* SMP operations       */
         void                    (*fixup)(struct tag *, char **,
                                          struct meminfo *);
         void                    (*reserve)(void);/* reserve mem blocks  */
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index a6efcdd6fd25..195ac2f9d3d3 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -9,6 +9,9 @@
  *
  *  Page table mapping constructs and function prototypes
  */
+#ifndef __ASM_MACH_MAP_H
+#define __ASM_MACH_MAP_H
+
 #include <asm/io.h>
 
 struct map_desc {
@@ -34,6 +37,8 @@ struct map_desc {
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
+extern void vm_reserve_area_early(unsigned long addr, unsigned long size,
+                                  void *caller);
 
 struct mem_type;
 extern const struct mem_type *get_mem_type(unsigned int type);
@@ -44,4 +49,7 @@ extern int ioremap_page(unsigned long virt, unsigned long phys,
                         const struct mem_type *mtype);
 #else
 #define iotable_init(map,num)   do { } while (0)
+#define vm_reserve_area_early(a,s,c)    do { } while (0)
+#endif
+
 #endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 26c511fddf8f..db9fedb57f2c 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_MACH_PCI_H
 #define __ASM_MACH_PCI_H
 
+#include <linux/ioport.h>
+
 struct pci_sys_data;
 struct pci_ops;
 struct pci_bus;
@@ -42,6 +44,8 @@ struct pci_sys_data {
         unsigned long   io_offset;      /* bus->cpu IO mapping offset           */
         struct pci_bus  *bus;           /* PCI bus                              */
         struct list_head resources;     /* root bus resources (apertures)       */
+        struct resource io_res;
+        char            io_res_name[12];
                                         /* Bridge swizzling                     */
         u8              (*swizzle)(struct pci_dev *, u8 *);
                                         /* IRQ mapping                          */
@@ -55,6 +59,15 @@ struct pci_sys_data {
 void pci_common_init(struct hw_pci *);
 
 /*
+ * Setup early fixed I/O mapping.
+ */
+#if defined(CONFIG_PCI)
+extern void pci_map_io_early(unsigned long pfn);
+#else
+static inline void pci_map_io_early(unsigned long pfn) {}
+#endif
+
+/*
  * PCI controllers
  */
 extern struct pci_ops iop3xx_ops;
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index e074948d8143..625cd621a436 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,6 +12,13 @@
 #ifndef __ARM_PERF_EVENT_H__
 #define __ARM_PERF_EVENT_H__
 
-/* Nothing to see here... */
+/*
+ * The ARMv7 CPU PMU supports up to 32 event counters.
+ */
+#define ARMPMU_MAX_HWEVENTS             32
+
+#define HW_OP_UNSUPPORTED               0xFFFF
+#define C(_x)                           PERF_COUNT_HW_CACHE_##_x
+#define CACHE_OP_UNSUPPORTED            0xFFFF
 
 #endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 4432305f4a2a..a26170dce02e 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -16,69 +16,30 @@
 #include <linux/perf_event.h>
 
 /*
- * Types of PMUs that can be accessed directly and require mutual
- * exclusion between profiling tools.
- */
-enum arm_pmu_type {
-        ARM_PMU_DEVICE_CPU      = 0,
-        ARM_NUM_PMU_DEVICES,
-};
-
-/*
  * struct arm_pmu_platdata - ARM PMU platform data
  *
  * @handle_irq: an optional handler which will be called from the
  *      interrupt and passed the address of the low level handler,
  *      and can be used to implement any platform specific handling
  *      before or after calling it.
- * @enable_irq: an optional handler which will be called after
- *      request_irq and be used to handle some platform specific
- *      irq enablement
- * @disable_irq: an optional handler which will be called before
- *      free_irq and be used to handle some platform specific
- *      irq disablement
+ * @runtime_resume: an optional handler which will be called by the
+ *      runtime PM framework following a call to pm_runtime_get().
+ *      Note that if pm_runtime_get() is called more than once in
+ *      succession this handler will only be called once.
+ * @runtime_suspend: an optional handler which will be called by the
+ *      runtime PM framework following a call to pm_runtime_put().
+ *      Note that if pm_runtime_get() is called more than once in
+ *      succession this handler will only be called following the
+ *      final call to pm_runtime_put() that actually disables the
+ *      hardware.
  */
 struct arm_pmu_platdata {
         irqreturn_t (*handle_irq)(int irq, void *dev,
                                   irq_handler_t pmu_handler);
-        void (*enable_irq)(int irq);
-        void (*disable_irq)(int irq);
+        int (*runtime_resume)(struct device *dev);
+        int (*runtime_suspend)(struct device *dev);
 };
 
-#ifdef CONFIG_CPU_HAS_PMU
-
-/**
- * reserve_pmu() - reserve the hardware performance counters
- *
- * Reserve the hardware performance counters in the system for exclusive use.
- * Returns 0 on success or -EBUSY if the lock is already held.
- */
-extern int
-reserve_pmu(enum arm_pmu_type type);
-
-/**
- * release_pmu() - Relinquish control of the performance counters
- *
- * Release the performance counters and allow someone else to use them.
- */
-extern void
-release_pmu(enum arm_pmu_type type);
-
-#else /* CONFIG_CPU_HAS_PMU */
-
-#include <linux/err.h>
-
-static inline int
-reserve_pmu(enum arm_pmu_type type)
-{
-        return -ENODEV;
-}
-
-static inline void
-release_pmu(enum arm_pmu_type type)     { }
-
-#endif /* CONFIG_CPU_HAS_PMU */
-
 #ifdef CONFIG_HW_PERF_EVENTS
 
 /* The events for a given PMU register set. */
@@ -103,7 +64,6 @@ struct pmu_hw_events {
 
 struct arm_pmu {
         struct pmu      pmu;
-        enum arm_pmu_type type;
         cpumask_t       active_irqs;
         char            *name;
         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
@@ -118,6 +78,8 @@ struct arm_pmu {
         void            (*start)(void);
         void            (*stop)(void);
         void            (*reset)(void *);
+        int             (*request_irq)(irq_handler_t handler);
+        void            (*free_irq)(void);
         int             (*map_event)(struct perf_event *event);
         int             num_events;
         atomic_t        active_events;
@@ -129,7 +91,9 @@ struct arm_pmu {
 
 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+extern const struct dev_pm_ops armpmu_dev_pm_ops;
+
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type);
 
 u64 armpmu_event_update(struct perf_event *event,
                         struct hw_perf_event *hwc,
@@ -139,6 +103,13 @@ int armpmu_event_set_period(struct perf_event *event,
                             struct hw_perf_event *hwc,
                             int idx);
 
+int armpmu_map_event(struct perf_event *event,
+                     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+                     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
+                                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                                [PERF_COUNT_HW_CACHE_RESULT_MAX],
+                     u32 raw_event_mask);
+
 #endif /* CONFIG_HW_PERF_EVENTS */
 
 #endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index ae29293270a3..2e3be16c6766 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -60,15 +60,6 @@ extern int boot_secondary(unsigned int cpu, struct task_struct *);
  */
 asmlinkage void secondary_start_kernel(void);
 
-/*
- * Perform platform specific initialisation of the specified CPU.
- */
-extern void platform_secondary_init(unsigned int cpu);
-
-/*
- * Initialize cpu_possible map, and enable coherency
- */
-extern void platform_smp_prepare_cpus(unsigned int);
 
 /*
  * Initial data for bringing up a secondary CPU.
@@ -79,18 +70,47 @@ struct secondary_data {
         void *stack;
 };
 extern struct secondary_data secondary_data;
+extern volatile int pen_release;
 
 extern int __cpu_disable(void);
-extern int platform_cpu_disable(unsigned int cpu);
 
 extern void __cpu_die(unsigned int cpu);
 extern void cpu_die(void);
 
-extern void platform_cpu_die(unsigned int cpu);
-extern int platform_cpu_kill(unsigned int cpu);
-extern void platform_cpu_enable(unsigned int cpu);
-
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
+struct smp_operations {
+#ifdef CONFIG_SMP
+        /*
+         * Setup the set of possible CPUs (via set_cpu_possible)
+         */
+        void (*smp_init_cpus)(void);
+        /*
+         * Initialize cpu_possible map, and enable coherency
+         */
+        void (*smp_prepare_cpus)(unsigned int max_cpus);
+
+        /*
+         * Perform platform specific initialisation of the specified CPU.
+         */
+        void (*smp_secondary_init)(unsigned int cpu);
+        /*
+         * Boot a secondary CPU, and assign it the specified idle task.
+         * This also gives us the initial stack to use for this CPU.
+         */
+        int  (*smp_boot_secondary)(unsigned int cpu, struct task_struct *idle);
+#ifdef CONFIG_HOTPLUG_CPU
+        int  (*cpu_kill)(unsigned int cpu);
+        void (*cpu_die)(unsigned int cpu);
+        int  (*cpu_disable)(unsigned int cpu);
+#endif
+#endif
+};
+
+/*
+ * set platform specific SMP operations
+ */
+extern void smp_set_ops(struct smp_operations *);
+
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index ce119442277c..963342acebb7 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -13,7 +13,11 @@
 #define _ASMARM_TIMEX_H
 
 #include <asm/arch_timer.h>
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+#define CLOCK_TICK_RATE 1000000
+#else
 #include <mach/timex.h>
+#endif
 
 typedef unsigned long cycles_t;
 
diff --git a/arch/arm/mach-highbank/include/mach/debug-macro.S b/arch/arm/include/debug/highbank.S
index cb57fe5bcd04..8cad4322a5a2 100644
--- a/arch/arm/mach-highbank/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/highbank.S
@@ -10,10 +10,8 @@
  */
 
                 .macro  addruart,rp,rv,tmp
-                movw    \rv, #0x6000
-                movt    \rv, #0xfee3
-                movw    \rp, #0x6000
-                movt    \rp, #0xfff3
+                ldr     \rv, =0xfee36000
+                ldr     \rp, =0xfff36000
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/debug/icedcc.S b/arch/arm/include/debug/icedcc.S
new file mode 100644
index 000000000000..43afcb021fa3
--- /dev/null
+++ b/arch/arm/include/debug/icedcc.S
@@ -0,0 +1,90 @@
+/*
+ *  arch/arm/include/debug/icedcc.S
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+                @@ debug using ARM EmbeddedICE DCC channel
+
+                .macro  addruart, rp, rv, tmp
+                .endm
+
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
+
+                .macro  senduart, rd, rx
+                mcr     p14, 0, \rd, c0, c5, 0
+                .endm
+
+                .macro  busyuart, rd, rx
+1001:
+                mrc     p14, 0, \rx, c0, c1, 0
+                tst     \rx, #0x20000000
+                beq     1001b
+                .endm
+
+                .macro  waituart, rd, rx
+                mov     \rd, #0x2000000
+1001:
+                subs    \rd, \rd, #1
+                bmi     1002f
+                mrc     p14, 0, \rx, c0, c1, 0
+                tst     \rx, #0x20000000
+                bne     1001b
+1002:
+                .endm
+
+#elif defined(CONFIG_CPU_XSCALE)
+
+                .macro  senduart, rd, rx
+                mcr     p14, 0, \rd, c8, c0, 0
+                .endm
+
+                .macro  busyuart, rd, rx
+1001:
+                mrc     p14, 0, \rx, c14, c0, 0
+                tst     \rx, #0x10000000
+                beq     1001b
+                .endm
+
+                .macro  waituart, rd, rx
+                mov     \rd, #0x10000000
+1001:
+                subs    \rd, \rd, #1
+                bmi     1002f
+                mrc     p14, 0, \rx, c14, c0, 0
+                tst     \rx, #0x10000000
+                bne     1001b
+1002:
+                .endm
+
+#else
+
+                .macro  senduart, rd, rx
+                mcr     p14, 0, \rd, c1, c0, 0
+                .endm
+
+                .macro  busyuart, rd, rx
+1001:
+                mrc     p14, 0, \rx, c0, c0, 0
+                tst     \rx, #2
+                beq     1001b
+
+                .endm
+
+                .macro  waituart, rd, rx
+                mov     \rd, #0x2000000
+1001:
+                subs    \rd, \rd, #1
+                bmi     1002f
+                mrc     p14, 0, \rx, c0, c0, 0
+                tst     \rx, #2
+                bne     1001b
+1002:
+                .endm
+
+#endif  /* CONFIG_CPU_V6 */
diff --git a/arch/arm/mach-mvebu/include/mach/debug-macro.S b/arch/arm/include/debug/mvebu.S
index 22825760c7e1..865c6d02b332 100644
--- a/arch/arm/mach-mvebu/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -11,7 +11,8 @@
  * published by the Free Software Foundation.
 */
 
-#include <mach/armada-370-xp.h>
+#define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
+#define ARMADA_370_XP_REGS_VIRT_BASE    0xfeb00000
 
         .macro  addruart, rp, rv, tmp
         ldr     \rp, =ARMADA_370_XP_REGS_PHYS_BASE
diff --git a/arch/arm/mach-picoxcell/include/mach/debug-macro.S b/arch/arm/include/debug/picoxcell.S
index 58d4ee3ae949..7419deb1b948 100644
--- a/arch/arm/mach-picoxcell/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/picoxcell.S
@@ -9,10 +9,10 @@
  * accesses to the 8250.
  */
 #include <linux/serial_reg.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
 
 #define UART_SHIFT 2
+#define PICOXCELL_UART1_BASE            0x80230000
+#define PHYS_TO_IO(x)                   (((x) & 0x00ffffff) | 0xfe000000)
 
                 .macro  addruart, rp, rv, tmp
                 ldr     \rv, =PHYS_TO_IO(PICOXCELL_UART1_BASE)
diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/include/debug/socfpga.S
index d6f26d23374f..d6f26d23374f 100644
--- a/arch/arm/mach-socfpga/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/socfpga.S
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/include/debug/vexpress.S
index 9f509f55d078..9f509f55d078 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/vexpress.S
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5cf7008..1c4321430737 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -69,8 +69,7 @@ obj-$(CONFIG_CPU_XSC3)		+= xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)        += xscale-cp0.o
 obj-$(CONFIG_CPU_PJ4)           += pj4-cp0.o
 obj-$(CONFIG_IWMMXT)            += iwmmxt.o
-obj-$(CONFIG_CPU_HAS_PMU)       += pmu.o
-obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o
+obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o perf_event_cpu.o
 AFLAGS_iwmmxt.o                 := -Wa,-mcpu=iwmmxt
 obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
 
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 2b2f25e7fef5..b244696de1a3 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 
 #include <asm/mach-types.h>
+#include <asm/mach/map.h>
 #include <asm/mach/pci.h>
 
 static int debug_pci;
@@ -423,6 +424,38 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
         return irq;
 }
 
+static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
+{
+        int ret;
+        struct pci_host_bridge_window *window;
+
+        if (list_empty(&sys->resources)) {
+                pci_add_resource_offset(&sys->resources,
+                         &iomem_resource, sys->mem_offset);
+        }
+
+        list_for_each_entry(window, &sys->resources, list) {
+                if (resource_type(window->res) == IORESOURCE_IO)
+                        return 0;
+        }
+
+        sys->io_res.start = (busnr * SZ_64K) ?  : pcibios_min_io;
+        sys->io_res.end = (busnr + 1) * SZ_64K - 1;
+        sys->io_res.flags = IORESOURCE_IO;
+        sys->io_res.name = sys->io_res_name;
+        sprintf(sys->io_res_name, "PCI%d I/O", busnr);
+
+        ret = request_resource(&ioport_resource, &sys->io_res);
+        if (ret) {
+                pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
+                return ret;
+        }
+        pci_add_resource_offset(&sys->resources, &sys->io_res,
+                                sys->io_offset);
+
+        return 0;
+}
+
 static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
 {
         struct pci_sys_data *sys = NULL;
@@ -445,11 +478,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                 ret = hw->setup(nr, sys);
 
                 if (ret > 0) {
-                        if (list_empty(&sys->resources)) {
-                                pci_add_resource_offset(&sys->resources,
-                                         &ioport_resource, sys->io_offset);
-                                pci_add_resource_offset(&sys->resources,
-                                         &iomem_resource, sys->mem_offset);
+                        ret = pcibios_init_resources(nr, sys);
+                        if (ret)  {
+                                kfree(sys);
+                                break;
                         }
 
                         if (hw->scan)
@@ -627,3 +659,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 
         return 0;
 }
+
+void __init pci_map_io_early(unsigned long pfn)
+{
+        struct map_desc pci_io_desc = {
+                .virtual        = PCI_IO_VIRT_BASE,
+                .type           = MT_DEVICE,
+                .length         = SZ_64K,
+        };
+
+        pci_io_desc.pfn = pfn;
+        iotable_init(&pci_io_desc, 1);
+}
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index c45522c36787..66f711b2e0e8 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -20,90 +20,9 @@
  * references to these in a production kernel!
  */
 
-#if defined(CONFIG_DEBUG_ICEDCC)
-                @@ debug using ARM EmbeddedICE DCC channel
-
-                .macro  addruart, rp, rv, tmp
-                .endm
-
-#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
-
-                .macro  senduart, rd, rx
-                mcr     p14, 0, \rd, c0, c5, 0
-                .endm
-
-                .macro  busyuart, rd, rx
-1001:
-                mrc     p14, 0, \rx, c0, c1, 0
-                tst     \rx, #0x20000000
-                beq     1001b
-                .endm
-
-                .macro  waituart, rd, rx
-                mov     \rd, #0x2000000
-1001:
-                subs    \rd, \rd, #1
-                bmi     1002f
-                mrc     p14, 0, \rx, c0, c1, 0
-                tst     \rx, #0x20000000
-                bne     1001b
-1002:
-                .endm
-
-#elif defined(CONFIG_CPU_XSCALE)
-
-                .macro  senduart, rd, rx
-                mcr     p14, 0, \rd, c8, c0, 0
-                .endm
-
-                .macro  busyuart, rd, rx
-1001:
-                mrc     p14, 0, \rx, c14, c0, 0
-                tst     \rx, #0x10000000
-                beq     1001b
-                .endm
-
-                .macro  waituart, rd, rx
-                mov     \rd, #0x10000000
-1001:
-                subs    \rd, \rd, #1
-                bmi     1002f
-                mrc     p14, 0, \rx, c14, c0, 0
-                tst     \rx, #0x10000000
-                bne     1001b
-1002:
-                .endm
-
-#else
-
-                .macro  senduart, rd, rx
-                mcr     p14, 0, \rd, c1, c0, 0
-                .endm
-
-                .macro  busyuart, rd, rx
-1001:
-                mrc     p14, 0, \rx, c0, c0, 0
-                tst     \rx, #2
-                beq     1001b
-
-                .endm
-
-                .macro  waituart, rd, rx
-                mov     \rd, #0x2000000
-1001:
-                subs    \rd, \rd, #1
-                bmi     1002f
-                mrc     p14, 0, \rx, c0, c0, 0
-                tst     \rx, #2
-                bne     1001b
-1002:
-                .endm
-
-#endif  /* CONFIG_CPU_V6 */
-
-#elif !defined(CONFIG_DEBUG_SEMIHOSTING)
-#include <mach/debug-macro.S>
-#endif  /* CONFIG_DEBUG_ICEDCC */
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
 
 #ifdef CONFIG_MMU
                 .macro  addruart_current, rx, tmp1, tmp2
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 3db960e20cb8..9874d0741191 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -23,8 +23,8 @@
 #include <asm/thread_info.h>
 #include <asm/pgtable.h>
 
-#ifdef CONFIG_DEBUG_LL
-#include <mach/debug-macro.S>
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
 #endif
 
 /*
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ab243b87118d..93971b1a4f0b 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -12,68 +12,15 @@
  */
 #define pr_fmt(fmt) "hw perfevents: " fmt
 
-#include <linux/bitmap.h>
-#include <linux/interrupt.h>
 #include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/perf_event.h>
 #include <linux/platform_device.h>
-#include <linux/spinlock.h>
+#include <linux/pm_runtime.h>
 #include <linux/uaccess.h>
 
-#include <asm/cputype.h>
-#include <asm/irq.h>
 #include <asm/irq_regs.h>
 #include <asm/pmu.h>
 #include <asm/stacktrace.h>
 
-/*
- * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
- * another platform that supports more, we need to increase this to be the
- * largest of all platforms.
- *
- * ARMv7 supports up to 32 events:
- *  cycle counter CCNT + 31 events counters CNT0..30.
- *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
- */
-#define ARMPMU_MAX_HWEVENTS             32
-
-static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
-static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
-static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
-
-#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-
-/* Set at runtime when we know what CPU type we are. */
-static struct arm_pmu *cpu_pmu;
-
-const char *perf_pmu_name(void)
-{
-        if (!cpu_pmu)
-                return NULL;
-
-        return cpu_pmu->pmu.name;
-}
-EXPORT_SYMBOL_GPL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
-        int max_events = 0;
-
-        if (cpu_pmu != NULL)
-                max_events = cpu_pmu->num_events;
-
-        return max_events;
-}
-EXPORT_SYMBOL_GPL(perf_num_counters);
-
-#define HW_OP_UNSUPPORTED               0xFFFF
-
-#define C(_x) \
-        PERF_COUNT_HW_CACHE_##_x
-
-#define CACHE_OP_UNSUPPORTED            0xFFFF
-
 static int
 armpmu_map_cache_event(const unsigned (*cache_map)
                                       [PERF_COUNT_HW_CACHE_MAX]
@@ -104,7 +51,7 @@ armpmu_map_cache_event(const unsigned (*cache_map)
 }
 
 static int
-armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
+armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 {
         int mapping = (*event_map)[config];
         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
@@ -116,19 +63,20 @@ armpmu_map_raw_event(u32 raw_event_mask, u64 config)
         return (int)(config & raw_event_mask);
 }
 
-static int map_cpu_event(struct perf_event *event,
-                         const unsigned (*event_map)[PERF_COUNT_HW_MAX],
-                         const unsigned (*cache_map)
-                                        [PERF_COUNT_HW_CACHE_MAX]
-                                        [PERF_COUNT_HW_CACHE_OP_MAX]
-                                        [PERF_COUNT_HW_CACHE_RESULT_MAX],
-                         u32 raw_event_mask)
+int
+armpmu_map_event(struct perf_event *event,
+                 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+                 const unsigned (*cache_map)
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX],
+                 u32 raw_event_mask)
 {
         u64 config = event->attr.config;
 
         switch (event->attr.type) {
         case PERF_TYPE_HARDWARE:
-                return armpmu_map_event(event_map, config);
+                return armpmu_map_hw_event(event_map, config);
         case PERF_TYPE_HW_CACHE:
                 return armpmu_map_cache_event(cache_map, config);
         case PERF_TYPE_RAW:
@@ -222,7 +170,6 @@ armpmu_stop(struct perf_event *event, int flags)
          */
         if (!(hwc->state & PERF_HES_STOPPED)) {
                 armpmu->disable(hwc, hwc->idx);
-                barrier(); /* why? */
                 armpmu_event_update(event, hwc, hwc->idx);
                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
         }
@@ -350,99 +297,41 @@ validate_group(struct perf_event *event)
         return 0;
 }
 
-static irqreturn_t armpmu_platform_irq(int irq, void *dev)
+static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 {
         struct arm_pmu *armpmu = (struct arm_pmu *) dev;
         struct platform_device *plat_device = armpmu->plat_device;
         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 
-        return plat->handle_irq(irq, dev, armpmu->handle_irq);
+        if (plat && plat->handle_irq)
+                return plat->handle_irq(irq, dev, armpmu->handle_irq);
+        else
+                return armpmu->handle_irq(irq, dev);
 }
 
 static void
 armpmu_release_hardware(struct arm_pmu *armpmu)
 {
-        int i, irq, irqs;
-        struct platform_device *pmu_device = armpmu->plat_device;
-        struct arm_pmu_platdata *plat =
-                dev_get_platdata(&pmu_device->dev);
-
-        irqs = min(pmu_device->num_resources, num_possible_cpus());
-
-        for (i = 0; i < irqs; ++i) {
-                if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
-                        continue;
-                irq = platform_get_irq(pmu_device, i);
-                if (irq >= 0) {
-                        if (plat && plat->disable_irq)
-                                plat->disable_irq(irq);
-                        free_irq(irq, armpmu);
-                }
-        }
-
-        release_pmu(armpmu->type);
+        armpmu->free_irq();
+        pm_runtime_put_sync(&armpmu->plat_device->dev);
 }
 
 static int
 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 {
-        struct arm_pmu_platdata *plat;
-        irq_handler_t handle_irq;
-        int i, err, irq, irqs;
+        int err;
         struct platform_device *pmu_device = armpmu->plat_device;
 
         if (!pmu_device)
                 return -ENODEV;
 
-        err = reserve_pmu(armpmu->type);
+        pm_runtime_get_sync(&pmu_device->dev);
+        err = armpmu->request_irq(armpmu_dispatch_irq);
         if (err) {
-                pr_warning("unable to reserve pmu\n");
+                armpmu_release_hardware(armpmu);
                 return err;
         }
 
-        plat = dev_get_platdata(&pmu_device->dev);
-        if (plat && plat->handle_irq)
-                handle_irq = armpmu_platform_irq;
-        else
-                handle_irq = armpmu->handle_irq;
-
-        irqs = min(pmu_device->num_resources, num_possible_cpus());
-        if (irqs < 1) {
-                pr_err("no irqs for PMUs defined\n");
-                return -ENODEV;
-        }
-
-        for (i = 0; i < irqs; ++i) {
-                err = 0;
-                irq = platform_get_irq(pmu_device, i);
-                if (irq < 0)
-                        continue;
-
-                /*
-                 * If we have a single PMU interrupt that we can't shift,
-                 * assume that we're running on a uniprocessor machine and
-                 * continue. Otherwise, continue without this interrupt.
-                 */
-                if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
-                        pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
-                                    irq, i);
-                        continue;
-                }
-
-                err = request_irq(irq, handle_irq,
-                                  IRQF_DISABLED | IRQF_NOBALANCING,
-                                  "arm-pmu", armpmu);
-                if (err) {
-                        pr_err("unable to request IRQ%d for ARM PMU counters\n",
-                                irq);
-                        armpmu_release_hardware(armpmu);
-                        return err;
-                } else if (plat && plat->enable_irq)
-                        plat->enable_irq(irq);
-
-                cpumask_set_cpu(i, &armpmu->active_irqs);
-        }
-
         return 0;
 }
 
@@ -581,6 +470,32 @@ static void armpmu_disable(struct pmu *pmu)
         armpmu->stop();
 }
 
+#ifdef CONFIG_PM_RUNTIME
+static int armpmu_runtime_resume(struct device *dev)
+{
+        struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+        if (plat && plat->runtime_resume)
+                return plat->runtime_resume(dev);
+
+        return 0;
+}
+
+static int armpmu_runtime_suspend(struct device *dev)
+{
+        struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+        if (plat && plat->runtime_suspend)
+                return plat->runtime_suspend(dev);
+
+        return 0;
+}
+#endif
+
+const struct dev_pm_ops armpmu_dev_pm_ops = {
+        SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
+};
+
 static void __init armpmu_init(struct arm_pmu *armpmu)
 {
         atomic_set(&armpmu->active_events, 0);
@@ -598,174 +513,14 @@ static void __init armpmu_init(struct arm_pmu *armpmu)
         };
 }
 
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 {
         armpmu_init(armpmu);
+        pr_info("enabled with %s PMU driver, %d counters available\n",
+                        armpmu->name, armpmu->num_events);
         return perf_pmu_register(&armpmu->pmu, name, type);
 }
 
-/* Include the PMU-specific implementations. */
-#include "perf_event_xscale.c"
-#include "perf_event_v6.c"
-#include "perf_event_v7.c"
-
-/*
- * Ensure the PMU has sane values out of reset.
- * This requires SMP to be available, so exists as a separate initcall.
- */
-static int __init
-cpu_pmu_reset(void)
-{
-        if (cpu_pmu && cpu_pmu->reset)
-                return on_each_cpu(cpu_pmu->reset, NULL, 1);
-        return 0;
-}
-arch_initcall(cpu_pmu_reset);
-
-/*
- * PMU platform driver and devicetree bindings.
- */
-static struct of_device_id armpmu_of_device_ids[] = {
-        {.compatible = "arm,cortex-a9-pmu"},
-        {.compatible = "arm,cortex-a8-pmu"},
-        {.compatible = "arm,arm1136-pmu"},
-        {.compatible = "arm,arm1176-pmu"},
-        {},
-};
-
-static struct platform_device_id armpmu_plat_device_ids[] = {
-        {.name = "arm-pmu"},
-        {},
-};
-
-static int __devinit armpmu_device_probe(struct platform_device *pdev)
-{
-        if (!cpu_pmu)
-                return -ENODEV;
-
-        cpu_pmu->plat_device = pdev;
-        return 0;
-}
-
-static struct platform_driver armpmu_driver = {
-        .driver         = {
-                .name   = "arm-pmu",
-                .of_match_table = armpmu_of_device_ids,
-        },
-        .probe          = armpmu_device_probe,
-        .id_table       = armpmu_plat_device_ids,
-};
-
-static int __init register_pmu_driver(void)
-{
-        return platform_driver_register(&armpmu_driver);
-}
-device_initcall(register_pmu_driver);
-
-static struct pmu_hw_events *armpmu_get_cpu_events(void)
-{
-        return &__get_cpu_var(cpu_hw_events);
-}
-
-static void __init cpu_pmu_init(struct arm_pmu *armpmu)
-{
-        int cpu;
-        for_each_possible_cpu(cpu) {
-                struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
-                events->events = per_cpu(hw_events, cpu);
-                events->used_mask = per_cpu(used_mask, cpu);
-                raw_spin_lock_init(&events->pmu_lock);
-        }
-        armpmu->get_hw_events = armpmu_get_cpu_events;
-        armpmu->type = ARM_PMU_DEVICE_CPU;
-}
-
-/*
- * PMU hardware loses all context when a CPU goes offline.
- * When a CPU is hotplugged back in, since some hardware registers are
- * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
- * junk values out of them.
- */
-static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
-                                        unsigned long action, void *hcpu)
-{
-        if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
-                return NOTIFY_DONE;
-
-        if (cpu_pmu && cpu_pmu->reset)
-                cpu_pmu->reset(NULL);
-
-        return NOTIFY_OK;
-}
-
-static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
-        .notifier_call = pmu_cpu_notify,
-};
-
-/*
- * CPU PMU identification and registration.
- */
-static int __init
-init_hw_perf_events(void)
-{
-        unsigned long cpuid = read_cpuid_id();
-        unsigned long implementor = (cpuid & 0xFF000000) >> 24;
-        unsigned long part_number = (cpuid & 0xFFF0);
-
-        /* ARM Ltd CPUs. */
-        if (0x41 == implementor) {
-                switch (part_number) {
-                case 0xB360:    /* ARM1136 */
-                case 0xB560:    /* ARM1156 */
-                case 0xB760:    /* ARM1176 */
-                        cpu_pmu = armv6pmu_init();
-                        break;
-                case 0xB020:    /* ARM11mpcore */
-                        cpu_pmu = armv6mpcore_pmu_init();
-                        break;
-                case 0xC080:    /* Cortex-A8 */
-                        cpu_pmu = armv7_a8_pmu_init();
-                        break;
-                case 0xC090:    /* Cortex-A9 */
-                        cpu_pmu = armv7_a9_pmu_init();
-                        break;
-                case 0xC050:    /* Cortex-A5 */
-                        cpu_pmu = armv7_a5_pmu_init();
-                        break;
-                case 0xC0F0:    /* Cortex-A15 */
-                        cpu_pmu = armv7_a15_pmu_init();
-                        break;
-                case 0xC070:    /* Cortex-A7 */
-                        cpu_pmu = armv7_a7_pmu_init();
-                        break;
-                }
-        /* Intel CPUs [xscale]. */
-        } else if (0x69 == implementor) {
-                part_number = (cpuid >> 13) & 0x7;
-                switch (part_number) {
-                case 1:
-                        cpu_pmu = xscale1pmu_init();
-                        break;
-                case 2:
-                        cpu_pmu = xscale2pmu_init();
-                        break;
-                }
-        }
-
-        if (cpu_pmu) {
-                pr_info("enabled with %s PMU driver, %d counters available\n",
-                        cpu_pmu->name, cpu_pmu->num_events);
-                cpu_pmu_init(cpu_pmu);
-                register_cpu_notifier(&pmu_cpu_notifier);
-                armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
-        } else {
-                pr_info("no hardware support available\n");
-        }
-
-        return 0;
-}
-early_initcall(init_hw_perf_events);
-
 /*
  * Callchain handling code.
  */
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
new file mode 100644
index 000000000000..8d7d8d4de9d6
--- /dev/null
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -0,0 +1,295 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+#define pr_fmt(fmt) "CPU PMU: " fmt
+
+#include <linux/bitmap.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#include <asm/cputype.h>
+#include <asm/irq_regs.h>
+#include <asm/pmu.h>
+
+/* Set at runtime when we know what CPU type we are. */
+static struct arm_pmu *cpu_pmu;
+
+static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
+static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
+static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
+
+/*
+ * Despite the names, these two functions are CPU-specific and are used
+ * by the OProfile/perf code.
+ */
+const char *perf_pmu_name(void)
+{
+        if (!cpu_pmu)
+                return NULL;
+
+        return cpu_pmu->pmu.name;
+}
+EXPORT_SYMBOL_GPL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+        int max_events = 0;
+
+        if (cpu_pmu != NULL)
+                max_events = cpu_pmu->num_events;
+
+        return max_events;
+}
+EXPORT_SYMBOL_GPL(perf_num_counters);
+
+/* Include the PMU-specific implementations. */
+#include "perf_event_xscale.c"
+#include "perf_event_v6.c"
+#include "perf_event_v7.c"
+
+static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
+{
+        return &__get_cpu_var(cpu_hw_events);
+}
+
+static void cpu_pmu_free_irq(void)
+{
+        int i, irq, irqs;
+        struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+        irqs = min(pmu_device->num_resources, num_possible_cpus());
+
+        for (i = 0; i < irqs; ++i) {
+                if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
+                        continue;
+                irq = platform_get_irq(pmu_device, i);
+                if (irq >= 0)
+                        free_irq(irq, cpu_pmu);
+        }
+}
+
+static int cpu_pmu_request_irq(irq_handler_t handler)
+{
+        int i, err, irq, irqs;
+        struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+        if (!pmu_device)
+                return -ENODEV;
+
+        irqs = min(pmu_device->num_resources, num_possible_cpus());
+        if (irqs < 1) {
+                pr_err("no irqs for PMUs defined\n");
+                return -ENODEV;
+        }
+
+        for (i = 0; i < irqs; ++i) {
+                err = 0;
+                irq = platform_get_irq(pmu_device, i);
+                if (irq < 0)
+                        continue;
+
+                /*
+                 * If we have a single PMU interrupt that we can't shift,
+                 * assume that we're running on a uniprocessor machine and
+                 * continue. Otherwise, continue without this interrupt.
+                 */
+                if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+                        pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+                                    irq, i);
+                        continue;
+                }
+
+                err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu",
+                                  cpu_pmu);
+                if (err) {
+                        pr_err("unable to request IRQ%d for ARM PMU counters\n",
+                                irq);
+                        return err;
+                }
+
+                cpumask_set_cpu(i, &cpu_pmu->active_irqs);
+        }
+
+        return 0;
+}
+
+static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
+{
+        int cpu;
+        for_each_possible_cpu(cpu) {
+                struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+                events->events = per_cpu(hw_events, cpu);
+                events->used_mask = per_cpu(used_mask, cpu);
+                raw_spin_lock_init(&events->pmu_lock);
+        }
+
+        cpu_pmu->get_hw_events  = cpu_pmu_get_cpu_events;
+        cpu_pmu->request_irq    = cpu_pmu_request_irq;
+        cpu_pmu->free_irq       = cpu_pmu_free_irq;
+
+        /* Ensure the PMU has sane values out of reset. */
+        if (cpu_pmu && cpu_pmu->reset)
+                on_each_cpu(cpu_pmu->reset, NULL, 1);
+}
+
+/*
+ * PMU hardware loses all context when a CPU goes offline.
+ * When a CPU is hotplugged back in, since some hardware registers are
+ * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
+ * junk values out of them.
+ */
+static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
+                                    unsigned long action, void *hcpu)
+{
+        if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
+                return NOTIFY_DONE;
+
+        if (cpu_pmu && cpu_pmu->reset)
+                cpu_pmu->reset(NULL);
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+        .notifier_call = cpu_pmu_notify,
+};
+
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
+        {.compatible = "arm,cortex-a15-pmu",    .data = armv7_a15_pmu_init},
+        {.compatible = "arm,cortex-a9-pmu",     .data = armv7_a9_pmu_init},
+        {.compatible = "arm,cortex-a8-pmu",     .data = armv7_a8_pmu_init},
+        {.compatible = "arm,cortex-a7-pmu",     .data = armv7_a7_pmu_init},
+        {.compatible = "arm,cortex-a5-pmu",     .data = armv7_a5_pmu_init},
+        {.compatible = "arm,arm11mpcore-pmu",   .data = armv6mpcore_pmu_init},
+        {.compatible = "arm,arm1176-pmu",       .data = armv6pmu_init},
+        {.compatible = "arm,arm1136-pmu",       .data = armv6pmu_init},
+        {},
+};
+
+static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
+        {.name = "arm-pmu"},
+        {},
+};
+
+/*
+ * CPU PMU identification and probing.
+ */
+static struct arm_pmu *__devinit probe_current_pmu(void)
+{
+        struct arm_pmu *pmu = NULL;
+        int cpu = get_cpu();
+        unsigned long cpuid = read_cpuid_id();
+        unsigned long implementor = (cpuid & 0xFF000000) >> 24;
+        unsigned long part_number = (cpuid & 0xFFF0);
+
+        pr_info("probing PMU on CPU %d\n", cpu);
+
+        /* ARM Ltd CPUs. */
+        if (0x41 == implementor) {
+                switch (part_number) {
+                case 0xB360:    /* ARM1136 */
+                case 0xB560:    /* ARM1156 */
+                case 0xB760:    /* ARM1176 */
+                        pmu = armv6pmu_init();
+                        break;
+                case 0xB020:    /* ARM11mpcore */
+                        pmu = armv6mpcore_pmu_init();
+                        break;
+                case 0xC080:    /* Cortex-A8 */
+                        pmu = armv7_a8_pmu_init();
+                        break;
+                case 0xC090:    /* Cortex-A9 */
+                        pmu = armv7_a9_pmu_init();
+                        break;
+                case 0xC050:    /* Cortex-A5 */
+                        pmu = armv7_a5_pmu_init();
+                        break;
+                case 0xC0F0:    /* Cortex-A15 */
+                        pmu = armv7_a15_pmu_init();
+                        break;
+                case 0xC070:    /* Cortex-A7 */
+                        pmu = armv7_a7_pmu_init();
+                        break;
+                }
+        /* Intel CPUs [xscale]. */
+        } else if (0x69 == implementor) {
+                part_number = (cpuid >> 13) & 0x7;
+                switch (part_number) {
+                case 1:
+                        pmu = xscale1pmu_init();
+                        break;
+                case 2:
+                        pmu = xscale2pmu_init();
+                        break;
+                }
+        }
+
+        put_cpu();
+        return pmu;
+}
+
+static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *of_id;
+        struct arm_pmu *(*init_fn)(void);
+        struct device_node *node = pdev->dev.of_node;
+
+        if (cpu_pmu) {
+                pr_info("attempt to register multiple PMU devices!");
+                return -ENOSPC;
+        }
+
+        if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
+                init_fn = of_id->data;
+                cpu_pmu = init_fn();
+        } else {
+                cpu_pmu = probe_current_pmu();
+        }
+
+        if (!cpu_pmu)
+                return -ENODEV;
+
+        cpu_pmu->plat_device = pdev;
+        cpu_pmu_init(cpu_pmu);
+        register_cpu_notifier(&cpu_pmu_hotplug_notifier);
+        armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
+
+        return 0;
+}
+
+static struct platform_driver cpu_pmu_driver = {
+        .driver         = {
+                .name   = "arm-pmu",
+                .pm     = &armpmu_dev_pm_ops,
+                .of_match_table = cpu_pmu_of_device_ids,
+        },
+        .probe          = cpu_pmu_device_probe,
+        .id_table       = cpu_pmu_plat_device_ids,
+};
+
+static int __init register_pmu_driver(void)
+{
+        return platform_driver_register(&cpu_pmu_driver);
+}
+device_initcall(register_pmu_driver);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index c90fcb2b6967..6ccc07971745 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -645,7 +645,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
 
 static int armv6_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv6_perf_map,
+        return armpmu_map_event(event, &armv6_perf_map,
                                 &armv6_perf_cache_map, 0xFF);
 }
 
@@ -664,7 +664,7 @@ static struct arm_pmu armv6pmu = {
         .max_period             = (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
 {
         return &armv6pmu;
 }
@@ -679,7 +679,7 @@ static struct arm_pmu *__init armv6pmu_init(void)
 
 static int armv6mpcore_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv6mpcore_perf_map,
+        return armpmu_map_event(event, &armv6mpcore_perf_map,
                                 &armv6mpcore_perf_cache_map, 0xFF);
 }
 
@@ -698,17 +698,17 @@ static struct arm_pmu armv6mpcore_pmu = {
         .max_period             = (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
 {
         return &armv6mpcore_pmu;
 }
 #else
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
 {
         return NULL;
 }
 
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
 {
         return NULL;
 }
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index f04070bd2183..bd4b090ebcfd 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1204,31 +1204,31 @@ static void armv7pmu_reset(void *info)
 
 static int armv7_a8_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a8_perf_map,
+        return armpmu_map_event(event, &armv7_a8_perf_map,
                                 &armv7_a8_perf_cache_map, 0xFF);
 }
 
 static int armv7_a9_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a9_perf_map,
+        return armpmu_map_event(event, &armv7_a9_perf_map,
                                 &armv7_a9_perf_cache_map, 0xFF);
 }
 
 static int armv7_a5_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a5_perf_map,
+        return armpmu_map_event(event, &armv7_a5_perf_map,
                                 &armv7_a5_perf_cache_map, 0xFF);
 }
 
 static int armv7_a15_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a15_perf_map,
+        return armpmu_map_event(event, &armv7_a15_perf_map,
                                 &armv7_a15_perf_cache_map, 0xFF);
 }
 
 static int armv7_a7_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a7_perf_map,
+        return armpmu_map_event(event, &armv7_a7_perf_map,
                                 &armv7_a7_perf_cache_map, 0xFF);
 }
 
@@ -1245,7 +1245,7 @@ static struct arm_pmu armv7pmu = {
         .max_period             = (1LLU << 32) - 1,
 };
 
-static u32 __init armv7_read_num_pmnc_events(void)
+static u32 __devinit armv7_read_num_pmnc_events(void)
 {
         u32 nb_cnt;
 
@@ -1256,7 +1256,7 @@ static u32 __init armv7_read_num_pmnc_events(void)
         return nb_cnt + 1;
 }
 
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
 {
         armv7pmu.name           = "ARMv7 Cortex-A8";
         armv7pmu.map_event      = armv7_a8_map_event;
@@ -1264,7 +1264,7 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
         return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
 {
         armv7pmu.name           = "ARMv7 Cortex-A9";
         armv7pmu.map_event      = armv7_a9_map_event;
@@ -1272,7 +1272,7 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void)
         return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
 {
         armv7pmu.name           = "ARMv7 Cortex-A5";
         armv7pmu.map_event      = armv7_a5_map_event;
@@ -1280,7 +1280,7 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void)
         return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
 {
         armv7pmu.name           = "ARMv7 Cortex-A15";
         armv7pmu.map_event      = armv7_a15_map_event;
@@ -1289,7 +1289,7 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void)
         return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
 {
         armv7pmu.name           = "ARMv7 Cortex-A7";
         armv7pmu.map_event      = armv7_a7_map_event;
@@ -1298,27 +1298,27 @@ static struct arm_pmu *__init armv7_a7_pmu_init(void)
         return &armv7pmu;
 }
 #else
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
 {
         return NULL;
 }
 
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
 {
         return NULL;
 }
 
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
 {
         return NULL;
 }
 
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
 {
         return NULL;
 }
 
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
 {
         return NULL;
 }
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index f759fe0bab63..426e19f380a2 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -430,7 +430,7 @@ xscale1pmu_write_counter(int counter, u32 val)
 
 static int xscale_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &xscale_perf_map,
+        return armpmu_map_event(event, &xscale_perf_map,
                                 &xscale_perf_cache_map, 0xFF);
 }
 
@@ -449,7 +449,7 @@ static struct arm_pmu xscale1pmu = {
         .max_period     = (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
 {
         return &xscale1pmu;
 }
@@ -816,17 +816,17 @@ static struct arm_pmu xscale2pmu = {
         .max_period     = (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
 {
         return &xscale2pmu;
 }
 #else
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
 {
         return NULL;
 }
 
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
 {
         return NULL;
 }
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
deleted file mode 100644
index 2334bf8a650a..000000000000
--- a/arch/arm/kernel/pmu.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  linux/arch/arm/kernel/pmu.c
- *
- *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
- *  Copyright (C) 2010 ARM Ltd, Will Deacon
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/pmu.h>
-
-/*
- * PMU locking to ensure mutual exclusion between different subsystems.
- */
-static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)];
-
-int
-reserve_pmu(enum arm_pmu_type type)
-{
-        return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0;
-}
-EXPORT_SYMBOL_GPL(reserve_pmu);
-
-void
-release_pmu(enum arm_pmu_type type)
-{
-        clear_bit_unlock(type, pmu_lock);
-}
-EXPORT_SYMBOL_GPL(release_pmu);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a81dcecc7343..725f9f2a9541 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -977,8 +977,10 @@ void __init setup_arch(char **cmdline_p)
         unflatten_device_tree();
 
 #ifdef CONFIG_SMP
-        if (is_smp())
+        if (is_smp()) {
+                smp_set_ops(mdesc->smp);
                 smp_init_cpus();
+        }
 #endif
         reserve_crashkernel();
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebd8ad274d76..aa4ffe6e5ecf 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -19,7 +19,6 @@
 #include <linux/mm.h>
 #include <linux/err.h>
 #include <linux/cpu.h>
-#include <linux/smp.h>
 #include <linux/seq_file.h>
 #include <linux/irq.h>
 #include <linux/percpu.h>
@@ -27,6 +26,7 @@
 #include <linux/completion.h>
 
 #include <linux/atomic.h>
+#include <asm/smp.h>
 #include <asm/cacheflush.h>
 #include <asm/cpu.h>
 #include <asm/cputype.h>
@@ -42,6 +42,7 @@
 #include <asm/ptrace.h>
 #include <asm/localtimer.h>
 #include <asm/smp_plat.h>
+#include <asm/mach/arch.h>
 
 /*
  * as from 2.5, kernels no longer have an init_tasks structure
@@ -50,6 +51,12 @@
  */
 struct secondary_data secondary_data;
 
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+
 enum ipi_msg_type {
         IPI_TIMER = 2,
         IPI_RESCHEDULE,
@@ -60,6 +67,14 @@ enum ipi_msg_type {
 
 static DECLARE_COMPLETION(cpu_running);
 
+static struct smp_operations smp_ops;
+
+void __init smp_set_ops(struct smp_operations *ops)
+{
+        if (ops)
+                smp_ops = *ops;
+};
+
 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
         int ret;
@@ -100,13 +115,64 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
         return ret;
 }
 
+/* platform specific SMP operations */
+void __init smp_init_cpus(void)
+{
+        if (smp_ops.smp_init_cpus)
+                smp_ops.smp_init_cpus();
+}
+
+static void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        if (smp_ops.smp_prepare_cpus)
+                smp_ops.smp_prepare_cpus(max_cpus);
+}
+
+static void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        if (smp_ops.smp_secondary_init)
+                smp_ops.smp_secondary_init(cpu);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        if (smp_ops.smp_boot_secondary)
+                return smp_ops.smp_boot_secondary(cpu, idle);
+        return -ENOSYS;
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 static void percpu_timer_stop(void);
 
+static int platform_cpu_kill(unsigned int cpu)
+{
+        if (smp_ops.cpu_kill)
+                return smp_ops.cpu_kill(cpu);
+        return 1;
+}
+
+static void platform_cpu_die(unsigned int cpu)
+{
+        if (smp_ops.cpu_die)
+                smp_ops.cpu_die(cpu);
+}
+
+static int platform_cpu_disable(unsigned int cpu)
+{
+        if (smp_ops.cpu_disable)
+                return smp_ops.cpu_disable(cpu);
+
+        /*
+         * By default, allow disabling all CPUs except the first one,
+         * since this is special on a lot of platforms, e.g. because
+         * of clock tick interrupts.
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
 /*
  * __cpu_disable runs on the processor to be shutdown.
  */
-int __cpu_disable(void)
+int __cpuinit __cpu_disable(void)
 {
         unsigned int cpu = smp_processor_id();
         int ret;
@@ -149,7 +215,7 @@ static DECLARE_COMPLETION(cpu_died);
  * called on the thread which is asking for a CPU to be shutdown -
  * waits until shutdown has completed, or it is timed out.
  */
-void __cpu_die(unsigned int cpu)
+void __cpuinit __cpu_die(unsigned int cpu)
 {
         if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
                 pr_err("CPU%u: cpu didn't die\n", cpu);
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 30bb7332e30b..5309f9b6aabc 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -12,27 +12,3 @@ else
 params_phys-y   := 0x20000100
 initrd_phys-y   := 0x20410000
 endif
-
-# Keep dtb files sorted alphabetically for each SoC
-# sam9260
-dtb-$(CONFIG_MACH_AT91SAM_DT) += aks-cdu.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb
-# sam9263
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9263ek.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9263.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9263.dtb
-# sam9g20
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += kizbox.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
-# sam9g45
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
-# sam9n12
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb
-# sam9x5
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 1b47319ca00b..e4c3b3709204 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -31,7 +31,7 @@
 #include <mach/at91sam9g45_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
+#include <linux/platform_data/dma-atmel.h>
 #include <mach/atmel-mci.h>
 
 #include <media/atmel-isi.h>
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index b3d365dadef5..dcda24838b5a 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -22,7 +22,7 @@
 #include <mach/at91sam9rl_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
+#include <linux/platform_data/dma-atmel.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 46090e642d8e..6bd7300a2bc5 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -47,7 +47,7 @@ static void at91x40_idle(void)
          * Disable the processor clock.  The processor will be automatically
          * re-enabled by an interrupt or by a reset.
          */
-        __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
+        __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
         cpu_do_idle();
 }
 
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 6ca680a1d5d1..ee06d7bcdf76 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -29,10 +29,10 @@
 #include <mach/at91_tc.h>
 
 #define at91_tc_read(field) \
-        __raw_readl(AT91_TC + field)
+        __raw_readl(AT91_IO_P2V(AT91_TC) + field)
 
 #define at91_tc_write(field, value) \
-        __raw_writel(value, AT91_TC + field);
+        __raw_writel(value, AT91_IO_P2V(AT91_TC) + field);
 
 /*
  *      3 counter/timer units present.
diff --git a/arch/arm/mach-at91/include/mach/atmel-mci.h b/arch/arm/mach-at91/include/mach/atmel-mci.h
index 998cb0c07135..cd580a12e904 100644
--- a/arch/arm/mach-at91/include/mach/atmel-mci.h
+++ b/arch/arm/mach-at91/include/mach/atmel-mci.h
@@ -1,7 +1,7 @@
 #ifndef __MACH_ATMEL_MCI_H
 #define __MACH_ATMEL_MCI_H
 
-#include <mach/at_hdmac.h>
+#include <linux/platform_data/dma-atmel.h>
 
 /**
  * struct mci_dma_data - DMA data for MCI interface
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 09242b67d277..711a7892d331 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -67,13 +67,13 @@
  * to 0xFEF78000 .. 0xFF000000.  (544Kb)
  */
 #define AT91_IO_PHYS_BASE       0xFFF78000
-#define AT91_IO_VIRT_BASE       (0xFF000000 - AT91_IO_SIZE)
+#define AT91_IO_VIRT_BASE       IOMEM(0xFF000000 - AT91_IO_SIZE)
 #else
 /*
  * Identity mapping for the non MMU case.
  */
 #define AT91_IO_PHYS_BASE       AT91_BASE_SYS
-#define AT91_IO_VIRT_BASE       AT91_IO_PHYS_BASE
+#define AT91_IO_VIRT_BASE       IOMEM(AT91_IO_PHYS_BASE)
 #endif
 
 #define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 6f6118d1576a..97ad68a826f8 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
         0,
 };
 
-static inline const u32* decomp_soc_detect(u32 dbgu_base)
+static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 {
         u32 cidr, socid;
 
@@ -142,10 +142,10 @@ static inline void arch_decomp_setup(void)
         int i = 0;
         const u32* usarts;
 
-        usarts = decomp_soc_detect(AT91_BASE_DBGU0);
+        usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
 
         if (!usarts)
-                usarts = decomp_soc_detect(AT91_BASE_DBGU1);
+                usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
         if (!usarts) {
                 at91_uart = NULL;
                 return;
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 944bffb08991..e6f52de1062f 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -73,7 +73,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 {
         struct map_desc *desc = &sram_desc[bank];
 
-        desc->virtual = AT91_IO_VIRT_BASE - length;
+        desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
         if (bank > 0)
                 desc->virtual -= sram_desc[bank - 1].length;
 
@@ -88,7 +88,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 }
 
 static struct map_desc at91_io_desc __initdata = {
-        .virtual        = AT91_VA_BASE_SYS,
+        .virtual        = (unsigned long)AT91_VA_BASE_SYS,
         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
         .length         = SZ_16K,
         .type           = MT_DEVICE,
diff --git a/arch/arm/mach-bcm2835/Makefile b/arch/arm/mach-bcm2835/Makefile
new file mode 100644
index 000000000000..4c3892fe02c3
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Makefile
@@ -0,0 +1 @@
+obj-y += bcm2835.o
diff --git a/arch/arm/mach-bcm2835/Makefile.boot b/arch/arm/mach-bcm2835/Makefile.boot
new file mode 100644
index 000000000000..2d30e17f5b69
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
new file mode 100644
index 000000000000..f6fea4933571
--- /dev/null
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/irqchip/bcm2835.h>
+#include <linux/of_platform.h>
+#include <linux/bcm2835_timer.h>
+#include <linux/clk/bcm2835.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/bcm2835_soc.h>
+
+static struct map_desc io_map __initdata = {
+        .virtual = BCM2835_PERIPH_VIRT,
+        .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
+        .length = BCM2835_PERIPH_SIZE,
+        .type = MT_DEVICE
+};
+
+void __init bcm2835_map_io(void)
+{
+        iotable_init(&io_map, 1);
+}
+
+void __init bcm2835_init(void)
+{
+        int ret;
+
+        bcm2835_init_clocks();
+
+        ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
+                                   NULL);
+        if (ret) {
+                pr_err("of_platform_populate failed: %d\n", ret);
+                BUG();
+        }
+}
+
+static const char * const bcm2835_compat[] = {
+        "brcm,bcm2835",
+        NULL
+};
+
+DT_MACHINE_START(BCM2835, "BCM2835")
+        .map_io = bcm2835_map_io,
+        .init_irq = bcm2835_init_irq,
+        .handle_irq = bcm2835_handle_irq,
+        .init_machine = bcm2835_init,
+        .timer = &bcm2835_timer,
+        .dt_compat = bcm2835_compat
+MACHINE_END
diff --git a/arch/arm/mach-picoxcell/include/mach/map.h b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
index c06afad218bb..d4dfcf7a9cda 100644
--- a/arch/arm/mach-picoxcell/include/mach/map.h
+++ b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
@@ -1,5 +1,8 @@
 /*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ * Copyright (C) 2012 Stephen Warren
+ *
+ * Derived from code:
+ * Copyright (C) 2010 Broadcom
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -11,15 +14,16 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-#ifndef __PICOXCELL_MAP_H__
-#define __PICOXCELL_MAP_H__
 
-#define PHYS_TO_IO(x)           (((x) & 0x00ffffff) | 0xfe000000)
+#ifndef __MACH_BCM2835_BCM2835_SOC_H__
+#define __MACH_BCM2835_BCM2835_SOC_H__
 
-#ifdef __ASSEMBLY__
-#define IO_ADDRESS(x)           PHYS_TO_IO((x))
-#else
-#define IO_ADDRESS(x)           (void __iomem __force *)(PHYS_TO_IO((x)))
-#endif
+#include <asm/sizes.h>
 
-#endif /* __PICOXCELL_MAP_H__ */
+#define BCM2835_PERIPH_PHYS     0x20000000
+#define BCM2835_PERIPH_VIRT     0xf0000000
+#define BCM2835_PERIPH_SIZE     SZ_16M
+#define BCM2835_DEBUG_PHYS      0x20201000
+#define BCM2835_DEBUG_VIRT      0xf0201000
+
+#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/debug-macro.S b/arch/arm/mach-bcm2835/include/mach/debug-macro.S
new file mode 100644
index 000000000000..8a161e44ae28
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/debug-macro.S
@@ -0,0 +1,21 @@
+/*
+ * Debugging macro include header
+ *
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/bcm2835_soc.h>
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =BCM2835_DEBUG_PHYS
+        ldr     \rv, =BCM2835_DEBUG_VIRT
+        .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-pnx4008/include/mach/param.h b/arch/arm/mach-bcm2835/include/mach/timex.h
index 6ea02f2176b7..6d021e136ae3 100644
--- a/arch/arm/mach-pnx4008/include/mach/param.h
+++ b/arch/arm/mach-bcm2835/include/mach/timex.h
@@ -1,7 +1,7 @@
 /*
- *  arch/arm/mach-pnx4008/include/mach/param.h
+ *  BCM2835 system clock frequency
  *
- *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2010 Broadcom
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,4 +18,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#define HZ 100
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE         (1000000)
+
+#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h
new file mode 100644
index 000000000000..cc46dcc72377
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/uncompress.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/amba/serial.h>
+#include <mach/bcm2835_soc.h>
+
+#define UART0_BASE BCM2835_DEBUG_PHYS
+
+#define BCM2835_UART_DR IOMEM(UART0_BASE + UART01x_DR)
+#define BCM2835_UART_FR IOMEM(UART0_BASE + UART01x_FR)
+#define BCM2835_UART_CR IOMEM(UART0_BASE + UART011_CR)
+
+static inline void putc(int c)
+{
+        while (__raw_readl(BCM2835_UART_FR) & UART01x_FR_TXFF)
+                barrier();
+
+        __raw_writel(c, BCM2835_UART_DR);
+}
+
+static inline void flush(void)
+{
+        int fr;
+
+        do {
+                fr = __raw_readl(BCM2835_UART_FR);
+                barrier();
+        } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 45c97b1ee9b1..c18a5048b6c5 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -29,7 +29,6 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
-#include <asm/pmu.h>
 
 #include <asm/mach/arch.h>
 #include <mach/dma.h>
@@ -38,7 +37,7 @@
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 
 #include "core.h"
 
@@ -116,7 +115,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
         .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
         .resource       = &pmu_resource,
         .num_resources  = 1,
 };
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index adbfb1994582..4b50228a6771 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -43,11 +43,10 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 
 #include "clock.h"
 
-#include <csp/secHw.h>
 #include <mach/csp/secHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 #include <mach/csp/tmrHw_reg.h>
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
index 96273ff34956..5050833817b7 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -26,15 +26,15 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/export.h>
 
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 
-#include <csp/reg.h>
-#include <csp/delay.h>
+#include <mach/csp/reg.h>
+#include <linux/delay.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 
@@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom)
 /****************************************************************************/
 chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
     ) {
-        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+        uint32_t __iomem *pPLLReg = NULL;
+        uint32_t __iomem *pClockCtrl = NULL;
+        uint32_t __iomem *pDependentClock = NULL;
         uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
         uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
         uint32_t dependentClockType = 0;
         uint32_t vcoHz = 0;
 
         /* Get VCO frequencies */
-        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+        if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
                 uint64_t adjustFreq = 0;
 
                 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                     chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
                 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configur
         } else {
                 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                     chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
         }
         vcoFreqPll2Hz =
             chipcHw_XTAL_FREQ_Hz *
                  chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+            ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
              chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
         switch (clock) {
@@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configur
 
         if (pPLLReg) {
                 /* Obtain PLL clock frequency */
-                if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
                         /* Return crystal clock frequency when bypassed */
                         return chipcHw_XTAL_FREQ_Hz;
                 } else if (clock == chipcHw_CLOCK_DDR) {
                         /* DDR frequency is configured in PLLDivider register */
-                        return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                        return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
                 } else {
                         /* From chip revision number B0, LCD clock is internally divided by 2 */
                         if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
                                 vcoHz >>= 1;
                         }
                         /* Obtain PLL clock frequency using VCO dividers */
-                        return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                        return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ?  (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
                 }
         } else if (pClockCtrl) {
                 /* Obtain divider clock frequency */
                 uint32_t div;
                 uint32_t freq = 0;
 
-                if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
                         /* Return crystal clock frequency when bypassed */
                         return chipcHw_XTAL_FREQ_Hz;
                 } else if (pDependentClock) {
                         /* Identify the dependent clock frequency */
                         switch (dependentClockType) {
                         case PLL_CLOCK:
-                                if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                                if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
                                         /* Use crystal clock frequency when dependent PLL clock is bypassed */
                                         freq = chipcHw_XTAL_FREQ_Hz;
                                 } else {
                                         /* Obtain PLL clock frequency using VCO dividers */
-                                        div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
+                                        div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
                                         freq = div ? chipcHw_divide(vcoHz, div) : 0;
                                 }
                                 break;
                         case NON_PLL_CLOCK:
-                                if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                if (pDependentClock == &pChipcHw->ACLKClock) {
                                         freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
                                 } else {
-                                        if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                                        if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
                                                 /* Use crystal clock frequency when dependent divider clock is bypassed */
                                                 freq = chipcHw_XTAL_FREQ_Hz;
                                         } else {
                                                 /* Obtain divider clock frequency using XTAL dividers */
-                                                div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                                div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                                                 freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
                                         }
                                 }
@@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configur
                         freq = chipcHw_XTAL_FREQ_Hz;
                 }
 
-                div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                 return chipcHw_divide(freq, (div ? div : 256));
         }
         return 0;
@@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configur
 chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
                                        uint32_t freq    /*  [ IN ] Clock frequency in Hz */
     ) {
-        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+        uint32_t __iomem *pPLLReg = NULL;
+        uint32_t __iomem *pClockCtrl = NULL;
+        uint32_t __iomem *pDependentClock = NULL;
         uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
         uint32_t desVcoFreqPll1Hz = 0;  /* Desired VCO frequency for PLL1 in Hz */
         uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
@@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
         uint32_t desVcoHz = 0;
 
         /* Get VCO frequencies */
-        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+        if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
                 uint64_t adjustFreq = 0;
 
                 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                     chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
                 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                 /* Desired VCO frequency */
                 desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                     chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                       chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
         } else {
                 vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                     chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
         }
         vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+            ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
              chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
         switch (clock) {
@@ -307,8 +307,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                 {
                         REG_LOCAL_IRQ_SAVE;
                         /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-                        pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                        writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock);
                         REG_LOCAL_IRQ_RESTORE;
                 }
                 pPLLReg = &pChipcHw->DDRClock;
@@ -329,8 +328,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                 /* Configure the VPM:BUS ratio settings */
                 {
                         REG_LOCAL_IRQ_SAVE;
-                        pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                        writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock);
                         REG_LOCAL_IRQ_RESTORE;
                 }
                 pPLLReg = &pChipcHw->VPMClock;
@@ -428,9 +426,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                 /* For DDR settings use only the PLL divider clock */
                 if (pPLLReg == &pChipcHw->DDRClock) {
                         /* Set M1DIV for PLL1, which controls the DDR clock */
-                        reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
+                        reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
                         /* Calculate expected frequency */
-                        freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                        freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
                 } else {
                         /* From chip revision number B0, LCD clock is internally divided by 2 */
                         if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
@@ -441,7 +439,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                         reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
                         reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
                         /* Calculate expected frequency */
-                        freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                        freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
                 }
                 /* Wait for for atleast 200ns as per the protocol to change frequency */
                 udelay(1);
@@ -460,16 +458,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                 if (pDependentClock) {
                         switch (dependentClockType) {
                         case PLL_CLOCK:
-                                divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
+                                divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
                                 break;
                         case NON_PLL_CLOCK:
                                 {
                                         uint32_t sourceClock = 0;
 
-                                        if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                        if (pDependentClock == &pChipcHw->ACLKClock) {
                                                 sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
                                         } else {
-                                                uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                                uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                                                 sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
                                         }
                                         divider = chipcHw_divide(sourceClock, freq);
@@ -483,7 +481,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configu
                 if (divider) {
                         REG_LOCAL_IRQ_SAVE;
                         /* Set the divider to obtain the required frequency */
-                        *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
+                        writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl);
                         REG_LOCAL_IRQ_RESTORE;
                         return freq;
                 }
@@ -515,25 +513,26 @@ static int vpmPhaseAlignA0(void)
         int count = 0;
 
         for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
-                phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
+                phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
                 phaseValue = 0;
                 prevPhaseComp = 0;
 
                 /* Step 1: Look for falling PH_COMP transition */
 
                 /* Read the contents of VPM Clock resgister */
-                phaseValue = pChipcHw->VPMClock;
+                phaseValue = readl(&pChipcHw->VPMClock);
                 do {
                         /* Store previous value of phase comparator */
                         prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
                         /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                         /* Wait atleast 20 ns */
                         udelay(1);
                         /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                         /* Read the contents of  VPM Clock resgister. */
-                        phaseValue = pChipcHw->VPMClock;
+                        phaseValue = readl(&pChipcHw->VPMClock);
 
                         if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
                                 phaseControl = (0x3F & (phaseControl - 1));
@@ -557,12 +556,13 @@ static int vpmPhaseAlignA0(void)
 
                 for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
                         phaseControl = (0x3F & (phaseControl + 1));
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                         /* Wait atleast 20 ns */
                         udelay(1);
                         /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                        phaseValue = pChipcHw->VPMClock;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+                        phaseValue = readl(&pChipcHw->VPMClock);
                         /* Count number of adjustment made */
                         adjustCount++;
                 }
@@ -581,12 +581,13 @@ static int vpmPhaseAlignA0(void)
 
                 for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
                         phaseControl = (0x3F & (phaseControl - 1));
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                         /* Wait atleast 20 ns */
                         udelay(1);
                         /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                        phaseValue = pChipcHw->VPMClock;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+                        phaseValue = readl(&pChipcHw->VPMClock);
                         /* Count number of adjustment made */
                         adjustCount++;
                 }
@@ -605,12 +606,13 @@ static int vpmPhaseAlignA0(void)
 
                 for (count = 0; (count < 5); count++) {
                         phaseControl = (0x3F & (phaseControl - 1));
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                         /* Wait atleast 20 ns */
                         udelay(1);
                         /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                        phaseValue = pChipcHw->VPMClock;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+                        phaseValue = readl(&pChipcHw->VPMClock);
                         /* Count number of adjustment made */
                         adjustCount++;
                 }
@@ -631,14 +633,14 @@ static int vpmPhaseAlignA0(void)
                         /* Store previous value of phase comparator */
                         prevPhaseComp = phaseValue;
                         /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                         /* Wait atleast 20 ns */
                         udelay(1);
                         /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^=
-                            chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                         /* Read the contents of  VPM Clock resgister. */
-                        phaseValue = pChipcHw->VPMClock;
+                        phaseValue = readl(&pChipcHw->VPMClock);
 
                         if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
                                 phaseControl = (0x3F & (phaseControl - 1));
@@ -661,13 +663,13 @@ static int vpmPhaseAlignA0(void)
         }
 
         /* For VPM Phase should be perfectly aligned. */
-        phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
+        phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
         {
                 REG_LOCAL_IRQ_SAVE;
 
-                pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
+                writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock);
                 /* Load new phase value */
-                pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
 
                 REG_LOCAL_IRQ_RESTORE;
         }
@@ -697,7 +699,7 @@ int chipcHw_vpmPhaseAlign(void)
                 int adjustCount = 0;
 
                 /* Disable VPM access */
-                pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
                 /* Disable HW VPM phase alignment  */
                 chipcHw_vpmHwPhaseAlignDisable();
                 /* Enable SW VPM phase alignment  */
@@ -715,23 +717,24 @@ int chipcHw_vpmPhaseAlign(void)
                                 phaseControl--;
                         } else {
                                 /* Enable VPM access */
-                                pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                                writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
                                 /* Return adjust count */
                                 return adjustCount;
                         }
                         /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        reg32_write(&pChipcHw->VPMClock,
+                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                         /* Wait atleast 20 ns */
                         udelay(1);
                         /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                         /* Count adjustment */
                         adjustCount++;
                 }
         }
 
         /* Disable VPM access */
-        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+        writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
         return -1;
 }
 
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
index 367df75d4bb3..8377d8054168 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -26,15 +26,15 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/export.h>
 
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 
-#include <csp/reg.h>
-#include <csp/delay.h>
+#include <mach/csp/reg.h>
+#include <linux/delay.h>
 /* ---- Private Constants and Types --------------------------------------- */
 
 /*
@@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
 
         {
                 REG_LOCAL_IRQ_SAVE;
-                pChipcHw->PLLConfig2 =
-                    chipcHw_REG_PLL_CONFIG_D_RESET |
-                    chipcHw_REG_PLL_CONFIG_A_RESET;
+                writel(chipcHw_REG_PLL_CONFIG_D_RESET |
+                       chipcHw_REG_PLL_CONFIG_A_RESET,
+                        &pChipcHw->PLLConfig2);
 
                 pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
@@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
                      chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
 
                 /* Enable CHIPC registers to control the PLL */
-                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+                writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
 
                 /* Set pre divider to get desired VCO frequency */
-                pChipcHw->PLLPreDivider2 = pllPreDivider2;
+                writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
                 /* Set NDIV Frac */
-                pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
+                writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
 
                 /* This has to be removed once the default values are fixed for PLL2. */
-                pChipcHw->PLLControl12 = 0x38000700;
-                pChipcHw->PLLControl22 = 0x00000015;
+                writel(0x38000700, &pChipcHw->PLLControl12);
+                writel(0x00000015, &pChipcHw->PLLControl22);
 
                 /* Reset PLL2 */
                 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                        writel(chipcHw_REG_PLL_CONFIG_D_RESET |
                             chipcHw_REG_PLL_CONFIG_A_RESET |
                             chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                            &pChipcHw->PLLConfig2);
                 } else {
-                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                        writel(chipcHw_REG_PLL_CONFIG_D_RESET |
                             chipcHw_REG_PLL_CONFIG_A_RESET |
                             chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                            &pChipcHw->PLLConfig2);
                 }
                 REG_LOCAL_IRQ_RESTORE;
         }
@@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
         {
                 REG_LOCAL_IRQ_SAVE;
                 /* Remove analog reset and Power on the PLL */
-                pChipcHw->PLLConfig2 &=
+                writel(readl(&pChipcHw->PLLConfig2) &
                     ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                      chipcHw_REG_PLL_CONFIG_POWER_DOWN),
+                      &pChipcHw->PLLConfig2);
 
                 REG_LOCAL_IRQ_RESTORE;
 
         }
 
         /* Wait until PLL is locked */
-        while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+        while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
                 ;
 
         {
                 REG_LOCAL_IRQ_SAVE;
                 /* Remove digital reset */
-                pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+                writel(readl(&pChipcHw->PLLConfig2) &
+                        ~chipcHw_REG_PLL_CONFIG_D_RESET,
+                        &pChipcHw->PLLConfig2);
 
                 REG_LOCAL_IRQ_RESTORE;
         }
@@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
         {
                 REG_LOCAL_IRQ_SAVE;
 
-                pChipcHw->PLLConfig =
-                    chipcHw_REG_PLL_CONFIG_D_RESET |
-                    chipcHw_REG_PLL_CONFIG_A_RESET;
+                writel(chipcHw_REG_PLL_CONFIG_D_RESET |
+                    chipcHw_REG_PLL_CONFIG_A_RESET,
+                    &pChipcHw->PLLConfig);
                 /* Setting VCO frequency */
                 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
                         pllPreDivider =
@@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
                 }
 
                 /* Enable CHIPC registers to control the PLL */
-                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+                writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
 
                 /* Set pre divider to get desired VCO frequency */
-                pChipcHw->PLLPreDivider = pllPreDivider;
+                writel(pllPreDivider, &pChipcHw->PLLPreDivider);
                 /* Set NDIV Frac */
                 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-                            chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
+                        writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
                 } else {
-                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-                            chipcHw_REG_PLL_DIVIDER_NDIV_f;
+                        writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
                 }
 
                 /* Reset PLL1 */
                 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                        writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
                 } else {
-                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                        writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
                 }
 
                 REG_LOCAL_IRQ_RESTORE;
@@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
                 {
                         REG_LOCAL_IRQ_SAVE;
                         /* Remove analog reset and Power on the PLL */
-                        pChipcHw->PLLConfig &=
-                            ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                              chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                        writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
                         REG_LOCAL_IRQ_RESTORE;
                 }
 
                 /* Wait until PLL is locked */
-                while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
-                       || !(pChipcHw->
-                            PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+                while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
+                       || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
                         ;
 
                 /* Remove digital reset */
                 {
                         REG_LOCAL_IRQ_SAVE;
-                        pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+                        writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
                         REG_LOCAL_IRQ_RESTORE;
                 }
         }
@@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip initializ
         chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
 
         /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
-        pChipcHw->ACLKClock =
-            (pChipcHw->
-             ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
-                                                                 armBusRatio &
-                                                                 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
+        writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
 
         /* Set various core component frequencies. The order in which this is done is important for some. */
         /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
index 2671d8896bbb..f95ce913fa1e 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -13,11 +13,11 @@
 *****************************************************************************/
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
-#include <csp/intcHw.h>
-#include <csp/cache.h>
+#include <mach/csp/intcHw_reg.h>
+#include <asm/cacheflush.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 /* ---- Private Variables ------------------------------------------------- */
@@ -50,17 +50,18 @@ void chipcHw_reset(uint32_t mask)
                         chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
                 }
                 /* Bypass the PLL clocks before reboot */
-                pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-                pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+                writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
+                        &pChipcHw->UARTClock);
+                writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
+                        &pChipcHw->SPIClock);
 
                 /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
                 do {
-                        ((uint32_t *) MM_IO_BASE_ARAM)[i] =
-                            ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
+                        writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
                         i++;
-                } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);  /* 0xe1a0f00f == asm ("mov r15, r15"); */
+                } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f);   /* 0xe1a0f00f == asm ("mov r15, r15"); */
 
-                CSP_CACHE_FLUSH_ALL;
+                flush_cache_all();
 
                 /* run the function from ARAM */
                 runFunc();
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
index 6b9be2e98e51..547f746c7ff4 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -25,11 +25,11 @@
 /****************************************************************************/
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/string.h>
-#include <stddef.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/stddef.h>
 
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
 #include <mach/csp/dmacHw_reg.h>
 #include <mach/csp/dmacHw_priv.h>
 #include <mach/csp/chipcHw_inline.h>
@@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel handl
     ) {
         uint32_t val = 0;
         dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_MISC_t *pMiscReg =
-            (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
+        dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);
 
         switch (pCblk->channel) {
         case 0:
-                val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
                 break;
         case 1:
-                val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
                 break;
         case 2:
-                val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
                 break;
         case 3:
-                val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
                 break;
         case 4:
-                val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
                 break;
         case 5:
-                val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
                 break;
         case 6:
-                val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
                 break;
         case 7:
-                val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
+                val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
                 break;
         }
 
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
index a1f328357aa4..fe438699d11e 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -26,10 +26,10 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/stdint.h>
-#include <stddef.h>
+#include <linux/types.h>
+#include <linux/stddef.h>
 
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
 #include <mach/csp/dmacHw_reg.h>
 #include <mach/csp/dmacHw_priv.h>
 
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
index 16225e43f3c3..dc4137ff75ca 100644
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
@@ -26,10 +26,10 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/errno.h>
-#include <csp/stdint.h>
+#include <linux/errno.h>
+#include <linux/types.h>
 
-#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw.h>
 #include <mach/csp/tmrHw_reg.h>
 
 #define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h
deleted file mode 100644
index f01da877148e..000000000000
--- a/arch/arm/mach-bcmring/include/cfg_global.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-
-#include <cfg_global_defines.h>
-
-#define CFG_GLOBAL_CHIP                         BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV                     0xB0
-#define CFG_GLOBAL_RAM_SIZE                     0x10000000
-#define CFG_GLOBAL_RAM_BASE                     0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
-
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
deleted file mode 100644
index caa20e59db99..000000000000
--- a/arch/arm/mach-bcmring/include/csp/cache.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_CACHE_H
-#define CSP_CACHE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <asm/cacheflush.h>
-
-#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
-
-#else
-
-#define CSP_CACHE_FLUSH_ALL
-
-#endif
-
-#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
deleted file mode 100644
index 8b3d80367293..000000000000
--- a/arch/arm/mach-bcmring/include/csp/delay.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_DELAY_H
-#define CSP_DELAY_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-/* Some CSP routines require use of the following delay routines. Use the OS */
-/* version if available, otherwise use a CSP specific definition. */
-/* void udelay(unsigned long usecs); */
-/* void mdelay(unsigned long msecs); */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-   #include <linux/delay.h>
-#else
-   #include <mach/csp/delay.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
deleted file mode 100644
index 51357dd5b666..000000000000
--- a/arch/arm/mach-bcmring/include/csp/errno.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_ERRNO_H
-#define CSP_ERRNO_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#if   defined(__KERNEL__)
-#include <linux/errno.h>
-#elif defined(CSP_SIMULATION)
-#include <asm-generic/errno.h>
-#else
-#include <errno.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
deleted file mode 100644
index 1c639c8ee08f..000000000000
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-/****************************************************************************/
-/**
-*  @file    intcHw.h
-*
-*  @brief   generic interrupt controller API
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_H
-#define _INTCHW_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask);
-static inline void intcHw_irq_enable(void *basep, uint32_t mask);
-
-#endif /* _INTCHW_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
deleted file mode 100644
index c30d2a5975a6..000000000000
--- a/arch/arm/mach-bcmring/include/csp/module.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_MODULE_H
-#define CSP_MODULE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-    #include <linux/module.h>
-#else
-    #define EXPORT_SYMBOL(symbol)
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h
deleted file mode 100644
index b9d7e0732dfc..000000000000
--- a/arch/arm/mach-bcmring/include/csp/secHw.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw.h
-*
-*  @brief   Definitions for accessing low level security features
-*
-*/
-/****************************************************************************/
-#ifndef SECHW_H
-#define SECHW_H
-
-typedef void (*secHw_FUNC_t) (void);
-
-typedef enum {
-        secHw_MODE_SECURE = 0x0,        /* Switches processor into secure mode */
-        secHw_MODE_NONSECURE = 0x1      /* Switches processor into non-secure mode */
-} secHw_MODE;
-
-/****************************************************************************/
-/**
-*  @brief   Requesting to execute the function in secure mode
-*
-*  This function requests the given function to run in secure mode
-*
-*/
-/****************************************************************************/
-void secHw_RunSecure(secHw_FUNC_t       /* Function to run in secure mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Sets the  mode
-*
-*  his function sets the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_SetMode(secHw_MODE   /* Processor mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get the current mode
-*
-*  This function retieves the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_GetMode(secHw_MODE *);
-
-#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
deleted file mode 100644
index 3a8718bbf700..000000000000
--- a/arch/arm/mach-bcmring/include/csp/stdint.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_STDINT_H
-#define CSP_STDINT_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
deleted file mode 100644
index ad9e4005f141..000000000000
--- a/arch/arm/mach-bcmring/include/csp/string.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-
-#ifndef CSP_STRING_H
-#define CSP_STRING_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-   #include <linux/string.h>
-#else
-   #include <string.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_STRING_H */
-
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/mach/cfg_global.h
index b5beb0b30734..449133eacdf5 100644
--- a/arch/arm/mach-bcmring/include/cfg_global_defines.h
+++ b/arch/arm/mach-bcmring/include/mach/cfg_global.h
@@ -38,3 +38,14 @@
 
 #define IMAGE_HEADER_SIZE_CHECKSUM    4
 #endif
+#ifndef _CFG_GLOBAL_H_
+#define _CFG_GLOBAL_H_
+
+#define CFG_GLOBAL_CHIP                         BCM11107
+#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
+#define CFG_GLOBAL_CHIP_REV                     0xB0
+#define CFG_GLOBAL_RAM_SIZE                     0x10000000
+#define CFG_GLOBAL_RAM_BASE                     0x00000000
+#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
+
+#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
index 933ce68ed90b..0a89e0c63419 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
@@ -17,7 +17,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <mach/csp/cap.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 #define CAP_CONFIG0_VPM_DIS          0x00000001
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
index 161973385faf..39f09cb89208 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
@@ -17,9 +17,9 @@
 
 /* ---- Include Files ----------------------------------------------------- */
 
-#include <csp/stdint.h>
-#include <csp/errno.h>
-#include <csp/reg.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/chipcHw_reg.h>
 
 /* ---- Public Constants and Types ---------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
index 03238c299001..a66f3f7abb86 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -17,8 +17,8 @@
 
 /* ---- Include Files ----------------------------------------------------- */
 
-#include <csp/errno.h>
-#include <csp/reg.h>
+#include <linux/errno.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/chipcHw_reg.h>
 #include <mach/csp/chipcHw_def.h>
 
@@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
 /****************************************************************************/
 static inline uint32_t chipcHw_getChipId(void)
 {
-        return pChipcHw->ChipId;
+        return readl(&pChipcHw->ChipId);
 }
 
 /****************************************************************************/
@@ -59,15 +59,16 @@ static inline uint32_t chipcHw_getChipId(void)
 /****************************************************************************/
 static inline void chipcHw_enableSpreadSpectrum(void)
 {
-        if ((pChipcHw->
-             PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
+        if ((readl(&pChipcHw->
+             PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
             chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-                ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
-                    (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
+                writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
                     (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-                     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
-                ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
-                    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
+                     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT),
+                     &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg);
+                writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) |
+                    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE,
+                    &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl);
         }
 }
 
@@ -93,8 +94,8 @@ static inline void chipcHw_disableSpreadSpectrum(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getChipProductId(void)
 {
-        return (pChipcHw->
-                 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
+        return (readl(&pChipcHw->
+                 ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >>
                 chipcHw_REG_CHIPID_BASE_SHIFT;
 }
 
@@ -109,7 +110,7 @@ static inline uint32_t chipcHw_getChipProductId(void)
 /****************************************************************************/
 static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
 {
-        return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
+        return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK;
 }
 
 /****************************************************************************/
@@ -156,7 +157,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
 {
-        return pChipcHw->BusIntfClock;
+        return readl(&pChipcHw->BusIntfClock);
 }
 
 /****************************************************************************/
@@ -215,8 +216,9 @@ static inline void chipcHw_softResetDisable(uint64_t mask)
 
         /* Deassert module soft reset */
         REG_LOCAL_IRQ_SAVE;
-        pChipcHw->SoftReset1 ^= ctrl1;
-        pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+        writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1);
+        writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 &
+                (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
         REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -227,9 +229,10 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
         uint32_t unhold = 0;
 
         REG_LOCAL_IRQ_SAVE;
-        pChipcHw->SoftReset1 |= ctrl1;
+        writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1);
         /* Mask out unhold request bits */
-        pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+        writel(readl(&pChipcHw->SoftReset2) | (ctrl2 &
+                (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
 
         /* Process unhold requests */
         if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
@@ -246,7 +249,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
 
         if (unhold) {
                 /* Make sure unhold request is effective */
-                pChipcHw->SoftReset1 &= ~unhold;
+                writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1);
         }
         REG_LOCAL_IRQ_RESTORE;
 }
@@ -307,7 +310,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getStickyBits(void)
 {
-        return pChipcHw->Sticky;
+        return readl(&pChipcHw->Sticky);
 }
 
 /****************************************************************************/
@@ -328,7 +331,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
                 bits |= chipcHw_REG_STICKY_POR_BROM;
         } else {
                 uint32_t sticky;
-                sticky = pChipcHw->Sticky;
+                sticky = readl(pChipcHw->Sticky);
 
                 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
                     && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
@@ -355,7 +358,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
                         bits |= chipcHw_REG_STICKY_GENERAL_5;
                 }
         }
-        pChipcHw->Sticky = bits;
+        writel(bits, pChipcHw->Sticky);
         REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -377,7 +380,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
             (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
              chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
              chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-                uint32_t sticky = pChipcHw->Sticky;
+                uint32_t sticky = readl(&pChipcHw->Sticky);
 
                 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
                     && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
@@ -410,7 +413,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
                         mask &= ~chipcHw_REG_STICKY_GENERAL_5;
                 }
         }
-        pChipcHw->Sticky = bits | mask;
+        writel(bits | mask, &pChipcHw->Sticky);
         REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -426,7 +429,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getSoftStraps(void)
 {
-        return pChipcHw->SoftStraps;
+        return readl(&pChipcHw->SoftStraps);
 }
 
 /****************************************************************************/
@@ -456,7 +459,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
 /****************************************************************************/
 static inline uint32_t chipcHw_getPinStraps(void)
 {
-        return pChipcHw->PinStraps;
+        return readl(&pChipcHw->PinStraps);
 }
 
 /****************************************************************************/
@@ -671,9 +674,9 @@ static inline void chipcHw_selectGE3(void)
 /****************************************************************************/
 static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
 {
-        return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
+        return (readl(chipcHw_REG_GPIO_MUX(pin))) &
                 (chipcHw_REG_GPIO_MUX_MASK <<
-                 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
+                 chipcHw_REG_GPIO_MUX_POSITION(pin)) >>
             chipcHw_REG_GPIO_MUX_POSITION(pin);
 }
 
@@ -841,8 +844,8 @@ static inline void chipcHw_setUsbDevice(void)
 static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
                                     chipcHw_OPTYPE_e type, int mode)
 {
-        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+        uint32_t __iomem *pPLLReg = NULL;
+        uint32_t __iomem *pClockCtrl = NULL;
 
         switch (clock) {
         case chipcHw_CLOCK_DDR:
@@ -1071,7 +1074,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
 /****************************************************************************/
 static inline int chipcHw_isSoftwareStrapsEnable(void)
 {
-        return pChipcHw->SoftStraps & 0x00000001;
+        return readl(&pChipcHw->SoftStraps) & 0x00000001;
 }
 
 /****************************************************************************/
@@ -1138,7 +1141,7 @@ static inline void chipcHw_pll2TestDisable(void)
 /****************************************************************************/
 static inline int chipcHw_isPllTestEnable(void)
 {
-        return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+        return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
 }
 
 /****************************************************************************/
@@ -1147,7 +1150,7 @@ static inline int chipcHw_isPllTestEnable(void)
 /****************************************************************************/
 static inline int chipcHw_isPll2TestEnable(void)
 {
-        return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+        return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
 }
 
 /****************************************************************************/
@@ -1183,8 +1186,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val)
 /****************************************************************************/
 static inline uint8_t chipcHw_getPllTestSelected(void)
 {
-        return (uint8_t) ((pChipcHw->
-                           PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+        return (uint8_t) ((readl(&pChipcHw->
+                           PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
                           >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
 }
 
@@ -1194,8 +1197,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void)
 /****************************************************************************/
 static inline uint8_t chipcHw_getPll2TestSelected(void)
 {
-        return (uint8_t) ((pChipcHw->
-                           PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+        return (uint8_t) ((readl(&pChipcHw->
+                           PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
                           >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
 }
 
@@ -1208,7 +1211,8 @@ static inline uint8_t chipcHw_getPll2TestSelected(void)
 static inline void chipcHw_pll1Disable(void)
 {
         REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+        writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                &pChipcHw->PLLConfig);
         REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1221,7 +1225,8 @@ static inline void chipcHw_pll1Disable(void)
 static inline void chipcHw_pll2Disable(void)
 {
         REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+        writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                &pChipcHw->PLLConfig2);
         REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1233,7 +1238,8 @@ static inline void chipcHw_pll2Disable(void)
 static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
 {
         REG_LOCAL_IRQ_SAVE;
-        pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+        writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+                &pChipcHw->Spare1);
         REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1245,7 +1251,8 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
 static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
 {
         REG_LOCAL_IRQ_SAVE;
-        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+        writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+                &pChipcHw->Spare1);
         REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1333,7 +1340,8 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void)
 static inline void chipcHw_vpmSwPhaseAlignEnable(void)
 {
         REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
+        writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE,
+                        &pChipcHw->VPMPhaseCtrl1);
         REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1372,7 +1380,8 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void)
 static inline void chipcHw_vpmHwPhaseAlignDisable(void)
 {
         REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
+        writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE,
+                &pChipcHw->VPMPhaseCtrl1);
         REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1474,8 +1483,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
 /****************************************************************************/
 static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
 {
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
+        return (readl(&pChipcHw->
+                PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
 }
 
 /****************************************************************************/
@@ -1488,8 +1497,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
 {
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
+        return (readl(&pChipcHw->
+                PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
 }
 
 /****************************************************************************/
@@ -1500,8 +1509,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
 {
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
+        return (readl(&pChipcHw->
+                PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
             chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
 }
 
@@ -1513,8 +1522,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
 {
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
+        return (readl(&pChipcHw->
+                PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
             chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
 }
 
@@ -1526,8 +1535,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getDdrPhaseControl(void)
 {
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
+        return (readl(&pChipcHw->
+                PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
             chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
 }
 
@@ -1539,8 +1548,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getVpmPhaseControl(void)
 {
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
+        return (readl(&pChipcHw->
+                PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
             chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
 }
 
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
index b162448f613c..26f5d0e4e1dd 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
@@ -24,7 +24,7 @@
 #define CHIPCHW_REG_H
 
 #include <mach/csp/mm_io.h>
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/ddrcReg.h>
 
 #define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
@@ -131,8 +131,8 @@ typedef struct {
         uint32_t MiscInput_0_15;        /* Input type for MISC 0 - 16 */
 } chipcHw_REG_t;
 
-#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
+#define pChipcHw  ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS)
+#define pChipcPhysical  (MM_ADDR_IO_CHIPC)
 
 #define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
 #define chipcHw_REG_CHIPID_BASE_SHIFT                   12
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
index f1b68e26fa6d..39da2c1fdafb 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
@@ -30,8 +30,8 @@ extern "C" {
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/reg.h>
-#include <csp/stdint.h>
+#include <mach/csp/reg.h>
+#include <linux/types.h>
 
 #include <mach/csp/mm_io.h>
 
@@ -416,7 +416,7 @@ extern "C" {
         } ddrcReg_PHY_ADDR_CTL_REG_t;
 
 #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
+#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
 
 /* @todo These SS definitions are duplicates of ones below */
 
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
index e6a1dc484ca7..9dc90f46a84d 100644
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
@@ -23,9 +23,9 @@
 #ifndef _DMACHW_H
 #define _DMACHW_H
 
-#include <stddef.h>
+#include <linux/stddef.h>
 
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/dmacHw_reg.h>
 
 /* Define DMA Channel ID using DMA controller number (m) and channel number (c).
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
index d67e2f8c22de..9d9455e0c391 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
@@ -24,7 +24,7 @@
 #ifndef _DMACHW_PRIV_H
 #define _DMACHW_PRIV_H
 
-#include <csp/stdint.h>
+#include <linux/types.h>
 
 /* Data type for DMA Link List Item */
 typedef struct {
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
index f1ecf96f2da5..7cd0aafa6f6e 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
@@ -24,7 +24,7 @@
 #ifndef _DMACHW_REG_H
 #define _DMACHW_REG_H
 
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/mm_io.h>
 
 /* Data type for 64 bit little endian register */
@@ -121,75 +121,75 @@ typedef struct {
 } dmacHw_MISC_t;
 
 /* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0       /* DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1       /* DMAC 1 module's base address */
+#define dmacHw_0_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA0        /* DMAC 0 module's base address */
+#define dmacHw_1_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA1        /* DMAC 1 module's base address */
 
 extern uint32_t dmaChannelCount_0;
 extern uint32_t dmaChannelCount_1;
 
 /* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
+#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
 
 /* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
+#define dmacHw_REG_INT_RAW_BASE(module)         ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
+#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
+#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
+#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
+#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
+#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
 
 /* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
+#define dmacHw_REG_INT_STAT_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
+#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
+#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
+#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
+#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
+#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
 
 /* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
+#define dmacHw_REG_INT_MASK_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
+#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
+#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
+#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
+#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
+#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
 
 /* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
+#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
+#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
+#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
+#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
+#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
+#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
+#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
 
 /* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
+#define dmacHw_REG_SW_HS_BASE(module)           ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
+#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
 
 /* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
+#define dmacHw_REG_MISC_BASE(module)            ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
+#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
+#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
+#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
+#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
+#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
+#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
+#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
+#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
+#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
+#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
+#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
+#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
+#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
+#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
 
 /* Channel control registers */
 #define dmacHw_REG_SAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
index cfa91bed9d34..27f59dd27792 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
@@ -18,7 +18,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #include <mach/csp/cap_inline.h>
 
 #if defined(__KERNEL__)
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
index 0aeb6a6fe7f8..f59db25b5632 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -27,8 +27,8 @@
 #define _INTCHW_REG_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/reg.h>
+#include <linux/types.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/mm_io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
@@ -37,9 +37,9 @@
 #define INTCHW_NUM_INTC           3
 
 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
-#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
+#define INTCHW_INTC0    (MM_IO_BASE_INTC0)
+#define INTCHW_INTC1    (MM_IO_BASE_INTC1)
+#define INTCHW_SINTC    (MM_IO_BASE_SINTC)
 
 /* INTC0 - interrupt controller 0 */
 #define INTCHW_INTC0_PIF_BITNUM           31    /* Peripheral interface interrupt */
@@ -232,15 +232,15 @@
 /* ---- Public Variable Externs ------------------------------------------ */
 /* ---- Public Function Prototypes --------------------------------------- */
 /* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
+static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask)
 {
-        __REG32(basep + INTCHW_INTENCLEAR) = mask;
+        writel(mask, basep + INTCHW_INTENCLEAR);
 }
 
 /* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
+static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask)
 {
-        __REG32(basep + INTCHW_INTENABLE) = mask;
+        writel(mask, basep + INTCHW_INTENABLE);
 }
 
 #endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
index ad58cf873377..d571962f2904 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
@@ -29,7 +29,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 
 #if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #endif
 
 /* ---- Public Constants and Types --------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
index de92ec6a01aa..47450c23685a 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
@@ -30,7 +30,7 @@
 #include <mach/csp/mm_addr.h>
 
 #if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #endif
 
 /* ---- Public Constants and Types --------------------------------------- */
@@ -49,7 +49,7 @@
 #ifdef __ASSEMBLY__
 #define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
 #else
-#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
+#define MM_IO_PHYS_TO_VIRT(phys)       (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
                         (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
 #endif
 #endif
@@ -60,8 +60,8 @@
 #ifdef __ASSEMBLY__
 #define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
 #else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-                        ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
+#define MM_IO_VIRT_TO_PHYS(virt)       (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
+                        ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF)))
 #endif
 #endif
 
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/mach/csp/reg.h
index 56654d23c3d7..d9cbdca8cd25 100644
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/reg.h
@@ -25,13 +25,14 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/stdint.h>
+#include <linux/types.h>
+#include <linux/io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
+#define __REG32(x)      (*((volatile uint32_t __iomem *)(x)))
+#define __REG16(x)      (*((volatile uint16_t __iomem *)(x)))
+#define __REG8(x)       (*((volatile uint8_t __iomem *) (x)))
 
 /* Macros used to define a sequence of reserved registers. The start / end */
 /* are byte offsets in the particular register definition, with the "end" */
@@ -84,31 +85,31 @@
 
 #endif
 
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value)
 {
         REG_LOCAL_IRQ_SAVE;
-        *reg &= value;
+        __raw_writel(__raw_readl(reg) & value, reg);
         REG_LOCAL_IRQ_RESTORE;
 }
 
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value)
 {
         REG_LOCAL_IRQ_SAVE;
-        *reg |= value;
+        __raw_writel(__raw_readl(reg) | value, reg);
         REG_LOCAL_IRQ_RESTORE;
 }
 
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
+static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask,
                                      uint32_t value)
 {
         REG_LOCAL_IRQ_SAVE;
-        *reg = (*reg & mask) | value;
+        __raw_writel((__raw_readl(reg) & mask) | value, reg);
         REG_LOCAL_IRQ_RESTORE;
 }
 
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value)
 {
-        *reg = value;
+        __raw_writel(value, reg);
 }
 
 #endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
index 9cd6a032ab71..55d3cd4fd1e7 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
@@ -34,7 +34,7 @@
 /****************************************************************************/
 static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
     ) {
-        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+        secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
 
         if (mask & 0x0000FFFF) {
                 regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
@@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask	/*  mask of type secHw_BLK_MASK
 /****************************************************************************/
 static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
     ) {
-        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+        secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
 
         if (mask & 0x0000FFFF) {
-                regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
+                writel(mask & 0x0000FFFF, &regp->reg[secHw_IDX_LS].setUnsecure);
         }
         if (mask & 0xFFFF0000) {
-                regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
+                writel(mask >> 16, &regp->reg[secHw_IDX_MS].setUnsecure);
         }
 }
 
@@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type secHw_BLK_MA
 /****************************************************************************/
 static inline uint32_t secHw_getStatus(void)
 {
-        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+        secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
 
         return (regp->reg[1].status << 16) + regp->reg[0].status;
 }
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
index 2cbb530db8ea..1cc882ae60f5 100644
--- a/arch/arm/mach-bcmring/include/csp/tmrHw.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
@@ -23,7 +23,7 @@
 #ifndef _TMRHW_H
 #define _TMRHW_H
 
-#include <csp/stdint.h>
+#include <linux/types.h>
 
 typedef uint32_t tmrHw_ID_t;    /* Timer ID */
 typedef uint32_t tmrHw_COUNT_t; /* Timer count */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
index 72543781207b..13e01384d6fc 100644
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ b/arch/arm/mach-bcmring/include/mach/dma.h
@@ -27,7 +27,7 @@
 
 #include <linux/kernel.h>
 #include <linux/semaphore.h>
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
 #include <mach/timer.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
index 6ae20a649a97..a0c92b4b8c60 100644
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ b/arch/arm/mach-bcmring/include/mach/hardware.h
@@ -22,7 +22,7 @@
 #define __ASM_ARCH_HARDWARE_H
 
 #include <asm/sizes.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #include <mach/csp/mm_io.h>
 
 /* Hardware addresses of major areas.
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h
index 387376ffb56b..f8d51a8b0b15 100644
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ b/arch/arm/mach-bcmring/include/mach/reg_nand.h
@@ -30,7 +30,7 @@
 #define __ASM_ARCH_REG_NAND_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/reg_umi.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
index 0992842caa77..56dd9de7d83f 100644
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h
@@ -30,7 +30,7 @@
 #define __ASM_ARCH_REG_UMI_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/mm_io.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
@@ -233,5 +233,5 @@
 #define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
 /* location within a page (512 byte) */
 #define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
+#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
 #endif
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 1adec78ec940..33824a81cac4 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -20,12 +20,12 @@
 #include <mach/hardware.h>
 #include <mach/csp/mm_io.h>
 
-#define IO_DESC(va, sz) { .virtual = va, \
+#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \
         .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
         .length = sz, \
         .type = MT_DEVICE }
 
-#define MEM_DESC(va, sz) { .virtual = va, \
+#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \
         .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
         .length = sz, \
         .type = MT_MEMORY }
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
index af9c3d7e2a0c..59412903466e 100644
--- a/arch/arm/mach-bcmring/timer.c
+++ b/arch/arm/mach-bcmring/timer.c
@@ -14,7 +14,7 @@
 
 #include <linux/types.h>
 #include <linux/module.h>
-#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw.h>
 
 #include <mach/timer.h>
 /* The core.c file initializes timers 1 and 3 as a linux clocksource. */
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index 1ce70a91f2e9..f091a9010c2f 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -15,7 +15,7 @@
 #include <linux/module.h>
 #include <linux/time.h>
 
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
 
 /* Timing value configuration */
 
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 0031864e7f11..95b5e102ceb1 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -28,11 +28,11 @@
 
 #include <mach/cp_intc.h>
 #include <mach/mux.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/da8xx.h>
-#include <mach/usb.h>
-#include <mach/aemif.h>
-#include <mach/spi.h>
+#include <linux/platform_data/usb-davinci.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
+#include <linux/platform_data/spi-davinci.h>
 
 #define DA830_EVM_PHY_ID                ""
 /*
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 0149fb453be3..1295e616ceee 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -40,10 +40,10 @@
 
 #include <mach/cp_intc.h>
 #include <mach/da8xx.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/mux.h>
-#include <mach/aemif.h>
-#include <mach/spi.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
+#include <linux/platform_data/spi-davinci.h>
 
 #define DA850_EVM_PHY_ID                "davinci_mdio-0:00"
 #define DA850_LCD_PWR_PIN               GPIO_TO_PIN(2, 8)
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 1c7b1f46a8f3..88ebea89abdf 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -26,11 +26,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
+#include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/mmc-davinci.h>
+#include <linux/platform_data/usb-davinci.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 8e7703213b08..2f88103c6459 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -23,11 +23,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
+#include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/mmc-davinci.h>
+#include <linux/platform_data/usb-davinci.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 688a9c556dc9..1b4a8adcfdc9 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -33,11 +33,11 @@
 
 #include <mach/mux.h>
 #include <mach/common.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
-#include <mach/mmc.h>
-#include <mach/nand.h>
-#include <mach/keyscan.h>
+#include <linux/platform_data/mmc-davinci.h>
+#include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/keyscan-davinci.h>
 
 #include <media/tvp514x.h>
 
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d34ed55912b2..ca72fc4b8cca 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -31,13 +31,13 @@
 #include <asm/mach/arch.h>
 
 #include <mach/common.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
 #include <mach/mux.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/mmc-davinci.h>
+#include <linux/platform_data/usb-davinci.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 958679a20e13..9944367b4931 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -38,11 +38,11 @@
 
 #include <mach/common.h>
 #include <mach/serial.h>
-#include <mach/i2c.h>
-#include <mach/nand.h>
+#include <linux/platform_data/i2c-davinci.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/clock.h>
 #include <mach/cdce949.h>
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index beecde3a1d2f..43e4a0d663fa 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -26,9 +26,9 @@
 #include <mach/common.h>
 #include <mach/cp_intc.h>
 #include <mach/da8xx.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/mux.h>
-#include <mach/spi.h>
+#include <linux/platform_data/spi-davinci.h>
 
 #define MITYOMAPL138_PHY_ID             ""
 
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index f6b9fc70161b..144bf31d68dd 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -31,12 +31,12 @@
 #include <asm/mach/arch.h>
 
 #include <mach/common.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
 #include <mach/mux.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
+#include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/mmc-davinci.h>
+#include <linux/platform_data/usb-davinci.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 9078acf94bac..6957787fa7f3 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -36,10 +36,10 @@
 #include <asm/mach/flash.h>
 
 #include <mach/common.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
 #include <mach/mux.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 8db0fc6809dd..a37fc44e29bc 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -24,7 +24,7 @@
 #include <linux/spi/spi.h>
 
 #include <mach/asp.h>
-#include <mach/keyscan.h>
+#include <linux/platform_data/keyscan-davinci.h>
 #include <mach/hardware.h>
 
 #include <media/davinci/vpfe_capture.h>
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index d2f9666284a7..3a42b6f79aa9 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -15,12 +15,12 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/irqs.h>
 #include <mach/cputype.h>
 #include <mach/mux.h>
 #include <mach/edma.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-davinci.h>
 #include <mach/time.h>
 
 #include "davinci.h"
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 678cd99b7336..adbde33eca01 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -27,7 +27,7 @@
 #include <mach/serial.h>
 #include <mach/common.h>
 #include <mach/asp.h>
-#include <mach/spi.h>
+#include <linux/platform_data/spi-davinci.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a50d49de1883..719e22f2a37e 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -30,8 +30,8 @@
 #include <mach/serial.h>
 #include <mach/common.h>
 #include <mach/asp.h>
-#include <mach/keyscan.h>
-#include <mach/spi.h>
+#include <linux/platform_data/keyscan-davinci.h>
+#include <linux/platform_data/spi-davinci.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index a2f1f274f189..33e78ae2a254 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -19,12 +19,12 @@
 
 #include <mach/serial.h>
 #include <mach/edma.h>
-#include <mach/i2c.h>
 #include <mach/asp.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
 #include <mach/pm.h>
-#include <mach/spi.h>
+#include <linux/platform_data/i2c-davinci.h>
+#include <linux/platform_data/mmc-davinci.h>
+#include <linux/platform_data/usb-davinci.h>
+#include <linux/platform_data/spi-davinci.h>
 
 extern void __iomem *da8xx_syscfg0_base;
 extern void __iomem *da8xx_syscfg1_base;
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 83e5926f3c46..1656a02e3eda 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -36,8 +36,8 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/mfd/ti_ssp.h>
 
-#include <mach/mmc.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mmc-davinci.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/serial.h>
 
 struct tnetv107x_device_info {
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 23d2b6d9fa63..f77b95336e2b 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -10,7 +10,7 @@
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/cputype.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
 
 #define DAVINCI_USB_OTG_BASE    0x01c64000
 
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index dd937c526a45..00154e74ce6b 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -15,6 +15,13 @@ config MACH_CM_A510
           Say 'Y' here if you want your kernel to support the
           CompuLab CM-A510 Board.
 
+config MACH_DOVE_DT
+        bool "Marvell Dove Flattened Device Tree"
+        select USE_OF
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Dove using flattened device tree.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index fa0f01856060..5e683baf96cf 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,4 @@
-obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
-
+obj-y                           += common.o addr-map.o irq.o mpp.o
+obj-$(CONFIG_PCI)               += pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
 obj-$(CONFIG_MACH_CM_A510)      += cm-a510.o
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 6321567d8eaa..b37bef1d5ffa 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,8 @@
 #include <linux/clk-provider.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -24,41 +26,30 @@
 #include <asm/mach/time.h>
 #include <asm/mach/pci.h>
 #include <mach/dove.h>
+#include <mach/pm.h>
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
 #include <plat/time.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
 #include "common.h"
 
-static int get_tclk(void);
-
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
 static struct map_desc dove_io_desc[] __initdata = {
         {
-                .virtual        = DOVE_SB_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
                 .length         = DOVE_SB_REGS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = DOVE_NB_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
                 .length         = DOVE_NB_REGS_SIZE,
                 .type           = MT_DEVICE,
-        }, {
-                .virtual        = DOVE_PCIE0_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
-                .length         = DOVE_PCIE0_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = DOVE_PCIE1_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
-                .length         = DOVE_PCIE1_IO_SIZE,
-                .type           = MT_DEVICE,
         },
 };
 
@@ -70,14 +61,69 @@ void __init dove_map_io(void)
 /*****************************************************************************
  * CLK tree
  ****************************************************************************/
+static int dove_tclk;
+
+static DEFINE_SPINLOCK(gating_lock);
 static struct clk *tclk;
 
-static void __init clk_init(void)
+static struct clk __init *dove_register_gate(const char *name,
+                                             const char *parent, u8 bit_idx)
 {
-        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
-                                       get_tclk());
+        return clk_register_gate(NULL, name, parent, 0,
+                                 (void __iomem *)CLOCK_GATING_CONTROL,
+                                 bit_idx, 0, &gating_lock);
+}
 
-        orion_clkdev_init(tclk);
+static void __init dove_clk_init(void)
+{
+        struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
+        struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
+        struct clk *xor0, *xor1, *ge, *gephy;
+
+        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
+                                       dove_tclk);
+
+        usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
+        usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
+        sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
+        pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
+        pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
+        sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
+        sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
+        nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
+        camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
+        i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
+        i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
+        crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
+        ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
+        pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
+        xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
+        xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
+        gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
+        ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
+
+        orion_clkdev_add(NULL, "orion_spi.0", tclk);
+        orion_clkdev_add(NULL, "orion_spi.1", tclk);
+        orion_clkdev_add(NULL, "orion_wdt", tclk);
+        orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
+
+        orion_clkdev_add(NULL, "orion-ehci.0", usb0);
+        orion_clkdev_add(NULL, "orion-ehci.1", usb1);
+        orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
+        orion_clkdev_add("0", "sata_mv.0", sata);
+        orion_clkdev_add("0", "pcie", pex0);
+        orion_clkdev_add("1", "pcie", pex1);
+        orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
+        orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
+        orion_clkdev_add(NULL, "orion_nand", nand);
+        orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
+        orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
+        orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
+        orion_clkdev_add(NULL, "mv_crypto", crypto);
+        orion_clkdev_add(NULL, "dove-ac97", ac97);
+        orion_clkdev_add(NULL, "dove-pdma", pdma);
+        orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
+        orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
 }
 
 /*****************************************************************************
@@ -188,16 +234,16 @@ void __init dove_init_early(void)
         orion_time_set_base(TIMER_VIRT_BASE);
 }
 
-static int get_tclk(void)
+static int __init dove_find_tclk(void)
 {
-        /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
         return 166666667;
 }
 
 static void __init dove_timer_init(void)
 {
+        dove_tclk = dove_find_tclk();
         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-                        IRQ_DOVE_BRIDGE, get_tclk());
+                        IRQ_DOVE_BRIDGE, dove_tclk);
 }
 
 struct sys_timer dove_timer = {
@@ -205,6 +251,15 @@ struct sys_timer dove_timer = {
 };
 
 /*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+void __init dove_crypto_init(void)
+{
+        orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
+                          DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
+}
+
+/*****************************************************************************
  * XOR 0
  ****************************************************************************/
 void __init dove_xor0_init(void)
@@ -285,16 +340,16 @@ void __init dove_sdio1_init(void)
 
 void __init dove_init(void)
 {
-        printk(KERN_INFO "Dove 88AP510 SoC, ");
-        printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
+        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+                (dove_tclk + 499999) / 1000000);
 
 #ifdef CONFIG_CACHE_TAUROS2
-        tauros2_init();
+        tauros2_init(0);
 #endif
         dove_setup_cpu_mbus();
 
         /* Setup root of clk tree */
-        clk_init();
+        dove_clk_init();
 
         /* internal devices that every board has */
         dove_rtc_init();
@@ -317,3 +372,67 @@ void dove_restart(char mode, const char *cmd)
         while (1)
                 ;
 }
+
+#if defined(CONFIG_MACH_DOVE_DT)
+/*
+ * Auxdata required until real OF clock provider
+ */
+struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
+        OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+        OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+                       NULL),
+        OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
+        OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
+        OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
+        {},
+};
+
+static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
+        .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+
+static void __init dove_dt_init(void)
+{
+        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+                (dove_tclk + 499999) / 1000000);
+
+#ifdef CONFIG_CACHE_TAUROS2
+        tauros2_init();
+#endif
+        dove_setup_cpu_mbus();
+
+        /* Setup root of clk tree */
+        dove_clk_init();
+
+        /* Internal devices not ported to DT yet */
+        dove_rtc_init();
+        dove_xor0_init();
+        dove_xor1_init();
+
+        dove_ge00_init(&dove_dt_ge00_data);
+        dove_ehci0_init();
+        dove_ehci1_init();
+        dove_pcie_init(1, 1);
+        dove_crypto_init();
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             dove_auxdata_lookup, NULL);
+}
+
+static const char * const dove_dt_board_compat[] = {
+        "marvell,dove",
+        NULL
+};
+
+DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+        .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
+        .init_irq       = orion_dt_init_irq,
+        .timer          = &dove_timer,
+        .init_machine   = dove_dt_init,
+        .restart        = dove_restart,
+        .dt_compat      = dove_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 6432a3ba864b..1a233404b735 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -26,7 +26,11 @@ void dove_init_irq(void);
 void dove_setup_cpu_mbus(void);
 void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void dove_sata_init(struct mv_sata_platform_data *sata_data);
+#ifdef CONFIG_PCI
 void dove_pcie_init(int init_port0, int init_port1);
+#else
+static inline void dove_pcie_init(int init_port0, int init_port1) { }
+#endif
 void dove_ehci0_init(void);
 void dove_ehci1_init(void);
 void dove_uart0_init(void);
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index f953bb54aa9d..99f259e8cf33 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -13,22 +13,22 @@
 
 #include <mach/dove.h>
 
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0000)
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0000)
 
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define  CPU_CTRL_PCIE0_LINK    0x00000001
 #define  CPU_RESET              0x00000002
 #define  CPU_CTRL_PCIE1_LINK    0x00000008
 
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define  SOFT_RESET_OUT_EN      0x00000004
 
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define  SOFT_RESET             0x00000001
 
 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF       0x0000
 #define IRQ_MASK_LOW_OFF        0x0004
 #define FIQ_MASK_LOW_OFF        0x0008
@@ -47,9 +47,9 @@
 #define ENDPOINT_MASK_HIGH      (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
 #define PCIE_INTERRUPT_MASK     (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
 
-#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE | 0x011c)
+#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE + 0x011c)
 
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
 #endif
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index d52b0ef313b7..661725e3115a 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -25,7 +25,7 @@
  */
 
 #define DOVE_CESA_PHYS_BASE             0xc8000000
-#define DOVE_CESA_VIRT_BASE             0xfdb00000
+#define DOVE_CESA_VIRT_BASE             IOMEM(0xfdb00000)
 #define DOVE_CESA_SIZE                  SZ_1M
 
 #define DOVE_PCIE0_MEM_PHYS_BASE        0xe0000000
@@ -38,101 +38,99 @@
 #define DOVE_BOOTROM_SIZE               SZ_128M
 
 #define DOVE_SCRATCHPAD_PHYS_BASE       0xf0000000
-#define DOVE_SCRATCHPAD_VIRT_BASE       0xfdd00000
+#define DOVE_SCRATCHPAD_VIRT_BASE       IOMEM(0xfdd00000)
 #define DOVE_SCRATCHPAD_SIZE            SZ_1M
 
 #define DOVE_SB_REGS_PHYS_BASE          0xf1000000
-#define DOVE_SB_REGS_VIRT_BASE          0xfde00000
+#define DOVE_SB_REGS_VIRT_BASE          IOMEM(0xfde00000)
 #define DOVE_SB_REGS_SIZE               SZ_8M
 
 #define DOVE_NB_REGS_PHYS_BASE          0xf1800000
-#define DOVE_NB_REGS_VIRT_BASE          0xfe600000
+#define DOVE_NB_REGS_VIRT_BASE          IOMEM(0xfe600000)
 #define DOVE_NB_REGS_SIZE               SZ_8M
 
 #define DOVE_PCIE0_IO_PHYS_BASE         0xf2000000
-#define DOVE_PCIE0_IO_VIRT_BASE         0xfee00000
 #define DOVE_PCIE0_IO_BUS_BASE          0x00000000
-#define DOVE_PCIE0_IO_SIZE              SZ_1M
+#define DOVE_PCIE0_IO_SIZE              SZ_64K
 
 #define DOVE_PCIE1_IO_PHYS_BASE         0xf2100000
-#define DOVE_PCIE1_IO_VIRT_BASE         0xfef00000
-#define DOVE_PCIE1_IO_BUS_BASE          0x00100000
-#define DOVE_PCIE1_IO_SIZE              SZ_1M
+#define DOVE_PCIE1_IO_BUS_BASE          0x00010000
+#define DOVE_PCIE1_IO_SIZE              SZ_64K
 
 /*
  * Dove Core Registers Map
  */
 
 /* SPI, I2C, UART */
-#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x11000)
-#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12000)
-#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12000)
-#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12100)
-#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12100)
-#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12200)
-#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12200)
-#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12300)
-#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12300)
-#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x10600)
-#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x14600)
+#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x11000)
+#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12000)
+#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12000)
+#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12100)
+#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12100)
+#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12200)
+#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12200)
+#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12300)
+#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12300)
+#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x10600)
+#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x14600)
 
 /* North-South Bridge */
-#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x20000)
-#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x20000)
+#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x20000)
+#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x20000)
 
 /* Cryptographic Engine */
-#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x30000)
 
 /* PCIe 0 */
-#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x40000)
+#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x40000)
 
 /* USB */
-#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x50000)
-#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x51000)
+#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x50000)
+#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x51000)
 
 /* XOR 0 Engine */
-#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60800)
-#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60800)
-#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
-#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
+#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60800)
+#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60800)
+#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
+#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
 
 /* XOR 1 Engine */
-#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60900)
-#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60900)
-#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
-#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
+#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60900)
+#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60900)
+#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
+#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
 
 /* Gigabit Ethernet */
-#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x70000)
+#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x70000)
 
 /* PCIe 1 */
-#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x80000)
+#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x80000)
 
 /* CAFE */
-#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x92000)
-#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x90000)
-#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x94000)
-#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
+#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x92000)
+#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x90000)
+#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x94000)
+#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
 
 /* SATA */
-#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
+#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
 
 /* I2S/SPDIF */
-#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
-#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
+#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
+#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
 
 /* NAND Flash Controller */
-#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
+#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
 
 /* MPP, GPIO, Reset Sampling */
-#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
-#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
-#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
-#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
-#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
-#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
-#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE + 0x014)
+#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE + 0x018)
+#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
+#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
+#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
+#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
 #define  DOVE_NAND_GPIO_EN              (1 << 0)
 #define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -144,44 +142,44 @@
 #define  DOVE_SD0_GPIO_SEL              (1 << 0)
 
 /* Power Management */
-#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
+#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
 #define DOVE_PMU_SIG_CTRL       (DOVE_PMU_VIRT_BASE + 0x802c)
 
 /* Real Time Clock */
-#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
+#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
 
 /* AC97 */
-#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
-#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
+#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
+#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
 
 /* Peripheral DMA */
-#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
-#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
+#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
+#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
 
-#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
 #define  DOVE_TWSI_ENABLE_OPTION1       (1 << 7)
-#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
 #define  DOVE_TWSI_ENABLE_OPTION2       (1 << 20)
 #define  DOVE_TWSI_ENABLE_OPTION3       (1 << 21)
 #define  DOVE_TWSI_OPTION3_GPIO         (1 << 22)
-#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xec000)
-#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xec000)
+#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
 #define  DOVE_SSP_ON_AU1                (1 << 0)
 #define  DOVE_SSP_CLOCK_ENABLE          (1 << 1)
 #define  DOVE_SSP_BPB_CLOCK_SRC_SSP     (1 << 11)
 /* Memory Controller */
-#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE | 0x00000)
+#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE + 0x00000)
 
 /* LCD Controller */
-#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x10000)
-#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x20000)
-#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x10000)
-#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x10000)
+#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x20000)
+#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x10000)
+#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
 
 /* Graphic Engine */
-#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x40000)
+#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x40000)
 
 /* Video Engine */
-#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x400000)
+#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x400000)
 
 #endif
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
deleted file mode 100644
index e7e5101e35a5..000000000000
--- a/arch/arm/mach-dove/include/mach/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
deleted file mode 100644
index 29c8b85355a5..000000000000
--- a/arch/arm/mach-dove/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "dove.h"
-
-#define IO_SPACE_LIMIT          0xffffffff
-
-#define __io(a)         ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
-                                                 DOVE_PCIE0_IO_VIRT_BASE))
-
-#endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 3ad9f946a9e8..7bcd0dfce4b1 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
 #include <mach/irqs.h>
 
 #define CLOCK_GATING_CONTROL    (DOVE_PMU_VIRT_BASE + 0x38)
-#define  CLOCK_GATING_USB0_MASK         (1 << 0)
-#define  CLOCK_GATING_USB1_MASK         (1 << 1)
-#define  CLOCK_GATING_GBE_MASK          (1 << 2)
-#define  CLOCK_GATING_SATA_MASK         (1 << 3)
-#define  CLOCK_GATING_PCIE0_MASK        (1 << 4)
-#define  CLOCK_GATING_PCIE1_MASK        (1 << 5)
-#define  CLOCK_GATING_SDIO0_MASK        (1 << 8)
-#define  CLOCK_GATING_SDIO1_MASK        (1 << 9)
-#define  CLOCK_GATING_NAND_MASK         (1 << 10)
-#define  CLOCK_GATING_CAMERA_MASK       (1 << 11)
-#define  CLOCK_GATING_I2S0_MASK         (1 << 12)
-#define  CLOCK_GATING_I2S1_MASK         (1 << 13)
-#define  CLOCK_GATING_CRYPTO_MASK       (1 << 15)
-#define  CLOCK_GATING_AC97_MASK         (1 << 21)
-#define  CLOCK_GATING_PDMA_MASK         (1 << 22)
-#define  CLOCK_GATING_XOR0_MASK         (1 << 23)
-#define  CLOCK_GATING_XOR1_MASK         (1 << 24)
-#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << 30)
+#define  CLOCK_GATING_BIT_USB0          0
+#define  CLOCK_GATING_BIT_USB1          1
+#define  CLOCK_GATING_BIT_GBE           2
+#define  CLOCK_GATING_BIT_SATA          3
+#define  CLOCK_GATING_BIT_PCIE0         4
+#define  CLOCK_GATING_BIT_PCIE1         5
+#define  CLOCK_GATING_BIT_SDIO0         8
+#define  CLOCK_GATING_BIT_SDIO1         9
+#define  CLOCK_GATING_BIT_NAND          10
+#define  CLOCK_GATING_BIT_CAMERA        11
+#define  CLOCK_GATING_BIT_I2S0          12
+#define  CLOCK_GATING_BIT_I2S1          13
+#define  CLOCK_GATING_BIT_CRYPTO        15
+#define  CLOCK_GATING_BIT_AC97          21
+#define  CLOCK_GATING_BIT_PDMA          22
+#define  CLOCK_GATING_BIT_XOR0          23
+#define  CLOCK_GATING_BIT_XOR1          24
+#define  CLOCK_GATING_BIT_GIGA_PHY      30
+#define  CLOCK_GATING_USB0_MASK         (1 << CLOCK_GATING_BIT_USB0)
+#define  CLOCK_GATING_USB1_MASK         (1 << CLOCK_GATING_BIT_USB1)
+#define  CLOCK_GATING_GBE_MASK          (1 << CLOCK_GATING_BIT_GBE)
+#define  CLOCK_GATING_SATA_MASK         (1 << CLOCK_GATING_BIT_SATA)
+#define  CLOCK_GATING_PCIE0_MASK        (1 << CLOCK_GATING_BIT_PCIE0)
+#define  CLOCK_GATING_PCIE1_MASK        (1 << CLOCK_GATING_BIT_PCIE1)
+#define  CLOCK_GATING_SDIO0_MASK        (1 << CLOCK_GATING_BIT_SDIO0)
+#define  CLOCK_GATING_SDIO1_MASK        (1 << CLOCK_GATING_BIT_SDIO1)
+#define  CLOCK_GATING_NAND_MASK         (1 << CLOCK_GATING_BIT_NAND)
+#define  CLOCK_GATING_CAMERA_MASK       (1 << CLOCK_GATING_BIT_CAMERA)
+#define  CLOCK_GATING_I2S0_MASK         (1 << CLOCK_GATING_BIT_I2S0)
+#define  CLOCK_GATING_I2S1_MASK         (1 << CLOCK_GATING_BIT_I2S1)
+#define  CLOCK_GATING_CRYPTO_MASK       (1 << CLOCK_GATING_BIT_CRYPTO)
+#define  CLOCK_GATING_AC97_MASK         (1 << CLOCK_GATING_BIT_AC97)
+#define  CLOCK_GATING_PDMA_MASK         (1 << CLOCK_GATING_BIT_PDMA)
+#define  CLOCK_GATING_XOR0_MASK         (1 << CLOCK_GATING_BIT_XOR0)
+#define  CLOCK_GATING_XOR1_MASK         (1 << CLOCK_GATING_BIT_XOR1)
+#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << CLOCK_GATING_BIT_GIGA_PHY)
 
 #define PMU_INTERRUPT_CAUSE     (DOVE_PMU_VIRT_BASE + 0x50)
 #define PMU_INTERRUPT_MASK      (DOVE_PMU_VIRT_BASE + 0x54)
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 9bc97a5baaa8..087711524e8a 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -18,6 +18,7 @@
 #include <asm/mach/irq.h>
 #include <mach/pm.h>
 #include <mach/bridge-regs.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 
 static void pmu_irq_mask(struct irq_data *d)
@@ -99,19 +100,19 @@ void __init dove_init_irq(void)
 {
         int i;
 
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
         /*
          * Initialize gpiolib for GPIOs 0-71.
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START, gpio0_irqs);
 
-        orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
 
-        orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
 
         /*
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 7f70afc26f91..60bd729a1ba5 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <plat/mpp.h>
 #include <mach/dove.h>
+#include <plat/orion-gpio.h>
 #include "mpp.h"
 
 struct dove_mpp_grp {
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 47921b0cdc65..bb15b26041cb 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -26,9 +26,8 @@ struct pcie_port {
         u8                      root_bus_nr;
         void __iomem            *base;
         spinlock_t              conf_lock;
-        char                    io_space_name[16];
         char                    mem_space_name[16];
-        struct resource         res[2];
+        struct resource         res;
 };
 
 static struct pcie_port pcie_port[2];
@@ -53,24 +52,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
 
         orion_pcie_setup(pp->base);
 
-        /*
-         * IORESOURCE_IO
-         */
-        snprintf(pp->io_space_name, sizeof(pp->io_space_name),
-                 "PCIe %d I/O", pp->index);
-        pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
-        pp->res[0].name = pp->io_space_name;
-        if (pp->index == 0) {
-                pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
-                pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
-        } else {
-                pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
-                pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
-        }
-        pp->res[0].flags = IORESOURCE_IO;
-        if (request_resource(&ioport_resource, &pp->res[0]))
-                panic("Request PCIe IO resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+        if (pp->index == 0)
+                pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
+        else
+                pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
 
         /*
          * IORESOURCE_MEM
@@ -78,18 +63,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
         snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                  "PCIe %d MEM", pp->index);
         pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-        pp->res[1].name = pp->mem_space_name;
+        pp->res.name = pp->mem_space_name;
         if (pp->index == 0) {
-                pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
-                pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
+                pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
+                pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
         } else {
-                pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
-                pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
+                pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
+                pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
         }
-        pp->res[1].flags = IORESOURCE_MEM;
-        if (request_resource(&iomem_resource, &pp->res[1]))
+        pp->res.flags = IORESOURCE_MEM;
+        if (request_resource(&iomem_resource, &pp->res))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
 
         return 1;
 }
@@ -197,20 +182,20 @@ static struct hw_pci dove_pci __initdata = {
         .map_irq        = dove_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
         printk(KERN_INFO "Dove PCIe port %d: ", index);
 
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
 
                 printk(KERN_INFO "link up\n");
 
                 pp->index = index;
                 pp->root_bus_nr = -1;
-                pp->base = (void __iomem *)base;
+                pp->base = base;
                 spin_lock_init(&pp->conf_lock);
-                memset(pp->res, 0, sizeof(pp->res));
+                memset(&pp->res, 0, sizeof(pp->res));
         } else {
                 printk(KERN_INFO "link down, ignoring\n");
         }
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 6f8068692edf..f0fe6b5350e2 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -74,22 +74,22 @@ static struct map_desc ebsa110_io_desc[] __initdata = {
          * sparse external-decode ISAIO space
          */
         {       /* IRQ_STAT/IRQ_MCLR */
-                .virtual        = IRQ_STAT,
+                .virtual        = (unsigned long)IRQ_STAT,
                 .pfn            = __phys_to_pfn(TRICK4_PHYS),
                 .length         = TRICK4_SIZE,
                 .type           = MT_DEVICE
         }, {    /* IRQ_MASK/IRQ_MSET */
-                .virtual        = IRQ_MASK,
+                .virtual        = (unsigned long)IRQ_MASK,
                 .pfn            = __phys_to_pfn(TRICK3_PHYS),
                 .length         = TRICK3_SIZE,
                 .type           = MT_DEVICE
         }, {    /* SOFT_BASE */
-                .virtual        = SOFT_BASE,
+                .virtual        = (unsigned long)SOFT_BASE,
                 .pfn            = __phys_to_pfn(TRICK1_PHYS),
                 .length         = TRICK1_SIZE,
                 .type           = MT_DEVICE
         }, {    /* PIT_BASE */
-                .virtual        = PIT_BASE,
+                .virtual        = (unsigned long)PIT_BASE,
                 .pfn            = __phys_to_pfn(TRICK0_PHYS),
                 .length         = TRICK0_SIZE,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-ebsa110/core.h b/arch/arm/mach-ebsa110/core.h
index c93c9e43012d..afe137ee172e 100644
--- a/arch/arm/mach-ebsa110/core.h
+++ b/arch/arm/mach-ebsa110/core.h
@@ -31,11 +31,11 @@
 #define TRICK7_PHYS             0xf3c00000
 
 /* Virtual addresses */
-#define PIT_BASE                0xfc000000      /* trick 0 */
-#define SOFT_BASE               0xfd000000      /* trick 1 */
-#define IRQ_MASK                0xfe000000      /* trick 3 - read */
-#define IRQ_MSET                0xfe000000      /* trick 3 - write */
-#define IRQ_STAT                0xff000000      /* trick 4 - read */
-#define IRQ_MCLR                0xff000000      /* trick 4 - write */
+#define PIT_BASE                IOMEM(0xfc000000)       /* trick 0 */
+#define SOFT_BASE               IOMEM(0xfd000000)       /* trick 1 */
+#define IRQ_MASK                IOMEM(0xfe000000)       /* trick 3 - read */
+#define IRQ_MSET                IOMEM(0xfe000000)       /* trick 3 - write */
+#define IRQ_STAT                IOMEM(0xff000000)       /* trick 4 - read */
+#define IRQ_MCLR                IOMEM(0xff000000)       /* trick 4 - write */
 
 #endif
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 4afe52aaaff3..e85bf17f2d2a 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -36,9 +36,9 @@
 #include <linux/export.h>
 
 #include <mach/hardware.h>
-#include <mach/fb.h>
-#include <mach/ep93xx_keypad.h>
-#include <mach/ep93xx_spi.h>
+#include <linux/platform_data/video-ep93xx.h>
+#include <linux/platform_data/keypad-ep93xx.h>
+#include <linux/platform_data/spi-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
index 16976d7bdc8a..d8bfd02f5047 100644
--- a/arch/arm/mach-ep93xx/dma.c
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -25,7 +25,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
-#include <mach/dma.h>
+#include <linux/platform_data/dma-ep93xx.h>
 #include <mach/hardware.h>
 
 #include "soc.h"
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 337ab7cf4c16..b8f53d57a299 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -35,8 +35,8 @@
 #include <sound/cs4271.h>
 
 #include <mach/hardware.h>
-#include <mach/fb.h>
-#include <mach/ep93xx_spi.h>
+#include <linux/platform_data/video-ep93xx.h>
+#include <linux/platform_data/spi-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 
 #include <asm/hardware/vic.h>
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 33dc07917417..0eb3f17a6fa2 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -22,7 +22,7 @@
 #include <linux/i2c-gpio.h>
 
 #include <mach/hardware.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 
 #include <asm/hardware/vic.h>
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 01abd3516a77..50043eef1cf2 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -28,7 +28,7 @@
 #include <linux/mtd/nand.h>
 
 #include <mach/hardware.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 
 #include <asm/hardware/vic.h>
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index 2905a4929bdc..ba92e25e3016 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -30,8 +30,8 @@
 #include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
-#include <mach/fb.h>
-#include <mach/ep93xx_spi.h>
+#include <linux/platform_data/video-ep93xx.h>
+#include <linux/platform_data/spi-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 
 #include <asm/hardware/vic.h>
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
index 31bd181b0514..b9862e22bf10 100644
--- a/arch/arm/mach-exynos/Makefile.boot
+++ b/arch/arm/mach-exynos/Makefile.boot
@@ -1,5 +1,2 @@
    zreladdr-y   += 0x40008000
 params_phys-y   := 0x40000100
-
-dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
-dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c67066..3b00e299b624 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 }
 
-static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
-}
-
 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -672,10 +667,6 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
-                .name           = "gps",
-                .enable         = exynos5_clk_ip_gps_ctrl,
-                .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
-        }, {
                 .name           = "nfcon",
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 22),
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index aed2eeb06517..dac146df79ac 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -14,6 +14,7 @@
 
 extern struct sys_timer exynos4_timer;
 
+struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 void exynos5_init_irq(void);
@@ -59,4 +60,8 @@ void exynos4212_register_clocks(void);
 #define exynos4212_register_clocks()
 #endif
 
+extern struct smp_operations exynos_smp_ops;
+
+extern void exynos_cpu_die(unsigned int cpu);
+
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index b33a5b67b547..ae321c7cb15f 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -16,7 +16,7 @@
 #include <linux/gpio.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 
 #include <mach/map.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
index b8e75300c77d..14ed7951a2c6 100644
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ b/arch/arm/mach-exynos/dev-ohci.c
@@ -15,7 +15,7 @@
 
 #include <mach/irqs.h>
 #include <mach/map.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-exynos.h>
 
 #include <plat/devs.h>
 #include <plat/usb-phy.h>
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 9c17a0a43858..f4d7dd20cdac 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -21,7 +21,7 @@
 
 #include <mach/regs-pmu.h>
 
-extern volatile int pen_release;
+#include "common.h"
 
 static inline void cpu_enter_lowpower(void)
 {
@@ -95,17 +95,12 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
         }
 }
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
  * Called with IRQs disabled
  */
-void platform_cpu_die(unsigned int cpu)
+void __ref exynos_cpu_die(unsigned int cpu)
 {
         int spurious = 0;
 
@@ -124,12 +119,3 @@ void platform_cpu_die(unsigned int cpu)
         if (spurious)
                 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675b3e4b..9d1f3ac86db2 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -131,7 +131,6 @@
 #define EXYNOS5_PA_SYSMMU_JPEG          0x11F20000
 #define EXYNOS5_PA_SYSMMU_IOP           0x12360000
 #define EXYNOS5_PA_SYSMMU_RTIC          0x12370000
-#define EXYNOS5_PA_SYSMMU_GPS           0x12630000
 #define EXYNOS5_PA_SYSMMU_ISP           0x13260000
 #define EXYNOS5_PA_SYSMMU_DRC           0x12370000
 #define EXYNOS5_PA_SYSMMU_SCALERC       0x13280000
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 5a3daa0168d8..3f37a5e8a1f4 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -199,6 +199,7 @@ static void __init armlex4210_machine_init(void)
 MACHINE_START(ARMLEX4210, "ARMLEX4210")
         /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
         .init_irq       = exynos4_init_irq,
         .map_io         = armlex4210_map_io,
         .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc2318f..8833060f77e9 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -79,6 +79,7 @@ static char const *exynos5250_dt_compat[] __initdata = {
 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         .init_irq       = exynos5_init_irq,
+        .smp            = smp_ops(exynos_smp_ops),
         .map_io         = exynos5250_dt_map_io,
         .handle_irq     = gic_handle_irq,
         .init_machine   = exynos5250_dt_machine_init,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index ea785fcaf6c3..480cd78f1920 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -45,14 +45,14 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
-#include <plat/ehci.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/clock.h>
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/mfc.h>
 #include <plat/fimc-core.h>
 #include <plat/camport.h>
-#include <plat/mipi_csis.h>
+#include <linux/platform_data/mipi-csis.h>
 
 #include <mach/map.h>
 
@@ -1383,6 +1383,7 @@ static void __init nuri_machine_init(void)
 MACHINE_START(NURI, "NURI")
         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
         .init_irq       = exynos4_init_irq,
         .map_io         = nuri_map_io,
         .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 4e574c24581c..fc23f74ade81 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -35,8 +35,8 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
-#include <plat/iic.h>
-#include <plat/ehci.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/clock.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
@@ -44,7 +44,7 @@
 #include <plat/mfc.h>
 #include <plat/hdmi.h>
 
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-exynos.h>
 #include <mach/map.h>
 
 #include <drm/exynos_drm.h>
@@ -806,6 +806,7 @@ static void __init origen_machine_init(void)
 MACHINE_START(ORIGEN, "ORIGEN")
         /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
         .init_irq       = exynos4_init_irq,
         .map_io         = origen_map_io,
         .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index b26beb13ebef..589f1db140f0 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -32,7 +32,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/mfc.h>
 #include <plat/regs-fb.h>
@@ -370,6 +370,7 @@ static void __init smdk4x12_machine_init(void)
 MACHINE_START(SMDK4212, "SMDK4212")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
         .init_irq       = exynos4_init_irq,
         .map_io         = smdk4x12_map_io,
         .handle_irq     = gic_handle_irq,
@@ -383,6 +384,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
         .init_irq       = exynos4_init_irq,
         .map_io         = smdk4x12_map_io,
         .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 73f2bce097e1..6e52cbd0b3e0 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -34,16 +34,16 @@
 #include <plat/fb.h>
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
-#include <plat/ehci.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/clock.h>
 #include <plat/hdmi.h>
 
 #include <mach/map.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-exynos.h>
 
 #include <drm/exynos_drm.h>
 #include "common.h"
@@ -417,6 +417,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .handle_irq     = gic_handle_irq,
@@ -429,6 +430,7 @@ MACHINE_END
 MACHINE_START(SMDKC210, "SMDKC210")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 4d1f40d44ed1..98d3aced2289 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -34,7 +34,7 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/fb.h>
 #include <plat/mfc.h>
@@ -43,7 +43,7 @@
 #include <plat/fimc-core.h>
 #include <plat/s5p-time.h>
 #include <plat/camport.h>
-#include <plat/mipi_csis.h>
+#include <linux/platform_data/mipi-csis.h>
 
 #include <mach/map.h>
 
@@ -1155,6 +1155,7 @@ static void __init universal_machine_init(void)
 MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
         .init_irq       = exynos4_init_irq,
         .map_io         = universal_map_io,
         .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984aaa47..8d57e4223bdb 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,19 +32,14 @@
 
 #include <plat/cpu.h>
 
+#include "common.h"
+
 extern void exynos4_secondary_startup(void);
 
 #define CPU1_BOOT_REG           (samsung_rev() == EXYNOS4210_REV_1_1 ? \
                                 S5P_INFORM5 : S5P_VA_SYSRAM)
 
 /*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-
-volatile int __cpuinitdata pen_release = -1;
-
-/*
  * Write pen_release in a way that is guaranteed to be visible to all
  * observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
@@ -64,7 +59,7 @@ static void __iomem *scu_base_addr(void)
 
 static DEFINE_SPINLOCK(boot_lock);
 
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit exynos_secondary_init(unsigned int cpu)
 {
         /*
          * if any interrupts are already enabled for the primary
@@ -86,7 +81,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         spin_unlock(&boot_lock);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned long timeout;
 
@@ -161,7 +156,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  * which may be present or become present in the system.
  */
 
-void __init smp_init_cpus(void)
+static void __init exynos_smp_init_cpus(void)
 {
         void __iomem *scu_base = scu_base_addr();
         unsigned int i, ncores;
@@ -184,7 +179,7 @@ void __init smp_init_cpus(void)
         set_smp_cross_call(gic_raise_softirq);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 {
         if (!soc_is_exynos5250())
                 scu_enable(scu_base_addr());
@@ -198,3 +193,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
         __raw_writel(virt_to_phys(exynos4_secondary_startup),
                         CPU1_BOOT_REG);
 }
+
+struct smp_operations exynos_smp_ops __initdata = {
+        .smp_init_cpus          = exynos_smp_init_cpus,
+        .smp_prepare_cpus       = exynos_smp_prepare_cpus,
+        .smp_secondary_init     = exynos_secondary_init,
+        .smp_boot_secondary     = exynos_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = exynos_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index b90d94c17f7c..5700f23629f7 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -14,7 +14,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c
index fd7235a43f6e..8d2279cc85dc 100644
--- a/arch/arm/mach-exynos/setup-i2c1.c
+++ b/arch/arm/mach-exynos/setup-i2c1.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c
index 2694b19e8b37..0ed62fc42a77 100644
--- a/arch/arm/mach-exynos/setup-i2c2.c
+++ b/arch/arm/mach-exynos/setup-i2c2.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c2_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c
index 379bd306993f..7787fd26076b 100644
--- a/arch/arm/mach-exynos/setup-i2c3.c
+++ b/arch/arm/mach-exynos/setup-i2c3.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c3_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c
index 9f3c04855b76..edc847f89826 100644
--- a/arch/arm/mach-exynos/setup-i2c4.c
+++ b/arch/arm/mach-exynos/setup-i2c4.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c4_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c
index 77e1a1e57c76..d88af7f75954 100644
--- a/arch/arm/mach-exynos/setup-i2c5.c
+++ b/arch/arm/mach-exynos/setup-i2c5.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c5_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c
index 284d12b7af0e..c590286c9d3a 100644
--- a/arch/arm/mach-exynos/setup-i2c6.c
+++ b/arch/arm/mach-exynos/setup-i2c6.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c6_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c
index b7611ee359a2..1bba75568a5f 100644
--- a/arch/arm/mach-exynos/setup-i2c7.c
+++ b/arch/arm/mach-exynos/setup-i2c7.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c7_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 3e6aaa6361da..a42b369bc439 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
- 
+
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/irq.h>
@@ -26,6 +26,7 @@
 
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 
 #include "common.h"
 
@@ -175,11 +176,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(DC21285_PCI_IACK),
                 .length         = PCIIACK_SIZE,
                 .type           = MT_DEVICE,
-        }, {
-                .virtual        = PCIO_BASE,
-                .pfn            = __phys_to_pfn(DC21285_PCI_IO),
-                .length         = PCIO_SIZE,
-                .type           = MT_DEVICE,
         },
 #endif
 };
@@ -196,8 +192,10 @@ void __init footbridge_map_io(void)
          * Now, work out what we've got to map in addition on this
          * platform.
          */
-        if (footbridge_cfn_mode())
+        if (footbridge_cfn_mode()) {
                 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
+                pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
+        }
 }
 
 void footbridge_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 9d62e3381024..a7cd2cf5e08d 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
 
         sys->mem_offset  = DC21285_PCI_MEM;
 
-        pci_add_resource_offset(&sys->resources,
-                                &ioport_resource, sys->io_offset);
+        pci_ioremap_io(0, DC21285_PCI_IO);
+
         pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
         pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
@@ -298,7 +298,7 @@ void __init dc21285_preinit(void)
         mem_size = (unsigned int)high_memory - PAGE_OFFSET;
         for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
                 if (mem_mask >= mem_size)
-                        break;          
+                        break;
 
         /*
          * These registers need to be set up whether we're the
@@ -350,14 +350,6 @@ void __init dc21285_preinit(void)
                             "PCI data parity", NULL);
 
         if (cfn_mode) {
-                static struct resource csrio;
-
-                csrio.flags  = IORESOURCE_IO;
-                csrio.name   = "Footbridge";
-
-                allocate_resource(&ioport_resource, &csrio, 128,
-                                  0xff00, 0xffff, 128, NULL, NULL);
-
                 /*
                  * Map our SDRAM at a known address in PCI space, just in case
                  * the firmware had other ideas.  Using a nonzero base is
@@ -365,7 +357,7 @@ void __init dc21285_preinit(void)
                  * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
                  */
                 *CSR_PCICSRBASE       = 0xf4000000;
-                *CSR_PCICSRIOBASE     = csrio.start;
+                *CSR_PCICSRIOBASE     = 0;
                 *CSR_PCISDRAMBASE     = __virt_to_bus(PAGE_OFFSET);
                 *CSR_PCIROMBASE       = 0;
                 *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index e5acde25ffc5..c169f0c99b2a 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -17,7 +17,8 @@
         /* For NetWinder debugging */
                 .macro  addruart, rp, rv, tmp
                 mov     \rp, #0x000003f8
-                orr     \rv, \rp, #0xff000000   @ virtual
+                orr     \rv, \rp, #0xfe000000   @ virtual
+                orr     \rv, \rv, #0x00e00000   @ virtual
                 orr     \rp, \rp, #0x7c000000   @ physical
                 .endm
 
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index aba531eebbc6..aba46388cc0c 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -14,18 +14,10 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#ifdef CONFIG_MMU
-#define MMU_IO(a, b)    (a)
-#else
-#define MMU_IO(a, b)    (b)
-#endif
-
-#define PCIO_SIZE       0x00100000
-#define PCIO_BASE       MMU_IO(0xff000000, 0x7c000000)
-
 /*
- * Translation of various region addresses to virtual addresses
+ * Translation of various i/o addresses to host addresses for !CONFIG_MMU
  */
+#define PCIO_BASE       0x7c000000
 #define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
 
 #endif
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
new file mode 100644
index 000000000000..0e1d0a42a3ea
--- /dev/null
+++ b/arch/arm/mach-highbank/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_HIGHBANK
+        bool "Calxeda ECX-1000 (Highbank)" if ARCH_MULTI_V7
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_AMBA
+        select ARM_GIC
+        select ARM_TIMER_SP804
+        select CACHE_L2X0
+        select CLKDEV_LOOKUP
+        select COMMON_CLK
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU
+        select HAVE_SMP
+        select SPARSE_IRQ
+        select USE_OF
diff --git a/arch/arm/mach-highbank/Makefile.boot b/arch/arm/mach-highbank/Makefile.boot
deleted file mode 100644
index dae9661a7689..000000000000
--- a/arch/arm/mach-highbank/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y      := 0x00008000
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 141ed5171826..286ec82a4f63 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -8,4 +8,13 @@ extern void highbank_lluart_map_io(void);
 static inline void highbank_lluart_map_io(void) {}
 #endif
 
+#ifdef CONFIG_PM_SLEEP
+extern void highbank_pm_init(void);
+#else
+static inline void highbank_pm_init(void) {}
+#endif
+
 extern void highbank_smc1(int fn, int arg);
+extern void highbank_cpu_die(unsigned int cpu);
+
+extern struct smp_operations highbank_smp_ops;
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index d75b0a78d88a..af1da34ccf9d 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -152,6 +152,7 @@ static void highbank_power_off(void)
 static void __init highbank_init(void)
 {
         pm_power_off = highbank_power_off;
+        highbank_pm_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
@@ -162,6 +163,7 @@ static const char *highbank_match[] __initconst = {
 };
 
 DT_MACHINE_START(HIGHBANK, "Highbank")
+        .smp            = smp_ops(highbank_smp_ops),
         .map_io         = highbank_map_io,
         .init_irq       = highbank_init_irq,
         .timer          = &highbank_timer,
diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c
index 977cebbea580..2c1b8c3c8e45 100644
--- a/arch/arm/mach-highbank/hotplug.c
+++ b/arch/arm/mach-highbank/hotplug.c
@@ -24,16 +24,11 @@
 
 extern void secondary_startup(void);
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
  */
-void platform_cpu_die(unsigned int cpu)
+void __ref highbank_cpu_die(unsigned int cpu)
 {
         flush_cache_all();
 
@@ -45,12 +40,3 @@ void platform_cpu_die(unsigned int cpu)
         /* We should never return from idle */
         panic("highbank: cpu %d unexpectedly exit from shutdown\n", cpu);
 }
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * CPU0 should not be shut down via hotplug.  cpu_idle can WFI
-         * or a proper shutdown or hibernate should be used.
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-highbank/include/mach/gpio.h b/arch/arm/mach-highbank/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-highbank/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-highbank/include/mach/timex.h b/arch/arm/mach-highbank/include/mach/timex.h
deleted file mode 100644
index 88dac7a55a97..000000000000
--- a/arch/arm/mach-highbank/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-#define CLOCK_TICK_RATE         1000000
-
-#endif
diff --git a/arch/arm/mach-highbank/include/mach/uncompress.h b/arch/arm/mach-highbank/include/mach/uncompress.h
deleted file mode 100644
index bbe20e696325..000000000000
--- a/arch/arm/mach-highbank/include/mach/uncompress.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-
-#define putc(c)
-#define flush()
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
-
-#endif
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index d01364c72b45..fa9560ec6e70 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -25,12 +25,12 @@
 
 extern void secondary_startup(void);
 
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit highbank_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         gic_raise_softirq(cpumask_of(cpu), 0);
         return 0;
@@ -40,7 +40,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
-void __init smp_init_cpus(void)
+static void __init highbank_smp_init_cpus(void)
 {
         unsigned int i, ncores;
 
@@ -61,7 +61,7 @@ void __init smp_init_cpus(void)
         set_smp_cross_call(gic_raise_softirq);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
 {
         int i;
 
@@ -76,3 +76,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
         for (i = 1; i < max_cpus; i++)
                 highbank_set_cpu_jump(i, secondary_startup);
 }
+
+struct smp_operations highbank_smp_ops __initdata = {
+        .smp_init_cpus          = highbank_smp_init_cpus,
+        .smp_prepare_cpus       = highbank_smp_prepare_cpus,
+        .smp_secondary_init     = highbank_secondary_init,
+        .smp_boot_secondary     = highbank_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = highbank_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c
index 33b3beb89982..de866f21331f 100644
--- a/arch/arm/mach-highbank/pm.c
+++ b/arch/arm/mach-highbank/pm.c
@@ -47,9 +47,7 @@ static const struct platform_suspend_ops highbank_pm_ops = {
         .valid = suspend_valid_only_mem,
 };
 
-static int __init highbank_pm_init(void)
+void __init highbank_pm_init(void)
 {
         suspend_set_ops(&highbank_pm_ops);
-        return 0;
 }
-module_init(highbank_pm_init);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542ad6f97..7ca5fe45945f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -101,13 +101,8 @@ config	SOC_IMX51
         select SOC_IMX5
         select ARCH_MX5
         select ARCH_MX51
-
-config  SOC_IMX53
-        bool
-        select SOC_IMX5
-        select ARCH_MX5
-        select ARCH_MX53
-        select HAVE_CAN_FLEXCAN if CAN
+        select PINCTRL
+        select PINCTRL_IMX51
 
 if ARCH_IMX_V4_V5
 
@@ -561,7 +556,6 @@ config MACH_BUG
 config MACH_IMX31_DT
         bool "Support i.MX31 platforms from device tree"
         select SOC_IMX31
-        select USE_OF
         help
           Include support for Freescale i.MX31 based platforms
           using the device tree for discovery.
@@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
 
 endchoice
 
-config MX51_EFIKA_COMMON
-        bool
-        select SOC_IMX51
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_PATA_IMX
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
-
-config MACH_MX51_EFIKAMX
-        bool "Support MX51 Genesi Efika MX nettop"
-        select LEDS_GPIO_REGISTER
-        select MX51_EFIKA_COMMON
-        help
-          Include support for Genesi Efika MX nettop. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX51_EFIKASB
-        bool "Support MX51 Genesi Efika Smartbook"
-        select LEDS_GPIO_REGISTER
-        select MX51_EFIKA_COMMON
-        help
-          Include support for Genesi Efika Smartbook. This includes specific
-          configurations for the board and its peripherals.
-
-comment "i.MX53 machines:"
-
-config MACH_IMX53_DT
-        bool "Support i.MX53 platforms from device tree"
-        select SOC_IMX53
-        select MACH_MX53_ARD
-        select MACH_MX53_EVK
-        select MACH_MX53_LOCO
-        select MACH_MX53_SMD
-        help
-          Include support for Freescale i.MX53 based platforms
-          using the device tree for discovery
-
-config MACH_MX53_EVK
-        bool "Support MX53 EVK platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select LEDS_GPIO_REGISTER
-        help
-          Include support for MX53 EVK platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX53_SMD
-        bool "Support MX53 SMD platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        help
-          Include support for MX53 SMD platform. This includes specific
-          configurations for the board and its peripherals.
+comment "Device tree only"
 
-config MACH_MX53_LOCO
-        bool "Support MX53 LOCO platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_GPIO_KEYS
-        select LEDS_GPIO_REGISTER
-        help
-          Include support for MX53 LOCO platform. This includes specific
-          configurations for the board and its peripherals.
+config  SOC_IMX53
+        bool "i.MX53 support"
+        select SOC_IMX5
+        select ARCH_MX5
+        select ARCH_MX53
+        select HAVE_CAN_FLEXCAN if CAN
+        select PINCTRL
+        select PINCTRL_IMX53
 
-config MACH_MX53_ARD
-        bool "Support MX53 ARD platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_GPIO_KEYS
         help
-          Include support for MX53 ARD platform. This includes specific
-          configurations for the board and its peripherals.
-
-comment "i.MX6 family:"
+          This enables support for Freescale i.MX53 processor.
 
 config SOC_IMX6Q
         bool "i.MX6 Quad support"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d004d37ad9d8..895754aeb4f3 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -13,7 +13,7 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o
 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
-                            clk-pfd.o clk-busy.o
+                            clk-pfd.o clk-busy.o clk.o
 
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -83,16 +83,9 @@ endif
 # i.MX5 based machines
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
-obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
-obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
-obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
-obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
-obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
-obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
-obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
 obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
 
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
-obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
+obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 05541cf4a878..b27815de8473 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -37,10 +37,3 @@ initrd_phys-$(CONFIG_SOC_IMX53)	:= 0x70800000
 zreladdr-$(CONFIG_SOC_IMX6Q)    += 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
-
-dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
-dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
-                               imx53-qsb.dtb imx53-smd.dtb
-dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
-                           imx6q-sabrelite.dtb \
-                           imx6q-sabresd.dtb \
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index ea13e61bd5f3..cf65148bc519 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -23,7 +23,6 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/module.h>
-#include <linux/clkdev.h>
 #include <linux/err.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 65fb8bcd86cb..177259b523cd 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -62,8 +62,8 @@ enum mx35_clks {
         kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
         rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
         ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
-        wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate,
-        clk_max
+        wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
+        gpu2d_gate, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -142,6 +142,9 @@ int __init mx35_clocks_init()
 
         clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
 
+        clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
+        clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
+
         clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0,  0);
         clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0,  2);
         clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0,  4);
@@ -192,7 +195,7 @@ int __init mx35_clocks_init()
         clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
         clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
 
-        clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3,  0);
+        clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3,  0);
         clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3,  2);
         clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);
 
@@ -228,6 +231,7 @@ int __init mx35_clocks_init()
         clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
         clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
         clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
+        clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
         clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
         clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
@@ -253,6 +257,7 @@ int __init mx35_clocks_init()
         clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
         clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
         clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
 
         clk_prepare_enable(clk[spba_gate]);
         clk_prepare_enable(clk[gpio1_gate]);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa97bd98..e5165a84f93f 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -39,16 +39,17 @@ static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
-static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };
+static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
 static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
-static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };
+static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
 static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
 static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
 static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
 static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
 static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
+static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
 
 enum imx5_clks {
         dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -82,6 +83,7 @@ enum imx5_clks {
         ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
         ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
         epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
+        can_sel, can1_serial_gate, can1_ipg_gate,
         clk_max
 };
 
@@ -421,8 +423,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
         clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
         clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
-        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6);
-        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
+        clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
+                                mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
+        clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
+        clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
+        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
+        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
         clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
@@ -455,6 +461,10 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
+        clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
+        clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
+        clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
+        clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
 
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4233d9e3531d..3ec242f3341e 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -157,6 +157,7 @@ enum mx6q_clks {
 };
 
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 
 static enum mx6q_clks const clks_init_on[] __initconst = {
         mmdc_ch0_axi, rom,
@@ -394,52 +395,24 @@ int __init mx6q_clocks_init(void)
                         pr_err("i.MX6q clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
         clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
         clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
         clk_register_clkdev(clk[twd], NULL, "smp_twd");
-        clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
-        clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
-        clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
-        clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
-        clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
-        clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
-        clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
-        clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
-        clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
-        clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
-        clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
-        clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
-        clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
-        clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
-        clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
-        clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
-        clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
-        clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
-        clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
-        clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
-        clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
-        clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
-        clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
-        clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
-        clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
-        clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
         clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
         clk_register_clkdev(clk[ahb], "ahb", NULL);
         clk_register_clkdev(clk[cko1], "cko1", NULL);
 
+        /*
+         * The gpmi needs 100MHz frequency in the EDO/Sync mode,
+         * We can not get the 100MHz from the pll2_pfd0_352m.
+         * So choose pll2_pfd2_396m as enfc_sel's parent.
+         */
+        clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clk[clks_init_on[i]]);
 
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 2d856f9ccf59..02be73178912 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -6,7 +6,7 @@
 #include <linux/err.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/clock.h>
+
 #include "clk.h"
 
 /**
@@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
                 unsigned long parent_rate)
 {
         struct clk_pllv1 *pll = to_clk_pllv1(hw);
+        long long ll;
+        int mfn_abs;
+        unsigned int mfi, mfn, mfd, pd;
+        u32 reg;
+        unsigned long rate;
+
+        reg = readl(pll->base);
+
+        /*
+         * Get the resulting clock rate from a PLL register value and the input
+         * frequency. PLLs with this register layout can be found on i.MX1,
+         * i.MX21, i.MX27 and i,MX31
+         *
+         *                  mfi + mfn / (mfd + 1)
+         *  f = 2 * f_ref * --------------------
+         *                        pd + 1
+         */
+
+        mfi = (reg >> 10) & 0xf;
+        mfn = reg & 0x3ff;
+        mfd = (reg >> 16) & 0x3ff;
+        pd =  (reg >> 26) & 0xf;
+
+        mfi = mfi <= 5 ? 5 : mfi;
+
+        mfn_abs = mfn;
+
+        /*
+         * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
+         * 2's complements number
+         */
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+                mfn_abs = 0x400 - mfn;
+
+        rate = parent_rate * 2;
+        rate /= pd + 1;
+
+        ll = (unsigned long long)rate * mfn_abs;
+
+        do_div(ll, mfd + 1);
+
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+                ll = -ll;
+
+        ll = (rate * mfi) + ll;
 
-        return mxc_decode_pll(readl(pll->base), parent_rate);
+        return ll;
 }
 
 struct clk_ops clk_pllv1_ops = {
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
new file mode 100644
index 000000000000..f5e8be8e7f11
--- /dev/null
+++ b/arch/arm/mach-imx/clk.c
@@ -0,0 +1,3 @@
+#include <linux/spinlock.h>
+
+DEFINE_SPINLOCK(imx_ccm_lock);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 1bf64fe2523c..5f2d8acca25f 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -3,7 +3,8 @@
 
 #include <linux/spinlock.h>
 #include <linux/clk-provider.h>
-#include <mach/clock.h>
+
+extern spinlock_t imx_ccm_lock;
 
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
                 void __iomem *base);
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
deleted file mode 100644
index 77e0db96c448..000000000000
--- a/arch/arm/mach-imx/devices-imx53.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx53.h>
-#include <mach/devices-common.h>
-
-extern const struct imx_fec_data imx53_fec_data;
-#define imx53_add_fec(pdata)   \
-        imx_add_fec(&imx53_fec_data, pdata)
-
-extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
-#define imx53_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
-
-
-extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
-#define imx53_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
-
-extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
-#define imx53_add_sdhci_esdhc_imx(id, pdata)    \
-        imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx53_ecspi_data[];
-#define imx53_add_ecspi(id, pdata)      \
-        imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
-
-extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
-#define imx53_add_imx2_wdt(id)  \
-        imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
-
-extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
-#define imx53_add_imx_ssi(id, pdata)    \
-        imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
-#define imx53_add_imx_keypad(pdata)     \
-        imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
-
-extern const struct imx_pata_imx_data imx53_pata_imx_data;
-#define imx53_add_pata_imx() \
-        imx_add_pata_imx(&imx53_pata_imx_data)
-
-extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h
deleted file mode 100644
index 014aa985faae..000000000000
--- a/arch/arm/mach-imx/efika.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _EFIKA_H
-#define _EFIKA_H
-
-#define EFIKA_WLAN_EN           IMX_GPIO_NR(2, 16)
-#define EFIKA_WLAN_RESET        IMX_GPIO_NR(2, 10)
-#define EFIKA_USB_PHY_RESET     IMX_GPIO_NR(2, 9)
-
-void __init efika_board_common_init(void);
-
-#endif
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 05bb41d99728..412c583a24b0 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
 
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
index fa69419eabdd..cd6e1f81508d 100644
--- a/arch/arm/mach-imx/ehci-imx27.c
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
 
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
index faad0f15ac7f..9a880c78af34 100644
--- a/arch/arm/mach-imx/ehci-imx31.c
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
 
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 73574c30cf50..779e16eb65cb 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
 
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
index a6a4afb0ad62..cf8d00e5cce1 100644
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ b/arch/arm/mach-imx/ehci-imx5.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 
 #define MXC_OTG_OFFSET                  0
 #define MXC_H1_OFFSET                   0x200
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index f8f7437c83b8..b07b778dc9a8 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -15,11 +15,6 @@
 #include <asm/cp15.h>
 #include <mach/common.h>
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -47,7 +42,7 @@ static inline void cpu_enter_lowpower(void)
  *
  * Called with IRQs disabled
  */
-void platform_cpu_die(unsigned int cpu)
+void imx_cpu_die(unsigned int cpu)
 {
         cpu_enter_lowpower();
         imx_enable_cpu(cpu, false);
@@ -56,12 +51,3 @@ void platform_cpu_die(unsigned int cpu)
         while (1)
                 ;
 }
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index d4067fe36357..f233b4bb2342 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -13,7 +13,6 @@
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
         { /* sentinel */ }
 };
 
-static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
-        { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
-        { /* sentinel */ }
-};
-
 static void __init imx51_dt_init(void)
 {
-        struct device_node *node;
-        const struct of_device_id *of_id;
-        void (*func)(void);
-
-        pinctrl_provide_dummies();
-
-        node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
-        if (node) {
-                of_id = of_match_node(imx51_iomuxc_of_match, node);
-                func = of_id->data;
-                func();
-                of_node_put(node);
-        }
-
         of_platform_populate(NULL, of_default_bus_match_table,
                              imx51_auxdata_lookup, NULL);
 }
@@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = {
 };
 
 static const char *imx51_dt_board_compat[] __initdata = {
-        "fsl,imx51-babbage",
         "fsl,imx51",
         NULL
 };
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/mach-imx53.c
index 1b7a2fc36591..29711e95579f 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -17,7 +17,6 @@
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
         { /* sentinel */ }
 };
 
-static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
-        { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
-        { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
-        { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
-        { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
-        { /* sentinel */ }
-};
-
 static void __init imx53_qsb_init(void)
 {
         struct clk *clk;
@@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void)
 
 static void __init imx53_dt_init(void)
 {
-        struct device_node *node;
-        const struct of_device_id *of_id;
-        void (*func)(void);
-
-        pinctrl_provide_dummies();
-
-        node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
-        if (node) {
-                of_id = of_match_node(imx53_iomuxc_of_match, node);
-                func = of_id->data;
-                func();
-                of_node_put(node);
-        }
-
         if (of_machine_is_compatible("fsl,imx53-qsb"))
                 imx53_qsb_init();
 
@@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = {
 };
 
 static const char *imx53_dt_board_compat[] __initdata = {
-        "fsl,imx53-ard",
-        "fsl,imx53-evk",
-        "fsl,imx53-qsb",
-        "fsl,imx53-smd",
         "fsl,imx53",
         NULL
 };
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 045b3f6a387d..36979d3dfe34 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -22,7 +22,6 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/anatop.h>
@@ -100,7 +99,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
         clk_set_parent(cko1_sel, ahb);
         rate = clk_round_rate(cko1, 16000000);
         clk_set_rate(cko1, rate);
-        clk_register_clkdev(cko1, NULL, "0-000a");
 put_clk:
         if (!IS_ERR(cko1_sel))
                 clk_put(cko1_sel);
@@ -159,12 +157,6 @@ static void __init imx6q_usb_init(void)
 
 static void __init imx6q_init_machine(void)
 {
-        /*
-         * This should be removed when all imx6q boards have pinctrl
-         * states for devices defined in device tree.
-         */
-        pinctrl_provide_dummies();
-
         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
                 imx6q_sabrelite_init();
 
@@ -218,14 +210,12 @@ static struct sys_timer imx6q_timer = {
 };
 
 static const char *imx6q_dt_compat[] __initdata = {
-        "fsl,imx6q-arm2",
-        "fsl,imx6q-sabrelite",
-        "fsl,imx6q-sabresd",
         "fsl,imx6q",
         NULL,
 };
 
 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
+        .smp            = smp_ops(imx_smp_ops),
         .map_io         = imx6q_map_io,
         .init_irq       = imx6q_init_irq,
         .handle_irq     = imx6q_handle_irq,
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 5d08533ab2c7..0330078ff788 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -36,7 +36,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
@@ -259,13 +258,13 @@ static void __init kzm_board_init(void)
  */
 static struct map_desc kzm_io_desc[] __initdata = {
         {
-                .virtual        = MX31_CS4_BASE_ADDR_VIRT,
+                .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                 .length         = MX31_CS4_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = MX31_CS5_BASE_ADDR_VIRT,
+                .virtual        = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS5_BASE_ADDR),
                 .length         = MX31_CS5_SIZE,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index d37f4809c556..e774b07f48d3 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -540,7 +540,7 @@ static void __init mxc_init_audio(void)
  */
 static struct map_desc mx31ads_io_desc[] __initdata = {
         {
-                .virtual        = MX31_CS4_BASE_ADDR_VIRT,
+                .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                 .length         = CS4_CS8900_MMIO_START,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index c8785b39eaed..ef57cff5abfb 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -207,7 +207,7 @@ static struct platform_device physmap_flash_device = {
  */
 static struct map_desc mx31lite_io_desc[] __initdata = {
         {
-                .virtual = MX31_CS4_BASE_ADDR_VIRT,
+                .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                 .length = MX31_CS4_SIZE,
                 .type = MT_DEVICE
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index d46290b288ed..459e754ef8c9 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -47,7 +47,7 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ulpi.h>
-#include <mach/ssi.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 
 #include "devices-imx31.h"
 
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
deleted file mode 100644
index 8d09c0126cab..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright (C) 2010 Linaro Limited
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/system_info.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-
-#define EFIKAMX_PCBID0          IMX_GPIO_NR(3, 16)
-#define EFIKAMX_PCBID1          IMX_GPIO_NR(3, 17)
-#define EFIKAMX_PCBID2          IMX_GPIO_NR(3, 11)
-
-#define EFIKAMX_BLUE_LED        IMX_GPIO_NR(3, 13)
-#define EFIKAMX_GREEN_LED       IMX_GPIO_NR(3, 14)
-#define EFIKAMX_RED_LED         IMX_GPIO_NR(3, 15)
-
-#define EFIKAMX_POWER_KEY       IMX_GPIO_NR(2, 31)
-
-/* board 1.1 doesn't have same reset gpio */
-#define EFIKAMX_RESET1_1        IMX_GPIO_NR(3, 2)
-#define EFIKAMX_RESET           IMX_GPIO_NR(1, 4)
-
-#define EFIKAMX_POWEROFF        IMX_GPIO_NR(4, 13)
-
-#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
-
-/* the pci ids pin have pull up. they're driven low according to board id */
-#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-
-static iomux_v3_cfg_t mx51efikamx_pads[] = {
-        /* board id */
-        MX51_PAD_PCBID0,
-        MX51_PAD_PCBID1,
-        MX51_PAD_PCBID2,
-
-        /* leds */
-        MX51_PAD_CSI1_D9__GPIO3_13,
-        MX51_PAD_CSI1_VSYNC__GPIO3_14,
-        MX51_PAD_CSI1_HSYNC__GPIO3_15,
-
-        /* power key */
-        MX51_PAD_PWRKEY,
-
-        /* reset */
-        MX51_PAD_DI1_PIN13__GPIO3_2,
-        MX51_PAD_GPIO1_4__GPIO1_4,
-
-        /* power off */
-        MX51_PAD_CSI2_VSYNC__GPIO4_13,
-};
-
-/*   PCBID2  PCBID1 PCBID0  STATE
-        1       1      1    ER1:rev1.1
-        1       1      0    ER2:rev1.2
-        1       0      1    ER3:rev1.3
-        1       0      0    ER4:rev1.4
-*/
-static void __init mx51_efikamx_board_id(void)
-{
-        int id;
-
-        /* things are taking time to settle */
-        msleep(150);
-
-        gpio_request(EFIKAMX_PCBID0, "pcbid0");
-        gpio_direction_input(EFIKAMX_PCBID0);
-        gpio_request(EFIKAMX_PCBID1, "pcbid1");
-        gpio_direction_input(EFIKAMX_PCBID1);
-        gpio_request(EFIKAMX_PCBID2, "pcbid2");
-        gpio_direction_input(EFIKAMX_PCBID2);
-
-        id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
-        id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
-        id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
-
-        switch (id) {
-        case 7:
-                system_rev = 0x11;
-                break;
-        case 6:
-                system_rev = 0x12;
-                break;
-        case 5:
-                system_rev = 0x13;
-                break;
-        case 4:
-                system_rev = 0x14;
-                break;
-        default:
-                system_rev = 0x10;
-                break;
-        }
-
-        if ((system_rev == 0x10)
-                || (system_rev == 0x12)
-                || (system_rev == 0x14)) {
-                printk(KERN_WARNING
-                        "EfikaMX: Unsupported board revision 1.%u!\n",
-                        system_rev & 0xf);
-        }
-}
-
-static struct gpio_led mx51_efikamx_leds[] __initdata = {
-        {
-                .name = "efikamx:green",
-                .default_trigger = "default-on",
-                .gpio = EFIKAMX_GREEN_LED,
-        },
-        {
-                .name = "efikamx:red",
-                .default_trigger = "ide-disk",
-                .gpio = EFIKAMX_RED_LED,
-        },
-        {
-                .name = "efikamx:blue",
-                .default_trigger = "mmc0",
-                .gpio = EFIKAMX_BLUE_LED,
-        },
-};
-
-static const struct gpio_led_platform_data
-                mx51_efikamx_leds_data __initconst = {
-        .leds = mx51_efikamx_leds,
-        .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
-};
-
-static struct esdhc_platform_data sd_pdata = {
-        .cd_type = ESDHC_CD_CONTROLLER,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct gpio_keys_button mx51_efikamx_powerkey[] = {
-        {
-                .code = KEY_POWER,
-                .gpio = EFIKAMX_POWER_KEY,
-                .type = EV_PWR,
-                .desc = "Power Button (CM)",
-                .wakeup = 1,
-                .debounce_interval = 10, /* ms */
-        },
-};
-
-static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
-        .buttons = mx51_efikamx_powerkey,
-        .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
-};
-
-static void mx51_efikamx_restart(char mode, const char *cmd)
-{
-        if (system_rev == 0x11)
-                gpio_direction_output(EFIKAMX_RESET1_1, 0);
-        else
-                gpio_direction_output(EFIKAMX_RESET, 0);
-}
-
-static struct regulator *pwgt1, *pwgt2, *coincell;
-
-static void mx51_efikamx_power_off(void)
-{
-        if (!IS_ERR(coincell))
-                regulator_disable(coincell);
-
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_disable(pwgt2);
-                regulator_disable(pwgt1);
-        }
-        gpio_direction_output(EFIKAMX_POWEROFF, 1);
-}
-
-static int __init mx51_efikamx_power_init(void)
-{
-        pwgt1 = regulator_get(NULL, "pwgt1");
-        pwgt2 = regulator_get(NULL, "pwgt2");
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_enable(pwgt1);
-                regulator_enable(pwgt2);
-        }
-        gpio_request(EFIKAMX_POWEROFF, "poweroff");
-        pm_power_off = mx51_efikamx_power_off;
-
-        /* enable coincell charger. maybe need a small power driver ? */
-        coincell = regulator_get(NULL, "coincell");
-        if (!IS_ERR(coincell)) {
-                regulator_set_voltage(coincell, 3000000, 3000000);
-                regulator_enable(coincell);
-        }
-
-        regulator_has_full_constraints();
-
-        return 0;
-}
-
-static void __init mx51_efikamx_init_late(void)
-{
-        imx51_init_late();
-        mx51_efikamx_power_init();
-}
-
-static void __init mx51_efikamx_init(void)
-{
-        imx51_soc_init();
-
-        mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
-                                        ARRAY_SIZE(mx51efikamx_pads));
-        efika_board_common_init();
-
-        mx51_efikamx_board_id();
-
-        /* on < 1.2 boards both SD controllers are used */
-        if (system_rev < 0x12) {
-                imx51_add_sdhci_esdhc_imx(0, NULL);
-                imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
-                mx51_efikamx_leds[2].default_trigger = "mmc1";
-        } else
-                imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
-
-        gpio_led_register_device(-1, &mx51_efikamx_leds_data);
-        imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
-
-        if (system_rev == 0x11) {
-                gpio_request(EFIKAMX_RESET1_1, "reset");
-                gpio_direction_output(EFIKAMX_RESET1_1, 1);
-        } else {
-                gpio_request(EFIKAMX_RESET, "reset");
-                gpio_direction_output(EFIKAMX_RESET, 1);
-        }
-
-        /*
-         * enable wifi by default only on mx
-         * sb and mx have same wlan pin but the value to enable it are
-         * different :/
-         */
-        gpio_request(EFIKA_WLAN_EN, "wlan_en");
-        gpio_direction_output(EFIKA_WLAN_EN, 0);
-        msleep(10);
-
-        gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
-        gpio_direction_output(EFIKA_WLAN_RESET, 0);
-        msleep(10);
-        gpio_set_value(EFIKA_WLAN_RESET, 1);
-}
-
-static void __init mx51_efikamx_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-
-static struct sys_timer mx51_efikamx_timer = {
-        .init = mx51_efikamx_timer_init,
-};
-
-MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .timer = &mx51_efikamx_timer,
-        .init_machine = mx51_efikamx_init,
-        .init_late = mx51_efikamx_init_late,
-        .restart = mx51_efikamx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
deleted file mode 100644
index fdbd181b97ef..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/system_info.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-
-#define EFIKASB_USBH2_STP       IMX_GPIO_NR(2, 20)
-#define EFIKASB_GREEN_LED       IMX_GPIO_NR(1, 3)
-#define EFIKASB_WHITE_LED       IMX_GPIO_NR(2, 25)
-#define EFIKASB_PCBID0          IMX_GPIO_NR(2, 28)
-#define EFIKASB_PCBID1          IMX_GPIO_NR(2, 29)
-#define EFIKASB_PWRKEY          IMX_GPIO_NR(2, 31)
-#define EFIKASB_LID             IMX_GPIO_NR(3, 14)
-#define EFIKASB_POWEROFF        IMX_GPIO_NR(4, 13)
-#define EFIKASB_RFKILL          IMX_GPIO_NR(3, 1)
-
-#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-
-static iomux_v3_cfg_t mx51efikasb_pads[] = {
-        /* USB HOST2 */
-        MX51_PAD_EIM_D16__USBH2_DATA0,
-        MX51_PAD_EIM_D17__USBH2_DATA1,
-        MX51_PAD_EIM_D18__USBH2_DATA2,
-        MX51_PAD_EIM_D19__USBH2_DATA3,
-        MX51_PAD_EIM_D20__USBH2_DATA4,
-        MX51_PAD_EIM_D21__USBH2_DATA5,
-        MX51_PAD_EIM_D22__USBH2_DATA6,
-        MX51_PAD_EIM_D23__USBH2_DATA7,
-        MX51_PAD_EIM_A24__USBH2_CLK,
-        MX51_PAD_EIM_A25__USBH2_DIR,
-        MX51_PAD_EIM_A26__USBH2_STP,
-        MX51_PAD_EIM_A27__USBH2_NXT,
-
-        /* leds */
-        MX51_PAD_EIM_CS0__GPIO2_25,
-        MX51_PAD_GPIO1_3__GPIO1_3,
-
-        /* pcb id */
-        MX51_PAD_EIM_CS3__GPIO2_28,
-        MX51_PAD_EIM_CS4__GPIO2_29,
-
-        /* lid */
-        MX51_PAD_CSI1_VSYNC__GPIO3_14,
-
-        /* power key*/
-        MX51_PAD_PWRKEY,
-
-        /* wifi/bt button */
-        MX51_PAD_DI1_PIN12__GPIO3_1,
-
-        /* power off */
-        MX51_PAD_CSI2_VSYNC__GPIO4_13,
-
-        /* wdog reset */
-        MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
-
-        /* BT */
-        MX51_PAD_EIM_A17__GPIO2_11,
-
-        MX51_PAD_SD1_CD,
-};
-
-static int initialize_usbh2_port(struct platform_device *pdev)
-{
-        iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
-        iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
-
-        mxc_iomux_v3_setup_pad(usbh2gpio);
-        gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
-        gpio_direction_output(EFIKASB_USBH2_STP, 0);
-        msleep(1);
-        gpio_set_value(EFIKASB_USBH2_STP, 1);
-        msleep(1);
-
-        gpio_free(EFIKASB_USBH2_STP);
-        mxc_iomux_v3_setup_pad(usbh2stp);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static struct mxc_usbh_platform_data usbh2_config __initdata = {
-        .init   = initialize_usbh2_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static void __init mx51_efikasb_usb(void)
-{
-        usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-        if (usbh2_config.otg)
-                imx51_add_mxc_ehci_hs(2, &usbh2_config);
-}
-
-static const struct gpio_led mx51_efikasb_leds[] __initconst = {
-        {
-                .name = "efikasb:green",
-                .default_trigger = "default-on",
-                .gpio = EFIKASB_GREEN_LED,
-                .active_low = 1,
-        },
-        {
-                .name = "efikasb:white",
-                .default_trigger = "caps",
-                .gpio = EFIKASB_WHITE_LED,
-        },
-};
-
-static const struct gpio_led_platform_data
-                mx51_efikasb_leds_data __initconst = {
-        .leds = mx51_efikasb_leds,
-        .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
-};
-
-static struct gpio_keys_button mx51_efikasb_keys[] = {
-        {
-                .code = KEY_POWER,
-                .gpio = EFIKASB_PWRKEY,
-                .type = EV_KEY,
-                .desc = "Power Button",
-                .wakeup = 1,
-                .active_low = 1,
-        },
-        {
-                .code = SW_LID,
-                .gpio = EFIKASB_LID,
-                .type = EV_SW,
-                .desc = "Lid Switch",
-                .active_low = 1,
-        },
-        {
-                .code = KEY_RFKILL,
-                .gpio = EFIKASB_RFKILL,
-                .type = EV_KEY,
-                .desc = "rfkill",
-                .active_low = 1,
-        },
-};
-
-static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
-        .buttons = mx51_efikasb_keys,
-        .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
-};
-
-static struct esdhc_platform_data sd0_pdata = {
-#define EFIKASB_SD1_CD  IMX_GPIO_NR(2, 27)
-        .cd_gpio = EFIKASB_SD1_CD,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct esdhc_platform_data sd1_pdata = {
-        .cd_type = ESDHC_CD_CONTROLLER,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct regulator *pwgt1, *pwgt2;
-
-static void mx51_efikasb_power_off(void)
-{
-        gpio_set_value(EFIKA_USB_PHY_RESET, 0);
-
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_disable(pwgt2);
-                regulator_disable(pwgt1);
-        }
-        gpio_direction_output(EFIKASB_POWEROFF, 1);
-}
-
-static int __init mx51_efikasb_power_init(void)
-{
-        pwgt1 = regulator_get(NULL, "pwgt1");
-        pwgt2 = regulator_get(NULL, "pwgt2");
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_enable(pwgt1);
-                regulator_enable(pwgt2);
-        }
-        gpio_request(EFIKASB_POWEROFF, "poweroff");
-        pm_power_off = mx51_efikasb_power_off;
-
-        regulator_has_full_constraints();
-
-        return 0;
-}
-
-static void __init mx51_efikasb_init_late(void)
-{
-        imx51_init_late();
-        mx51_efikasb_power_init();
-}
-
-/* 01     R1.3 board
-   10     R2.0 board */
-static void __init mx51_efikasb_board_id(void)
-{
-        int id;
-
-        gpio_request(EFIKASB_PCBID0, "pcb id0");
-        gpio_direction_input(EFIKASB_PCBID0);
-        gpio_request(EFIKASB_PCBID1, "pcb id1");
-        gpio_direction_input(EFIKASB_PCBID1);
-
-        id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
-        id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
-
-        switch (id) {
-        default:
-                break;
-        case 1:
-                system_rev = 0x13;
-                break;
-        case 2:
-                system_rev = 0x20;
-                break;
-        }
-}
-
-static void __init efikasb_board_init(void)
-{
-        imx51_soc_init();
-
-        mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
-                                        ARRAY_SIZE(mx51efikasb_pads));
-        efika_board_common_init();
-
-        mx51_efikasb_board_id();
-        mx51_efikasb_usb();
-        imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
-        imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
-
-        gpio_led_register_device(-1, &mx51_efikasb_leds_data);
-        imx_add_gpio_keys(&mx51_efikasb_keys_data);
-}
-
-static void __init mx51_efikasb_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-
-static struct sys_timer mx51_efikasb_timer = {
-        .init   = mx51_efikasb_timer_init,
-};
-
-MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .init_machine =  efikasb_board_init,
-        .init_late = mx51_efikasb_init_late,
-        .timer = &mx51_efikasb_timer,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
deleted file mode 100644
index 6c28e65f424d..000000000000
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define ARD_ETHERNET_INT_B      IMX_GPIO_NR(2, 31)
-#define ARD_SD1_CD              IMX_GPIO_NR(1, 1)
-#define ARD_SD1_WP              IMX_GPIO_NR(1, 9)
-#define ARD_I2CPORTEXP_B        IMX_GPIO_NR(2, 3)
-#define ARD_VOLUMEDOWN          IMX_GPIO_NR(4, 0)
-#define ARD_HOME                        IMX_GPIO_NR(5, 10)
-#define ARD_BACK                        IMX_GPIO_NR(5, 11)
-#define ARD_PROG                        IMX_GPIO_NR(5, 12)
-#define ARD_VOLUMEUP            IMX_GPIO_NR(5, 13)
-
-static iomux_v3_cfg_t mx53_ard_pads[] = {
-        /* UART1 */
-        MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
-        MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
-        /* WEIM for CS1 */
-        MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
-        MX53_PAD_EIM_D16__EMI_WEIM_D_16,
-        MX53_PAD_EIM_D17__EMI_WEIM_D_17,
-        MX53_PAD_EIM_D18__EMI_WEIM_D_18,
-        MX53_PAD_EIM_D19__EMI_WEIM_D_19,
-        MX53_PAD_EIM_D20__EMI_WEIM_D_20,
-        MX53_PAD_EIM_D21__EMI_WEIM_D_21,
-        MX53_PAD_EIM_D22__EMI_WEIM_D_22,
-        MX53_PAD_EIM_D23__EMI_WEIM_D_23,
-        MX53_PAD_EIM_D24__EMI_WEIM_D_24,
-        MX53_PAD_EIM_D25__EMI_WEIM_D_25,
-        MX53_PAD_EIM_D26__EMI_WEIM_D_26,
-        MX53_PAD_EIM_D27__EMI_WEIM_D_27,
-        MX53_PAD_EIM_D28__EMI_WEIM_D_28,
-        MX53_PAD_EIM_D29__EMI_WEIM_D_29,
-        MX53_PAD_EIM_D30__EMI_WEIM_D_30,
-        MX53_PAD_EIM_D31__EMI_WEIM_D_31,
-        MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
-        MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
-        MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
-        MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
-        MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
-        MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
-        MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
-        MX53_PAD_EIM_OE__EMI_WEIM_OE,
-        MX53_PAD_EIM_RW__EMI_WEIM_RW,
-        MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
-        /* SDHC1 */
-        MX53_PAD_SD1_CMD__ESDHC1_CMD,
-        MX53_PAD_SD1_CLK__ESDHC1_CLK,
-        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-        MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
-        MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
-        MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
-        MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
-        MX53_PAD_GPIO_1__GPIO1_1,
-        MX53_PAD_GPIO_9__GPIO1_9,
-        /* I2C2 */
-        MX53_PAD_EIM_EB2__I2C2_SCL,
-        MX53_PAD_KEY_ROW3__I2C2_SDA,
-        /* I2C3 */
-        MX53_PAD_GPIO_3__I2C3_SCL,
-        MX53_PAD_GPIO_16__I2C3_SDA,
-        /* GPIO */
-        MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
-        MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
-        MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
-        MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
-        MX53_PAD_GPIO_10__GPIO4_0,              /* vol down */
-};
-
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)    \
-{                                                       \
-        .gpio           = gpio_num,                             \
-        .type           = EV_KEY,                               \
-        .code           = ev_code,                              \
-        .active_low     = act_low,                              \
-        .desc           = "btn " descr,                 \
-        .wakeup         = wake,                                 \
-}
-
-static struct gpio_keys_button ard_buttons[] = {
-        GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
-        GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
-        GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
-        GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
-        GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-
-static const struct gpio_keys_platform_data ard_button_data __initconst = {
-        .buttons        = ard_buttons,
-        .nbuttons       = ARRAY_SIZE(ard_buttons),
-};
-
-static struct resource ard_smsc911x_resources[] = {
-        {
-                .start = MX53_CS1_64MB_BASE_ADDR,
-                .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                /* irq number is run-time assigned */
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct smsc911x_platform_config ard_smsc911x_config = {
-        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags = SMSC911X_USE_32BIT,
-};
-
-static struct platform_device ard_smsc_lan9220_device = {
-        .name = "smsc911x",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
-        .resource = ard_smsc911x_resources,
-        .dev = {
-                .platform_data = &ard_smsc911x_config,
-        },
-};
-
-static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
-        .cd_gpio = ARD_SD1_CD,
-        .wp_gpio = ARD_SD1_WP,
-};
-
-static struct imxi2c_platform_data mx53_ard_i2c2_data = {
-        .bitrate = 50000,
-};
-
-static struct imxi2c_platform_data mx53_ard_i2c3_data = {
-        .bitrate = 400000,
-};
-
-static void __init mx53_ard_io_init(void)
-{
-        gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
-        gpio_direction_input(ARD_ETHERNET_INT_B);
-
-        gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
-        gpio_direction_output(ARD_I2CPORTEXP_B, 1);
-}
-
-/* Config CS1 settings for ethernet controller */
-static int weim_cs_config(void)
-{
-        u32 reg;
-        void __iomem *weim_base, *iomuxc_base;
-
-        weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
-        if (!weim_base)
-                return -ENOMEM;
-
-        iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
-        if (!iomuxc_base) {
-                iounmap(weim_base);
-                return -ENOMEM;
-        }
-
-        /* CS1 timings for LAN9220 */
-        writel(0x20001, (weim_base + 0x18));
-        writel(0x0, (weim_base + 0x1C));
-        writel(0x16000202, (weim_base + 0x20));
-        writel(0x00000002, (weim_base + 0x24));
-        writel(0x16002082, (weim_base + 0x28));
-        writel(0x00000000, (weim_base + 0x2C));
-        writel(0x00000000, (weim_base + 0x90));
-
-        /* specify 64 MB on CS1 and CS0 on GPR1 */
-        reg = readl(iomuxc_base + 0x4);
-        reg &= ~0x3F;
-        reg |= 0x1B;
-        writel(reg, (iomuxc_base + 0x4));
-
-        iounmap(iomuxc_base);
-        iounmap(weim_base);
-
-        return 0;
-}
-
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-void __init imx53_ard_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
-                                         ARRAY_SIZE(mx53_ard_pads));
-        weim_cs_config();
-}
-
-static struct platform_device *devices[] __initdata = {
-        &ard_smsc_lan9220_device,
-};
-
-static void __init mx53_ard_board_init(void)
-{
-        imx53_soc_init();
-        imx53_add_imx_uart(0, NULL);
-
-        imx53_ard_common_init();
-        mx53_ard_io_init();
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-        ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
-        ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-
-        imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
-        imx53_add_imx2_wdt(0);
-        imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
-        imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
-        imx_add_gpio_keys(&ard_button_data);
-        imx53_add_ahci_imx();
-}
-
-static void __init mx53_ard_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_ard_timer = {
-        .init   = mx53_ard_timer_init,
-};
-
-MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_ard_timer,
-        .init_machine = mx53_ard_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
deleted file mode 100644
index 09fe2197b491..000000000000
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/iomux-mx53.h>
-
-#define MX53_EVK_FEC_PHY_RST    IMX_GPIO_NR(7, 6)
-#define EVK_ECSPI1_CS0          IMX_GPIO_NR(2, 30)
-#define EVK_ECSPI1_CS1          IMX_GPIO_NR(3, 19)
-#define MX53EVK_LED             IMX_GPIO_NR(7, 7)
-
-#include "devices-imx53.h"
-
-static iomux_v3_cfg_t mx53_evk_pads[] = {
-        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-
-        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-        MX53_PAD_PATA_DIOR__UART2_RTS,
-        MX53_PAD_PATA_INTRQ__UART2_CTS,
-
-        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-
-        MX53_PAD_EIM_D16__ECSPI1_SCLK,
-        MX53_PAD_EIM_D17__ECSPI1_MISO,
-        MX53_PAD_EIM_D18__ECSPI1_MOSI,
-
-        /* ecspi chip select lines */
-        MX53_PAD_EIM_EB2__GPIO2_30,
-        MX53_PAD_EIM_D19__GPIO3_19,
-        /* LED */
-        MX53_PAD_PATA_DA_1__GPIO7_7,
-};
-
-static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct gpio_led mx53evk_leds[] __initconst = {
-        {
-                .name                   = "green",
-                .default_trigger        = "heartbeat",
-                .gpio                   = MX53EVK_LED,
-        },
-};
-
-static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
-        .leds           = mx53evk_leds,
-        .num_leds       = ARRAY_SIZE(mx53evk_leds),
-};
-
-static inline void mx53_evk_init_uart(void)
-{
-        imx53_add_imx_uart(0, NULL);
-        imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
-        imx53_add_imx_uart(2, NULL);
-}
-
-static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-static inline void mx53_evk_fec_reset(void)
-{
-        int ret;
-
-        /* reset FEC PHY */
-        ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
-                                                        "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        msleep(1);
-        gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
-}
-
-static const struct fec_platform_data mx53_evk_fec_pdata __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
-        {
-                .modalias = "mtd_dataflash",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .mode = SPI_MODE_0,
-                .platform_data = NULL,
-        },
-};
-
-static int mx53_evk_spi_cs[] = {
-        EVK_ECSPI1_CS0,
-        EVK_ECSPI1_CS1,
-};
-
-static const struct spi_imx_master mx53_evk_spi_data __initconst = {
-        .chipselect     = mx53_evk_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
-};
-
-void __init imx53_evk_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
-                                         ARRAY_SIZE(mx53_evk_pads));
-}
-
-static void __init mx53_evk_board_init(void)
-{
-        imx53_soc_init();
-        imx53_evk_common_init();
-
-        mx53_evk_init_uart();
-        mx53_evk_fec_reset();
-        imx53_add_fec(&mx53_evk_fec_pdata);
-
-        imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
-        imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
-
-        imx53_add_sdhci_esdhc_imx(0, NULL);
-        imx53_add_sdhci_esdhc_imx(1, NULL);
-
-        spi_register_board_info(mx53_evk_spi_board_info,
-                ARRAY_SIZE(mx53_evk_spi_board_info));
-        imx53_add_ecspi(0, &mx53_evk_spi_data);
-        imx53_add_imx2_wdt(0);
-        gpio_led_register_device(-1, &mx53evk_leds_data);
-}
-
-static void __init mx53_evk_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_evk_timer = {
-        .init   = mx53_evk_timer_init,
-};
-
-MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_evk_timer,
-        .init_machine = mx53_evk_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
deleted file mode 100644
index 8abe23c1d3c8..000000000000
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define MX53_LOCO_POWER                 IMX_GPIO_NR(1, 8)
-#define MX53_LOCO_UI1                   IMX_GPIO_NR(2, 14)
-#define MX53_LOCO_UI2                   IMX_GPIO_NR(2, 15)
-#define LOCO_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
-#define LOCO_LED                        IMX_GPIO_NR(7, 7)
-#define LOCO_SD3_CD                     IMX_GPIO_NR(3, 11)
-#define LOCO_SD3_WP                     IMX_GPIO_NR(3, 12)
-#define LOCO_SD1_CD                     IMX_GPIO_NR(3, 13)
-#define LOCO_ACCEL_EN                   IMX_GPIO_NR(6, 14)
-
-static iomux_v3_cfg_t mx53_loco_pads[] = {
-        /* FEC */
-        MX53_PAD_FEC_MDC__FEC_MDC,
-        MX53_PAD_FEC_MDIO__FEC_MDIO,
-        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-        MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-        MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-        MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-        MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-        MX53_PAD_FEC_TX_EN__FEC_TX_EN,
-        MX53_PAD_FEC_TXD1__FEC_TDATA_1,
-        MX53_PAD_FEC_TXD0__FEC_TDATA_0,
-        /* FEC_nRST */
-        MX53_PAD_PATA_DA_0__GPIO7_6,
-        /* FEC_nINT */
-        MX53_PAD_PATA_DATA4__GPIO2_4,
-        /* AUDMUX5 */
-        MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
-        MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
-        MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
-        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
-        /* I2C1 */
-        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        MX53_PAD_NANDF_CS1__GPIO6_14,   /* Accelerometer Enable */
-        /* I2C2 */
-        MX53_PAD_KEY_COL3__I2C2_SCL,
-        MX53_PAD_KEY_ROW3__I2C2_SDA,
-        /* SD1 */
-        MX53_PAD_SD1_CMD__ESDHC1_CMD,
-        MX53_PAD_SD1_CLK__ESDHC1_CLK,
-        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-        /* SD1_CD */
-        MX53_PAD_EIM_DA13__GPIO3_13,
-        /* SD3 */
-        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-        /* SD3_CD */
-        MX53_PAD_EIM_DA11__GPIO3_11,
-        /* SD3_WP */
-        MX53_PAD_EIM_DA12__GPIO3_12,
-        /* VGA */
-        MX53_PAD_EIM_OE__IPU_DI1_PIN7,
-        MX53_PAD_EIM_RW__IPU_DI1_PIN8,
-        /* DISPLB */
-        MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
-        MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
-        MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
-        MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
-        /* DISP0_POWER_EN */
-        MX53_PAD_EIM_D24__GPIO3_24,
-        /* DISP0 DET INT */
-        MX53_PAD_EIM_D31__GPIO3_31,
-        /* LVDS */
-        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
-        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
-        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
-        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
-        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
-        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
-        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
-        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
-        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
-        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
-        /* I2C1 */
-        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        /* UART1 */
-        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-        /* CSI0 */
-        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
-        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
-        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
-        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
-        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
-        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
-        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
-        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
-        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
-        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
-        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
-        /* DISPLAY */
-        MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
-        MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
-        MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
-        MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
-        MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
-        MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
-        MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
-        MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
-        MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
-        MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
-        MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
-        MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
-        MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
-        MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
-        MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
-        MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
-        MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
-        MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
-        MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
-        MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
-        MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
-        MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
-        MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
-        MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
-        MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
-        MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
-        MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
-        MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
-        /* Audio CLK*/
-        MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
-        /* PWM */
-        MX53_PAD_GPIO_1__PWM2_PWMO,
-        /* SPDIF */
-        MX53_PAD_GPIO_7__SPDIF_PLOCK,
-        MX53_PAD_GPIO_17__SPDIF_OUT1,
-        /* GPIO */
-        MX53_PAD_PATA_DA_1__GPIO7_7,            /* LED */
-        MX53_PAD_PATA_DA_2__GPIO7_8,
-        MX53_PAD_PATA_DATA5__GPIO2_5,
-        MX53_PAD_PATA_DATA6__GPIO2_6,
-        MX53_PAD_PATA_DATA14__GPIO2_14,
-        MX53_PAD_PATA_DATA15__GPIO2_15,
-        MX53_PAD_PATA_INTRQ__GPIO7_2,
-        MX53_PAD_EIM_WAIT__GPIO5_0,
-        MX53_PAD_NANDF_WP_B__GPIO6_9,
-        MX53_PAD_NANDF_RB0__GPIO6_10,
-        MX53_PAD_NANDF_CS1__GPIO6_14,
-        MX53_PAD_NANDF_CS2__GPIO6_15,
-        MX53_PAD_NANDF_CS3__GPIO6_16,
-        MX53_PAD_GPIO_5__GPIO1_5,
-        MX53_PAD_GPIO_16__GPIO7_11,
-        MX53_PAD_GPIO_8__GPIO1_8,
-};
-
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)    \
-{                                                               \
-        .gpio           = gpio_num,                             \
-        .type           = EV_KEY,                               \
-        .code           = ev_code,                              \
-        .active_low     = act_low,                              \
-        .desc           = "btn " descr,                         \
-        .wakeup         = wake,                                 \
-}
-
-static struct gpio_keys_button loco_buttons[] = {
-        GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
-        GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
-        GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-
-static const struct gpio_keys_platform_data loco_button_data __initconst = {
-        .buttons        = loco_buttons,
-        .nbuttons       = ARRAY_SIZE(loco_buttons),
-};
-
-static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
-        .cd_gpio = LOCO_SD1_CD,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_NONE,
-};
-
-static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
-        .cd_gpio = LOCO_SD3_CD,
-        .wp_gpio = LOCO_SD3_WP,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_GPIO,
-};
-
-static inline void mx53_loco_fec_reset(void)
-{
-        int ret;
-
-        /* reset FEC PHY */
-        ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        gpio_direction_output(LOCO_FEC_PHY_RST, 0);
-        msleep(1);
-        gpio_set_value(LOCO_FEC_PHY_RST, 1);
-}
-
-static const struct fec_platform_data mx53_loco_fec_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-static const struct gpio_led mx53loco_leds[] __initconst = {
-        {
-                .name                   = "green",
-                .default_trigger        = "heartbeat",
-                .gpio                   = LOCO_LED,
-        },
-};
-
-static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
-        .leds           = mx53loco_leds,
-        .num_leds       = ARRAY_SIZE(mx53loco_leds),
-};
-
-void __init imx53_qsb_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
-                                         ARRAY_SIZE(mx53_loco_pads));
-}
-
-static struct i2c_board_info mx53loco_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("mma8450", 0x1C),
-        },
-};
-
-static void __init mx53_loco_board_init(void)
-{
-        int ret;
-        imx53_soc_init();
-        imx53_qsb_common_init();
-
-        imx53_add_imx_uart(0, NULL);
-        mx53_loco_fec_reset();
-        imx53_add_fec(&mx53_loco_fec_data);
-        imx53_add_imx2_wdt(0);
-
-        ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
-        if (ret)
-                pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
-
-        i2c_register_board_info(0, mx53loco_i2c_devices,
-                                ARRAY_SIZE(mx53loco_i2c_devices));
-        imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
-        imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
-        imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
-        imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
-        imx_add_gpio_keys(&loco_button_data);
-        gpio_led_register_device(-1, &mx53loco_leds_data);
-        imx53_add_ahci_imx();
-}
-
-static void __init mx53_loco_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 0, 0);
-}
-
-static struct sys_timer mx53_loco_timer = {
-        .init   = mx53_loco_timer_init,
-};
-
-MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_loco_timer,
-        .init_machine = mx53_loco_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
deleted file mode 100644
index b15d6a6d3b68..000000000000
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
-#define MX53_SMD_SATA_PWR_EN    IMX_GPIO_NR(3, 3)
-
-static iomux_v3_cfg_t mx53_smd_pads[] = {
-        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-
-        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-
-        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-        MX53_PAD_PATA_DA_1__UART3_CTS,
-        MX53_PAD_PATA_DA_2__UART3_RTS,
-        /* I2C1 */
-        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        /* SD1 */
-        MX53_PAD_SD1_CMD__ESDHC1_CMD,
-        MX53_PAD_SD1_CLK__ESDHC1_CLK,
-        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-        /* SD2 */
-        MX53_PAD_SD2_CMD__ESDHC2_CMD,
-        MX53_PAD_SD2_CLK__ESDHC2_CLK,
-        MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
-        MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
-        MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
-        MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
-        /* SD3 */
-        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-};
-
-static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static inline void mx53_smd_init_uart(void)
-{
-        imx53_add_imx_uart(0, NULL);
-        imx53_add_imx_uart(1, NULL);
-        imx53_add_imx_uart(2, &mx53_smd_uart_data);
-}
-
-static inline void mx53_smd_fec_reset(void)
-{
-        int ret;
-
-        /* reset FEC PHY */
-        ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        gpio_direction_output(SMD_FEC_PHY_RST, 0);
-        msleep(1);
-        gpio_set_value(SMD_FEC_PHY_RST, 1);
-}
-
-static const struct fec_platform_data mx53_smd_fec_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-static inline void mx53_smd_ahci_pwr_on(void)
-{
-        int ret;
-
-        /* Enable SATA PWR */
-        ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
-                        GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
-        if (ret) {
-                pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
-                return;
-        }
-}
-
-void __init imx53_smd_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
-                                         ARRAY_SIZE(mx53_smd_pads));
-}
-
-static void __init mx53_smd_board_init(void)
-{
-        imx53_soc_init();
-        imx53_smd_common_init();
-
-        mx53_smd_init_uart();
-        mx53_smd_fec_reset();
-        imx53_add_fec(&mx53_smd_fec_data);
-        imx53_add_imx2_wdt(0);
-        imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
-        imx53_add_sdhci_esdhc_imx(0, NULL);
-        imx53_add_sdhci_esdhc_imx(1, NULL);
-        imx53_add_sdhci_esdhc_imx(2, NULL);
-        mx53_smd_ahci_pwr_on();
-        imx53_add_ahci_imx();
-}
-
-static void __init mx53_smd_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_smd_timer = {
-        .init   = mx53_smd_timer_init,
-};
-
-MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_smd_timer,
-        .init_machine = mx53_smd_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 52d8f534be10..acb0aadb4255 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
         .script_addrs = &imx51_sdma_script,
 };
 
-static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
-        .ap_2_ap_addr = 642,
-        .app_2_mcu_addr = 683,
-        .mcu_2_app_addr = 747,
-        .uart_2_mcu_addr = 817,
-        .shp_2_mcu_addr = 891,
-        .mcu_2_shp_addr = 960,
-        .uartsh_2_mcu_addr = 1032,
-        .spdif_2_mcu_addr = 1100,
-        .mcu_2_spdif_addr = 1134,
-        .firi_2_mcu_addr = 1193,
-        .mcu_2_firi_addr = 1290,
-};
-
-static struct sdma_platform_data imx53_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx53.bin",
-        .script_addrs = &imx53_sdma_script,
-};
-
 static const struct resource imx50_audmux_res[] __initconst = {
         DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
 };
@@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = {
         DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
 };
 
-static const struct resource imx53_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
 void __init imx50_soc_init(void)
 {
         /* i.mx50 has the i.mx35 type gpio */
@@ -196,30 +173,6 @@ void __init imx51_soc_init(void)
                                         ARRAY_SIZE(imx51_audmux_res));
 }
 
-void __init imx53_soc_init(void)
-{
-        /* i.mx53 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
-        mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
-        mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
-        mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
-
-        pinctrl_provide_dummies();
-        /* i.mx53 has the i.mx35 type sdma */
-        imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
-
-        /* Setup AIPS registers */
-        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
-        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
-
-        /* i.mx53 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
-                                        ARRAY_SIZE(imx53_audmux_res));
-}
-
 void __init imx51_init_late(void)
 {
         mx51_neon_fixup();
diff --git a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
index b09ee12a4ff0..fb38436ca67f 100644
--- a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
+++ b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
@@ -11,7 +11,7 @@
 #include <linux/platform_device.h>
 #include <linux/module.h>
 
-#include <mach/mx1_camera.h>
+#include <linux/platform_data/camera-mx1.h>
 
 /* IMX camera FIQ handler */
 EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
deleted file mode 100644
index ee870c49bc63..000000000000
--- a/arch/arm/mach-imx/mx51_efika.c
+++ /dev/null
@@ -1,633 +0,0 @@
-/*
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-#include "cpu_op-mx51.h"
-
-#define MX51_USB_CTRL_1_OFFSET          0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
-#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
-
-#define EFIKAMX_USB_HUB_RESET   IMX_GPIO_NR(1, 5)
-#define EFIKAMX_USBH1_STP       IMX_GPIO_NR(1, 27)
-
-#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
-
-#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
-
-static iomux_v3_cfg_t mx51efika_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-
-        /* SD 1 */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-
-        /* SD 2 */
-        MX51_PAD_SD2_CMD__SD2_CMD,
-        MX51_PAD_SD2_CLK__SD2_CLK,
-        MX51_PAD_SD2_DATA0__SD2_DATA0,
-        MX51_PAD_SD2_DATA1__SD2_DATA1,
-        MX51_PAD_SD2_DATA2__SD2_DATA2,
-        MX51_PAD_SD2_DATA3__SD2_DATA3,
-
-        /* SD/MMC WP/CD */
-        MX51_PAD_GPIO1_0__SD1_CD,
-        MX51_PAD_GPIO1_1__SD1_WP,
-        MX51_PAD_GPIO1_7__SD2_WP,
-        MX51_PAD_GPIO1_8__SD2_CD,
-
-        /* spi */
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,
-        MX51_PAD_CSPI1_SS1__GPIO4_25,
-        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-        MX51_PAD_GPIO1_6__GPIO1_6,
-
-        /* USB HOST1 */
-        MX51_PAD_USBH1_CLK__USBH1_CLK,
-        MX51_PAD_USBH1_DIR__USBH1_DIR,
-        MX51_PAD_USBH1_NXT__USBH1_NXT,
-        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-
-        /* USB HUB RESET */
-        MX51_PAD_GPIO1_5__GPIO1_5,
-
-        /* WLAN */
-        MX51_PAD_EIM_A22__GPIO2_16,
-        MX51_PAD_EIM_A16__GPIO2_10,
-
-        /* USB PHY RESET */
-        MX51_PAD_EIM_D27__GPIO2_9,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/* This function is board specific as the bit mask for the plldiv will also
- * be different for other Freescale SoCs, thus a common bitmask is not
- * possible and cannot get place in /plat-mxc/ehci.c.
- */
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_19_2_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
-}
-
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-        .init   = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-};
-
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-        iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *socregs_base;
-
-        mxc_iomux_v3_setup_pad(usbh1gpio);
-        gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
-        gpio_direction_output(EFIKAMX_USBH1_STP, 0);
-        msleep(1);
-        gpio_set_value(EFIKAMX_USBH1_STP, 1);
-        msleep(1);
-
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-        /* The clock for the USBH1 ULPI port will come externally */
-        /* from the PHY. */
-        v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
-        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
-                        socregs_base + MX51_USB_CTRL_1_OFFSET);
-
-        iounmap(usb_base);
-
-        gpio_free(EFIKAMX_USBH1_STP);
-        mxc_iomux_v3_setup_pad(usbh1stp);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static struct mxc_usbh_platform_data usbh1_config __initdata = {
-        .init   = initialize_usbh1_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static void mx51_efika_hubreset(void)
-{
-        gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
-        gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
-        msleep(1);
-        gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
-        msleep(1);
-        gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
-}
-
-static void __init mx51_efika_usb(void)
-{
-        mx51_efika_hubreset();
-
-        /* pulling it low, means no USB at all... */
-        gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
-        gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
-        msleep(1);
-        gpio_set_value(EFIKA_USB_PHY_RESET, 1);
-
-        usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-
-        imx51_add_mxc_ehci_otg(&dr_utmi_config);
-        if (usbh1_config.otg)
-                imx51_add_mxc_ehci_hs(1, &usbh1_config);
-}
-
-static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
-        {
-         .name = "u-boot",
-         .offset = 0,
-         .size = SZ_256K,
-        },
-        {
-          .name = "config",
-          .offset = MTDPART_OFS_APPEND,
-          .size = SZ_64K,
-        },
-};
-
-static struct flash_platform_data mx51_efika_spi_flash_data = {
-        .name           = "spi_flash",
-        .parts          = mx51_efika_spi_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
-        .type           = "sst25vf032b",
-};
-
-static struct regulator_consumer_supply sw1_consumers[] = {
-        {
-                .supply = "cpu_vcc",
-        }
-};
-
-static struct regulator_consumer_supply vdig_consumers[] = {
-        /* sgtl5000 */
-        REGULATOR_SUPPLY("VDDA", "1-000a"),
-        REGULATOR_SUPPLY("VDDD", "1-000a"),
-};
-
-static struct regulator_consumer_supply vvideo_consumers[] = {
-        /* sgtl5000 */
-        REGULATOR_SUPPLY("VDDIO", "1-000a"),
-};
-
-static struct regulator_consumer_supply vsd_consumers[] = {
-        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
-        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
-};
-
-static struct regulator_consumer_supply pwgt1_consumer[] = {
-        {
-                .supply = "pwgt1",
-        }
-};
-
-static struct regulator_consumer_supply pwgt2_consumer[] = {
-        {
-                .supply = "pwgt2",
-        }
-};
-
-static struct regulator_consumer_supply coincell_consumer[] = {
-        {
-                .supply = "coincell",
-        }
-};
-
-static struct regulator_init_data sw1_init = {
-        .constraints = {
-                .name = "SW1",
-                .min_uV = 600000,
-                .max_uV = 1375000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .valid_modes_mask = 0,
-                .always_on = 1,
-                .boot_on = 1,
-                .state_mem = {
-                        .uV = 850000,
-                        .mode = REGULATOR_MODE_NORMAL,
-                        .enabled = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
-        .consumer_supplies = sw1_consumers,
-};
-
-static struct regulator_init_data sw2_init = {
-        .constraints = {
-                .name = "SW2",
-                .min_uV = 900000,
-                .max_uV = 1850000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on = 1,
-                .boot_on = 1,
-                .state_mem = {
-                        .uV = 950000,
-                        .mode = REGULATOR_MODE_NORMAL,
-                        .enabled = 1,
-                },
-        }
-};
-
-static struct regulator_init_data sw3_init = {
-        .constraints = {
-                .name = "SW3",
-                .min_uV = 1100000,
-                .max_uV = 1850000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on = 1,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data sw4_init = {
-        .constraints = {
-                .name = "SW4",
-                .min_uV = 1100000,
-                .max_uV = 1850000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on = 1,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data viohi_init = {
-        .constraints = {
-                .name = "VIOHI",
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vusb_init = {
-        .constraints = {
-                .name = "VUSB",
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data swbst_init = {
-        .constraints = {
-                .name = "SWBST",
-        }
-};
-
-static struct regulator_init_data vdig_init = {
-        .constraints = {
-                .name = "VDIG",
-                .min_uV = 1050000,
-                .max_uV = 1800000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
-        .consumer_supplies = vdig_consumers,
-};
-
-static struct regulator_init_data vpll_init = {
-        .constraints = {
-                .name = "VPLL",
-                .min_uV = 1050000,
-                .max_uV = 1800000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vusb2_init = {
-        .constraints = {
-                .name = "VUSB2",
-                .min_uV = 2400000,
-                .max_uV = 2775000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vvideo_init = {
-        .constraints = {
-                .name = "VVIDEO",
-                .min_uV = 2775000,
-                .max_uV = 2775000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .apply_uV = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
-        .consumer_supplies = vvideo_consumers,
-};
-
-static struct regulator_init_data vaudio_init = {
-        .constraints = {
-                .name = "VAUDIO",
-                .min_uV = 2300000,
-                .max_uV = 3000000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vsd_init = {
-        .constraints = {
-                .name = "VSD",
-                .min_uV = 1800000,
-                .max_uV = 3150000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE,
-                .boot_on = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
-        .consumer_supplies = vsd_consumers,
-};
-
-static struct regulator_init_data vcam_init = {
-        .constraints = {
-                .name = "VCAM",
-                .min_uV = 2500000,
-                .max_uV = 3000000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
-                .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vgen1_init = {
-        .constraints = {
-                .name = "VGEN1",
-                .min_uV = 1200000,
-                .max_uV = 3150000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vgen2_init = {
-        .constraints = {
-                .name = "VGEN2",
-                .min_uV = 1200000,
-                .max_uV = 3150000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vgen3_init = {
-        .constraints = {
-                .name = "VGEN3",
-                .min_uV = 1800000,
-                .max_uV = 2900000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data gpo1_init = {
-        .constraints = {
-                .name = "GPO1",
-        }
-};
-
-static struct regulator_init_data gpo2_init = {
-        .constraints = {
-                .name = "GPO2",
-        }
-};
-
-static struct regulator_init_data gpo3_init = {
-        .constraints = {
-                .name = "GPO3",
-        }
-};
-
-static struct regulator_init_data gpo4_init = {
-        .constraints = {
-                .name = "GPO4",
-        }
-};
-
-static struct regulator_init_data pwgt1_init = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
-        .consumer_supplies = pwgt1_consumer,
-};
-
-static struct regulator_init_data pwgt2_init = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
-        .consumer_supplies = pwgt2_consumer,
-};
-
-static struct regulator_init_data vcoincell_init = {
-        .constraints = {
-                .name = "COINCELL",
-                .min_uV = 3000000,
-                .max_uV = 3000000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
-        .consumer_supplies = coincell_consumer,
-};
-
-static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
-        { .id = MC13892_SW1,            .init_data =  &sw1_init },
-        { .id = MC13892_SW2,            .init_data =  &sw2_init },
-        { .id = MC13892_SW3,            .init_data =  &sw3_init },
-        { .id = MC13892_SW4,            .init_data =  &sw4_init },
-        { .id = MC13892_SWBST,          .init_data =  &swbst_init },
-        { .id = MC13892_VIOHI,          .init_data =  &viohi_init },
-        { .id = MC13892_VPLL,           .init_data =  &vpll_init },
-        { .id = MC13892_VDIG,           .init_data =  &vdig_init },
-        { .id = MC13892_VSD,            .init_data =  &vsd_init },
-        { .id = MC13892_VUSB2,          .init_data =  &vusb2_init },
-        { .id = MC13892_VVIDEO,         .init_data =  &vvideo_init },
-        { .id = MC13892_VAUDIO,         .init_data =  &vaudio_init },
-        { .id = MC13892_VCAM,           .init_data =  &vcam_init },
-        { .id = MC13892_VGEN1,          .init_data =  &vgen1_init },
-        { .id = MC13892_VGEN2,          .init_data =  &vgen2_init },
-        { .id = MC13892_VGEN3,          .init_data =  &vgen3_init },
-        { .id = MC13892_VUSB,           .init_data =  &vusb_init },
-        { .id = MC13892_GPO1,           .init_data =  &gpo1_init },
-        { .id = MC13892_GPO2,           .init_data =  &gpo2_init },
-        { .id = MC13892_GPO3,           .init_data =  &gpo3_init },
-        { .id = MC13892_GPO4,           .init_data =  &gpo4_init },
-        { .id = MC13892_PWGT1SPI,       .init_data = &pwgt1_init },
-        { .id = MC13892_PWGT2SPI,       .init_data = &pwgt2_init },
-        { .id = MC13892_VCOINCELL,      .init_data = &vcoincell_init },
-};
-
-static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
-        .flags = MC13XXX_USE_RTC,
-        .regulators = {
-                .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
-                .regulators = mx51_efika_regulators,
-        },
-};
-
-static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
-        {
-                .modalias = "m25p80",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .platform_data = &mx51_efika_spi_flash_data,
-                .irq = -1,
-        },
-        {
-                .modalias = "mc13892",
-                .max_speed_hz = 1000000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .platform_data = &mx51_efika_mc13892_data,
-                /* irq number is run-time assigned */
-        },
-};
-
-static int mx51_efika_spi_cs[] = {
-        EFIKAMX_SPI_CS0,
-        EFIKAMX_SPI_CS1,
-};
-
-static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
-        .chipselect     = mx51_efika_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
-};
-
-void __init efika_board_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
-                                        ARRAY_SIZE(mx51efika_pads));
-        imx51_add_imx_uart(0, &uart_pdata);
-        mx51_efika_usb();
-
-        /* FIXME: comes from original code. check this. */
-        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
-                sw2_init.constraints.state_mem.uV = 1100000;
-        else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
-                sw2_init.constraints.state_mem.uV = 1250000;
-                sw1_init.constraints.state_mem.uV = 1000000;
-        }
-        if (machine_is_mx51_efikasb())
-                vgen1_init.constraints.max_uV = 1200000;
-
-        gpio_request(EFIKAMX_PMIC, "pmic irq");
-        gpio_direction_input(EFIKAMX_PMIC);
-        mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
-        spi_register_board_info(mx51_efika_spi_board_info,
-                ARRAY_SIZE(mx51_efika_spi_board_info));
-        imx51_add_ecspi(0, &mx51_efika_spi_pdata);
-
-        imx51_add_pata_imx();
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-        get_cpu_op = mx51_get_cpu_op;
-#endif
-}
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index ab98c6fec9eb..2ac43e1a2dfd 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -41,7 +41,7 @@ void __init imx_scu_map_io(void)
         scu_base = IMX_IO_ADDRESS(base);
 }
 
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit imx_secondary_init(unsigned int cpu)
 {
         /*
          * if any interrupts are already enabled for the primary
@@ -51,7 +51,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         gic_secondary_init(0);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         imx_set_cpu_jump(cpu, v7_secondary_startup);
         imx_enable_cpu(cpu, true);
@@ -62,7 +62,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
-void __init smp_init_cpus(void)
+static void __init imx_smp_init_cpus(void)
 {
         int i, ncores;
 
@@ -79,7 +79,17 @@ void imx_smp_prepare(void)
         scu_enable(scu_base);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
 {
         imx_smp_prepare();
 }
+
+struct smp_operations  imx_smp_ops __initdata = {
+        .smp_init_cpus          = imx_smp_init_cpus,
+        .smp_prepare_cpus       = imx_smp_prepare_cpus,
+        .smp_secondary_init     = imx_secondary_init,
+        .smp_boot_secondary     = imx_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = imx_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 3fa6c51390da..a432d4325f89 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -95,8 +95,8 @@ arch_initcall(integrator_init);
  *  UART0  7    6
  *  UART1  5    4
  */
-#define SC_CTRLC        IO_ADDRESS(INTEGRATOR_SC_CTRLC)
-#define SC_CTRLS        IO_ADDRESS(INTEGRATOR_SC_CTRLS)
+#define SC_CTRLC        __io_address(INTEGRATOR_SC_CTRLC)
+#define SC_CTRLS        __io_address(INTEGRATOR_SC_CTRLS)
 
 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 {
diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c
index fbb457779895..590c192cdf4d 100644
--- a/arch/arm/mach-integrator/cpu.c
+++ b/arch/arm/mach-integrator/cpu.c
@@ -25,10 +25,10 @@
 
 static struct cpufreq_driver integrator_driver;
 
-#define CM_ID   IO_ADDRESS(INTEGRATOR_HDR_ID)
-#define CM_OSC  IO_ADDRESS(INTEGRATOR_HDR_OSC)
-#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT)
-#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
+#define CM_ID   __io_address(INTEGRATOR_HDR_ID)
+#define CM_OSC  __io_address(INTEGRATOR_HDR_OSC)
+#define CM_STAT __io_address(INTEGRATOR_HDR_STAT)
+#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK)
 
 static const struct icst_params lclk_params = {
         .ref            = 24000000,
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
deleted file mode 100644
index 8de70de3dd0a..000000000000
--- a/arch/arm/mach-integrator/include/mach/io.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/*
- * WARNING: this has to mirror definitions in platform.h
- */
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
-
-#define __io(a)                 ((void __iomem *)(PCI_IO_VADDR + (a)))
-
-#endif
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index ec467baade09..4c0347526851 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -324,6 +324,10 @@
  */
 #define PHYS_PCI_V3_BASE                0x62000000
 
+#define PCI_MEMORY_VADDR                0xe8000000
+#define PCI_CONFIG_VADDR                0xec000000
+#define PCI_V3_VADDR                    0xed000000
+
 /* ------------------------------------------------------------------------
  *  Integrator Interrupt Controllers
  * ------------------------------------------------------------------------
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 3b2267529f5e..2215d96cd735 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -50,6 +50,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 
 #include <plat/fpga-irq.h>
@@ -73,7 +74,7 @@
  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
- * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
+ * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  * ef000000                     Cache flush
  * f1000000     10000000        Core module registers
  * f1100000     11000000        System controller registers
@@ -133,25 +134,20 @@ static struct map_desc ap_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = PCI_MEMORY_VADDR,
+                .virtual        = (unsigned long)PCI_MEMORY_VADDR,
                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = PCI_CONFIG_VADDR,
+                .virtual        = (unsigned long)PCI_CONFIG_VADDR,
                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = PCI_V3_VADDR,
+                .virtual        = (unsigned long)PCI_V3_VADDR,
                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
                 .length         = SZ_64K,
                 .type           = MT_DEVICE
-        }, {
-                .virtual        = PCI_IO_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE
         }
 };
 
@@ -159,6 +155,7 @@ static void __init ap_map_io(void)
 {
         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
         vga_base = PCI_MEMORY_VADDR;
+        pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
 }
 
 #define INTEGRATOR_SC_VALID_INT 0x003fffff
@@ -317,9 +314,9 @@ static void __init ap_init(void)
 /*
  * Where is the timer (VA)?
  */
-#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
-#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
-#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
+#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
+#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
+#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
 
 static unsigned long timer_reload;
 
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 82d5c837cc74..3df5fc369361 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -59,7 +59,7 @@
 
 #define INTCP_ETH_SIZE                  0x10
 
-#define INTCP_VA_CTRL_BASE              IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
+#define INTCP_VA_CTRL_BASE              __io_address(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG                 0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
@@ -265,8 +265,8 @@ static struct platform_device *intcp_devs[] __initdata = {
  */
 static unsigned int mmc_status(struct device *dev)
 {
-        unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
-        writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
+        unsigned int status = readl(__io_address(0xca000000 + 4));
+        writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8));
 
         return status & 8;
 }
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index b866880e82ac..bbeca59df66b 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -41,61 +41,61 @@
 /*
  * The V3 PCI interface chip in Integrator provides several windows from
  * local bus memory into the PCI memory areas.   Unfortunately, there
- * are not really enough windows for our usage, therefore we reuse 
+ * are not really enough windows for our usage, therefore we reuse
  * one of the windows for access to PCI configuration space.  The
  * memory map is as follows:
- * 
+ *
  * Local Bus Memory         Usage
- * 
+ *
  * 40000000 - 4FFFFFFF      PCI memory.  256M non-prefetchable
  * 50000000 - 5FFFFFFF      PCI memory.  256M prefetchable
  * 60000000 - 60FFFFFF      PCI IO.  16M
  * 61000000 - 61FFFFFF      PCI Configuration. 16M
- * 
+ *
  * There are three V3 windows, each described by a pair of V3 registers.
  * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
  * Base0 and Base1 can be used for any type of PCI memory access.   Base2
  * can be used either for PCI I/O or for I20 accesses.  By default, uHAL
  * uses this only for PCI IO space.
- * 
+ *
  * Normally these spaces are mapped using the following base registers:
- * 
+ *
  * Usage Local Bus Memory         Base/Map registers used
- * 
+ *
  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
  * Mem   50000000 - 5FFFFFFF      LB_BASE1/LB_MAP1
  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
  * Cfg   61000000 - 61FFFFFF
- * 
+ *
  * This means that I20 and PCI configuration space accesses will fail.
- * When PCI configuration accesses are needed (via the uHAL PCI 
+ * When PCI configuration accesses are needed (via the uHAL PCI
  * configuration space primitives) we must remap the spaces as follows:
- * 
+ *
  * Usage Local Bus Memory         Base/Map registers used
- * 
+ *
  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
  * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0
  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
  * Cfg   61000000 - 61FFFFFF      LB_BASE1/LB_MAP1
- * 
+ *
  * To make this work, the code depends on overlapping windows working.
- * The V3 chip translates an address by checking its range within 
+ * The V3 chip translates an address by checking its range within
  * each of the BASE/MAP pairs in turn (in ascending register number
  * order).  It will use the first matching pair.   So, for example,
  * if the same address is mapped by both LB_BASE0/LB_MAP0 and
- * LB_BASE1/LB_MAP1, the V3 will use the translation from 
+ * LB_BASE1/LB_MAP1, the V3 will use the translation from
  * LB_BASE0/LB_MAP0.
- * 
+ *
  * To allow PCI Configuration space access, the code enlarges the
  * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M.  This occludes
  * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
  * be remapped for use by configuration cycles.
- * 
- * At the end of the PCI Configuration space accesses, 
+ *
+ * At the end of the PCI Configuration space accesses,
  * LB_BASE1/LB_MAP1 is reset to map PCI Memory.  Finally the window
  * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
  * reveal the now restored LB_BASE1/LB_MAP1 window.
- * 
+ *
  * NOTE: We do not set up I2O mapping.  I suspect that this is only
  * for an intelligent (target) device.  Using I2O disables most of
  * the mappings into PCI memory.
@@ -127,8 +127,8 @@
  *
  * returns:     configuration address to play on the PCI bus
  *
- * To generate the appropriate PCI configuration cycles in the PCI 
- * configuration address space, you present the V3 with the following pattern 
+ * To generate the appropriate PCI configuration cycles in the PCI
+ * configuration address space, you present the V3 with the following pattern
  * (which is very nearly a type 1 (except that the lower two bits are 00 and
  * not 01).   In order for this mapping to work you need to set up one of
  * the local to PCI aperatures to 16Mbytes in length translating to
@@ -138,7 +138,7 @@
  *
  * Type 0:
  *
- *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
+ *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
@@ -150,7 +150,7 @@
  *
  * Type 1:
  *
- *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
+ *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
@@ -161,7 +161,7 @@
  *      15:11   Device number (5 bits)
  *      10:8    function number
  *       7:2    register number
- *  
+ *
  */
 static DEFINE_RAW_SPINLOCK(v3_lock);
 
@@ -181,7 +181,7 @@ static DEFINE_RAW_SPINLOCK(v3_lock);
 #undef V3_LB_BASE_PREFETCH
 #define V3_LB_BASE_PREFETCH 0
 
-static unsigned long v3_open_config_window(struct pci_bus *bus,
+static void __iomem *v3_open_config_window(struct pci_bus *bus,
                                            unsigned int devfn, int offset)
 {
         unsigned int address, mapaddress, busnr;
@@ -280,7 +280,7 @@ static void v3_close_config_window(void)
 static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
                           int size, u32 *val)
 {
-        unsigned long addr;
+        void __iomem *addr;
         unsigned long flags;
         u32 v;
 
@@ -311,7 +311,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
                            int size, u32 val)
 {
-        unsigned long addr;
+        void __iomem *addr;
         unsigned long flags;
 
         raw_spin_lock_irqsave(&v3_lock, flags);
@@ -374,12 +374,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
         }
 
         /*
-         * the IO resource for this bus
          * the mem resource for this bus
          * the prefetch mem resource for this bus
          */
-        pci_add_resource_offset(&sys->resources,
-                                &ioport_resource, sys->io_offset);
         pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
         pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
 
@@ -391,9 +388,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
  * means I can't get additional information on the reason for the pm2fb
  * problems.  I suppose I'll just have to mind-meld with the machine. ;)
  */
-#define SC_PCI     IO_ADDRESS(INTEGRATOR_SC_PCIENABLE)
-#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20)
-#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24)
+#define SC_PCI     __io_address(INTEGRATOR_SC_PCIENABLE)
+#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20)
+#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24)
 
 static int
 v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
@@ -498,7 +495,6 @@ void __init pci_v3_preinit(void)
         unsigned int temp;
         int ret;
 
-        pcibios_min_io = 0x6000;
         pcibios_min_mem = 0x00100000;
 
         /*
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
deleted file mode 100644
index f13188518025..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * iop13xx custom ioremap implementation
- * Copyright (c) 2005-2006, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a) __iop13xx_io(a)
-
-extern void __iomem * __iop13xx_io(unsigned long io_addr);
-
-#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index e190dcd7d72d..7480f58267aa 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -69,21 +69,11 @@ extern unsigned long get_iop_tick_rate(void);
  * 0x8000.0000 + 928M   0x2.8000.0000   (ioremap)       PCIE outbound memory window
  *
  * IO MAP
- * 0x1000 + 64K 0x0.fffb.1000   0xfec6.1000     PCIX outbound i/o window
- * 0x1000 + 64K 0x0.fffd.1000   0xfed7.1000     PCIE outbound i/o window
+ * 0x00000 + 64K        0x0.fffb.0000   0xfee0.0000     PCIX outbound i/o window
+ * 0x10000 + 64K        0x0.fffd.0000   0xfee1.0000     PCIE outbound i/o window
  */
-#define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
 #define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
-#define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
 #define IOP13XX_PCIX_LOWER_IO_BA      0x0UL /* OIOTVR */
-#define IOP13XX_PCIX_IO_BUS_OFFSET    0x1000UL
-#define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
-                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
-                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
-                                           (IOP13XX_PCIX_LOWER_IO_PA\
-                                           - IOP13XX_PCIX_LOWER_IO_VA))
 
 #define IOP13XX_PCIX_MEM_PHYS_OFFSET  0x100000000ULL
 #define IOP13XX_PCIX_MEM_WINDOW_SIZE  0x3a000000UL
@@ -103,20 +93,8 @@ extern unsigned long get_iop_tick_rate(void);
                                         IOP13XX_PCIX_LOWER_MEM_BA)
 
 /* PCI-E ranges */
-#define IOP13XX_PCIE_IO_WINDOW_SIZE      0x10000UL
 #define IOP13XX_PCIE_LOWER_IO_PA         0xfffd0000UL
-#define IOP13XX_PCIE_LOWER_IO_VA         0xfed70000UL
-#define IOP13XX_PCIE_LOWER_IO_BA         0x0UL  /* OIOTVR */
-#define IOP13XX_PCIE_IO_BUS_OFFSET       0x1000UL
-#define IOP13XX_PCIE_UPPER_IO_PA         (IOP13XX_PCIE_LOWER_IO_PA +\
-                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_UPPER_IO_VA         (IOP13XX_PCIE_LOWER_IO_VA +\
-                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_UPPER_IO_BA         (IOP13XX_PCIE_LOWER_IO_BA +\
-                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
-                                           (IOP13XX_PCIE_LOWER_IO_PA\
-                                           - IOP13XX_PCIE_LOWER_IO_VA))
+#define IOP13XX_PCIE_LOWER_IO_BA         0x10000UL  /* OIOTVR */
 
 #define IOP13XX_PCIE_MEM_PHYS_OFFSET     0x200000000ULL
 #define IOP13XX_PCIE_MEM_WINDOW_SIZE     0x3a000000UL
@@ -148,18 +126,16 @@ extern unsigned long get_iop_tick_rate(void);
  * IOP13XX chipset registers
  */
 #define IOP13XX_PMMR_PHYS_MEM_BASE         0xffd80000UL  /* PMMR phys. address */
-#define IOP13XX_PMMR_VIRT_MEM_BASE         0xfee80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_VIRT_MEM_BASE         (void __iomem *)(0xfee80000UL)  /* PMMR phys. address */
 #define IOP13XX_PMMR_MEM_WINDOW_SIZE       0x80000
 #define IOP13XX_PMMR_UPPER_MEM_VA          (IOP13XX_PMMR_VIRT_MEM_BASE +\
                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 #define IOP13XX_PMMR_UPPER_MEM_PA          (IOP13XX_PMMR_PHYS_MEM_BASE +\
                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
-#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
-                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
-                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
-#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
-                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
-                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
+                                           + IOP13XX_PMMR_PHYS_MEM_BASE)
+#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
+                                           + IOP13XX_PMMR_VIRT_MEM_BASE)
 #define IOP13XX_REG_ADDR32(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 #define IOP13XX_REG_ADDR16(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 #define IOP13XX_REG_ADDR8(reg)             (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
@@ -169,10 +145,10 @@ extern unsigned long get_iop_tick_rate(void);
 #define IOP13XX_PMMR_SIZE                  0x00080000
 
 /*=================== Defines for Platform Devices =====================*/
-#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
-#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
-#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
-#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
+#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
+#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
+#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
+#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
 
 #define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
 #define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index 1afa99ef97fa..7c032d0ab24a 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -16,12 +16,12 @@
 #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
 #define IOP13XX_PMMR_P_END   (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
 
-static inline dma_addr_t __virt_to_lbus(unsigned long x)
+static inline dma_addr_t __virt_to_lbus(void __iomem *x)
 {
         return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
 }
 
-static inline unsigned long __lbus_to_virt(dma_addr_t x)
+static inline void __iomem *__lbus_to_virt(dma_addr_t x)
 {
         return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
 }
@@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
 
 #define __arch_dma_to_virt(dev, addr)                                   \
         ({                                                              \
-                unsigned long __virt;                                   \
+                void * __virt;                                          \
                 dma_addr_t __dma = addr;                                \
                 if (is_lbus_device(dev) && __is_lbus_dma(__dma))        \
                         __virt = __lbus_to_virt(__dma);                 \
                 else                                                    \
-                        __virt = __phys_to_virt(__dma);                 \
-                (void *)__virt;                                         \
+                        __virt = (void *)__phys_to_virt(__dma);         \
+                __virt;                                                 \
         })
 
 #define __arch_virt_to_dma(dev, addr)                                   \
         ({                                                              \
-                unsigned long __virt = (unsigned long)addr;             \
+                void * __virt = addr;                                   \
                 dma_addr_t __dma;                                       \
                 if (is_lbus_device(dev) && __is_lbus_virt(__virt))      \
                         __dma = __virt_to_lbus(__virt);                 \
                 else                                                    \
-                        __dma = __virt_to_phys(__virt);                 \
+                        __dma = __virt_to_phys((unsigned long)__virt);  \
                 __dma;                                                  \
         })
 
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 3c364198db9c..183dc8b5511b 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,25 +23,6 @@
 
 #include "pci.h"
 
-void * __iomem __iop13xx_io(unsigned long io_addr)
-{
-        void __iomem * io_virt;
-
-        switch (io_addr) {
-        case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
-                io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr);
-                break;
-        case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
-                io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr);
-                break;
-        default:
-                BUG();
-        }
-
-        return io_virt;
-}
-EXPORT_SYMBOL(__iop13xx_io);
-
 static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
         size_t size, unsigned int mtype, void *caller)
 {
@@ -52,14 +33,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
                 if (unlikely(!iop13xx_atux_mem_base))
                         retval = NULL;
                 else
-                        retval = (void *)(iop13xx_atux_mem_base +
+                        retval = (iop13xx_atux_mem_base +
                                  (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
                 break;
         case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
                 if (unlikely(!iop13xx_atue_mem_base))
                         retval = NULL;
                 else
-                        retval = (void *)(iop13xx_atue_mem_base +
+                        retval = (iop13xx_atue_mem_base +
                                  (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
                 break;
         case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
@@ -67,14 +48,8 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
                                        (cookie - IOP13XX_PBI_LOWER_MEM_RA),
                                        size, mtype, __builtin_return_address(0));
                 break;
-        case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
-                retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
-                break;
-        case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
-                retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
-                break;
         case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
-                retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
+                retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
                 break;
         default:
                 retval = __arm_ioremap_caller(cookie, size, mtype,
@@ -99,9 +74,7 @@ static void __iop13xx_iounmap(volatile void __iomem *addr)
                     goto skip;
 
         switch ((u32) addr) {
-        case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
-        case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
-        case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
+        case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
                 goto skip;
         }
         __iounmap(addr);
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 861cb12ef436..9082b84aeebb 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
 u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
 static struct pci_bus *pci_bus_atux = 0;
 static struct pci_bus *pci_bus_atue = 0;
-u32 iop13xx_atue_mem_base;
-u32 iop13xx_atux_mem_base;
+void __iomem *iop13xx_atue_mem_base;
+void __iomem *iop13xx_atux_mem_base;
 size_t iop13xx_atue_mem_size;
 size_t iop13xx_atux_mem_size;
 
@@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void)
                                 }
 
                                 if (end) {
-                                        iop13xx_atux_mem_base =
-                                        (u32) __arm_ioremap_pfn(
+                                        iop13xx_atux_mem_base = __arm_ioremap_pfn(
                                         __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
                                         , 0, iop13xx_atux_mem_size, MT_DEVICE);
                                         if (!iop13xx_atux_mem_base) {
@@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void)
                                         }
                                 } else
                                         iop13xx_atux_mem_size = 0;
-                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
                                 __func__, atu, iop13xx_atux_mem_size,
                                 iop13xx_atux_mem_base);
                                 break;
@@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void)
                                 }
 
                                 if (end) {
-                                        iop13xx_atue_mem_base =
-                                        (u32) __arm_ioremap_pfn(
+                                        iop13xx_atue_mem_base = __arm_ioremap_pfn(
                                         __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
                                         , 0, iop13xx_atue_mem_size, MT_DEVICE);
                                         if (!iop13xx_atue_mem_base) {
@@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void)
                                         }
                                 } else
                                         iop13xx_atue_mem_size = 0;
-                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
                                 __func__, atu, iop13xx_atue_mem_size,
                                 iop13xx_atue_mem_base);
                                 break;
                         }
 
-                        printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
+                        printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
                         atu ? "ATUE" : "ATUX",
                         (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
                         SZ_1M,
@@ -970,7 +968,6 @@ void __init iop13xx_pci_init(void)
         __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
 
         /* Setup the Min Address for PCI memory... */
-        pcibios_min_io = 0;
         pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
 
         /* if Linux is given control of an ATU
@@ -1003,7 +1000,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
         if (nr > 1)
                 return 0;
 
-        res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
+        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
         if (!res)
                 panic("PCI: unable to alloc resources");
 
@@ -1042,17 +1039,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                                   << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
                 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
 
-                res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
-                res[0].end   = IOP13XX_PCIX_UPPER_IO_PA;
-                res[0].name  = "IQ81340 ATUX PCI I/O Space";
-                res[0].flags = IORESOURCE_IO;
+                pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
 
-                res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
-                res[1].end   = IOP13XX_PCIX_UPPER_MEM_RA;
-                res[1].name  = "IQ81340 ATUX PCI Memory Space";
-                res[1].flags = IORESOURCE_MEM;
+                res->start = IOP13XX_PCIX_LOWER_MEM_RA;
+                res->end   = IOP13XX_PCIX_UPPER_MEM_RA;
+                res->name  = "IQ81340 ATUX PCI Memory Space";
+                res->flags = IORESOURCE_MEM;
                 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
-                sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
                 break;
         case IOP13XX_INIT_ATU_ATUE:
                 /* Note: the function number field in the PCSR is ro */
@@ -1063,17 +1056,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
 
                 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
 
-                res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
-                res[0].end   = IOP13XX_PCIE_UPPER_IO_PA;
-                res[0].name  = "IQ81340 ATUE PCI I/O Space";
-                res[0].flags = IORESOURCE_IO;
+                pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
 
-                res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
-                res[1].end   = IOP13XX_PCIE_UPPER_MEM_RA;
-                res[1].name  = "IQ81340 ATUE PCI Memory Space";
-                res[1].flags = IORESOURCE_MEM;
+                res->start = IOP13XX_PCIE_LOWER_MEM_RA;
+                res->end   = IOP13XX_PCIE_UPPER_MEM_RA;
+                res->name  = "IQ81340 ATUE PCI Memory Space";
+                res->flags = IORESOURCE_MEM;
                 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
-                sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
                 sys->map_irq = iop13xx_pcie_map_irq;
                 break;
         default:
@@ -1081,11 +1070,9 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                 return 0;
         }
 
-        request_resource(&ioport_resource, &res[0]);
-        request_resource(&iomem_resource, &res[1]);
+        request_resource(&iomem_resource, res);
 
-        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h
index c70cf5b41e31..d45a80b3080e 100644
--- a/arch/arm/mach-iop13xx/pci.h
+++ b/arch/arm/mach-iop13xx/pci.h
@@ -1,6 +1,6 @@
 #include <linux/types.h>
 
-extern u32 iop13xx_atue_mem_base;
-extern u32 iop13xx_atux_mem_base;
+extern void __iomem *iop13xx_atue_mem_base;
+extern void __iomem *iop13xx_atux_mem_base;
 extern size_t iop13xx_atue_mem_size;
 extern size_t iop13xx_atux_mem_size;
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index daabb1fa6c2c..3181f61ea63e 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -36,20 +36,10 @@
  */
 static struct map_desc iop13xx_std_desc[] __initdata = {
         {    /* mem mapped registers */
-                .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
+                .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
                 .pfn     = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
                 .length  = IOP13XX_PMMR_SIZE,
                 .type    = MT_DEVICE,
-        }, { /* PCIE IO space */
-                .virtual = IOP13XX_PCIE_LOWER_IO_VA,
-                .pfn     = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
-                .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
-                .type    = MT_DEVICE,
-        }, { /* PCIX IO space */
-                .virtual = IOP13XX_PCIX_LOWER_IO_VA,
-                .pfn     = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
-                .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
-                .type    = MT_DEVICE,
         },
 };
 
@@ -81,8 +71,8 @@ static struct resource iop13xx_uart1_resources[] = {
 
 static struct plat_serial8250_port iop13xx_uart0_data[] = {
         {
-       .membase     = (char*)(IOP13XX_UART0_VIRT),
-       .mapbase     = (IOP13XX_UART0_PHYS),
+       .membase     = IOP13XX_UART0_VIRT,
+       .mapbase     = IOP13XX_UART0_PHYS,
        .irq         = IRQ_IOP13XX_UART0,
        .uartclk     = IOP13XX_UART_XTAL,
        .regshift    = 2,
@@ -94,8 +84,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = {
 
 static struct plat_serial8250_port iop13xx_uart1_data[] = {
         {
-       .membase     = (char*)(IOP13XX_UART1_VIRT),
-       .mapbase     = (IOP13XX_UART1_PHYS),
+       .membase     = IOP13XX_UART1_VIRT,
+       .mapbase     = IOP13XX_UART1_PHYS,
        .irq         = IRQ_IOP13XX_UART1,
        .uartclk     = IOP13XX_UART_XTAL,
        .regshift    = 2,
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index c15a100ba779..02e20c3912ba 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -183,7 +183,7 @@ static struct i2c_board_info __initdata glantank_i2c_devices[] = {
 
 static void glantank_power_off(void)
 {
-        __raw_writeb(0x01, 0xfe8d0004);
+        __raw_writeb(0x01, IOMEM(0xfe8d0004));
 
         while (1)
                 ;
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
deleted file mode 100644
index e2ada265bb8d..000000000000
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/io.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IO_H
-#define __IO_H
-
-#include <asm/hardware/iop3xx.h>
-
-#define IO_SPACE_LIMIT          0xffffffff
-#define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-
-#endif
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
deleted file mode 100644
index f7c1b6595660..000000000000
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/io.h
- *
- * Copyright (C) 2001  MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IO_H
-#define __IO_H
-
-#include <asm/hardware/iop3xx.h>
-
-#define IO_SPACE_LIMIT          0xffffffff
-#define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-
-#endif
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index a9f80943d01f..fdf91a160884 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx;
  *************************************************************************/
 static struct map_desc ixp4xx_io_desc[] __initdata = {
         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
-                .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
                 .type           = MT_DEVICE
         }, {    /* Expansion Bus Config Registers */
-                .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
                 .type           = MT_DEVICE
         }, {    /* PCI Registers */
-                .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
                 .type           = MT_DEVICE
         },
 #ifdef CONFIG_DEBUG_LL
         {       /* Debug UART mapping */
-                .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
index b2ef65db0e91..ebc0ba31ce85 100644
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -14,6 +14,7 @@
 #ifndef __ASM_ARCH_CPU_H__
 #define __ASM_ARCH_CPU_H__
 
+#include <linux/io.h>
 #include <asm/cputype.h>
 
 /* Processor id value in CP15 Register 0 */
@@ -37,7 +38,7 @@
 
 static inline u32 ixp4xx_read_feature_bits(void)
 {
-        u32 val = ~*IXP4XX_EXP_CFG2;
+        u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
 
         if (cpu_is_ixp42x_rev_a0())
                 return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
@@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void)
 
 static inline void ixp4xx_write_feature_bits(u32 value)
 {
-        *IXP4XX_EXP_CFG2 = ~value;
+        __raw_writel(~value, IXP4XX_EXP_CFG2);
 }
 
 #endif  /* _ASM_ARCH_CPU_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h
deleted file mode 100644
index ef37f2635b0e..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/gpio.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* empty */
-
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index 97c530f66e78..eb68b61ce975 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -49,21 +49,21 @@
  * Expansion BUS Configuration registers
  */
 #define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFE000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        IOMEM(0xFFBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
 
 /*
  * PCI Config registers
  */
 #define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
-#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        IOMEM(0xFFBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
 
 /*
  * Peripheral space
  */
 #define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBEB000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     IOMEM(0xFFBEB000)
 #define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
 
 /*
@@ -73,7 +73,7 @@
  * aligned so that it * can be used with the low-level debug code.
  */
 #define IXP4XX_DEBUG_UART_BASE_PHYS     (0xC8000000)
-#define IXP4XX_DEBUG_UART_BASE_VIRT     (0xffb00000)
+#define IXP4XX_DEBUG_UART_BASE_VIRT     IOMEM(0xffb00000)
 #define IXP4XX_DEBUG_UART_REGION_SIZE   (0x00001000)
 
 #define IXP4XX_EXP_CS0_OFFSET   0x00
@@ -92,7 +92,7 @@
 /*
  * Expansion Bus Controller registers.
  */
-#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
+#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
 
 #define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
 #define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a4e626..50bca5032b7e 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -94,6 +94,13 @@ config MACH_TS219_DT
           or MV6282. If you have the wrong one, the buttons will not
           work.
 
+config MACH_DOCKSTAR_DT
+        bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate FreeAgent Dockstar (Flattened Device Tree).
+
 config MACH_GOFLEXNET_DT
         bool "Seagate GoFlex Net (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
@@ -109,6 +116,20 @@ config MACH_LSXL_DT
           Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
           Flattened Device Tree.
 
+config MACH_IOMEGA_IX2_200_DT
+        bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Iomega StorCenter ix2-200 (Flattened Device Tree).
+
+config MACH_KM_KIRKWOOD_DT
+        bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
+
 config MACH_TS219
         bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a1cc46..294779f892d9 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -26,5 +26,8 @@ obj-$(CONFIG_MACH_ICONNECT_DT)		+= board-iconnect.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
 obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
+obj-$(CONFIG_MACH_DOCKSTAR_DT)          += board-dockstar.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)         += board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
+obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)       += board-km_kirkwood.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index a13299d758e1..760a0efe7580 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -1,14 +1,3 @@
    zreladdr-y   += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-
-dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
-dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
-dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
-dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
-dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
-dtb-$(CONFIG_MACH_TS219_DT)     += kirkwood-ts219-6281.dtb
-dtb-$(CONFIG_MACH_TS219_DT)     += kirkwood-ts219-6282.dtb
-dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
-dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
-dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index e9a7180863d9..8f0d162a1e1d 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
         /*
          * Setup MBUS dram target info.
          */
-        orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    (void __iomem *) DDR_WINDOW_CPU_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 4ab35065a144..43d16d6714b8 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -14,18 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/of.h>
 #include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio-fan.h>
-#include <linux/leds.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/kirkwood.h>
-#include <mach/bridge-regs.h>
 #include "common.h"
 #include "mpp.h"
 
@@ -67,29 +57,6 @@ static unsigned int dnskw_mpp_config[] __initdata = {
         0
 };
 
-/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
-static struct gpio_fan_speed dnskw_fan_speed[] = {
-        {    0,  0 },
-        { 3000,  1 },
-        { 6000,  2 },
-};
-static unsigned dnskw_fan_pins[] = {46, 45};
-
-static struct gpio_fan_platform_data dnskw_fan_data = {
-        .num_ctrl       = ARRAY_SIZE(dnskw_fan_pins),
-        .ctrl           = dnskw_fan_pins,
-        .num_speed      = ARRAY_SIZE(dnskw_fan_speed),
-        .speed          = dnskw_fan_speed,
-};
-
-static struct platform_device dnskw_fan_device = {
-        .name   = "gpio-fan",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &dnskw_fan_data,
-        },
-};
-
 static void dnskw_power_off(void)
 {
         gpio_set_value(36, 1);
@@ -114,8 +81,6 @@ void __init dnskw_init(void)
         kirkwood_ehci_init();
         kirkwood_ge00_init(&dnskw_ge00_data);
 
-        platform_device_register(&dnskw_fan_device);
-
         /* Register power-off GPIO. */
         if (gpio_request(36, "dnskw:power:off") == 0
             && gpio_direction_output(36, 0) == 0)
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
new file mode 100644
index 000000000000..f2fbb023e679
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dockstar.c
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-kirkwood/board-dockstar.c
+ *
+ * Seagate FreeAgent Dockstar Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Copied and modified for Seagate GoFlex Net support by
+ * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's
+ * GoFlex kernel patches.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <linux/platform_data/mmc-mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int dockstar_mpp_config[] __initdata = {
+        MPP29_GPIO,     /* USB Power Enable */
+        MPP46_GPIO,     /* LED green */
+        MPP47_GPIO,     /* LED orange */
+        0
+};
+
+void __init dockstar_dt_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(dockstar_mpp_config);
+
+        if (gpio_request(29, "USB Power Enable") != 0 ||
+            gpio_direction_output(29, 1) != 0)
+                pr_err("can't setup GPIO 29 (USB Power Enable)\n");
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&dockstar_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index aeb234d0d0e3..20af53a56c0e 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -30,7 +30,7 @@
 #include <asm/mach/map.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450de301..70c5a2882409 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -33,6 +33,7 @@ struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
         OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
         OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL),
+        OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1030000, "mv_crypto", NULL),
         {},
 };
 
@@ -60,7 +61,6 @@ static void __init kirkwood_dt_init(void)
         /* internal devices that every board has */
         kirkwood_xor0_init();
         kirkwood_xor1_init();
-        kirkwood_crypto_init();
 
 #ifdef CONFIG_KEXEC
         kexec_reinit = kirkwood_enable_pcie;
@@ -81,12 +81,21 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("qnap,ts219"))
                 qnap_dt_ts219_init();
 
+        if (of_machine_is_compatible("seagate,dockstar"))
+                dockstar_dt_init();
+
         if (of_machine_is_compatible("seagate,goflexnet"))
                 goflexnet_init();
 
         if (of_machine_is_compatible("buffalo,lsxl"))
                 lsxl_init();
 
+        if (of_machine_is_compatible("iom,ix2-200"))
+                iomega_ix2_200_init();
+
+        if (of_machine_is_compatible("keymile,km_kirkwood"))
+                km_kirkwood_init();
+
         of_platform_populate(NULL, kirkwood_dt_match_table,
                              kirkwood_auxdata_lookup, NULL);
 }
@@ -98,8 +107,11 @@ static const char *kirkwood_dt_board_compat[] = {
         "iom,iconnect",
         "raidsonic,ib-nas62x0",
         "qnap,ts219",
+        "seagate,dockstar",
         "seagate,goflexnet",
         "buffalo,lsxl",
+        "iom,ix2-200",
+        "keymile,km_kirkwood",
         NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
index 413e2c8ef5fe..001ca8c96980 100644
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -32,7 +32,7 @@
 #include <asm/mach/map.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index d7a9198ed300..d084b1e2943a 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -16,11 +16,8 @@
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/mtd/partitions.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
@@ -44,57 +41,12 @@ static unsigned int iconnect_mpp_config[] __initdata = {
         0
 };
 
-static struct mtd_partition iconnect_nand_parts[] = {
-        {
-                .name = "flash",
-                .offset = 0,
-                .size = MTDPART_SIZ_FULL,
-        },
-};
-
-/* yikes... theses are the original input buttons */
-/* but I'm not convinced by the sw event choices  */
-static struct gpio_keys_button iconnect_buttons[] = {
-        {
-                .type           = EV_SW,
-                .code           = SW_LID,
-                .gpio           = 12,
-                .desc           = "Reset Button",
-                .active_low     = 1,
-                .debounce_interval = 100,
-        }, {
-                .type           = EV_SW,
-                .code           = SW_TABLET_MODE,
-                .gpio           = 35,
-                .desc           = "OTB Button",
-                .active_low     = 1,
-                .debounce_interval = 100,
-        },
-};
-
-static struct gpio_keys_platform_data iconnect_button_data = {
-        .buttons        = iconnect_buttons,
-        .nbuttons       = ARRAY_SIZE(iconnect_buttons),
-};
-
-static struct platform_device iconnect_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev        = {
-                .platform_data  = &iconnect_button_data,
-        },
-};
-
 void __init iconnect_init(void)
 {
         kirkwood_mpp_conf(iconnect_mpp_config);
-        kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&iconnect_ge00_data);
-
-        platform_device_register(&iconnect_button_device);
 }
 
 static int __init iconnect_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
new file mode 100644
index 000000000000..158fb97d0397
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
+};
+
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+        MPP12_GPIO,                     /* Reset Button */
+        MPP14_GPIO,                     /* Power Button */
+        MPP15_GPIO,                     /* Backup LED (blue) */
+        MPP16_GPIO,                     /* Power LED (white) */
+        MPP35_GPIO,                     /* OTB Button */
+        MPP36_GPIO,                     /* Rebuild LED (white) */
+        MPP37_GPIO,                     /* Health LED (red) */
+        MPP38_GPIO,                     /* SATA LED brightness control 1 */
+        MPP39_GPIO,                     /* SATA LED brightness control 2 */
+        MPP40_GPIO,                     /* Backup LED brightness control 1 */
+        MPP41_GPIO,                     /* Backup LED brightness control 2 */
+        MPP42_GPIO,                     /* Power LED brightness control 1 */
+        MPP43_GPIO,                     /* Power LED brightness control 2 */
+        MPP44_GPIO,                     /* Health LED brightness control 1 */
+        MPP45_GPIO,                     /* Health LED brightness control 2 */
+        MPP46_GPIO,                     /* Rebuild LED brightness control 1 */
+        MPP47_GPIO,                     /* Rebuild LED brightness control 2 */
+        0
+};
+
+void __init iomega_ix2_200_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+
+        kirkwood_ehci_init();
+
+        kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
new file mode 100644
index 000000000000..f7d32834b757
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * arch/arm/mach-kirkwood/board-km_kirkwood.c
+ *
+ * Keymile km_kirkwood Reference Desing Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int km_kirkwood_mpp_config[] __initdata = {
+        MPP8_GPIO,      /* I2C SDA */
+        MPP9_GPIO,      /* I2C SCL */
+        0
+};
+
+void __init km_kirkwood_init(void)
+{
+        struct clk *sata_clk;
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(km_kirkwood_mpp_config);
+
+        /*
+         * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
+         * SATA bits (14-15) of the Clock Gating Control Register. Since these
+         * devices are also not present in this variant, their clocks get
+         * disabled because unused when clk_disable_unused() gets called.
+         * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
+         */
+        sata_clk = clk_get_sys("sata_mv.0", "0");
+        if (!IS_ERR(sata_clk))
+                sata_clk->flags |= CLK_IGNORE_UNUSED;
+        sata_clk = clk_get_sys("sata_mv.0", "1");
+        if (!IS_ERR(sata_clk))
+                sata_clk->flags |= CLK_IGNORE_UNUSED;
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&km_kirkwood_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 1201191d7f1b..3991077f58a2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -26,15 +26,15 @@
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-kirkwood.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/mvsdio.h>
-#include <plat/orion_nand.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/mmc-mvsdio.h>
+#include <linux/platform_data/mtd-orion_nand.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/common.h>
 #include <plat/time.h>
 #include <plat/addr-map.h>
-#include <plat/mv_xor.h>
+#include <linux/platform_data/dma-mv_xor.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -42,17 +42,7 @@
  ****************************************************************************/
 static struct map_desc kirkwood_io_desc[] __initdata = {
         {
-                .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
-                .length         = KIRKWOOD_PCIE_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
-                .length         = KIRKWOOD_PCIE1_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = KIRKWOOD_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
                 .length         = KIRKWOOD_REGS_SIZE,
                 .type           = MT_DEVICE,
@@ -215,8 +205,7 @@ static struct clk *tclk;
 
 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
 {
-        return clk_register_gate(NULL, name, "tclk", 0,
-                                 (void __iomem *)CLOCK_GATING_CTRL,
+        return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
                                  bit_idx, 0, &gating_lock);
 }
 
@@ -225,8 +214,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
                                                     void (*fn_en)(void),
                                                     void (*fn_dis)(void))
 {
-        return clk_register_gate_fn(NULL, name, "tclk", 0,
-                                    (void __iomem *)CLOCK_GATING_CTRL,
+        return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
                                     bit_idx, 0, &gating_lock, fn_en, fn_dis);
 }
 
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1abfdca..bcffd7ca1ca2 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -82,6 +82,12 @@ void ib62x0_init(void);
 static inline void ib62x0_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DOCKSTAR_DT
+void dockstar_dt_init(void);
+#else
+static inline void dockstar_dt_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_GOFLEXNET_DT
 void goflexnet_init(void);
 #else
@@ -94,6 +100,18 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+
+#ifdef CONFIG_MACH_KM_KIRKWOOD_DT
+void km_kirkwood_init(void);
+#else
+static inline void km_kirkwood_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index 6e1bac929ab5..2c1a453df201 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <mach/leds-ns2.h>
+#include <linux/platform_data/leds-kirkwood-ns2.h>
 #include "common.h"
 #include "mpp.h"
 #include "lacie_v2-common.h"
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index be90b7d0e10b..c49b177c1523 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -18,7 +18,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 61d9a552a054..23dcb19cc2a7 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -19,7 +19,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index bdaed3867d13..7cb55f982243 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -19,7 +19,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index a115142f8690..5c82b7dce4e2 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -13,37 +13,37 @@
 
 #include <mach/kirkwood.h>
 
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0100)
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0100)
 #define CPU_CONFIG_ERROR_PROP   0x00000004
 
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define CPU_RESET               0x00000002
 
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define WDT_RESET_OUT_EN        0x00000002
 #define SOFT_RESET_OUT_EN       0x00000004
 
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
 
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
 #define WDT_INT_REQ             0x0008
 
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF       0x0000
 #define IRQ_MASK_LOW_OFF        0x0004
 #define IRQ_CAUSE_HIGH_OFF      0x0010
 #define IRQ_MASK_HIGH_OFF       0x0014
 
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
-#define L2_CONFIG_REG           (BRIDGE_VIRT_BASE | 0x0128)
+#define L2_CONFIG_REG           (BRIDGE_VIRT_BASE + 0x0128)
 #define L2_WRITETHROUGH         0x00000010
 
-#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE | 0x11c)
+#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE + 0x11c)
 #define CGC_BIT_GE0             (0)
 #define CGC_BIT_PEX0            (2)
 #define CGC_BIT_USB0            (3)
diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h
deleted file mode 100644
index 84f340b546c0..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
deleted file mode 100644
index 5d0ab61700d2..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "kirkwood.h"
-
-#define IO_SPACE_LIMIT          0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE)
-                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
-}
-
-#define __io(a)                 __io(a)
-
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index c5b68510776b..041653a04a9c 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -37,17 +37,15 @@
 #define KIRKWOOD_NAND_MEM_SIZE          SZ_1K
 
 #define KIRKWOOD_PCIE1_IO_PHYS_BASE     0xf3000000
-#define KIRKWOOD_PCIE1_IO_VIRT_BASE     0xfef00000
-#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00100000
-#define KIRKWOOD_PCIE1_IO_SIZE          SZ_1M
+#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00010000
+#define KIRKWOOD_PCIE1_IO_SIZE          SZ_64K
 
 #define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfee00000
 #define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
-#define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
+#define KIRKWOOD_PCIE_IO_SIZE           SZ_64K
 
 #define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE         0xfed00000
+#define KIRKWOOD_REGS_VIRT_BASE         IOMEM(0xfed00000)
 #define KIRKWOOD_REGS_SIZE              SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
@@ -61,61 +59,61 @@
 /*
  * Register Map
  */
-#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
-#define DDR_OPERATION_BASE      (DDR_VIRT_BASE | 0x1418)
-
-#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
-#define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
-#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE | 0x0100)
-#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE | 0x0140)
-#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
-#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
-#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
-
-#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
-#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE | 0x20000)
-
-#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
-
-#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
-#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE | 0x70)
-#define PCIE_STATUS             (PCIE_VIRT_BASE | 0x1a04)
-#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
-#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE | 0x70)
-#define PCIE1_STATUS            (PCIE1_VIRT_BASE | 0x1a04)
-
-#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
-
-#define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60800)
-#define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60800)
-#define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60900)
-#define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60900)
-#define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
-#define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
-#define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
-#define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
-
-#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
-
-#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
-#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
-#define SATA0_IF_CTRL           (SATA_VIRT_BASE | 0x2050)
-#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE | 0x2330)
-#define SATA1_IF_CTRL           (SATA_VIRT_BASE | 0x4050)
-#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE | 0x4330)
-
-#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
-
-#define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0xA0000)
-#define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0xA0000)
+#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
+#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE + 0x1500)
+#define DDR_OPERATION_BASE      (DDR_VIRT_BASE + 0x1418)
+
+#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
+#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
+#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE + 0x0030)
+#define  DEVICE_ID              (DEV_BUS_VIRT_BASE + 0x0034)
+#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE + 0x0100)
+#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x0140)
+#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0300)
+#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0600)
+#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x1000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
+
+#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
+#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
+
+#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
+
+#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
+#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE + 0x70)
+#define PCIE_STATUS             (PCIE_VIRT_BASE + 0x1a04)
+#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
+#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE + 0x70)
+#define PCIE1_STATUS            (PCIE1_VIRT_BASE + 0x1a04)
+
+#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
+
+#define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
+#define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
+#define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
+#define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
+#define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
+#define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
+#define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
+#define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
+
+#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
+#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
+
+#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
+#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
+#define SATA0_IF_CTRL           (SATA_VIRT_BASE + 0x2050)
+#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE + 0x2330)
+#define SATA1_IF_CTRL           (SATA_VIRT_BASE + 0x4050)
+#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE + 0x4330)
+
+#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
+
+#define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
+#define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
 
 /*
  * Supported devices and revisions.
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 720063ffa19d..884703535a0a 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -10,7 +10,9 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
+#include <plat/orion-gpio.h>
 #include <plat/irq.h>
 
 static int __initdata gpio0_irqs[4] = {
@@ -29,14 +31,14 @@ static int __initdata gpio1_irqs[4] = {
 
 void __init kirkwood_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
         /*
          * Initialize gpiolib for GPIOs 0-49.
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0,
                         IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
-        orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
                         IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
 }
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index e6bba01bae38..88b0788bacae 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -34,7 +34,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <mach/leds-ns2.h>
+#include <linux/platform_data/leds-kirkwood-ns2.h>
 #include "common.h"
 #include "mpp.h"
 #include "lacie_v2-common.h"
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 31ae8de34e93..a3b091470b8a 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <mach/leds-netxbig.h>
+#include <linux/platform_data/leds-kirkwood-netxbig.h>
 #include "common.h"
 #include "mpp.h"
 #include "lacie_v2-common.h"
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 7e99c3f340fc..134ef50d58fc 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -20,7 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 6e8b2efa3c35..ec544918b12c 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void)
 void kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
         kirkwood_enable_pcie();
-        *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
-        *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+        *dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
+        *rev = orion_pcie_rev(PCIE_VIRT_BASE);
 }
 
 struct pcie_port {
@@ -56,7 +56,7 @@ struct pcie_port {
         void __iomem            *base;
         spinlock_t              conf_lock;
         int                     irq;
-        struct resource         res[2];
+        struct resource         res;
 };
 
 static int pcie_port_map[2];
@@ -133,46 +133,30 @@ static struct pci_ops pcie_ops = {
 
 static void __init pcie0_ioresources_init(struct pcie_port *pp)
 {
-        pp->base = (void __iomem *)PCIE_VIRT_BASE;
+        pp->base = PCIE_VIRT_BASE;
         pp->irq = IRQ_KIRKWOOD_PCIE;
 
         /*
-         * IORESOURCE_IO
-         */
-        pp->res[0].name = "PCIe 0 I/O Space";
-        pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-        pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-        pp->res[0].flags = IORESOURCE_IO;
-
-        /*
          * IORESOURCE_MEM
          */
-        pp->res[1].name = "PCIe 0 MEM";
-        pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
-        pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-        pp->res[1].flags = IORESOURCE_MEM;
+        pp->res.name = "PCIe 0 MEM";
+        pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+        pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+        pp->res.flags = IORESOURCE_MEM;
 }
 
 static void __init pcie1_ioresources_init(struct pcie_port *pp)
 {
-        pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+        pp->base = PCIE1_VIRT_BASE;
         pp->irq = IRQ_KIRKWOOD_PCIE1;
 
         /*
-         * IORESOURCE_IO
-         */
-        pp->res[0].name = "PCIe 1 I/O Space";
-        pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
-        pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
-        pp->res[0].flags = IORESOURCE_IO;
-
-        /*
          * IORESOURCE_MEM
          */
-        pp->res[1].name = "PCIe 1 MEM";
-        pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
-        pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
-        pp->res[1].flags = IORESOURCE_MEM;
+        pp->res.name = "PCIe 1 MEM";
+        pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+        pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+        pp->res.flags = IORESOURCE_MEM;
 }
 
 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
@@ -197,23 +181,21 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
         case 0:
                 kirkwood_enable_pcie_clk("0");
                 pcie0_ioresources_init(pp);
+                pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
                 break;
         case 1:
                 kirkwood_enable_pcie_clk("1");
                 pcie1_ioresources_init(pp);
+                pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE);
                 break;
         default:
                 panic("PCIe setup: invalid controller %d", index);
         }
 
-        if (request_resource(&ioport_resource, &pp->res[0]))
-                panic("Request PCIe%d IO resource failed\n", index);
-        if (request_resource(&iomem_resource, &pp->res[1]))
+        if (request_resource(&iomem_resource, &pp->res))
                 panic("Request PCIe%d Memory resource failed\n", index);
 
-        sys->io_offset = 0;
-        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
-        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
 
         /*
          * Generic PCIe unit setup.
@@ -273,11 +255,11 @@ static struct hw_pci kirkwood_pci __initdata = {
         .map_irq        = kirkwood_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
         printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
 
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                 printk(KERN_INFO "link up\n");
                 pcie_port_map[num_pcie_ports++] = index;
         } else
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index f742a66a7045..19072c84008f 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -19,6 +19,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 
 #define RD88F6192_GPIO_USB_VBUS         10
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index ef922079348b..9717101a7437 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -20,7 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 4ea70e5f7137..28d0abaf4bd9 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -19,7 +19,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 5bbca2680442..367a9400f532 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -20,6 +20,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void)
                  * (Marvell 88sx7042/sata_mv) is known to stop working
                  * after a few minutes.
                  */
-                orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
+                orion_pcie_reset(PCIE_VIRT_BASE);
 
                 kirkwood_pcie_id(&dev, &rev);
                 if (dev == MV88F6282_DEV_ID)
diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c
index 7f3f24053a00..ddb24222918e 100644
--- a/arch/arm/mach-ks8695/cpu.c
+++ b/arch/arm/mach-ks8695/cpu.c
@@ -36,7 +36,7 @@
 
 static struct __initdata map_desc ks8695_io_desc[] = {
         {
-                .virtual        = KS8695_IO_VA,
+                .virtual        = (unsigned long)KS8695_IO_VA,
                 .pfn            = __phys_to_pfn(KS8695_IO_PA),
                 .length         = KS8695_IO_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h
index 5e0c388143da..5090338c0db2 100644
--- a/arch/arm/mach-ks8695/include/mach/hardware.h
+++ b/arch/arm/mach-ks8695/include/mach/hardware.h
@@ -33,7 +33,7 @@
  * head debug code as the initial MMU setup only deals in L1 sections.
  */
 #define KS8695_IO_PA            0x03F00000
-#define KS8695_IO_VA            0xF0000000
+#define KS8695_IO_VA            IOMEM(0xF0000000)
 #define KS8695_IO_SIZE          SZ_1M
 
 #define KS8695_PCIMEM_PA        0x60000000
diff --git a/arch/arm/mach-ks8695/include/mach/regs-timer.h b/arch/arm/mach-ks8695/include/mach/regs-timer.h
deleted file mode 100644
index e620cda99d2d..000000000000
--- a/arch/arm/mach-ks8695/include/mach/regs-timer.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/regs-timer.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - Timer registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_TIMER_H
-#define KS8695_TIMER_H
-
-#define KS8695_TMR_OFFSET       (0xF0000 + 0xE400)
-#define KS8695_TMR_VA           (KS8695_IO_VA + KS8695_TMR_OFFSET)
-#define KS8695_TMR_PA           (KS8695_IO_PA + KS8695_TMR_OFFSET)
-
-
-/*
- * Timer registers
- */
-#define KS8695_TMCON            (0x00)          /* Timer Control Register */
-#define KS8695_T1TC             (0x04)          /* Timer 1 Timeout Count Register */
-#define KS8695_T0TC             (0x08)          /* Timer 0 Timeout Count Register */
-#define KS8695_T1PD             (0x0C)          /* Timer 1 Pulse Count Register */
-#define KS8695_T0PD             (0x10)          /* Timer 0 Pulse Count Register */
-
-
-/* Timer Control Register */
-#define TMCON_T1EN              (1 << 1)        /* Timer 1 Enable */
-#define TMCON_T0EN              (1 << 0)        /* Timer 0 Enable */
-
-/* Timer0 Timeout Counter Register */
-#define T0TC_WATCHDOG           (0xff)          /* Enable watchdog mode */
-
-
-#endif
diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h
index 9495cb4d701a..8879d610308a 100644
--- a/arch/arm/mach-ks8695/include/mach/uncompress.h
+++ b/arch/arm/mach-ks8695/include/mach/uncompress.h
@@ -19,15 +19,15 @@
 
 static void putc(char c)
 {
-        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
+        while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
                 barrier();
 
-        __raw_writel(c, KS8695_UART_PA + KS8695_URTH);
+        __raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH);
 }
 
 static inline void flush(void)
 {
-        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
+        while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
                 barrier();
 }
 
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index ec783a3070ae..46c84bc7792c 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -25,53 +25,98 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
-#include <mach/regs-timer.h>
 #include <mach/regs-irq.h>
 
 #include "generic.h"
 
+#define KS8695_TMR_OFFSET       (0xF0000 + 0xE400)
+#define KS8695_TMR_VA           (KS8695_IO_VA + KS8695_TMR_OFFSET)
+#define KS8695_TMR_PA           (KS8695_IO_PA + KS8695_TMR_OFFSET)
+
 /*
- * Returns number of ms since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
+ * Timer registers
  */
-static unsigned long ks8695_gettimeoffset (void)
+#define KS8695_TMCON            (0x00)          /* Timer Control Register */
+#define KS8695_T1TC             (0x04)          /* Timer 1 Timeout Count Register */
+#define KS8695_T0TC             (0x08)          /* Timer 0 Timeout Count Register */
+#define KS8695_T1PD             (0x0C)          /* Timer 1 Pulse Count Register */
+#define KS8695_T0PD             (0x10)          /* Timer 0 Pulse Count Register */
+
+/* Timer Control Register */
+#define TMCON_T1EN              (1 << 1)        /* Timer 1 Enable */
+#define TMCON_T0EN              (1 << 0)        /* Timer 0 Enable */
+
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG           (0xff)          /* Enable watchdog mode */
+
+static void ks8695_set_mode(enum clock_event_mode mode,
+                            struct clock_event_device *evt)
 {
-        unsigned long elapsed, tick2, intpending;
+        u32 tmcon;
 
-        /*
-         * Get the current number of ticks.  Note that there is a race
-         * condition between us reading the timer and checking for an
-         * interrupt.  We solve this by ensuring that the counter has not
-         * reloaded between our two reads.
-         */
-        elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
-        do {
-                tick2 = elapsed;
-                intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
-                elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
-        } while (elapsed > tick2);
-
-        /* Convert to number of ticks expired (not remaining) */
-        elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
-
-        /* Is interrupt pending?  If so, then timer has been reloaded already. */
-        if (intpending)
-                elapsed += (CLOCK_TICK_RATE / HZ);
-
-        /* Convert ticks to usecs */
-        return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
+        if (mode == CLOCK_EVT_FEAT_PERIODIC) {
+                u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
+                u32 half = DIV_ROUND_CLOSEST(rate, 2);
+
+                /* Disable timer 1 */
+                tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+                tmcon &= ~TMCON_T1EN;
+                writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+                /* Both registers need to count down */
+                writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+                writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+
+                /* Re-enable timer1 */
+                tmcon |= TMCON_T1EN;
+                writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+        }
 }
 
+static int ks8695_set_next_event(unsigned long cycles,
+                                 struct clock_event_device *evt)
+
+{
+        u32 half = DIV_ROUND_CLOSEST(cycles, 2);
+        u32 tmcon;
+
+        /* Disable timer 1 */
+        tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+        tmcon &= ~TMCON_T1EN;
+        writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+        /* Both registers need to count down */
+        writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+        writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+
+        /* Re-enable timer1 */
+        tmcon |= TMCON_T1EN;
+        writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+        return 0;
+}
+
+static struct clock_event_device clockevent_ks8695 = {
+        .name           = "ks8695_t1tc",
+        .rating         = 300, /* Reasonably fast and accurate clock event */
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+        .set_next_event = ks8695_set_next_event,
+        .set_mode       = ks8695_set_mode,
+};
+
 /*
  * IRQ handler for the timer.
  */
 static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
 {
-        timer_tick();
+        struct clock_event_device *evt = &clockevent_ks8695;
+
+        evt->event_handler(evt);
         return IRQ_HANDLED;
 }
 
@@ -83,18 +128,22 @@ static struct irqaction ks8695_timer_irq = {
 
 static void ks8695_timer_setup(void)
 {
-        unsigned long tmout = CLOCK_TICK_RATE / HZ;
         unsigned long tmcon;
 
-        /* disable timer1 */
-        tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
-        __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
-
-        __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
-        __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
+        /* Disable timer 0 and 1 */
+        tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+        tmcon &= ~TMCON_T0EN;
+        tmcon &= ~TMCON_T1EN;
+        writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
 
-        /* re-enable timer1 */
-        __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+        /*
+         * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles
+         * (one on each counter) maximum 2*2^32, but the API will only
+         * accept up to a 32bit full word (0xFFFFFFFFU).
+         */
+        clockevents_config_and_register(&clockevent_ks8695,
+                                        KS8695_CLOCK_RATE, 2,
+                                        0xFFFFFFFFU);
 }
 
 static void __init ks8695_timer_init (void)
@@ -107,8 +156,6 @@ static void __init ks8695_timer_init (void)
 
 struct sys_timer ks8695_timer = {
         .init           = ks8695_timer_init,
-        .offset         = ks8695_gettimeoffset,
-        .resume         = ks8695_timer_setup,
 };
 
 void ks8695_restart(char mode, const char *cmd)
@@ -119,12 +166,12 @@ void ks8695_restart(char mode, const char *cmd)
                 soft_restart(0);
 
         /* disable timer0 */
-        reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
-        __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+        reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+        writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
 
         /* enable watchdog mode */
-        __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
+        writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
 
         /* re-enable timer0 */
-        __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+        writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
 }
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
index 697323b5f92d..d7392a475247 100644
--- a/arch/arm/mach-lpc32xx/Makefile.boot
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -1,5 +1,3 @@
    zreladdr-y   += 0x80008000
 params_phys-y   := 0x80000100
 initrd_phys-y   := 0x82000000
-
-dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index a48dc2dec485..0d4db8c544b5 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -177,25 +177,25 @@ u32 clk_get_pclk_div(void)
 
 static struct map_desc lpc32xx_io_desc[] __initdata = {
         {
-                .virtual        = IO_ADDRESS(LPC32XX_AHB0_START),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
                 .pfn            = __phys_to_pfn(LPC32XX_AHB0_START),
                 .length         = LPC32XX_AHB0_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = IO_ADDRESS(LPC32XX_AHB1_START),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
                 .pfn            = __phys_to_pfn(LPC32XX_AHB1_START),
                 .length         = LPC32XX_AHB1_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = IO_ADDRESS(LPC32XX_FABAPB_START),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
                 .pfn            = __phys_to_pfn(LPC32XX_FABAPB_START),
                 .length         = LPC32XX_FABAPB_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = IO_ADDRESS(LPC32XX_IRAM_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
                 .pfn            = __phys_to_pfn(LPC32XX_IRAM_BASE),
                 .length         = (LPC32XX_IRAM_BANK_SIZE * 2),
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
index 33e1dde37bd9..69065de97a3d 100644
--- a/arch/arm/mach-lpc32xx/include/mach/hardware.h
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -25,7 +25,7 @@
 /*
  * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
  */
-#define IO_ADDRESS(x)   (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
+#define IO_ADDRESS(x)   IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
                          IO_BASE)
 
 #define io_p2v(x)       ((void __iomem *) (unsigned long) IO_ADDRESS(x))
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 5b1cc35e6fba..3c6332753358 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -283,21 +283,25 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
         case IRQ_TYPE_EDGE_RISING:
                 /* Rising edge sensitive */
                 __lpc32xx_set_irq_type(d->hwirq, 1, 1);
+                __irq_set_handler_locked(d->hwirq, handle_edge_irq);
                 break;
 
         case IRQ_TYPE_EDGE_FALLING:
                 /* Falling edge sensitive */
                 __lpc32xx_set_irq_type(d->hwirq, 0, 1);
+                __irq_set_handler_locked(d->hwirq, handle_edge_irq);
                 break;
 
         case IRQ_TYPE_LEVEL_LOW:
                 /* Low level sensitive */
                 __lpc32xx_set_irq_type(d->hwirq, 0, 0);
+                __irq_set_handler_locked(d->hwirq, handle_level_irq);
                 break;
 
         case IRQ_TYPE_LEVEL_HIGH:
                 /* High level sensitive */
                 __lpc32xx_set_irq_type(d->hwirq, 1, 0);
+                __irq_set_handler_locked(d->hwirq, handle_level_irq);
                 break;
 
         /* Other modes are not supported */
@@ -305,9 +309,6 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
                 return -EINVAL;
         }
 
-        /* Ok to use the level handler for all types */
-        irq_set_handler(d->hwirq, handle_level_irq);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index b07dcc90829d..8f2a2f8712d7 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -37,6 +37,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/clk.h>
+#include <linux/mtd/lpc32xx_slc.h>
+#include <linux/mtd/lpc32xx_mlc.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -223,6 +225,14 @@ static struct mmci_platform_data lpc32xx_mmci_data = {
          * gather, and the MMCI driver doesn't do it this way */
 };
 
+static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
+        .dma_filter = pl08x_filter_id,
+};
+
+static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
+        .dma_filter = pl08x_filter_id,
+};
+
 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
         OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
@@ -230,6 +240,10 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
         OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
                        &lpc32xx_mmci_data),
+        OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
+                       &lpc32xx_slc_data),
+        OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
+                       &lpc32xx_mlc_data),
         { }
 };
 
@@ -253,12 +267,6 @@ static void __init lpc3250_machine_init(void)
 
         of_platform_populate(NULL, of_default_bus_match_table,
                              lpc32xx_auxdata_lookup, NULL);
-
-        /* Register GPIOs used on this board */
-        if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
-                pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
-        else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
-                pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
 }
 
 static char const *lpc32xx_dt_compat[] __initdata = {
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 7fddd01b85b9..d697d07a1bf0 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -108,18 +108,21 @@ endmenu
 config CPU_PXA168
         bool
         select CPU_MOHAWK
+        select COMMON_CLK
         help
           Select code specific to PXA168
 
 config CPU_PXA910
         bool
         select CPU_MOHAWK
+        select COMMON_CLK
         help
           Select code specific to PXA910
 
 config CPU_MMP2
         bool
         select CPU_PJ4
+        select COMMON_CLK
         help
           Select code specific to MMP2. MMP2 is ARMv7 compatible.
 
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index b786f7e6cd1f..095c155d6fb8 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,13 +2,19 @@
 # Makefile for Marvell's PXA168 processors line
 #
 
-obj-y                           += common.o clock.o devices.o time.o irq.o
+obj-y                           += common.o devices.o time.o irq.o
 
 # SoC support
 obj-$(CONFIG_CPU_PXA168)        += pxa168.o
 obj-$(CONFIG_CPU_PXA910)        += pxa910.o
 obj-$(CONFIG_CPU_MMP2)          += mmp2.o sram.o
 
+ifeq ($(CONFIG_COMMON_CLK), )
+obj-y                           += clock.o
+obj-$(CONFIG_CPU_PXA168)        += clock-pxa168.o
+obj-$(CONFIG_CPU_PXA910)        += clock-pxa910.o
+obj-$(CONFIG_CPU_MMP2)          += clock-mmp2.o
+endif
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_CPU_PXA910)        += pm-pxa910.o
 obj-$(CONFIG_CPU_MMP2)          += pm-mmp2.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 223090b1444d..e5dba9c5dc54 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -27,7 +27,7 @@
 #include <mach/irqs.h>
 #include <video/pxa168fb.h>
 #include <linux/input.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
new file mode 100644
index 000000000000..21d22002cd19
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-mmp2.c
@@ -0,0 +1,111 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB Clock register offsets for MMP2
+ */
+#define APBC_RTC        APBC_REG(0x000)
+#define APBC_TWSI1      APBC_REG(0x004)
+#define APBC_TWSI2      APBC_REG(0x008)
+#define APBC_TWSI3      APBC_REG(0x00c)
+#define APBC_TWSI4      APBC_REG(0x010)
+#define APBC_KPC        APBC_REG(0x018)
+#define APBC_UART1      APBC_REG(0x02c)
+#define APBC_UART2      APBC_REG(0x030)
+#define APBC_UART3      APBC_REG(0x034)
+#define APBC_GPIO       APBC_REG(0x038)
+#define APBC_PWM0       APBC_REG(0x03c)
+#define APBC_PWM1       APBC_REG(0x040)
+#define APBC_PWM2       APBC_REG(0x044)
+#define APBC_PWM3       APBC_REG(0x048)
+#define APBC_SSP0       APBC_REG(0x04c)
+#define APBC_SSP1       APBC_REG(0x050)
+#define APBC_SSP2       APBC_REG(0x054)
+#define APBC_SSP3       APBC_REG(0x058)
+#define APBC_SSP4       APBC_REG(0x05c)
+#define APBC_SSP5       APBC_REG(0x060)
+#define APBC_TWSI5      APBC_REG(0x07c)
+#define APBC_TWSI6      APBC_REG(0x080)
+#define APBC_UART4      APBC_REG(0x088)
+
+#define APMU_USB        APMU_REG(0x05c)
+#define APMU_NAND       APMU_REG(0x060)
+#define APMU_SDH0       APMU_REG(0x054)
+#define APMU_SDH1       APMU_REG(0x058)
+#define APMU_SDH2       APMU_REG(0x0e8)
+#define APMU_SDH3       APMU_REG(0x0ec)
+
+static void sdhc_clk_enable(struct clk *clk)
+{
+        uint32_t clk_rst;
+
+        clk_rst  =  __raw_readl(clk->clk_rst);
+        clk_rst |= clk->enable_val;
+        __raw_writel(clk_rst, clk->clk_rst);
+}
+
+static void sdhc_clk_disable(struct clk *clk)
+{
+        uint32_t clk_rst;
+
+        clk_rst  =  __raw_readl(clk->clk_rst);
+        clk_rst &= ~clk->enable_val;
+        __raw_writel(clk_rst, clk->clk_rst);
+}
+
+struct clkops sdhc_clk_ops = {
+        .enable         = sdhc_clk_enable,
+        .disable        = sdhc_clk_disable,
+};
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 26000000);
+static APBC_CLK(uart2, UART2, 1, 26000000);
+static APBC_CLK(uart3, UART3, 1, 26000000);
+static APBC_CLK(uart4, UART4, 1, 26000000);
+static APBC_CLK(twsi1, TWSI1, 0, 26000000);
+static APBC_CLK(twsi2, TWSI2, 0, 26000000);
+static APBC_CLK(twsi3, TWSI3, 0, 26000000);
+static APBC_CLK(twsi4, TWSI4, 0, 26000000);
+static APBC_CLK(twsi5, TWSI5, 0, 26000000);
+static APBC_CLK(twsi6, TWSI6, 0, 26000000);
+static APBC_CLK(gpio, GPIO, 0, 26000000);
+
+static APMU_CLK(nand, NAND, 0xbf, 100000000);
+static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
+
+static struct clk_lookup mmp2_clkregs[] = {
+        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+        INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
+        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
+        INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
+        INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
+        INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
+        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
+};
+
+void __init mmp2_clk_init(void)
+{
+        clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+}
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
new file mode 100644
index 000000000000..5e6c18ccebd4
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -0,0 +1,91 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB clock register offsets for PXA168
+ */
+#define APBC_UART1      APBC_REG(0x000)
+#define APBC_UART2      APBC_REG(0x004)
+#define APBC_GPIO       APBC_REG(0x008)
+#define APBC_PWM1       APBC_REG(0x00c)
+#define APBC_PWM2       APBC_REG(0x010)
+#define APBC_PWM3       APBC_REG(0x014)
+#define APBC_PWM4       APBC_REG(0x018)
+#define APBC_RTC        APBC_REG(0x028)
+#define APBC_TWSI0      APBC_REG(0x02c)
+#define APBC_KPC        APBC_REG(0x030)
+#define APBC_TWSI1      APBC_REG(0x06c)
+#define APBC_UART3      APBC_REG(0x070)
+#define APBC_SSP1       APBC_REG(0x81c)
+#define APBC_SSP2       APBC_REG(0x820)
+#define APBC_SSP3       APBC_REG(0x84c)
+#define APBC_SSP4       APBC_REG(0x858)
+#define APBC_SSP5       APBC_REG(0x85c)
+
+#define APMU_NAND       APMU_REG(0x060)
+#define APMU_LCD        APMU_REG(0x04c)
+#define APMU_ETH        APMU_REG(0x0fc)
+#define APMU_USB        APMU_REG(0x05c)
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 14745600);
+static APBC_CLK(uart2, UART2, 1, 14745600);
+static APBC_CLK(uart3, UART3, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(ssp1, SSP1, 4, 0);
+static APBC_CLK(ssp2, SSP2, 4, 0);
+static APBC_CLK(ssp3, SSP3, 4, 0);
+static APBC_CLK(ssp4, SSP4, 4, 0);
+static APBC_CLK(ssp5, SSP5, 4, 0);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(keypad, KPC, 0, 32000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(lcd, LCD, 0x7f, 312000000);
+static APMU_CLK(eth, ETH, 0x09, 0);
+static APMU_CLK(usb, USB, 0x12, 0);
+
+/* device and clock bindings */
+static struct clk_lookup pxa168_clkregs[] = {
+        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
+        INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
+        INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
+        INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
+        INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
+        INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
+        INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
+        INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
+        INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
+        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
+        INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
+        INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
+        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+
+void __init pxa168_clk_init(void)
+{
+        clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+}
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
new file mode 100644
index 000000000000..933ea71d0b56
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa910.c
@@ -0,0 +1,67 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB Clock register offsets for PXA910
+ */
+#define APBC_UART0      APBC_REG(0x000)
+#define APBC_UART1      APBC_REG(0x004)
+#define APBC_GPIO       APBC_REG(0x008)
+#define APBC_PWM1       APBC_REG(0x00c)
+#define APBC_PWM2       APBC_REG(0x010)
+#define APBC_PWM3       APBC_REG(0x014)
+#define APBC_PWM4       APBC_REG(0x018)
+#define APBC_SSP1       APBC_REG(0x01c)
+#define APBC_SSP2       APBC_REG(0x020)
+#define APBC_RTC        APBC_REG(0x028)
+#define APBC_TWSI0      APBC_REG(0x02c)
+#define APBC_KPC        APBC_REG(0x030)
+#define APBC_SSP3       APBC_REG(0x04c)
+#define APBC_TWSI1      APBC_REG(0x06c)
+
+#define APMU_NAND       APMU_REG(0x060)
+#define APMU_USB        APMU_REG(0x05c)
+
+static APBC_CLK(uart1, UART0, 1, 14745600);
+static APBC_CLK(uart2, UART1, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(u2o, USB, 0x1b, 480000000);
+
+/* device and clock bindings */
+static struct clk_lookup pxa910_clkregs[] = {
+        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
+        INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
+        INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
+        INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
+        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
+        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+
+void __init pxa910_clk_init(void)
+{
+        clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 1c9d6c1ea97a..bd453274fca2 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -7,3 +7,6 @@ extern void timer_init(int irq);
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
 extern void mmp_restart(char, const char *);
+extern void __init pxa168_clk_init(void);
+extern void __init pxa910_clk_init(void);
+extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index cba22fed2265..c4ca4d17194a 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -13,7 +13,7 @@ extern void mmp2_clear_pmic_int(void);
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <mach/devices.h>
-#include <mach/sram.h>
+#include <linux/platform_data/dma-mmp_tdma.h>
 
 extern struct pxa_device_desc mmp2_device_uart1;
 extern struct pxa_device_desc mmp2_device_uart2;
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 09dcd6e2b6a8..37632d964d50 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -11,9 +11,9 @@ extern void pxa168_clear_keypad_wakeup(void);
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <mach/devices.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 #include <video/pxa168fb.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/cputype.h>
 #include <linux/pxa168_eth.h>
 #include <linux/platform_data/mv_usb.h>
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index 793634c837ef..3b58a3b2d7df 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -9,7 +9,7 @@ extern void __init pxa910_init_irq(void);
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <mach/devices.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 
 extern struct pxa_device_desc pxa910_device_uart1;
 extern struct pxa_device_desc pxa910_device_uart2;
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 68b0c93ec6a1..ddc812f40341 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -13,101 +13,6 @@
 
 #include <mach/addr-map.h>
 
-/*
- * APB clock register offsets for PXA168
- */
-#define APBC_PXA168_UART1       APBC_REG(0x000)
-#define APBC_PXA168_UART2       APBC_REG(0x004)
-#define APBC_PXA168_GPIO        APBC_REG(0x008)
-#define APBC_PXA168_PWM1        APBC_REG(0x00c)
-#define APBC_PXA168_PWM2        APBC_REG(0x010)
-#define APBC_PXA168_PWM3        APBC_REG(0x014)
-#define APBC_PXA168_PWM4        APBC_REG(0x018)
-#define APBC_PXA168_RTC         APBC_REG(0x028)
-#define APBC_PXA168_TWSI0       APBC_REG(0x02c)
-#define APBC_PXA168_KPC         APBC_REG(0x030)
-#define APBC_PXA168_TIMERS      APBC_REG(0x034)
-#define APBC_PXA168_AIB         APBC_REG(0x03c)
-#define APBC_PXA168_SW_JTAG     APBC_REG(0x040)
-#define APBC_PXA168_ONEWIRE     APBC_REG(0x048)
-#define APBC_PXA168_ASFAR       APBC_REG(0x050)
-#define APBC_PXA168_ASSAR       APBC_REG(0x054)
-#define APBC_PXA168_TWSI1       APBC_REG(0x06c)
-#define APBC_PXA168_UART3       APBC_REG(0x070)
-#define APBC_PXA168_AC97        APBC_REG(0x084)
-#define APBC_PXA168_SSP1        APBC_REG(0x81c)
-#define APBC_PXA168_SSP2        APBC_REG(0x820)
-#define APBC_PXA168_SSP3        APBC_REG(0x84c)
-#define APBC_PXA168_SSP4        APBC_REG(0x858)
-#define APBC_PXA168_SSP5        APBC_REG(0x85c)
-
-/*
- * APB Clock register offsets for PXA910
- */
-#define APBC_PXA910_UART0       APBC_REG(0x000)
-#define APBC_PXA910_UART1       APBC_REG(0x004)
-#define APBC_PXA910_GPIO        APBC_REG(0x008)
-#define APBC_PXA910_PWM1        APBC_REG(0x00c)
-#define APBC_PXA910_PWM2        APBC_REG(0x010)
-#define APBC_PXA910_PWM3        APBC_REG(0x014)
-#define APBC_PXA910_PWM4        APBC_REG(0x018)
-#define APBC_PXA910_SSP1        APBC_REG(0x01c)
-#define APBC_PXA910_SSP2        APBC_REG(0x020)
-#define APBC_PXA910_IPC         APBC_REG(0x024)
-#define APBC_PXA910_RTC         APBC_REG(0x028)
-#define APBC_PXA910_TWSI0       APBC_REG(0x02c)
-#define APBC_PXA910_KPC         APBC_REG(0x030)
-#define APBC_PXA910_TIMERS      APBC_REG(0x034)
-#define APBC_PXA910_TBROT       APBC_REG(0x038)
-#define APBC_PXA910_AIB         APBC_REG(0x03c)
-#define APBC_PXA910_SW_JTAG     APBC_REG(0x040)
-#define APBC_PXA910_TIMERS1     APBC_REG(0x044)
-#define APBC_PXA910_ONEWIRE     APBC_REG(0x048)
-#define APBC_PXA910_SSP3        APBC_REG(0x04c)
-#define APBC_PXA910_ASFAR       APBC_REG(0x050)
-#define APBC_PXA910_ASSAR       APBC_REG(0x054)
-
-/*
- * APB Clock register offsets for MMP2
- */
-#define APBC_MMP2_RTC           APBC_REG(0x000)
-#define APBC_MMP2_TWSI1         APBC_REG(0x004)
-#define APBC_MMP2_TWSI2         APBC_REG(0x008)
-#define APBC_MMP2_TWSI3         APBC_REG(0x00c)
-#define APBC_MMP2_TWSI4         APBC_REG(0x010)
-#define APBC_MMP2_ONEWIRE       APBC_REG(0x014)
-#define APBC_MMP2_KPC           APBC_REG(0x018)
-#define APBC_MMP2_TB_ROTARY     APBC_REG(0x01c)
-#define APBC_MMP2_SW_JTAG       APBC_REG(0x020)
-#define APBC_MMP2_TIMERS        APBC_REG(0x024)
-#define APBC_MMP2_UART1         APBC_REG(0x02c)
-#define APBC_MMP2_UART2         APBC_REG(0x030)
-#define APBC_MMP2_UART3         APBC_REG(0x034)
-#define APBC_MMP2_GPIO          APBC_REG(0x038)
-#define APBC_MMP2_PWM0          APBC_REG(0x03c)
-#define APBC_MMP2_PWM1          APBC_REG(0x040)
-#define APBC_MMP2_PWM2          APBC_REG(0x044)
-#define APBC_MMP2_PWM3          APBC_REG(0x048)
-#define APBC_MMP2_SSP0          APBC_REG(0x04c)
-#define APBC_MMP2_SSP1          APBC_REG(0x050)
-#define APBC_MMP2_SSP2          APBC_REG(0x054)
-#define APBC_MMP2_SSP3          APBC_REG(0x058)
-#define APBC_MMP2_SSP4          APBC_REG(0x05c)
-#define APBC_MMP2_SSP5          APBC_REG(0x060)
-#define APBC_MMP2_AIB           APBC_REG(0x064)
-#define APBC_MMP2_ASFAR         APBC_REG(0x068)
-#define APBC_MMP2_ASSAR         APBC_REG(0x06c)
-#define APBC_MMP2_USIM          APBC_REG(0x070)
-#define APBC_MMP2_MPMU          APBC_REG(0x074)
-#define APBC_MMP2_IPC           APBC_REG(0x078)
-#define APBC_MMP2_TWSI5         APBC_REG(0x07c)
-#define APBC_MMP2_TWSI6         APBC_REG(0x080)
-#define APBC_MMP2_TWSI_INTSTS   APBC_REG(0x084)
-#define APBC_MMP2_UART4         APBC_REG(0x088)
-#define APBC_MMP2_RIPC          APBC_REG(0x08c)
-#define APBC_MMP2_THSENS1       APBC_REG(0x090) /* Thermal Sensor */
-#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4)
-
 /* Common APB clock register bit definitions */
 #define APBC_APBCLK     (1 << 0)  /* APB Bus Clock Enable */
 #define APBC_FNCLK      (1 << 1)  /* Functional Clock Enable */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 7af8deb63e83..93c8d0e29bb9 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -13,21 +13,6 @@
 
 #include <mach/addr-map.h>
 
-/* Clock Reset Control */
-#define APMU_IRE        APMU_REG(0x048)
-#define APMU_LCD        APMU_REG(0x04c)
-#define APMU_CCIC       APMU_REG(0x050)
-#define APMU_SDH0       APMU_REG(0x054)
-#define APMU_SDH1       APMU_REG(0x058)
-#define APMU_USB        APMU_REG(0x05c)
-#define APMU_NAND       APMU_REG(0x060)
-#define APMU_DMA        APMU_REG(0x064)
-#define APMU_GEU        APMU_REG(0x068)
-#define APMU_BUS        APMU_REG(0x06c)
-#define APMU_SDH2       APMU_REG(0x0e8)
-#define APMU_SDH3       APMU_REG(0x0ec)
-#define APMU_ETH        APMU_REG(0x0fc)
-
 #define APMU_FNCLK_EN   (1 << 4)
 #define APMU_AXICLK_EN  (1 << 3)
 #define APMU_FNRST_DIS  (1 << 1)
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
index e60c7d98922b..3c71246cd994 100644
--- a/arch/arm/mach-mmp/irq.c
+++ b/arch/arm/mach-mmp/irq.c
@@ -153,10 +153,8 @@ static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
                 status = readl_relaxed(data->reg_status) & ~mask;
                 if (status == 0)
                         break;
-                n = find_first_bit(&status, BITS_PER_LONG);
-                while (n < BITS_PER_LONG) {
+                for_each_set_bit(n, &status, BITS_PER_LONG) {
                         generic_handle_irq(icu_data[i].virq_base + n);
-                        n = find_next_bit(&status, BITS_PER_LONG, n + 1);
                 }
         }
 }
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c709a24a9d25..3a3768c7a191 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -20,7 +20,6 @@
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/dma.h>
@@ -29,7 +28,6 @@
 #include <mach/mmp2.h>
 
 #include "common.h"
-#include "clock.h"
 
 #define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
 
@@ -98,95 +96,36 @@ void __init mmp2_init_irq(void)
         mmp2_init_icu();
 }
 
-static void sdhc_clk_enable(struct clk *clk)
-{
-        uint32_t clk_rst;
-
-        clk_rst  =  __raw_readl(clk->clk_rst);
-        clk_rst |= clk->enable_val;
-        __raw_writel(clk_rst, clk->clk_rst);
-}
-
-static void sdhc_clk_disable(struct clk *clk)
-{
-        uint32_t clk_rst;
-
-        clk_rst  =  __raw_readl(clk->clk_rst);
-        clk_rst &= ~clk->enable_val;
-        __raw_writel(clk_rst, clk->clk_rst);
-}
-
-struct clkops sdhc_clk_ops = {
-        .enable         = sdhc_clk_enable,
-        .disable        = sdhc_clk_disable,
-};
-
-/* APB peripheral clocks */
-static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
-static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
-static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
-static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
-static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
-static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
-static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
-static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
-static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
-static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
-static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
-
-static APMU_CLK(nand, NAND, 0xbf, 100000000);
-static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
-
-static struct clk_lookup mmp2_clkregs[] = {
-        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
-        INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
-        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
-        INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
-        INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
-        INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
-        INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
-        INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
-        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-        INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
-        INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
-        INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
-        INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
-};
-
 static int __init mmp2_init(void)
 {
         if (cpu_is_mmp2()) {
 #ifdef CONFIG_CACHE_TAUROS2
-                tauros2_init();
+                tauros2_init(0);
 #endif
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(mmp2_addr_map);
                 pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
-                clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+                mmp2_clk_init();
         }
 
         return 0;
 }
 postcore_initcall(mmp2_init);
 
+#define APBC_TIMERS     APBC_REG(0x024)
+
 static void __init mmp2_timer_init(void)
 {
         unsigned long clk_rst;
 
-        __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS);
+        __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
 
         /*
          * enable bus/functional clock, enable 6.5MHz (divider 4),
          * release reset
          */
         clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
-        __raw_writel(clk_rst, APBC_MMP2_TIMERS);
+        __raw_writel(clk_rst, APBC_TIMERS);
 
         timer_init(IRQ_MMP2_TIMER1);
 }
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 62d787c34475..b7f074f15498 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -18,8 +18,8 @@
 
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
-#include <mach/addr-map.h>
 #include <mach/cputype.h>
+#include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
 #include <mach/regs-apmu.h>
 #include <mach/irqs.h>
@@ -50,62 +50,13 @@ void __init pxa168_init_irq(void)
         icu_init_irq();
 }
 
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
-static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
-static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
-static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
-static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
-static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
-static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
-static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
-static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
-static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
-static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(lcd, LCD, 0x7f, 312000000);
-static APMU_CLK(eth, ETH, 0x09, 0);
-static APMU_CLK(usb, USB, 0x12, 0);
-
-/* device and clock bindings */
-static struct clk_lookup pxa168_clkregs[] = {
-        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
-        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
-        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
-        INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
-        INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
-        INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
-        INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
-        INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
-        INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
-        INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
-        INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
-        INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
-        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
-        INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
-        INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
-        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
 static int __init pxa168_init(void)
 {
         if (cpu_is_pxa168()) {
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(pxa168_mfp_addr_map);
                 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
-                clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+                pxa168_clk_init();
         }
 
         return 0;
@@ -114,6 +65,7 @@ postcore_initcall(pxa168_init);
 
 /* system timer - clock enabled, 3.25MHz */
 #define TIMER_CLK_RST   (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS     APBC_REG(0x34)
 
 static void __init pxa168_timer_init(void)
 {
@@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void)
          * ourselves instead of using clk_* API. Clock rate is defined
          * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
          */
-        __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
+        __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
 
         /* 3.25MHz, bus/functional clock enabled, release reset */
-        __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
+        __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
 
         timer_init(IRQ_PXA168_TIMER1);
 }
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 6da52e9f2bdc..8b1e16fbb7a5 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -14,10 +14,10 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 
+#include <asm/hardware/cache-tauros2.h>
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/dma.h>
@@ -25,7 +25,6 @@
 #include <mach/devices.h>
 
 #include "common.h"
-#include "clock.h"
 
 #define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
 
@@ -82,44 +81,16 @@ void __init pxa910_init_irq(void)
         icu_init_irq();
 }
 
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
-static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
-static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
-static APBC_CLK(rtc, PXA910_RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(u2o, USB, 0x1b, 480000000);
-
-/* device and clock bindings */
-static struct clk_lookup pxa910_clkregs[] = {
-        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
-        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
-        INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
-        INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
-        INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
-        INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
-        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-        INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
-        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
 static int __init pxa910_init(void)
 {
         if (cpu_is_pxa910()) {
+#ifdef CONFIG_CACHE_TAUROS2
+                tauros2_init(0);
+#endif
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(pxa910_mfp_addr_map);
                 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
-                clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+                pxa910_clk_init();
         }
 
         return 0;
@@ -128,12 +99,13 @@ postcore_initcall(pxa910_init);
 
 /* system timer - clock enabled, 3.25MHz */
 #define TIMER_CLK_RST   (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS     APBC_REG(0x34)
 
 static void __init pxa910_timer_init(void)
 {
         /* reset and configure */
-        __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS);
-        __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS);
+        __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
+        __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
 
         timer_init(IRQ_PXA910_AP1_TIMER1);
 }
diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c
index 7e8a5a2e1ec7..a6c08ede4491 100644
--- a/arch/arm/mach-mmp/sram.c
+++ b/arch/arm/mach-mmp/sram.c
@@ -22,7 +22,7 @@
 #include <linux/slab.h>
 #include <linux/genalloc.h>
 
-#include <mach/sram.h>
+#include <linux/platform_data/dma-mmp_tdma.h>
 
 struct sram_bank_info {
         char *pool_name;
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index 42bef6674ecf..dd30ea74785c 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -17,7 +17,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <linux/i2c.h>
 
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 1cd40ad301d3..b2740c800e8c 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -38,8 +38,6 @@ config ARCH_QSD8X50
 
 config ARCH_MSM8X60
         bool "MSM8X60"
-        select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
-                                  && !MACH_MSM8X60_FFA)
         select ARCH_MSM_SCORPIONMP
         select ARM_GIC
         select CPU_V7
@@ -47,16 +45,17 @@ config ARCH_MSM8X60
         select GPIO_MSM_V2
         select MSM_GPIOMUX
         select MSM_SCM if SMP
+        select USE_OF
 
 config ARCH_MSM8960
         bool "MSM8960"
         select ARCH_MSM_SCORPIONMP
-        select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
         select ARM_GIC
         select CPU_V7
         select MSM_V2_TLMM
         select MSM_GPIOMUX
         select MSM_SCM if SMP
+        select USE_OF
 
 endchoice
 
@@ -112,42 +111,6 @@ config MACH_QSD8X50A_ST1_5
         help
           Support for the Qualcomm ST1.5.
 
-config MACH_MSM8X60_RUMI3
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 RUMI3"
-        help
-          Support for the Qualcomm MSM8x60 RUMI3 emulator.
-
-config MACH_MSM8X60_SURF
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 SURF"
-        help
-          Support for the Qualcomm MSM8x60 SURF eval board.
-
-config MACH_MSM8X60_SIM
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 Simulator"
-        help
-          Support for the Qualcomm MSM8x60 simulator.
-
-config MACH_MSM8X60_FFA
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 FFA"
-        help
-          Support for the Qualcomm MSM8x60 FFA eval board.
-
-config MACH_MSM8960_SIM
-        depends on ARCH_MSM8960
-        bool "MSM8960 Simulator"
-        help
-          Support for the Qualcomm MSM8960 simulator.
-
-config MACH_MSM8960_RUMI3
-        depends on ARCH_MSM8960
-        bool "MSM8960 RUMI3"
-        help
-          Support for the Qualcomm MSM8960 RUMI3 emulator.
-
 endmenu
 
 config MSM_SMD_PKG3
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 4ad3969b9881..17519faf082f 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,11 +1,11 @@
-obj-y += io.o idle.o timer.o
+obj-y += io.o timer.o
 obj-y += clock.o
 obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
 obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
 
-obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
 obj-$(CONFIG_ARCH_MSM7X30) += dma.o
 obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 
@@ -25,8 +25,8 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
-obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
-obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o
+obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o
+obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o
 
 obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
deleted file mode 100644
index 805d4ee53f7e..000000000000
--- a/arch/arm/mach-msm/acpuclock-arm11.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/* arch/arm/mach-msm/acpuclock.c
- *
- * MSM architecture clock driver
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007 QUALCOMM Incorporated
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-#include "proc_comm.h"
-#include "acpuclock.h"
-
-
-#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
-#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
-#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
-
-/*
- * ARM11 clock configuration for specific ACPU speeds
- */
-
-#define ACPU_PLL_TCXO   -1
-#define ACPU_PLL_0      0
-#define ACPU_PLL_1      1
-#define ACPU_PLL_2      2
-#define ACPU_PLL_3      3
-
-#define PERF_SWITCH_DEBUG 0
-#define PERF_SWITCH_STEP_DEBUG 0
-
-struct clock_state
-{
-        struct clkctl_acpu_speed        *current_speed;
-        struct mutex                    lock;
-        uint32_t                        acpu_switch_time_us;
-        uint32_t                        max_speed_delta_khz;
-        uint32_t                        vdd_switch_time_us;
-        unsigned long                   power_collapse_khz;
-        unsigned long                   wait_for_irq_khz;
-};
-
-static struct clk *ebi1_clk;
-static struct clock_state drv_state = { 0 };
-
-static void __init acpuclk_init(void);
-
-/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */
-enum {
-        VDD_0 = 0,
-        VDD_1 = 1,
-        VDD_2 = 2,
-        VDD_3 = 3,
-        VDD_4 = 3,
-        VDD_5 = 3,
-        VDD_6 = 3,
-        VDD_7 = 7,
-        VDD_END
-};
-
-struct clkctl_acpu_speed {
-        unsigned int    a11clk_khz;
-        int             pll;
-        unsigned int    a11clk_src_sel;
-        unsigned int    a11clk_src_div;
-        unsigned int    ahbclk_khz;
-        unsigned int    ahbclk_div;
-        int             vdd;
-        unsigned int    axiclk_khz;
-        unsigned long   lpj; /* loops_per_jiffy */
-/* Index in acpu_freq_tbl[] for steppings. */
-        short           down;
-        short           up;
-};
-
-/*
- * ACPU speed table. Complete table is shown but certain speeds are commented
- * out to optimized speed switching. Initialize loops_per_jiffy to 0.
- *
- * Table stepping up/down is optimized for 256mhz jumps while staying on the
- * same PLL.
- */
-#if (0)
-static struct clkctl_acpu_speed  acpu_freq_tbl[] = {
-        { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 },
-        { 61440, ACPU_PLL_0,  4, 3, 61440,  0, VDD_0, 30720,  0, 0, 8 },
-        { 81920, ACPU_PLL_0,  4, 2, 40960,  1, VDD_0, 61440,  0, 0, 8 },
-        { 96000, ACPU_PLL_1,  1, 7, 48000,  1, VDD_0, 61440,  0, 0, 9 },
-        { 122880, ACPU_PLL_0, 4, 1, 61440,  1, VDD_3, 61440,  0, 0, 8 },
-        { 128000, ACPU_PLL_1, 1, 5, 64000,  1, VDD_3, 61440,  0, 0, 12 },
-        { 176000, ACPU_PLL_2, 2, 5, 88000,  1, VDD_3, 61440,  0, 0, 11 },
-        { 192000, ACPU_PLL_1, 1, 3, 64000,  2, VDD_3, 61440,  0, 0, 12 },
-        { 245760, ACPU_PLL_0, 4, 0, 81920,  2, VDD_4, 61440,  0, 0, 12 },
-        { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 },
-        { 264000, ACPU_PLL_2, 2, 3, 88000,  2, VDD_5, 128000, 0, 6, 13 },
-        { 352000, ACPU_PLL_2, 2, 2, 88000,  3, VDD_5, 128000, 0, 6, 13 },
-        { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 },
-        { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 },
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-};
-#else /* Table of freq we currently use. */
-static struct clkctl_acpu_speed  acpu_freq_tbl[] = {
-        { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
-        { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
-        { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
-        { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
-        { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
-        { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
-        { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 },
-        { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-};
-#endif
-
-
-#ifdef CONFIG_CPU_FREQ_TABLE
-static struct cpufreq_frequency_table freq_table[] = {
-        { 0, 122880 },
-        { 1, 128000 },
-        { 2, 245760 },
-        { 3, 384000 },
-        { 4, 528000 },
-        { 5, CPUFREQ_TABLE_END },
-};
-#endif
-
-static int pc_pll_request(unsigned id, unsigned on)
-{
-        int res;
-        on = !!on;
-
-#if PERF_SWITCH_DEBUG
-        if (on)
-                printk(KERN_DEBUG "Enabling PLL %d\n", id);
-        else
-                printk(KERN_DEBUG "Disabling PLL %d\n", id);
-#endif
-
-        res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
-        if (res < 0)
-                return res;
-
-#if PERF_SWITCH_DEBUG
-        if (on)
-                printk(KERN_DEBUG "PLL %d enabled\n", id);
-        else
-                printk(KERN_DEBUG "PLL %d disabled\n", id);
-#endif
-        return res;
-}
-
-
-/*----------------------------------------------------------------------------
- * ARM11 'owned' clock control
- *---------------------------------------------------------------------------*/
-
-unsigned long acpuclk_power_collapse(void) {
-        int ret = acpuclk_get_rate();
-        ret *= 1000;
-        if (ret > drv_state.power_collapse_khz)
-                acpuclk_set_rate(drv_state.power_collapse_khz, 1);
-        return ret;
-}
-
-unsigned long acpuclk_get_wfi_rate(void)
-{
-        return drv_state.wait_for_irq_khz;
-}
-
-unsigned long acpuclk_wait_for_irq(void) {
-        int ret = acpuclk_get_rate();
-        ret *= 1000;
-        if (ret > drv_state.wait_for_irq_khz)
-                acpuclk_set_rate(drv_state.wait_for_irq_khz, 1);
-        return ret;
-}
-
-static int acpuclk_set_vdd_level(int vdd)
-{
-        uint32_t current_vdd;
-
-        current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
-
-#if PERF_SWITCH_DEBUG
-        printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n",
-               current_vdd, vdd);
-#endif
-        writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
-        udelay(drv_state.vdd_switch_time_us);
-        if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
-#if PERF_SWITCH_DEBUG
-                printk(KERN_ERR "acpuclock: VDD set failed\n");
-#endif
-                return -EIO;
-        }
-
-#if PERF_SWITCH_DEBUG
-        printk(KERN_DEBUG "acpuclock: VDD switched\n");
-#endif
-        return 0;
-}
-
-/* Set proper dividers for the given clock speed. */
-static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) {
-        uint32_t reg_clkctl, reg_clksel, clk_div;
-
-        /* AHB_CLK_DIV */
-        clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03;
-        /*
-         * If the new clock divider is higher than the previous, then
-         * program the divider before switching the clock
-         */
-        if (hunt_s->ahbclk_div > clk_div) {
-                reg_clksel = readl(A11S_CLK_SEL_ADDR);
-                reg_clksel &= ~(0x3 << 1);
-                reg_clksel |= (hunt_s->ahbclk_div << 1);
-                writel(reg_clksel, A11S_CLK_SEL_ADDR);
-        }
-        if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) {
-                /* SRC0 */
-
-                /* Program clock source */
-                reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-                reg_clkctl &= ~(0x07 << 4);
-                reg_clkctl |= (hunt_s->a11clk_src_sel << 4);
-                writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-                /* Program clock divider */
-                reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-                reg_clkctl &= ~0xf;
-                reg_clkctl |= hunt_s->a11clk_src_div;
-                writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-                /* Program clock source selection */
-                reg_clksel = readl(A11S_CLK_SEL_ADDR);
-                reg_clksel |= 1; /* CLK_SEL_SRC1NO  == SRC1 */
-                writel(reg_clksel, A11S_CLK_SEL_ADDR);
-        } else {
-                /* SRC1 */
-
-                /* Program clock source */
-                reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-                reg_clkctl &= ~(0x07 << 12);
-                reg_clkctl |= (hunt_s->a11clk_src_sel << 12);
-                writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-                /* Program clock divider */
-                reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-                reg_clkctl &= ~(0xf << 8);
-                reg_clkctl |= (hunt_s->a11clk_src_div << 8);
-                writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-                /* Program clock source selection */
-                reg_clksel = readl(A11S_CLK_SEL_ADDR);
-                reg_clksel &= ~1; /* CLK_SEL_SRC1NO  == SRC0 */
-                writel(reg_clksel, A11S_CLK_SEL_ADDR);
-        }
-
-        /*
-         * If the new clock divider is lower than the previous, then
-         * program the divider after switching the clock
-         */
-        if (hunt_s->ahbclk_div < clk_div) {
-                reg_clksel = readl(A11S_CLK_SEL_ADDR);
-                reg_clksel &= ~(0x3 << 1);
-                reg_clksel |= (hunt_s->ahbclk_div << 1);
-                writel(reg_clksel, A11S_CLK_SEL_ADDR);
-        }
-}
-
-int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
-{
-        uint32_t reg_clkctl;
-        struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
-        int rc = 0;
-        unsigned int plls_enabled = 0, pll;
-
-        strt_s = cur_s = drv_state.current_speed;
-
-        WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n");
-        if (cur_s == NULL)
-                return -ENOENT;
-
-        if (rate == (cur_s->a11clk_khz * 1000))
-                return 0;
-
-        for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
-                if (tgt_s->a11clk_khz == (rate / 1000))
-                        break;
-        }
-
-        if (tgt_s->a11clk_khz == 0)
-                return -EINVAL;
-
-        /* Choose the highest speed speed at or below 'rate' with same PLL. */
-        if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) {
-                while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
-                        tgt_s--;
-        }
-
-        if (strt_s->pll != ACPU_PLL_TCXO)
-                plls_enabled |= 1 << strt_s->pll;
-
-        if (!for_power_collapse) {
-                mutex_lock(&drv_state.lock);
-                if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
-                        rc = pc_pll_request(tgt_s->pll, 1);
-                        if (rc < 0) {
-                                pr_err("PLL%d enable failed (%d)\n",
-                                        tgt_s->pll, rc);
-                                goto out;
-                        }
-                        plls_enabled |= 1 << tgt_s->pll;
-                }
-                /* Increase VDD if needed. */
-                if (tgt_s->vdd > cur_s->vdd) {
-                        if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) {
-                                printk(KERN_ERR "Unable to switch ACPU vdd\n");
-                                goto out;
-                        }
-                }
-        }
-
-        /* Set wait states for CPU between frequency changes */
-        reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-        reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
-        writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-#if PERF_SWITCH_DEBUG
-        printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n",
-               strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000);
-#endif
-
-        while (cur_s != tgt_s) {
-                /*
-                 * Always jump to target freq if within 256mhz, regulardless of
-                 * PLL. If differnece is greater, use the predefinied
-                 * steppings in the table.
-                 */
-                int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
-                if (d > drv_state.max_speed_delta_khz) {
-                        /* Step up or down depending on target vs current. */
-                        int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
-                                cur_s->up : cur_s->down;
-                        if (clk_index < 0) { /* This should not happen. */
-                                printk(KERN_ERR "cur:%u target: %u\n",
-                                        cur_s->a11clk_khz, tgt_s->a11clk_khz);
-                                rc = -EINVAL;
-                                goto out;
-                        }
-                        cur_s = &acpu_freq_tbl[clk_index];
-                } else {
-                        cur_s = tgt_s;
-                }
-#if PERF_SWITCH_STEP_DEBUG
-                printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n",
-                        __FUNCTION__, cur_s->a11clk_khz, cur_s->pll);
-#endif
-                if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO
-                    && !(plls_enabled & (1 << cur_s->pll))) {
-                        rc = pc_pll_request(cur_s->pll, 1);
-                        if (rc < 0) {
-                                pr_err("PLL%d enable failed (%d)\n",
-                                        cur_s->pll, rc);
-                                goto out;
-                        }
-                        plls_enabled |= 1 << cur_s->pll;
-                }
-
-                acpuclk_set_div(cur_s);
-                drv_state.current_speed = cur_s;
-                /* Re-adjust lpj for the new clock speed. */
-                loops_per_jiffy = cur_s->lpj;
-                udelay(drv_state.acpu_switch_time_us);
-        }
-
-        /* Nothing else to do for power collapse. */
-        if (for_power_collapse)
-                return 0;
-
-        /* Disable PLLs we are not using anymore. */
-        plls_enabled &= ~(1 << tgt_s->pll);
-        for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++)
-                if (plls_enabled & (1 << pll)) {
-                        rc = pc_pll_request(pll, 0);
-                        if (rc < 0) {
-                                pr_err("PLL%d disable failed (%d)\n", pll, rc);
-                                goto out;
-                        }
-                }
-
-        /* Change the AXI bus frequency if we can. */
-        if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
-                rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000);
-                if (rc < 0)
-                        pr_err("Setting AXI min rate failed!\n");
-        }
-
-        /* Drop VDD level if we can. */
-        if (tgt_s->vdd < strt_s->vdd) {
-                if (acpuclk_set_vdd_level(tgt_s->vdd) < 0)
-                        printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n");
-        }
-
-#if PERF_SWITCH_DEBUG
-        printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__);
-#endif
-out:
-        if (!for_power_collapse)
-                mutex_unlock(&drv_state.lock);
-        return rc;
-}
-
-static void __init acpuclk_init(void)
-{
-        struct clkctl_acpu_speed *speed;
-        uint32_t div, sel;
-        int rc;
-
-        /*
-         * Determine the rate of ACPU clock
-         */
-
-        if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
-                /* CLK_SRC0_SEL */
-                sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
-                /* CLK_SRC0_DIV */
-                div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
-        } else {
-                /* CLK_SRC1_SEL */
-                sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
-                /* CLK_SRC1_DIV */
-                div = readl(A11S_CLK_CNTL_ADDR) & 0x0f;
-        }
-
-        for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
-                if (speed->a11clk_src_sel == sel
-                 && (speed->a11clk_src_div == div))
-                        break;
-        }
-        if (speed->a11clk_khz == 0) {
-                printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n");
-                return;
-        }
-
-        drv_state.current_speed = speed;
-
-        rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000);
-        if (rc < 0)
-                pr_err("Setting AXI min rate failed!\n");
-
-        printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz);
-}
-
-unsigned long acpuclk_get_rate(void)
-{
-        WARN_ONCE(drv_state.current_speed == NULL,
-                  "acpuclk_get_rate: not initialized\n");
-        if (drv_state.current_speed)
-                return drv_state.current_speed->a11clk_khz;
-        else
-                return 0;
-}
-
-uint32_t acpuclk_get_switch_time(void)
-{
-        return drv_state.acpu_switch_time_us;
-}
-
-/*----------------------------------------------------------------------------
- * Clock driver initialization
- *---------------------------------------------------------------------------*/
-
-/* Initialize the lpj field in the acpu_freq_tbl. */
-static void __init lpj_init(void)
-{
-        int i;
-        const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
-        for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
-                acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
-                                                base_clk->a11clk_khz,
-                                                acpu_freq_tbl[i].a11clk_khz);
-        }
-}
-
-void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
-{
-        pr_info("acpu_clock_init()\n");
-
-        ebi1_clk = clk_get(NULL, "ebi1_clk");
-
-        mutex_init(&drv_state.lock);
-        drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
-        drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
-        drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
-        drv_state.power_collapse_khz = clkdata->power_collapse_khz;
-        drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
-        acpuclk_init();
-        lpj_init();
-#ifdef CONFIG_CPU_FREQ_TABLE
-        cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
-#endif
-}
diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h
deleted file mode 100644
index 415de2eb9a5e..000000000000
--- a/arch/arm/mach-msm/acpuclock.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* arch/arm/mach-msm/acpuclock.h
- *
- * MSM architecture clock driver header
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007 QUALCOMM Incorporated
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
-#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
-
-int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
-unsigned long acpuclk_get_rate(void);
-uint32_t acpuclk_get_switch_time(void);
-unsigned long acpuclk_wait_for_irq(void);
-unsigned long acpuclk_power_collapse(void);
-unsigned long acpuclk_get_wfi_rate(void);
-
-
-#endif
-
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
new file mode 100644
index 000000000000..b5b4de2cdf9e
--- /dev/null
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -0,0 +1,64 @@
+/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include "common.h"
+
+static const struct of_device_id msm_dt_gic_match[] __initconst = {
+        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
+        {}
+};
+
+static void __init msm8x60_init_irq(void)
+{
+        of_irq_init(msm_dt_gic_match);
+}
+
+static void __init msm8x60_init_late(void)
+{
+        smd_debugfs_init();
+}
+
+static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
+        {}
+};
+
+static void __init msm8x60_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        msm_auxdata_lookup, NULL);
+}
+
+static const char *msm8x60_fluid_match[] __initdata = {
+        "qcom,msm8660-fluid",
+        "qcom,msm8660-surf",
+        NULL
+};
+
+DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
+        .smp = smp_ops(msm_smp_ops),
+        .map_io = msm_map_msm8x60_io,
+        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
+        .init_machine = msm8x60_dt_init,
+        .init_late = msm8x60_init_late,
+        .timer = &msm_dt_timer,
+        .dt_compat = msm8x60_fluid_match,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
new file mode 100644
index 000000000000..4490edb71c17
--- /dev/null
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -0,0 +1,50 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const struct of_device_id msm_dt_gic_match[] __initconst = {
+        { .compatible = "qcom,msm-qgic2", .data = gic_of_init },
+        { }
+};
+
+static void __init msm_dt_init_irq(void)
+{
+        of_irq_init(msm_dt_gic_match);
+}
+
+static void __init msm_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const msm8960_dt_match[] __initconst = {
+        "qcom,msm8960-cdp",
+        NULL
+};
+
+DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
+        .smp = smp_ops(msm_smp_ops),
+        .map_io = msm_map_msm8960_io,
+        .init_irq = msm_dt_init_irq,
+        .timer = &msm_dt_timer,
+        .init_machine = msm_dt_init,
+        .dt_compat = msm8960_dt_match,
+        .handle_irq = gic_handle_irq,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 4fa3e99d9a62..6ce542e2e21c 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -36,6 +36,7 @@
 #include <linux/mtd/partitions.h>
 
 #include "devices.h"
+#include "common.h"
 
 static struct resource smc91x_resources[] = {
         [0] = {
@@ -66,8 +67,6 @@ static struct platform_device *devices[] __initdata = {
         &smc91x_device,
 };
 
-extern struct sys_timer msm_timer;
-
 static void __init halibut_init_early(void)
 {
         arch_ioremap_caller = __msm_ioremap_caller;
@@ -107,5 +106,5 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
         .init_irq       = halibut_init_irq,
         .init_machine   = halibut_init,
         .init_late      = halibut_init_late,
-        .timer          = &msm_timer,
+        .timer          = &msm7x01_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index cf1f89a5dc62..df00bc03ce74 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -30,7 +30,6 @@
 
 #include <mach/board.h>
 #include <mach/hardware.h>
-#include <mach/system.h>
 
 #include "board-mahimahi.h"
 #include "devices.h"
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
deleted file mode 100644
index 451ab1d43c92..000000000000
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/power_supply.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/setup.h>
-#ifdef CONFIG_CACHE_L2X0
-#include <asm/hardware/cache-l2x0.h>
-#endif
-
-#include <mach/vreg.h>
-#include <mach/mpp.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-
-#include "devices.h"
-#include "socinfo.h"
-#include "clock.h"
-
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .start  = 0x9C004300,
-                .end    = 0x9C0043ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = MSM_GPIO_TO_INT(132),
-                .end    = MSM_GPIO_TO_INT(132),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device smc91x_device = {
-        .name           = "smc91x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-        &msm_device_uart3,
-        &msm_device_smd,
-        &msm_device_dmov,
-        &msm_device_nand,
-        &smc91x_device,
-};
-
-extern struct sys_timer msm_timer;
-
-static void __init msm7x2x_init_irq(void)
-{
-        msm_init_irq();
-}
-
-static void __init msm7x2x_init(void)
-{
-        if (socinfo_init() < 0)
-                BUG();
-
-        if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) {
-                smc91x_resources[0].start = 0x98000300;
-                smc91x_resources[0].end = 0x980003ff;
-                smc91x_resources[1].start = MSM_GPIO_TO_INT(85);
-                smc91x_resources[1].end = MSM_GPIO_TO_INT(85);
-                if (gpio_tlmm_config(GPIO_CFG(85, 0,
-                                              GPIO_INPUT,
-                                              GPIO_PULL_DOWN,
-                                              GPIO_2MA),
-                                     GPIO_ENABLE)) {
-                        printk(KERN_ERR
-                               "%s: Err: Config GPIO-85 INT\n",
-                                __func__);
-                }
-        }
-
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init msm7x2x_map_io(void)
-{
-        msm_map_common_io();
-        /* Technically dependent on the SoC but using machine_is
-         * macros since socinfo is not available this early and there
-         * are plans to restructure the code which will eliminate the
-         * need for socinfo.
-         */
-        if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa())
-                msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27);
-
-        if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa())
-                msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25);
-
-#ifdef CONFIG_CACHE_L2X0
-        if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) {
-                /* 7x27 has 256KB L2 cache:
-                        64Kb/Way and 4-Way Associativity;
-                        R/W latency: 3 cycles;
-                        evmon/parity/share disabled. */
-                l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
-        }
-#endif
-}
-
-static void __init msm7x2x_init_late(void)
-{
-        smd_debugfs_init();
-}
-
-MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
-        .atag_offset    = 0x100,
-        .map_io         = msm7x2x_map_io,
-        .init_irq       = msm7x2x_init_irq,
-        .init_machine   = msm7x2x_init,
-        .init_late      = msm7x2x_init_late,
-        .timer          = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
-        .atag_offset    = 0x100,
-        .map_io         = msm7x2x_map_io,
-        .init_irq       = msm7x2x_init_irq,
-        .init_machine   = msm7x2x_init,
-        .init_late      = msm7x2x_init_late,
-        .timer          = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
-        .atag_offset    = 0x100,
-        .map_io         = msm7x2x_map_io,
-        .init_irq       = msm7x2x_init_irq,
-        .init_machine   = msm7x2x_init,
-        .init_late      = msm7x2x_init_late,
-        .timer          = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
-        .atag_offset    = 0x100,
-        .map_io         = msm7x2x_map_io,
-        .init_irq       = msm7x2x_init_irq,
-        .init_machine   = msm7x2x_init,
-        .init_late      = msm7x2x_init_late,
-        .timer          = &msm_timer,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index a5001378135d..effa6f4336c7 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -38,8 +38,7 @@
 #include "devices.h"
 #include "gpiomux.h"
 #include "proc_comm.h"
-
-extern struct sys_timer msm_timer;
+#include "common.h"
 
 static void __init msm7x30_fixup(struct tag *tag, char **cmdline,
                 struct meminfo *mi)
@@ -132,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
         .init_irq = msm7x30_init_irq,
         .init_machine = msm7x30_init,
         .init_late = msm7x30_init_late,
-        .timer = &msm_timer,
+        .timer = &msm7x30_timer,
 MACHINE_END
 
 MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
@@ -143,7 +142,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
         .init_irq = msm7x30_init_irq,
         .init_machine = msm7x30_init,
         .init_late = msm7x30_init_late,
-        .timer = &msm_timer,
+        .timer = &msm7x30_timer,
 MACHINE_END
 
 MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
@@ -154,5 +153,5 @@ MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
         .init_irq = msm7x30_init_irq,
         .init_machine = msm7x30_init,
         .init_late = msm7x30_init_late,
-        .timer = &msm_timer,
+        .timer = &msm7x30_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
deleted file mode 100644
index 65f4a1daa2e5..000000000000
--- a/arch/arm/mach-msm/board-msm8960.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/clkdev.h>
-#include <linux/memblock.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-#include "devices.h"
-
-static void __init msm8960_fixup(struct tag *tag, char **cmdline,
-                struct meminfo *mi)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM &&
-                                tag->u.mem.start == 0x40200000) {
-                        tag->u.mem.start = 0x40000000;
-                        tag->u.mem.size += SZ_2M;
-                }
-}
-
-static void __init msm8960_reserve(void)
-{
-        memblock_remove(0x40000000, SZ_2M);
-}
-
-static void __init msm8960_map_io(void)
-{
-        msm_map_msm8960_io();
-}
-
-static void __init msm8960_init_irq(void)
-{
-        unsigned int i;
-        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-                 (void *)MSM_QGIC_CPU_BASE);
-
-        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
-        if (machine_is_msm8960_rumi3())
-                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-
-        /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
-         * as they are configured as level, which does not play nice with
-         * handle_percpu_irq.
-         */
-        for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
-                if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
-                        irq_set_handler(i, handle_percpu_irq);
-        }
-}
-
-static struct platform_device *sim_devices[] __initdata = {
-        &msm8960_device_uart_gsbi2,
-};
-
-static struct platform_device *rumi3_devices[] __initdata = {
-        &msm8960_device_uart_gsbi5,
-};
-
-static void __init msm8960_sim_init(void)
-{
-        platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices));
-}
-
-static void __init msm8960_rumi3_init(void)
-{
-        platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
-}
-
-static void __init msm8960_init_late(void)
-{
-        smd_debugfs_init();
-}
-
-MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
-        .fixup = msm8960_fixup,
-        .reserve = msm8960_reserve,
-        .map_io = msm8960_map_io,
-        .init_irq = msm8960_init_irq,
-        .timer = &msm_timer,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8960_sim_init,
-        .init_late = msm8960_init_late,
-MACHINE_END
-
-MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
-        .fixup = msm8960_fixup,
-        .reserve = msm8960_reserve,
-        .map_io = msm8960_map_io,
-        .init_irq = msm8960_init_irq,
-        .timer = &msm_timer,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8960_rumi3_init,
-        .init_late = msm8960_init_late,
-MACHINE_END
-
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
deleted file mode 100644
index e37a724cd1eb..000000000000
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/memblock.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-static void __init msm8x60_fixup(struct tag *tag, char **cmdline,
-                struct meminfo *mi)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM &&
-                                tag->u.mem.start == 0x40200000) {
-                        tag->u.mem.start = 0x40000000;
-                        tag->u.mem.size += SZ_2M;
-                }
-}
-
-static void __init msm8x60_reserve(void)
-{
-        memblock_remove(0x40000000, SZ_2M);
-}
-
-static void __init msm8x60_map_io(void)
-{
-        msm_map_msm8x60_io();
-}
-
-#ifdef CONFIG_OF
-static struct of_device_id msm_dt_gic_match[] __initdata = {
-        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
-        {}
-};
-#endif
-
-static void __init msm8x60_init_irq(void)
-{
-        if (!of_have_populated_dt())
-                gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-                         (void *)MSM_QGIC_CPU_BASE);
-#ifdef CONFIG_OF
-        else
-                of_irq_init(msm_dt_gic_match);
-#endif
-
-        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
-        /* RUMI does not adhere to GIC spec by enabling STIs by default.
-         * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
-         */
-        if (!machine_is_msm8x60_sim())
-                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-}
-
-static void __init msm8x60_init(void)
-{
-}
-
-static void __init msm8x60_init_late(void)
-{
-        smd_debugfs_init();
-}
-
-#ifdef CONFIG_OF
-static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
-        {}
-};
-
-static void __init msm8x60_dt_init(void)
-{
-        if (of_machine_is_compatible("qcom,msm8660-surf")) {
-                printk(KERN_INFO "Init surf UART registers\n");
-                msm8x60_init_uart12dm();
-        }
-
-        of_platform_populate(NULL, of_default_bus_match_table,
-                        msm_auxdata_lookup, NULL);
-}
-
-static const char *msm8x60_fluid_match[] __initdata = {
-        "qcom,msm8660-fluid",
-        "qcom,msm8660-surf",
-        NULL
-};
-#endif /* CONFIG_OF */
-
-MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-
-#ifdef CONFIG_OF
-/* TODO: General device tree support for all MSM. */
-DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .init_machine = msm8x60_dt_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-        .dt_compat = msm8x60_fluid_match,
-MACHINE_END
-#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index c8fe0edb9761..a344a373928b 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -32,11 +32,10 @@
 #include <mach/irqs.h>
 #include <mach/sirc.h>
 #include <mach/vreg.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 
 #include "devices.h"
-
-extern struct sys_timer msm_timer;
+#include "common.h"
 
 static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
 static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;
@@ -201,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
         .init_irq = qsd8x50_init_irq,
         .init_machine = qsd8x50_init,
         .init_late = qsd8x50_init_late,
-        .timer = &msm_timer,
+        .timer = &qsd8x50_timer,
 MACHINE_END
 
 MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
@@ -210,5 +209,5 @@ MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
         .init_irq = qsd8x50_init_irq,
         .init_machine = qsd8x50_init,
         .init_late = qsd8x50_init_late,
-        .timer = &msm_timer,
+        .timer = &qsd8x50_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 2e569ab10eef..b7b0fc7e3278 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -27,7 +27,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <mach/system.h>
 #include <mach/vreg.h>
 #include <mach/board.h>
 
diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c
index 8650342b7493..3723e55819d6 100644
--- a/arch/arm/mach-msm/board-trout-mmc.c
+++ b/arch/arm/mach-msm/board-trout-mmc.c
@@ -15,7 +15,7 @@
 
 #include <mach/vreg.h>
 
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 
 #include "devices.h"
 
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
index 89bf6b426699..f9a5db6d2ced 100644
--- a/arch/arm/mach-msm/board-trout-panel.c
+++ b/arch/arm/mach-msm/board-trout-panel.c
@@ -14,7 +14,7 @@
 #include <asm/mach-types.h>
 #include <asm/system_info.h>
 
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 #include <mach/vreg.h>
 
 #include "board-trout.h"
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index bbe13f12fa01..4ba0800e243e 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -31,6 +31,7 @@
 
 #include "devices.h"
 #include "board-trout.h"
+#include "common.h"
 
 extern int trout_init_mmc(unsigned int);
 
@@ -42,8 +43,6 @@ static struct platform_device *devices[] __initdata = {
         &msm_device_i2c,
 };
 
-extern struct sys_timer msm_timer;
-
 static void __init trout_init_early(void)
 {
         arch_ioremap_caller = __msm_ioremap_caller;
@@ -111,5 +110,5 @@ MACHINE_START(TROUT, "HTC Dream")
         .init_irq       = trout_init_irq,
         .init_machine   = trout_init,
         .init_late      = trout_init_late,
-        .timer          = &msm_timer,
+        .timer          = &msm7x01_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index 63b711311086..a52c970df157 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -25,7 +25,7 @@
 /*
  * glue for the proc_comm interface
  */
-int pc_clk_enable(unsigned id)
+static int pc_clk_enable(unsigned id)
 {
         int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
         if (rc < 0)
@@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id)
                 return (int)id < 0 ? -EINVAL : 0;
 }
 
-void pc_clk_disable(unsigned id)
+static void pc_clk_disable(unsigned id)
 {
         msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
@@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
                 return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(unsigned id, unsigned rate)
 {
         /* The rate _might_ be rounded off to the nearest KHz value by the
          * remote function. So a return value of 0 doesn't necessarily mean
@@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate)
                 return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_min_rate(unsigned id, unsigned rate)
+static int pc_clk_set_min_rate(unsigned id, unsigned rate)
 {
         int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
         if (rc < 0)
@@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate)
                 return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_max_rate(unsigned id, unsigned rate)
+static int pc_clk_set_max_rate(unsigned id, unsigned rate)
 {
         int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
         if (rc < 0)
@@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate)
                 return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_flags(unsigned id, unsigned flags)
+static int pc_clk_set_flags(unsigned id, unsigned flags)
 {
         int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
         if (rc < 0)
@@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags)
                 return (int)id < 0 ? -EINVAL : 0;
 }
 
-unsigned pc_clk_get_rate(unsigned id)
+static unsigned pc_clk_get_rate(unsigned id)
 {
         if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
                 return 0;
@@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id)
                 return id;
 }
 
-unsigned pc_clk_is_enabled(unsigned id)
+static unsigned pc_clk_is_enabled(unsigned id)
 {
         if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
                 return 0;
@@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id)
                 return id;
 }
 
-long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(unsigned id, unsigned rate)
 {
 
         /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
new file mode 100644
index 000000000000..633a7159d5ff
--- /dev/null
+++ b/arch/arm/mach-msm/common.h
@@ -0,0 +1,32 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_COMMON_H
+#define __MACH_COMMON_H
+
+extern struct sys_timer msm7x01_timer;
+extern struct sys_timer msm7x30_timer;
+extern struct sys_timer msm_dt_timer;
+extern struct sys_timer qsd8x50_timer;
+
+extern void msm_map_common_io(void);
+extern void msm_map_msm7x30_io(void);
+extern void msm_map_msm8x60_io(void);
+extern void msm_map_msm8960_io(void);
+extern void msm_map_qsd8x50_io(void);
+
+extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+                                          unsigned int mtype, void *caller);
+
+extern struct smp_operations msm_smp_ops;
+extern void msm_cpu_die(unsigned int cpu);
+
+#endif
diff --git a/arch/arm/mach-msm/core.h b/arch/arm/mach-msm/core.h
new file mode 100644
index 000000000000..a9bab53dddf4
--- /dev/null
+++ b/arch/arm/mach-msm/core.h
@@ -0,0 +1,2 @@
+extern struct smp_operations msm_smp_ops;
+extern void msm_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 993780f490ad..f66ee6ea8720 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -27,7 +27,7 @@
 
 #include "clock.h"
 #include "clock-pcom.h"
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 
 static struct resource resources_uart1[] = {
         {
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 09b4f1403824..e90ab5938c5f 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -31,7 +31,7 @@
 #include "clock-pcom.h"
 #include "clock-7x30.h"
 
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 
 static struct resource resources_uart2[] = {
         {
diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c
deleted file mode 100644
index d9e1f26475de..000000000000
--- a/arch/arm/mach-msm/devices-msm8960.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-
-#include <linux/dma-mapping.h>
-#include <mach/irqs-8960.h>
-#include <mach/board.h>
-
-#include "devices.h"
-
-#define MSM_GSBI2_PHYS          0x16100000
-#define MSM_UART2DM_PHYS        (MSM_GSBI2_PHYS + 0x40000)
-
-#define MSM_GSBI5_PHYS          0x16400000
-#define MSM_UART5DM_PHYS        (MSM_GSBI5_PHYS + 0x40000)
-
-static struct resource resources_uart_gsbi2[] = {
-        {
-                .start  = GSBI2_UARTDM_IRQ,
-                .end    = GSBI2_UARTDM_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART2DM_PHYS,
-                .end    = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
-                .name   = "uart_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MSM_GSBI2_PHYS,
-                .end    = MSM_GSBI2_PHYS + PAGE_SIZE - 1,
-                .name   = "gsbi_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device msm8960_device_uart_gsbi2 = {
-        .name   = "msm_serial",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(resources_uart_gsbi2),
-        .resource       = resources_uart_gsbi2,
-};
-
-static struct resource resources_uart_gsbi5[] = {
-        {
-                .start  = GSBI5_UARTDM_IRQ,
-                .end    = GSBI5_UARTDM_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART5DM_PHYS,
-                .end    = MSM_UART5DM_PHYS + PAGE_SIZE - 1,
-                .name   = "uart_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MSM_GSBI5_PHYS,
-                .end    = MSM_GSBI5_PHYS + PAGE_SIZE - 1,
-                .name   = "gsbi_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device msm8960_device_uart_gsbi5 = {
-        .name   = "msm_serial",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(resources_uart_gsbi5),
-        .resource       = resources_uart_gsbi5,
-};
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 131633b12a34..4db61d5fe317 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -27,7 +27,7 @@
 
 #include <asm/mach/flash.h>
 
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 #include "clock-pcom.h"
 
 static struct resource resources_uart3[] = {
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 02cae5e2951c..354b91d4c3ac 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -223,8 +223,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
                         PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
                         if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
                                 cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
-                                list_del(&cmd->list);
-                                list_add_tail(&cmd->list, &active_commands[id]);
+                                list_move_tail(&cmd->list, &active_commands[id]);
                                 if (cmd->execute_func)
                                         cmd->execute_func(cmd);
                                 PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index a446fc14221f..750446feb444 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -13,7 +13,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 
-extern volatile int pen_release;
+#include "common.h"
 
 static inline void cpu_enter_lowpower(void)
 {
@@ -57,17 +57,12 @@ static inline void platform_do_lowpower(unsigned int cpu)
         }
 }
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
  * Called with IRQs disabled
  */
-void platform_cpu_die(unsigned int cpu)
+void __ref msm_cpu_die(unsigned int cpu)
 {
         /*
          * we're ready for shutdown now, so do it
@@ -81,12 +76,3 @@ void platform_cpu_die(unsigned int cpu)
          */
         cpu_leave_lowpower();
 }
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
deleted file mode 100644
index 0c9e13c65743..000000000000
--- a/arch/arm/mach-msm/idle.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* arch/arm/mach-msm/idle.c
- *
- * Idle processing for MSM7K - work around bugs with SWFI.
- *
- * Copyright (c) 2007 QUALCOMM Incorporated.
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <asm/system.h>
-
-static void msm_idle(void)
-{
-#ifdef CONFIG_MSM7X00A_IDLE
-        asm volatile (
-
-        "mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */ \n\t"
-        "bic     r0, r1, #(1 << 2)        /* clear dcache bit   */ \n\t"
-        "bic     r0, r0, #(1 << 12)       /* clear icache bit   */ \n\t"
-        "mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */ \n\t"
-
-        "mov     r0, #0                   /* prepare wfi value  */ \n\t"
-        "mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */ \n\t"
-        "mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */ \n\t"
-        "mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */ \n\t"
-
-        "mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */ \n\t"
-
-        : : : "r0","r1" );
-#endif
-}
-
-static int __init msm_idle_init(void)
-{
-        arm_pm_idle = msm_idle;
-        return 0;
-}
-
-arch_initcall(msm_idle_init);
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 435f8edfafd1..8cebedb11233 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -18,31 +18,18 @@
 #define __ASM_ARCH_MSM_BOARD_H
 
 #include <linux/types.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 
 /* platform device data structures */
 
-struct msm_acpu_clock_platform_data
-{
-        uint32_t acpu_switch_time_us;
-        uint32_t max_speed_delta_khz;
-        uint32_t vdd_switch_time_us;
-        unsigned long power_collapse_khz;
-        unsigned long wait_for_irq_khz;
-};
-
 struct clk_lookup;
 
-extern struct sys_timer msm_timer;
-
 /* common init routines for use by arch/arm/mach-msm/board-*.c */
 
 void __init msm_add_devices(void);
-void __init msm_map_common_io(void);
 void __init msm_init_irq(void);
 void __init msm_init_gpio(void);
 void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
-void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
 int __init msm_add_sdcc(unsigned int controller,
                         struct msm_mmc_platform_data *plat,
                         unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 6c4046c21296..67dc0e98b958 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -105,11 +105,4 @@
 #define MSM_AD5_PHYS          0xAC000000
 #define MSM_AD5_SIZE          (SZ_1M*13)
 
-#ifndef __ASSEMBLY__
-
-extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
-                                          unsigned int mtype, void *caller);
-
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index f944fe65a657..198202c267c8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -100,8 +100,4 @@
 #define MSM_HSUSB_PHYS        0xA3600000
 #define MSM_HSUSB_SIZE        SZ_1K
 
-#ifndef __ASSEMBLY__
-extern void msm_map_msm7x30_io(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index a1752c0284fc..9819a556acae 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -46,12 +46,8 @@
 #define MSM8960_TMR0_SIZE       SZ_4K
 
 #ifdef CONFIG_DEBUG_MSM8960_UART
-#define MSM_DEBUG_UART_BASE     0xE1040000
+#define MSM_DEBUG_UART_BASE     0xF0040000
 #define MSM_DEBUG_UART_PHYS     0x16440000
 #endif
 
-#ifndef __ASSEMBLY__
-extern void msm_map_msm8960_io(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index da77cc1d545d..0faa894729b7 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -122,8 +122,4 @@
 #define MSM_SDC4_PHYS          0xA0600000
 #define MSM_SDC4_SIZE          SZ_4K
 
-#ifndef __ASSEMBLY__
-extern void msm_map_qsd8x50_io(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 5aed57dc808c..c6d38f1d0c98 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -63,12 +63,8 @@
 #define MSM8X60_TMR0_SIZE       SZ_4K
 
 #ifdef CONFIG_DEBUG_MSM8660_UART
-#define MSM_DEBUG_UART_BASE     0xE1040000
+#define MSM_DEBUG_UART_BASE     0xF0040000
 #define MSM_DEBUG_UART_PHYS     0x19C40000
 #endif
 
-#ifndef __ASSEMBLY__
-extern void msm_map_msm8x60_io(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
deleted file mode 100644
index f5fb2ec87ffe..000000000000
--- a/arch/arm/mach-msm/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* arch/arm/mach-msm/include/mach/system.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-/* low level hardware reset hook -- for example, hitting the
- * PSHOLD line on the PMIC to hard reset the system
- */
-extern void (*msm_hw_reset_hook)(void);
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index a1e7b1168850..3854f6f20ce2 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -29,30 +29,32 @@
 
 #include <mach/board.h>
 
-#define MSM_CHIP_DEVICE(name, chip) {                         \
+#include "common.h"
+
+#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) {                          \
                 .virtual = (unsigned long) MSM_##name##_BASE, \
                 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
                 .length = chip##_##name##_SIZE, \
-                .type = MT_DEVICE_NONSHARED, \
+                .type = mem_type, \
          }
 
+#define MSM_DEVICE_TYPE(name, mem_type) \
+                MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
+#define MSM_CHIP_DEVICE(name, chip) \
+                MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
 #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
 
-#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
-        || defined(CONFIG_ARCH_MSM7X25)
+#if defined(CONFIG_ARCH_MSM7X00A)
 static struct map_desc msm_io_desc[] __initdata = {
-        MSM_DEVICE(VIC),
-        MSM_CHIP_DEVICE(CSR, MSM7X00),
-        MSM_DEVICE(DMOV),
-        MSM_CHIP_DEVICE(GPIO1, MSM7X00),
-        MSM_CHIP_DEVICE(GPIO2, MSM7X00),
-        MSM_DEVICE(CLK_CTL),
+        MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
+        MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
+        MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
+        MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
+        MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
+        MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
         defined(CONFIG_DEBUG_MSM_UART3)
-        MSM_DEVICE(DEBUG_UART),
-#endif
-#ifdef CONFIG_ARCH_MSM7X30
-        MSM_DEVICE(GCC),
+        MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
 #endif
         {
                 .virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index e012dc8391cf..7ed69b69c87c 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -22,23 +22,14 @@
 #include <asm/mach-types.h>
 #include <asm/smp_plat.h>
 
-#include <mach/msm_iomap.h>
-
 #include "scm-boot.h"
+#include "common.h"
 
 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
 #define SCSS_CPU1CORE_RESET 0xD80
 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
 
-/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
-
 extern void msm_secondary_startup(void);
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen".
- */
-volatile int pen_release = -1;
 
 static DEFINE_SPINLOCK(boot_lock);
 
@@ -48,11 +39,8 @@ static inline int get_core_count(void)
         return ((read_cpuid_id() >> 4) & 3) + 1;
 }
 
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit msm_secondary_init(unsigned int cpu)
 {
-        /* Configure edge-triggered PPIs */
-        writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
         /*
          * if any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
@@ -93,7 +81,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
                                   "address\n");
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned long timeout;
         static int cold_boot_done;
@@ -153,7 +141,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  * does not support the ARM SCU, so just set the possible cpu mask to
  * NR_CPUS.
  */
-void __init smp_init_cpus(void)
+static void __init msm_smp_init_cpus(void)
 {
         unsigned int i, ncores = get_core_count();
 
@@ -169,6 +157,16 @@ void __init smp_init_cpus(void)
         set_smp_cross_call(gic_raise_softirq);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
 {
 }
+
+struct smp_operations msm_smp_ops __initdata = {
+        .smp_init_cpus          = msm_smp_init_cpus,
+        .smp_prepare_cpus       = msm_smp_prepare_cpus,
+        .smp_secondary_init     = msm_secondary_init,
+        .smp_boot_secondary     = msm_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = msm_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
index 9980dc736e7b..8f1eecd88186 100644
--- a/arch/arm/mach-msm/proc_comm.c
+++ b/arch/arm/mach-msm/proc_comm.c
@@ -19,7 +19,6 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 #include <mach/msm_iomap.h>
-#include <mach/system.h>
 
 #include "proc_comm.h"
 
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 657be73297db..c5a2eddc6cdc 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -30,7 +30,6 @@
 #include <linux/delay.h>
 
 #include <mach/msm_smd.h>
-#include <mach/system.h>
 
 #include "smd_private.h"
 #include "proc_comm.h"
@@ -39,8 +38,6 @@
 #define CONFIG_QDSP6 1
 #endif
 
-void (*msm_hw_reset_hook)(void);
-
 #define MODULE_NAME "msm_smd"
 
 enum {
@@ -52,13 +49,14 @@ static int msm_smd_debug_mask;
 
 struct shared_info {
         int ready;
-        unsigned state;
+        void __iomem *state;
 };
 
 static unsigned dummy_state[SMSM_STATE_COUNT];
 
 static struct shared_info smd_info = {
-        .state = (unsigned) &dummy_state,
+        /* FIXME: not a real __iomem pointer */
+        .state = &dummy_state,
 };
 
 module_param_named(debug_mask, msm_smd_debug_mask,
@@ -101,10 +99,6 @@ static void handle_modem_crash(void)
         pr_err("ARM9 has CRASHED\n");
         smd_diag();
 
-        /* hard reboot if possible */
-        if (msm_hw_reset_hook)
-                msm_hw_reset_hook();
-
         /* in this case the modem or watchdog should reboot us */
         for (;;)
                 ;
@@ -796,22 +790,22 @@ void *smem_alloc(unsigned id, unsigned size)
         return smem_find(id, size);
 }
 
-void *smem_item(unsigned id, unsigned *size)
+void __iomem *smem_item(unsigned id, unsigned *size)
 {
         struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
         struct smem_heap_entry *toc = shared->heap_toc;
 
         if (id >= SMEM_NUM_ITEMS)
-                return 0;
+                return NULL;
 
         if (toc[id].allocated) {
                 *size = toc[id].size;
-                return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset);
+                return (MSM_SHARED_RAM_BASE + toc[id].offset);
         } else {
                 *size = 0;
         }
 
-        return 0;
+        return NULL;
 }
 
 void *smem_find(unsigned id, unsigned size_in)
@@ -857,7 +851,7 @@ static irqreturn_t smsm_irq_handler(int irq, void *data)
 int smsm_change_state(enum smsm_state_item item,
                       uint32_t clear_mask, uint32_t set_mask)
 {
-        unsigned long addr = smd_info.state + item * 4;
+        void __iomem *addr = smd_info.state + item * 4;
         unsigned long flags;
         unsigned state;
 
@@ -943,10 +937,10 @@ int smd_core_init(void)
         /* wait for essential items to be initialized */
         for (;;) {
                 unsigned size;
-                void *state;
+                void __iomem *state;
                 state = smem_item(SMEM_SMSM_SHARED_STATE, &size);
                 if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) {
-                        smd_info.state = (unsigned)state;
+                        smd_info.state = state;
                         break;
                 }
         }
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 812808254936..476549a8a709 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -1,7 +1,7 @@
 /*
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -20,15 +20,16 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
 #include <asm/sched_clock.h>
 
-#include <mach/msm_iomap.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
+#include "common.h"
 
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
@@ -36,7 +37,6 @@
 #define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
 #define TIMER_ENABLE_EN                 BIT(0)
 #define TIMER_CLEAR             0x000C
-#define DGT_CLK_CTL             0x0034
 #define DGT_CLK_CTL_DIV_4       0x3
 
 #define GPT_HZ 32768
@@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = {
 
 static union {
         struct clock_event_device *evt;
-        struct clock_event_device __percpu **percpu_evt;
+        struct clock_event_device * __percpu *percpu_evt;
 } msm_evt;
 
 static void __iomem *source_base;
@@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
 
         *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
         clockevents_register_device(evt);
-        enable_percpu_irq(evt->irq, 0);
+        enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
         return 0;
 }
 
@@ -172,44 +172,21 @@ static notrace u32 msm_sched_clock_read(void)
         return msm_clocksource.read(&msm_clocksource);
 }
 
-static void __init msm_timer_init(void)
+static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
+                                  bool percpu)
 {
         struct clock_event_device *ce = &msm_clockevent;
         struct clocksource *cs = &msm_clocksource;
         int res;
-        u32 dgt_hz;
-
-        if (cpu_is_msm7x01()) {
-                event_base = MSM_CSR_BASE;
-                source_base = MSM_CSR_BASE + 0x10;
-                dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
-                cs->read = msm_read_timer_count_shift;
-                cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
-        } else if (cpu_is_msm7x30()) {
-                event_base = MSM_CSR_BASE + 0x04;
-                source_base = MSM_CSR_BASE + 0x24;
-                dgt_hz = 24576000 / 4;
-        } else if (cpu_is_qsd8x50()) {
-                event_base = MSM_CSR_BASE;
-                source_base = MSM_CSR_BASE + 0x10;
-                dgt_hz = 19200000 / 4;
-        } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
-                event_base = MSM_TMR_BASE + 0x04;
-                /* Use CPU0's timer as the global clock source. */
-                source_base = MSM_TMR0_BASE + 0x24;
-                dgt_hz = 27000000 / 4;
-                writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
-        } else
-                BUG();
 
         writel_relaxed(0, event_base + TIMER_ENABLE);
         writel_relaxed(0, event_base + TIMER_CLEAR);
         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
         ce->cpumask = cpumask_of(0);
+        ce->irq = irq;
 
-        ce->irq = INT_GP_TIMER_EXP;
         clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
-        if (cpu_is_msm8x60() || cpu_is_msm8960()) {
+        if (percpu) {
                 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
                 if (!msm_evt.percpu_evt) {
                         pr_err("memory allocation failed for %s\n", ce->name);
@@ -219,7 +196,7 @@ static void __init msm_timer_init(void)
                 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
                                          ce->name, msm_evt.percpu_evt);
                 if (!res) {
-                        enable_percpu_irq(ce->irq, 0);
+                        enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
 #ifdef CONFIG_LOCAL_TIMERS
                         local_timer_register(&msm_local_timer_ops);
 #endif
@@ -238,10 +215,143 @@ err:
         res = clocksource_register_hz(cs, dgt_hz);
         if (res)
                 pr_err("clocksource_register failed\n");
-        setup_sched_clock(msm_sched_clock_read,
-                        cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
+        setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
 }
 
-struct sys_timer msm_timer = {
-        .init = msm_timer_init
+#ifdef CONFIG_OF
+static const struct of_device_id msm_dgt_match[] __initconst = {
+        { .compatible = "qcom,msm-dgt" },
+        { },
+};
+
+static const struct of_device_id msm_gpt_match[] __initconst = {
+        { .compatible = "qcom,msm-gpt" },
+        { },
+};
+
+static void __init msm_dt_timer_init(void)
+{
+        struct device_node *np;
+        u32 freq;
+        int irq;
+        struct resource res;
+        u32 percpu_offset;
+        void __iomem *dgt_clk_ctl;
+
+        np = of_find_matching_node(NULL, msm_gpt_match);
+        if (!np) {
+                pr_err("Can't find GPT DT node\n");
+                return;
+        }
+
+        event_base = of_iomap(np, 0);
+        if (!event_base) {
+                pr_err("Failed to map event base\n");
+                return;
+        }
+
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq <= 0) {
+                pr_err("Can't get irq\n");
+                return;
+        }
+        of_node_put(np);
+
+        np = of_find_matching_node(NULL, msm_dgt_match);
+        if (!np) {
+                pr_err("Can't find DGT DT node\n");
+                return;
+        }
+
+        if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
+                percpu_offset = 0;
+
+        if (of_address_to_resource(np, 0, &res)) {
+                pr_err("Failed to parse DGT resource\n");
+                return;
+        }
+
+        source_base = ioremap(res.start + percpu_offset, resource_size(&res));
+        if (!source_base) {
+                pr_err("Failed to map source base\n");
+                return;
+        }
+
+        if (!of_address_to_resource(np, 1, &res)) {
+                dgt_clk_ctl = ioremap(res.start + percpu_offset,
+                                      resource_size(&res));
+                if (!dgt_clk_ctl) {
+                        pr_err("Failed to map DGT control base\n");
+                        return;
+                }
+                writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
+                iounmap(dgt_clk_ctl);
+        }
+
+        if (of_property_read_u32(np, "clock-frequency", &freq)) {
+                pr_err("Unknown frequency\n");
+                return;
+        }
+        of_node_put(np);
+
+        msm_timer_init(freq, 32, irq, !!percpu_offset);
+}
+
+struct sys_timer msm_dt_timer = {
+        .init = msm_dt_timer_init
+};
+#endif
+
+static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
+{
+        event_base = ioremap(event, SZ_64);
+        if (!event_base) {
+                pr_err("Failed to map event base\n");
+                return 1;
+        }
+        source_base = ioremap(source, SZ_64);
+        if (!source_base) {
+                pr_err("Failed to map source base\n");
+                return 1;
+        }
+        return 0;
+}
+
+static void __init msm7x01_timer_init(void)
+{
+        struct clocksource *cs = &msm_clocksource;
+
+        if (msm_timer_map(0xc0100000, 0xc0100010))
+                return;
+        cs->read = msm_read_timer_count_shift;
+        cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
+        /* 600 KHz */
+        msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
+                        false);
+}
+
+struct sys_timer msm7x01_timer = {
+        .init = msm7x01_timer_init
+};
+
+static void __init msm7x30_timer_init(void)
+{
+        if (msm_timer_map(0xc0100004, 0xc0100024))
+                return;
+        msm_timer_init(24576000 / 4, 32, 1, false);
+}
+
+struct sys_timer msm7x30_timer = {
+        .init = msm7x30_timer_init
+};
+
+static void __init qsd8x50_timer_init(void)
+{
+        if (msm_timer_map(0xAC100000, 0xAC100010))
+                return;
+        msm_timer_init(19200000 / 4, 32, 7, false);
+}
+
+struct sys_timer qsd8x50_timer = {
+        .init = qsd8x50_timer_init
 };
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index a9bc84180d21..343c435b4176 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -13,6 +13,7 @@
 #include <linux/mbus.h>
 #include <linux/io.h>
 #include <plat/addr-map.h>
+#include <mach/mv78xx0.h>
 #include "common.h"
 
 /*
@@ -47,7 +48,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
          * so we don't need to take that into account here.
          */
 
-        return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
+        return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
 }
 
 /*
@@ -71,17 +72,17 @@ void __init mv78xx0_setup_cpu_mbus(void)
          */
         if (mv78xx0_core_index() == 0)
                 orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            DDR_WINDOW_CPU0_BASE);
+                                            (void __iomem *) DDR_WINDOW_CPU0_BASE);
         else
                 orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            DDR_WINDOW_CPU1_BASE);
+                                            (void __iomem *) DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                                       int maj, int min)
 {
         orion_setup_cpu_win(&addr_map_cfg, window, base, size,
-                            TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
+                            TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
 }
 
 void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 3057f7d4329a..131cd4883f3d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -20,8 +20,8 @@
 #include <mach/mv78xx0.h>
 #include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/ehci-orion.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/usb-ehci-orion.h>
+#include <linux/platform_data/mtd-orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
@@ -130,17 +130,12 @@ static int get_tclk(void)
  ****************************************************************************/
 static struct map_desc mv78xx0_io_desc[] __initdata = {
         {
-                .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
                 .pfn            = 0,
                 .length         = MV78XX0_CORE_REGS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = MV78XX0_PCIE_IO_VIRT_BASE(0),
-                .pfn            = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
-                .length         = MV78XX0_PCIE_IO_SIZE * 8,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = MV78XX0_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) MV78XX0_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
                 .length         = MV78XX0_REGS_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index eb187e0e059b..5f03484584d4 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -11,18 +11,18 @@
 
 #include <mach/mv78xx0.h>
 
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define L2_WRITETHROUGH         0x00020000
 
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define SOFT_RESET_OUT_EN       0x00000004
 
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
 
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_ERR_OFF       0x0000
 #define IRQ_CAUSE_LOW_OFF       0x0004
 #define IRQ_CAUSE_HIGH_OFF      0x0008
@@ -30,7 +30,7 @@
 #define IRQ_MASK_LOW_OFF        0x0010
 #define IRQ_MASK_HIGH_OFF       0x0014
 
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
deleted file mode 100644
index c7d9d00d8fc1..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "mv78xx0.h"
-
-#define IO_SPACE_LIMIT          0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
-                                        + MV78XX0_PCIE_IO_VIRT_BASE(0));
-}
-
-#define __io(a)                 __io(a)
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index e807c4c52a0b..46200a183cf2 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -29,28 +29,27 @@
  *
  * virt         phys            size
  * fe400000     f102x000        16K     core-specific peripheral registers
- * fe700000     f0800000        1M      PCIe #0 I/O space
- * fe800000     f0900000        1M      PCIe #1 I/O space
- * fe900000     f0a00000        1M      PCIe #2 I/O space
- * fea00000     f0b00000        1M      PCIe #3 I/O space
- * feb00000     f0c00000        1M      PCIe #4 I/O space
- * fec00000     f0d00000        1M      PCIe #5 I/O space
- * fed00000     f0e00000        1M      PCIe #6 I/O space
- * fee00000     f0f00000        1M      PCIe #7 I/O space
- * fef00000     f1000000        1M      on-chip peripheral registers
+ * fee00000     f0800000        64K     PCIe #0 I/O space
+ * fee10000     f0900000        64K     PCIe #1 I/O space
+ * fee20000     f0a00000        64K     PCIe #2 I/O space
+ * fee30000     f0b00000        64K     PCIe #3 I/O space
+ * fee40000     f0c00000        64K     PCIe #4 I/O space
+ * fee50000     f0d00000        64K     PCIe #5 I/O space
+ * fee60000     f0e00000        64K     PCIe #6 I/O space
+ * fee70000     f0f00000        64K     PCIe #7 I/O space
+ * fd000000     f1000000        1M      on-chip peripheral registers
  */
 #define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
 #define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
-#define MV78XX0_CORE_REGS_VIRT_BASE     0xfe400000
+#define MV78XX0_CORE_REGS_VIRT_BASE     IOMEM(0xfe400000)
 #define MV78XX0_CORE_REGS_PHYS_BASE     0xfe400000
 #define MV78XX0_CORE_REGS_SIZE          SZ_16K
 
 #define MV78XX0_PCIE_IO_PHYS_BASE(i)    (0xf0800000 + ((i) << 20))
-#define MV78XX0_PCIE_IO_VIRT_BASE(i)    (0xfe700000 + ((i) << 20))
 #define MV78XX0_PCIE_IO_SIZE            SZ_1M
 
 #define MV78XX0_REGS_PHYS_BASE          0xf1000000
-#define MV78XX0_REGS_VIRT_BASE          0xfef00000
+#define MV78XX0_REGS_VIRT_BASE          IOMEM(0xfd000000)
 #define MV78XX0_REGS_SIZE               SZ_1M
 
 #define MV78XX0_PCIE_MEM_PHYS_BASE      0xc0000000
@@ -65,47 +64,47 @@
 /*
  * Register Map
  */
-#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
-#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1570)
-
-#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
-#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
-#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE | 0x0100)
-#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1000)
-#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1100)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
-#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
-#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
-#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
-#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
-
-#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
-#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
-
-#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
-#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
-#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
-#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
-
-#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
-#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
-#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
-
-#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
-
-#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
-#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
-#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
-#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
-
-#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE + 0x00000)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE + 0x1500)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE + 0x1570)
+
+#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE + 0x10000)
+#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x10000)
+#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE + 0x0030)
+#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE + 0x0034)
+#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE + 0x0100)
+#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1000)
+#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1100)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
+#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2200)
+#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2200)
+#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2300)
+#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2300)
+
+#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x30000)
+#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x34000)
+
+#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x40000)
+#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x44000)
+#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x48000)
+#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x4c000)
+
+#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x50000)
+#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x51000)
+#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x52000)
+
+#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x70000)
+#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x74000)
+
+#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x80000)
+#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x84000)
+#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x88000)
+#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x8c000)
+
+#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0xa0000)
 
 /*
  * Supported devices and revisions.
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index eff9a750bbe2..32073444024b 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -10,7 +10,9 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
+#include <plat/orion-gpio.h>
 #include <plat/irq.h>
 #include "common.h"
 
@@ -23,16 +25,16 @@ static int __initdata gpio0_irqs[4] = {
 
 void __init mv78xx0_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
-        orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
+        orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
 
         /*
          * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
          * registers for core #1 are at an offset of 0x18 from those of
          * core #0.)
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE,
+        orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
                         mv78xx0_core_index() ? 0x18 : 0,
                         IRQ_MV78XX0_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 2e56e86b6d68..a9a154a646dd 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -15,6 +15,7 @@
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
 #include <plat/addr-map.h>
+#include <mach/mv78xx0.h>
 #include "common.h"
 
 struct pcie_port {
@@ -23,119 +24,73 @@ struct pcie_port {
         u8                      root_bus_nr;
         void __iomem            *base;
         spinlock_t              conf_lock;
-        char                    io_space_name[16];
         char                    mem_space_name[16];
-        struct resource         res[2];
+        struct resource         res;
 };
 
 static struct pcie_port pcie_port[8];
 static int num_pcie_ports;
 static struct resource pcie_io_space;
-static struct resource pcie_mem_space;
-
 
 void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
 {
-        *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
-        *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
+        *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
+        *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
 }
 
+u32 pcie_port_size[8] = {
+        0,
+        0x30000000,
+        0x10000000,
+        0x10000000,
+        0x08000000,
+        0x08000000,
+        0x08000000,
+        0x04000000,
+};
+
 static void __init mv78xx0_pcie_preinit(void)
 {
         int i;
         u32 size_each;
         u32 start;
-        int win;
+        int win = 0;
 
         pcie_io_space.name = "PCIe I/O Space";
         pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
         pcie_io_space.end =
                 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
-        pcie_io_space.flags = IORESOURCE_IO;
+        pcie_io_space.flags = IORESOURCE_MEM;
         if (request_resource(&iomem_resource, &pcie_io_space))
                 panic("can't allocate PCIe I/O space");
 
-        pcie_mem_space.name = "PCIe MEM Space";
-        pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
-        pcie_mem_space.end =
-                MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
-        pcie_mem_space.flags = IORESOURCE_MEM;
-        if (request_resource(&iomem_resource, &pcie_mem_space))
-                panic("can't allocate PCIe MEM space");
+        if (num_pcie_ports > 7)
+                panic("invalid number of PCIe ports");
+
+        size_each = pcie_port_size[num_pcie_ports];
 
+        start = MV78XX0_PCIE_MEM_PHYS_BASE;
         for (i = 0; i < num_pcie_ports; i++) {
                 struct pcie_port *pp = pcie_port + i;
 
-                snprintf(pp->io_space_name, sizeof(pp->io_space_name),
-                        "PCIe %d.%d I/O", pp->maj, pp->min);
-                pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
-                pp->res[0].name = pp->io_space_name;
-                pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
-                pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
-                pp->res[0].flags = IORESOURCE_IO;
-
                 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                         "PCIe %d.%d MEM", pp->maj, pp->min);
                 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-                pp->res[1].name = pp->mem_space_name;
-                pp->res[1].flags = IORESOURCE_MEM;
-        }
-
-        switch (num_pcie_ports) {
-        case 0:
-                size_each = 0;
-                break;
-
-        case 1:
-                size_each = 0x30000000;
-                break;
-
-        case 2 ... 3:
-                size_each = 0x10000000;
-                break;
-
-        case 4 ... 6:
-                size_each = 0x08000000;
-                break;
-
-        case 7:
-                size_each = 0x04000000;
-                break;
-
-        default:
-                panic("invalid number of PCIe ports");
-        }
-
-        start = MV78XX0_PCIE_MEM_PHYS_BASE;
-        for (i = 0; i < num_pcie_ports; i++) {
-                struct pcie_port *pp = pcie_port + i;
-
-                pp->res[1].start = start;
-                pp->res[1].end = start + size_each - 1;
+                pp->res.name = pp->mem_space_name;
+                pp->res.flags = IORESOURCE_MEM;
+                pp->res.start = start;
+                pp->res.end = start + size_each - 1;
                 start += size_each;
-        }
-
-        for (i = 0; i < num_pcie_ports; i++) {
-                struct pcie_port *pp = pcie_port + i;
 
-                if (request_resource(&pcie_io_space, &pp->res[0]))
-                        panic("can't allocate PCIe I/O sub-space");
-
-                if (request_resource(&pcie_mem_space, &pp->res[1]))
+                if (request_resource(&iomem_resource, &pp->res))
                         panic("can't allocate PCIe MEM sub-space");
-        }
 
-        win = 0;
-        for (i = 0; i < num_pcie_ports; i++) {
-                struct pcie_port *pp = pcie_port + i;
+                mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
+                                           resource_size(&pp->res),
+                                           pp->maj, pp->min);
 
-                mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
-                                          resource_size(&pp->res[0]),
+                mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
                                           pp->maj, pp->min);
-
-                mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
-                                           resource_size(&pp->res[1]),
-                                           pp->maj, pp->min);
         }
 }
 
@@ -156,8 +111,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
         orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
         orion_pcie_setup(pp->base);
 
-        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
-        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+        pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
+
+        pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
 
         return 1;
 }
@@ -267,11 +223,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
         .map_irq        = mv78xx0_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int maj, int min, unsigned long base)
+static void __init add_pcie_port(int maj, int min, void __iomem *base)
 {
         printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
 
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
 
                 printk("link up\n");
@@ -279,9 +235,9 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
                 pp->maj = maj;
                 pp->min = min;
                 pp->root_bus_nr = -1;
-                pp->base = (void __iomem *)base;
+                pp->base = base;
                 spin_lock_init(&pp->conf_lock);
-                memset(pp->res, 0, sizeof(pp->res));
+                memset(&pp->res, 0, sizeof(pp->res));
         } else {
                 printk("link down, ignoring\n");
         }
@@ -293,7 +249,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
 
         if (init_port0) {
                 add_pcie_port(0, 0, PCIE00_VIRT_BASE);
-                if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
+                if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
                         add_pcie_port(0, 1, PCIE01_VIRT_BASE);
                         add_pcie_port(0, 2, PCIE02_VIRT_BASE);
                         add_pcie_port(0, 3, PCIE03_VIRT_BASE);
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e734fe..416d46ef7ebd 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,15 +1,39 @@
+config ARCH_MVEBU
+        bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+        select CLKSRC_MMIO
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select IRQ_DOMAIN
+        select MULTI_IRQ_HANDLER
+        select PINCTRL
+        select PLAT_ORION
+        select SPARSE_IRQ
+
 if ARCH_MVEBU
 
 menu "Marvell SOC with device tree"
 
 config MACH_ARMADA_370_XP
-        bool "Marvell Armada 370 and Aramada XP boards"
+        bool
         select ARMADA_370_XP_TIMER
         select CPU_V7
+
+config MACH_ARMADA_370
+        bool "Marvell Armada 370 boards"
+        select MACH_ARMADA_370_XP
+        select PINCTRL_ARMADA_370
         help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada 370 SoC with device tree.
 
-          Say 'Y' here if you want your kernel to support boards based on
-          Marvell Armada 370 or Armada XP with device tree.
+config MACH_ARMADA_XP
+        bool "Marvell Armada XP boards"
+        select MACH_ARMADA_370_XP
+        select PINCTRL_ARMADA_XP
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada XP SoC with device tree.
 
 endmenu
 
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index e61d2b8fdf50..57f996b6aa0e 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,2 +1,5 @@
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+        -I$(srctree)/arch/arm/plat-orion/include
+
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
diff --git a/arch/arm/mach-mvebu/Makefile.boot b/arch/arm/mach-mvebu/Makefile.boot
deleted file mode 100644
index 2579a2fc2334..000000000000
--- a/arch/arm/mach-mvebu/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y := 0x00008000
-dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-db.dtb
-dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-xp-db.dtb
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
new file mode 100644
index 000000000000..fe454a4430be
--- /dev/null
+++ b/arch/arm/mach-mvebu/addr-map.c
@@ -0,0 +1,134 @@
+/*
+ * Address map functions for Marvell 370 / XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <plat/addr-map.h>
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define ARMADA_XP_TARGET_DEV_BUS        1
+#define   ARMADA_XP_ATTR_DEV_BOOTROM    0x1D
+#define ARMADA_XP_TARGET_ETH1           3
+#define ARMADA_XP_TARGET_PCIE_0_2       4
+#define ARMADA_XP_TARGET_ETH0           7
+#define ARMADA_XP_TARGET_PCIE_1_3       8
+
+#define ARMADA_370_TARGET_DEV_BUS       1
+#define   ARMADA_370_ATTR_DEV_BOOTROM   0x1D
+#define ARMADA_370_TARGET_PCIE_0        4
+#define ARMADA_370_TARGET_PCIE_1        8
+
+#define ARMADA_WINDOW_8_PLUS_OFFSET       0x90
+#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
+
+static const struct __initdata orion_addr_map_info
+armada_xp_addr_map_info[] = {
+        /*
+         * Window for the BootROM, needed for SMP on Armada XP
+         */
+        { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
+          ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 },
+};
+
+static const struct __initdata orion_addr_map_info
+armada_370_addr_map_info[] = {
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 },
+};
+
+static struct of_device_id of_addr_decoding_controller_table[] = {
+        { .compatible = "marvell,armada-addr-decoding-controller" },
+        { /* end of list */ },
+};
+
+static void __iomem *
+armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
+{
+        unsigned int offset;
+
+        /* The register layout is a bit annoying and the below code
+         * tries to cope with it.
+         * - At offset 0x0, there are the registers for the first 8
+         *   windows, with 4 registers of 32 bits per window (ctrl,
+         *   base, remap low, remap high)
+         * - Then at offset 0x80, there is a hole of 0x10 bytes for
+         *   the internal registers base address and internal units
+         *   sync barrier register.
+         * - Then at offset 0x90, there the registers for 12
+         *   windows, with only 2 registers of 32 bits per window
+         *   (ctrl, base).
+         */
+        if (win < 8)
+                offset = (win << 4);
+        else
+                offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
+
+        return cfg->bridge_virt_base + offset;
+}
+
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 20,
+        .remappable_wins = 8,
+        .win_cfg_base = armada_cfg_base,
+};
+
+static int __init armada_setup_cpu_mbus(void)
+{
+        struct device_node *np;
+        void __iomem *mbus_unit_addr_decoding_base;
+        void __iomem *sdram_addr_decoding_base;
+
+        np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
+        if (!np)
+                return -ENODEV;
+
+        mbus_unit_addr_decoding_base = of_iomap(np, 0);
+        BUG_ON(!mbus_unit_addr_decoding_base);
+
+        sdram_addr_decoding_base =
+                mbus_unit_addr_decoding_base +
+                ARMADA_SDRAM_ADDR_DECODING_OFFSET;
+
+        addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
+
+        /*
+         * Disable, clear and configure windows.
+         */
+        if (of_machine_is_compatible("marvell,armadaxp"))
+                orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
+        else if (of_machine_is_compatible("marvell,armada370"))
+                orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
+        else {
+                pr_err("Unsupported SoC\n");
+                return -EINVAL;
+        }
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    sdram_addr_decoding_base);
+        return 0;
+}
+
+/* Using a early_initcall is needed so that this initialization gets
+ * done before the SMP initialization, which requires the BootROM to
+ * be remapped. */
+early_initcall(armada_setup_cpu_mbus);
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 4ef923b032ec..49d791548ad6 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -20,12 +20,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/armada-370-xp.h>
+#include "armada-370-xp.h"
 #include "common.h"
 
 static struct map_desc armada_370_xp_io_desc[] __initdata = {
         {
-                .virtual        = ARMADA_370_XP_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
                 .length         = ARMADA_370_XP_REGS_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 25f0ca8d7820..aac9bebc6b03 100644
--- a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,7 +16,7 @@
 #define __MACH_ARMADA_370_XP_H
 
 #define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE    0xfeb00000
+#define ARMADA_370_XP_REGS_VIRT_BASE    IOMEM(0xfeb00000)
 #define ARMADA_370_XP_REGS_SIZE         SZ_1M
 
 #endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/arch/arm/mach-ep93xx/include/mach/gpio.h
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
diff --git a/arch/arm/mach-mvebu/include/mach/timex.h b/arch/arm/mach-mvebu/include/mach/timex.h
deleted file mode 100644
index ab324a3748f2..000000000000
--- a/arch/arm/mach-mvebu/include/mach/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Marvell Armada SoC time definitions
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-mvebu/include/mach/uncompress.h b/arch/arm/mach-mvebu/include/mach/uncompress.h
deleted file mode 100644
index d6a100ccf302..000000000000
--- a/arch/arm/mach-mvebu/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Marvell Armada SoC kernel uncompression UART routines
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <mach/armada-370-xp.h>
-
-#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
-                                                                + 0x12000))
-#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
-                                                                + 0x12014))
-
-#define LSR_THRE        0x20
-
-static void putc(const char c)
-{
-        int i;
-
-        for (i = 0; i < 0x1000; i++) {
-                /* Transmit fifo not full? */
-                if (*UART_LSR & LSR_THRE)
-                        break;
-        }
-
-        *UART_THR = c;
-}
-
-static void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 9a8bbda195b2..ecc431909d6f 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -1,7 +1,5 @@
 if ARCH_MXS
 
-source "arch/arm/mach-mxs/devices/Kconfig"
-
 config SOC_IMX23
         bool
         select ARM_AMBA
@@ -27,91 +25,4 @@ config MACH_MXS_DT
           Include support for Freescale MXS platforms(i.MX23 and i.MX28)
           using the device tree for discovery
 
-config MACH_STMP378X_DEVB
-        bool "Support STMP378x_devb Platform"
-        select SOC_IMX23
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        help
-          Include support for STMP378x-devb platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX23EVK
-        bool "Support MX23EVK Platform"
-        select SOC_IMX23
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXSFB
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        help
-          Include support for MX23EVK platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX28EVK
-        bool "Support MX28EVK Platform"
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_FLEXCAN
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXSFB
-        select MXS_HAVE_PLATFORM_MXS_SAIF
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        help
-          Include support for MX28EVK platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MODULE_TX28
-        bool
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXS_PWM
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-
-config MODULE_M28
-        bool
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_FLEXCAN
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXSFB
-
-config MODULE_APX4
-        bool
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXS_SAIF
-
-config MACH_TX28
-        bool "Ka-Ro TX28 module"
-        select MODULE_TX28
-
-config MACH_M28EVK
-        bool "Support DENX M28EVK Platform"
-        select MODULE_M28
-
-config MACH_APX4DEVKIT
-        bool "Support Bluegiga APX4 Development Kit"
-        select MODULE_APX4
-
 endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index fed3695a1339..3d3c8a973062 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,15 +1,6 @@
 # Common support
-obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o
+obj-y := icoll.o ocotp.o system.o timer.o mm.o
 
 obj-$(CONFIG_PM) += pm.o
 
 obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
-obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
-obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
-obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
-obj-$(CONFIG_MACH_M28EVK)    += mach-m28evk.o
-obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o
-obj-$(CONFIG_MODULE_TX28) += module-tx28.o
-obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
-
-obj-y += devices/
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
index 4582999cf080..07b11fe6453f 100644
--- a/arch/arm/mach-mxs/Makefile.boot
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -1,10 +1 @@
 zreladdr-y += 0x40008000
-
-dtb-y += imx23-evk.dtb \
-         imx23-olinuxino.dtb \
-         imx23-stmp378x_devb.dtb \
-         imx28-apx4devkit.dtb \
-         imx28-cfa10036.dtb \
-         imx28-evk.dtb \
-         imx28-m28evk.dtb \
-         imx28-tx28.dtb \
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
deleted file mode 100644
index 9ee5cede3d42..000000000000
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx23.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-#include <linux/amba/bus.h>
-
-static inline int mx23_add_duart(void)
-{
-        struct amba_device *d;
-
-        d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K,
-                                MX23_INT_DUART, 0, 0, 0);
-        return IS_ERR(d) ? PTR_ERR(d) : 0;
-}
-
-extern const struct mxs_auart_data mx23_auart_data[] __initconst;
-#define mx23_add_auart(id)      mxs_add_auart(&mx23_auart_data[id])
-#define mx23_add_auart0()               mx23_add_auart(0)
-#define mx23_add_auart1()               mx23_add_auart(1)
-
-extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst;
-#define mx23_add_gpmi_nand(pdata)       \
-        mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data)
-
-extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst;
-#define mx23_add_mxs_mmc(id, pdata) \
-        mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata)
-
-#define mx23_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
-
-struct platform_device *__init mx23_add_mxsfb(
-                const struct mxsfb_platform_data *pdata);
-
-struct platform_device *__init mx23_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
deleted file mode 100644
index fcab431060f4..000000000000
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-#include <linux/amba/bus.h>
-
-static inline int mx28_add_duart(void)
-{
-        struct amba_device *d;
-
-        d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K,
-                                MX28_INT_DUART, 0, 0, 0);
-        return IS_ERR(d) ? PTR_ERR(d) : 0;
-}
-
-extern const struct mxs_auart_data mx28_auart_data[] __initconst;
-#define mx28_add_auart(id)      mxs_add_auart(&mx28_auart_data[id])
-#define mx28_add_auart0()               mx28_add_auart(0)
-#define mx28_add_auart1()               mx28_add_auart(1)
-#define mx28_add_auart2()               mx28_add_auart(2)
-#define mx28_add_auart3()               mx28_add_auart(3)
-#define mx28_add_auart4()               mx28_add_auart(4)
-
-extern const struct mxs_fec_data mx28_fec_data[] __initconst;
-#define mx28_add_fec(id, pdata) \
-        mxs_add_fec(&mx28_fec_data[id], pdata)
-
-extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
-#define mx28_add_flexcan(id, pdata)     \
-        mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
-#define mx28_add_flexcan0(pdata)        mx28_add_flexcan(0, pdata)
-#define mx28_add_flexcan1(pdata)        mx28_add_flexcan(1, pdata)
-
-extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst;
-#define mx28_add_gpmi_nand(pdata)       \
-        mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data)
-
-extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
-#define mx28_add_mxs_i2c(id)            mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
-
-extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;
-#define mx28_add_mxs_mmc(id, pdata) \
-        mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata)
-
-#define mx28_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
-
-struct platform_device *__init mx28_add_mxsfb(
-                const struct mxsfb_platform_data *pdata);
-
-extern const struct mxs_saif_data mx28_saif_data[] __initconst;
-#define mx28_add_saif(id, pdata) \
-        mxs_add_saif(&mx28_saif_data[id], pdata)
-
-struct platform_device *__init mx28_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
deleted file mode 100644
index cf50b5a66dda..000000000000
--- a/arch/arm/mach-mxs/devices.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-
-struct platform_device *__init mxs_add_platform_device_dmamask(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data, u64 dmamask)
-{
-        int ret = -ENOMEM;
-        struct platform_device *pdev;
-
-        pdev = platform_device_alloc(name, id);
-        if (!pdev)
-                goto err;
-
-        if (dmamask) {
-                /*
-                 * This memory isn't freed when the device is put,
-                 * I don't have a nice idea for that though.  Conceptually
-                 * dma_mask in struct device should not be a pointer.
-                 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
-                 */
-                pdev->dev.dma_mask =
-                        kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
-                if (!pdev->dev.dma_mask)
-                        /* ret is still -ENOMEM; */
-                        goto err;
-
-                *pdev->dev.dma_mask = dmamask;
-                pdev->dev.coherent_dma_mask = dmamask;
-        }
-
-        if (res) {
-                ret = platform_device_add_resources(pdev, res, num_resources);
-                if (ret)
-                        goto err;
-        }
-
-        if (data) {
-                ret = platform_device_add_data(pdev, data, size_data);
-                if (ret)
-                        goto err;
-        }
-
-        ret = platform_device_add(pdev);
-        if (ret) {
-err:
-                if (dmamask)
-                        kfree(pdev->dev.dma_mask);
-                platform_device_put(pdev);
-                return ERR_PTR(ret);
-        }
-
-        return pdev;
-}
-
-struct device mxs_apbh_bus = {
-        .init_name      = "mxs_apbh",
-        .parent         = &platform_bus,
-};
-
-static int __init mxs_device_init(void)
-{
-        return device_register(&mxs_apbh_bus);
-}
-core_initcall(mxs_device_init);
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
deleted file mode 100644
index 19659de1c4e8..000000000000
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-config MXS_HAVE_AMBA_DUART
-        bool
-
-config MXS_HAVE_PLATFORM_AUART
-        bool
-
-config MXS_HAVE_PLATFORM_FEC
-        bool
-
-config MXS_HAVE_PLATFORM_FLEXCAN
-        select HAVE_CAN_FLEXCAN if CAN
-        bool
-
-config MXS_HAVE_PLATFORM_GPMI_NAND
-        bool
-
-config MXS_HAVE_PLATFORM_MXS_I2C
-        bool
-
-config MXS_HAVE_PLATFORM_MXS_MMC
-        bool
-
-config MXS_HAVE_PLATFORM_MXS_PWM
-        bool
-
-config MXS_HAVE_PLATFORM_MXSFB
-        bool
-
-config MXS_HAVE_PLATFORM_MXS_SAIF
-        bool
-
-config MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
deleted file mode 100644
index 5f72d9787444..000000000000
--- a/arch/arm/mach-mxs/devices/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
-obj-y += platform-dma.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
-obj-y += platform-gpio-mxs.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
deleted file mode 100644
index 27608f5d2ac8..000000000000
--- a/arch/arm/mach-mxs/devices/platform-auart.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_auart_data_entry_single(soc, _id, hwid)                     \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _AUART ## hwid ## _BASE_ADDR,          \
-                .irq = soc ## _INT_AUART ## hwid,                       \
-        }
-
-#define mxs_auart_data_entry(soc, _id, hwid)                            \
-        [_id] = mxs_auart_data_entry_single(soc, _id, hwid)
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_auart_data mx23_auart_data[] __initconst = {
-#define mx23_auart_data_entry(_id, hwid)                                \
-        mxs_auart_data_entry(MX23, _id, hwid)
-        mx23_auart_data_entry(0, 1),
-        mx23_auart_data_entry(1, 2),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_auart_data mx28_auart_data[] __initconst = {
-#define mx28_auart_data_entry(_id)                                      \
-        mxs_auart_data_entry(MX28, _id, _id)
-        mx28_auart_data_entry(0),
-        mx28_auart_data_entry(1),
-        mx28_auart_data_entry(2),
-        mx28_auart_data_entry(3),
-        mx28_auart_data_entry(4),
-};
-#endif
-
-struct platform_device *__init mxs_add_auart(
-                const struct mxs_auart_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device_dmamask("mxs-auart", data->id,
-                                        res, ARRAY_SIZE(res), NULL, 0,
-                                        DMA_BIT_MASK(32));
-}
-
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
deleted file mode 100644
index 46824501de00..000000000000
--- a/arch/arm/mach-mxs/devices/platform-dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/dma-mapping.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-struct platform_device *__init mxs_add_dma(const char *devid,
-                                                resource_size_t base)
-{
-        struct resource res[] = {
-                {
-                        .start = base,
-                        .end = base + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }
-        };
-
-        return mxs_add_platform_device_dmamask(devid, -1,
-                                res, ARRAY_SIZE(res), NULL, 0,
-                                DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
deleted file mode 100644
index ae96a4fd8f14..000000000000
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_fec_data_entry_single(soc, _id)                             \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR,        \
-                .irq = soc ## _INT_ENET_MAC ## _id,                     \
-        }
-
-#define mxs_fec_data_entry(soc, _id)                                    \
-        [_id] = mxs_fec_data_entry_single(soc, _id)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_fec_data mx28_fec_data[] __initconst = {
-#define mx28_fec_data_entry(_id)                                        \
-        mxs_fec_data_entry(MX28, _id)
-        mx28_fec_data_entry(0),
-        mx28_fec_data_entry(1),
-};
-#endif
-
-struct platform_device *__init mxs_add_fec(
-                const struct mxs_fec_data *data,
-                const struct fec_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device_dmamask("imx28-fec", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
-                        DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c
deleted file mode 100644
index 43a6b4bae6fe..000000000000
--- a/arch/arm/mach-mxs/devices/platform-flexcan.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2010, 2011 Pengutronix,
- *                          Marc Kleine-Budde <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)           \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_CAN ## _hwid,                        \
-        }
-
-#define mxs_flexcan_data_entry(soc, _id, _hwid, _size)                  \
-        [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = {
-#define mx28_flexcan_data_entry(_id, _hwid)                             \
-        mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K)
-        mx28_flexcan_data_entry(0, 0),
-        mx28_flexcan_data_entry(1, 1),
-};
-#endif /* ifdef CONFIG_SOC_IMX28 */
-
-struct platform_device *__init mxs_add_flexcan(
-                const struct mxs_flexcan_data *data,
-                const struct flexcan_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device("flexcan", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
deleted file mode 100644
index cd99f19ec637..000000000000
--- a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-struct platform_device *__init mxs_add_gpio(
-        char *name, int id, resource_size_t iobase, int irq)
-{
-        struct resource res[] = {
-                {
-                        .start = iobase,
-                        .end = iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = irq,
-                        .end = irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return platform_device_register_resndata(&mxs_apbh_bus,
-                        name, id, res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
deleted file mode 100644
index 3e22df5944a8..000000000000
--- a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/dma-mapping.h>
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = {
-        .devid = "imx23-gpmi-nand",
-        .res = {
-                /* GPMI */
-                DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION,
-                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
-                /* BCH */
-                DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX23_INT_BCH,
-                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
-                /* DMA */
-                DEFINE_RES_NAMED(MX23_DMA_GPMI0,
-                                        MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1,
-                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
-                                        IORESOURCE_DMA),
-                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA,
-                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
-        },
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = {
-        .devid = "imx28-gpmi-nand",
-        .res = {
-                /* GPMI */
-                DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI,
-                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
-                /* BCH */
-                DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX28_INT_BCH,
-                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
-                /* DMA */
-                DEFINE_RES_NAMED(MX28_DMA_GPMI0,
-                                        MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1,
-                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
-                                        IORESOURCE_DMA),
-                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA,
-                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
-        },
-};
-#endif
-
-struct platform_device *__init
-mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
-                const struct mxs_gpmi_nand_data *data)
-{
-        return mxs_add_platform_device_dmamask(data->devid, -1,
-                                data->res, GPMI_NAND_RES_SIZE,
-                                pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
deleted file mode 100644
index 79222ec8ede1..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix
- * Wolfram Sang <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_i2c_data_entry_single(soc, _id)                             \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _I2C ## _id ## _BASE_ADDR,             \
-                .errirq = soc ## _INT_I2C ## _id ## _ERROR,             \
-                .dmairq = soc ## _INT_I2C ## _id ## _DMA,               \
-        }
-
-#define mxs_i2c_data_entry(soc, _id)                                    \
-        [_id] = mxs_i2c_data_entry_single(soc, _id)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
-        mxs_i2c_data_entry(MX28, 0),
-        mxs_i2c_data_entry(MX28, 1),
-};
-#endif
-
-struct platform_device *__init mxs_add_mxs_i2c(
-                const struct mxs_mxs_i2c_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->errirq,
-                        .end = data->errirq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->dmairq,
-                        .end = data->dmairq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device("mxs-i2c", data->id, res,
-                                        ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
deleted file mode 100644
index b33c9d05c552..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid)           \
-        {                                                               \
-                .devid = _devid,                                        \
-                .id = _id,                                              \
-                .iobase = soc ## _SSP ## hwid ## _BASE_ADDR,            \
-                .dma = soc ## _DMA_SSP ## hwid,                         \
-                .irq_err = soc ## _INT_SSP ## hwid ## _ERROR,           \
-                .irq_dma = soc ## _INT_SSP ## hwid ## _DMA,             \
-        }
-
-#define mxs_mxs_mmc_data_entry(soc, _devid, _id, hwid)                  \
-        [_id] = mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid)
-
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = {
-        mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 0, 1),
-        mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 1, 2),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = {
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 0, 0),
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 1, 1),
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 2, 2),
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 3, 3),
-};
-#endif
-
-struct platform_device *__init mxs_add_mxs_mmc(
-                const struct mxs_mxs_mmc_data *data,
-                const struct mxs_mmc_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start  = data->iobase,
-                        .end    = data->iobase + SZ_8K - 1,
-                        .flags  = IORESOURCE_MEM,
-                }, {
-                        .start  = data->dma,
-                        .end    = data->dma,
-                        .flags  = IORESOURCE_DMA,
-                }, {
-                        .start  = data->irq_err,
-                        .end    = data->irq_err,
-                        .flags  = IORESOURCE_IRQ,
-                }, {
-                        .start  = data->irq_dma,
-                        .end    = data->irq_dma,
-                        .flags  = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device(data->devid, data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
deleted file mode 100644
index 680f5a902936..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/devices-common.h>
-
-struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id)
-{
-        struct resource res = {
-                .flags = IORESOURCE_MEM,
-        };
-
-        res.start = iobase + 0x10 + 0x20 * id;
-        res.end = res.start + 0x1f;
-
-        return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
deleted file mode 100644
index f6e3a60b4201..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_saif_data_entry_single(soc, _id)                            \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _SAIF ## _id ## _BASE_ADDR,            \
-                .irq = soc ## _INT_SAIF ## _id,                         \
-                .dma = soc ## _DMA_SAIF ## _id,                         \
-                .dmairq = soc ## _INT_SAIF ## _id ##_DMA,               \
-        }
-
-#define mxs_saif_data_entry(soc, _id)                                   \
-        [_id] = mxs_saif_data_entry_single(soc, _id)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_saif_data mx28_saif_data[] __initconst = {
-        mxs_saif_data_entry(MX28, 0),
-        mxs_saif_data_entry(MX28, 1),
-};
-#endif
-
-struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data,
-                                const struct mxs_saif_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->dma,
-                        .end = data->dma,
-                        .flags = IORESOURCE_DMA,
-                }, {
-                        .start = data->dmairq,
-                        .end = data->dmairq,
-                        .flags = IORESOURCE_IRQ,
-                },
-
-        };
-
-        return mxs_add_platform_device("mxs-saif", data->id, res,
-                                ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
deleted file mode 100644
index 76b53f73418e..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxsfb.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-
-#ifdef CONFIG_SOC_IMX23
-struct platform_device *__init mx23_add_mxsfb(
-                const struct mxsfb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = MX23_LCDIF_BASE_ADDR,
-                        .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-
-        return mxs_add_platform_device_dmamask("imx23-fb", -1,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-#endif /* ifdef CONFIG_SOC_IMX23 */
-
-#ifdef CONFIG_SOC_IMX28
-struct platform_device *__init mx28_add_mxsfb(
-                const struct mxsfb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = MX28_LCDIF_BASE_ADDR,
-                        .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-
-        return mxs_add_platform_device_dmamask("imx28-fb", -1,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-#endif /* ifdef CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
deleted file mode 100644
index 639eaee15553..000000000000
--- a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#ifdef CONFIG_SOC_IMX23
-struct platform_device *__init mx23_add_rtc_stmp3xxx(void)
-{
-        struct resource res[] = {
-                {
-                        .start = MX23_RTC_BASE_ADDR,
-                        .end = MX23_RTC_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = MX23_INT_RTC_ALARM,
-                        .end = MX23_INT_RTC_ALARM,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
-                                        NULL, 0);
-}
-#endif /* CONFIG_SOC_IMX23 */
-
-#ifdef CONFIG_SOC_IMX28
-struct platform_device *__init mx28_add_rtc_stmp3xxx(void)
-{
-        struct resource res[] = {
-                {
-                        .start = MX28_RTC_BASE_ADDR,
-                        .end = MX28_RTC_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = MX28_INT_RTC_ALARM,
-                        .end = MX28_INT_RTC_ALARM,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
-                                        NULL, 0);
-}
-#endif /* CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index de6c7ba42544..4dec79563f19 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -17,21 +17,12 @@ extern void mxs_timer_init(int);
 extern void mxs_restart(char, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
 
-extern void mx23_soc_init(void);
 extern int mx23_clocks_init(void);
 extern void mx23_map_io(void);
-extern void mx23_init_irq(void);
 
-extern void mx28_soc_init(void);
 extern int mx28_clocks_init(void);
 extern void mx28_map_io(void);
-extern void mx28_init_irq(void);
 
 extern void icoll_init_irq(void);
 
-extern struct platform_device *mxs_add_dma(const char *devid,
-                                                resource_size_t base);
-extern struct platform_device *mxs_add_gpio(char *name, int id,
-                                            resource_size_t iobase, int irq);
-
 #endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
deleted file mode 100644
index e8b1d958240b..000000000000
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/amba/bus.h>
-
-extern struct device mxs_apbh_bus;
-
-struct platform_device *mxs_add_platform_device_dmamask(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data, u64 dmamask);
-
-static inline struct platform_device *mxs_add_platform_device(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data)
-{
-        return mxs_add_platform_device_dmamask(
-                        name, id, res, num_resources, data, size_data, 0);
-}
-
-/* auart */
-struct mxs_auart_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_auart(
-                const struct mxs_auart_data *data);
-
-/* fec */
-#include <linux/fec.h>
-struct mxs_fec_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_fec(
-                const struct mxs_fec_data *data,
-                const struct fec_platform_data *pdata);
-
-/* flexcan */
-#include <linux/can/platform/flexcan.h>
-struct mxs_flexcan_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_flexcan(
-                const struct mxs_flexcan_data *data,
-                const struct flexcan_platform_data *pdata);
-
-/* gpmi-nand */
-#include <linux/mtd/gpmi-nand.h>
-struct mxs_gpmi_nand_data {
-        const char *devid;
-        const struct resource res[GPMI_NAND_RES_SIZE];
-};
-struct platform_device *__init
-mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
-                const struct mxs_gpmi_nand_data *data);
-
-/* i2c */
-struct mxs_mxs_i2c_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t errirq;
-        resource_size_t dmairq;
-};
-struct platform_device * __init mxs_add_mxs_i2c(
-                const struct mxs_mxs_i2c_data *data);
-
-/* mmc */
-#include <linux/mmc/mxs-mmc.h>
-struct mxs_mxs_mmc_data {
-        const char *devid;
-        int id;
-        resource_size_t iobase;
-        resource_size_t dma;
-        resource_size_t irq_err;
-        resource_size_t irq_dma;
-};
-struct platform_device *__init mxs_add_mxs_mmc(
-                const struct mxs_mxs_mmc_data *data,
-                const struct mxs_mmc_platform_data *pdata);
-
-/* pwm */
-struct platform_device *__init mxs_add_mxs_pwm(
-                resource_size_t iobase, int id);
-
-/* saif */
-#include <sound/saif.h>
-struct mxs_saif_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t irq;
-        resource_size_t dma;
-        resource_size_t dmairq;
-};
-
-struct platform_device *__init mxs_add_saif(
-                const struct mxs_saif_data *data,
-                const struct mxs_saif_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-mxs/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
deleted file mode 100644
index b0190a4822f2..000000000000
--- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX23_H__
-#define __MACH_IOMUX_MX23_H__
-
-#include <mach/iomux.h>
-
-/*
- * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux.h
- *
- *                                                                      BANK    PIN     MUX
- */
-/* MUXSEL_0 */
-#define MX23_PAD_GPMI_D00__GPMI_D00             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D01__GPMI_D01             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D02__GPMI_D02             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D03__GPMI_D03             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D04__GPMI_D04             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D05__GPMI_D05             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D06__GPMI_D06             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D07__GPMI_D07             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D08__GPMI_D08             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D09__GPMI_D09             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D10__GPMI_D10             MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D11__GPMI_D11             MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D12__GPMI_D12             MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D13__GPMI_D13             MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D14__GPMI_D14             MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D15__GPMI_D15             MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CLE__GPMI_CLE             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_ALE__GPMI_ALE             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE2N__GPMI_CE2N           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY0__GPMI_RDY0           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY1__GPMI_RDY1           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY2__GPMI_RDY2           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY3__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_WPN__GPMI_WPN             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_WRN__GPMI_WRN             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDN__GPMI_RDN             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_CTS__AUART1_CTS         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_RTS__AUART1_RTS         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_RX__AUART1_RX           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_TX__AUART1_TX           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
-#define MX23_PAD_I2C_SCL__I2C_SCL               MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
-#define MX23_PAD_I2C_SDA__I2C_SDA               MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
-
-#define MX23_PAD_LCD_D00__LCD_D00               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D01__LCD_D01               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D02__LCD_D02               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D03__LCD_D03               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D04__LCD_D04               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D05__LCD_D05               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D06__LCD_D06               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D07__LCD_D07               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D08__LCD_D08               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D09__LCD_D09               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D10__LCD_D10               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D11__LCD_D11               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D12__LCD_D12               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D13__LCD_D13               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D14__LCD_D14               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D15__LCD_D15               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D16__LCD_D16               MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D17__LCD_D17               MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_RESET__LCD_RESET           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_RS__LCD_RS                 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_WR__LCD_WR                 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_CS__LCD_CS                 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_DOTCK__LCD_DOTCK           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_ENABLE__LCD_ENABLE         MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_HSYNC__LCD_HSYNC           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_VSYNC__LCD_VSYNC           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
-#define MX23_PAD_PWM0__PWM0                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
-#define MX23_PAD_PWM1__PWM1                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
-#define MX23_PAD_PWM2__PWM2                     MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
-#define MX23_PAD_PWM3__PWM3                     MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
-#define MX23_PAD_PWM4__PWM4                     MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
-
-#define MX23_PAD_SSP1_CMD__SSP1_CMD             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DETECT__SSP1_DETECT       MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA0__SSP1_DATA0         MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA1__SSP1_DATA1         MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA2__SSP1_DATA2         MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA3__SSP1_DATA3         MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_SCK__SSP1_SCK             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
-#define MX23_PAD_ROTARYA__ROTARYA               MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
-#define MX23_PAD_ROTARYB__ROTARYB               MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A00__EMI_A00               MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A01__EMI_A01               MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A02__EMI_A02               MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A03__EMI_A03               MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A04__EMI_A04               MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A05__EMI_A05               MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A06__EMI_A06               MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A07__EMI_A07               MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A08__EMI_A08               MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A09__EMI_A09               MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A10__EMI_A10               MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A11__EMI_A11               MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A12__EMI_A12               MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_BA0__EMI_BA0               MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_BA1__EMI_BA1               MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CASN__EMI_CASN             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CE0N__EMI_CE0N             MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CE1N__EMI_CE1N             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE1N__GPMI_CE1N           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE0N__GPMI_CE0N           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CKE__EMI_CKE               MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_RASN__EMI_RASN             MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_WEN__EMI_WEN               MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
-
-#define MX23_PAD_EMI_D00__EMI_D00               MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D01__EMI_D01               MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D02__EMI_D02               MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D03__EMI_D03               MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D04__EMI_D04               MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D05__EMI_D05               MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D06__EMI_D06               MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D07__EMI_D07               MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D08__EMI_D08               MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D09__EMI_D09               MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D10__EMI_D10               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D11__EMI_D11               MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D12__EMI_D12               MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D13__EMI_D13               MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D14__EMI_D14               MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D15__EMI_D15               MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQM0__EMI_DQM0             MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQM1__EMI_DQM1             MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQS0__EMI_DQS0             MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQS1__EMI_DQS1             MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CLK__EMI_CLK               MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CLKN__EMI_CLKN             MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
-
-/* MUXSEL_1 */
-#define MX23_PAD_GPMI_D00__LCD_D8               MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D01__LCD_D9               MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D02__LCD_D10              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D03__LCD_D11              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D04__LCD_D12              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D05__LCD_D13              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D06__LCD_D14              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D07__LCD_D15              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D08__LCD_D18              MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D09__LCD_D19              MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D10__LCD_D20              MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D11__LCD_D21              MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D12__LCD_D22              MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D13__LCD_D23              MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D14__AUART2_RX            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D15__AUART2_TX            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_CLE__LCD_D16              MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_ALE__LCD_D17              MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_CE2N__ATA_A2              MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_RTS__IR_CLK             MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_RX__IR_RX               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_TX__IR_TX               MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
-#define MX23_PAD_I2C_SCL__GPMI_RDY2             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
-#define MX23_PAD_I2C_SDA__GPMI_CE2N             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
-
-#define MX23_PAD_LCD_D00__ETM_DA8               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D01__ETM_DA9               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D02__ETM_DA10              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D03__ETM_DA11              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D04__ETM_DA12              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D05__ETM_DA13              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D06__ETM_DA14              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D07__ETM_DA15              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D08__ETM_DA0               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D09__ETM_DA1               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D10__ETM_DA2               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D11__ETM_DA3               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D12__ETM_DA4               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D13__ETM_DA5               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D14__ETM_DA6               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D15__ETM_DA7               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_RESET__ETM_TCTL            MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_RS__ETM_TCLK               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_DOTCK__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_ENABLE__I2C_SCL            MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_HSYNC__I2C_SDA             MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_VSYNC__LCD_BUSY            MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
-#define MX23_PAD_PWM0__ROTARYA                  MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
-#define MX23_PAD_PWM1__ROTARYB                  MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
-#define MX23_PAD_PWM2__GPMI_RDY3                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
-#define MX23_PAD_PWM3__ETM_TCTL                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
-#define MX23_PAD_PWM4__ETM_TCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
-
-#define MX23_PAD_SSP1_DETECT__GPMI_CE3N         MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DATA1__I2C_SCL            MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DATA2__I2C_SDA            MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
-#define MX23_PAD_ROTARYA__AUART2_RTS            MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
-#define MX23_PAD_ROTARYB__AUART2_CTS            MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
-
-/* MUXSEL_2 */
-#define MX23_PAD_GPMI_D00__SSP2_DATA0           MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D01__SSP2_DATA1           MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D02__SSP2_DATA2           MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D03__SSP2_DATA3           MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D04__SSP2_DATA4           MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D05__SSP2_DATA5           MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D06__SSP2_DATA6           MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D07__SSP2_DATA7           MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D08__SSP1_DATA4           MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D09__SSP1_DATA5           MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D10__SSP1_DATA6           MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D11__SSP1_DATA7           MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D15__GPMI_CE3N            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_RDY0__SSP2_DETECT         MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_RDY1__SSP2_CMD            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_WRN__SSP2_SCK             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_CTS__SSP1_DATA4         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_RTS__SSP1_DATA5         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_RX__SSP1_DATA6          MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_TX__SSP1_DATA7          MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
-#define MX23_PAD_I2C_SCL__AUART1_TX             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
-#define MX23_PAD_I2C_SDA__AUART1_RX             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
-
-#define MX23_PAD_LCD_D08__SAIF2_SDATA0          MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D09__SAIF1_SDATA0          MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D11__SAIF_LRCLK            MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D12__SAIF2_SDATA1          MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D13__SAIF2_SDATA2          MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D14__SAIF1_SDATA2          MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D15__SAIF1_SDATA1          MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_RESET__GPMI_CE3N           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
-#define MX23_PAD_PWM0__DUART_RX                 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
-#define MX23_PAD_PWM1__DUART_TX                 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
-#define MX23_PAD_PWM3__AUART1_CTS               MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
-#define MX23_PAD_PWM4__AUART1_RTS               MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
-
-#define MX23_PAD_SSP1_CMD__JTAG_TDO             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DETECT__USB_OTG_ID        MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA0__JTAG_TDI           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA1__JTAG_TCLK          MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA2__JTAG_RTCK          MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA3__JTAG_TMS           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_SCK__JTAG_TRST            MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
-#define MX23_PAD_ROTARYA__SPDIF                 MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
-#define MX23_PAD_ROTARYB__GPMI_CE3N             MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
-
-/* MUXSEL_GPIO */
-#define MX23_PAD_GPMI_D00__GPIO_0_0             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D01__GPIO_0_1             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D02__GPIO_0_2             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D03__GPIO_0_3             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D04__GPIO_0_4             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D05__GPIO_0_5             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D06__GPIO_0_6             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D07__GPIO_0_7             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D08__GPIO_0_8             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D09__GPIO_0_9             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D10__GPIO_0_10            MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D11__GPIO_0_11            MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D12__GPIO_0_12            MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D13__GPIO_0_13            MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D14__GPIO_0_14            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D15__GPIO_0_15            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CLE__GPIO_0_16            MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_ALE__GPIO_0_17            MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE2N__GPIO_0_18           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY0__GPIO_0_19           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY1__GPIO_0_20           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY2__GPIO_0_21           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY3__GPIO_0_22           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WPN__GPIO_0_23            MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WRN__GPIO_0_24            MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDN__GPIO_0_25            MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_CTS__GPIO_0_26          MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RTS__GPIO_0_27          MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RX__GPIO_0_28           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_TX__GPIO_0_29           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SCL__GPIO_0_30             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SDA__GPIO_0_31             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
-
-#define MX23_PAD_LCD_D00__GPIO_1_0              MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D01__GPIO_1_1              MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D02__GPIO_1_2              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D03__GPIO_1_3              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D04__GPIO_1_4              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D05__GPIO_1_5              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D06__GPIO_1_6              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D07__GPIO_1_7              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D08__GPIO_1_8              MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D09__GPIO_1_9              MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D10__GPIO_1_10             MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D11__GPIO_1_11             MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D12__GPIO_1_12             MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D13__GPIO_1_13             MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D14__GPIO_1_14             MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D15__GPIO_1_15             MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D16__GPIO_1_16             MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D17__GPIO_1_17             MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RESET__GPIO_1_18           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RS__GPIO_1_19              MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_WR__GPIO_1_20              MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_CS__GPIO_1_21              MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_DOTCK__GPIO_1_22           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_ENABLE__GPIO_1_23          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_HSYNC__GPIO_1_24           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_VSYNC__GPIO_1_25           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM0__GPIO_1_26                MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM1__GPIO_1_27                MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM2__GPIO_1_28                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM3__GPIO_1_29                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM4__GPIO_1_30                MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-
-#define MX23_PAD_SSP1_CMD__GPIO_2_0             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DETECT__GPIO_2_1          MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA0__GPIO_2_2           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA1__GPIO_2_3           MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA2__GPIO_2_4           MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA3__GPIO_2_5           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_SCK__GPIO_2_6             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYA__GPIO_2_7              MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYB__GPIO_2_8              MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A00__GPIO_2_9              MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A01__GPIO_2_10             MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A02__GPIO_2_11             MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A03__GPIO_2_12             MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A04__GPIO_2_13             MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A05__GPIO_2_14             MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A06__GPIO_2_15             MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A07__GPIO_2_16             MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A08__GPIO_2_17             MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A09__GPIO_2_18             MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A10__GPIO_2_19             MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A11__GPIO_2_20             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A12__GPIO_2_21             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA0__GPIO_2_22             MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA1__GPIO_2_23             MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CASN__GPIO_2_24            MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE0N__GPIO_2_25            MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE1N__GPIO_2_26            MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE1N__GPIO_2_27           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE0N__GPIO_2_28           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CKE__GPIO_2_29             MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_RASN__GPIO_2_30            MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_WEN__GPIO_2_31             MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
-
-#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
deleted file mode 100644
index f50fefd10520..000000000000
--- a/arch/arm/mach-mxs/include/mach/iomux-mx28.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX28_H__
-#define __MACH_IOMUX_MX28_H__
-
-#include <mach/iomux.h>
-
-/*
- * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux.h
- *
- *                                                                      BANK    PIN     MUX
- */
-/* MUXSEL_0 */
-#define MX28_PAD_GPMI_D00__GPMI_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D01__GPMI_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D02__GPMI_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D03__GPMI_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D04__GPMI_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D05__GPMI_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D06__GPMI_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D07__GPMI_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE0N__GPMI_CE0N                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE1N__GPMI_CE1N                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE2N__GPMI_CE2N                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE3N__GPMI_CE3N                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY0__GPMI_READY0                 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY1__GPMI_READY1                 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY2__GPMI_READY2                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY3__GPMI_READY3                 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDN__GPMI_RDN                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_WRN__GPMI_WRN                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_ALE__GPMI_ALE                     MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CLE__GPMI_CLE                     MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RESETN__GPMI_RESETN               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
-
-#define MX28_PAD_LCD_D00__LCD_D0                        MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D01__LCD_D1                        MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D02__LCD_D2                        MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D03__LCD_D3                        MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D04__LCD_D4                        MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D05__LCD_D5                        MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D06__LCD_D6                        MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D07__LCD_D7                        MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D08__LCD_D8                        MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D09__LCD_D9                        MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D10__LCD_D10                       MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D11__LCD_D11                       MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D12__LCD_D12                       MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D13__LCD_D13                       MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D14__LCD_D14                       MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D15__LCD_D15                       MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D16__LCD_D16                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D17__LCD_D17                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D18__LCD_D18                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D19__LCD_D19                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D20__LCD_D20                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D21__LCD_D21                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D22__LCD_D22                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D23__LCD_D23                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RD_E__LCD_RD_E                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN                 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RS__LCD_RS                         MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_CS__LCD_CS                         MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_VSYNC__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_HSYNC__LCD_HSYNC                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_ENABLE__LCD_ENABLE                 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
-
-#define MX28_PAD_SSP0_DATA0__SSP0_D0                    MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA1__SSP0_D1                    MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA2__SSP0_D2                    MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA3__SSP0_D3                    MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA4__SSP0_D4                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA5__SSP0_D5                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA6__SSP0_D6                    MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA7__SSP0_D7                    MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_CMD__SSP0_CMD                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT          MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_SCK__SSP0_SCK                     MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_SCK__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_CMD__SSP1_CMD                     MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_DATA0__SSP1_D0                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_DATA3__SSP1_D3                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SCK__SSP2_SCK                     MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_MOSI__SSP2_CMD                    MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_MISO__SSP2_D0                     MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS0__SSP2_D3                      MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS1__SSP2_D4                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS2__SSP2_D5                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_SCK__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_MOSI__SSP3_CMD                    MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_MISO__SSP3_D0                     MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_SS0__SSP3_D3                      MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
-
-#define MX28_PAD_AUART0_RX__AUART0_RX                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_TX__AUART0_TX                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_CTS__AUART0_CTS                 MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_RTS__AUART0_RTS                 MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_RX__AUART1_RX                   MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_TX__AUART1_TX                   MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_CTS__AUART1_CTS                 MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_RTS__AUART1_RTS                 MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_RX__AUART2_RX                   MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_TX__AUART2_TX                   MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_CTS__AUART2_CTS                 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_RTS__AUART2_RTS                 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_RX__AUART3_RX                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_TX__AUART3_TX                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_CTS__AUART3_CTS                 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_RTS__AUART3_RTS                 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
-#define MX28_PAD_PWM0__PWM_0                            MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
-#define MX28_PAD_PWM1__PWM_1                            MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
-#define MX28_PAD_PWM2__PWM_2                            MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK               MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK             MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0             MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
-#define MX28_PAD_I2C0_SCL__I2C0_SCL                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
-#define MX28_PAD_I2C0_SDA__I2C0_SDA                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
-#define MX28_PAD_SPDIF__SPDIF_TX                        MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
-#define MX28_PAD_PWM3__PWM_3                            MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
-#define MX28_PAD_PWM4__PWM_4                            MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RESET__LCD_RESET                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
-
-#define MX28_PAD_ENET0_MDC__ENET0_MDC                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_MDIO__ENET0_MDIO                 MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN               MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD0__ENET0_RXD0                 MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD1__ENET0_RXD1                 MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK             MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD0__ENET0_TXD0                 MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD1__ENET0_TXD1                 MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD2__ENET0_RXD2                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD3__ENET0_RXD3                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD2__ENET0_TXD2                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD3__ENET0_TXD3                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK             MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_COL__ENET0_COL                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_CRS__ENET0_CRS                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
-#define MX28_PAD_ENET_CLK__CLKCTRL_ENET                 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
-#define MX28_PAD_JTAG_RTCK__JTAG_RTCK                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
-
-#define MX28_PAD_EMI_D00__EMI_DATA0                     MXS_IOMUX_PAD_NAKED(5,  0, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D01__EMI_DATA1                     MXS_IOMUX_PAD_NAKED(5,  1, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D02__EMI_DATA2                     MXS_IOMUX_PAD_NAKED(5,  2, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D03__EMI_DATA3                     MXS_IOMUX_PAD_NAKED(5,  3, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D04__EMI_DATA4                     MXS_IOMUX_PAD_NAKED(5,  4, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D05__EMI_DATA5                     MXS_IOMUX_PAD_NAKED(5,  5, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D06__EMI_DATA6                     MXS_IOMUX_PAD_NAKED(5,  6, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D07__EMI_DATA7                     MXS_IOMUX_PAD_NAKED(5,  7, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D08__EMI_DATA8                     MXS_IOMUX_PAD_NAKED(5,  8, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D09__EMI_DATA9                     MXS_IOMUX_PAD_NAKED(5,  9, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D10__EMI_DATA10                    MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D11__EMI_DATA11                    MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D12__EMI_DATA12                    MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D13__EMI_DATA13                    MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D14__EMI_DATA14                    MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D15__EMI_DATA15                    MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_ODT0__EMI_ODT0                     MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQM0__EMI_DQM0                     MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_ODT1__EMI_ODT1                     MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQM1__EMI_DQM1                     MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CLK__EMI_CLK                       MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQS0__EMI_DQS0                     MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQS1__EMI_DQS1                     MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN             MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
-
-#define MX28_PAD_EMI_A00__EMI_ADDR0                     MXS_IOMUX_PAD_NAKED(6,  0, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A01__EMI_ADDR1                     MXS_IOMUX_PAD_NAKED(6,  1, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A02__EMI_ADDR2                     MXS_IOMUX_PAD_NAKED(6,  2, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A03__EMI_ADDR3                     MXS_IOMUX_PAD_NAKED(6,  3, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A04__EMI_ADDR4                     MXS_IOMUX_PAD_NAKED(6,  4, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A05__EMI_ADDR5                     MXS_IOMUX_PAD_NAKED(6,  5, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A06__EMI_ADDR6                     MXS_IOMUX_PAD_NAKED(6,  6, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A07__EMI_ADDR7                     MXS_IOMUX_PAD_NAKED(6,  7, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A08__EMI_ADDR8                     MXS_IOMUX_PAD_NAKED(6,  8, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A09__EMI_ADDR9                     MXS_IOMUX_PAD_NAKED(6,  9, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A10__EMI_ADDR10                    MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A11__EMI_ADDR11                    MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A12__EMI_ADDR12                    MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A13__EMI_ADDR13                    MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A14__EMI_ADDR14                    MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA0__EMI_BA0                       MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA1__EMI_BA1                       MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA2__EMI_BA2                       MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CASN__EMI_CASN                     MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_RASN__EMI_RASN                     MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_WEN__EMI_WEN                       MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CE0N__EMI_CE0N                     MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CE1N__EMI_CE1N                     MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CKE__EMI_CKE                       MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
-
-/* MUXSEL_1 */
-#define MX28_PAD_GPMI_D00__SSP1_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D01__SSP1_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D02__SSP1_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D03__SSP1_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D04__SSP1_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D05__SSP1_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D06__SSP1_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D07__SSP1_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE0N__SSP3_D0                     MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE1N__SSP3_D3                     MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE2N__CAN1_TX                     MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE3N__CAN1_RX                     MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY1__SSP1_CMD                    MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY2__CAN0_TX                     MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY3__CAN0_RX                     MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDN__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_WRN__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_ALE__SSP3_D1                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CLE__SSP3_D2                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RESETN__SSP3_CMD                  MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
-
-#define MX28_PAD_LCD_D03__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D04__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D08__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D09__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT         MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN          MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT         MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RD_E__LCD_VSYNC                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RS__LCD_DOTCLK                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_CS__LCD_ENABLE                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
-
-#define MX28_PAD_SSP0_DATA4__SSP2_D0                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA5__SSP2_D3                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA6__SSP2_CMD                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA7__SSP2_SCK                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_SCK__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_CMD__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_DATA0__SSP2_D6                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_DATA3__SSP2_D7                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SCK__AUART2_RX                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_MOSI__AUART2_TX                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_MISO__AUART3_RX                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS0__AUART3_TX                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS1__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS2__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_SCK__AUART4_TX                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_MOSI__AUART4_RX                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_MISO__AUART4_RTS                  MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_SS0__AUART4_CTS                   MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
-
-#define MX28_PAD_AUART0_RX__I2C0_SCL                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_TX__I2C0_SDA                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_CTS__AUART4_RX                  MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_RTS__AUART4_TX                  MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT           MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_RTS__USB0_ID                    MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_RX__SSP3_D1                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_TX__SSP3_D2                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_CTS__I2C1_SCL                   MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_RTS__I2C1_SDA                   MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_RX__CAN0_TX                     MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_TX__CAN0_RX                     MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_CTS__CAN1_TX                    MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_RTS__CAN1_RX                    MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
-#define MX28_PAD_PWM0__I2C1_SCL                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
-#define MX28_PAD_PWM1__I2C1_SDA                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
-#define MX28_PAD_PWM2__USB0_ID                          MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_MCLK__PWM_3                      MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_LRCLK__PWM_4                     MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_BITCLK__PWM_5                    MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_SDATA0__PWM_6                    MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
-#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA               MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
-#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB               MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF1_SDATA0__PWM_7                    MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RESET__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
-
-#define MX28_PAD_ENET0_MDC__GPMI_CE4N                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_MDIO__GPMI_CE5N                  MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N                 MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD0__GPMI_CE7N                  MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD1__GPMI_READY4                MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER            MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TX_EN__GPMI_READY5               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD0__GPMI_READY6                MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD1__GPMI_READY7                MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD2__ENET1_RXD0                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD3__ENET1_RXD1                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD2__ENET1_TXD0                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD3__ENET1_TXD1                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER              MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_COL__ENET1_TX_EN                 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_CRS__ENET1_RX_EN                 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
-
-/* MUXSEL_2 */
-#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER                 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK                  MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY0__USB0_ID                     MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER               MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_ALE__SSP3_D4                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_CLE__SSP3_D5                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
-
-#define MX28_PAD_LCD_D00__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D01__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D02__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D03__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D04__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D05__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D06__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D07__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D08__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D09__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D10__ETM_DA10                      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D11__ETM_DA11                      MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D12__ETM_DA12                      MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D13__ETM_DA13                      MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D14__ETM_DA14                      MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D15__ETM_DA15                      MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D16__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D17__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D18__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D19__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D20__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D21__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D22__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D23__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_RD_E__ETM_TCTL                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_WR_RWN__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_HSYNC__ETM_TCTL                    MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_DOTCLK__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
-
-#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT        MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN         MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT      MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN       MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1                 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2                MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2                 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT        MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT       MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN         MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
-
-#define MX28_PAD_AUART0_RX__DUART_CTS                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_TX__DUART_RTS                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_CTS__DUART_RX                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_RTS__DUART_TX                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_RX__PWM_0                       MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_TX__PWM_1                       MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA             MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB             MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_RX__SSP3_D4                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_TX__SSP3_D5                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK                MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT       MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
-#define MX28_PAD_PWM0__DUART_RX                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
-#define MX28_PAD_PWM1__DUART_TX                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
-#define MX28_PAD_PWM2__USB1_OVERCURRENT                 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_MCLK__AUART4_CTS                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS                MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_BITCLK__AUART4_RX                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_SDATA0__AUART4_TX                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
-#define MX28_PAD_I2C0_SCL__DUART_RX                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
-#define MX28_PAD_I2C0_SDA__DUART_TX                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
-#define MX28_PAD_SPDIF__ENET1_RX_ER                     MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
-
-#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1                MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2               MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1              MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2               MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT    MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT      MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN       MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN     MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT       MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN        MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
-
-/* MUXSEL_GPIO */
-#define MX28_PAD_GPMI_D00__GPIO_0_0                     MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D01__GPIO_0_1                     MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D02__GPIO_0_2                     MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D03__GPIO_0_3                     MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D04__GPIO_0_4                     MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D05__GPIO_0_5                     MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D06__GPIO_0_6                     MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D07__GPIO_0_7                     MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE0N__GPIO_0_16                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE1N__GPIO_0_17                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE2N__GPIO_0_18                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE3N__GPIO_0_19                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY0__GPIO_0_20                   MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY1__GPIO_0_21                   MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY2__GPIO_0_22                   MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY3__GPIO_0_23                   MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDN__GPIO_0_24                    MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_WRN__GPIO_0_25                    MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_ALE__GPIO_0_26                    MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CLE__GPIO_0_27                    MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RESETN__GPIO_0_28                 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_LCD_D00__GPIO_1_0                      MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D01__GPIO_1_1                      MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D02__GPIO_1_2                      MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D03__GPIO_1_3                      MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D04__GPIO_1_4                      MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D05__GPIO_1_5                      MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D06__GPIO_1_6                      MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D07__GPIO_1_7                      MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D08__GPIO_1_8                      MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D09__GPIO_1_9                      MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D10__GPIO_1_10                     MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D11__GPIO_1_11                     MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D12__GPIO_1_12                     MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D13__GPIO_1_13                     MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D14__GPIO_1_14                     MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D15__GPIO_1_15                     MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D16__GPIO_1_16                     MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D17__GPIO_1_17                     MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D18__GPIO_1_18                     MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D19__GPIO_1_19                     MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D20__GPIO_1_20                     MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D21__GPIO_1_21                     MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D22__GPIO_1_22                     MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D23__GPIO_1_23                     MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RD_E__GPIO_1_24                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_WR_RWN__GPIO_1_25                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RS__GPIO_1_26                      MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_CS__GPIO_1_27                      MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_VSYNC__GPIO_1_28                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_HSYNC__GPIO_1_29                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_DOTCLK__GPIO_1_30                  MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_ENABLE__GPIO_1_31                  MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_SSP0_DATA0__GPIO_2_0                   MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA1__GPIO_2_1                   MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA2__GPIO_2_2                   MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA3__GPIO_2_3                   MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA4__GPIO_2_4                   MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA5__GPIO_2_5                   MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA6__GPIO_2_6                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA7__GPIO_2_7                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_CMD__GPIO_2_8                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DETECT__GPIO_2_9                  MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_SCK__GPIO_2_10                    MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_SCK__GPIO_2_12                    MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_CMD__GPIO_2_13                    MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_DATA0__GPIO_2_14                  MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_DATA3__GPIO_2_15                  MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SCK__GPIO_2_16                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_MOSI__GPIO_2_17                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_MISO__GPIO_2_18                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS0__GPIO_2_19                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS1__GPIO_2_20                    MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS2__GPIO_2_21                    MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_SCK__GPIO_2_24                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_MOSI__GPIO_2_25                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_MISO__GPIO_2_26                   MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_SS0__GPIO_2_27                    MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_AUART0_RX__GPIO_3_0                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_TX__GPIO_3_1                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_CTS__GPIO_3_2                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_RTS__GPIO_3_3                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_RX__GPIO_3_4                    MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_TX__GPIO_3_5                    MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_CTS__GPIO_3_6                   MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_RTS__GPIO_3_7                   MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_RX__GPIO_3_8                    MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_TX__GPIO_3_9                    MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_CTS__GPIO_3_10                  MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_RTS__GPIO_3_11                  MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_RX__GPIO_3_12                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_TX__GPIO_3_13                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_CTS__GPIO_3_14                  MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_RTS__GPIO_3_15                  MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM0__GPIO_3_16                        MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM1__GPIO_3_17                        MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM2__GPIO_3_18                        MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_MCLK__GPIO_3_20                  MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21                 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_I2C0_SCL__GPIO_3_24                    MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_I2C0_SDA__GPIO_3_25                    MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26                MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SPDIF__GPIO_3_27                       MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM3__GPIO_3_28                        MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM4__GPIO_3_29                        MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RESET__GPIO_3_30                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_ENET0_MDC__GPIO_4_0                    MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_MDIO__GPIO_4_1                   MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RX_EN__GPIO_4_2                  MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD0__GPIO_4_3                   MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD1__GPIO_4_4                   MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5                 MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TX_EN__GPIO_4_6                  MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD0__GPIO_4_7                   MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD1__GPIO_4_8                   MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD2__GPIO_4_9                   MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD3__GPIO_4_10                  MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD2__GPIO_4_11                  MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD3__GPIO_4_12                  MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13                MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_COL__GPIO_4_14                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_CRS__GPIO_4_15                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET_CLK__GPIO_4_16                    MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_JTAG_RTCK__GPIO_4_20                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
-
-#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
deleted file mode 100644
index 7abdf58b8bb7..000000000000
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                      <armlinux@phytec.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_MXS_IOMUX_H__
-#define __MACH_MXS_IOMUX_H__
-
-/*
- * IOMUX/PAD Bit field definitions
- *
- * PAD_BANK:             0..2   (3)
- * PAD_PIN:              3..7   (5)
- * PAD_MUXSEL:           8..9   (2)
- * PAD_MA:              10..11  (2)
- * PAD_MA_VALID:        12      (1)
- * PAD_VOL:             13      (1)
- * PAD_VOL_VALID:       14      (1)
- * PAD_PULL:            15      (1)
- * PAD_PULL_VALID:      16      (1)
- * RESERVED:            17..31  (15)
- */
-typedef u32 iomux_cfg_t;
-
-#define MXS_PAD_BANK_SHIFT      0
-#define MXS_PAD_BANK_MASK       ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
-#define MXS_PAD_PIN_SHIFT       3
-#define MXS_PAD_PIN_MASK        ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
-#define MXS_PAD_MUXSEL_SHIFT    8
-#define MXS_PAD_MUXSEL_MASK     ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
-#define MXS_PAD_MA_SHIFT        10
-#define MXS_PAD_MA_MASK         ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
-#define MXS_PAD_MA_VALID_SHIFT  12
-#define MXS_PAD_MA_VALID_MASK   ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
-#define MXS_PAD_VOL_SHIFT       13
-#define MXS_PAD_VOL_MASK        ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
-#define MXS_PAD_VOL_VALID_SHIFT 14
-#define MXS_PAD_VOL_VALID_MASK  ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
-#define MXS_PAD_PULL_SHIFT      15
-#define MXS_PAD_PULL_MASK       ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
-#define MXS_PAD_PULL_VALID_SHIFT 16
-#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
-
-#define PAD_MUXSEL_0            0
-#define PAD_MUXSEL_1            1
-#define PAD_MUXSEL_2            2
-#define PAD_MUXSEL_GPIO         3
-
-#define PAD_4MA                 0
-#define PAD_8MA                 1
-#define PAD_12MA                2
-#define PAD_16MA                3
-
-#define PAD_1V8                 0
-#define PAD_3V3                 1
-
-#define PAD_NOPULL              0
-#define PAD_PULLUP              1
-
-#define MXS_PAD_4MA     ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_8MA     ((PAD_8MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_12MA    ((PAD_12MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_16MA    ((PAD_16MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-
-#define MXS_PAD_1V8     ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
-                                        MXS_PAD_VOL_VALID_MASK)
-#define MXS_PAD_3V3     ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
-                                        MXS_PAD_VOL_VALID_MASK)
-
-#define MXS_PAD_NOPULL  ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
-                                        MXS_PAD_PULL_VALID_MASK)
-#define MXS_PAD_PULLUP  ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
-                                        MXS_PAD_PULL_VALID_MASK)
-
-/* generic pad control used in most cases */
-#define MXS_PAD_CTRL    (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
-
-#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)           \
-                (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |         \
-                ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |            \
-                ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) |      \
-                ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) |              \
-                ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) |            \
-                ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
-
-/*
- * A pad becomes naked, when none of mA, vol or pull
- * validity bits is set.
- */
-#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
-                MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
-
-static inline unsigned int PAD_BANK(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
-}
-
-static inline unsigned int PAD_PIN(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
-}
-
-static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
-}
-
-static inline unsigned int PAD_MA(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
-}
-
-static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
-}
-
-static inline unsigned int PAD_VOL(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
-}
-
-static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
-}
-
-static inline unsigned int PAD_PULL(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
-}
-
-static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
-}
-
-/*
- * configures a single pad in the iomuxer
- */
-int mxs_iomux_setup_pad(iomux_cfg_t pad);
-
-/*
- * configures multiple pads
- * convenient way to call the above function with tables
- */
-int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
-
-#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c
deleted file mode 100644
index 0e804e2f11f4..000000000000
--- a/arch/arm/mach-mxs/iomux.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                       <armlinux@phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/mxs.h>
-#include <mach/iomux.h>
-
-/*
- * configures a single pad in the iomuxer
- */
-int mxs_iomux_setup_pad(iomux_cfg_t pad)
-{
-        u32 reg, ofs, bp, bm;
-        void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR);
-
-        /* muxsel */
-        ofs = 0x100;
-        ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
-        bp = PAD_PIN(pad) % 16 * 2;
-        bm = 0x3 << bp;
-        reg = __raw_readl(iomux_base + ofs);
-        reg &= ~bm;
-        reg |= PAD_MUXSEL(pad) << bp;
-        __raw_writel(reg, iomux_base + ofs);
-
-        /* drive */
-        ofs = cpu_is_mx23() ? 0x200 : 0x300;
-        ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
-        /* mA */
-        if (PAD_MA_VALID(pad)) {
-                bp = PAD_PIN(pad) % 8 * 4;
-                bm = 0x3 << bp;
-                reg = __raw_readl(iomux_base + ofs);
-                reg &= ~bm;
-                reg |= PAD_MA(pad) << bp;
-                __raw_writel(reg, iomux_base + ofs);
-        }
-        /* vol */
-        if (PAD_VOL_VALID(pad)) {
-                bp = PAD_PIN(pad) % 8 * 4 + 2;
-                if (PAD_VOL(pad))
-                        __mxs_setl(1 << bp, iomux_base + ofs);
-                else
-                        __mxs_clrl(1 << bp, iomux_base + ofs);
-        }
-
-        /* pull */
-        if (PAD_PULL_VALID(pad)) {
-                ofs = cpu_is_mx23() ? 0x400 : 0x600;
-                ofs += PAD_BANK(pad) * 0x10;
-                bp = PAD_PIN(pad);
-                if (PAD_PULL(pad))
-                        __mxs_setl(1 << bp, iomux_base + ofs);
-                else
-                        __mxs_clrl(1 << bp, iomux_base + ofs);
-        }
-
-        return 0;
-}
-
-int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
-{
-        const iomux_cfg_t *p = pad_list;
-        int i;
-        int ret;
-
-        for (i = 0; i < count; i++) {
-                ret = mxs_iomux_setup_pad(*p);
-                if (ret)
-                        return ret;
-                p++;
-        }
-
-        return 0;
-}
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
deleted file mode 100644
index f5f061757deb..000000000000
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Copyright (C) 2011-2012
- * Lauri Hintsala, Bluegiga, <lauri.hintsala@bluegiga.com>
- * Veli-Pekka Peltola, Bluegiga, <veli-pekka.peltola@bluegiga.com>
- *
- * based on: mach-mx28evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/micrel_phy.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/digctl.h>
-#include <mach/iomux-mx28.h>
-
-#include "devices-mx28.h"
-
-#define APX4DEVKIT_GPIO_USERLED MXS_GPIO_NR(3, 28)
-
-static const iomux_cfg_t apx4devkit_pads[] __initconst = {
-        /* duart */
-        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-
-        /* auart0 */
-        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
-
-        /* auart1 */
-        MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
-
-        /* auart2 */
-        MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL,
-        MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL,
-
-        /* auart3 */
-        MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL,
-        MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL,
-
-#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-
-        /* i2c */
-        MX28_PAD_I2C0_SCL__I2C0_SCL,
-        MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-        /* mmc0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA4__SSP0_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA5__SSP0_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA6__SSP0_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA7__SSP0_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* led */
-        MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
-
-        /* saif0 & saif1 */
-        MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-};
-
-/* led */
-static const struct gpio_led apx4devkit_leds[] __initconst = {
-        {
-                .name = "user-led",
-                .default_trigger = "heartbeat",
-                .gpio = APX4DEVKIT_GPIO_USERLED,
-        },
-};
-
-static const struct gpio_led_platform_data apx4devkit_led_data __initconst = {
-        .leds = apx4devkit_leds,
-        .num_leds = ARRAY_SIZE(apx4devkit_leds),
-};
-
-static const struct fec_platform_data mx28_fec_pdata __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = {
-        .wp_gpio = -EINVAL,
-        .flags = SLOTF_4_BIT_CAPABLE,
-};
-
-static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = {
-        { I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */
-        { I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */
-};
-
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \
-                defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("VDDA", "0-000a"),
-        REGULATOR_SUPPLY("VDDIO", "0-000a"),
-};
-
-static struct regulator_init_data apx4devkit_vdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .always_on = 1,
-        },
-        .consumer_supplies = apx4devkit_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies),
-};
-
-static struct fixed_voltage_config apx4devkit_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 1,
-        .init_data      = &apx4devkit_vdd_reg_init_data,
-};
-
-static struct platform_device apx4devkit_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &apx4devkit_vdd_pdata,
-        },
-};
-
-static void __init apx4devkit_add_regulators(void)
-{
-        platform_device_register(&apx4devkit_voltage_regulator);
-}
-#else
-static void __init apx4devkit_add_regulators(void) {}
-#endif
-
-static const struct mxs_saif_platform_data
-                        apx4devkit_mxs_saif_pdata[] __initconst = {
-        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
-        {
-                .master_mode = 1,
-                .master_id = 0,
-        }, {
-                .master_mode = 0,
-                .master_id = 0,
-        },
-};
-
-static int apx4devkit_phy_fixup(struct phy_device *phy)
-{
-        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
-        return 0;
-}
-
-static void __init apx4devkit_fec_phy_clk_enable(void)
-{
-        struct clk *clk;
-
-        /* Enable fec phy clock */
-        clk = clk_get_sys("enet_out", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-}
-
-static void __init apx4devkit_init(void)
-{
-        mx28_soc_init();
-
-        mxs_iomux_setup_multiple_pads(apx4devkit_pads,
-                        ARRAY_SIZE(apx4devkit_pads));
-
-        mx28_add_duart();
-        mx28_add_auart0();
-        mx28_add_auart1();
-        mx28_add_auart2();
-        mx28_add_auart3();
-
-        /*
-         * Register fixup for the Micrel KS8031 PHY clock
-         * (shares same ID with KS8051)
-         */
-        phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
-                        apx4devkit_phy_fixup);
-
-        apx4devkit_fec_phy_clk_enable();
-        mx28_add_fec(0, &mx28_fec_pdata);
-
-        mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata);
-
-        gpio_led_register_device(0, &apx4devkit_led_data);
-
-        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
-        mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]);
-        mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]);
-
-        apx4devkit_add_regulators();
-
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, apx4devkit_i2c_boardinfo,
-                        ARRAY_SIZE(apx4devkit_i2c_boardinfo));
-
-        mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0);
-}
-
-static void __init apx4devkit_timer_init(void)
-{
-        mx28_clocks_init();
-}
-
-static struct sys_timer apx4devkit_timer = {
-        .init   = apx4devkit_timer_init,
-};
-
-MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit")
-        .map_io         = mx28_map_io,
-        .init_irq       = mx28_init_irq,
-        .timer          = &apx4devkit_timer,
-        .init_machine   = apx4devkit_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
deleted file mode 100644
index 4c00c879b893..000000000000
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
- *
- * based on: mach-mx28_evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-
-#include "devices-mx28.h"
-
-#define M28EVK_GPIO_USERLED1    MXS_GPIO_NR(3, 16)
-#define M28EVK_GPIO_USERLED2    MXS_GPIO_NR(3, 17)
-
-#define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
-#define M28EVK_LCD_ENABLE       MXS_GPIO_NR(3, 28)
-
-#define MX28EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(2, 12)
-#define MX28EVK_MMC1_WRITE_PROTECT      MXS_GPIO_NR(0, 28)
-
-static const iomux_cfg_t m28evk_pads[] __initconst = {
-        /* duart */
-        MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL,
-
-        /* auart0 */
-        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-
-        /* auart3 */
-        MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
-
-#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-        /* fec1 */
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
-
-        /* flexcan0 */
-        MX28_PAD_GPMI_RDY2__CAN0_TX,
-        MX28_PAD_GPMI_RDY3__CAN0_RX,
-
-        /* flexcan1 */
-        MX28_PAD_GPMI_CE2N__CAN1_TX,
-        MX28_PAD_GPMI_CE3N__CAN1_RX,
-
-        /* I2C */
-        MX28_PAD_I2C0_SCL__I2C0_SCL,
-        MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-        /* mxsfb (lcdif) */
-        MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
-
-        MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
-        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
-
-        /* mmc0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA4__SSP0_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA5__SSP0_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA6__SSP0_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA7__SSP0_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* mmc1 */
-        MX28_PAD_GPMI_D00__SSP1_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D01__SSP1_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D02__SSP1_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D03__SSP1_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D04__SSP1_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D05__SSP1_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D06__SSP1_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D07__SSP1_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY1__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_WRN__SSP1_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX28_PAD_GPMI_RESETN__GPIO_0_28 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX28_PAD_PWM4__GPIO_3_29 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* led */
-        MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL,
-
-        /* nand */
-        MX28_PAD_GPMI_D00__GPMI_D0 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D01__GPMI_D1 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D02__GPMI_D2 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D03__GPMI_D3 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D04__GPMI_D4 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D05__GPMI_D5 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D06__GPMI_D6 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D07__GPMI_D7 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_CE0N__GPMI_CE0N |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_RDY0__GPMI_READY0 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_RDN__GPMI_RDN |
-                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_WRN__GPMI_WRN |
-                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_ALE__GPMI_ALE |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_CLE__GPMI_CLE |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RESETN__GPMI_RESETN |
-                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-
-        /* Backlight */
-        MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
-};
-
-/* led */
-static const struct gpio_led m28evk_leds[] __initconst = {
-        {
-                .name = "user-led1",
-                .default_trigger = "heartbeat",
-                .gpio = M28EVK_GPIO_USERLED1,
-        },
-        {
-                .name = "user-led2",
-                .default_trigger = "heartbeat",
-                .gpio = M28EVK_GPIO_USERLED2,
-        },
-};
-
-static const struct gpio_led_platform_data m28evk_led_data __initconst = {
-        .leds = m28evk_leds,
-        .num_leds = ARRAY_SIZE(m28evk_leds),
-};
-
-static struct fec_platform_data mx28_fec_pdata[] __initdata = {
-        {
-                /* fec0 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        }, {
-                /* fec1 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        },
-};
-
-static int __init m28evk_fec_get_mac(void)
-{
-        int i;
-        u32 val;
-        const u32 *ocotp = mxs_get_ocotp();
-
-        if (!ocotp)
-                return -ETIMEDOUT;
-
-        /*
-         * OCOTP only stores the last 4 octets for each mac address,
-         * so hard-code DENX OUI (C0:E5:4E) here.
-         */
-        for (i = 0; i < 2; i++) {
-                val = ocotp[i];
-                mx28_fec_pdata[i].mac[0] = 0xC0;
-                mx28_fec_pdata[i].mac[1] = 0xE5;
-                mx28_fec_pdata[i].mac[2] = 0x4E;
-                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
-                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
-                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
-        }
-
-        return 0;
-}
-
-/* mxsfb (lcdif) */
-static struct fb_videomode m28evk_video_modes[] = {
-        {
-                .name           = "Ampire AM-800480R2TMQW-T01H",
-                .refresh        = 60,
-                .xres           = 800,
-                .yres           = 480,
-                .pixclock       = 30066, /* picosecond (33.26 MHz) */
-                .left_margin    = 0,
-                .right_margin   = 256,
-                .upper_margin   = 0,
-                .lower_margin   = 45,
-                .hsync_len      = 1,
-                .vsync_len      = 1,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT,
-        },
-};
-
-static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = {
-        .mode_list      = m28evk_video_modes,
-        .mode_count     = ARRAY_SIZE(m28evk_video_modes),
-        .default_bpp    = 16,
-        .ld_intf_width  = STMLCDIF_18BIT,
-};
-
-static struct at24_platform_data m28evk_eeprom = {
-        .byte_len = 16384,
-        .page_size = 32,
-        .flags = AT24_FLAG_ADDR16,
-};
-
-static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = {
-        {
-                I2C_BOARD_INFO("at24", 0x51),   /* E0=1, E1=0, E2=0 */
-                .platform_data = &m28evk_eeprom,
-        },
-};
-
-static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
-        {
-                /* mmc0 */
-                .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        }, {
-                /* mmc1 */
-                .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        },
-};
-
-static void __init m28evk_init(void)
-{
-        mx28_soc_init();
-
-        mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
-
-        mx28_add_duart();
-        mx28_add_auart0();
-        mx28_add_auart3();
-
-        if (!m28evk_fec_get_mac()) {
-                mx28_add_fec(0, &mx28_fec_pdata[0]);
-                mx28_add_fec(1, &mx28_fec_pdata[1]);
-        }
-
-        mx28_add_flexcan(0, NULL);
-        mx28_add_flexcan(1, NULL);
-
-        mx28_add_mxsfb(&m28evk_mxsfb_pdata);
-
-        mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]);
-        mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]);
-
-        gpio_led_register_device(0, &m28evk_led_data);
-
-        /* I2C */
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo,
-                        ARRAY_SIZE(m28_stk5v3_i2c_boardinfo));
-}
-
-static void __init m28evk_timer_init(void)
-{
-        mx28_clocks_init();
-}
-
-static struct sys_timer m28evk_timer = {
-        .init   = m28evk_timer_init,
-};
-
-MACHINE_START(M28EVK, "DENX M28 EVK")
-        .map_io         = mx28_map_io,
-        .init_irq       = mx28_init_irq,
-        .timer          = &m28evk_timer,
-        .init_machine   = m28evk_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
deleted file mode 100644
index e7272a41939d..000000000000
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx23.h>
-
-#include "devices-mx23.h"
-
-#define MX23EVK_LCD_ENABLE      MXS_GPIO_NR(1, 18)
-#define MX23EVK_BL_ENABLE       MXS_GPIO_NR(1, 28)
-#define MX23EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(1, 30)
-#define MX23EVK_MMC0_SLOT_POWER         MXS_GPIO_NR(1, 29)
-
-static const iomux_cfg_t mx23evk_pads[] __initconst = {
-        /* duart */
-        MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-
-        /* auart */
-        MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
-        MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
-        MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL,
-        MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL,
-
-        /* mxsfb (lcdif) */
-        MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
-        MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
-        MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL,
-        MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
-        /* LCD panel enable */
-        MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
-        /* backlight control */
-        MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
-
-        /* mmc */
-        MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D08__SSP1_DATA4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D09__SSP1_DATA5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D10__SSP1_DATA6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D11__SSP1_DATA7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_CMD__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DETECT__SSP1_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX23_PAD_SSP1_SCK__SSP1_SCK |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX23_PAD_PWM4__GPIO_1_30 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX23_PAD_PWM3__GPIO_1_29 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-};
-
-/* mxsfb (lcdif) */
-static struct fb_videomode mx23evk_video_modes[] = {
-        {
-                .name           = "Samsung-LMS430HF02",
-                .refresh        = 60,
-                .xres           = 480,
-                .yres           = 272,
-                .pixclock       = 108096, /* picosecond (9.2 MHz) */
-                .left_margin    = 15,
-                .right_margin   = 8,
-                .upper_margin   = 12,
-                .lower_margin   = 4,
-                .hsync_len      = 1,
-                .vsync_len      = 1,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                  FB_SYNC_DOTCLK_FAILING_ACT,
-        },
-};
-
-static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
-        .mode_list      = mx23evk_video_modes,
-        .mode_count     = ARRAY_SIZE(mx23evk_video_modes),
-        .default_bpp    = 32,
-        .ld_intf_width  = STMLCDIF_24BIT,
-};
-
-static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = {
-        .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT,
-        .flags = SLOTF_8_BIT_CAPABLE,
-};
-
-static void __init mx23evk_init(void)
-{
-        int ret;
-
-        mx23_soc_init();
-
-        mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
-
-        mx23_add_duart();
-        mx23_add_auart0();
-
-        /* power on mmc slot by writing 0 to the gpio */
-        ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
-                               "mmc0-slot-power");
-        if (ret)
-                pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
-        mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata);
-
-        ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
-        if (ret)
-                pr_warn("failed to request gpio lcd-enable: %d\n", ret);
-        else
-                gpio_set_value(MX23EVK_LCD_ENABLE, 1);
-
-        ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
-        if (ret)
-                pr_warn("failed to request gpio bl-enable: %d\n", ret);
-        else
-                gpio_set_value(MX23EVK_BL_ENABLE, 1);
-
-        mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
-        mx23_add_rtc_stmp3xxx();
-}
-
-static void __init mx23evk_timer_init(void)
-{
-        mx23_clocks_init();
-}
-
-static struct sys_timer mx23evk_timer = {
-        .init   = mx23evk_timer_init,
-};
-
-MACHINE_START(MX23EVK, "Freescale MX23 EVK")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .map_io         = mx23_map_io,
-        .init_irq       = mx23_init_irq,
-        .timer          = &mx23evk_timer,
-        .init_machine   = mx23evk_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
deleted file mode 100644
index dafd48e86c8c..000000000000
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-#include <mach/digctl.h>
-
-#include "devices-mx28.h"
-
-#define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
-#define MX28EVK_FEC_PHY_POWER   MXS_GPIO_NR(2, 15)
-#define MX28EVK_GPIO_LED        MXS_GPIO_NR(3, 5)
-#define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
-#define MX28EVK_LCD_ENABLE      MXS_GPIO_NR(3, 30)
-#define MX28EVK_FEC_PHY_RESET   MXS_GPIO_NR(4, 13)
-
-#define MX28EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(2, 12)
-#define MX28EVK_MMC1_WRITE_PROTECT      MXS_GPIO_NR(0, 28)
-#define MX28EVK_MMC0_SLOT_POWER         MXS_GPIO_NR(3, 28)
-#define MX28EVK_MMC1_SLOT_POWER         MXS_GPIO_NR(3, 29)
-
-static const iomux_cfg_t mx28evk_pads[] __initconst = {
-        /* duart */
-        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-
-        /* auart0 */
-        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
-        /* auart3 */
-        MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
-
-#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-        /* fec1 */
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
-        /* phy power line */
-        MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
-        /* phy reset line */
-        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
-
-        /* flexcan0 */
-        MX28_PAD_GPMI_RDY2__CAN0_TX,
-        MX28_PAD_GPMI_RDY3__CAN0_RX,
-        /* flexcan1 */
-        MX28_PAD_GPMI_CE2N__CAN1_TX,
-        MX28_PAD_GPMI_CE3N__CAN1_RX,
-        /* transceiver power control */
-        MX28_PAD_SSP1_CMD__GPIO_2_13,
-
-        /* mxsfb (lcdif) */
-        MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
-        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
-        MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
-        MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL,
-        /* LCD panel enable */
-        MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
-        /* backlight control */
-        MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
-        /* mmc0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA4__SSP0_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA5__SSP0_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA6__SSP0_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA7__SSP0_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX28_PAD_SSP1_SCK__GPIO_2_12 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX28_PAD_PWM3__GPIO_3_28 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* mmc1 */
-        MX28_PAD_GPMI_D00__SSP1_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D01__SSP1_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D02__SSP1_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D03__SSP1_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D04__SSP1_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D05__SSP1_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D06__SSP1_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D07__SSP1_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY1__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_WRN__SSP1_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX28_PAD_GPMI_RESETN__GPIO_0_28 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX28_PAD_PWM4__GPIO_3_29 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* led */
-        MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL,
-
-        /* I2C */
-        MX28_PAD_I2C0_SCL__I2C0_SCL |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_I2C0_SDA__I2C0_SDA |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-
-        /* saif0 & saif1 */
-        MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-};
-
-/* led */
-static const struct gpio_led mx28evk_leds[] __initconst = {
-        {
-                .name = "GPIO-LED",
-                .default_trigger = "heartbeat",
-                .gpio = MX28EVK_GPIO_LED,
-        },
-};
-
-static const struct gpio_led_platform_data mx28evk_led_data __initconst = {
-        .leds = mx28evk_leds,
-        .num_leds = ARRAY_SIZE(mx28evk_leds),
-};
-
-/* fec */
-static void __init mx28evk_fec_reset(void)
-{
-        struct clk *clk;
-
-        /* Enable fec phy clock */
-        clk = clk_get_sys("enet_out", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-
-        gpio_set_value(MX28EVK_FEC_PHY_RESET, 0);
-        mdelay(1);
-        gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
-}
-
-static struct fec_platform_data mx28_fec_pdata[] __initdata = {
-        {
-                /* fec0 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        }, {
-                /* fec1 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        },
-};
-
-static int __init mx28evk_fec_get_mac(void)
-{
-        int i;
-        u32 val;
-        const u32 *ocotp = mxs_get_ocotp();
-
-        if (!ocotp)
-                return -ETIMEDOUT;
-
-        /*
-         * OCOTP only stores the last 4 octets for each mac address,
-         * so hard-code Freescale OUI (00:04:9f) here.
-         */
-        for (i = 0; i < 2; i++) {
-                val = ocotp[i];
-                mx28_fec_pdata[i].mac[0] = 0x00;
-                mx28_fec_pdata[i].mac[1] = 0x04;
-                mx28_fec_pdata[i].mac[2] = 0x9f;
-                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
-                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
-                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
-        }
-
-        return 0;
-}
-
-/*
- * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
- */
-static int flexcan0_en, flexcan1_en;
-
-static void mx28evk_flexcan_switch(void)
-{
-        if (flexcan0_en || flexcan1_en)
-                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
-        else
-                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
-}
-
-static void mx28evk_flexcan0_switch(int enable)
-{
-        flexcan0_en = enable;
-        mx28evk_flexcan_switch();
-}
-
-static void mx28evk_flexcan1_switch(int enable)
-{
-        flexcan1_en = enable;
-        mx28evk_flexcan_switch();
-}
-
-static const struct flexcan_platform_data
-                mx28evk_flexcan_pdata[] __initconst = {
-        {
-                .transceiver_switch = mx28evk_flexcan0_switch,
-        }, {
-                .transceiver_switch = mx28evk_flexcan1_switch,
-        }
-};
-
-/* mxsfb (lcdif) */
-static struct fb_videomode mx28evk_video_modes[] = {
-        {
-                .name           = "Seiko-43WVF1G",
-                .refresh        = 60,
-                .xres           = 800,
-                .yres           = 480,
-                .pixclock       = 29851, /* picosecond (33.5 MHz) */
-                .left_margin    = 89,
-                .right_margin   = 164,
-                .upper_margin   = 23,
-                .lower_margin   = 10,
-                .hsync_len      = 10,
-                .vsync_len      = 10,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                  FB_SYNC_DOTCLK_FAILING_ACT,
-        },
-};
-
-static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
-        .mode_list      = mx28evk_video_modes,
-        .mode_count     = ARRAY_SIZE(mx28evk_video_modes),
-        .default_bpp    = 32,
-        .ld_intf_width  = STMLCDIF_24BIT,
-};
-
-static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = {
-        {
-                /* mmc0 */
-                .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        }, {
-                /* mmc1 */
-                .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        },
-};
-
-static struct i2c_board_info mxs_i2c0_board_info[] __initdata = {
-        {
-                I2C_BOARD_INFO("sgtl5000", 0x0a),
-        },
-};
-
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("VDDA", "0-000a"),
-        REGULATOR_SUPPLY("VDDIO", "0-000a"),
-};
-
-static struct regulator_init_data mx28evk_vdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .always_on = 1,
-        },
-        .consumer_supplies = mx28evk_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies),
-};
-
-static struct fixed_voltage_config mx28evk_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 1,
-        .init_data      = &mx28evk_vdd_reg_init_data,
-};
-static struct platform_device mx28evk_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &mx28evk_vdd_pdata,
-        },
-};
-static void __init mx28evk_add_regulators(void)
-{
-        platform_device_register(&mx28evk_voltage_regulator);
-}
-#else
-static void __init mx28evk_add_regulators(void) {}
-#endif
-
-static const struct gpio mx28evk_gpios[] __initconst = {
-        { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
-        { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
-        { MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" },
-        { MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" },
-        { MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" },
-        { MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
-        { MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" },
-};
-
-static const struct mxs_saif_platform_data
-                        mx28evk_mxs_saif_pdata[] __initconst = {
-        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
-        {
-                .master_mode = 1,
-                .master_id = 0,
-        }, {
-                .master_mode = 0,
-                .master_id = 0,
-        },
-};
-
-static void __init mx28evk_init(void)
-{
-        int ret;
-
-        mx28_soc_init();
-
-        mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
-
-        mx28_add_duart();
-        mx28_add_auart0();
-        mx28_add_auart3();
-
-        if (mx28evk_fec_get_mac())
-                pr_warn("%s: failed on fec mac setup\n", __func__);
-
-        ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios));
-        if (ret)
-                pr_err("One or more GPIOs failed to be requested: %d\n", ret);
-
-        mx28evk_fec_reset();
-        mx28_add_fec(0, &mx28_fec_pdata[0]);
-        mx28_add_fec(1, &mx28_fec_pdata[1]);
-
-        mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
-        mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
-
-        mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
-
-        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
-        mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]);
-        mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]);
-
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, mxs_i2c0_board_info,
-                                ARRAY_SIZE(mxs_i2c0_board_info));
-
-        mx28evk_add_regulators();
-
-        mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0,
-                        NULL, 0);
-
-        mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
-        mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
-
-        mx28_add_rtc_stmp3xxx();
-
-        gpio_led_register_device(0, &mx28evk_led_data);
-}
-
-static void __init mx28evk_timer_init(void)
-{
-        mx28_clocks_init();
-}
-
-static struct sys_timer mx28evk_timer = {
-        .init   = mx28evk_timer_init,
-};
-
-MACHINE_START(MX28EVK, "Freescale MX28 EVK")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .map_io         = mx28_map_io,
-        .init_irq       = mx28_init_irq,
-        .timer          = &mx28evk_timer,
-        .init_machine   = mx28evk_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 8dabfe81d07c..433af893ad8a 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -12,8 +12,10 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/can/platform/flexcan.h>
+#include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/irqdomain.h>
 #include <linux/micrel_phy.h>
@@ -21,9 +23,12 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
+#include <linux/pinctrl/consumer.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
+#include <mach/digctl.h>
+#include <mach/mxs.h>
 
 static struct fb_videomode mx23evk_video_modes[] = {
         {
@@ -99,9 +104,40 @@ static struct fb_videomode apx4devkit_video_modes[] = {
 
 static struct mxsfb_platform_data mxsfb_pdata __initdata;
 
+/*
+ * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
+ */
+#define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
+
+static int flexcan0_en, flexcan1_en;
+
+static void mx28evk_flexcan_switch(void)
+{
+        if (flexcan0_en || flexcan1_en)
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
+        else
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
+}
+
+static void mx28evk_flexcan0_switch(int enable)
+{
+        flexcan0_en = enable;
+        mx28evk_flexcan_switch();
+}
+
+static void mx28evk_flexcan1_switch(int enable)
+{
+        flexcan1_en = enable;
+        mx28evk_flexcan_switch();
+}
+
+static struct flexcan_platform_data flexcan_pdata[2];
+
 static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
         OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+        OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
+        OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
         { /* sentinel */ }
 };
 
@@ -237,13 +273,21 @@ static void __init imx28_evk_init(void)
         mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
         mxsfb_pdata.default_bpp = 32;
         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+
+        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
 }
 
-static void __init m28evk_init(void)
+static void __init imx28_evk_post_init(void)
 {
-        enable_clk_enet_out();
-        update_fec_mac_prop(OUI_DENX);
+        if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
+                              "flexcan-switch")) {
+                flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
+                flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
+        }
+}
 
+static void __init m28evk_init(void)
+{
         mxsfb_pdata.mode_list = m28evk_video_modes;
         mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
         mxsfb_pdata.default_bpp = 16;
@@ -270,6 +314,80 @@ static void __init apx4devkit_init(void)
         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
 }
 
+#define ENET0_MDC__GPIO_4_0     MXS_GPIO_NR(4, 0)
+#define ENET0_MDIO__GPIO_4_1    MXS_GPIO_NR(4, 1)
+#define ENET0_RX_EN__GPIO_4_2   MXS_GPIO_NR(4, 2)
+#define ENET0_RXD0__GPIO_4_3    MXS_GPIO_NR(4, 3)
+#define ENET0_RXD1__GPIO_4_4    MXS_GPIO_NR(4, 4)
+#define ENET0_TX_EN__GPIO_4_6   MXS_GPIO_NR(4, 6)
+#define ENET0_TXD0__GPIO_4_7    MXS_GPIO_NR(4, 7)
+#define ENET0_TXD1__GPIO_4_8    MXS_GPIO_NR(4, 8)
+#define ENET_CLK__GPIO_4_16     MXS_GPIO_NR(4, 16)
+
+#define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
+#define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
+#define TX28_FEC_nINT           MXS_GPIO_NR(4, 5)
+
+static const struct gpio tx28_gpios[] __initconst = {
+        { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
+        { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
+        { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
+        { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
+        { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
+        { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
+        { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
+        { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
+        { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
+        { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
+        { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
+        { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
+};
+
+static void __init tx28_post_init(void)
+{
+        struct device_node *np;
+        struct platform_device *pdev;
+        struct pinctrl *pctl;
+        int ret;
+
+        enable_clk_enet_out();
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
+        pdev = of_find_device_by_node(np);
+        if (!pdev) {
+                pr_err("%s: failed to find fec device\n", __func__);
+                return;
+        }
+
+        pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
+        if (IS_ERR(pctl)) {
+                pr_err("%s: failed to get pinctrl state\n", __func__);
+                return;
+        }
+
+        ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
+        if (ret) {
+                pr_err("%s: failed to request gpios: %d\n", __func__, ret);
+                return;
+        }
+
+        /* Power up fec phy */
+        gpio_set_value(TX28_FEC_PHY_POWER, 1);
+        msleep(26); /* 25ms according to data sheet */
+
+        /* Mode strap pins */
+        gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
+        gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
+        gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
+
+        udelay(100); /* minimum assertion time for nRST */
+
+        /* Deasserting FEC PHY RESET */
+        gpio_set_value(TX28_FEC_PHY_RESET, 1);
+
+        pinctrl_put(pctl);
+}
+
 static void __init mxs_machine_init(void)
 {
         if (of_machine_is_compatible("fsl,imx28-evk"))
@@ -283,22 +401,20 @@ static void __init mxs_machine_init(void)
 
         of_platform_populate(NULL, of_default_bus_match_table,
                              mxs_auxdata_lookup, NULL);
+
+        if (of_machine_is_compatible("karo,tx28"))
+                tx28_post_init();
+
+        if (of_machine_is_compatible("fsl,imx28-evk"))
+                imx28_evk_post_init();
 }
 
 static const char *imx23_dt_compat[] __initdata = {
-        "fsl,imx23-evk",
-        "fsl,stmp378x_devb"
-        "olimex,imx23-olinuxino",
         "fsl,imx23",
         NULL,
 };
 
 static const char *imx28_dt_compat[] __initdata = {
-        "bluegiga,apx4devkit",
-        "crystalfontz,cfa10036",
-        "denx,m28evk",
-        "fsl,imx28-evk",
-        "karo,tx28",
         "fsl,imx28",
         NULL,
 };
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
deleted file mode 100644
index 6548965e4a76..000000000000
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * board setup for STMP378x-Development-Board
- *
- * based on mx23evk board setup and information gained form the original
- * plat-stmp based board setup, now converted to mach-mxs.
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/spi/spi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx23.h>
-
-#include "devices-mx23.h"
-
-#define STMP378X_DEVB_MMC0_WRITE_PROTECT        MXS_GPIO_NR(1, 30)
-#define STMP378X_DEVB_MMC0_SLOT_POWER           MXS_GPIO_NR(1, 29)
-
-#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL)
-
-static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = {
-        /* duart (extended setup missing in old boardcode, too */
-        MX23_PAD_PWM0__DUART_RX,
-        MX23_PAD_PWM1__DUART_TX,
-
-        /* auart */
-        MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART,
-        MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART,
-        MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART,
-        MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART,
-
-        /* mmc */
-        MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_CMD__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DETECT__SSP1_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX23_PAD_SSP1_SCK__SSP1_SCK |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */
-        MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */
-};
-
-static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = {
-        .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT,
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
-        {
-                .modalias       = "enc28j60",
-                .max_speed_hz   = 6 * 1000 * 1000,
-                .bus_num        = 1,
-                .chip_select    = 0,
-                .platform_data  = NULL,
-        },
-#endif
-};
-
-static void __init stmp378x_dvb_init(void)
-{
-        int ret;
-
-        mx23_soc_init();
-
-        mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
-                        ARRAY_SIZE(stmp378x_dvb_pads));
-
-        mx23_add_duart();
-        mx23_add_auart0();
-        mx23_add_rtc_stmp3xxx();
-
-        /* power on mmc slot */
-        ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER,
-                GPIOF_OUT_INIT_LOW, "mmc0-slot-power");
-        if (ret)
-                pr_warn("could not power mmc (%d)\n", ret);
-
-        mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata);
-
-        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-}
-
-static void __init stmp378x_dvb_timer_init(void)
-{
-        mx23_clocks_init();
-}
-
-static struct sys_timer stmp378x_dvb_timer = {
-        .init   = stmp378x_dvb_timer_init,
-};
-
-MACHINE_START(STMP378X, "STMP378X")
-        .map_io         = mx23_map_io,
-        .init_irq       = mx23_init_irq,
-        .timer          = &stmp378x_dvb_timer,
-        .init_machine   = stmp378x_dvb_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
deleted file mode 100644
index 8837029de1a4..000000000000
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (C) 2010 <LW@KARO-electronics.de>
- *
- * based on: mach-mx28_evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation
- */
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-#include <linux/i2c.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-
-#include "devices-mx28.h"
-#include "module-tx28.h"
-
-#define TX28_STK5_GPIO_LED              MXS_GPIO_NR(4, 10)
-
-static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
-        /* LED */
-        MX28_PAD_ENET0_RXD3__GPIO_4_10 |
-                MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL,
-
-        /* framebuffer */
-#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA)
-        MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE,
-        MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE,
-        MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE,
-        MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE,
-        MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE,
-        MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE,
-        MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE,
-        MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE,
-        MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE,
-        MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE,
-        MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE,
-        MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE,
-        MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE,
-        MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE,
-        MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE,
-        MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE,
-        MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE,
-        MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE,
-        MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE,
-        MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE,
-        MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE,
-        MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE,
-        MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE,
-        MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE,
-        MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE,
-        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE,
-        MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE,
-        MX28_PAD_LCD_CS__LCD_CS | LCD_MODE,
-        MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE,
-        MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE,
-        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE,
-        MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE,
-        MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE,
-        MX28_PAD_PWM0__PWM_0 | LCD_MODE,
-
-        /* UART1 */
-        MX28_PAD_AUART0_CTS__DUART_RX,
-        MX28_PAD_AUART0_RTS__DUART_TX,
-        MX28_PAD_AUART0_TX__DUART_RTS,
-        MX28_PAD_AUART0_RX__DUART_CTS,
-
-        /* UART2 */
-        MX28_PAD_AUART1_RX__AUART1_RX,
-        MX28_PAD_AUART1_TX__AUART1_TX,
-        MX28_PAD_AUART1_RTS__AUART1_RTS,
-        MX28_PAD_AUART1_CTS__AUART1_CTS,
-
-        /* CAN */
-        MX28_PAD_GPMI_RDY2__CAN0_TX,
-        MX28_PAD_GPMI_RDY3__CAN0_RX,
-
-        /* I2C */
-        MX28_PAD_I2C0_SCL__I2C0_SCL,
-        MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-        /* TSC2007 */
-        MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
-
-        /* MMC0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-};
-
-static const struct gpio_led tx28_stk5v3_leds[] __initconst = {
-        {
-                .name = "GPIO-LED",
-                .default_trigger = "heartbeat",
-                .gpio = TX28_STK5_GPIO_LED,
-        },
-};
-
-static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = {
-        .leds = tx28_stk5v3_leds,
-        .num_leds = ARRAY_SIZE(tx28_stk5v3_leds),
-};
-
-static struct spi_board_info tx28_spi_board_info[] = {
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT,
-                .mode = SPI_MODE_0,
-        },
-};
-
-static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
-        {
-                I2C_BOARD_INFO("ds1339", 0x68),
-        },
-};
-
-static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
-       .wp_gpio = -EINVAL,
-       .flags = SLOTF_4_BIT_CAPABLE,
-};
-
-static void __init tx28_stk5v3_init(void)
-{
-        mx28_soc_init();
-
-        mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
-                        ARRAY_SIZE(tx28_stk5v3_pads));
-
-        mx28_add_duart(); /* UART1 */
-        mx28_add_auart(1); /* UART2 */
-
-        tx28_add_fec0();
-        /* spi via ssp will be added when available */
-        spi_register_board_info(tx28_spi_board_info,
-                        ARRAY_SIZE(tx28_spi_board_info));
-        gpio_led_register_device(0, &tx28_stk5v3_led_data);
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
-                        ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
-        mx28_add_mxs_mmc(0, &tx28_mmc0_pdata);
-        mx28_add_rtc_stmp3xxx();
-}
-
-static void __init tx28_timer_init(void)
-{
-        mx28_clocks_init();
-}
-
-static struct sys_timer tx28_timer = {
-        .init = tx28_timer_init,
-};
-
-MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
-        .map_io = mx28_map_io,
-        .init_irq = mx28_init_irq,
-        .timer = &tx28_timer,
-        .init_machine = tx28_stk5v3_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index dccb67a9e7c4..a4294aa9f301 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -13,14 +13,11 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <linux/pinctrl/machine.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/mx23.h>
 #include <mach/mx28.h>
-#include <mach/common.h>
-#include <mach/iomux.h>
 
 /*
  * Define the MX23 memory map.
@@ -48,43 +45,7 @@ void __init mx23_map_io(void)
         iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
 }
 
-void __init mx23_init_irq(void)
-{
-        icoll_init_irq();
-}
-
 void __init mx28_map_io(void)
 {
         iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
 }
-
-void __init mx28_init_irq(void)
-{
-        icoll_init_irq();
-}
-
-void __init mx23_soc_init(void)
-{
-        pinctrl_provide_dummies();
-
-        mxs_add_dma("imx23-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
-        mxs_add_dma("imx23-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
-
-        mxs_add_gpio("imx23-gpio", 0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0);
-        mxs_add_gpio("imx23-gpio", 1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1);
-        mxs_add_gpio("imx23-gpio", 2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2);
-}
-
-void __init mx28_soc_init(void)
-{
-        pinctrl_provide_dummies();
-
-        mxs_add_dma("imx28-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
-        mxs_add_dma("imx28-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
-
-        mxs_add_gpio("imx28-gpio", 0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0);
-        mxs_add_gpio("imx28-gpio", 1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1);
-        mxs_add_gpio("imx28-gpio", 2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2);
-        mxs_add_gpio("imx28-gpio", 3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3);
-        mxs_add_gpio("imx28-gpio", 4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4);
-}
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
deleted file mode 100644
index 0f71f82101cc..000000000000
--- a/arch/arm/mach-mxs/module-tx28.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright (C) 2010 <LW@KARO-electronics.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include <linux/delay.h>
-#include <linux/fec.h>
-#include <linux/gpio.h>
-
-#include <mach/iomux-mx28.h>
-#include "devices-mx28.h"
-
-#include "module-tx28.h"
-
-#define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
-#define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
-
-static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
-        /* PHY POWER */
-        MX28_PAD_PWM4__GPIO_3_29 |
-                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-        /* PHY RESET */
-        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
-                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-        /* Mode strap pins 0-2 */
-        MX28_PAD_ENET0_RXD0__GPIO_4_3 |
-                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-        MX28_PAD_ENET0_RXD1__GPIO_4_4 |
-                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-        MX28_PAD_ENET0_RX_EN__GPIO_4_2 |
-                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-        /* nINT */
-        MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
-                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-
-        MX28_PAD_ENET0_MDC__GPIO_4_0,
-        MX28_PAD_ENET0_MDIO__GPIO_4_1,
-        MX28_PAD_ENET0_TX_EN__GPIO_4_6,
-        MX28_PAD_ENET0_TXD0__GPIO_4_7,
-        MX28_PAD_ENET0_TXD1__GPIO_4_8,
-        MX28_PAD_ENET_CLK__GPIO_4_16,
-};
-
-#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
-static const iomux_cfg_t tx28_fec0_pads[] __initconst = {
-        MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
-};
-
-static const iomux_cfg_t tx28_fec1_pads[] __initconst = {
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1,
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0,
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN,
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN,
-};
-
-static const struct fec_platform_data tx28_fec0_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct fec_platform_data tx28_fec1_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-int __init tx28_add_fec0(void)
-{
-        int i, ret;
-
-        pr_debug("%s: Switching FEC PHY power off\n", __func__);
-        ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads,
-                        ARRAY_SIZE(tx28_fec_gpio_pads));
-        for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) {
-                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
-                        PAD_PIN(tx28_fec_gpio_pads[i]));
-
-                ret = gpio_request(gpio, "FEC");
-                if (ret) {
-                        pr_err("Failed to request GPIO_%d_%d: %d\n",
-                                PAD_BANK(tx28_fec_gpio_pads[i]),
-                                PAD_PIN(tx28_fec_gpio_pads[i]), ret);
-                        goto free_gpios;
-                }
-                ret = gpio_direction_output(gpio, 0);
-                if (ret) {
-                        pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n",
-                                        gpio / 32 + 1, gpio % 32, ret);
-                        goto free_gpios;
-                }
-        }
-
-        /* Power up fec phy */
-        pr_debug("%s: Switching FEC PHY power on\n", __func__);
-        ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1);
-        if (ret) {
-                pr_err("Failed to power on PHY: %d\n", ret);
-                goto free_gpios;
-        }
-        mdelay(26); /* 25ms according to data sheet */
-
-        /* nINT */
-        gpio_direction_input(MXS_GPIO_NR(4, 5));
-        /* Mode strap pins */
-        gpio_direction_output(MXS_GPIO_NR(4, 2), 1);
-        gpio_direction_output(MXS_GPIO_NR(4, 3), 1);
-        gpio_direction_output(MXS_GPIO_NR(4, 4), 1);
-
-        udelay(100); /* minimum assertion time for nRST */
-
-        pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
-        gpio_set_value(TX28_FEC_PHY_RESET, 1);
-
-        ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads,
-                        ARRAY_SIZE(tx28_fec0_pads));
-        if (ret) {
-                pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
-                                __func__, ret);
-                goto free_gpios;
-        }
-        pr_debug("%s: Registering FEC0 device\n", __func__);
-        mx28_add_fec(0, &tx28_fec0_data);
-        return 0;
-
-free_gpios:
-        while (--i >= 0) {
-                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
-                        PAD_PIN(tx28_fec_gpio_pads[i]));
-
-                gpio_free(gpio);
-        }
-
-        return ret;
-}
-
-int __init tx28_add_fec1(void)
-{
-        int ret;
-
-        ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads,
-                        ARRAY_SIZE(tx28_fec1_pads));
-        if (ret) {
-                pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
-                                __func__, ret);
-                return ret;
-        }
-        pr_debug("%s: Registering FEC1 device\n", __func__);
-        mx28_add_fec(1, &tx28_fec1_data);
-        return 0;
-}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
deleted file mode 100644
index 8ed425457d30..000000000000
--- a/arch/arm/mach-mxs/module-tx28.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- *   Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-int __init tx28_add_fec0(void);
-int __init tx28_add_fec1(void);
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index 180ea899a48a..8b781ff7c9e9 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -30,7 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
-#include <mach/eth.h>
+#include <linux/platform_data/eth-netx.h>
 
 #include "generic.h"
 #include "fb.h"
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index 58009e29b20e..b26dbce334f2 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -30,7 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
-#include <mach/eth.h>
+#include <linux/platform_data/eth-netx.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index 122e99826ef6..257382efafa0 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -30,7 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
-#include <mach/eth.h>
+#include <linux/platform_data/eth-netx.h>
 
 #include "generic.h"
 #include "fb.h"
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index f4535a7dadf5..381c08027df4 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -34,7 +34,7 @@
 #include <plat/gpio-nomadik.h>
 #include <plat/mtu.h>
 
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-nomadik-nand.h>
 #include <mach/fsmc.h>
 
 #include "cpu-8815.h"
diff --git a/arch/arm/mach-nomadik/include/mach/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h
deleted file mode 100644
index efdde0ae0a4f..000000000000
--- a/arch/arm/mach-nomadik/include/mach/gpio.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-nomadik/include/mach/hardware.h b/arch/arm/mach-nomadik/include/mach/hardware.h
index 6316dba3bfc8..02035e459f50 100644
--- a/arch/arm/mach-nomadik/include/mach/hardware.h
+++ b/arch/arm/mach-nomadik/include/mach/hardware.h
@@ -30,7 +30,7 @@
                         - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
 
 /* used in asm code, so no casts */
-#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
+#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
 
 /*
  *   Base address defination for Nomadik Onchip Logic Block
diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h
index 071003bc8456..7d4687e9cbdf 100644
--- a/arch/arm/mach-nomadik/include/mach/uncompress.h
+++ b/arch/arm/mach-nomadik/include/mach/uncompress.h
@@ -27,10 +27,10 @@
 struct amba_device;
 #include <linux/amba/serial.h>
 
-#define NOMADIK_UART_DR         0x101FB000
-#define NOMADIK_UART_LCRH       0x101FB02c
-#define NOMADIK_UART_CR         0x101FB030
-#define NOMADIK_UART_FR         0x101FB018
+#define NOMADIK_UART_DR         (void __iomem *)0x101FB000
+#define NOMADIK_UART_LCRH       (void __iomem *)0x101FB02c
+#define NOMADIK_UART_CR         (void __iomem *)0x101FB030
+#define NOMADIK_UART_FR         (void __iomem *)0x101FB018
 
 static void putc(const char c)
 {
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index d2b6acce8fc1..3d1e1c250a1a 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -16,7 +16,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <mach/irqs.h>
 #include <mach/ams-delta-fiq.h>
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index 68e8e5654c0a..f12a12af3523 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -19,7 +19,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <asm/fiq.h>
 
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 6f192c4900b1..9518bf5996dc 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -35,9 +35,9 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board-ams-delta.h>
-#include <plat/keypad.h>
-#include <plat/mux.h>
+#include <mach/board-ams-delta.h>
+#include <linux/platform_data/keypad-omap.h>
+#include <mach/mux.h>
 
 #include <mach/hardware.h>
 #include <mach/ams-delta-fiq.h>
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 6d985521a39e..4b6de70c47a6 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -28,10 +28,10 @@
 #include <asm/mach/map.h>
 
 #include <plat/tc.h>
-#include <plat/mux.h>
-#include <plat/flash.h>
+#include <mach/mux.h>
+#include <mach/flash.h>
 #include <plat/fpga.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 04b5fdaff831..4ec579fdd366 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -22,7 +22,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #include <mach/usb.h>
 
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index fe79c56b2dc0..af283a2bc7c7 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -37,12 +37,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/irda.h>
-#include <plat/keypad.h>
-#include <plat/flash.h>
+#include <mach/irda.h>
+#include <linux/platform_data/keypad-omap.h>
+#include <mach/flash.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 6c46f33894fb..06d11b1ee9c6 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -39,11 +39,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 #include <plat/dma.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 1dcb751b8fe5..87ab2086ef96 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -37,12 +37,12 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <mach/omap7xx.h>
-#include <plat/keypad.h>
 #include <plat/mmc.h>
 
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index f21c2966daad..db5f7d2976e7 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -31,11 +31,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
-#include <plat/flash.h>
+#include <mach/mux.h>
+#include <mach/flash.h>
 #include <plat/fpga.h>
 #include <plat/tc.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 #include <plat/mmc.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index ec01f03d0446..7d5c06d6a52a 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -21,13 +21,14 @@
 #include <linux/workqueue.h>
 #include <linux/delay.h>
 
+#include <linux/platform_data/keypad-omap.h>
+#include <linux/platform_data/lcd-mipid.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
-#include <plat/keypad.h>
-#include <plat/lcd_mipid.h>
+#include <mach/mux.h>
 #include <plat/mmc.h>
 #include <plat/clock.h>
 
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 3b2d9071022a..2f1f9b967576 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -46,8 +46,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 
 #include <mach/hardware.h>
@@ -304,7 +304,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 
 static struct at24_platform_data at24c04 = {
         .byte_len       = SZ_4K / 8,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 49f8d745ea1f..1c578d58923a 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -34,12 +34,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 #include <plat/dma.h>
-#include <plat/irda.h>
-#include <plat/keypad.h>
+#include <mach/irda.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 01523cd78e58..97158095083c 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -34,12 +34,12 @@
 #include <asm/mach/map.h>
 
 #include <plat/led.h>
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/irda.h>
-#include <plat/keypad.h>
+#include <mach/irda.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index a7abce69043a..e311032e7eeb 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -36,12 +36,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/irda.h>
-#include <plat/keypad.h>
+#include <mach/irda.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 277e0bc60a43..198b05417bfc 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -22,16 +22,16 @@
 #include <linux/input.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <plat/tc.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/fpga.h>
-#include <plat/flash.h>
-#include <plat/keypad.h>
+#include <mach/flash.h>
 
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
index b59f78850e69..5932d56e17bf 100644
--- a/arch/arm/mach-omap1/board-sx1-mmc.c
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -17,7 +17,7 @@
 
 #include <mach/hardware.h>
 #include <plat/mmc.h>
-#include <plat/board-sx1.h>
+#include <mach/board-sx1.h>
 
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2e1fff26a2f3..13bf2cc56814 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -28,18 +28,18 @@
 #include <linux/errno.h>
 #include <linux/export.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
-#include <plat/irda.h>
+#include <mach/irda.h>
 #include <plat/tc.h>
-#include <plat/keypad.h>
-#include <plat/board-sx1.h>
+#include <mach/board-sx1.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 1668af3017de..ad75e3411d46 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -31,9 +31,9 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board-voiceblue.h>
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/board-voiceblue.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 7a5a3285e965..726c02c9c0cd 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -20,7 +20,7 @@
 #include <asm/mach/map.h>
 
 #include <plat/tc.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/mmc.h>
 
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index 401eb3c080c2..73ae6169aa4a 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -11,7 +11,7 @@
 #include <linux/mtd/map.h>
 
 #include <plat/tc.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
 
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index 5446c9912641..a0551a6d7451 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -20,7 +20,7 @@
  */
 
 #include <plat/i2c.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/cpu.h>
 
 void __init omap1_i2c_mux_pins(int bus_id)
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/mach-omap1/include/mach/board-ams-delta.h
index ad6f865d1f16..ad6f865d1f16 100644
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ b/arch/arm/mach-omap1/include/mach/board-ams-delta.h
diff --git a/arch/arm/plat-omap/include/plat/board-sx1.h b/arch/arm/mach-omap1/include/mach/board-sx1.h
index 355adbdaae33..355adbdaae33 100644
--- a/arch/arm/plat-omap/include/plat/board-sx1.h
+++ b/arch/arm/mach-omap1/include/mach/board-sx1.h
diff --git a/arch/arm/plat-omap/include/plat/board-voiceblue.h b/arch/arm/mach-omap1/include/mach/board-voiceblue.h
index 27916b210f57..27916b210f57 100644
--- a/arch/arm/plat-omap/include/plat/board-voiceblue.h
+++ b/arch/arm/mach-omap1/include/mach/board-voiceblue.h
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/mach-omap1/include/mach/flash.h
index 0d88499b79e9..0d88499b79e9 100644
--- a/arch/arm/plat-omap/include/plat/flash.h
+++ b/arch/arm/mach-omap1/include/mach/flash.h
diff --git a/arch/arm/plat-omap/include/plat/irda.h b/arch/arm/mach-omap1/include/mach/irda.h
index 40f60339d1c6..40f60339d1c6 100644
--- a/arch/arm/plat-omap/include/plat/irda.h
+++ b/arch/arm/mach-omap1/include/mach/irda.h
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/mach-omap1/include/mach/mux.h
index 323948959200..323948959200 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/mach-omap1/include/mach/mux.h
diff --git a/arch/arm/mach-omap1/include/mach/smp.h b/arch/arm/mach-omap1/include/mach/smp.h
deleted file mode 100644
index 80a371c06e59..000000000000
--- a/arch/arm/mach-omap1/include/mach/smp.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/smp.h
- */
-
-#include <plat/smp.h>
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 6c95a59f0f16..6a5baab1f4cb 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -16,7 +16,7 @@
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 #include <plat/dma.h>
 
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
index 7b1a3833165d..4071479f7106 100644
--- a/arch/arm/mach-omap1/leds.c
+++ b/arch/arm/mach-omap1/leds.c
@@ -11,7 +11,7 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index adf00975b9bb..bdc2e7541adb 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -20,9 +20,9 @@
 #include <linux/slab.h>
 
 #include <plat/dma.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/cpu.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include <mach/irqs.h>
 
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index e9cc52d4cb28..667ce5027f63 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -29,7 +29,7 @@
 
 #include <mach/hardware.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
@@ -451,6 +451,56 @@ static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
 #endif
 }
 
+static struct omap_mux_cfg *mux_cfg;
+
+int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
+{
+        if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
+                        || !arch_mux_cfg->cfg_reg) {
+                printk(KERN_ERR "Invalid pin table\n");
+                return -EINVAL;
+        }
+
+        mux_cfg = arch_mux_cfg;
+
+        return 0;
+}
+
+/*
+ * Sets the Omap MUX and PULL_DWN registers based on the table
+ */
+int __init_or_module omap_cfg_reg(const unsigned long index)
+{
+        struct pin_config *reg;
+
+        if (!cpu_class_is_omap1()) {
+                printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
+                                index);
+                WARN_ON(1);
+                return -EINVAL;
+        }
+
+        if (mux_cfg == NULL) {
+                printk(KERN_ERR "Pin mux table not initialized\n");
+                return -ENODEV;
+        }
+
+        if (index >= mux_cfg->size) {
+                printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
+                       index, mux_cfg->size);
+                dump_stack();
+                return -ENODEV;
+        }
+
+        reg = &mux_cfg->pins[index];
+
+        if (!mux_cfg->cfg_reg)
+                return -ENODEV;
+
+        return mux_cfg->cfg_reg(reg);
+}
+EXPORT_SYMBOL(omap_cfg_reg);
+
 int __init omap1_mux_init(void)
 {
         if (cpu_is_omap7xx()) {
@@ -468,4 +518,8 @@ int __init omap1_mux_init(void)
         return omap_mux_register(&arch_mux_cfg);
 }
 
-#endif
+#else
+#define omap_mux_init() do {} while(0)
+#define omap_cfg_reg(x) do {} while(0)
+#endif  /* CONFIG_OMAP_MUX */
+
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index b2560d32b3a0..47ec16155483 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -53,7 +53,7 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/tc.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
 
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 0d1709b1a6fe..b9d6834af835 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -22,7 +22,7 @@
 
 #include <asm/mach-types.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/fpga.h>
 
 #include "pm.h"
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 65f88176fba8..84267edd9421 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -26,7 +26,7 @@
 
 #include <asm/irq.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #include <mach/usb.h>
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 346fd26f3aa6..eef99b77c40b 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -18,6 +18,7 @@ config ARCH_OMAP2PLUS_TYPICAL
         select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
         select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
         select HIGHMEM
+        select PINCTRL
         help
           Compile a kernel suitable for booting most boards
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 0deb30072977..b807deb0f521 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,36 +4,30 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o
 
-omap-2-3-common                         = irq.o
-hwmod-common                            = omap_hwmod.o \
-                                          omap_hwmod_common_data.o
-clock-common                            = clock.o clock_common_data.o \
-                                          clkt_dpll.o clkt_clksel.o
-secure-common                           = omap-smc.o omap-secure.o
+# INTCPS IP block support - XXX should be moved to drivers/
+obj-$(CONFIG_ARCH_OMAP2)                += irq.o
+obj-$(CONFIG_ARCH_OMAP3)                += irq.o
+obj-$(CONFIG_SOC_AM33XX)                += irq.o
 
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
-obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
-obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
+# Secure monitor API support
+obj-$(CONFIG_ARCH_OMAP3)                += omap-smc.o omap-secure.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap-smc.o omap-secure.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap-smc.o omap-secure.o
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
 endif
 
-obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
-obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
+obj-$(CONFIG_TWL4030_CORE)              += omap_twl.o
 
 # SMP support ONLY available for OMAP4
 
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o \
-                                           sleep44xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common)
-obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common)
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap4-common.o omap-wakeupgen.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,6 +52,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= mux44xx.o
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
+obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
 
 # OPP table initialization
 ifeq ($(CONFIG_PM_OPP),y)
@@ -68,15 +63,15 @@ endif
 
 # Power Management
 ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
-obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP4)                += sleep44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o sleep44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 
 obj-$(CONFIG_POWER_AVS_OMAP)            += sr_device.o
-obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)     += smartreflex-class3.o
 
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
@@ -88,92 +83,76 @@ endif
 endif
 
 ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
 endif
 
 # PRCM
-omap-prcm-4-5-common                    =  prcm.o cminst44xx.o cm44xx.o \
-                                           prcm_mpu44xx.o prminst44xx.o \
-                                           vc44xx_data.o vp44xx_data.o
-obj-y                                   += prm_common.o
-obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
-obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-y                                   += prcm.o prm_common.o
+obj-$(CONFIG_ARCH_OMAP2)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += prcm.o prm33xx.o cm33xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_SOC_AM33XX)                += prm33xx.o cm33xx.o
+omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
+                                           prcm_mpu44xx.o prminst44xx.o \
+                                           vc44xx_data.o vp44xx_data.o \
+                                           prm44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
-voltagedomain-common                    := voltage.o vc.o vp.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common)
+obj-y                                   += voltage.o vc.o vp.o
 obj-$(CONFIG_ARCH_OMAP2)                += voltagedomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += voltagedomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
-obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
+obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
 
 # OMAP powerdomain framework
-powerdomain-common                      += powerdomain.o powerdomain-common.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(powerdomain-common)
+obj-y                                   += powerdomain.o powerdomain-common.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_data.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += powerdomain44xx.o
 
 # PRCM clockdomain control
-clockdomain-common                      += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(clockdomain-common)
+obj-y                                   += clockdomain.o
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += clockdomain44xx.o
 
 # Clock framework
-obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
-obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_sys.o
-obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o
+obj-y                                   += clock.o clock_common_data.o \
+                                           clkt_dpll.o clkt_clksel.o
+obj-$(CONFIG_ARCH_OMAP2)                += clock2xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o clkt2xxx_sys.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_virt_prcm_set.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_apll.o clkt2xxx_osc.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpll.o clkt_iclk.o
 obj-$(CONFIG_SOC_OMAP2420)              += clock2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o clock2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o clkt34xx_dpll3m2.o
-obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP3)                += dpll3xxx.o clock3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += clock44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
-obj-$(CONFIG_SOC_AM33XX)                += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)                += clock33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(clock-common)
+obj-$(CONFIG_SOC_AM33XX)                += dpll3xxx.o clock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)                 += dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
@@ -181,6 +160,7 @@ obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 
 # hwmod data
+obj-y                                   += omap_hwmod_common_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_interconnect_data.o
@@ -231,10 +211,10 @@ obj-$(CONFIG_MACH_OMAP_H4)		+= board-h4.o
 obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
 obj-$(CONFIG_MACH_OMAP_APOLLON)         += board-apollon.o
 obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
-obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
+obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
 obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 2c90ac686686..d0c54c573d34 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -19,7 +19,7 @@
 #include <linux/davinci_emac.h>
 #include <asm/system.h>
 #include <plat/omap_device.h>
-#include <mach/am35xx.h>
+#include "am35xx.h"
 #include "control.h"
 #include "am35xx-emac.h"
 
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/am35xx.h
index 95594495fcf6..95594495fcf6 100644
--- a/arch/arm/mach-omap2/include/mach/am35xx.h
+++ b/arch/arm/mach-omap2/am35xx.h
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 0900eac57d56..95b384d54f8a 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -36,7 +36,7 @@
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 5453173ff57b..96cd3693e1ae 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -24,12 +24,12 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mcspi.h>
 #include <plat/usb.h>
 #include "common.h"
 #include <plat/dma.h>
@@ -37,7 +37,7 @@
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 
 #include "board-flash.h"
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 8518b1345988..fc224ad86747 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -17,7 +17,7 @@
 #include <asm/mach/arch.h>
 
 #include "common.h"
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index db43e22526c0..6fe90796d462 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -36,7 +36,7 @@
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
-#include <plat/omap4-keypad.h>
+#include "omap4-keypad.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-nokia-dsi.h>
 #include <video/omap-panel-picodlp.h>
@@ -907,6 +907,7 @@ static void __init omap_4430sdp_init(void)
 MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
         /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(omap4_smp_ops),
         .reserve        = omap_reserve,
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 403d048a00ee..0d99c9110d01 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -27,7 +27,7 @@
 #include <linux/mmc/host.h>
 #include <linux/platform_data/gpio-omap.h>
 
-#include <mach/am35xx.h>
+#include "am35xx.h"
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 34cb90471d96..8ffd612c5e07 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -39,13 +39,13 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <mach/hardware.h>
 
@@ -64,7 +64,7 @@
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
         .id             = 0,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 27a5450751ed..59c0a45f75b0 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -40,10 +40,10 @@
 
 #include "common.h"
 #include <plat/usb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
 
-#include <mach/am35xx.h>
+#include "am35xx.h"
 
 #include "mux.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 18b63ad56274..7bb8056d4388 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -32,7 +32,7 @@
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
-#include <mach/id.h>
+#include "id.h"
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -40,13 +40,13 @@
 
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/dm9000.h>
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 9017813f9abc..0cabe61cd507 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -19,8 +19,8 @@
 
 #include <plat/cpu.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <plat/tc.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 2ea7c577b295..601ecdfb1cf9 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -125,6 +125,7 @@ static const char *omap4_boards_compat[] __initdata = {
 
 DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
         .reserve        = omap_reserve,
+        .smp            = smp_ops(omap4_smp_ops),
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
         .init_irq       = omap_gic_of_init,
@@ -145,6 +146,7 @@ static const char *omap5_boards_compat[] __initdata = {
 
 DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
         .reserve        = omap_reserve,
+        .smp            = smp_ops(omap4_smp_ops),
         .map_io         = omap5_map_io,
         .init_early     = omap5_init_early,
         .init_irq       = omap_gic_of_init,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 313b3f426a56..8d04bf851af4 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -34,7 +34,7 @@
 #include <plat/menelaus.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/debug-devices.h>
+#include "debug-devices.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 8408bb2748a6..fb8bd837dd13 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -35,7 +35,7 @@
 
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -192,7 +192,7 @@ static void __init igep_flash_init(void) {}
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
         .cs             = IGEP2_SMSC911X_CS,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 3f3a552b1036..ee8c3cfb95b3 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -28,17 +28,17 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mcspi.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <mach/board-zoom.h>
 #include <plat/usb.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 4b43fe311571..d95f727ca39a 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -20,6 +20,8 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <sound/tlv320aic3x.h>
 
 #include <asm/mach/arch.h>
@@ -27,8 +29,6 @@
 
 #include "common.h"
 #include <plat/menelaus.h>
-#include <plat/mcspi.h>
-#include <plat/onenand.h>
 #include <plat/mmc.h>
 
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 801bcb4c5e22..68ff8d51973c 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -42,7 +42,7 @@
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b94873d0c6b6..3fe5f0f69c73 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -45,9 +45,9 @@
 #include <asm/mach/map.h>
 
 #include <plat/usb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include "common.h"
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
@@ -118,7 +118,7 @@ static void __init omap3_evm_get_revision(void)
 }
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
         .cs             = OMAP3EVM_SMSC911X_CS,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index b5e56fa83c19..7bd8253b5d1d 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -34,7 +34,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
 #include <plat/usb.h>
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index e700a98feba6..00a1f4ae6e44 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -35,16 +35,16 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 #include <linux/regulator/fixed.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/mcspi.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index b8756f0d2a08..c7f3d026e6d4 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -41,13 +41,13 @@
 
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/interrupt.h>
@@ -60,7 +60,7 @@
 #include "common-board-devices.h"
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 #define OMAP3STALKER_ETHR_START 0x2c000000
 #define OMAP3STALKER_ETHR_SIZE  1024
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 0e2f838e4009..944ffc436577 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -29,7 +29,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/spi/spi.h>
 
 #include <linux/spi/ads7846.h>
@@ -45,7 +45,7 @@
 
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 8ae2c599dd7f..556e777b9c40 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -516,6 +516,7 @@ static void __init omap4_panda_init(void)
 MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
         /* Maintainer: David Anders - Texas Instruments Inc */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(omap4_smp_ops),
         .reserve        = omap_reserve,
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 13c101c2c643..2e7f24030fc9 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -37,6 +37,9 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
 
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
@@ -47,8 +50,6 @@
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
-#include <plat/mcspi.h>
 #include <plat/usb.h>
 
 #include "mux.h"
@@ -113,7 +114,7 @@ static inline void __init overo_ads7846_init(void) { return; }
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
         .id             = 0,
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 00773a32524a..45997bfbcbd2 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -17,6 +17,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -26,7 +27,6 @@
 #include <plat/usb.h>
 #include <plat/gpmc.h>
 #include "common.h"
-#include <plat/onenand.h>
 #include <plat/serial.h>
 
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 456049055daa..3945c5017085 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -25,16 +25,17 @@
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
 #include <linux/power/isp1704_charger.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
+
 #include <asm/system_info.h>
 
-#include <plat/mcspi.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/onenand.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 
-#include <mach/board-rx51.h>
+#include "board-rx51.h"
 
 #include <sound/tlv320aic3x.h>
 #include <sound/tpa6130a2-plat.h>
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 2c1289bd5e6a..c22e111bcd00 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -17,9 +17,9 @@
 #include <asm/mach-types.h>
 #include <video/omapdss.h>
 #include <plat/vram.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/board-rx51.h>
+#include "board-rx51.h"
 
 #include "mux.h"
 
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 93b466150002..7bbb05d9689b 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -17,12 +17,12 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mcspi.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/board-rx51.h
index b76f49e7eed5..b76f49e7eed5 100644
--- a/arch/arm/mach-omap2/include/mach/board-rx51.h
+++ b/arch/arm/mach-omap2/board-rx51.h
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 0d8d91917d10..afb2278a29f6 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -18,7 +18,7 @@
 #include <linux/regulator/machine.h>
 
 #include <plat/gpmc.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 #include <mach/board-zoom.h>
 
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index ea79bc299baf..b940ab2259fb 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -14,7 +14,7 @@
 #include <linux/gpio.h>
 #include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <mach/board-zoom.h>
 
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index f81dd0a18aaf..48daac2581b4 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -24,8 +24,8 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 
-#include <plat/mcspi.h>
-#include <plat/nand.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include "common.h"
 #include "common-board-devices.h"
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 8e43c4d885d5..17950c6e130b 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -17,7 +17,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/mux.h>
 #include <plat/clock.h>
 
 #include "soc.h"
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index da0f5c187353..7045e4d61ac3 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -285,6 +285,11 @@ extern void omap_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
+
+extern void omap4_cpu_die(unsigned int cpu);
+
+extern struct smp_operations omap4_smp_ops;
+
 extern void omap5_secondary_startup(void);
 #endif
 
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 5594b42372ee..a89e8256fd0e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -16,10 +16,10 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
 
-#include <mach/ctrl_module_core_44xx.h>
-#include <mach/ctrl_module_wkup_44xx.h>
-#include <mach/ctrl_module_pad_core_44xx.h>
-#include <mach/ctrl_module_pad_wkup_44xx.h>
+#include "ctrl_module_core_44xx.h"
+#include "ctrl_module_wkup_44xx.h"
+#include "ctrl_module_pad_core_44xx.h"
+#include "ctrl_module_pad_wkup_44xx.h"
 
 #include "am33xx.h"
 
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_core_44xx.h
index 01970824e0e5..01970824e0e5 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_core_44xx.h
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
index c88420de1151..c88420de1151 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
index 17c9b37042c0..17c9b37042c0 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h
index a0af9baec3f7..a0af9baec3f7 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h
diff --git a/arch/arm/plat-omap/include/plat/debug-devices.h b/arch/arm/mach-omap2/debug-devices.h
index a4edbd2f7484..a4edbd2f7484 100644
--- a/arch/arm/plat-omap/include/plat/debug-devices.h
+++ b/arch/arm/mach-omap2/debug-devices.h
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 1b7e1c6e5359..c8c211731d26 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -22,13 +22,12 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
-#include <asm/pmu.h>
 
 #include "iomap.h"
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-#include <plat/omap4-keypad.h>
+#include "omap4-keypad.h"
 
 #include "soc.h"
 #include "common.h"
@@ -385,7 +384,7 @@ static inline void omap_init_hdmi_audio(void) {}
 
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index a636ebc16b39..98388109f22a 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -30,7 +30,7 @@
 #include <plat/omap-pm.h>
 #endif
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 static struct platform_device *omap_dsp_pdev;
 
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 9e9f47ad6187..4acf497faeb3 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -13,10 +13,10 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include <asm/mach/flash.h>
 
-#include <plat/nand.h>
 #include <plat/gpmc.h>
 
 #include "soc.h"
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index b66fb8e5faaa..916716e1da3b 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -15,10 +15,10 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/onenand_regs.h>
 #include <linux/io.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach/flash.h>
 
-#include <plat/onenand.h>
 #include <plat/gpmc.h>
 
 #include "soc.h"
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 245839dfc722..565475310374 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -18,7 +18,7 @@
 #include <linux/smc91x.h>
 
 #include <plat/gpmc.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 
 #include "soc.h"
 
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h b/arch/arm/mach-omap2/gpmc-smc91x.h
index b64fbee4d567..b64fbee4d567 100644
--- a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
+++ b/arch/arm/mach-omap2/gpmc-smc91x.h
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index a3a28878f0c9..249a0b440cd6 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -21,7 +21,7 @@
 #include <linux/smsc911x.h>
 
 #include <plat/gpmc.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct resource gpmc_smsc911x_resources[] = {
         [0] = {
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/mach-omap2/gpmc-smsc911x.h
index ea6c9c88c725..ea6c9c88c725 100644
--- a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.h
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index cdd6dda03828..e003f2bba30c 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -29,7 +29,7 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-#include <plat/hdq1w.h>
+#include "hdq1w.h"
 
 #include "common.h"
 
diff --git a/arch/arm/plat-omap/include/plat/hdq1w.h b/arch/arm/mach-omap2/hdq1w.h
index 0c1efc846d8d..0c1efc846d8d 100644
--- a/arch/arm/plat-omap/include/plat/hdq1w.h
+++ b/arch/arm/mach-omap2/hdq1w.h
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 80399d740952..03ebf47cfa9a 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -19,7 +19,6 @@
 
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
-#include <plat/mux.h>
 #include <plat/omap_device.h>
 
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 6b98a178fbe0..cf2362ccb234 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -23,7 +23,7 @@
 
 #include "common.h"
 
-#include <mach/id.h>
+#include "id.h"
 
 #include "soc.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/id.h
index 02ed3aa56f1e..02ed3aa56f1e 100644
--- a/arch/arm/mach-omap2/include/mach/id.h
+++ b/arch/arm/mach-omap2/id.h
diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h
deleted file mode 100644
index 323675f21b69..000000000000
--- a/arch/arm/mach-omap2/include/mach/smp.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/smp.h
- */
-
-#include <plat/smp.h>
diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h
index b8b5641379b0..b8b5641379b0 100644
--- a/arch/arm/plat-omap/include/plat/l3_2xxx.h
+++ b/arch/arm/mach-omap2/l3_2xxx.h
diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/mach-omap2/l3_3xxx.h
index cde1938c5f82..cde1938c5f82 100644
--- a/arch/arm/plat-omap/include/plat/l3_3xxx.h
+++ b/arch/arm/mach-omap2/l3_3xxx.h
diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h
index 3f39cf8a35c6..3f39cf8a35c6 100644
--- a/arch/arm/plat-omap/include/plat/l4_2xxx.h
+++ b/arch/arm/mach-omap2/l4_2xxx.h
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/mach-omap2/l4_3xxx.h
index 881a858b1ffc..881a858b1ffc 100644
--- a/arch/arm/plat-omap/include/plat/l4_3xxx.h
+++ b/arch/arm/mach-omap2/l4_3xxx.h
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index d493727632e9..7d47407d6d46 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -17,9 +17,9 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include <plat/dma.h>
-#include <plat/mcbsp.h>
 #include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
 
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 414083b427df..e712d1725a8b 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -20,22 +20,17 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-wakeupgen.h"
 
 #include "common.h"
 
 #include "powerdomain.h"
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
 /*
  * platform-specific code to shutdown a CPU
  * Called with IRQs disabled
  */
-void __ref platform_cpu_die(unsigned int cpu)
+void __ref omap4_cpu_die(unsigned int cpu)
 {
         unsigned int boot_cpu = 0;
         void __iomem *base = omap_get_wakeupgen_base();
@@ -75,12 +70,3 @@ void __ref platform_cpu_die(unsigned int cpu)
                 pr_debug("CPU%u: spurious wakeup call\n", cpu);
         }
 }
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index d9ae4a53d818..a004cb9acf52 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -19,7 +19,7 @@
 #include <asm/memblock.h>
 
 #include <plat/omap-secure.h>
-#include <mach/omap-secure.h>
+#include "omap-secure.h"
 
 static phys_addr_t omap_secure_memblock_base;
 
diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index c90a43589abe..c90a43589abe 100644
--- a/arch/arm/mach-omap2/include/mach/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 19cc5f504f7e..4d05fa8a4e48 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,8 +24,8 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 
-#include <mach/omap-secure.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-secure.h"
+#include "omap-wakeupgen.h"
 #include <asm/cputype.h>
 
 #include "soc.h"
@@ -49,7 +49,7 @@ void __iomem *omap4_get_scu_base(void)
         return scu_base;
 }
 
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit omap4_secondary_init(unsigned int cpu)
 {
         /*
          * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
@@ -77,7 +77,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         spin_unlock(&boot_lock);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         static struct clockdomain *cpu1_clkdm;
         static bool booted;
@@ -165,7 +165,7 @@ static void __init wakeup_secondary(void)
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
-void __init smp_init_cpus(void)
+static void __init omap4_smp_init_cpus(void)
 {
         unsigned int i = 0, ncores = 1, cpu_id;
 
@@ -196,7 +196,7 @@ void __init smp_init_cpus(void)
         set_smp_cross_call(gic_raise_softirq);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
 
         /*
@@ -207,3 +207,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
                 scu_enable(scu_base);
         wakeup_secondary();
 }
+
+struct smp_operations omap4_smp_ops __initdata = {
+        .smp_init_cpus          = omap4_smp_init_cpus,
+        .smp_prepare_cpus       = omap4_smp_prepare_cpus,
+        .smp_secondary_init     = omap4_secondary_init,
+        .smp_boot_secondary     = omap4_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = omap4_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index ecaad7d371ee..b3275babf192 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -27,8 +27,8 @@
 
 #include <asm/hardware/gic.h>
 
-#include <mach/omap-wakeupgen.h>
-#include <mach/omap-secure.h>
+#include "omap-wakeupgen.h"
+#include "omap-secure.h"
 
 #include "soc.h"
 #include "omap4-sar-layout.h"
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h
index b0fd16f5c391..b0fd16f5c391 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/omap-wakeupgen.h
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 73c1440a8253..e1f289748c5d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -29,7 +29,7 @@
 #include <plat/omap-secure.h>
 #include <plat/mmc.h>
 
-#include <mach/omap-wakeupgen.h>
+#include "omap-wakeupgen.h"
 
 #include "soc.h"
 #include "common.h"
@@ -170,7 +170,10 @@ static int __init omap_l2_cache_init(void)
         /* Enable PL310 L2 Cache controller */
         omap_smc1(0x102, 0x1);
 
-        l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+        if (of_have_populated_dt())
+                l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+        else
+                l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 
         /*
          * Override default outer_cache.disable with a OMAP4
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/mach-omap2/omap4-keypad.h
index 20de0d5a7e77..20de0d5a7e77 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/mach-omap2/omap4-keypad.h
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6af64bbd9e1d..299ca2821ad1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3403,6 +3403,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 }
 
 /**
+ * omap_hwmod_fill_dma_resources - fill struct resource array with dma data
+ * @oh: struct omap_hwmod *
+ * @res: pointer to the array of struct resource to fill
+ *
+ * Fill the struct resource array @res with dma resource data from the
+ * omap_hwmod @oh.  Intended to be called by code that registers
+ * omap_devices.  See also omap_hwmod_count_resources().  Returns the
+ * number of array elements filled.
+ */
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res)
+{
+        int i, sdma_reqs_cnt;
+        int r = 0;
+
+        sdma_reqs_cnt = _count_sdma_reqs(oh);
+        for (i = 0; i < sdma_reqs_cnt; i++) {
+                (res + r)->name = (oh->sdma_reqs + i)->name;
+                (res + r)->start = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->end = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->flags = IORESOURCE_DMA;
+                r++;
+        }
+
+        return r;
+}
+
+/**
  * omap_hwmod_get_resource_byname - fetch IP block integration data by name
  * @oh: struct omap_hwmod * to operate on
  * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index e778ff4e1887..b5db6007c523 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -12,14 +12,15 @@
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <plat/omap_hwmod.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/mcspi.h>
 #include <plat/dmtimer.h>
-#include <plat/l3_2xxx.h>
-#include <plat/l4_2xxx.h>
+#include "l3_2xxx.h"
+#include "l4_2xxx.h"
 #include <plat/mmc.h>
 
 #include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index cc4ed9024372..c455e41b0237 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -12,15 +12,16 @@
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <plat/omap_hwmod.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/mcbsp.h>
-#include <plat/mcspi.h>
 #include <plat/dmtimer.h>
 #include <plat/mmc.h>
-#include <plat/l3_2xxx.h>
+#include "l3_2xxx.h"
 
 #include "soc.h"
 #include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index bea700e928e7..8851bbb6bb24 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -13,7 +13,7 @@
 #include <plat/serial.h>
 #include <plat/dma.h>
 #include <plat/common.h>
-#include <plat/hdq1w.h>
+#include "hdq1w.h"
 
 #include "omap_hwmod_common_data.h"
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index c83d6c517be4..1a1287d62648 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -15,8 +15,8 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
-#include <plat/l3_2xxx.h>
-#include <plat/l4_2xxx.h>
+#include "l3_2xxx.h"
+#include "l4_2xxx.h"
 
 #include "omap_hwmod_common_data.h"
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index d59a9ce40d2a..35dcdb66a4e0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -13,7 +13,7 @@
 #include <linux/platform_data/gpio-omap.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include "omap_hwmod_common_data.h"
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 22433cb2bec0..59d5c1cd316d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -17,9 +17,9 @@
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dma.h>
 #include <plat/mmc.h>
-#include <plat/mcspi.h>
 #include <plat/i2c.h>
 
 #include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 016429d89bb0..285777241d5a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -20,16 +20,16 @@
 #include <plat/omap_hwmod.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
-#include <plat/l3_3xxx.h>
-#include <plat/l4_3xxx.h>
+#include "l3_3xxx.h"
+#include "l4_3xxx.h"
 #include <plat/i2c.h>
 #include <plat/mmc.h>
-#include <plat/mcbsp.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
 #include <plat/iommu.h>
 
-#include <mach/am35xx.h>
+#include "am35xx.h"
 
 #include "soc.h"
 #include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e6b8d02d0b0e..ae0acaf506ed 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -25,8 +25,8 @@
 #include <plat/omap_hwmod.h>
 #include <plat/i2c.h>
 #include <plat/dma.h>
-#include <plat/mcspi.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index b7d8ead4b86a..88ff83a0942e 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -14,7 +14,7 @@
 #include <asm/memory.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include <mach/omap-secure.h>
+#include "omap-secure.h"
 
 #include "common.h"
 #include "omap44xx.h"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5214d5bfba27..810aa1a332e1 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -36,6 +36,7 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
@@ -394,6 +395,11 @@ static void __init omap4_timer_init(void)
         if (omap_rev() != OMAP4430_REV_ES1_0) {
                 int err;
 
+                if (of_have_populated_dt()) {
+                        twd_local_timer_of_register();
+                        return;
+                }
+
                 err = twd_local_timer_register(&twd_local_timer);
                 if (err)
                         pr_err("twd_local_timer_register failed %d\n", err);
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 89150b2435e5..136c64bc9028 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -28,7 +28,7 @@
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 
-#include <mach/am35xx.h>
+#include "am35xx.h"
 
 #include "mux.h"
 
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 0ac2caf15941..7283b7ed7de8 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -16,7 +16,7 @@
 
 #include <linux/err.h>
 
-#include <plat/voltage.h>
+#include <linux/platform_data/voltage-omap.h>
 
 #include "vc.h"
 #include "vp.h"
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index eaac83d1df6f..b5efc0fd31cb 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
         /*
          * Setup MBUS dram target info.
          */
-        orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
 }
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 410291c67666..3e07f52f2127 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -30,8 +30,8 @@
 #include <mach/bridge-regs.h>
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
-#include <plat/orion_nand.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/mtd-orion_nand.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
@@ -42,22 +42,12 @@
  ****************************************************************************/
 static struct map_desc orion5x_io_desc[] __initdata = {
         {
-                .virtual        = ORION5X_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) ORION5X_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
                 .length         = ORION5X_REGS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
-                .length         = ORION5X_PCIE_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = ORION5X_PCI_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
-                .length         = ORION5X_PCI_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
+                .virtual        = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
                 .length         = ORION5X_PCIE_WA_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index d75dcfa0f01c..e3629c063df2 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -27,6 +27,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 49a3fd630313..41fe2b1ff47c 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -24,7 +24,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/mtd-orion_nand.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index d470864b4e42..e533588880ff 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -34,6 +34,7 @@
 #include <asm/mach/pci.h>
 #include <asm/system_info.h>
 #include <mach/orion5x.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 #include "mpp.h"
 
@@ -700,7 +701,7 @@ static void __init dns323_init(void)
                  * Note: AFAIK, rev B1 needs the same treatement but I'll let
                  * somebody else test it.
                  */
-                writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
+                writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
                 break;
         }
 }
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 11a3c1e9801f..461fd69a10ae 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -13,27 +13,27 @@
 
 #include <mach/orion5x.h>
 
-#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE | 0x100)
+#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE + 0x100)
 
-#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE | 0x104)
+#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE + 0x104)
 
-#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE + 0x108)
 #define WDT_RESET_OUT_EN        0x0002
 
-#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
 
-#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE + 0x110)
 
-#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
+#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
 
 #define WDT_INT_REQ             0x0008
 
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
-#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE | 0x200)
+#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE + 0x200)
 
-#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE | 0x204)
+#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE + 0x204)
 
-#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE | 0x300)
-#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE | 0x300)
+#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE + 0x300)
+#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE + 0x300)
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
deleted file mode 100644
index a1d0b78decb1..000000000000
--- a/arch/arm/mach-orion5x/include/mach/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
deleted file mode 100644
index 1aa5d0a50a0b..000000000000
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include <mach/orion5x.h>
-#include <asm/sizes.h>
-
-#define IO_SPACE_LIMIT          SZ_2M
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE);
-}
-
-#define __io(a)                  __io(a)
-#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 683e085ce162..d265f5484a8e 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -31,31 +31,29 @@
  * fc000000     device bus mappings (cs0/cs1)
  *
  * virt         phys            size
- * fdd00000     f1000000        1M      on-chip peripheral registers
- * fde00000     f2000000        1M      PCIe I/O space
- * fdf00000     f2100000        1M      PCI I/O space
- * fe000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
+ * fe000000     f1000000        1M      on-chip peripheral registers
+ * fee00000     f2000000        64K     PCIe I/O space
+ * fee10000     f2100000        64K     PCI I/O space
+ * fd000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
  ****************************************************************************/
 #define ORION5X_REGS_PHYS_BASE          0xf1000000
-#define ORION5X_REGS_VIRT_BASE          0xfdd00000
+#define ORION5X_REGS_VIRT_BASE          IOMEM(0xfe000000)
 #define ORION5X_REGS_SIZE               SZ_1M
 
 #define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
-#define ORION5X_PCIE_IO_VIRT_BASE       0xfde00000
 #define ORION5X_PCIE_IO_BUS_BASE        0x00000000
-#define ORION5X_PCIE_IO_SIZE            SZ_1M
+#define ORION5X_PCIE_IO_SIZE            SZ_64K
 
 #define ORION5X_PCI_IO_PHYS_BASE        0xf2100000
-#define ORION5X_PCI_IO_VIRT_BASE        0xfdf00000
-#define ORION5X_PCI_IO_BUS_BASE         0x00100000
-#define ORION5X_PCI_IO_SIZE             SZ_1M
+#define ORION5X_PCI_IO_BUS_BASE         0x00010000
+#define ORION5X_PCI_IO_SIZE             SZ_64K
 
 #define ORION5X_SRAM_PHYS_BASE          (0xf2200000)
 #define ORION5X_SRAM_SIZE               SZ_8K
 
 /* Relevant only for Orion-1/Orion-NAS */
 #define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
-#define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
+#define ORION5X_PCIE_WA_VIRT_BASE       IOMEM(0xfd000000)
 #define ORION5X_PCIE_WA_SIZE            SZ_16M
 
 #define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
@@ -68,42 +66,42 @@
  * Orion Registers Map
  ******************************************************************************/
 
-#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
-#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE | 0x1500)
-#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
-#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
-#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x00000)
+#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE + 0x1500)
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE + 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE + 0x10000)
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE + (x))
 #define  GPIO_VIRT_BASE                 ORION5X_DEV_BUS_REG(0x0100)
-#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
-#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
 
-#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
-#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x20000)
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE + 0x20000)
+#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x20000)
 
-#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x30000)
 
-#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x40000)
 
-#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
-#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x50000)
 
-#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x60900)
-#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x60900)
+#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x60900)
+#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x60900)
 
-#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
-#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x70000)
 
-#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
-#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x80000)
 
-#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x90000)
+#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x90000)
 
-#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
-#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0xa0000)
 
 /*******************************************************************************
  * Device Bus Registers
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 17da7091d310..30a192b9c517 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -12,7 +12,9 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
+#include <plat/orion-gpio.h>
 #include <plat/irq.h>
 
 static int __initdata gpio0_irqs[4] = {
@@ -24,11 +26,11 @@ static int __initdata gpio0_irqs[4] = {
 
 void __init orion5x_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
+        orion_irq_init(0, MAIN_IRQ_MASK);
 
         /*
          * Initialize gpiolib for GPIOs 0-31.
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0,
                         IRQ_ORION5X_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 1e458efafb9a..f1ae10ae5bd4 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -24,7 +24,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/mtd-orion_nand.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 0180c393c711..3506f16c0bf2 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -25,6 +25,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/orion5x.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index cb19e1661bb3..cd50e328db2a 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -38,7 +38,7 @@
 /*****************************************************************************
  * PCIe controller
  ****************************************************************************/
-#define PCIE_BASE       ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
+#define PCIE_BASE       (ORION5X_PCIE_VIRT_BASE)
 
 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
 {
@@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
                 return PCIBIOS_DEVICE_NOT_FOUND;
         }
 
-        ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
+        ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
                                     bus, devfn, where, size, val);
 
         return ret;
@@ -162,35 +162,25 @@ static int __init pcie_setup(struct pci_sys_data *sys)
                 pcie_ops.read = pcie_rd_conf_wa;
         }
 
+        pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
+
         /*
          * Request resources.
          */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
         if (!res)
                 panic("pcie_setup unable to alloc resources");
 
         /*
-         * IORESOURCE_IO
-         */
-        sys->io_offset = 0;
-        res[0].name = "PCIe I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = ORION5X_PCIE_IO_BUS_BASE;
-        res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCIe IO resource failed\n");
-        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-
-        /*
          * IORESOURCE_MEM
          */
-        res[1].name = "PCIe Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
-        res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
+        res->name = "PCIe Memory Space";
+        res->flags = IORESOURCE_MEM;
+        res->start = ORION5X_PCIE_MEM_PHYS_BASE;
+        res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
+        if (request_resource(&iomem_resource, res))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
 
         return 1;
 }
@@ -198,7 +188,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
 /*****************************************************************************
  * PCI controller
  ****************************************************************************/
-#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE | (x))
+#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE + (x))
 #define PCI_MODE                ORION5X_PCI_REG(0xd00)
 #define PCI_CMD                 ORION5X_PCI_REG(0xc00)
 #define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)
@@ -489,35 +479,25 @@ static int __init pci_setup(struct pci_sys_data *sys)
          */
         orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
 
+        pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
+
         /*
          * Request resources
          */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
         if (!res)
                 panic("pci_setup unable to alloc resources");
 
         /*
-         * IORESOURCE_IO
-         */
-        sys->io_offset = 0;
-        res[0].name = "PCI I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = ORION5X_PCI_IO_BUS_BASE;
-        res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCI IO resource failed\n");
-        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-
-        /*
          * IORESOURCE_MEM
          */
-        res[1].name = "PCI Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
-        res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
+        res->name = "PCI Memory Space";
+        res->flags = IORESOURCE_MEM;
+        res->start = ORION5X_PCI_MEM_PHYS_BASE;
+        res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
+        if (request_resource(&iomem_resource, res))
                 panic("Request PCI Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
new file mode 100644
index 000000000000..868796f8085c
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -0,0 +1,14 @@
+config ARCH_PICOXCELL
+        bool "Picochip PicoXcell" if ARCH_MULTI_V6
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_PATCH_PHYS_VIRT
+        select ARM_VIC
+        select CPU_V6K
+        select DW_APB_TIMER
+        select DW_APB_TIMER_OF
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select HAVE_TCM
+        select NO_IOPORT
+        select SPARSE_IRQ
+        select USE_OF
diff --git a/arch/arm/mach-picoxcell/Makefile.boot b/arch/arm/mach-picoxcell/Makefile.boot
deleted file mode 100644
index b3271754e9fd..000000000000
--- a/arch/arm/mach-picoxcell/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 8f9a0b47a7fa..f6c0849af5e9 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -20,14 +20,15 @@
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
 
-#include <mach/map.h>
-#include <mach/picoxcell_soc.h>
-
 #include "common.h"
 
-#define WDT_CTRL_REG_EN_MASK    (1 << 0)
-#define WDT_CTRL_REG_OFFS       (0x00)
-#define WDT_TIMEOUT_REG_OFFS    (0x04)
+#define PHYS_TO_IO(x)                   (((x) & 0x00ffffff) | 0xfe000000)
+#define PICOXCELL_PERIPH_BASE           0x80000000
+#define PICOXCELL_PERIPH_LENGTH         SZ_4M
+
+#define WDT_CTRL_REG_EN_MASK            (1 << 0)
+#define WDT_CTRL_REG_OFFS               (0x00)
+#define WDT_TIMEOUT_REG_OFFS            (0x04)
 static void __iomem *wdt_regs;
 
 /*
diff --git a/arch/arm/mach-picoxcell/include/mach/gpio.h b/arch/arm/mach-picoxcell/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h b/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
deleted file mode 100644
index 5566fc88ddbc..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This file contains the hardware definitions of the picoXcell SoC devices.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __PICOXCELL_SOC_H__
-#define __PICOXCELL_SOC_H__
-
-#define PICOXCELL_UART1_BASE            0x80230000
-#define PICOXCELL_PERIPH_BASE           0x80000000
-#define PICOXCELL_PERIPH_LENGTH         SZ_4M
-#define PICOXCELL_VIC0_BASE             0x80060000
-#define PICOXCELL_VIC1_BASE             0x80064000
-
-#endif /* __PICOXCELL_SOC_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/timex.h b/arch/arm/mach-picoxcell/include/mach/timex.h
deleted file mode 100644
index 6c540a69f405..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __TIMEX_H__
-#define __TIMEX_H__
-
-/* Bogus value to allow the kernel to compile. */
-#define CLOCK_TICK_RATE         1000000
-
-#endif /* __TIMEX_H__ */
-
diff --git a/arch/arm/mach-picoxcell/include/mach/uncompress.h b/arch/arm/mach-picoxcell/include/mach/uncompress.h
deleted file mode 100644
index b60b19d1d739..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/uncompress.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define putc(c)
-#define flush()
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pnx4008/Makefile b/arch/arm/mach-pnx4008/Makefile
deleted file mode 100644
index 777564c90a12..000000000000
--- a/arch/arm/mach-pnx4008/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y                   := core.o irq.o time.o clock.o gpio.o serial.o dma.o i2c.o
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
-
-# Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
-
diff --git a/arch/arm/mach-pnx4008/Makefile.boot b/arch/arm/mach-pnx4008/Makefile.boot
deleted file mode 100644
index 9fa19baa7f2e..000000000000
--- a/arch/arm/mach-pnx4008/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y           += 0x80008000
-params_phys-y           := 0x80000100
-initrd_phys-y           := 0x80800000
-
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
deleted file mode 100644
index a4a3819c96cb..000000000000
--- a/arch/arm/mach-pnx4008/clock.c
+++ /dev/null
@@ -1,1001 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.c
- *
- * Clock control driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- * Generic clock management functions are partially based on:
- *  linux/arch/arm/mach-omap/clock.c
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/hardware.h>
-#include <mach/clock.h>
-#include "clock.h"
-
-/*forward declaration*/
-static struct clk per_ck;
-static struct clk hclk_ck;
-static struct clk ck_1MHz;
-static struct clk ck_13MHz;
-static struct clk ck_pll1;
-static int local_set_rate(struct clk *clk, u32 rate);
-
-static inline void clock_lock(void)
-{
-        local_irq_disable();
-}
-
-static inline void clock_unlock(void)
-{
-        local_irq_enable();
-}
-
-static void propagate_rate(struct clk *clk)
-{
-        struct clk *tmp_clk;
-
-        tmp_clk = clk;
-        while (tmp_clk->propagate_next) {
-                tmp_clk = tmp_clk->propagate_next;
-                local_set_rate(tmp_clk, tmp_clk->user_rate);
-        }
-}
-
-static void clk_reg_disable(struct clk *clk)
-{
-        if (clk->enable_reg)
-                __raw_writel(__raw_readl(clk->enable_reg) &
-                             ~(1 << clk->enable_shift), clk->enable_reg);
-}
-
-static int clk_reg_enable(struct clk *clk)
-{
-        if (clk->enable_reg)
-                __raw_writel(__raw_readl(clk->enable_reg) |
-                             (1 << clk->enable_shift), clk->enable_reg);
-        return 0;
-}
-
-static inline void clk_reg_disable1(struct clk *clk)
-{
-        if (clk->enable_reg1)
-                __raw_writel(__raw_readl(clk->enable_reg1) &
-                             ~(1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static inline void clk_reg_enable1(struct clk *clk)
-{
-        if (clk->enable_reg1)
-                __raw_writel(__raw_readl(clk->enable_reg1) |
-                             (1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static int clk_wait_for_pll_lock(struct clk *clk)
-{
-        int i;
-        i = 0;
-        while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ;     /*wait for PLL to lock */
-
-        if (!(__raw_readl(clk->scale_reg) & 1)) {
-                printk(KERN_ERR
-                       "%s ERROR: failed to lock, scale reg data: %x\n",
-                       clk->name, __raw_readl(clk->scale_reg));
-                return -1;
-        }
-        return 0;
-}
-
-static int switch_to_dirty_13mhz(struct clk *clk)
-{
-        int i;
-        int ret;
-        u32 tmp_reg;
-
-        ret = 0;
-
-        if (!clk->rate)
-                clk_reg_enable1(clk);
-
-        tmp_reg = __raw_readl(clk->parent_switch_reg);
-        /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
-        if (!(tmp_reg & 1)) {
-                tmp_reg |= (1 << 1);    /* Trigger switch to 13'MHz (dirty) clock */
-                __raw_writel(tmp_reg, clk->parent_switch_reg);
-                i = 0;
-                while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ;     /*wait for 13'MHz selection status */
-
-                if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
-                        printk(KERN_ERR
-                               "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
-                               clk->name, __raw_readl(clk->parent_switch_reg));
-                        ret = -1;
-                }
-        }
-
-        if (!clk->rate)
-                clk_reg_disable1(clk);
-
-        return ret;
-}
-
-static int switch_to_clean_13mhz(struct clk *clk)
-{
-        int i;
-        int ret;
-        u32 tmp_reg;
-
-        ret = 0;
-
-        if (!clk->rate)
-                clk_reg_enable1(clk);
-
-        tmp_reg = __raw_readl(clk->parent_switch_reg);
-        /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
-        if (tmp_reg & 1) {
-                tmp_reg &= ~(1 << 1);   /* Trigger switch to 13MHz (clean) clock */
-                __raw_writel(tmp_reg, clk->parent_switch_reg);
-                i = 0;
-                while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ;      /*wait for 13MHz selection status */
-
-                if (__raw_readl(clk->parent_switch_reg) & 1) {
-                        printk(KERN_ERR
-                               "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
-                               clk->name, __raw_readl(clk->parent_switch_reg));
-                        ret = -1;
-                }
-        }
-
-        if (!clk->rate)
-                clk_reg_disable1(clk);
-
-        return ret;
-}
-
-static int set_13MHz_parent(struct clk *clk, struct clk *parent)
-{
-        int ret = -EINVAL;
-
-        if (parent == &ck_13MHz)
-                ret = switch_to_clean_13mhz(clk);
-        else if (parent == &ck_pll1)
-                ret = switch_to_dirty_13mhz(clk);
-
-        return ret;
-}
-
-#define PLL160_MIN_FCCO 156000
-#define PLL160_MAX_FCCO 320000
-
-/*
- * Calculate pll160 settings.
- * Possible input: up to 320MHz with step of clk->parent->rate.
- * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
- * Ignored paths: "feedback" (bit 13 set), "div-by-N".
- * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
- * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
- * Please refer to PNX4008 IC manual for details.
- */
-
-static int pll160_set_rate(struct clk *clk, u32 rate)
-{
-        u32 tmp_reg, tmp_m, tmp_2p, i;
-        u32 parent_rate;
-        int ret = -EINVAL;
-
-        parent_rate = clk->parent->rate;
-
-        if (!parent_rate)
-                goto out;
-
-        /* set direct run for ARM or disable output for others  */
-        clk_reg_disable(clk);
-
-        /* disable source input as well (ignored for ARM) */
-        clk_reg_disable1(clk);
-
-        tmp_reg = __raw_readl(clk->scale_reg);
-        tmp_reg &= ~0x1ffff;    /*clear all settings, power down */
-        __raw_writel(tmp_reg, clk->scale_reg);
-
-        rate -= rate % parent_rate;     /*round down the input */
-
-        if (rate > PLL160_MAX_FCCO)
-                rate = PLL160_MAX_FCCO;
-
-        if (!rate) {
-                clk->rate = 0;
-                ret = 0;
-                goto out;
-        }
-
-        clk_reg_enable1(clk);
-        tmp_reg = __raw_readl(clk->scale_reg);
-
-        if (rate == parent_rate) {
-                /*enter direct bypass mode */
-                tmp_reg |= ((1 << 14) | (1 << 15));
-                __raw_writel(tmp_reg, clk->scale_reg);
-                clk->rate = parent_rate;
-                clk_reg_enable(clk);
-                ret = 0;
-                goto out;
-        }
-
-        i = 0;
-        for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
-                if (rate * tmp_2p >= PLL160_MIN_FCCO)
-                        break;
-                i++;
-        }
-
-        if (tmp_2p > 1)
-                tmp_reg |= ((i - 1) << 11);
-        else
-                tmp_reg |= (1 << 14);   /*direct mode, no divide */
-
-        tmp_m = rate * tmp_2p;
-        tmp_m /= parent_rate;
-
-        tmp_reg |= (tmp_m - 1) << 1;    /*calculate M */
-        tmp_reg |= (1 << 16);   /*power up PLL */
-        __raw_writel(tmp_reg, clk->scale_reg);
-
-        if (clk_wait_for_pll_lock(clk) < 0) {
-                clk_reg_disable(clk);
-                clk_reg_disable1(clk);
-
-                tmp_reg = __raw_readl(clk->scale_reg);
-                tmp_reg &= ~0x1ffff;    /*clear all settings, power down */
-                __raw_writel(tmp_reg, clk->scale_reg);
-                clk->rate = 0;
-                ret = -EFAULT;
-                goto out;
-        }
-
-        clk->rate = (tmp_m * parent_rate) / tmp_2p;
-
-        if (clk->flags & RATE_PROPAGATES)
-                propagate_rate(clk);
-
-        clk_reg_enable(clk);
-        ret = 0;
-
-out:
-        return ret;
-}
-
-/*configure PER_CLK*/
-static int per_clk_set_rate(struct clk *clk, u32 rate)
-{
-        u32 tmp;
-
-        tmp = __raw_readl(clk->scale_reg);
-        tmp &= ~(0x1f << 2);
-        tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
-        __raw_writel(tmp, clk->scale_reg);
-        clk->rate = rate;
-        return 0;
-}
-
-/*configure HCLK*/
-static int hclk_set_rate(struct clk *clk, u32 rate)
-{
-        u32 tmp;
-        tmp = __raw_readl(clk->scale_reg);
-        tmp = tmp & ~0x3;
-        switch (rate) {
-        case 1:
-                break;
-        case 2:
-                tmp |= 1;
-                break;
-        case 4:
-                tmp |= 2;
-                break;
-        }
-
-        __raw_writel(tmp, clk->scale_reg);
-        clk->rate = rate;
-        return 0;
-}
-
-static u32 hclk_round_rate(struct clk *clk, u32 rate)
-{
-        switch (rate) {
-        case 1:
-        case 4:
-                return rate;
-        }
-        return 2;
-}
-
-static u32 per_clk_round_rate(struct clk *clk, u32 rate)
-{
-        return CLK_RATE_13MHZ;
-}
-
-static int on_off_set_rate(struct clk *clk, u32 rate)
-{
-        if (rate) {
-                clk_reg_enable(clk);
-                clk->rate = 1;
-        } else {
-                clk_reg_disable(clk);
-                clk->rate = 0;
-        }
-        return 0;
-}
-
-static int on_off_inv_set_rate(struct clk *clk, u32 rate)
-{
-        if (rate) {
-                clk_reg_disable(clk);   /*enable bit is inverted */
-                clk->rate = 1;
-        } else {
-                clk_reg_enable(clk);
-                clk->rate = 0;
-        }
-        return 0;
-}
-
-static u32 on_off_round_rate(struct clk *clk, u32 rate)
-{
-        return (rate ? 1 : 0);
-}
-
-static u32 pll4_round_rate(struct clk *clk, u32 rate)
-{
-        if (rate > CLK_RATE_208MHZ)
-                rate = CLK_RATE_208MHZ;
-        if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
-                rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
-        return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
-}
-
-static u32 pll3_round_rate(struct clk *clk, u32 rate)
-{
-        if (rate > CLK_RATE_208MHZ)
-                rate = CLK_RATE_208MHZ;
-        return (rate - rate % CLK_RATE_13MHZ);
-}
-
-static u32 pll5_round_rate(struct clk *clk, u32 rate)
-{
-        return (rate ? CLK_RATE_48MHZ : 0);
-}
-
-static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
-{
-        return (rate ? CLK_RATE_13MHZ : 0);
-}
-
-static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
-{
-        if (rate) {
-                clk_reg_disable(clk);   /*enable bit is inverted */
-                udelay(500);
-                clk->rate = CLK_RATE_13MHZ;
-                ck_1MHz.rate = CLK_RATE_1MHZ;
-        } else {
-                clk_reg_enable(clk);
-                clk->rate = 0;
-                ck_1MHz.rate = 0;
-        }
-        return 0;
-}
-
-static int pll1_set_rate(struct clk *clk, u32 rate)
-{
-#if 0 /* doesn't work on some boards, probably a HW BUG */
-        if (rate) {
-                clk_reg_disable(clk);   /*enable bit is inverted */
-                if (!clk_wait_for_pll_lock(clk)) {
-                        clk->rate = CLK_RATE_13MHZ;
-                } else {
-                        clk_reg_enable(clk);
-                        clk->rate = 0;
-                }
-
-        } else {
-                clk_reg_enable(clk);
-                clk->rate = 0;
-        }
-#endif
-        return 0;
-}
-
-/* Clock sources */
-
-static struct clk osc_13MHz = {
-        .name = "osc_13MHz",
-        .flags = FIXED_RATE,
-        .rate = CLK_RATE_13MHZ,
-};
-
-static struct clk ck_13MHz = {
-        .name = "ck_13MHz",
-        .parent = &osc_13MHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &ck_13MHz_round_rate,
-        .set_rate = &ck_13MHz_set_rate,
-        .enable_reg = OSC13CTRL_REG,
-        .enable_shift = 0,
-        .rate = CLK_RATE_13MHZ,
-};
-
-static struct clk osc_32KHz = {
-        .name = "osc_32KHz",
-        .flags = FIXED_RATE,
-        .rate = CLK_RATE_32KHZ,
-};
-
-/*attached to PLL5*/
-static struct clk ck_1MHz = {
-        .name = "ck_1MHz",
-        .flags = FIXED_RATE | PARENT_SET_RATE,
-        .parent = &ck_13MHz,
-};
-
-/* PLL1 (397) - provides 13' MHz clock */
-static struct clk ck_pll1 = {
-        .name = "ck_pll1",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &ck_13MHz_round_rate,
-        .set_rate = &pll1_set_rate,
-        .enable_reg = PLLCTRL_REG,
-        .enable_shift = 1,
-        .scale_reg = PLLCTRL_REG,
-        .rate = CLK_RATE_13MHZ,
-};
-
-/* CPU/Bus PLL */
-static struct clk ck_pll4 = {
-        .name = "ck_pll4",
-        .parent = &ck_pll1,
-        .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
-        .propagate_next = &per_ck,
-        .round_rate = &pll4_round_rate,
-        .set_rate = &pll160_set_rate,
-        .rate = CLK_RATE_208MHZ,
-        .scale_reg = HCLKPLLCTRL_REG,
-        .enable_reg = PWRCTRL_REG,
-        .enable_shift = 2,
-        .parent_switch_reg = SYSCLKCTRL_REG,
-        .set_parent = &set_13MHz_parent,
-};
-
-/* USB PLL */
-static struct clk ck_pll5 = {
-        .name = "ck_pll5",
-        .parent = &ck_1MHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &pll5_round_rate,
-        .set_rate = &pll160_set_rate,
-        .scale_reg = USBCTRL_REG,
-        .enable_reg = USBCTRL_REG,
-        .enable_shift = 18,
-        .enable_reg1 = USBCTRL_REG,
-        .enable_shift1 = 17,
-};
-
-/* XPERTTeak DSP PLL */
-static struct clk ck_pll3 = {
-        .name = "ck_pll3",
-        .parent = &ck_pll1,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &pll3_round_rate,
-        .set_rate = &pll160_set_rate,
-        .scale_reg = DSPPLLCTRL_REG,
-        .enable_reg = DSPCLKCTRL_REG,
-        .enable_shift = 3,
-        .enable_reg1 = DSPCLKCTRL_REG,
-        .enable_shift1 = 2,
-        .parent_switch_reg = DSPCLKCTRL_REG,
-        .set_parent = &set_13MHz_parent,
-};
-
-static struct clk hclk_ck = {
-        .name = "hclk_ck",
-        .parent = &ck_pll4,
-        .flags = PARENT_SET_RATE,
-        .set_rate = &hclk_set_rate,
-        .round_rate = &hclk_round_rate,
-        .scale_reg = HCLKDIVCTRL_REG,
-        .rate = 2,
-        .user_rate = 2,
-};
-
-static struct clk per_ck = {
-        .name = "per_ck",
-        .parent = &ck_pll4,
-        .flags = FIXED_RATE,
-        .propagate_next = &hclk_ck,
-        .set_rate = &per_clk_set_rate,
-        .round_rate = &per_clk_round_rate,
-        .scale_reg = HCLKDIVCTRL_REG,
-        .rate = CLK_RATE_13MHZ,
-        .user_rate = CLK_RATE_13MHZ,
-};
-
-static struct clk m2hclk_ck = {
-        .name = "m2hclk_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_inv_set_rate,
-        .rate = 1,
-        .enable_shift = 6,
-        .enable_reg = PWRCTRL_REG,
-};
-
-static struct clk vfp9_ck = {
-        .name = "vfp9_ck",
-        .parent = &ck_pll4,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .rate = 1,
-        .enable_shift = 4,
-        .enable_reg = VFP9CLKCTRL_REG,
-};
-
-static struct clk keyscan_ck = {
-        .name = "keyscan_ck",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = KEYCLKCTRL_REG,
-};
-
-static struct clk touch_ck = {
-        .name = "touch_ck",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = TSCLKCTRL_REG,
-};
-
-static struct clk pwm1_ck = {
-        .name = "pwm1_ck",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk pwm2_ck = {
-        .name = "pwm2_ck",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 2,
-        .enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk jpeg_ck = {
-        .name = "jpeg_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = JPEGCLKCTRL_REG,
-};
-
-static struct clk ms_ck = {
-        .name = "ms_ck",
-        .parent = &ck_pll4,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 5,
-        .enable_reg = MSCTRL_REG,
-};
-
-static struct clk dum_ck = {
-        .name = "dum_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = DUMCLKCTRL_REG,
-};
-
-static struct clk flash_ck = {
-        .name = "flash_ck",
-        .parent = &hclk_ck,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 1,      /* Only MLC clock supported */
-        .enable_reg = FLASHCLKCTRL_REG,
-};
-
-static struct clk i2c0_ck = {
-        .name = "i2c0_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
-        .enable_shift = 0,
-        .enable_reg = I2CCLKCTRL_REG,
-        .rate = 13000000,
-        .enable = clk_reg_enable,
-        .disable = clk_reg_disable,
-};
-
-static struct clk i2c1_ck = {
-        .name = "i2c1_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
-        .enable_shift = 1,
-        .enable_reg = I2CCLKCTRL_REG,
-        .rate = 13000000,
-        .enable = clk_reg_enable,
-        .disable = clk_reg_disable,
-};
-
-static struct clk i2c2_ck = {
-        .name = "i2c2_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
-        .enable_shift = 2,
-        .enable_reg = USB_OTG_CLKCTRL_REG,
-        .rate = 13000000,
-        .enable = clk_reg_enable,
-        .disable = clk_reg_disable,
-};
-
-static struct clk spi0_ck = {
-        .name = "spi0_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = SPICTRL_REG,
-};
-
-static struct clk spi1_ck = {
-        .name = "spi1_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 4,
-        .enable_reg = SPICTRL_REG,
-};
-
-static struct clk dma_ck = {
-        .name = "dma_ck",
-        .parent = &hclk_ck,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = DMACLKCTRL_REG,
-};
-
-static struct clk uart3_ck = {
-        .name = "uart3_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .rate = 1,
-        .enable_shift = 0,
-        .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart4_ck = {
-        .name = "uart4_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 1,
-        .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart5_ck = {
-        .name = "uart5_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .rate = 1,
-        .enable_shift = 2,
-        .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart6_ck = {
-        .name = "uart6_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 3,
-        .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk wdt_ck = {
-        .name = "wdt_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .enable_shift = 0,
-        .enable_reg = TIMCLKCTRL_REG,
-        .enable = clk_reg_enable,
-        .disable = clk_reg_disable,
-};
-
-/* These clocks are visible outside this module
- * and can be initialized
- */
-static struct clk *onchip_clks[] __initdata = {
-        &ck_13MHz,
-        &ck_pll1,
-        &ck_pll4,
-        &ck_pll5,
-        &ck_pll3,
-        &vfp9_ck,
-        &m2hclk_ck,
-        &hclk_ck,
-        &dma_ck,
-        &flash_ck,
-        &dum_ck,
-        &keyscan_ck,
-        &pwm1_ck,
-        &pwm2_ck,
-        &jpeg_ck,
-        &ms_ck,
-        &touch_ck,
-        &i2c0_ck,
-        &i2c1_ck,
-        &i2c2_ck,
-        &spi0_ck,
-        &spi1_ck,
-        &uart3_ck,
-        &uart4_ck,
-        &uart5_ck,
-        &uart6_ck,
-        &wdt_ck,
-};
-
-static struct clk_lookup onchip_clkreg[] = {
-        { .clk = &ck_13MHz,     .con_id = "ck_13MHz"    },
-        { .clk = &ck_pll1,      .con_id = "ck_pll1"     },
-        { .clk = &ck_pll4,      .con_id = "ck_pll4"     },
-        { .clk = &ck_pll5,      .con_id = "ck_pll5"     },
-        { .clk = &ck_pll3,      .con_id = "ck_pll3"     },
-        { .clk = &vfp9_ck,      .con_id = "vfp9_ck"     },
-        { .clk = &m2hclk_ck,    .con_id = "m2hclk_ck"   },
-        { .clk = &hclk_ck,      .con_id = "hclk_ck"     },
-        { .clk = &dma_ck,       .con_id = "dma_ck"      },
-        { .clk = &flash_ck,     .con_id = "flash_ck"    },
-        { .clk = &dum_ck,       .con_id = "dum_ck"      },
-        { .clk = &keyscan_ck,   .con_id = "keyscan_ck"  },
-        { .clk = &pwm1_ck,      .con_id = "pwm1_ck"     },
-        { .clk = &pwm2_ck,      .con_id = "pwm2_ck"     },
-        { .clk = &jpeg_ck,      .con_id = "jpeg_ck"     },
-        { .clk = &ms_ck,        .con_id = "ms_ck"       },
-        { .clk = &touch_ck,     .con_id = "touch_ck"    },
-        { .clk = &i2c0_ck,      .dev_id = "pnx-i2c.0"   },
-        { .clk = &i2c1_ck,      .dev_id = "pnx-i2c.1"   },
-        { .clk = &i2c2_ck,      .dev_id = "pnx-i2c.2"   },
-        { .clk = &spi0_ck,      .con_id = "spi0_ck"     },
-        { .clk = &spi1_ck,      .con_id = "spi1_ck"     },
-        { .clk = &uart3_ck,     .con_id = "uart3_ck"    },
-        { .clk = &uart4_ck,     .con_id = "uart4_ck"    },
-        { .clk = &uart5_ck,     .con_id = "uart5_ck"    },
-        { .clk = &uart6_ck,     .con_id = "uart6_ck"    },
-        { .clk = &wdt_ck,       .dev_id = "pnx4008-watchdog" },
-};
-
-static void local_clk_disable(struct clk *clk)
-{
-        if (WARN_ON(clk->usecount == 0))
-                return;
-
-        if (!(--clk->usecount)) {
-                if (clk->disable)
-                        clk->disable(clk);
-                else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
-                        clk->set_rate(clk, 0);
-                if (clk->parent)
-                        local_clk_disable(clk->parent);
-        }
-}
-
-static int local_clk_enable(struct clk *clk)
-{
-        int ret = 0;
-
-        if (clk->usecount == 0) {
-                if (clk->parent) {
-                        ret = local_clk_enable(clk->parent);
-                        if (ret != 0)
-                                goto out;
-                }
-
-                if (clk->enable)
-                        ret = clk->enable(clk);
-                else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
-                            && clk->user_rate)
-                        ret = clk->set_rate(clk, clk->user_rate);
-
-                if (ret != 0 && clk->parent) {
-                        local_clk_disable(clk->parent);
-                        goto out;
-                }
-
-                clk->usecount++;
-        }
-out:
-        return ret;
-}
-
-static int local_set_rate(struct clk *clk, u32 rate)
-{
-        int ret = -EINVAL;
-        if (clk->set_rate) {
-
-                if (clk->user_rate == clk->rate && clk->parent->rate) {
-                        /* if clock enabled or rate not set */
-                        clk->user_rate = clk->round_rate(clk, rate);
-                        ret = clk->set_rate(clk, clk->user_rate);
-                } else
-                        clk->user_rate = clk->round_rate(clk, rate);
-                ret = 0;
-        }
-        return ret;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        int ret = -EINVAL;
-
-        if (clk->flags & FIXED_RATE)
-                goto out;
-
-        clock_lock();
-        if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
-
-                clk->user_rate = clk->round_rate(clk, rate);
-                /* parent clock needs to be refreshed
-                   for the setting to take effect */
-        } else {
-                ret = local_set_rate(clk, rate);
-        }
-        ret = 0;
-        clock_unlock();
-
-out:
-        return ret;
-}
-
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long ret;
-        clock_lock();
-        ret = clk->rate;
-        clock_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_enable(struct clk *clk)
-{
-        int ret;
-
-        clock_lock();
-        ret = local_clk_enable(clk);
-        clock_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-        clock_lock();
-        local_clk_disable(clk);
-        clock_unlock();
-}
-
-EXPORT_SYMBOL(clk_disable);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        long ret;
-        clock_lock();
-        if (clk->round_rate)
-                ret = clk->round_rate(clk, rate);
-        else
-                ret = clk->rate;
-        clock_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int ret = -ENODEV;
-        if (!clk->set_parent)
-                goto out;
-
-        clock_lock();
-        ret = clk->set_parent(clk, parent);
-        if (!ret)
-                clk->parent = parent;
-        clock_unlock();
-
-out:
-        return ret;
-}
-
-EXPORT_SYMBOL(clk_set_parent);
-
-static int __init clk_init(void)
-{
-        struct clk **clkp;
-
-        /* Disable autoclocking, as it doesn't seem to work */
-        __raw_writel(0xff, AUTOCLK_CTRL);
-
-        for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-             clkp++) {
-                struct clk *clk = *clkp;
-                if (clk->flags & NEEDS_INITIALIZATION) {
-                        if (clk->set_rate) {
-                                clk->user_rate = clk->rate;
-                                local_set_rate(clk, clk->user_rate);
-                                if (clk->set_parent)
-                                        clk->set_parent(clk, clk->parent);
-                        }
-                        if (clk->enable && clk->usecount)
-                                clk->enable(clk);
-                        if (clk->disable && !clk->usecount)
-                                clk->disable(clk);
-                }
-                pr_debug("%s: clock %s, rate %ld\n",
-                        __func__, clk->name, clk->rate);
-        }
-
-        local_clk_enable(&ck_pll4);
-
-        /* if ck_13MHz is not used, disable it. */
-        if (ck_13MHz.usecount == 0)
-                local_clk_disable(&ck_13MHz);
-
-        /* Disable autoclocking */
-        __raw_writeb(0xff, AUTOCLK_CTRL);
-
-        clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
-
-        return 0;
-}
-
-arch_initcall(clk_init);
diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h
deleted file mode 100644
index 39720d6c0d01..000000000000
--- a/arch/arm/mach-pnx4008/clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.h
- *
- * Clock control driver for PNX4008 - internal header file
- *
- * Author: Vitaly Wool <source@mvista.com>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ARCH_ARM_PNX4008_CLOCK_H__
-#define __ARCH_ARM_PNX4008_CLOCK_H__
-
-struct clk {
-        const char *name;
-        struct clk *parent;
-        struct clk *propagate_next;
-        u32 rate;
-        u32 user_rate;
-        s8 usecount;
-        u32 flags;
-        u32 scale_reg;
-        u8 enable_shift;
-        u32 enable_reg;
-        u8 enable_shift1;
-        u32 enable_reg1;
-        u32 parent_switch_reg;
-        u32(*round_rate) (struct clk *, u32);
-        int (*set_rate) (struct clk *, u32);
-        int (*set_parent) (struct clk * clk, struct clk * parent);
-        int (*enable)(struct clk *);
-        void (*disable)(struct clk *);
-};
-
-/* Flags */
-#define RATE_PROPAGATES      (1<<0)
-#define NEEDS_INITIALIZATION (1<<1)
-#define PARENT_SET_RATE      (1<<2)
-#define FIXED_RATE           (1<<3)
-
-#endif
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
deleted file mode 100644
index a00d2f1254ed..000000000000
--- a/arch/arm/mach-pnx4008/core.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/core.c
- *
- * PNX4008 core startup code
- *
- * Authors: Vitaly Wool, Dmitry Chigirev,
- * Grigory Tolstolytkin, Dmitry Pervushin <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/serial_8250.h>
-#include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/system_misc.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include <mach/irq.h>
-#include <mach/clock.h>
-#include <mach/dma.h>
-
-struct resource spipnx_0_resources[] = {
-        {
-                .start = PNX4008_SPI1_BASE,
-                .end = PNX4008_SPI1_BASE + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = PER_SPI1_REC_XMIT,
-                .flags = IORESOURCE_DMA,
-        }, {
-                .start = SPI1_INT,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .flags = 0,
-        },
-};
-
-struct resource spipnx_1_resources[] = {
-        {
-                .start = PNX4008_SPI2_BASE,
-                .end = PNX4008_SPI2_BASE + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = PER_SPI2_REC_XMIT,
-                .flags = IORESOURCE_DMA,
-        }, {
-                .start = SPI2_INT,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-        {
-                .modalias       = "m25p80",
-                .max_speed_hz   = 1000000,
-                .bus_num        = 1,
-                .chip_select    = 0,
-        },
-};
-
-static struct platform_device spipnx_1 = {
-        .name = "spipnx",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(spipnx_0_resources),
-        .resource = spipnx_0_resources,
-        .dev = {
-                .coherent_dma_mask = 0xFFFFFFFF,
-                },
-};
-
-static struct platform_device spipnx_2 = {
-        .name = "spipnx",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(spipnx_1_resources),
-        .resource = spipnx_1_resources,
-        .dev = {
-                .coherent_dma_mask = 0xFFFFFFFF,
-                },
-};
-
-static struct plat_serial8250_port platform_serial_ports[] = {
-        {
-                .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)),
-                .mapbase = (unsigned long)PNX4008_UART5_BASE,
-                .irq = IIR5_INT,
-                .uartclk = PNX4008_UART_CLK,
-                .regshift = 2,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-        },
-        {
-                .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)),
-                .mapbase = (unsigned long)PNX4008_UART3_BASE,
-                .irq = IIR3_INT,
-                .uartclk = PNX4008_UART_CLK,
-                .regshift = 2,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-         },
-        {}
-};
-
-static struct platform_device serial_device = {
-        .name = "serial8250",
-        .id = PLAT8250_DEV_PLATFORM,
-        .dev = {
-                .platform_data = &platform_serial_ports,
-        },
-};
-
-static struct platform_device nand_flash_device = {
-        .name = "pnx4008-flash",
-        .id = -1,
-        .dev = {
-                .coherent_dma_mask = 0xFFFFFFFF,
-        },
-};
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32) 0;
-
-static struct resource ohci_resources[] = {
-        {
-                .start = IO_ADDRESS(PNX4008_USB_CONFIG_BASE),
-                .end = IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x100),
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = USB_HOST_INT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ohci_device = {
-        .name = "pnx4008-usb-ohci",
-        .id = -1,
-        .dev = {
-                .dma_mask = &ohci_dmamask,
-                .coherent_dma_mask = 0xffffffff,
-                },
-        .num_resources = ARRAY_SIZE(ohci_resources),
-        .resource = ohci_resources,
-};
-
-static struct platform_device sdum_device = {
-        .name = "pnx4008-sdum",
-        .id = 0,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-        },
-};
-
-static struct platform_device rgbfb_device = {
-        .name = "pnx4008-rgbfb",
-        .id = 0,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-        }
-};
-
-struct resource watchdog_resources[] = {
-        {
-                .start = PNX4008_WDOG_BASE,
-                .end = PNX4008_WDOG_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device watchdog_device = {
-        .name = "pnx4008-watchdog",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(watchdog_resources),
-        .resource = watchdog_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-        &spipnx_1,
-        &spipnx_2,
-        &serial_device,
-        &ohci_device,
-        &nand_flash_device,
-        &sdum_device,
-        &rgbfb_device,
-        &watchdog_device,
-};
-
-
-extern void pnx4008_uart_init(void);
-
-static void __init pnx4008_init(void)
-{
-        /*disable all START interrupt sources,
-           and clear all START interrupt flags */
-        __raw_writel(0, START_INT_ER_REG(SE_PIN_BASE_INT));
-        __raw_writel(0, START_INT_ER_REG(SE_INT_BASE_INT));
-        __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-        __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-        /* Switch on the UART clocks */
-        pnx4008_uart_init();
-}
-
-static struct map_desc pnx4008_io_desc[] __initdata = {
-        {
-                .virtual        = IO_ADDRESS(PNX4008_IRAM_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_IRAM_BASE),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IO_ADDRESS(PNX4008_NDF_FLASH_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_NDF_FLASH_BASE),
-                .length         = SZ_1M - SZ_128K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_JPEG_CONFIG_BASE),
-                .length         = SZ_128K * 3,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IO_ADDRESS(PNX4008_DMA_CONFIG_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_DMA_CONFIG_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IO_ADDRESS(PNX4008_AHB2FAB_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_AHB2FAB_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE,
-        },
-};
-
-void __init pnx4008_map_io(void)
-{
-        iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc));
-}
-
-static void pnx4008_restart(char mode, const char *cmd)
-{
-        soft_restart(0);
-}
-
-#ifdef CONFIG_PM
-extern int pnx4008_pm_init(void);
-#else
-static inline int pnx4008_pm_init(void) { return 0; }
-#endif
-
-void __init pnx4008_init_late(void)
-{
-        pnx4008_pm_init();
-}
-
-extern struct sys_timer pnx4008_timer;
-
-MACHINE_START(PNX4008, "Philips PNX4008")
-        /* Maintainer: MontaVista Software Inc. */
-        .atag_offset            = 0x100,
-        .map_io                 = pnx4008_map_io,
-        .init_irq               = pnx4008_init_irq,
-        .init_machine           = pnx4008_init,
-        .init_late              = pnx4008_init_late,
-        .timer                  = &pnx4008_timer,
-        .restart                = pnx4008_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
deleted file mode 100644
index a4739e9fb2fb..000000000000
--- a/arch/arm/mach-pnx4008/dma.c
+++ /dev/null
@@ -1,1105 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/dma.c
- *
- *  PNX4008 DMA registration and IRQ dispatching
- *
- *  Author:     Vitaly Wool
- *  Copyright:  MontaVista Software Inc. (c) 2005
- *
- *  Based on the code from Nicolas Pitre
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/gfp.h>
-
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <asm/dma-mapping.h>
-#include <mach/clock.h>
-
-static struct dma_channel {
-        char *name;
-        void (*irq_handler) (int, int, void *);
-        void *data;
-        struct pnx4008_dma_ll *ll;
-        u32 ll_dma;
-        void *target_addr;
-        int target_id;
-} dma_channels[MAX_DMA_CHANNELS];
-
-static struct ll_pool {
-        void *vaddr;
-        void *cur;
-        dma_addr_t dma_addr;
-        int count;
-} ll_pool;
-
-static DEFINE_SPINLOCK(ll_lock);
-
-struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma)
-{
-        struct pnx4008_dma_ll *ll = NULL;
-        unsigned long flags;
-
-        spin_lock_irqsave(&ll_lock, flags);
-        if (ll_pool.count > 4) { /* can give one more */
-                ll = *(struct pnx4008_dma_ll **) ll_pool.cur;
-                *ll_dma = ll_pool.dma_addr + ((void *)ll - ll_pool.vaddr);
-                *(void **)ll_pool.cur = **(void ***)ll_pool.cur;
-                memset(ll, 0, sizeof(*ll));
-                ll_pool.count--;
-        }
-        spin_unlock_irqrestore(&ll_lock, flags);
-
-        return ll;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_alloc_ll_entry);
-
-void pnx4008_free_ll_entry(struct pnx4008_dma_ll * ll, dma_addr_t ll_dma)
-{
-        unsigned long flags;
-
-        if (ll) {
-                if ((unsigned long)((long)ll - (long)ll_pool.vaddr) > 0x4000) {
-                        printk(KERN_ERR "Trying to free entry not allocated by DMA\n");
-                        BUG();
-                }
-
-                if (ll->flags & DMA_BUFFER_ALLOCATED)
-                        ll->free(ll->alloc_data);
-
-                spin_lock_irqsave(&ll_lock, flags);
-                *(long *)ll = *(long *)ll_pool.cur;
-                *(long *)ll_pool.cur = (long)ll;
-                ll_pool.count++;
-                spin_unlock_irqrestore(&ll_lock, flags);
-        }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll_entry);
-
-void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll * ll)
-{
-        struct pnx4008_dma_ll *ptr;
-        u32 dma;
-
-        while (ll) {
-                dma = ll->next_dma;
-                ptr = ll->next;
-                pnx4008_free_ll_entry(ll, ll_dma);
-
-                ll_dma = dma;
-                ll = ptr;
-        }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll);
-
-static int dma_channels_requested = 0;
-
-static inline void dma_increment_usage(void)
-{
-        if (!dma_channels_requested++) {
-                struct clk *clk = clk_get(0, "dma_ck");
-                if (!IS_ERR(clk)) {
-                        clk_set_rate(clk, 1);
-                        clk_put(clk);
-                }
-                pnx4008_config_dma(-1, -1, 1);
-        }
-}
-static inline void dma_decrement_usage(void)
-{
-        if (!--dma_channels_requested) {
-                struct clk *clk = clk_get(0, "dma_ck");
-                if (!IS_ERR(clk)) {
-                        clk_set_rate(clk, 0);
-                        clk_put(clk);
-                }
-                pnx4008_config_dma(-1, -1, 0);
-
-        }
-}
-
-static DEFINE_SPINLOCK(dma_lock);
-
-static inline void pnx4008_dma_lock(void)
-{
-        spin_lock_irq(&dma_lock);
-}
-
-static inline void pnx4008_dma_unlock(void)
-{
-        spin_unlock_irq(&dma_lock);
-}
-
-#define VALID_CHANNEL(c)        (((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
-
-int pnx4008_request_channel(char *name, int ch,
-                            void (*irq_handler) (int, int, void *), void *data)
-{
-        int i, found = 0;
-
-        /* basic sanity checks */
-        if (!name || (ch != -1 && !VALID_CHANNEL(ch)))
-                return -EINVAL;
-
-        pnx4008_dma_lock();
-
-        /* try grabbing a DMA channel with the requested priority */
-        for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-                if (!dma_channels[i].name && (ch == -1 || ch == i)) {
-                        found = 1;
-                        break;
-                }
-        }
-
-        if (found) {
-                dma_increment_usage();
-                dma_channels[i].name = name;
-                dma_channels[i].irq_handler = irq_handler;
-                dma_channels[i].data = data;
-                dma_channels[i].ll = NULL;
-                dma_channels[i].ll_dma = 0;
-        } else {
-                printk(KERN_WARNING "No more available DMA channels for %s\n",
-                       name);
-                i = -ENODEV;
-        }
-
-        pnx4008_dma_unlock();
-        return i;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_request_channel);
-
-void pnx4008_free_channel(int ch)
-{
-        if (!dma_channels[ch].name) {
-                printk(KERN_CRIT
-                       "%s: trying to free channel %d which is already freed\n",
-                       __func__, ch);
-                return;
-        }
-
-        pnx4008_dma_lock();
-        pnx4008_free_ll(dma_channels[ch].ll_dma, dma_channels[ch].ll);
-        dma_channels[ch].ll = NULL;
-        dma_decrement_usage();
-
-        dma_channels[ch].name = NULL;
-        pnx4008_dma_unlock();
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_channel);
-
-int pnx4008_config_dma(int ahb_m1_be, int ahb_m2_be, int enable)
-{
-        unsigned long dma_cfg = __raw_readl(DMAC_CONFIG);
-
-        switch (ahb_m1_be) {
-        case 0:
-                dma_cfg &= ~(1 << 1);
-                break;
-        case 1:
-                dma_cfg |= (1 << 1);
-                break;
-        default:
-                break;
-        }
-
-        switch (ahb_m2_be) {
-        case 0:
-                dma_cfg &= ~(1 << 2);
-                break;
-        case 1:
-                dma_cfg |= (1 << 2);
-                break;
-        default:
-                break;
-        }
-
-        switch (enable) {
-        case 0:
-                dma_cfg &= ~(1 << 0);
-                break;
-        case 1:
-                dma_cfg |= (1 << 0);
-                break;
-        default:
-                break;
-        }
-
-        pnx4008_dma_lock();
-        __raw_writel(dma_cfg, DMAC_CONFIG);
-        pnx4008_dma_unlock();
-
-        return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_dma);
-
-int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl * ch_ctrl,
-                             unsigned long *ctrl)
-{
-        int i = 0, dbsize, sbsize, err = 0;
-
-        if (!ctrl || !ch_ctrl) {
-                err = -EINVAL;
-                goto out;
-        }
-
-        *ctrl = 0;
-
-        switch (ch_ctrl->tc_mask) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 31);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-
-        switch (ch_ctrl->cacheable) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 30);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->bufferable) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 29);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->priv_mode) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 28);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->di) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 27);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->si) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 26);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->dest_ahb1) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 25);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->src_ahb1) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 24);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->dwidth) {
-        case WIDTH_BYTE:
-                *ctrl &= ~(7 << 21);
-                break;
-        case WIDTH_HWORD:
-                *ctrl &= ~(7 << 21);
-                *ctrl |= (1 << 21);
-                break;
-        case WIDTH_WORD:
-                *ctrl &= ~(7 << 21);
-                *ctrl |= (2 << 21);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->swidth) {
-        case WIDTH_BYTE:
-                *ctrl &= ~(7 << 18);
-                break;
-        case WIDTH_HWORD:
-                *ctrl &= ~(7 << 18);
-                *ctrl |= (1 << 18);
-                break;
-        case WIDTH_WORD:
-                *ctrl &= ~(7 << 18);
-                *ctrl |= (2 << 18);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        dbsize = ch_ctrl->dbsize;
-        while (!(dbsize & 1)) {
-                i++;
-                dbsize >>= 1;
-        }
-        if (ch_ctrl->dbsize != 1 || i > 8 || i == 1) {
-                err = -EINVAL;
-                goto out;
-        } else if (i > 1)
-                i--;
-        *ctrl &= ~(7 << 15);
-        *ctrl |= (i << 15);
-
-        sbsize = ch_ctrl->sbsize;
-        while (!(sbsize & 1)) {
-                i++;
-                sbsize >>= 1;
-        }
-        if (ch_ctrl->sbsize != 1 || i > 8 || i == 1) {
-                err = -EINVAL;
-                goto out;
-        } else if (i > 1)
-                i--;
-        *ctrl &= ~(7 << 12);
-        *ctrl |= (i << 12);
-
-        if (ch_ctrl->tr_size > 0x7ff) {
-                err = -E2BIG;
-                goto out;
-        }
-        *ctrl &= ~0x7ff;
-        *ctrl |= ch_ctrl->tr_size & 0x7ff;
-
-out:
-        return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_control);
-
-int pnx4008_dma_parse_control(unsigned long ctrl,
-                              struct pnx4008_dma_ch_ctrl * ch_ctrl)
-{
-        int err = 0;
-
-        if (!ch_ctrl) {
-                err = -EINVAL;
-                goto out;
-        }
-
-        ch_ctrl->tr_size = ctrl & 0x7ff;
-        ctrl >>= 12;
-
-        ch_ctrl->sbsize = 1 << (ctrl & 7);
-        if (ch_ctrl->sbsize > 1)
-                ch_ctrl->sbsize <<= 1;
-        ctrl >>= 3;
-
-        ch_ctrl->dbsize = 1 << (ctrl & 7);
-        if (ch_ctrl->dbsize > 1)
-                ch_ctrl->dbsize <<= 1;
-        ctrl >>= 3;
-
-        switch (ctrl & 7) {
-        case 0:
-                ch_ctrl->swidth = WIDTH_BYTE;
-                break;
-        case 1:
-                ch_ctrl->swidth = WIDTH_HWORD;
-                break;
-        case 2:
-                ch_ctrl->swidth = WIDTH_WORD;
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        ctrl >>= 3;
-
-        switch (ctrl & 7) {
-        case 0:
-                ch_ctrl->dwidth = WIDTH_BYTE;
-                break;
-        case 1:
-                ch_ctrl->dwidth = WIDTH_HWORD;
-                break;
-        case 2:
-                ch_ctrl->dwidth = WIDTH_WORD;
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        ctrl >>= 3;
-
-        ch_ctrl->src_ahb1 = ctrl & 1;
-        ctrl >>= 1;
-
-        ch_ctrl->dest_ahb1 = ctrl & 1;
-        ctrl >>= 1;
-
-        ch_ctrl->si = ctrl & 1;
-        ctrl >>= 1;
-
-        ch_ctrl->di = ctrl & 1;
-        ctrl >>= 1;
-
-        ch_ctrl->priv_mode = ctrl & 1;
-        ctrl >>= 1;
-
-        ch_ctrl->bufferable = ctrl & 1;
-        ctrl >>= 1;
-
-        ch_ctrl->cacheable = ctrl & 1;
-        ctrl >>= 1;
-
-        ch_ctrl->tc_mask = ctrl & 1;
-
-out:
-        return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_control);
-
-int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config * ch_cfg,
-                            unsigned long *cfg)
-{
-        int err = 0;
-
-        if (!cfg || !ch_cfg) {
-                err = -EINVAL;
-                goto out;
-        }
-
-        *cfg = 0;
-
-        switch (ch_cfg->halt) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 18);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->active) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 17);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->lock) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 16);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->itc) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 15);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->ie) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 14);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->flow_cntrl) {
-        case FC_MEM2MEM_DMA:
-                *cfg &= ~(7 << 11);
-                break;
-        case FC_MEM2PER_DMA:
-                *cfg &= ~(7 << 11);
-                *cfg |= (1 << 11);
-                break;
-        case FC_PER2MEM_DMA:
-                *cfg &= ~(7 << 11);
-                *cfg |= (2 << 11);
-                break;
-        case FC_PER2PER_DMA:
-                *cfg &= ~(7 << 11);
-                *cfg |= (3 << 11);
-                break;
-        case FC_PER2PER_DPER:
-                *cfg &= ~(7 << 11);
-                *cfg |= (4 << 11);
-                break;
-        case FC_MEM2PER_PER:
-                *cfg &= ~(7 << 11);
-                *cfg |= (5 << 11);
-                break;
-        case FC_PER2MEM_PER:
-                *cfg &= ~(7 << 11);
-                *cfg |= (6 << 11);
-                break;
-        case FC_PER2PER_SPER:
-                *cfg |= (7 << 11);
-                break;
-
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        *cfg &= ~(0x1f << 6);
-        *cfg |= ((ch_cfg->dest_per & 0x1f) << 6);
-
-        *cfg &= ~(0x1f << 1);
-        *cfg |= ((ch_cfg->src_per & 0x1f) << 1);
-
-out:
-        return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_config);
-
-int pnx4008_dma_parse_config(unsigned long cfg,
-                             struct pnx4008_dma_ch_config * ch_cfg)
-{
-        int err = 0;
-
-        if (!ch_cfg) {
-                err = -EINVAL;
-                goto out;
-        }
-
-        cfg >>= 1;
-
-        ch_cfg->src_per = cfg & 0x1f;
-        cfg >>= 5;
-
-        ch_cfg->dest_per = cfg & 0x1f;
-        cfg >>= 5;
-
-        switch (cfg & 7) {
-        case 0:
-                ch_cfg->flow_cntrl = FC_MEM2MEM_DMA;
-                break;
-        case 1:
-                ch_cfg->flow_cntrl = FC_MEM2PER_DMA;
-                break;
-        case 2:
-                ch_cfg->flow_cntrl = FC_PER2MEM_DMA;
-                break;
-        case 3:
-                ch_cfg->flow_cntrl = FC_PER2PER_DMA;
-                break;
-        case 4:
-                ch_cfg->flow_cntrl = FC_PER2PER_DPER;
-                break;
-        case 5:
-                ch_cfg->flow_cntrl = FC_MEM2PER_PER;
-                break;
-        case 6:
-                ch_cfg->flow_cntrl = FC_PER2MEM_PER;
-                break;
-        case 7:
-                ch_cfg->flow_cntrl = FC_PER2PER_SPER;
-        }
-        cfg >>= 3;
-
-        ch_cfg->ie = cfg & 1;
-        cfg >>= 1;
-
-        ch_cfg->itc = cfg & 1;
-        cfg >>= 1;
-
-        ch_cfg->lock = cfg & 1;
-        cfg >>= 1;
-
-        ch_cfg->active = cfg & 1;
-        cfg >>= 1;
-
-        ch_cfg->halt = cfg & 1;
-
-out:
-        return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_config);
-
-void pnx4008_dma_split_head_entry(struct pnx4008_dma_config * config,
-                                  struct pnx4008_dma_ch_ctrl * ctrl)
-{
-        int new_len = ctrl->tr_size, num_entries = 0;
-        int old_len = new_len;
-        int src_width, dest_width, count = 1;
-
-        switch (ctrl->swidth) {
-        case WIDTH_BYTE:
-                src_width = 1;
-                break;
-        case WIDTH_HWORD:
-                src_width = 2;
-                break;
-        case WIDTH_WORD:
-                src_width = 4;
-                break;
-        default:
-                return;
-        }
-
-        switch (ctrl->dwidth) {
-        case WIDTH_BYTE:
-                dest_width = 1;
-                break;
-        case WIDTH_HWORD:
-                dest_width = 2;
-                break;
-        case WIDTH_WORD:
-                dest_width = 4;
-                break;
-        default:
-                return;
-        }
-
-        while (new_len > 0x7FF) {
-                num_entries++;
-                new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-        }
-        if (num_entries != 0) {
-                struct pnx4008_dma_ll *ll = NULL;
-                config->ch_ctrl &= ~0x7ff;
-                config->ch_ctrl |= new_len;
-                if (!config->is_ll) {
-                        config->is_ll = 1;
-                        while (num_entries) {
-                                if (!ll) {
-                                        config->ll =
-                                            pnx4008_alloc_ll_entry(&config->
-                                                                   ll_dma);
-                                        ll = config->ll;
-                                } else {
-                                        ll->next =
-                                            pnx4008_alloc_ll_entry(&ll->
-                                                                   next_dma);
-                                        ll = ll->next;
-                                }
-
-                                if (ctrl->si)
-                                        ll->src_addr =
-                                            config->src_addr +
-                                            src_width * new_len * count;
-                                else
-                                        ll->src_addr = config->src_addr;
-                                if (ctrl->di)
-                                        ll->dest_addr =
-                                            config->dest_addr +
-                                            dest_width * new_len * count;
-                                else
-                                        ll->dest_addr = config->dest_addr;
-                                ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-                                ll->next_dma = 0;
-                                ll->next = NULL;
-                                num_entries--;
-                                count++;
-                        }
-                } else {
-                        struct pnx4008_dma_ll *ll_old = config->ll;
-                        unsigned long ll_dma_old = config->ll_dma;
-                        while (num_entries) {
-                                if (!ll) {
-                                        config->ll =
-                                            pnx4008_alloc_ll_entry(&config->
-                                                                   ll_dma);
-                                        ll = config->ll;
-                                } else {
-                                        ll->next =
-                                            pnx4008_alloc_ll_entry(&ll->
-                                                                   next_dma);
-                                        ll = ll->next;
-                                }
-
-                                if (ctrl->si)
-                                        ll->src_addr =
-                                            config->src_addr +
-                                            src_width * new_len * count;
-                                else
-                                        ll->src_addr = config->src_addr;
-                                if (ctrl->di)
-                                        ll->dest_addr =
-                                            config->dest_addr +
-                                            dest_width * new_len * count;
-                                else
-                                        ll->dest_addr = config->dest_addr;
-                                ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-                                ll->next_dma = 0;
-                                ll->next = NULL;
-                                num_entries--;
-                                count++;
-                        }
-                        ll->next_dma = ll_dma_old;
-                        ll->next = ll_old;
-                }
-                /* adjust last length/tc */
-                ll->ch_ctrl = config->ch_ctrl & (~0x7ff);
-                ll->ch_ctrl |= old_len - new_len * (count - 1);
-                config->ch_ctrl &= 0x7fffffff;
-        }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_head_entry);
-
-void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll * cur_ll,
-                                struct pnx4008_dma_ch_ctrl * ctrl)
-{
-        int new_len = ctrl->tr_size, num_entries = 0;
-        int old_len = new_len;
-        int src_width, dest_width, count = 1;
-
-        switch (ctrl->swidth) {
-        case WIDTH_BYTE:
-                src_width = 1;
-                break;
-        case WIDTH_HWORD:
-                src_width = 2;
-                break;
-        case WIDTH_WORD:
-                src_width = 4;
-                break;
-        default:
-                return;
-        }
-
-        switch (ctrl->dwidth) {
-        case WIDTH_BYTE:
-                dest_width = 1;
-                break;
-        case WIDTH_HWORD:
-                dest_width = 2;
-                break;
-        case WIDTH_WORD:
-                dest_width = 4;
-                break;
-        default:
-                return;
-        }
-
-        while (new_len > 0x7FF) {
-                num_entries++;
-                new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-        }
-        if (num_entries != 0) {
-                struct pnx4008_dma_ll *ll = NULL;
-                cur_ll->ch_ctrl &= ~0x7ff;
-                cur_ll->ch_ctrl |= new_len;
-                if (!cur_ll->next) {
-                        while (num_entries) {
-                                if (!ll) {
-                                        cur_ll->next =
-                                            pnx4008_alloc_ll_entry(&cur_ll->
-                                                                   next_dma);
-                                        ll = cur_ll->next;
-                                } else {
-                                        ll->next =
-                                            pnx4008_alloc_ll_entry(&ll->
-                                                                   next_dma);
-                                        ll = ll->next;
-                                }
-
-                                if (ctrl->si)
-                                        ll->src_addr =
-                                            cur_ll->src_addr +
-                                            src_width * new_len * count;
-                                else
-                                        ll->src_addr = cur_ll->src_addr;
-                                if (ctrl->di)
-                                        ll->dest_addr =
-                                            cur_ll->dest_addr +
-                                            dest_width * new_len * count;
-                                else
-                                        ll->dest_addr = cur_ll->dest_addr;
-                                ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-                                ll->next_dma = 0;
-                                ll->next = NULL;
-                                num_entries--;
-                                count++;
-                        }
-                } else {
-                        struct pnx4008_dma_ll *ll_old = cur_ll->next;
-                        unsigned long ll_dma_old = cur_ll->next_dma;
-                        while (num_entries) {
-                                if (!ll) {
-                                        cur_ll->next =
-                                            pnx4008_alloc_ll_entry(&cur_ll->
-                                                                   next_dma);
-                                        ll = cur_ll->next;
-                                } else {
-                                        ll->next =
-                                            pnx4008_alloc_ll_entry(&ll->
-                                                                   next_dma);
-                                        ll = ll->next;
-                                }
-
-                                if (ctrl->si)
-                                        ll->src_addr =
-                                            cur_ll->src_addr +
-                                            src_width * new_len * count;
-                                else
-                                        ll->src_addr = cur_ll->src_addr;
-                                if (ctrl->di)
-                                        ll->dest_addr =
-                                            cur_ll->dest_addr +
-                                            dest_width * new_len * count;
-                                else
-                                        ll->dest_addr = cur_ll->dest_addr;
-                                ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-                                ll->next_dma = 0;
-                                ll->next = NULL;
-                                num_entries--;
-                                count++;
-                        }
-
-                        ll->next_dma = ll_dma_old;
-                        ll->next = ll_old;
-                }
-                /* adjust last length/tc */
-                ll->ch_ctrl = cur_ll->ch_ctrl & (~0x7ff);
-                ll->ch_ctrl |= old_len - new_len * (count - 1);
-                cur_ll->ch_ctrl &= 0x7fffffff;
-        }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_ll_entry);
-
-int pnx4008_config_channel(int ch, struct pnx4008_dma_config * config)
-{
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-                return -EINVAL;
-
-        pnx4008_dma_lock();
-        __raw_writel(config->src_addr, DMAC_Cx_SRC_ADDR(ch));
-        __raw_writel(config->dest_addr, DMAC_Cx_DEST_ADDR(ch));
-
-        if (config->is_ll)
-                __raw_writel(config->ll_dma, DMAC_Cx_LLI(ch));
-        else
-                __raw_writel(0, DMAC_Cx_LLI(ch));
-
-        __raw_writel(config->ch_ctrl, DMAC_Cx_CONTROL(ch));
-        __raw_writel(config->ch_cfg, DMAC_Cx_CONFIG(ch));
-        pnx4008_dma_unlock();
-
-        return 0;
-
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_channel);
-
-int pnx4008_channel_get_config(int ch, struct pnx4008_dma_config * config)
-{
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name || !config)
-                return -EINVAL;
-
-        pnx4008_dma_lock();
-        config->ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-        config->ch_ctrl = __raw_readl(DMAC_Cx_CONTROL(ch));
-
-        config->ll_dma = __raw_readl(DMAC_Cx_LLI(ch));
-        config->is_ll = config->ll_dma ? 1 : 0;
-
-        config->src_addr = __raw_readl(DMAC_Cx_SRC_ADDR(ch));
-        config->dest_addr = __raw_readl(DMAC_Cx_DEST_ADDR(ch));
-        pnx4008_dma_unlock();
-
-        return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_channel_get_config);
-
-int pnx4008_dma_ch_enable(int ch)
-{
-        unsigned long ch_cfg;
-
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-                return -EINVAL;
-
-        pnx4008_dma_lock();
-        ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-        ch_cfg |= 1;
-        __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-        pnx4008_dma_unlock();
-
-        return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enable);
-
-int pnx4008_dma_ch_disable(int ch)
-{
-        unsigned long ch_cfg;
-
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-                return -EINVAL;
-
-        pnx4008_dma_lock();
-        ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-        ch_cfg &= ~1;
-        __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-        pnx4008_dma_unlock();
-
-        return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_disable);
-
-int pnx4008_dma_ch_enabled(int ch)
-{
-        unsigned long ch_cfg;
-
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-                return -EINVAL;
-
-        pnx4008_dma_lock();
-        ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-        pnx4008_dma_unlock();
-
-        return ch_cfg & 1;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled);
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-        int i;
-        unsigned long dint = __raw_readl(DMAC_INT_STAT);
-        unsigned long tcint = __raw_readl(DMAC_INT_TC_STAT);
-        unsigned long eint = __raw_readl(DMAC_INT_ERR_STAT);
-        unsigned long i_bit;
-
-        for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-                i_bit = 1 << i;
-                if (dint & i_bit) {
-                        struct dma_channel *channel = &dma_channels[i];
-
-                        if (channel->name && channel->irq_handler) {
-                                int cause = 0;
-
-                                if (eint & i_bit)
-                                        cause |= DMA_ERR_INT;
-                                if (tcint & i_bit)
-                                        cause |= DMA_TC_INT;
-                                channel->irq_handler(i, cause, channel->data);
-                        } else {
-                                /*
-                                 * IRQ for an unregistered DMA channel
-                                 */
-                                printk(KERN_WARNING
-                                       "spurious IRQ for DMA channel %d\n", i);
-                        }
-                        if (tcint & i_bit)
-                                __raw_writel(i_bit, DMAC_INT_TC_CLEAR);
-                        if (eint & i_bit)
-                                __raw_writel(i_bit, DMAC_INT_ERR_CLEAR);
-                }
-        }
-        return IRQ_HANDLED;
-}
-
-static int __init pnx4008_dma_init(void)
-{
-        int ret, i;
-
-        ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-        if (ret) {
-                printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
-                goto out;
-        }
-
-        ll_pool.count = 0x4000 / sizeof(struct pnx4008_dma_ll);
-        ll_pool.cur = ll_pool.vaddr =
-            dma_alloc_coherent(NULL, ll_pool.count * sizeof(struct pnx4008_dma_ll),
-                               &ll_pool.dma_addr, GFP_KERNEL);
-
-        if (!ll_pool.vaddr) {
-                ret = -ENOMEM;
-                free_irq(DMA_INT, NULL);
-                goto out;
-        }
-
-        for (i = 0; i < ll_pool.count - 1; i++) {
-                void **addr = ll_pool.vaddr + i * sizeof(struct pnx4008_dma_ll);
-                *addr = (void *)addr + sizeof(struct pnx4008_dma_ll);
-        }
-        *(long *)(ll_pool.vaddr +
-                  (ll_pool.count - 1) * sizeof(struct pnx4008_dma_ll)) =
-            (long)ll_pool.vaddr;
-
-        __raw_writel(1, DMAC_CONFIG);
-
-out:
-        return ret;
-}
-arch_initcall(pnx4008_dma_init);
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
deleted file mode 100644
index d3e71d3847b4..000000000000
--- a/arch/arm/mach-pnx4008/gpio.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/gpio.c
- *
- * PNX4008 GPIO driver
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/gpio-pnx4008.h>
-
-/* register definitions */
-#define PIO_VA_BASE     IO_ADDRESS(PNX4008_PIO_BASE)
-
-#define PIO_INP_STATE   (0x00U)
-#define PIO_OUTP_SET    (0x04U)
-#define PIO_OUTP_CLR    (0x08U)
-#define PIO_OUTP_STATE  (0x0CU)
-#define PIO_DRV_SET     (0x10U)
-#define PIO_DRV_CLR     (0x14U)
-#define PIO_DRV_STATE   (0x18U)
-#define PIO_SDINP_STATE (0x1CU)
-#define PIO_SDOUTP_SET  (0x20U)
-#define PIO_SDOUTP_CLR  (0x24U)
-#define PIO_MUX_SET     (0x28U)
-#define PIO_MUX_CLR     (0x2CU)
-#define PIO_MUX_STATE   (0x30U)
-
-static inline void gpio_lock(void)
-{
-        local_irq_disable();
-}
-
-static inline void gpio_unlock(void)
-{
-        local_irq_enable();
-}
-
-/* Inline functions */
-static inline int gpio_read_bit(u32 reg, int gpio)
-{
-        u32 bit, val;
-        int ret = -EFAULT;
-
-        if (gpio < 0)
-                goto out;
-
-        bit = GPIO_BIT(gpio);
-        if (bit) {
-                val = __raw_readl(PIO_VA_BASE + reg);
-                ret = (val & bit) ? 1 : 0;
-        }
-out:
-        return ret;
-}
-
-static inline int gpio_set_bit(u32 reg, int gpio)
-{
-        u32 bit, val;
-        int ret = -EFAULT;
-
-        if (gpio < 0)
-                goto out;
-
-        bit = GPIO_BIT(gpio);
-        if (bit) {
-                val = __raw_readl(PIO_VA_BASE + reg);
-                val |= bit;
-                __raw_writel(val, PIO_VA_BASE + reg);
-                ret = 0;
-        }
-out:
-        return ret;
-}
-
-/* Very simple access control, bitmap for allocated/free */
-static unsigned long access_map[4];
-#define INP_INDEX       0
-#define OUTP_INDEX      1
-#define GPIO_INDEX      2
-#define MUX_INDEX       3
-
-/*GPIO to Input Mapping */
-static short gpio_to_inp_map[32] = {
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, 10, 11, 12, 13, 14, 24, -1
-};
-
-/*GPIO to Mux Mapping */
-static short gpio_to_mux_map[32] = {
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, 0, 1, 4, 5, -1
-};
-
-/*Output to Mux Mapping */
-static short outp_to_mux_map[32] = {
-        -1, -1, -1, 6, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, 2, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1
-};
-
-int pnx4008_gpio_register_pin(unsigned short pin)
-{
-        unsigned long bit = GPIO_BIT(pin);
-        int ret = -EBUSY;       /* Already in use */
-
-        gpio_lock();
-
-        if (GPIO_ISBID(pin)) {
-                if (access_map[GPIO_INDEX] & bit)
-                        goto out;
-                access_map[GPIO_INDEX] |= bit;
-
-        } else if (GPIO_ISRAM(pin)) {
-                if (access_map[GPIO_INDEX] & bit)
-                        goto out;
-                access_map[GPIO_INDEX] |= bit;
-
-        } else if (GPIO_ISMUX(pin)) {
-                if (access_map[MUX_INDEX] & bit)
-                        goto out;
-                access_map[MUX_INDEX] |= bit;
-
-        } else if (GPIO_ISOUT(pin)) {
-                if (access_map[OUTP_INDEX] & bit)
-                        goto out;
-                access_map[OUTP_INDEX] |= bit;
-
-        } else if (GPIO_ISIN(pin)) {
-                if (access_map[INP_INDEX] & bit)
-                        goto out;
-                access_map[INP_INDEX] |= bit;
-        } else
-                goto out;
-        ret = 0;
-
-out:
-        gpio_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_register_pin);
-
-int pnx4008_gpio_unregister_pin(unsigned short pin)
-{
-        unsigned long bit = GPIO_BIT(pin);
-        int ret = -EFAULT;      /* Not registered */
-
-        gpio_lock();
-
-        if (GPIO_ISBID(pin)) {
-                if (~access_map[GPIO_INDEX] & bit)
-                        goto out;
-                access_map[GPIO_INDEX] &= ~bit;
-        } else if (GPIO_ISRAM(pin)) {
-                if (~access_map[GPIO_INDEX] & bit)
-                        goto out;
-                access_map[GPIO_INDEX] &= ~bit;
-        } else if (GPIO_ISMUX(pin)) {
-                if (~access_map[MUX_INDEX] & bit)
-                        goto out;
-                access_map[MUX_INDEX] &= ~bit;
-        } else if (GPIO_ISOUT(pin)) {
-                if (~access_map[OUTP_INDEX] & bit)
-                        goto out;
-                access_map[OUTP_INDEX] &= ~bit;
-        } else if (GPIO_ISIN(pin)) {
-                if (~access_map[INP_INDEX] & bit)
-                        goto out;
-                access_map[INP_INDEX] &= ~bit;
-        } else
-                goto out;
-        ret = 0;
-
-out:
-        gpio_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_unregister_pin);
-
-unsigned long pnx4008_gpio_read_pin(unsigned short pin)
-{
-        unsigned long ret = -EFAULT;
-        int gpio = GPIO_BIT_MASK(pin);
-        gpio_lock();
-        if (GPIO_ISOUT(pin)) {
-                ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-        } else if (GPIO_ISRAM(pin)) {
-                if (gpio_read_bit(PIO_DRV_STATE, gpio) == 0) {
-                        ret = gpio_read_bit(PIO_SDINP_STATE, gpio);
-                }
-        } else if (GPIO_ISBID(pin)) {
-                ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-                if (ret > 0)
-                        ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-                else if (ret == 0)
-                        ret =
-                            gpio_read_bit(PIO_INP_STATE, gpio_to_inp_map[gpio]);
-        } else if (GPIO_ISIN(pin)) {
-                ret = gpio_read_bit(PIO_INP_STATE, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin);
-
-/* Write Value to output */
-int pnx4008_gpio_write_pin(unsigned short pin, int output)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-
-        gpio_lock();
-        if (GPIO_ISOUT(pin)) {
-                printk( "writing '%x' to '%x'\n",
-                                gpio, output ? PIO_OUTP_SET : PIO_OUTP_CLR );
-                ret = gpio_set_bit(output ? PIO_OUTP_SET : PIO_OUTP_CLR, gpio);
-        } else if (GPIO_ISRAM(pin)) {
-                if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-                        ret = gpio_set_bit(output ? PIO_SDOUTP_SET :
-                                           PIO_SDOUTP_CLR, gpio);
-        } else if (GPIO_ISBID(pin)) {
-                if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-                        ret = gpio_set_bit(output ? PIO_OUTP_SET :
-                                           PIO_OUTP_CLR, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_write_pin);
-
-/* Value = 1 : Set GPIO pin as output */
-/* Value = 0 : Set GPIO pin as input */
-int pnx4008_gpio_set_pin_direction(unsigned short pin, int output)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-
-        gpio_lock();
-        if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-                ret = gpio_set_bit(output ? PIO_DRV_SET : PIO_DRV_CLR, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_direction);
-
-/* Read GPIO pin direction: 0= pin used as input, 1= pin used as output*/
-int pnx4008_gpio_read_pin_direction(unsigned short pin)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-
-        gpio_lock();
-        if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-                ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_direction);
-
-/* Value = 1 : Set pin to muxed function  */
-/* Value = 0 : Set pin as GPIO */
-int pnx4008_gpio_set_pin_mux(unsigned short pin, int output)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-
-        gpio_lock();
-        if (GPIO_ISBID(pin)) {
-                ret =
-                    gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-                                 gpio_to_mux_map[gpio]);
-        } else if (GPIO_ISOUT(pin)) {
-                ret =
-                    gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-                                 outp_to_mux_map[gpio]);
-        } else if (GPIO_ISMUX(pin)) {
-                ret = gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_mux);
-
-/* Read pin mux function: 0= pin used as GPIO, 1= pin used for muxed function*/
-int pnx4008_gpio_read_pin_mux(unsigned short pin)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-
-        gpio_lock();
-        if (GPIO_ISBID(pin)) {
-                ret = gpio_read_bit(PIO_MUX_STATE, gpio_to_mux_map[gpio]);
-        } else if (GPIO_ISOUT(pin)) {
-                ret = gpio_read_bit(PIO_MUX_STATE, outp_to_mux_map[gpio]);
-        } else if (GPIO_ISMUX(pin)) {
-                ret = gpio_read_bit(PIO_MUX_STATE, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_mux);
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
deleted file mode 100644
index 550cfc2a1f2e..000000000000
--- a/arch/arm/mach-pnx4008/i2c.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * I2C initialization for PNX4008.
- *
- * Author: Vitaly Wool <vitalywool@gmail.com>
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c-pnx.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <mach/platform.h>
-#include <mach/irqs.h>
-
-static struct resource i2c0_resources[] = {
-        {
-                .start = PNX4008_I2C1_BASE,
-                .end = PNX4008_I2C1_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = I2C_1_INT,
-                .end = I2C_1_INT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource i2c1_resources[] = {
-        {
-                .start = PNX4008_I2C2_BASE,
-                .end = PNX4008_I2C2_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = I2C_2_INT,
-                .end = I2C_2_INT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource i2c2_resources[] = {
-        {
-                .start = PNX4008_USB_CONFIG_BASE + 0x300,
-                .end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = USB_I2C_INT,
-                .end = USB_I2C_INT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device i2c0_device = {
-        .name = "pnx-i2c.0",
-        .id = 0,
-        .resource = i2c0_resources,
-        .num_resources = ARRAY_SIZE(i2c0_resources),
-};
-
-static struct platform_device i2c1_device = {
-        .name = "pnx-i2c.1",
-        .id = 1,
-        .resource = i2c1_resources,
-        .num_resources = ARRAY_SIZE(i2c1_resources),
-};
-
-static struct platform_device i2c2_device = {
-        .name = "pnx-i2c.2",
-        .id = 2,
-        .resource = i2c2_resources,
-        .num_resources = ARRAY_SIZE(i2c2_resources),
-};
-
-static struct platform_device *devices[] __initdata = {
-        &i2c0_device,
-        &i2c1_device,
-        &i2c2_device,
-};
-
-void __init pnx4008_register_i2c_devices(void)
-{
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
diff --git a/arch/arm/mach-pnx4008/include/mach/clock.h b/arch/arm/mach-pnx4008/include/mach/clock.h
deleted file mode 100644
index 8d2a5ef52c90..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/clock.h
- *
- * Clock control driver for PNX4008 - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_CLOCK_H__
-#define __PNX4008_CLOCK_H__
-
-struct module;
-struct clk;
-
-#define PWRMAN_VA_BASE          IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define HCLKDIVCTRL_REG         (PWRMAN_VA_BASE + 0x40)
-#define PWRCTRL_REG             (PWRMAN_VA_BASE + 0x44)
-#define PLLCTRL_REG             (PWRMAN_VA_BASE + 0x48)
-#define OSC13CTRL_REG           (PWRMAN_VA_BASE + 0x4c)
-#define SYSCLKCTRL_REG          (PWRMAN_VA_BASE + 0x50)
-#define HCLKPLLCTRL_REG         (PWRMAN_VA_BASE + 0x58)
-#define USBCTRL_REG             (PWRMAN_VA_BASE + 0x64)
-#define SDRAMCLKCTRL_REG        (PWRMAN_VA_BASE + 0x68)
-#define MSCTRL_REG              (PWRMAN_VA_BASE + 0x80)
-#define BTCLKCTRL               (PWRMAN_VA_BASE + 0x84)
-#define DUMCLKCTRL_REG          (PWRMAN_VA_BASE + 0x90)
-#define I2CCLKCTRL_REG          (PWRMAN_VA_BASE + 0xac)
-#define KEYCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb0)
-#define TSCLKCTRL_REG           (PWRMAN_VA_BASE + 0xb4)
-#define PWMCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb8)
-#define TIMCLKCTRL_REG          (PWRMAN_VA_BASE + 0xbc)
-#define SPICTRL_REG             (PWRMAN_VA_BASE + 0xc4)
-#define FLASHCLKCTRL_REG        (PWRMAN_VA_BASE + 0xc8)
-#define UART3CLK_REG            (PWRMAN_VA_BASE + 0xd0)
-#define UARTCLKCTRL_REG         (PWRMAN_VA_BASE + 0xe4)
-#define DMACLKCTRL_REG          (PWRMAN_VA_BASE + 0xe8)
-#define AUTOCLK_CTRL            (PWRMAN_VA_BASE + 0xec)
-#define JPEGCLKCTRL_REG         (PWRMAN_VA_BASE + 0xfc)
-
-#define AUDIOCONFIG_VA_BASE     IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
-#define DSPPLLCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x60)
-#define DSPCLKCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x64)
-#define AUDIOCLKCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x68)
-#define AUDIOPLLCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x6C)
-
-#define USB_OTG_CLKCTRL_REG     IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
-
-#define VFP9CLKCTRL_REG         IO_ADDRESS(PNX4008_DEBUG_BASE)
-
-#define CLK_RATE_13MHZ 13000
-#define CLK_RATE_1MHZ 1000
-#define CLK_RATE_208MHZ 208000
-#define CLK_RATE_48MHZ 48000
-#define CLK_RATE_32KHZ 32
-
-#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
deleted file mode 100644
index 469d60d97f5c..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-pnx4008/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0x00090000
-                add     \rv, \rp, #0xf4000000   @ virtual
-                add     \rp, \rp, #0x40000000   @ physical
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pnx4008/include/mach/dma.h b/arch/arm/mach-pnx4008/include/mach/dma.h
deleted file mode 100644
index f094bf8bfb18..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/dma.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/dma.h
- *
- *  PNX4008 DMA header file
- *
- *  Author:     Vitaly Wool
- *  Copyright:  MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include "platform.h"
-
-#define MAX_DMA_CHANNELS        8
-
-#define DMAC_BASE               IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
-#define DMAC_INT_STAT           (DMAC_BASE + 0x0000)
-#define DMAC_INT_TC_STAT        (DMAC_BASE + 0x0004)
-#define DMAC_INT_TC_CLEAR       (DMAC_BASE + 0x0008)
-#define DMAC_INT_ERR_STAT       (DMAC_BASE + 0x000c)
-#define DMAC_INT_ERR_CLEAR      (DMAC_BASE + 0x0010)
-#define DMAC_SOFT_SREQ          (DMAC_BASE + 0x0024)
-#define DMAC_CONFIG             (DMAC_BASE + 0x0030)
-#define DMAC_Cx_SRC_ADDR(c)     (DMAC_BASE + 0x0100 + (c) * 0x20)
-#define DMAC_Cx_DEST_ADDR(c)    (DMAC_BASE + 0x0104 + (c) * 0x20)
-#define DMAC_Cx_LLI(c)          (DMAC_BASE + 0x0108 + (c) * 0x20)
-#define DMAC_Cx_CONTROL(c)      (DMAC_BASE + 0x010c + (c) * 0x20)
-#define DMAC_Cx_CONFIG(c)       (DMAC_BASE + 0x0110 + (c) * 0x20)
-
-enum {
-        WIDTH_BYTE = 0,
-        WIDTH_HWORD,
-        WIDTH_WORD
-};
-
-enum {
-        FC_MEM2MEM_DMA,
-        FC_MEM2PER_DMA,
-        FC_PER2MEM_DMA,
-        FC_PER2PER_DMA,
-        FC_PER2PER_DPER,
-        FC_MEM2PER_PER,
-        FC_PER2MEM_PER,
-        FC_PER2PER_SPER
-};
-
-enum {
-        DMA_INT_UNKNOWN = 0,
-        DMA_ERR_INT = 1,
-        DMA_TC_INT = 2,
-};
-
-enum {
-        DMA_BUFFER_ALLOCATED = 1,
-        DMA_HAS_LL = 2,
-};
-
-enum {
-        PER_CAM_DMA_1 = 0,
-        PER_NDF_FLASH = 1,
-        PER_MBX_SLAVE_FIFO = 2,
-        PER_SPI2_REC_XMIT = 3,
-        PER_MS_SD_RX_XMIT = 4,
-        PER_HS_UART_1_XMIT = 5,
-        PER_HS_UART_1_RX = 6,
-        PER_HS_UART_2_XMIT = 7,
-        PER_HS_UART_2_RX = 8,
-        PER_HS_UART_7_XMIT = 9,
-        PER_HS_UART_7_RX = 10,
-        PER_SPI1_REC_XMIT = 11,
-        PER_MLC_NDF_SREC = 12,
-        PER_CAM_DMA_2 = 13,
-        PER_PRNG_INFIFO = 14,
-        PER_PRNG_OUTFIFO = 15,
-};
-
-struct pnx4008_dma_ch_ctrl {
-        int tc_mask;
-        int cacheable;
-        int bufferable;
-        int priv_mode;
-        int di;
-        int si;
-        int dest_ahb1;
-        int src_ahb1;
-        int dwidth;
-        int swidth;
-        int dbsize;
-        int sbsize;
-        int tr_size;
-};
-
-struct pnx4008_dma_ch_config {
-        int halt;
-        int active;
-        int lock;
-        int itc;
-        int ie;
-        int flow_cntrl;
-        int dest_per;
-        int src_per;
-};
-
-struct pnx4008_dma_ll {
-        unsigned long src_addr;
-        unsigned long dest_addr;
-        u32 next_dma;
-        unsigned long ch_ctrl;
-        struct pnx4008_dma_ll *next;
-        int flags;
-        void *alloc_data;
-        int (*free) (void *);
-};
-
-struct pnx4008_dma_config {
-        int is_ll;
-        unsigned long src_addr;
-        unsigned long dest_addr;
-        unsigned long ch_ctrl;
-        unsigned long ch_cfg;
-        struct pnx4008_dma_ll *ll;
-        u32 ll_dma;
-        int flags;
-        void *alloc_data;
-        int (*free) (void *);
-};
-
-extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
-extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
-extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
-
-extern int pnx4008_request_channel(char *, int,
-                                   void (*)(int, int, void *),
-                                   void *);
-extern void pnx4008_free_channel(int);
-extern int pnx4008_config_dma(int, int, int);
-extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
-                                    unsigned long *);
-extern int pnx4008_dma_parse_control(unsigned long,
-                                     struct pnx4008_dma_ch_ctrl *);
-extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
-                                   unsigned long *);
-extern int pnx4008_dma_parse_config(unsigned long,
-                                    struct pnx4008_dma_ch_config *);
-extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
-extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
-extern int pnx4008_dma_ch_enable(int);
-extern int pnx4008_dma_ch_disable(int);
-extern int pnx4008_dma_ch_enabled(int);
-extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
-                                         struct pnx4008_dma_ch_ctrl *);
-extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
-                                       struct pnx4008_dma_ch_ctrl *);
-
-#endif                          /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
deleted file mode 100644
index 77a555846719..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/entry-macro.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for PNX4008-based platforms
- *
- * 2005-2006 (c) MontaVista Software, Inc.
- * Author: Vitaly Wool <vwool@ru.mvista.com>
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include "platform.h"
-
-#define IO_BASE         0xF0000000
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#define INTRC_MASK                      0x00
-#define INTRC_RAW_STAT                  0x04
-#define INTRC_STAT                      0x08
-#define INTRC_POLAR                     0x0C
-#define INTRC_ACT_TYPE                  0x10
-#define INTRC_TYPE                      0x14
-
-#define SIC1_BASE_INT   32
-#define SIC2_BASE_INT   64
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* decode the MIC interrupt numbers */
-                ldr     \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-                ldr     \irqstat, [\base, #INTRC_STAT]
-
-                cmp     \irqstat,#1<<16
-                movhs   \irqnr,#16
-                movlo   \irqnr,#0
-                movhs   \irqstat,\irqstat,lsr#16
-                cmp     \irqstat,#1<<8
-                addhs   \irqnr,\irqnr,#8
-                movhs   \irqstat,\irqstat,lsr#8
-                cmp     \irqstat,#1<<4
-                addhs   \irqnr,\irqnr,#4
-                movhs   \irqstat,\irqstat,lsr#4
-                cmp     \irqstat,#1<<2
-                addhs   \irqnr,\irqnr,#2
-                movhs   \irqstat,\irqstat,lsr#2
-                cmp     \irqstat,#1<<1
-                addhs   \irqnr,\irqnr,#1
-
-/* was there an interrupt ? if not then drop out with EQ status */
-                teq     \irqstat,#0
-                beq     1003f
-
-/* and now check for extended IRQ reasons */
-                cmp     \irqnr,#1
-                bls     1003f
-                cmp     \irqnr,#30
-                blo     1002f
-
-/* IRQ 31,30  : High priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
-/* set the base IRQ number */
-                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-                moveq  \irqnr,#SIC1_BASE_INT
-                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-                movne   \irqnr,#SIC2_BASE_INT
-                ldr     \irqstat, [\base, #INTRC_STAT]
-                ldr     \tmp,     [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-                and     \irqstat,\irqstat,\tmp
-                b       1004f
-
-1003:
-/* IRQ 1,0  : Low priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
-/* read the correct SIC */
-/* set the base IRQ number  */
-                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-                movne   \irqnr,#SIC1_BASE_INT
-                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-                moveq   \irqnr,#SIC2_BASE_INT
-                ldr     \irqstat, [\base, #INTRC_STAT]
-                ldr     \tmp,     [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-                bic     \irqstat,\irqstat,\tmp
-
-1004:
-
-                cmp     \irqstat,#1<<16
-                addhs   \irqnr,\irqnr,#16
-                movhs   \irqstat,\irqstat,lsr#16
-                cmp     \irqstat,#1<<8
-                addhs   \irqnr,\irqnr,#8
-                movhs   \irqstat,\irqstat,lsr#8
-                cmp     \irqstat,#1<<4
-                addhs   \irqnr,\irqnr,#4
-                movhs   \irqstat,\irqstat,lsr#4
-                cmp     \irqstat,#1<<2
-                addhs   \irqnr,\irqnr,#2
-                movhs   \irqstat,\irqstat,lsr#2
-                cmp     \irqstat,#1<<1
-                addhs   \irqnr,\irqnr,#1
-
-
-/* is irqstat not zero */
-
-1002:
-/* we assert that irqstat is not equal to zero and return ne status if true*/
-                teq     \irqstat,#0
-1003:
-                .endm
-
diff --git a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h b/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
deleted file mode 100644
index 41027dd7cf74..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
- *
- * PNX4008 GPIO driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef _PNX4008_GPIO_H_
-#define _PNX4008_GPIO_H_
-
-
-/* Block numbers */
-#define GPIO_IN         (0)
-#define GPIO_OUT                (0x100)
-#define GPIO_BID                (0x200)
-#define GPIO_RAM                (0x300)
-#define GPIO_MUX                (0x400)
-
-#define GPIO_TYPE_MASK(K) ((K) & 0x700)
-
-/* INPUT GPIOs */
-/* GPI */
-#define GPI_00          (GPIO_IN | 0)
-#define GPI_01          (GPIO_IN | 1)
-#define GPI_02          (GPIO_IN | 2)
-#define GPI_03          (GPIO_IN | 3)
-#define GPI_04          (GPIO_IN | 4)
-#define GPI_05          (GPIO_IN | 5)
-#define GPI_06          (GPIO_IN | 6)
-#define GPI_07          (GPIO_IN | 7)
-#define GPI_08          (GPIO_IN | 8)
-#define GPI_09          (GPIO_IN | 9)
-#define U1_RX           (GPIO_IN | 15)
-#define U2_HTCS         (GPIO_IN | 16)
-#define U2_RX           (GPIO_IN | 17)
-#define U3_RX           (GPIO_IN | 18)
-#define U4_RX           (GPIO_IN | 19)
-#define U5_RX           (GPIO_IN | 20)
-#define U6_IRRX         (GPIO_IN | 21)
-#define U7_HCTS         (GPIO_IN | 22)
-#define U7_RX           (GPIO_IN | 23)
-/* MISC IN */
-#define SPI1_DATIN      (GPIO_IN | 25)
-#define DISP_SYNC       (GPIO_IN | 26)
-#define SPI2_DATIN      (GPIO_IN | 27)
-#define GPI_11          (GPIO_IN | 28)
-
-#define GPIO_IN_MASK   0x1eff83ff
-
-/* OUTPUT GPIOs */
-/* GPO */
-#define GPO_00          (GPIO_OUT | 0)
-#define GPO_01          (GPIO_OUT | 1)
-#define GPO_02          (GPIO_OUT | 2)
-#define GPO_03          (GPIO_OUT | 3)
-#define GPO_04          (GPIO_OUT | 4)
-#define GPO_05          (GPIO_OUT | 5)
-#define GPO_06          (GPIO_OUT | 6)
-#define GPO_07          (GPIO_OUT | 7)
-#define GPO_08          (GPIO_OUT | 8)
-#define GPO_09          (GPIO_OUT | 9)
-#define GPO_10          (GPIO_OUT | 10)
-#define GPO_11          (GPIO_OUT | 11)
-#define GPO_12          (GPIO_OUT | 12)
-#define GPO_13          (GPIO_OUT | 13)
-#define GPO_14          (GPIO_OUT | 14)
-#define GPO_15          (GPIO_OUT | 15)
-#define GPO_16          (GPIO_OUT | 16)
-#define GPO_17          (GPIO_OUT | 17)
-#define GPO_18          (GPIO_OUT | 18)
-#define GPO_19          (GPIO_OUT | 19)
-#define GPO_20          (GPIO_OUT | 20)
-#define GPO_21          (GPIO_OUT | 21)
-#define GPO_22          (GPIO_OUT | 22)
-#define GPO_23          (GPIO_OUT | 23)
-
-#define GPIO_OUT_MASK   0xffffff
-
-/* BIDIRECTIONAL GPIOs */
-/* RAM pins */
-#define RAM_D19         (GPIO_RAM | 0)
-#define RAM_D20         (GPIO_RAM | 1)
-#define RAM_D21         (GPIO_RAM | 2)
-#define RAM_D22         (GPIO_RAM | 3)
-#define RAM_D23         (GPIO_RAM | 4)
-#define RAM_D24         (GPIO_RAM | 5)
-#define RAM_D25         (GPIO_RAM | 6)
-#define RAM_D26         (GPIO_RAM | 7)
-#define RAM_D27         (GPIO_RAM | 8)
-#define RAM_D28         (GPIO_RAM | 9)
-#define RAM_D29         (GPIO_RAM | 10)
-#define RAM_D30         (GPIO_RAM | 11)
-#define RAM_D31         (GPIO_RAM | 12)
-
-#define GPIO_RAM_MASK   0x1fff
-
-/* I/O pins */
-#define GPIO_00         (GPIO_BID | 25)
-#define GPIO_01         (GPIO_BID | 26)
-#define GPIO_02         (GPIO_BID | 27)
-#define GPIO_03         (GPIO_BID | 28)
-#define GPIO_04         (GPIO_BID | 29)
-#define GPIO_05         (GPIO_BID | 30)
-
-#define GPIO_BID_MASK   0x7e000000
-
-/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
-#define GPIO_SDRAM_SEL  (GPIO_MUX | 3)
-
-#define GPIO_MUX_MASK   0x8
-
-/* Extraction/assembly macros */
-#define GPIO_BIT_MASK(K) ((K) & 0x1F)
-#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
-#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
-#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
-#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
-#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
-#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-#define SE_USB_OTG_ATX_INT_N    19
-/*18 unused*/
-#define SE_DSP_GPIO4_INT        17
-#define SE_KEY_IRQ              16
-#define SE_DSP_SLAVEPORT_INT    15
-#define SE_DSP_GPIO1_INT        14
-#define SE_DSP_GPIO0_INT        13
-#define SE_DSP_AHB_INT          12
-/*11-6 unused*/
-#define SE_GPIO_05_INT          5
-#define SE_GPIO_04_INT          4
-#define SE_GPIO_03_INT          3
-#define SE_GPIO_02_INT          2
-#define SE_GPIO_01_INT          1
-#define SE_GPIO_00_INT          0
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern int pnx4008_gpio_register_pin(unsigned short pin);
-extern int pnx4008_gpio_unregister_pin(unsigned short pin);
-extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
-extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
-extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
-extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
-
-static inline void start_int_umask(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
-                     START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_mask(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
-                     ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_ack(u8 irq)
-{
-        __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
-}
-
-static inline void start_int_set_falling_edge(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
-                     ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-static inline void start_int_set_rising_edge(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
-                     START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-#endif                          /* _PNX4008_GPIO_H_ */
diff --git a/arch/arm/mach-pnx4008/include/mach/hardware.h b/arch/arm/mach-pnx4008/include/mach/hardware.h
deleted file mode 100644
index 7b98b828d368..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/hardware.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <mach/platform.h>
-
-/* Start of virtual addresses for IO devices */
-#define IO_BASE         0xF0000000
-
-/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/irq.h b/arch/arm/mach-pnx4008/include/mach/irq.h
deleted file mode 100644
index 2a690ca33870..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/irq.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irq.h
- *
- * PNX4008 IRQ controller driver - header file
- * this one is used in entry-arnv.S as well so it cannot contain C code
- *
- * Copyright (c) 2005 Philips Semiconductors
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __PNX4008_IRQ_H__
-#define __PNX4008_IRQ_H__
-
-#define MIC_VA_BASE             IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-#define SIC1_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-#define SIC2_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-
-/* Manual: Chapter 20, page 195 */
-
-#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
-
-#define INTC_ER(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
-#define INTC_RSR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
-#define INTC_SR(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
-#define INTC_APR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
-#define INTC_ATR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
-#define INTC_ITR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern void __init pnx4008_init_irq(void);
-
-#endif /* __PNX4008_IRQ_H__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/irqs.h b/arch/arm/mach-pnx4008/include/mach/irqs.h
deleted file mode 100644
index f6b33cf23ae2..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/irqs.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irqs.h
- *
- * PNX4008 IRQ controller driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_IRQS_h__
-#define __PNX4008_IRQS_h__
-
-#define NR_IRQS         96
-
-/*Manual: table 259, page 199*/
-
-/*SUB2 Interrupt Routing (SIC2)*/
-
-#define SIC2_BASE_INT   64
-
-#define CLK_SWITCH_ARM_INT 95   /*manual: Clkswitch ARM  */
-#define CLK_SWITCH_DSP_INT 94   /*manual: ClkSwitch DSP  */
-#define CLK_SWITCH_AUD_INT 93   /*manual: Clkswitch AUD  */
-#define GPI_06_INT         92
-#define GPI_05_INT         91
-#define GPI_04_INT         90
-#define GPI_03_INT         89
-#define GPI_02_INT         88
-#define GPI_01_INT         87
-#define GPI_00_INT         86
-#define BT_CLKREQ_INT      85
-#define SPI1_DATIN_INT     84
-#define U5_RX_INT          83
-#define SDIO_INT_N         82
-#define CAM_HS_INT         81
-#define CAM_VS_INT         80
-#define GPI_07_INT         79
-#define DISP_SYNC_INT      78
-#define DSP_INT8           77
-#define U7_HCTS_INT        76
-#define GPI_10_INT         75
-#define GPI_09_INT         74
-#define GPI_08_INT         73
-#define DSP_INT7           72
-#define U2_HCTS_INT        71
-#define SPI2_DATIN_INT     70
-#define GPIO_05_INT        69
-#define GPIO_04_INT        68
-#define GPIO_03_INT        67
-#define GPIO_02_INT        66
-#define GPIO_01_INT        65
-#define GPIO_00_INT        64
-
-/*Manual: table 258, page 198*/
-
-/*SUB1 Interrupt Routing (SIC1)*/
-
-#define SIC1_BASE_INT   32
-
-#define USB_I2C_INT        63
-#define USB_DEV_HP_INT     62
-#define USB_DEV_LP_INT     61
-#define USB_DEV_DMA_INT    60
-#define USB_HOST_INT       59
-#define USB_OTG_ATX_INT_N  58
-#define USB_OTG_TIMER_INT  57
-#define SW_INT             56
-#define SPI1_INT           55
-#define KEY_IRQ            54
-#define DSP_M_INT          53
-#define RTC_INT            52
-#define I2C_1_INT          51
-#define I2C_2_INT          50
-#define PLL1_LOCK_INT      49
-#define PLL2_LOCK_INT      48
-#define PLL3_LOCK_INT      47
-#define PLL4_LOCK_INT      46
-#define PLL5_LOCK_INT      45
-#define SPI2_INT           44
-#define DSP_INT1           43
-#define DSP_INT2           42
-#define DSP_TDM_INT2       41
-#define TS_AUX_INT         40
-#define TS_IRQ             39
-#define TS_P_INT           38
-#define UOUT1_TO_PAD_INT   37
-#define GPI_11_INT         36
-#define DSP_INT4           35
-#define JTAG_COMM_RX_INT   34
-#define JTAG_COMM_TX_INT   33
-#define DSP_INT3           32
-
-/*Manual: table 257, page 197*/
-
-/*MAIN Interrupt Routing*/
-
-#define MAIN_BASE_INT   0
-
-#define SUB2_FIQ_N         31   /*active low */
-#define SUB1_FIQ_N         30   /*active low */
-#define JPEG_INT           29
-#define DMA_INT            28
-#define MSTIMER_INT        27
-#define IIR1_INT           26
-#define IIR2_INT           25
-#define IIR7_INT           24
-#define DSP_TDM_INT0       23
-#define DSP_TDM_INT1       22
-#define DSP_P_INT          21
-#define DSP_INT0           20
-#define DUM_INT            19
-#define UOUT0_TO_PAD_INT   18
-#define MP4_ENC_INT        17
-#define MP4_DEC_INT        16
-#define SD0_INT            15
-#define MBX_INT            14
-#define SD1_INT            13
-#define MS_INT_N           12
-#define FLASH_INT          11 /*NAND*/
-#define IIR6_INT           10
-#define IIR5_INT           9
-#define IIR4_INT           8
-#define IIR3_INT           7
-#define WATCH_INT          6
-#define HSTIMER_INT        5
-#define ARCH_TIMER_IRQ     HSTIMER_INT
-#define CAM_INT            4
-#define PRNG_INT           3
-#define CRYPTO_INT         2
-#define SUB2_IRQ_N         1    /*active low */
-#define SUB1_IRQ_N         0    /*active low */
-
-#define PNX4008_IRQ_TYPES \
-{                                           /*IRQ #'s: */         \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /*  0, 1, 2, 3 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  4, 5, 6, 7 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  8, 9,10,11 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 28,29,30,31 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */  \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 48,49,50,51 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */     \
-}
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-
-#endif /* __PNX4008_IRQS_h__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/platform.h b/arch/arm/mach-pnx4008/include/mach/platform.h
deleted file mode 100644
index 368c2c10a308..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/platform.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/platform.h
- *
- * PNX4008 Base addresses - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-
-#ifndef __ASM_ARCH_PLATFORM_H__
-#define __ASM_ARCH_PLATFORM_H__
-
-#define PNX4008_IRAM_BASE               0x08000000
-#define PNX4008_IRAM_SIZE               0x00010000
-#define PNX4008_YUV_SLAVE_BASE          0x10000000
-#define PNX4008_DUM_SLAVE_BASE          0x18000000
-#define PNX4008_NDF_FLASH_BASE          0x20020000
-#define PNX4008_SPI1_BASE               0x20088000
-#define PNX4008_SPI2_BASE               0x20090000
-#define PNX4008_SD_CONFIG_BASE          0x20098000
-#define PNX4008_FLASH_DATA              0x200B0000
-#define PNX4008_MLC_FLASH_BASE          0x200B8000
-#define PNX4008_JPEG_CONFIG_BASE        0x300A0000
-#define PNX4008_DMA_CONFIG_BASE         0x31000000
-#define PNX4008_USB_CONFIG_BASE         0x31020000
-#define PNX4008_SDRAM_CFG_BASE          0x31080000
-#define PNX4008_AHB2FAB_BASE            0x40000000
-#define PNX4008_PWRMAN_BASE             0x40004000
-#define PNX4008_INTCTRLMIC_BASE         0x40008000
-#define PNX4008_INTCTRLSIC1_BASE        0x4000C000
-#define PNX4008_INTCTRLSIC2_BASE        0x40010000
-#define PNX4008_HSUART1_BASE            0x40014000
-#define PNX4008_HSUART2_BASE            0x40018000
-#define PNX4008_HSUART7_BASE            0x4001C000
-#define PNX4008_RTC_BASE                0x40024000
-#define PNX4008_PIO_BASE                0x40028000
-#define PNX4008_MSTIMER_BASE            0x40034000
-#define PNX4008_HSTIMER_BASE            0x40038000
-#define PNX4008_WDOG_BASE               0x4003C000
-#define PNX4008_DEBUG_BASE              0x40040000
-#define PNX4008_TOUCH1_BASE             0x40048000
-#define PNX4008_KEYSCAN_BASE            0x40050000
-#define PNX4008_UARTCTRL_BASE           0x40054000
-#define PNX4008_PWM_BASE                0x4005C000
-#define PNX4008_UART3_BASE              0x40080000
-#define PNX4008_UART4_BASE              0x40088000
-#define PNX4008_UART5_BASE              0x40090000
-#define PNX4008_UART6_BASE              0x40098000
-#define PNX4008_I2C1_BASE               0x400A0000
-#define PNX4008_I2C2_BASE               0x400A8000
-#define PNX4008_MAGICGATE_BASE          0x400B0000
-#define PNX4008_DUMCONF_BASE            0x400B8000
-#define PNX4008_DUM_MAINCFG_BASE        0x400BC000
-#define PNX4008_DSP_BASE                0x400C0000
-#define PNX4008_PROFCOUNTER_BASE        0x400C8000
-#define PNX4008_CRYPTO_BASE             0x400D0000
-#define PNX4008_CAMIFCONF_BASE          0x400D8000
-#define PNX4008_YUV2RGB_BASE            0x400E0000
-#define PNX4008_AUDIOCONFIG_BASE        0x400E8000
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/pm.h b/arch/arm/mach-pnx4008/include/mach/pm.h
deleted file mode 100644
index 2fa685bff858..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/pm.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/pm.h
- *
- * PNX4008 Power Management Routiness - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARCH_PNX4008_PM_H
-#define __ASM_ARCH_PNX4008_PM_H
-
-#ifndef __ASSEMBLER__
-#include "irq.h"
-#include "irqs.h"
-#include "clock.h"
-
-extern void pnx4008_pm_idle(void);
-extern void pnx4008_pm_suspend(void);
-extern unsigned int pnx4008_cpu_suspend_sz;
-extern void pnx4008_cpu_suspend(void);
-extern unsigned int pnx4008_cpu_standby_sz;
-extern void pnx4008_cpu_standby(void);
-
-extern int pnx4008_startup_pll(struct clk *);
-extern int pnx4008_shutdown_pll(struct clk *);
-
-#endif                          /* ASSEMBLER */
-#endif                          /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
deleted file mode 100644
index b383c7de7ab4..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PNX4008_TIMEX_H
-#define __PNX4008_TIMEX_H
-
-#define CLOCK_TICK_RATE         1000000
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/uncompress.h b/arch/arm/mach-pnx4008/include/mach/uncompress.h
deleted file mode 100644
index bb4751ee2539..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2006 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define UART5_BASE 0x40090000
-
-#define UART5_DR    (*(volatile unsigned char *) (UART5_BASE))
-#define UART5_FR    (*(volatile unsigned char *) (UART5_BASE + 18))
-
-static __inline__ void putc(char c)
-{
-        while (UART5_FR & (1 << 5))
-                barrier();
-
-        UART5_DR = c;
-}
-
-/*
- * This does not append a newline
- */
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
deleted file mode 100644
index 41e4201972d5..000000000000
--- a/arch/arm/mach-pnx4008/irq.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/irq.c
- *
- * PNX4008 IRQ controller driver
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <mach/irq.h>
-
-static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
-
-static void pnx4008_mask_irq(struct irq_data *d)
-{
-        __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));        /* mask interrupt */
-}
-
-static void pnx4008_unmask_irq(struct irq_data *d)
-{
-        __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */
-}
-
-static void pnx4008_mask_ack_irq(struct irq_data *d)
-{
-        __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));        /* mask interrupt */
-        __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq));        /* clear interrupt status */
-}
-
-static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
-{
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
-                __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /*rising edge */
-                irq_set_handler(d->irq, handle_edge_irq);
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
-                __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*falling edge */
-                irq_set_handler(d->irq, handle_edge_irq);
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
-                __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*low level */
-                irq_set_handler(d->irq, handle_level_irq);
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
-                __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /* high level */
-                irq_set_handler(d->irq, handle_level_irq);
-                break;
-
-        /* IRQ_TYPE_EDGE_BOTH is not supported */
-        default:
-                printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
-                return -1;
-        }
-        return 0;
-}
-
-static struct irq_chip pnx4008_irq_chip = {
-        .irq_ack = pnx4008_mask_ack_irq,
-        .irq_mask = pnx4008_mask_irq,
-        .irq_unmask = pnx4008_unmask_irq,
-        .irq_set_type = pnx4008_set_irq_type,
-};
-
-void __init pnx4008_init_irq(void)
-{
-        unsigned int i;
-
-        /* configure IRQ's */
-        for (i = 0; i < NR_IRQS; i++) {
-                set_irq_flags(i, IRQF_VALID);
-                irq_set_chip(i, &pnx4008_irq_chip);
-                pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
-        }
-
-        /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
-        pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
-                             pnx4008_irq_type[SUB1_IRQ_N]);
-        pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
-                             pnx4008_irq_type[SUB2_IRQ_N]);
-        pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
-                             pnx4008_irq_type[SUB1_FIQ_N]);
-        pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
-                             pnx4008_irq_type[SUB2_FIQ_N]);
-
-        /* mask all others */
-        __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
-                        (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
-                INTC_ER(MAIN_BASE_INT));
-        __raw_writel(0, INTC_ER(SIC1_BASE_INT));
-        __raw_writel(0, INTC_ER(SIC2_BASE_INT));
-}
-
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
deleted file mode 100644
index 26f8d06b142a..000000000000
--- a/arch/arm/mach-pnx4008/pm.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/pm.c
- *
- * Power Management driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/pm.h>
-#include <linux/rtc.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/suspend.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <asm/cacheflush.h>
-
-#include <mach/hardware.h>
-#include <mach/pm.h>
-#include <mach/clock.h>
-
-#define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE)
-
-static void *saved_sram;
-
-static struct clk *pll4_clk;
-
-static inline void pnx4008_standby(void)
-{
-        void (*pnx4008_cpu_standby_ptr) (void);
-
-        local_irq_disable();
-        local_fiq_disable();
-
-        clk_disable(pll4_clk);
-
-        /*saving portion of SRAM to be used by suspend function. */
-        memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz);
-
-        /*make sure SRAM copy gets physically written into SDRAM.
-           SDRAM will be placed into self-refresh during power down */
-        flush_cache_all();
-
-        /*copy suspend function into SRAM */
-        memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz);
-
-        /*do suspend */
-        pnx4008_cpu_standby_ptr = (void *)SRAM_VA;
-        pnx4008_cpu_standby_ptr();
-
-        /*restoring portion of SRAM that was used by suspend function */
-        memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz);
-
-        clk_enable(pll4_clk);
-
-        local_fiq_enable();
-        local_irq_enable();
-}
-
-static inline void pnx4008_suspend(void)
-{
-        void (*pnx4008_cpu_suspend_ptr) (void);
-
-        local_irq_disable();
-        local_fiq_disable();
-
-        clk_disable(pll4_clk);
-
-        __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-        __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
-        /*saving portion of SRAM to be used by suspend function. */
-        memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz);
-
-        /*make sure SRAM copy gets physically written into SDRAM.
-           SDRAM will be placed into self-refresh during power down */
-        flush_cache_all();
-
-        /*copy suspend function into SRAM */
-        memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz);
-
-        /*do suspend */
-        pnx4008_cpu_suspend_ptr = (void *)SRAM_VA;
-        pnx4008_cpu_suspend_ptr();
-
-        /*restoring portion of SRAM that was used by suspend function */
-        memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz);
-
-        clk_enable(pll4_clk);
-
-        local_fiq_enable();
-        local_irq_enable();
-}
-
-static int pnx4008_pm_enter(suspend_state_t state)
-{
-        switch (state) {
-        case PM_SUSPEND_STANDBY:
-                pnx4008_standby();
-                break;
-        case PM_SUSPEND_MEM:
-                pnx4008_suspend();
-                break;
-        }
-        return 0;
-}
-
-static int pnx4008_pm_valid(suspend_state_t state)
-{
-        return (state == PM_SUSPEND_STANDBY) ||
-               (state == PM_SUSPEND_MEM);
-}
-
-static const struct platform_suspend_ops pnx4008_pm_ops = {
-        .enter = pnx4008_pm_enter,
-        .valid = pnx4008_pm_valid,
-};
-
-int __init pnx4008_pm_init(void)
-{
-        u32 sram_size_to_allocate;
-
-        pll4_clk = clk_get(0, "ck_pll4");
-        if (IS_ERR(pll4_clk)) {
-                printk(KERN_ERR
-                       "PM Suspend cannot acquire ARM(PLL4) clock control\n");
-                return PTR_ERR(pll4_clk);
-        }
-
-        if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz)
-                sram_size_to_allocate = pnx4008_cpu_standby_sz;
-        else
-                sram_size_to_allocate = pnx4008_cpu_suspend_sz;
-
-        saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
-        if (!saved_sram) {
-                printk(KERN_ERR
-                       "PM Suspend: cannot allocate memory to save portion of SRAM\n");
-                clk_put(pll4_clk);
-                return -ENOMEM;
-        }
-
-        suspend_set_ops(&pnx4008_pm_ops);
-        return 0;
-}
diff --git a/arch/arm/mach-pnx4008/serial.c b/arch/arm/mach-pnx4008/serial.c
deleted file mode 100644
index 374c138ac1ac..000000000000
--- a/arch/arm/mach-pnx4008/serial.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/serial.c
- *
- *  PNX4008 UART initialization
- *
- *  Copyright:  MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include <mach/platform.h>
-#include <mach/hardware.h>
-
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-
-#include <mach/gpio-pnx4008.h>
-#include <mach/clock.h>
-
-#define UART_3          0
-#define UART_4          1
-#define UART_5          2
-#define UART_6          3
-#define UART_UNKNOWN    (-1)
-
-#define UART3_BASE_VA   IO_ADDRESS(PNX4008_UART3_BASE)
-#define UART4_BASE_VA   IO_ADDRESS(PNX4008_UART4_BASE)
-#define UART5_BASE_VA   IO_ADDRESS(PNX4008_UART5_BASE)
-#define UART6_BASE_VA   IO_ADDRESS(PNX4008_UART6_BASE)
-
-#define UART_FCR_OFFSET         8
-#define UART_FIFO_SIZE          64
-
-void pnx4008_uart_init(void)
-{
-        u32 tmp;
-        int i = UART_FIFO_SIZE;
-
-        __raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET);
-        __raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET);
-
-        /* Send a NULL to fix the UART HW bug */
-        __raw_writel(0x00, UART5_BASE_VA);
-        __raw_writel(0x00, UART3_BASE_VA);
-
-        while (i--) {
-                tmp = __raw_readl(UART5_BASE_VA);
-                tmp = __raw_readl(UART3_BASE_VA);
-        }
-        __raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET);
-        __raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET);
-
-        /* setup wakeup interrupt */
-        start_int_set_rising_edge(SE_U3_RX_INT);
-        start_int_ack(SE_U3_RX_INT);
-        start_int_umask(SE_U3_RX_INT);
-
-        start_int_set_rising_edge(SE_U5_RX_INT);
-        start_int_ack(SE_U5_RX_INT);
-        start_int_umask(SE_U5_RX_INT);
-}
-
diff --git a/arch/arm/mach-pnx4008/sleep.S b/arch/arm/mach-pnx4008/sleep.S
deleted file mode 100644
index f4eed495d295..000000000000
--- a/arch/arm/mach-pnx4008/sleep.S
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * linux/arch/arm/mach-pnx4008/sleep.S
- *
- * PNX4008 support for STOP mode and SDRAM self-refresh
- *
- * Authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/hardware.h>
-
-#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define PWR_CTRL_REG_OFFS 0x44
-
-#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
-#define MPMC_STATUS_REG_OFFS 0x4
-
-                .text
-
-ENTRY(pnx4008_cpu_suspend)
-        @this function should be entered in Direct run mode.
-
-        @ save registers on stack
-        stmfd   sp!, {r0 - r6, lr}
-
-        @ setup Power Manager base address in r4
-        @ and put it's value in r5
-        mov     r4, #(PWRMAN_VA_BASE & 0xff000000)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-        ldr     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ setup SDRAM controller base address in r2
-        @ and put it's value in r3
-        mov     r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-        ldr     r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        @ clear SDRAM self-refresh bit
-        and     r5, r5, #(~(1 << 9))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ do save current bit settings in r1
-        mov     r1, r5
-
-        @ set SDRAM self-refresh bit
-        orr     r5, r5, #(1 << 9)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ set SDRAM self-refresh bit latch
-        orr     r5, r5, #(1 << 8)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ clear SDRAM self-refresh bit
-        and     r5, r5, #(~(1 << 9))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ wait for SDRAM to get into self-refresh mode
-2:      ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-        tst     r3, #(1 << 2)
-        beq     2b
-
-        @ to prepare SDRAM to get out of self-refresh mode after wakeup
-        orr     r5, r5, #(1 << 7)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ do enter stop mode
-        orr     r5, r5, #(1 << 0)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-
-        @ sleeping now...
-
-        @ coming out of STOP mode into Direct Run mode
-        @ clear STOP mode and SDRAM self-refresh bits
-        str     r1, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ wait for SDRAM to get out self-refresh mode
-3:      ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-        tst     r3, #5
-        bne     3b
-
-        @ restore regs and return
-        ldmfd   sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_suspend_sz)
-        .word   . - pnx4008_cpu_suspend
-
-ENTRY(pnx4008_cpu_standby)
-        @ save registers on stack
-        stmfd   sp!, {r0 - r6, lr}
-
-        @ setup Power Manager base address in r4
-        @ and put it's value in r5
-        mov     r4, #(PWRMAN_VA_BASE & 0xff000000)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-        ldr     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ setup SDRAM controller base address in r2
-        @ and put it's value in r3
-        mov     r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-        ldr     r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        @ clear SDRAM self-refresh bit
-        and     r5, r5, #(~(1 << 9))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ do save current bit settings in r1
-        mov     r1, r5
-
-        @ set SDRAM self-refresh bit
-        orr     r5, r5, #(1 << 9)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ set SDRAM self-refresh bit latch
-        orr     r5, r5, #(1 << 8)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ clear SDRAM self-refresh bit
-        and     r5, r5, #(~(1 << 9))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ wait for SDRAM to get into self-refresh mode
-2:      ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-        tst     r3, #(1 << 2)
-        beq     2b
-
-        @ set 'get out of self-refresh mode after wakeup' bit
-        orr     r5, r5, #(1 << 7)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        mcr     p15, 0, r0, c7, c0, 4   @ kinda sleeping now...
-
-        @ set SDRAM self-refresh bit latch
-        orr     r5, r5, #(1 << 8)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-        @ wait for SDRAM to get out self-refresh mode
-3:      ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-        tst     r3, #5
-        bne     3b
-
-        @ restore regs and return
-        ldmfd   sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_standby_sz)
-        .word   . - pnx4008_cpu_standby
-
-ENTRY(pnx4008_cache_clean_invalidate)
-        stmfd   sp!, {r0 - r6, lr}
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
-#else
-1:      mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
-        bne     1b
-#endif
-        ldmfd   sp!, {r0 - r6, pc}
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
deleted file mode 100644
index 0cfe8af3d3be..000000000000
--- a/arch/arm/mach-pnx4008/time.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/time.c
- *
- * PNX4008 Timers
- *
- * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach/time.h>
-#include <asm/errno.h>
-
-#include "time.h"
-
-/*! Note: all timers are UPCOUNTING */
-
-/*!
- * Returns number of us since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long pnx4008_gettimeoffset(void)
-{
-        u32 ticks_to_match =
-            __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
-        u32 elapsed = LATCH - ticks_to_match;
-        return (elapsed * (tick_nsec / 1000)) / LATCH;
-}
-
-/*!
- * IRQ handler for the timer
- */
-static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
-{
-        if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
-
-                do {
-                        timer_tick();
-
-                        /*
-                         * this algorithm takes care of possible delay
-                         * for this interrupt handling longer than a normal
-                         * timer period
-                         */
-                        __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
-                                     HSTIM_MATCH0);
-                        __raw_writel(MATCH0_INT, HSTIM_INT);    /* clear interrupt */
-
-                        /*
-                         * The goal is to keep incrementing HSTIM_MATCH0
-                         * register until HSTIM_MATCH0 indicates time after
-                         * what HSTIM_COUNTER indicates.
-                         */
-                } while ((signed)
-                         (__raw_readl(HSTIM_MATCH0) -
-                          __raw_readl(HSTIM_COUNTER)) < 0);
-        }
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction pnx4008_timer_irq = {
-        .name = "PNX4008 Tick Timer",
-        .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler = pnx4008_timer_interrupt
-};
-
-/*!
- * Set up timer and timer interrupt.
- */
-static __init void pnx4008_setup_timer(void)
-{
-        __raw_writel(RESET_COUNT, MSTIM_CTRL);
-        while (__raw_readl(MSTIM_COUNTER)) ;    /* wait for reset to complete. 100% guarantee event */
-        __raw_writel(0, MSTIM_CTRL);    /* stop the timer */
-        __raw_writel(0, MSTIM_MCTRL);
-
-        __raw_writel(RESET_COUNT, HSTIM_CTRL);
-        while (__raw_readl(HSTIM_COUNTER)) ;    /* wait for reset to complete. 100% guarantee event */
-        __raw_writel(0, HSTIM_CTRL);
-        __raw_writel(0, HSTIM_MCTRL);
-        __raw_writel(0, HSTIM_CCR);
-        __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
-        __raw_writel(LATCH, HSTIM_MATCH0);
-        __raw_writel(MR0_INT, HSTIM_MCTRL);
-
-        setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
-
-        __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL);        /*start timer, stop when JTAG active */
-}
-
-/* Timer Clock Control in PM register */
-#define TIMCLK_CTRL_REG  IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
-#define WATCHDOG_CLK_EN                   1
-#define TIMER_CLK_EN                      2     /* HS and MS timers? */
-
-static u32 timclk_ctrl_reg_save;
-
-void pnx4008_timer_suspend(void)
-{
-        timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
-        __raw_writel(0, TIMCLK_CTRL_REG);       /* disable timers */
-}
-
-void pnx4008_timer_resume(void)
-{
-        __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG);    /* enable timers */
-}
-
-struct sys_timer pnx4008_timer = {
-        .init = pnx4008_setup_timer,
-        .offset = pnx4008_gettimeoffset,
-        .suspend = pnx4008_timer_suspend,
-        .resume = pnx4008_timer_resume,
-};
-
diff --git a/arch/arm/mach-pnx4008/time.h b/arch/arm/mach-pnx4008/time.h
deleted file mode 100644
index 75e88c570aa7..000000000000
--- a/arch/arm/mach-pnx4008/time.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef PNX_TIME_H
-#define PNX_TIME_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-
-#define TICKS2USECS(x)  (x)
-
-/* MilliSecond Timer - Chapter 21 Page 202 */
-
-#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
-#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
-#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
-#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
-#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
-#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
-
-/* High Speed Timer - Chpater 22, Page 205 */
-
-#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
-#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
-#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
-#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
-#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
-#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
-#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
-#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
-#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
-#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
-#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
-#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
-
-/* IMPORTANT: both timers are UPCOUNTING */
-
-/* xSTIM_MCTRL bit definitions */
-#define MR0_INT        1
-#define RESET_COUNT0   (1<<1)
-#define STOP_COUNT0    (1<<2)
-#define MR1_INT        (1<<3)
-#define RESET_COUNT1   (1<<4)
-#define STOP_COUNT1    (1<<5)
-#define MR2_INT        (1<<6)
-#define RESET_COUNT2   (1<<7)
-#define STOP_COUNT2    (1<<8)
-
-/* xSTIM_CTRL bit definitions */
-#define COUNT_ENAB     1
-#define RESET_COUNT    (1<<1)
-#define DEBUG_EN       (1<<2)
-
-/* xSTIM_INT bit definitions */
-#define MATCH0_INT     1
-#define MATCH1_INT     (1<<1)
-#define MATCH2_INT     (1<<2)
-#define RTC_TICK0      (1<<4)
-#define RTC_TICK1      (1<<5)
-
-#endif
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
new file mode 100644
index 000000000000..41fc85327673
--- /dev/null
+++ b/arch/arm/mach-prima2/Kconfig
@@ -0,0 +1,19 @@
+if ARCH_SIRF
+
+menu "CSR SiRF primaII/Marco/Polo Specific Features"
+
+config ARCH_PRIMA2
+        bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+        default y
+        select CPU_V7
+        select ZONE_DMA
+        select SIRF_IRQ
+        help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
+
+endmenu
+
+config SIRF_IRQ
+        bool
+
+endif
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 13dd1604d951..fc9ce22e2b5a 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,9 +1,8 @@
 obj-y := timer.o
-obj-y += irq.o
-obj-y += clock.o
 obj-y += rstc.o
-obj-y += prima2.o
+obj-y += common.o
 obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
+obj-$(CONFIG_SIRF_IRQ) += irq.o
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
deleted file mode 100644
index aebad7e565cf..000000000000
--- a/arch/arm/mach-prima2/clock.c
+++ /dev/null
@@ -1,510 +0,0 @@
-/*
- * Clock tree for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <asm/mach/map.h>
-#include <mach/map.h>
-
-#define SIRFSOC_CLKC_CLK_EN0    0x0000
-#define SIRFSOC_CLKC_CLK_EN1    0x0004
-#define SIRFSOC_CLKC_REF_CFG    0x0014
-#define SIRFSOC_CLKC_CPU_CFG    0x0018
-#define SIRFSOC_CLKC_MEM_CFG    0x001c
-#define SIRFSOC_CLKC_SYS_CFG    0x0020
-#define SIRFSOC_CLKC_IO_CFG     0x0024
-#define SIRFSOC_CLKC_DSP_CFG    0x0028
-#define SIRFSOC_CLKC_GFX_CFG    0x002c
-#define SIRFSOC_CLKC_MM_CFG     0x0030
-#define SIRFSOC_LKC_LCD_CFG     0x0034
-#define SIRFSOC_CLKC_MMC_CFG    0x0038
-#define SIRFSOC_CLKC_PLL1_CFG0  0x0040
-#define SIRFSOC_CLKC_PLL2_CFG0  0x0044
-#define SIRFSOC_CLKC_PLL3_CFG0  0x0048
-#define SIRFSOC_CLKC_PLL1_CFG1  0x004c
-#define SIRFSOC_CLKC_PLL2_CFG1  0x0050
-#define SIRFSOC_CLKC_PLL3_CFG1  0x0054
-#define SIRFSOC_CLKC_PLL1_CFG2  0x0058
-#define SIRFSOC_CLKC_PLL2_CFG2  0x005c
-#define SIRFSOC_CLKC_PLL3_CFG2  0x0060
-
-#define SIRFSOC_CLOCK_VA_BASE           SIRFSOC_VA(0x005000)
-
-#define KHZ     1000
-#define MHZ     (KHZ * KHZ)
-
-struct clk_ops {
-        unsigned long (*get_rate)(struct clk *clk);
-        long (*round_rate)(struct clk *clk, unsigned long rate);
-        int (*set_rate)(struct clk *clk, unsigned long rate);
-        int (*enable)(struct clk *clk);
-        int (*disable)(struct clk *clk);
-        struct clk *(*get_parent)(struct clk *clk);
-        int (*set_parent)(struct clk *clk, struct clk *parent);
-};
-
-struct clk {
-        struct clk *parent;     /* parent clk */
-        unsigned long rate;     /* clock rate in Hz */
-        signed char usage;      /* clock enable count */
-        signed char enable_bit; /* enable bit: 0 ~ 63 */
-        unsigned short regofs;  /* register offset */
-        struct clk_ops *ops;    /* clock operation */
-};
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-static inline unsigned long clkc_readl(unsigned reg)
-{
-        return readl(SIRFSOC_CLOCK_VA_BASE + reg);
-}
-
-static inline void clkc_writel(u32 val, unsigned reg)
-{
-        writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
-}
-
-/*
- * osc_rtc - real time oscillator - 32.768KHz
- * osc_sys - high speed oscillator - 26MHz
- */
-
-static struct clk clk_rtc = {
-        .rate = 32768,
-};
-
-static struct clk clk_osc = {
-        .rate = 26 * MHZ,
-};
-
-/*
- * std pll
- */
-static unsigned long std_pll_get_rate(struct clk *clk)
-{
-        unsigned long fin = clk_get_rate(clk->parent);
-        u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
-                SIRFSOC_CLKC_PLL1_CFG0;
-
-        if (clkc_readl(regcfg2) & BIT(2)) {
-                /* pll bypass mode */
-                clk->rate = fin;
-        } else {
-                /* fout = fin * nf / nr / od */
-                u32 cfg0 = clkc_readl(clk->regofs);
-                u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
-                u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
-                u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
-                WARN_ON(fin % MHZ);
-                clk->rate = fin / MHZ * nf / nr / od * MHZ;
-        }
-
-        return clk->rate;
-}
-
-static int std_pll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long fin, nf, nr, od, reg;
-
-        /*
-         * fout = fin * nf / (nr * od);
-         * set od = 1, nr = fin/MHz, so fout = nf * MHz
-         */
-
-        nf = rate / MHZ;
-        if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
-                return -EINVAL;
-
-        fin = clk_get_rate(clk->parent);
-        BUG_ON(fin < MHZ);
-
-        nr = fin / MHZ;
-        BUG_ON((fin % MHZ) || nr > BIT(6));
-
-        od = 1;
-
-        reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
-        clkc_writel(reg, clk->regofs);
-
-        reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
-        clkc_writel((nf >> 1) - 1, reg);
-
-        reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
-        while (!(clkc_readl(reg) & BIT(6)))
-                cpu_relax();
-
-        clk->rate = 0; /* set to zero will force recalculation */
-        return 0;
-}
-
-static struct clk_ops std_pll_ops = {
-        .get_rate = std_pll_get_rate,
-        .set_rate = std_pll_set_rate,
-};
-
-static struct clk clk_pll1 = {
-        .parent = &clk_osc,
-        .regofs = SIRFSOC_CLKC_PLL1_CFG0,
-        .ops = &std_pll_ops,
-};
-
-static struct clk clk_pll2 = {
-        .parent = &clk_osc,
-        .regofs = SIRFSOC_CLKC_PLL2_CFG0,
-        .ops = &std_pll_ops,
-};
-
-static struct clk clk_pll3 = {
-        .parent = &clk_osc,
-        .regofs = SIRFSOC_CLKC_PLL3_CFG0,
-        .ops = &std_pll_ops,
-};
-
-/*
- * clock domains - cpu, mem, sys/io
- */
-
-static struct clk clk_mem;
-
-static struct clk *dmn_get_parent(struct clk *clk)
-{
-        struct clk *clks[] = {
-                &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
-        };
-        u32 cfg = clkc_readl(clk->regofs);
-        WARN_ON((cfg & (BIT(3) - 1)) > 4);
-        return clks[cfg & (BIT(3) - 1)];
-}
-
-static int dmn_set_parent(struct clk *clk, struct clk *parent)
-{
-        const struct clk *clks[] = {
-                &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
-        };
-        u32 cfg = clkc_readl(clk->regofs);
-        int i;
-        for (i = 0; i < ARRAY_SIZE(clks); i++) {
-                if (clks[i] == parent) {
-                        cfg &= ~(BIT(3) - 1);
-                        clkc_writel(cfg | i, clk->regofs);
-                        /* BIT(3) - switching status: 1 - busy, 0 - done */
-                        while (clkc_readl(clk->regofs) & BIT(3))
-                                cpu_relax();
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-
-static unsigned long dmn_get_rate(struct clk *clk)
-{
-        unsigned long fin = clk_get_rate(clk->parent);
-        u32 cfg = clkc_readl(clk->regofs);
-        if (cfg & BIT(24)) {
-                /* fcd bypass mode */
-                clk->rate = fin;
-        } else {
-                /*
-                 * wait count: bit[19:16], hold count: bit[23:20]
-                 */
-                u32 wait = (cfg >> 16) & (BIT(4) - 1);
-                u32 hold = (cfg >> 20) & (BIT(4) - 1);
-
-                clk->rate = fin / (wait + hold + 2);
-        }
-
-        return clk->rate;
-}
-
-static int dmn_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long fin;
-        unsigned ratio, wait, hold, reg;
-        unsigned bits = (clk == &clk_mem) ? 3 : 4;
-
-        fin = clk_get_rate(clk->parent);
-        ratio = fin / rate;
-
-        if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
-                return -EINVAL;
-
-        WARN_ON(fin % rate);
-
-        wait = (ratio >> 1) - 1;
-        hold = ratio - wait - 2;
-
-        reg = clkc_readl(clk->regofs);
-        reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
-        reg |= (wait << 16) | (hold << 20) | BIT(25);
-        clkc_writel(reg, clk->regofs);
-
-        /* waiting FCD been effective */
-        while (clkc_readl(clk->regofs) & BIT(25))
-                cpu_relax();
-
-        clk->rate = 0; /* set to zero will force recalculation */
-
-        return 0;
-}
-
-/*
- * cpu clock has no FCD register in Prima2, can only change pll
- */
-static int cpu_set_rate(struct clk *clk, unsigned long rate)
-{
-        int ret1, ret2;
-        struct clk *cur_parent, *tmp_parent;
-
-        cur_parent = dmn_get_parent(clk);
-        BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
-
-        /* switch to tmp pll before setting parent clock's rate */
-        tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
-        ret1 = dmn_set_parent(clk, tmp_parent);
-        BUG_ON(ret1);
-
-        ret2 = clk_set_rate(cur_parent, rate);
-
-        ret1 = dmn_set_parent(clk, cur_parent);
-
-        clk->rate = 0; /* set to zero will force recalculation */
-
-        return ret2 ? ret2 : ret1;
-}
-
-static struct clk_ops cpu_ops = {
-        .get_parent = dmn_get_parent,
-        .set_parent = dmn_set_parent,
-        .set_rate = cpu_set_rate,
-};
-
-static struct clk clk_cpu = {
-        .parent = &clk_pll1,
-        .regofs = SIRFSOC_CLKC_CPU_CFG,
-        .ops = &cpu_ops,
-};
-
-
-static struct clk_ops msi_ops = {
-        .set_rate = dmn_set_rate,
-        .get_rate = dmn_get_rate,
-        .set_parent = dmn_set_parent,
-        .get_parent = dmn_get_parent,
-};
-
-static struct clk clk_mem = {
-        .parent = &clk_pll2,
-        .regofs = SIRFSOC_CLKC_MEM_CFG,
-        .ops = &msi_ops,
-};
-
-static struct clk clk_sys = {
-        .parent = &clk_pll3,
-        .regofs = SIRFSOC_CLKC_SYS_CFG,
-        .ops = &msi_ops,
-};
-
-static struct clk clk_io = {
-        .parent = &clk_pll3,
-        .regofs = SIRFSOC_CLKC_IO_CFG,
-        .ops = &msi_ops,
-};
-
-/*
- * on-chip clock sets
- */
-static struct clk_lookup onchip_clks[] = {
-        {
-                .dev_id = "rtc",
-                .clk = &clk_rtc,
-        }, {
-                .dev_id = "osc",
-                .clk = &clk_osc,
-        }, {
-                .dev_id = "pll1",
-                .clk = &clk_pll1,
-        }, {
-                .dev_id = "pll2",
-                .clk = &clk_pll2,
-        }, {
-                .dev_id = "pll3",
-                .clk = &clk_pll3,
-        }, {
-                .dev_id = "cpu",
-                .clk = &clk_cpu,
-        }, {
-                .dev_id = "mem",
-                .clk = &clk_mem,
-        }, {
-                .dev_id = "sys",
-                .clk = &clk_sys,
-        }, {
-                .dev_id = "io",
-                .clk = &clk_io,
-        },
-};
-
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return -EINVAL;
-
-        if (clk->parent)
-                clk_enable(clk->parent);
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (!clk->usage++ && clk->ops && clk->ops->enable)
-                clk->ops->enable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return;
-
-        WARN_ON(!clk->usage);
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (--clk->usage == 0 && clk->ops && clk->ops->disable)
-                clk->ops->disable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        if (clk->parent)
-                clk_disable(clk->parent);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return 0;
-
-        if (clk->rate)
-                return clk->rate;
-
-        if (clk->ops && clk->ops->get_rate)
-                return clk->ops->get_rate(clk);
-
-        return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return 0;
-
-        if (clk->ops && clk->ops->round_rate)
-                return clk->ops->round_rate(clk, rate);
-
-        return 0;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return -EINVAL;
-
-        if (!clk->ops || !clk->ops->set_rate)
-                return -EINVAL;
-
-        return clk->ops->set_rate(clk, rate);
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int ret;
-        unsigned long flags;
-
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return -EINVAL;
-
-        if (!clk->ops || !clk->ops->set_parent)
-                return -EINVAL;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        ret = clk->ops->set_parent(clk, parent);
-        if (!ret) {
-                parent->usage += clk->usage;
-                clk->parent->usage -= clk->usage;
-                BUG_ON(clk->parent->usage < 0);
-                clk->parent = parent;
-        }
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return NULL;
-
-        if (!clk->ops || !clk->ops->get_parent)
-                return clk->parent;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        clk->parent = clk->ops->get_parent(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-static void __init sirfsoc_clk_init(void)
-{
-        clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
-}
-
-static struct of_device_id clkc_ids[] = {
-        { .compatible = "sirf,prima2-clkc" },
-        {},
-};
-
-void __init sirfsoc_of_clk_init(void)
-{
-        struct device_node *np;
-        struct resource res;
-        struct map_desc sirfsoc_clkc_iodesc = {
-                .virtual = SIRFSOC_CLOCK_VA_BASE,
-                .type    = MT_DEVICE,
-        };
-
-        np = of_find_matching_node(NULL, clkc_ids);
-        if (!np)
-                panic("unable to find compatible clkc node in dtb\n");
-
-        if (of_address_to_resource(np, 0, &res))
-                panic("unable to find clkc range in dtb");
-        of_node_put(np);
-
-        sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
-        sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
-
-        iotable_init(&sirfsoc_clkc_iodesc, 1);
-
-        sirfsoc_clk_init();
-}
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/common.c
index 8f0429d4b79f..f25a54194639 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/common.c
@@ -30,21 +30,21 @@ void __init sirfsoc_init_late(void)
         sirfsoc_pm_init();
 }
 
-static const char *prima2cb_dt_match[] __initdata = {
-       "sirf,prima2-cb",
+#ifdef CONFIG_ARCH_PRIMA2
+static const char *prima2_dt_match[] __initdata = {
+       "sirf,prima2",
        NULL
 };
 
-MACHINE_START(PRIMA2_EVB, "prima2cb")
+DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
         /* Maintainer: Barry Song <baohua.song@csr.com> */
-        .atag_offset    = 0x100,
-        .init_early     = sirfsoc_of_clk_init,
         .map_io         = sirfsoc_map_lluart,
         .init_irq       = sirfsoc_of_irq_init,
         .timer          = &sirfsoc_timer,
         .dma_zone_size  = SZ_256M,
         .init_machine   = sirfsoc_mach_init,
         .init_late      = sirfsoc_init_late,
-        .dt_compat      = prima2cb_dt_match,
+        .dt_compat      = prima2_dt_match,
         .restart        = sirfsoc_restart,
 MACHINE_END
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
index 83125c6a30b3..0c898fcf909c 100644
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ b/arch/arm/mach-prima2/include/mach/uncompress.h
@@ -25,11 +25,11 @@ static __inline__ void putc(char c)
          * during kernel decompression, all mappings are flat:
          *  virt_addr == phys_addr
          */
-        while (__raw_readl(SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
+        while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
                 & SIRFSOC_UART1_TXFIFO_FULL)
                 barrier();
 
-        __raw_writel(c, SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
+        __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
 }
 
 static inline void flush(void)
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index a7b9415d30f8..7dee9176e77a 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -63,7 +63,7 @@ void __init sirfsoc_of_irq_init(void)
 
         np = of_find_matching_node(NULL, intc_ids);
         if (!np)
-                panic("unable to find compatible intc node in dtb\n");
+                return;
 
         sirfsoc_intc_base = of_iomap(np, 0);
         if (!sirfsoc_intc_base)
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index f224107de7bc..d95bf252f694 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -21,6 +21,8 @@
 #include <asm/sched_clock.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+
 #define SIRFSOC_TIMER_COUNTER_LO        0x0000
 #define SIRFSOC_TIMER_COUNTER_HI        0x0004
 #define SIRFSOC_TIMER_MATCH_0           0x0008
@@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void)
 static void __init sirfsoc_timer_init(void)
 {
         unsigned long rate;
+        struct clk *clk;
+
+        /* initialize clocking early, we want to set the OS timer */
+        sirfsoc_of_clk_init();
 
         /* timer's input clock is io clock */
-        struct clk *clk = clk_get_sys("io", NULL);
+        clk = clk_get_sys("io", NULL);
 
         BUG_ON(IS_ERR(clk));
 
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index fe2d1f80ef50..8e6288de69b9 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -25,6 +25,18 @@ config PXA_V7_MACH_AUTO
 if !ARCH_PXA_V7
 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
 
+config MACH_PXA3XX_DT
+        bool "Support PXA3xx platforms from device tree"
+        select PXA3xx
+        select CPU_PXA300
+        select POWER_SUPPLY
+        select HAVE_PWM
+        select USE_OF
+        help
+          Include support for Marvell PXA3xx based platforms using
+          the device tree. Needn't select any other machine while
+          MACH_PXA3XX_DT is enabled.
+
 config ARCH_LUBBOCK
         bool "Intel DBPXA250 Development Platform (aka Lubbock)"
         select PXA25x
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index be0f7df8685c..2bedc9ed076c 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -26,6 +26,9 @@ obj-$(CONFIG_CPU_PXA930)	+= pxa930.o
 
 # NOTE: keep the order of boards in accordance to their order in Kconfig
 
+# Device Tree support
+obj-$(CONFIG_MACH_PXA3XX_DT)    += pxa-dt.o
+
 # Intel/Marvell Dev Platforms
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
index ccdac4b6a469..ffa6d811aad8 100644
--- a/arch/arm/mach-pxa/am200epd.c
+++ b/arch/arm/mach-pxa/am200epd.c
@@ -32,7 +32,7 @@
 
 #include <mach/pxa25x.h>
 #include <mach/gumstix.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
index 76c4b9494031..3dfec1ec462d 100644
--- a/arch/arm/mach-pxa/am300epd.c
+++ b/arch/arm/mach-pxa/am300epd.c
@@ -30,7 +30,7 @@
 
 #include <mach/gumstix.h>
 #include <mach/mfp-pxa25x.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 9244493dbcb7..208229342514 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -45,12 +45,12 @@
 #include <mach/pxa27x.h>
 #include <mach/balloon3.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/pxa27x-udc.h>
-#include <mach/irda.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
index 2a37a9a8f621..d4e9499832dc 100644
--- a/arch/arm/mach-pxa/clock-pxa3xx.c
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -127,8 +127,10 @@ void clk_pxa3xx_cken_enable(struct clk *clk)
 
         if (clk->cken < 32)
                 CKENA |= mask;
-        else
+        else if (clk->cken < 64)
                 CKENB |= mask;
+        else
+                CKENC |= mask;
 }
 
 void clk_pxa3xx_cken_disable(struct clk *clk)
@@ -137,8 +139,10 @@ void clk_pxa3xx_cken_disable(struct clk *clk)
 
         if (clk->cken < 32)
                 CKENA &= ~mask;
-        else
+        else if (clk->cken < 64)
                 CKENB &= ~mask;
+        else
+                CKENC &= ~mask;
 }
 
 const struct clkops clk_pxa3xx_cken_ops = {
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 431ef56700c4..2503db9e3253 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -22,8 +22,8 @@
 #include <linux/spi/libertas_spi.h>
 
 #include <mach/pxa27x.h>
-#include <mach/ohci.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/mmc-pxamci.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index 8fa4ad27edf3..fc3afc7cd366 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -24,7 +24,7 @@
 #include <mach/pxa25x.h>
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/smemc.h>
 
 #include <asm/hardware/it8152.h>
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 3e4e9fe2d462..cc2b23afcaaf 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -48,12 +48,12 @@
 
 #include <mach/pxa300.h>
 #include <mach/pxa27x-udc.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <mach/ohci.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 #include <mach/audio.h>
-#include <mach/pxa3xx-u2d.h>
+#include <linux/platform_data/usb-pxa3xx-ulpi.h>
 
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c
index d28e802e2448..8404b24240ea 100644
--- a/arch/arm/mach-pxa/colibri-evalboard.c
+++ b/arch/arm/mach-pxa/colibri-evalboard.c
@@ -23,8 +23,8 @@
 
 #include <mach/pxa27x.h>
 #include <mach/colibri.h>
-#include <mach/mmc.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa27x-udc.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c
index 248804bb2c9d..2d4a7b4d5d78 100644
--- a/arch/arm/mach-pxa/colibri-pxa270-income.c
+++ b/arch/arm/mach-pxa/colibri-pxa270-income.c
@@ -27,11 +27,11 @@
 #include <asm/mach-types.h>
 
 #include <mach/hardware.h>
-#include <mach/mmc.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index bb6def8ec979..a9c9c163dd95 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -24,8 +24,8 @@
 
 #include <mach/pxa300.h>
 #include <mach/colibri.h>
-#include <mach/ohci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/audio.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index d88e7b37f1da..25515cd7e68f 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -25,8 +25,8 @@
 
 #include <mach/pxa320.h>
 #include <mach/colibri.h>
-#include <mach/pxafb.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/audio.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/udc.h>
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 68cc75fac219..8240291ab8cf 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -24,9 +24,9 @@
 #include <mach/pxa3xx-regs.h>
 #include <mach/mfp-pxa300.h>
 #include <mach/colibri.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index c1fe32db4755..7c83f52c549c 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -46,8 +46,8 @@
 #include <asm/mach/irq.h>
 
 #include <mach/pxa25x.h>
-#include <mach/irda.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/corgi.h>
 #include <mach/sharpsl_pm.h>
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 67f0de37f46e..7039f44b3647 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -23,8 +23,8 @@
 #include <asm/mach/arch.h>
 #include <mach/csb726.h>
 #include <mach/pxa27x.h>
-#include <mach/mmc.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/audio.h>
 #include <mach/smemc.h>
 
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 166eee5b8a70..ddaa04de8e22 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -6,19 +6,18 @@
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/i2c/pxa-i2c.h>
 
-#include <asm/pmu.h>
 #include <mach/udc.h>
-#include <mach/pxa3xx-u2d.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <mach/irda.h>
+#include <linux/platform_data/usb-pxa3xx-ulpi.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/irqs.h>
-#include <mach/ohci.h>
-#include <plat/pxa27x_keypad.h>
-#include <mach/camera.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/keypad-pxa27x.h>
+#include <linux/platform_data/camera-pxa.h>
 #include <mach/audio.h>
 #include <mach/hardware.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 
 #include "devices.h"
 #include "generic.h"
@@ -42,7 +41,7 @@ static struct resource pxa_resource_pmu = {
 
 struct platform_device pxa_device_pmu = {
         .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
         .resource       = &pxa_resource_pmu,
         .num_resources  = 1,
 };
@@ -384,9 +383,24 @@ struct platform_device pxa_device_asoc_platform = {
 
 static u64 pxaficp_dmamask = ~(u32)0;
 
+static struct resource pxa_ir_resources[] = {
+        [0] = {
+                .start  = IRQ_STUART,
+                .end    = IRQ_STUART,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start  = IRQ_ICP,
+                .end    = IRQ_ICP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 struct platform_device pxa_device_ficp = {
         .name           = "pxa2xx-ir",
         .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_ir_resources),
+        .resource       = pxa_ir_resources,
         .dev            = {
                 .dma_mask = &pxaficp_dmamask,
                 .coherent_dma_mask = 0xffffffff,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 97f82ad341bf..1b6411439ec8 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -42,11 +42,11 @@
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
-#include <mach/ohci.h>
-#include <mach/mmc.h>
-#include <plat/pxa27x_keypad.h>
-#include <mach/camera.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/keypad-pxa27x.h>
+#include <linux/platform_data/camera-pxa.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 4cb2391a782e..be2ee9bf5c6e 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -32,9 +32,9 @@
 #include <mach/eseries-gpio.h>
 #include <mach/eseries-irq.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/udc.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 15ab2533667d..dc58fa0edb66 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -29,11 +29,11 @@
 #include <asm/mach/arch.h>
 
 #include <mach/pxa27x.h>
-#include <mach/pxafb.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/hardware.h>
-#include <plat/pxa27x_keypad.h>
-#include <mach/camera.h>
+#include <linux/platform_data/keypad-pxa27x.h>
+#include <linux/platform_data/camera-pxa.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index e529a35a44ce..60755a6bb1c6 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -41,7 +41,7 @@
 #include <asm/mach/flash.h>
 
 #include <mach/pxa25x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/gumstix.h>
 
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index e6311988add2..5ecbd17b5641 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -45,7 +45,7 @@
 
 #include <mach/pxa27x.h>
 #include <mach/hx4700.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 
 #include <sound/ak4641.h>
 #include <video/platform_lcd.h>
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 6ff466bd43e8..c36151940d17 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -33,9 +33,9 @@
 
 #include <mach/pxa25x.h>
 #include <mach/idp.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/bitfield.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index 207ecb49a61b..f4d48d20754e 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -131,6 +131,7 @@
 #define AICSR           __REG(0x41340008)       /* Application Subsystem Interrupt Control/Status Register */
 #define CKENA           __REG(0x4134000C)       /* A Clock Enable Register */
 #define CKENB           __REG(0x41340010)       /* B Clock Enable Register */
+#define CKENC           __REG(0x41340024)       /* C Clock Enable Register */
 #define AC97_DIV        __REG(0x41340014)       /* AC97 clock divisor value register */
 
 #define ACCR_XPDIS              (1 << 31)       /* Core PLL Output Disable */
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 5dae15ea6718..b6cc1816463e 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -17,6 +17,8 @@
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/exception.h>
 
@@ -25,8 +27,6 @@
 
 #include "generic.h"
 
-#define IRQ_BASE                io_p2v(0x40d00000)
-
 #define ICIP                    (0x000)
 #define ICMR                    (0x004)
 #define ICLR                    (0x008)
@@ -48,22 +48,19 @@
  * This is for peripheral IRQs internal to the PXA chip.
  */
 
+static void __iomem *pxa_irq_base;
 static int pxa_internal_irq_nr;
-
-static inline int cpu_has_ipr(void)
-{
-        return !cpu_is_pxa25x();
-}
+static bool cpu_has_ipr;
 
 static inline void __iomem *irq_base(int i)
 {
-        static unsigned long phys_base[] = {
-                0x40d00000,
-                0x40d0009c,
-                0x40d00130,
+        static unsigned long phys_base_offset[] = {
+                0x0,
+                0x9c,
+                0x130,
         };
 
-        return io_p2v(phys_base[i]);
+        return pxa_irq_base + phys_base_offset[i];
 }
 
 void pxa_mask_irq(struct irq_data *d)
@@ -96,8 +93,8 @@ asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
         uint32_t icip, icmr, mask;
 
         do {
-                icip = __raw_readl(IRQ_BASE + ICIP);
-                icmr = __raw_readl(IRQ_BASE + ICMR);
+                icip = __raw_readl(pxa_irq_base + ICIP);
+                icmr = __raw_readl(pxa_irq_base + ICMR);
                 mask = icip & icmr;
 
                 if (mask == 0)
@@ -128,6 +125,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
         BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
 
         pxa_internal_irq_nr = irq_nr;
+        cpu_has_ipr = !cpu_is_pxa25x();
+        pxa_irq_base = io_p2v(0x40d00000);
 
         for (n = 0; n < irq_nr; n += 32) {
                 void __iomem *base = irq_base(n >> 5);
@@ -136,8 +135,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
                 __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
                 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
                         /* initialize interrupt priority */
-                        if (cpu_has_ipr())
-                                __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
+                        if (cpu_has_ipr)
+                                __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
 
                         irq = PXA_IRQ(i);
                         irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
@@ -168,9 +167,9 @@ static int pxa_irq_suspend(void)
                 __raw_writel(0, base + ICMR);
         }
 
-        if (cpu_has_ipr()) {
+        if (cpu_has_ipr) {
                 for (i = 0; i < pxa_internal_irq_nr; i++)
-                        saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
+                        saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
         }
 
         return 0;
@@ -187,11 +186,11 @@ static void pxa_irq_resume(void)
                 __raw_writel(0, base + ICLR);
         }
 
-        if (cpu_has_ipr())
+        if (cpu_has_ipr)
                 for (i = 0; i < pxa_internal_irq_nr; i++)
-                        __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
+                        __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
 
-        __raw_writel(1, IRQ_BASE + ICCR);
+        __raw_writel(1, pxa_irq_base + ICCR);
 }
 #else
 #define pxa_irq_suspend         NULL
@@ -202,3 +201,93 @@ struct syscore_ops pxa_irq_syscore_ops = {
         .suspend        = pxa_irq_suspend,
         .resume         = pxa_irq_resume,
 };
+
+#ifdef CONFIG_OF
+static struct irq_domain *pxa_irq_domain;
+
+static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
+                       irq_hw_number_t hw)
+{
+        void __iomem *base = irq_base(hw / 32);
+
+        /* initialize interrupt priority */
+        if (cpu_has_ipr)
+                __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
+
+        irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
+                                 handle_level_irq);
+        irq_set_chip_data(hw, base);
+        set_irq_flags(hw, IRQF_VALID);
+
+        return 0;
+}
+
+static struct irq_domain_ops pxa_irq_ops = {
+        .map    = pxa_irq_map,
+        .xlate  = irq_domain_xlate_onecell,
+};
+
+static const struct of_device_id intc_ids[] __initconst = {
+        { .compatible = "marvell,pxa-intc", },
+        {}
+};
+
+void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        struct pxa_intc_conf *conf;
+        struct resource res;
+        int n, ret;
+
+        node = of_find_matching_node(NULL, intc_ids);
+        if (!node) {
+                pr_err("Failed to find interrupt controller in arch-pxa\n");
+                return;
+        }
+        of_id = of_match_node(intc_ids, node);
+        conf = of_id->data;
+
+        ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
+                                   &pxa_internal_irq_nr);
+        if (ret) {
+                pr_err("Not found marvell,intc-nr-irqs property\n");
+                return;
+        }
+
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret < 0) {
+                pr_err("No registers defined for node\n");
+                return;
+        }
+        pxa_irq_base = io_p2v(res.start);
+
+        if (of_find_property(node, "marvell,intc-priority", NULL))
+                cpu_has_ipr = 1;
+
+        ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
+        if (ret < 0) {
+                pr_err("Failed to allocate IRQ numbers\n");
+                return;
+        }
+
+        pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
+                                               &pxa_irq_ops, NULL);
+        if (!pxa_irq_domain)
+                panic("Unable to add PXA IRQ domain\n");
+
+        irq_set_default_host(pxa_irq_domain);
+
+        for (n = 0; n < pxa_internal_irq_nr; n += 32) {
+                void __iomem *base = irq_base(n >> 5);
+
+                __raw_writel(0, base + ICMR);   /* disable all IRQs */
+                __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
+        }
+
+        /* only unmasked interrupts kick us out of idle */
+        __raw_writel(1, irq_base(0) + ICCR);
+
+        pxa_internal_irq_chip.irq_set_wake = fn;
+}
+#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 1fb86edb857c..402874f9021f 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -42,11 +42,11 @@
 #include <asm/mach/irq.h>
 
 #include <mach/pxa300.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/littleton.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index cee9ce2fc0b5..1a63eaa89867 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -41,10 +41,10 @@
 #include <mach/pxa27x.h>
 #include <mach/lpd270.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <mach/irda.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/smemc.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 0ca0db787903..44dd7565707e 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -46,9 +46,9 @@
 #include <mach/audio.h>
 #include <mach/lubbock.h>
 #include <mach/udc.h>
-#include <mach/irda.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/pm.h>
 #include <mach/smemc.h>
 
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 39561dcf65f2..f7922404d941 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -38,10 +38,10 @@
 
 #include <mach/pxa27x.h>
 #include <mach/magician.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <mach/irda.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 1aebaf719462..5d9475730a3f 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -45,11 +45,11 @@
 #include <mach/pxa27x.h>
 #include <mach/mainstone.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <mach/irda.h>
-#include <mach/ohci.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/smemc.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index bf99022b021f..2831308dba68 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -46,12 +46,12 @@
 
 #include <mach/pxa27x.h>
 #include <mach/regs-rtc.h>
-#include <plat/pxa27x_keypad.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/keypad-pxa27x.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/pxa27x-udc.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 #include <mach/audio.h>
 #include <mach/smemc.h>
 #include <media/soc_camera.h>
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index 83570a79e7d2..d04ed4961e60 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -24,11 +24,11 @@
 #include <linux/gpio.h>
 #include <linux/i2c/pxa-i2c.h>
 
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa320.h>
 
 #include <mach/mxm8x10.h>
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index dad71cfa34c8..17d4c53017ca 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -29,11 +29,11 @@
 
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 31e0433d83ba..8bcc96e3b0db 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -35,11 +35,11 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmld.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <mach/irda.h>
-#include <plat/pxa27x_keypad.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/keypad-pxa27x.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 0f6bd4fcfa3b..5ca7b904a30e 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -36,12 +36,12 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmt5.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <mach/irda.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index e2d97eed07a7..ca924cfedfc0 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -34,9 +34,9 @@
 #include <mach/pxa25x.h>
 #include <mach/audio.h>
 #include <mach/palmtc.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/udc.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index c054827c567f..997e6da9a9c4 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -34,11 +34,11 @@
 #include <mach/pxa25x.h>
 #include <mach/audio.h>
 #include <mach/palmte2.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index fbdebee39a53..3f3c48f2f7ce 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -35,15 +35,15 @@
 #include <mach/pxa27x-udc.h>
 #include <mach/audio.h>
 #include <mach/palmtreo.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <mach/irda.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/udc.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/palmasoc.h>
-#include <mach/camera.h>
+#include <linux/platform_data/asoc-palm27x.h>
+#include <linux/platform_data/camera-pxa.h>
 #include <mach/palm27x.h>
 
 #include <sound/pxa2xx-lib.h>
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 0da35dccfd89..8b4366628a12 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -40,12 +40,12 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmtx.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <mach/irda.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index a97b59965bb9..8cdd4f58e253 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -40,16 +40,16 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmz72.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <mach/irda.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 
 #include <mach/pm.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 
 #include <media/soc_camera.h>
 
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index cb723e84bc27..113c57a03565 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -28,14 +28,14 @@
 
 #include <media/soc_camera.h>
 
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 #include <asm/mach/map.h>
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
-#include <mach/mmc.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pcm990_baseboard.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 89d98c832189..2910bb935c75 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -40,11 +40,11 @@
 #include <asm/mach/irq.h>
 
 #include <mach/pxa25x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/poodle.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 
 #include <asm/hardware/scoop.h>
 #include <asm/hardware/locomo.h>
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c
new file mode 100644
index 000000000000..c9192cea0033
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa-dt.c
@@ -0,0 +1,63 @@
+/*
+ *  linux/arch/arm/mach-pxa/pxa-dt.c
+ *
+ *  Copyright (C) 2012 Daniel Mack
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/pxa3xx.h>
+
+#include "generic.h"
+
+#ifdef CONFIG_PXA3xx
+extern void __init pxa3xx_dt_init_irq(void);
+
+static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40100000, "pxa2xx-uart.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40200000, "pxa2xx-uart.1", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40700000, "pxa2xx-uart.2", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x41600000, "pxa2xx-uart.3", NULL),
+        OF_DEV_AUXDATA("marvell,pxa-mmc",       0x41100000, "pxa2xx-mci.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-gpio",         0x40e00000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,pxa-ohci",      0x4c000000, "pxa27x-ohci", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-i2c",          0x40301680, "pxa2xx-i2c.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pwri2c",           0x40f500c0, "pxa3xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("marvell,pxa3xx-nand",   0x43100000, "pxa3xx-nand", NULL),
+        {}
+};
+
+static void __init pxa3xx_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             pxa3xx_auxdata_lookup, NULL);
+}
+
+static const char *pxa3xx_dt_board_compat[] __initdata = {
+        "marvell,pxa300",
+        "marvell,pxa310",
+        "marvell,pxa320",
+        NULL,
+};
+#endif
+
+#ifdef CONFIG_PXA3xx
+DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)")
+        .map_io         = pxa3xx_map_io,
+        .init_irq       = pxa3xx_dt_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
+        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
+        .init_machine   = pxa3xx_dt_init,
+        .dt_compat      = pxa3xx_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 4726c246dcdc..8047ee0effc5 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -30,7 +30,7 @@
 #include <mach/irqs.h>
 #include <mach/pxa27x.h>
 #include <mach/reset.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
 #include <mach/smemc.h>
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
index f8ec85450c42..447dcbb22f6f 100644
--- a/arch/arm/mach-pxa/pxa2xx.c
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -19,7 +19,7 @@
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa25x.h>
 #include <mach/reset.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 
 void pxa2xx_clear_reset_status(unsigned int mask)
 {
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
index 5ead6d480c6d..7dbe3ccf1993 100644
--- a/arch/arm/mach-pxa/pxa3xx-ulpi.c
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -27,7 +27,7 @@
 
 #include <mach/hardware.h>
 #include <mach/regs-u2d.h>
-#include <mach/pxa3xx-u2d.h>
+#include <linux/platform_data/usb-pxa3xx-ulpi.h>
 
 struct pxa3xx_u2d_ulpi {
         struct clk              *clk;
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index dffb7e813d98..656a1bb16d14 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/syscore_ops.h>
 #include <linux/i2c/pxa-i2c.h>
 
@@ -27,7 +28,7 @@
 #include <mach/hardware.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/reset.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
 #include <mach/smemc.h>
@@ -40,6 +41,8 @@
 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
 
+extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
+
 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -382,7 +385,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
         pxa_ext_wakeup_chip.irq_set_wake = fn;
 }
 
-void __init pxa3xx_init_irq(void)
+static void __init __pxa3xx_init_irq(void)
 {
         /* enable CP6 access */
         u32 value;
@@ -390,10 +393,23 @@ void __init pxa3xx_init_irq(void)
         value |= (1 << 6);
         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 
-        pxa_init_irq(56, pxa3xx_set_wake);
         pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
 }
 
+void __init pxa3xx_init_irq(void)
+{
+        __pxa3xx_init_irq();
+        pxa_init_irq(56, pxa3xx_set_wake);
+}
+
+#ifdef CONFIG_OF
+void __init pxa3xx_dt_init_irq(void)
+{
+        __pxa3xx_init_irq();
+        pxa_dt_irq_init(pxa3xx_set_wake);
+}
+#endif  /* CONFIG_OF */
+
 static struct map_desc pxa3xx_io_desc[] __initdata = {
         {       /* Mem Ctl */
                 .virtual        = (unsigned long)SMEMC_VIRT,
@@ -466,7 +482,8 @@ static int __init pxa3xx_init(void)
                 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa3xx_clock_syscore_ops);
 
-                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+                if (!of_have_populated_dt())
+                        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         }
 
         return ret;
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index d89d87ae144c..25b08bfa997b 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -49,10 +49,10 @@
 #include <asm/mach/arch.h>
 
 #include <mach/pxa300.h>
-#include <mach/ohci.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 86c95a5d8533..08d87a5d2639 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -32,7 +32,7 @@
 #include <asm/mach/flash.h>
 
 #include <mach/pxa930.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index bdf4cb88ca0a..9a154bad1984 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -879,7 +879,7 @@ static const struct platform_suspend_ops sharpsl_pm_ops = {
 
 static int __devinit sharpsl_pm_probe(struct platform_device *pdev)
 {
-        int ret;
+        int ret, irq;
 
         if (!pdev->dev.platform_data)
                 return -EINVAL;
@@ -907,24 +907,28 @@ static int __devinit sharpsl_pm_probe(struct platform_device *pdev)
         gpio_direction_input(sharpsl_pm.machinfo->gpio_batlock);
 
         /* Register interrupt handlers */
-        if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
-                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin));
+        irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_acin);
+        if (request_irq(irq, sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
+                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
         }
 
-        if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
-                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock));
+        irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock);
+        if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
+                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
         }
 
         if (sharpsl_pm.machinfo->gpio_fatal) {
-                if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
-                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal));
+                irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal);
+                if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
+                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
                 }
         }
 
         if (sharpsl_pm.machinfo->batfull_irq) {
                 /* Register interrupt handler. */
-                if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
-                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull));
+                irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull);
+                if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
+                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
                 }
         }
 
@@ -953,14 +957,14 @@ static int sharpsl_pm_remove(struct platform_device *pdev)
 
         led_trigger_unregister_simple(sharpsl_charge_led_trigger);
 
-        free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
-        free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
+        free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
+        free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
 
         if (sharpsl_pm.machinfo->gpio_fatal)
-                free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
+                free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
 
         if (sharpsl_pm.machinfo->batfull_irq)
-                free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
+                free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
 
         gpio_free(sharpsl_pm.machinfo->gpio_batlock);
         gpio_free(sharpsl_pm.machinfo->gpio_batfull);
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 363d91b44ecb..2073f0e6db0d 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -41,10 +41,10 @@
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
-#include <mach/irda.h>
-#include <mach/mmc.h>
-#include <mach/ohci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/spitz.h>
 #include <mach/sharpsl_pm.h>
 #include <mach/smemc.h>
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 30b1b0b3c7f7..08ea7a84a291 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -44,7 +44,7 @@
 #include <asm/mach/flash.h>
 
 #include <mach/pxa27x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/smemc.h>
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 736bfdc50ee6..1a25f8a7b0ce 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -24,8 +24,8 @@
 #include <asm/mach/arch.h>
 
 #include <mach/pxa930.h>
-#include <mach/pxafb.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 4d4eb60bad1e..233629edf7ee 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -42,8 +42,8 @@
 
 #include <mach/pxa25x.h>
 #include <mach/reset.h>
-#include <mach/irda.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/tosa_bt.h>
 #include <mach/audio.h>
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 166dd32cc1d3..fbbcbed4d1d4 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -43,10 +43,10 @@
 #include <mach/pxa27x.h>
 #include <mach/trizeps4.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <mach/irda.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/irda-pxaficp.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/smemc.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 130379fb9d0f..392412ce4dac 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -48,9 +48,9 @@
 
 #include <mach/pxa25x.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/regs-uart.h>
-#include <mach/arcom-pcmcia.h>
+#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
 #include <mach/viper.h>
 
 #include <asm/setup.h>
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index e1740acd15f1..491b6c9a2a9b 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -33,12 +33,12 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/vpac270.h>
-#include <mach/mmc.h>
-#include <mach/pxafb.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/udc.h>
-#include <mach/pata_pxa.h>
+#include <linux/platform_data/ata-pxa.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index b9320cb8a11f..97529face7aa 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -37,9 +37,9 @@
 #include <mach/pxa27x.h>
 #include <mach/mfp-pxa27x.h>
 #include <mach/z2.h>
-#include <mach/pxafb.h>
-#include <mach/mmc.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/video-pxafb.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/pm.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index af3d4f7646d7..abd3aa145083 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -38,14 +38,14 @@
 
 #include <mach/pxa27x.h>
 #include <mach/regs-uart.h>
-#include <mach/ohci.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/udc.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/pm.h>
 #include <mach/audio.h>
-#include <mach/arcom-pcmcia.h>
+#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
 #include <mach/zeus.h>
 #include <mach/smemc.h>
 
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 98eec80623e3..226279fac9d4 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -26,12 +26,12 @@
 #include <asm/mach/arch.h>
 #include <mach/pxa3xx.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/zylonite.h>
-#include <mach/mmc.h>
-#include <mach/ohci.h>
-#include <plat/pxa27x_keypad.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mmc-pxamci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/keypad-pxa27x.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 45868bb43cbd..ff007d15e0ec 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -30,7 +30,6 @@
 #include <linux/ata_platform.h>
 #include <linux/amba/mmci.h>
 #include <linux/gfp.h>
-#include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
@@ -226,115 +225,10 @@ struct mmci_platform_data realview_mmc1_plat_data = {
         .cd_invert      = true,
 };
 
-/*
- * Clock handling
- */
-static const struct icst_params realview_oscvco_params = {
-        .ref            = 24000000,
-        .vco_max        = ICST307_VCO_MAX,
-        .vco_min        = ICST307_VCO_MIN,
-        .vd_min         = 4 + 8,
-        .vd_max         = 511 + 8,
-        .rd_min         = 1 + 2,
-        .rd_max         = 127 + 2,
-        .s2div          = icst307_s2div,
-        .idx2s          = icst307_idx2s,
-};
-
-static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
-{
-        void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
-        u32 val;
-
-        val = readl(clk->vcoreg) & ~0x7ffff;
-        val |= vco.v | (vco.r << 9) | (vco.s << 16);
-
-        writel(0xa05f, sys_lock);
-        writel(val, clk->vcoreg);
-        writel(0, sys_lock);
-}
-
-static const struct clk_ops oscvco_clk_ops = {
-        .round  = icst_clk_round,
-        .set    = icst_clk_set,
-        .setvco = realview_oscvco_set,
-};
-
-static struct clk oscvco_clk = {
-        .ops    = &oscvco_clk_ops,
-        .params = &realview_oscvco_params,
-};
-
-/*
- * These are fixed clocks.
- */
-static struct clk ref24_clk = {
-        .rate   = 24000000,
-};
-
-static struct clk sp804_clk = {
-        .rate   = 1000000,
-};
-
-static struct clk dummy_apb_pclk;
-
-static struct clk_lookup lookups[] = {
-        {       /* Bus clock */
-                .con_id         = "apb_pclk",
-                .clk            = &dummy_apb_pclk,
-        }, {    /* UART0 */
-                .dev_id         = "dev:uart0",
-                .clk            = &ref24_clk,
-        }, {    /* UART1 */
-                .dev_id         = "dev:uart1",
-                .clk            = &ref24_clk,
-        }, {    /* UART2 */
-                .dev_id         = "dev:uart2",
-                .clk            = &ref24_clk,
-        }, {    /* UART3 */
-                .dev_id         = "fpga:uart3",
-                .clk            = &ref24_clk,
-        }, {    /* UART3 is on the dev chip in PB1176 */
-                .dev_id         = "dev:uart3",
-                .clk            = &ref24_clk,
-        }, {    /* UART4 only exists in PB1176 */
-                .dev_id         = "fpga:uart4",
-                .clk            = &ref24_clk,
-        }, {    /* KMI0 */
-                .dev_id         = "fpga:kmi0",
-                .clk            = &ref24_clk,
-        }, {    /* KMI1 */
-                .dev_id         = "fpga:kmi1",
-                .clk            = &ref24_clk,
-        }, {    /* MMC0 */
-                .dev_id         = "fpga:mmc0",
-                .clk            = &ref24_clk,
-        }, {    /* CLCD is in the PB1176 and EB DevChip */
-                .dev_id         = "dev:clcd",
-                .clk            = &oscvco_clk,
-        }, {    /* PB:CLCD */
-                .dev_id         = "issp:clcd",
-                .clk            = &oscvco_clk,
-        }, {    /* SSP */
-                .dev_id         = "dev:ssp0",
-                .clk            = &ref24_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .clk            = &sp804_clk,
-        },
-};
-
 void __init realview_init_early(void)
 {
         void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
 
-        if (machine_is_realview_pb1176())
-                oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
-        else
-                oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
         versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
 }
 
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index f8f2c0ac4c01..78cd970c80f2 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -56,4 +56,7 @@ extern void realview_init_early(void);
 extern void realview_fixup(struct tag *tags, char **from,
                            struct meminfo *meminfo);
 
+extern struct smp_operations realview_smp_ops;
+extern void realview_cpu_die(unsigned int cpu);
+
 #endif
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index 57d9efba2956..53818e5cd3ad 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -16,8 +16,6 @@
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
 
-extern volatile int pen_release;
-
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -89,17 +87,12 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
         }
 }
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
  * Called with IRQs disabled
  */
-void platform_cpu_die(unsigned int cpu)
+void __ref realview_cpu_die(unsigned int cpu)
 {
         int spurious = 0;
 
@@ -118,12 +111,3 @@ void platform_cpu_die(unsigned int cpu)
         if (spurious)
                 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-realview/include/mach/clkdev.h b/arch/arm/mach-realview/include/mach/clkdev.h
deleted file mode 100644
index e58d0771b64e..000000000000
--- a/arch/arm/mach-realview/include/mach/clkdev.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#include <plat/clock.h>
-
-struct clk {
-        unsigned long           rate;
-        const struct clk_ops    *ops;
-        const struct icst_params *params;
-        void __iomem            *vcoreg;
-};
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-realview/include/mach/gpio.h b/arch/arm/mach-realview/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-realview/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 17c878ddbc70..300f7064465d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -22,9 +22,9 @@
 #include <mach/board-pb11mp.h>
 #include <mach/board-pbx.h>
 
-#include "core.h"
+#include <plat/platsmp.h>
 
-extern void versatile_secondary_startup(void);
+#include "core.h"
 
 static void __iomem *scu_base_addr(void)
 {
@@ -43,7 +43,7 @@ static void __iomem *scu_base_addr(void)
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
-void __init smp_init_cpus(void)
+static void __init realview_smp_init_cpus(void)
 {
         void __iomem *scu_base = scu_base_addr();
         unsigned int i, ncores;
@@ -63,7 +63,7 @@ void __init smp_init_cpus(void)
         set_smp_cross_call(gic_raise_softirq);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
 {
 
         scu_enable(scu_base_addr());
@@ -77,3 +77,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
         __raw_writel(virt_to_phys(versatile_secondary_startup),
                      __io_address(REALVIEW_SYS_FLAGSSET));
 }
+
+struct smp_operations realview_smp_ops __initdata = {
+        .smp_init_cpus          = realview_smp_init_cpus,
+        .smp_prepare_cpus       = realview_smp_prepare_cpus,
+        .smp_secondary_init     = versatile_secondary_init,
+        .smp_boot_secondary     = versatile_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = realview_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index baf382c5e776..ce7747692c8b 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -27,12 +27,12 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -297,7 +297,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
         .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
         .num_resources          = ARRAY_SIZE(pmu_resources),
         .resource               = pmu_resources,
 };
@@ -414,6 +414,7 @@ static void __init realview_eb_timer_init(void)
         else
                 timer_irq = IRQ_EB_TIMER0_1;
 
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
         realview_timer_init(timer_irq);
         realview_eb_twd_init();
 }
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b1d7cafa1a6d..e21711d72ee2 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -29,12 +29,12 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -280,7 +280,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
         .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
         .num_resources          = 1,
         .resource               = &pmu_resource,
 };
@@ -326,6 +326,7 @@ static void __init realview_pb1176_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
 
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), true);
         realview_timer_init(IRQ_DC1176_TIMER0);
 }
 
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a98c536e3327..a80269981dd4 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -27,12 +27,12 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -263,7 +263,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
         .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
         .num_resources          = ARRAY_SIZE(pmu_resources),
         .resource               = pmu_resources,
 };
@@ -312,6 +312,7 @@ static void __init realview_pb11mp_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
 
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
         realview_timer_init(IRQ_TC11MP_TIMER0_1);
         realview_pb11mp_twd_init();
 }
@@ -366,6 +367,7 @@ static void __init realview_pb11mp_init(void)
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(realview_smp_ops),
         .fixup          = realview_fixup,
         .map_io         = realview_pb11mp_map_io,
         .init_early     = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 59650174e6ed..1435cd863965 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -27,11 +27,11 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 
@@ -241,7 +241,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
         .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
         .num_resources          = 1,
         .resource               = &pmu_resource,
 };
@@ -261,6 +261,7 @@ static void __init realview_pba8_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20;
 
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
         realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
 
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3f2f605624e9..a4b1aa93bb5a 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -26,11 +26,11 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/smp_twd.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
@@ -280,7 +280,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
         .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
         .num_resources          = ARRAY_SIZE(pmu_resources),
         .resource               = pmu_resources,
 };
@@ -320,6 +320,7 @@ static void __init realview_pbx_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
 
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
         realview_timer_init(IRQ_PBX_TIMER0_1);
         realview_pbx_twd_init();
 }
@@ -403,6 +404,7 @@ static void __init realview_pbx_init(void)
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(realview_smp_ops),
         .fixup          = realview_pbx_fixup,
         .map_io         = realview_pbx_map_io,
         .init_early     = realview_init_early,
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 87e75a250d5e..3b2cf6db3634 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -37,9 +37,9 @@
 #include <asm/irq.h>
 
 #include <mach/regs-gpio.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 
 #include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index a5eeb62ce1c2..57aee916bdb1 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
@@ -138,19 +138,7 @@ static struct platform_driver h1940bt_driver = {
         .remove         = h1940bt_remove,
 };
 
-
-static int __init h1940bt_init(void)
-{
-        return platform_driver_register(&h1940bt_driver);
-}
-
-static void __exit h1940bt_exit(void)
-{
-        platform_driver_unregister(&h1940bt_driver);
-}
-
-module_init(h1940bt_init);
-module_exit(h1940bt_exit);
+module_platform_driver(h1940bt_driver);
 
 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
 MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip");
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index ea2c4b003d58..f4ad99c1e476 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -53,7 +53,7 @@
 #include <mach/regs-lcd.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 5a7d0c0010f7..1ee8c4638743 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -40,8 +40,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <plat/nand.h>
-#include <plat/iic.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -53,7 +53,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/audio-simtec.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
 
 #include "simtec.h"
 #include "common.h"
@@ -424,7 +424,8 @@ static void __init anubis_map_io(void)
                 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
         } else {
                 /* ensure that the GPIO is setup */
-                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+                gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+                gpio_free(S3C2410_GPA(0));
         }
 }
 
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 7a05abf1270b..00381fe5de32 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -36,8 +36,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <plat/nand.h>
-#include <plat/iic.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -47,7 +47,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/mci.h>
+#include <linux/platform_data/mmc-s3cmci.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 1cf1720682d3..6a30ce7e4aa7 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -45,9 +45,9 @@
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 
-#include <plat/hwmon.h>
-#include <plat/nand.h>
-#include <plat/iic.h>
+#include <linux/platform_data/hwmon-s3c.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
 
 #include <linux/mtd/mtd.h>
@@ -62,7 +62,7 @@
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
 #include <plat/gpio-cfg.h>
-#include <plat/audio-simtec.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
 
 #include "simtec.h"
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 92e1f93a6bca..4a963467b7ee 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -73,21 +73,21 @@
 #include <mach/regs-gpio.h>
 #include <mach/fb.h>
 
-#include <plat/usb-control.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <mach/regs-mem.h>
 #include <mach/hardware.h>
 
 #include <mach/gta02.h>
 
 #include <plat/regs-serial.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
-#include <plat/ts.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index bb8d008d5a5c..9638b337593c 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -56,8 +56,8 @@
 #include <mach/h1940.h>
 #include <mach/h1940-latch.h>
 #include <mach/fb.h>
-#include <plat/udc.h>
-#include <plat/iic.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
@@ -65,8 +65,8 @@
 #include <plat/cpu.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
-#include <plat/mci.h>
-#include <plat/ts.h>
+#include <linux/platform_data/mmc-s3cmci.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include <sound/uda1380.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index ae73ba34ecc6..c9954e26b492 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -32,8 +32,8 @@
 #include <asm/mach/irq.h>
 
 #include <plat/regs-serial.h>
-#include <plat/nand.h>
-#include <plat/iic.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
@@ -54,7 +54,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 
 static struct map_desc jive_iodesc[] __initdata = {
 };
@@ -512,8 +512,8 @@ static void jive_power_off(void)
 {
         printk(KERN_INFO "powering system down...\n");
 
-        s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
-        s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+        gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPC(5));
 }
 
 static void __init jive_machine_init(void)
@@ -623,11 +623,11 @@ static void __init jive_machine_init(void)
         gpio_request(S3C2410_GPB(7), "jive spi");
         gpio_direction_output(S3C2410_GPB(7), 1);
 
-        s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
-        s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
+        gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
+        gpio_free(S3C2410_GPB(6));
 
-        s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
-        s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
+        gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPG(8));
 
         /* initialise the WM8750 spi */
 
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index bd6d2525debe..393c0f1ac11a 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -39,14 +39,14 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/irqs.h>
-#include <plat/nand.h>
-#include <plat/iic.h>
-#include <plat/mci.h>
-#include <plat/udc.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mmc-s3cmci.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -638,9 +638,9 @@ static void __init mini2440_init(void)
         gpio_free(S3C2410_GPG(4));
 
         /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
+        gpio_request_one(S3C2410_GPB(1), GPIOF_IN, NULL);
         s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
-        s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
-        s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
+        gpio_free(S3C2410_GPB(1));
 
         /* mark the key as input, without pullups (there is one on the board) */
         for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 383d00ca8f60..c53a9bfe1417 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -33,7 +33,7 @@
 #include <asm/mach-types.h>
 
 #include <mach/fb.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 
@@ -41,15 +41,15 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/regs-serial.h>
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/mci.h>
+#include <linux/platform_data/mmc-s3cmci.h>
 #include <plat/s3c2410.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 5c05ba1c330f..a2b92b0898e2 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -38,7 +38,7 @@
 //#include <asm/debug-ll.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/gpio-cfg.h>
 #include <plat/s3c2410.h>
@@ -119,17 +119,17 @@ static struct platform_device *nexcoder_devices[] __initdata = {
 
 static void __init nexcoder_sensorboard_init(void)
 {
-        // Initialize SCCB bus
-        s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
-        s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
-        s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
-
-        // Power up the sensor board
-        s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
-        s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
-        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-        s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
+        /* Initialize SCCB bus */
+        gpio_request_one(S3C2410_GPE(14), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPE(14)); /* IICSCL */
+        gpio_request_one(S3C2410_GPE(15), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPE(15)); /* IICSDA */
+
+        /* Power up the sensor board */
+        gpio_request_one(S3C2410_GPF(1), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPF(1)); /* CAM_GPIO7 => nLDO_PWRDN */
+        gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
+        gpio_free(S3C2410_GPF(2)); /* CAM_GPIO6 => CAM_PWRDN */
 }
 
 static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
index ad2792dfbee1..5876c6ba7500 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
@@ -175,18 +175,7 @@ static struct platform_driver osiris_dvs_driver = {
         },
 };
 
-static int __init osiris_dvs_init(void)
-{
-        return platform_driver_register(&osiris_dvs_driver);
-}
-
-static void __exit osiris_dvs_exit(void)
-{
-        platform_driver_unregister(&osiris_dvs_driver);
-}
-
-module_init(osiris_dvs_init);
-module_exit(osiris_dvs_exit);
+module_platform_driver(osiris_dvs_driver);
 
 MODULE_DESCRIPTION("Simtec OSIRIS DVS support");
 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 95d077255024..bb36d832bd3d 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -41,8 +41,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <plat/nand.h>
-#include <plat/iic.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -274,8 +274,8 @@ static int osiris_pm_suspend(void)
         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 
         /* ensure that an nRESET is not generated on resume. */
-        s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-        s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
+        gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPA(21));
 
         return 0;
 }
@@ -396,7 +396,8 @@ static void __init osiris_map_io(void)
                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
         } else {
                 /* write-protect line to the NAND */
-                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+                gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+                gpio_free(S3C2410_GPA(0));
         }
 
         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index bc4b6efb3b27..bca39f0232b3 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -35,7 +35,7 @@
 #include <plat/s3c2410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/cpu.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 678bbca2b5e5..7b6ba13d7285 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -47,13 +47,13 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-lcd.h>
 #include <plat/regs-serial.h>
 #include <mach/fb.h>
-#include <plat/nand.h>
-#include <plat/udc.h>
-#include <plat/iic.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 7ee73f27f207..379fde521d37 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -49,15 +49,15 @@
 #include <plat/clock.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-iic.h>
-#include <plat/mci.h>
-#include <plat/udc.h>
-#include <plat/nand.h>
-#include <plat/iic.h>
+#include <linux/platform_data/mmc-s3cmci.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <plat/irq.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include <sound/uda1380.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index 56af35447598..dacbb9a2122a 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -43,7 +43,7 @@
 #include <mach/regs-lcd.h>
 
 #include <mach/h1940.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <mach/fb.h>
 
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index bdc27e772876..82796b97cb04 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -47,7 +47,7 @@
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index b11451b853d8..ce99fd8bbbc5 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -38,8 +38,8 @@
 #include <mach/regs-lcd.h>
 
 #include <mach/idle.h>
-#include <plat/udc.h>
-#include <plat/iic.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
 
 #include <plat/s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index c3100a044fbe..db2787aa1e5e 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -39,17 +39,17 @@
 #include <mach/regs-s3c2443-clock.h>
 
 #include <mach/idle.h>
-#include <mach/leds-gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/leds-s3c24xx.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/s3c2416.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/sdhci.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/s3c-hsudc.h>
 
 #include <plat/regs-fb-v4.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 83a1036d7dcb..b7ff882c6ce6 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -37,7 +37,7 @@
 
 #include <mach/idle.h>
 #include <mach/fb.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/s3c2410.h>
 #include <plat/s3c244x.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 209236956222..2568656f046f 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -37,7 +37,7 @@
 
 #include <mach/idle.h>
 #include <mach/fb.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/s3c2410.h>
 #include <plat/s3c2443.h>
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index fe990289ee7d..495bf5cf52e9 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -45,7 +45,7 @@
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index bd5f189f0424..14d5b12e388c 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -43,13 +43,13 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
-#include <plat/audio-simtec.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
 
 #include "simtec.h"
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 94bfaa1fb148..f1d44ae11833 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -39,8 +39,8 @@
 #include <mach/idle.h>
 #include <mach/fb.h>
 
-#include <plat/iic.h>
-#include <plat/nand.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 
 #include <plat/s3c2410.h>
 #include <plat/s3c2412.h>
diff --git a/arch/arm/mach-s3c24xx/setup-i2c.c b/arch/arm/mach-s3c24xx/setup-i2c.c
index 9e90a7cbd1d6..7b4f33332d19 100644
--- a/arch/arm/mach-s3c24xx/setup-i2c.c
+++ b/arch/arm/mach-s3c24xx/setup-i2c.c
@@ -16,7 +16,7 @@
 struct platform_device;
 
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
diff --git a/arch/arm/mach-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c
index 11881c9a38c0..fd0ef05763a9 100644
--- a/arch/arm/mach-s3c24xx/simtec-audio.c
+++ b/arch/arm/mach-s3c24xx/simtec-audio.c
@@ -24,7 +24,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/audio-simtec.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
 #include <plat/devs.h>
 
 #include "simtec.h"
diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index d91c1a725139..17f8356177c1 100644
--- a/arch/arm/mach-s3c24xx/simtec-usb.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -34,7 +34,7 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 
-#include <plat/usb-control.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/devs.h>
 
 #include "simtec.h"
diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c
index 124fd5d63006..35f3e07eaccc 100644
--- a/arch/arm/mach-s3c64xx/dev-audio.c
+++ b/arch/arm/mach-s3c64xx/dev-audio.c
@@ -20,7 +20,7 @@
 #include <mach/dma.h>
 
 #include <plat/devs.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <plat/gpio-cfg.h>
 
 static const char *rclksrc[] = {
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index ffa29ddfdfce..15c58dfc4584 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -42,7 +42,7 @@
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
 #include <plat/regs-fb-v4.h>
 
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 9e382e7c77cb..181aa99427fe 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -24,7 +24,7 @@
 #include <sound/wm8962.h>
 #include <sound/wm9081.h>
 
-#include <plat/s3c64xx-spi.h>
+#include <linux/platform_data/spi-s3c64xx.h>
 
 #include <mach/crag6410.h>
 
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 09cd81207a3f..717d675188d4 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -61,14 +61,14 @@
 #include <plat/fb.h>
 #include <plat/sdhci.h>
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
+#include <linux/platform_data/spi-s3c64xx.h>
 
 #include <plat/keypad.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/adc.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 689088162f77..02222b32b7d3 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -34,9 +34,9 @@
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 
 #include <plat/clock.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 5539a255a704..09311cc40115 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -38,9 +38,9 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/regs-serial.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/regs-fb-v4.h>
 
 #include <video/platform_lcd.h>
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index cad2e05eddf7..46ee88d16815 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -37,7 +37,7 @@
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
 
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 326b21604bc3..6daca203e72b 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -39,9 +39,9 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/regs-serial.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/regs-fb-v4.h>
 
 #include <video/platform_lcd.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ceeb1de40376..c6d7390939ae 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -30,13 +30,13 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
-#include <plat/hwmon.h>
+#include <linux/platform_data/hwmon-s3c.h>
 #include <plat/regs-serial.h>
-#include <plat/usb-control.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/sdhci.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include <video/platform_lcd.h>
 
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index b0f4525c66bd..a928fae5694e 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -35,7 +35,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 0fe4f1503f4f..2547a8846472 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -60,8 +60,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-sys.h>
 #include <mach/regs-srom.h>
-#include <plat/ata.h>
-#include <plat/iic.h>
+#include <linux/platform_data/ata-samsung_cf.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
 
@@ -69,7 +69,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/adc.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
diff --git a/arch/arm/mach-s3c64xx/setup-i2c0.c b/arch/arm/mach-s3c64xx/setup-i2c0.c
index 241af94a9e70..40666ba8d607 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c0.c
+++ b/arch/arm/mach-s3c64xx/setup-i2c0.c
@@ -18,7 +18,7 @@
 
 struct platform_device; /* don't need the contents */
 
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s3c64xx/setup-i2c1.c b/arch/arm/mach-s3c64xx/setup-i2c1.c
index 3d13a961986d..3fdb24c4e62a 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c1.c
+++ b/arch/arm/mach-s3c64xx/setup-i2c1.c
@@ -18,7 +18,7 @@
 
 struct platform_device; /* don't need the contents */
 
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c
index 41b425602d88..648d8b85bf6b 100644
--- a/arch/arm/mach-s3c64xx/setup-ide.c
+++ b/arch/arm/mach-s3c64xx/setup-ide.c
@@ -17,7 +17,7 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
-#include <plat/ata.h>
+#include <linux/platform_data/ata-samsung_cf.h>
 
 void s3c64xx_ide_setup_gpio(void)
 {
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
index 91113ddc51da..a0d6edfd23a0 100644
--- a/arch/arm/mach-s5p64x0/dev-audio.c
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -13,7 +13,7 @@
 #include <linux/gpio.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 
 #include <mach/map.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 92fefad505cc..dea78a848244 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -45,10 +45,10 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pll.h>
 #include <plat/adc.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index e2335ecf6eae..6f14fc729b8f 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -45,10 +45,10 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pll.h>
 #include <plat/adc.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index 46b463917c54..a32edc545e6c 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -19,7 +19,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <mach/i2c.h>
 
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index 6ad3b986021c..ca2c5c7f8aa6 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -19,7 +19,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 #include <mach/i2c.h>
 
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
index 9d4bde3f1110..1cc252cef268 100644
--- a/arch/arm/mach-s5pc100/dev-audio.c
+++ b/arch/arm/mach-s5pc100/dev-audio.c
@@ -13,7 +13,7 @@
 #include <linux/gpio.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 
 #include <mach/map.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 0c3ae38d27ca..5d2c0934928b 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -44,12 +44,12 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
-#include <plat/iic.h>
-#include <plat/ata.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/ata-samsung_cf.h>
 #include <plat/adc.h>
 #include <plat/keypad.h>
-#include <plat/ts.h>
-#include <plat/audio.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
 
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
index eaef7a3bda49..89a6a769d622 100644
--- a/arch/arm/mach-s5pc100/setup-i2c0.c
+++ b/arch/arm/mach-s5pc100/setup-i2c0.c
@@ -18,7 +18,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
index aaff74a90dee..faa667ef02cb 100644
--- a/arch/arm/mach-s5pc100/setup-i2c1.c
+++ b/arch/arm/mach-s5pc100/setup-i2c1.c
@@ -18,7 +18,7 @@
 struct platform_device; /* don't need the contents */
 
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 8367749c3eec..0a5480bbcbd5 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -13,7 +13,7 @@
 #include <linux/gpio.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 
 #include <mach/map.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 822a55950685..00f1e47d490a 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -43,7 +43,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index dfc29236321c..d9c99fcc1aa7 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -27,8 +27,8 @@
 #include <plat/regs-serial.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/ata.h>
-#include <plat/iic.h>
+#include <linux/platform_data/ata-samsung_cf.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
 #include <plat/s5p-time.h>
 #include <plat/mfc.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 918b23d71fdf..7d6fab420508 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -38,9 +38,9 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/adc.h>
-#include <plat/ts.h>
-#include <plat/ata.h>
-#include <plat/iic.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/ata-samsung_cf.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/pm.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 74e99bc0dc9b..18785cb5e1ef 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -26,7 +26,7 @@
 #include <plat/regs-serial.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/s5p-time.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c
index 0f1cc3a1c1e8..4a15849766c0 100644
--- a/arch/arm/mach-s5pv210/setup-i2c0.c
+++ b/arch/arm/mach-s5pv210/setup-i2c0.c
@@ -18,7 +18,7 @@
 
 struct platform_device; /* don't need the contents */
 
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c
index f61365a34c56..4777f6b97a92 100644
--- a/arch/arm/mach-s5pv210/setup-i2c1.c
+++ b/arch/arm/mach-s5pv210/setup-i2c1.c
@@ -18,7 +18,7 @@
 
 struct platform_device; /* don't need the contents */
 
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c
index 2f91b5cefbc6..bbce6c74b915 100644
--- a/arch/arm/mach-s5pv210/setup-i2c2.c
+++ b/arch/arm/mach-s5pv210/setup-i2c2.c
@@ -18,7 +18,7 @@
 
 struct platform_device; /* don't need the contents */
 
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c2_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index d673211f121c..ba49241b02f0 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -37,7 +37,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
 #include <mach/assabet.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 09d7f4b4b354..985d0b584717 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -28,7 +28,7 @@
 #include <asm/mach/serial_sa1100.h>
 
 #include <mach/cerf.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index ea5cff38745c..170cb6107f68 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -45,7 +45,7 @@
 #include <asm/hardware/scoop.h>
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/locomo.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index cdea671e8931..ac2ea767215d 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -87,7 +87,7 @@
 #define SIMPAD_CS3_PCMCIA_SHORT         (SIMPAD_CS3_GPIO_BASE + 22)
 #define SIMPAD_CS3_GPIO_23              (SIMPAD_CS3_GPIO_BASE + 23)
 
-#define CS3_BASE        0xf1000000
+#define CS3_BASE        IOMEM(0xf1000000)
 
 long simpad_get_cs3_ro(void);
 long simpad_get_cs3_shadow(void);
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index b775a0abec0a..7dc1a89b1273 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -16,7 +16,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 5d33fc3108ef..ff6b7b35bca9 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -19,7 +19,7 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/shannon.h>
 #include <mach/irqs.h>
 
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index fbd53593be54..71790e581d93 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -24,7 +24,7 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/simpad.h>
 #include <mach/irqs.h>
 
@@ -124,7 +124,7 @@ static struct map_desc simpad_io_desc[] __initdata = {
                 .length         = 0x00800000,
                 .type           = MT_DEVICE
         }, {    /* Simpad CS3 */
-                .virtual        = CS3_BASE,
+                .virtual        = (unsigned long)CS3_BASE,
                 .pfn            = __phys_to_pfn(SA1100_CS3_PHYS),
                 .length         = 0x00100000,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 2704bcd869cd..d35b94ef73b7 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -21,9 +21,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#define IO_BASE                 0xe0000000
-#define IO_SIZE                 0x08000000
-#define IO_START                0x40000000
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
 
@@ -104,20 +101,6 @@ arch_initcall(shark_init);
 
 extern void shark_init_irq(void);
 
-static struct map_desc shark_io_desc[] __initdata = {
-        {
-                .virtual        = IO_BASE,
-                .pfn            = __phys_to_pfn(IO_START),
-                .length         = IO_SIZE,
-                .type           = MT_DEVICE
-        }
-};
-
-static void __init shark_map_io(void)
-{
-        iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc));
-}
-
 #define IRQ_TIMER 0
 #define HZ_TIME ((1193180 + HZ/2) / HZ)
 
@@ -158,7 +141,6 @@ static void shark_init_early(void)
 MACHINE_START(SHARK, "Shark")
         /* Maintainer: Alexander Schulz */
         .atag_offset    = 0x3000,
-        .map_io         = shark_map_io,
         .init_early     = shark_init_early,
         .init_irq       = shark_init_irq,
         .timer          = &shark_timer,
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 20eb2bf2a42b..d129119a3f69 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -12,9 +12,10 @@
 */
 
                 .macro  addruart, rp, rv, tmp
-                mov     \rp, #0xe0000000
-                orr     \rp, \rp, #0x000003f8
-                mov     \rv, \rp
+                mov     \rp, #0x3f8
+                orr     \rv, \rp, #0xfe000000
+                orr     \rv, \rv, #0x00e00000
+                orr     \rp, \rp, #0x40000000
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S
index 5901b09fc96a..c9e49f049532 100644
--- a/arch/arm/mach-shark/include/mach/entry-macro.S
+++ b/arch/arm/mach-shark/include/mach/entry-macro.S
@@ -8,7 +8,8 @@
  * warranty of any kind, whether express or implied.
  */
                 .macro  get_irqnr_preamble, base, tmp
-                mov     \base, #0xe0000000
+                mov     \base, #0xfe000000
+                orr     \base, \base, #0x00e00000
                 .endm
 
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
deleted file mode 100644
index 1a45fc01ff1d..000000000000
--- a/arch/arm/mach-shark/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-shark/include/mach/io.h
- *
- * by Alexander Schulz
- *
- * derived from:
- * arch/arm/mach-ebsa110/include/mach/io.h
- * Copyright (C) 1997,1998 Russell King
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)                 ((void __iomem *)(0xe0000000 + (a)))
-
-#endif
diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c
index 9089407d5326..b8b4ab323a3e 100644
--- a/arch/arm/mach-shark/pci.c
+++ b/arch/arm/mach-shark/pci.c
@@ -8,12 +8,15 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <video/vga.h>
 
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#define IO_START        0x40000000
+
 static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
         if (dev->bus->number == 0)
@@ -44,6 +47,8 @@ static int __init shark_pci_init(void)
         pcibios_min_mem = 0x50000000;
         vga_base = 0xe8000000;
 
+        pci_ioremap_io(0, IO_START);
+
         pci_common_init(&shark_pci);
 
         return 0;
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index d82c010fdfc6..25eb88a923e6 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -40,7 +40,6 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
-#include <linux/videodev2.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
 #include <sound/sh_fsi.h>
@@ -650,6 +649,7 @@ static void __init ag5evm_init(void)
 }
 
 MACHINE_START(AG5EVM, "ag5evm")
+        .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
         .init_early     = sh73a0_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index f172ca85905c..bc3b5da59e25 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -66,6 +66,8 @@
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
 
+#include "sh-gpio.h"
+
 /*
  * Address      Interface               BusWidth        note
  * ------------------------------------------------------------------
@@ -432,7 +434,7 @@ static void usb1_host_port_power(int port, int power)
                 return;
 
         /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
-        __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
+        __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
 }
 
 static struct r8a66597_platdata usb1_host_data = {
@@ -1224,9 +1226,9 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 
-#define GPIO_PORT9CR    0xE6051009
-#define GPIO_PORT10CR   0xE605100A
-#define USCCR1          0xE6058144
+#define GPIO_PORT9CR    IOMEM(0xE6051009)
+#define GPIO_PORT10CR   IOMEM(0xE605100A)
+#define USCCR1          IOMEM(0xE6058144)
 static void __init ap4evb_init(void)
 {
         u32 srcr4;
@@ -1304,7 +1306,7 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_OVCN2_1,    NULL);
 
         /* setup USB phy */
-        __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
+        __raw_writew(0x8a0a, IOMEM(0xE6058130));        /* USBCR4 */
 
         /* enable FSI2 port A (ak4643) */
         gpio_request(GPIO_FN_FSIAIBT,   NULL);
@@ -1453,7 +1455,7 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_HDMI_CEC, NULL);
 
         /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
-#define SRCR4 0xe61580bc
+#define SRCR4 IOMEM(0xe61580bc)
         srcr4 = __raw_readl(SRCR4);
         __raw_writel(srcr4 | (1 << 13), SRCR4);
         udelay(50);
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 453a6e50db8b..206c3227f83d 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -54,6 +54,8 @@
 #include <sound/sh_fsi.h>
 #include <sound/simple_card.h>
 
+#include "sh-gpio.h"
+
 /*
  * CON1         Camera Module
  * CON2         Extension Bus
@@ -135,7 +137,7 @@
  *      usbhsf_power_ctrl()
  */
 #define IRQ7            evt2irq(0x02e0)
-#define USBCR1          0xe605810a
+#define USBCR1          IOMEM(0xe605810a)
 #define USBH            0xC6700000
 #define USBH_USBCTR     0x10834
 
@@ -950,8 +952,8 @@ clock_error:
 /*
  * board init
  */
-#define GPIO_PORT7CR    0xe6050007
-#define GPIO_PORT8CR    0xe6050008
+#define GPIO_PORT7CR    IOMEM(0xe6050007)
+#define GPIO_PORT8CR    IOMEM(0xe6050008)
 static void __init eva_init(void)
 {
         struct platform_device *usb = NULL;
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 4129008eae29..cb8c994e1430 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -108,12 +108,12 @@ static struct regulator_consumer_supply dummy_supplies[] = {
 #define FPGA_ETH_IRQ            (FPGA_IRQ0 + 15)
 static u16 bonito_fpga_read(u32 offset)
 {
-        return __raw_readw(0xf0003000 + offset);
+        return __raw_readw(IOMEM(0xf0003000) + offset);
 }
 
 static void bonito_fpga_write(u32 offset, u16 val)
 {
-        __raw_writew(val, 0xf0003000 + offset);
+        __raw_writew(val, IOMEM(0xf0003000) + offset);
 }
 
 static void bonito_fpga_irq_disable(struct irq_data *data)
@@ -361,8 +361,8 @@ static void __init bonito_map_io(void)
 #define BIT_ON(sw, bit)         (sw & (1 << bit))
 #define BIT_OFF(sw, bit)        (!(sw & (1 << bit)))
 
-#define VCCQ1CR         0xE6058140
-#define VCCQ1LCDCR      0xE6058186
+#define VCCQ1CR         IOMEM(0xE6058140)
+#define VCCQ1LCDCR      IOMEM(0xE6058186)
 
 static void __init bonito_init(void)
 {
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 796fa00ad3c4..b179d4c213bb 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -106,7 +106,7 @@ static void usb_host_port_power(int port, int power)
                 return;
 
         /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-        __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+        __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
 }
 
 static struct r8a66597_platdata usb_host_data = {
@@ -279,10 +279,10 @@ static void __init g3evm_init(void)
         gpio_request(GPIO_FN_IDIN, NULL);
 
         /* setup USB phy */
-        __raw_writew(0x0300, 0xe605810a);       /* USBCR1 */
-        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
-        __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
-        __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+        __raw_writew(0x0300, IOMEM(0xe605810a));        /* USBCR1 */
+        __raw_writew(0x00e0, IOMEM(0xe60581c0));        /* CPFCH */
+        __raw_writew(0x6010, IOMEM(0xe60581c6));        /* CGPOSR */
+        __raw_writew(0x8a0a, IOMEM(0xe605810c));        /* USBCR2 */
 
         /* KEYSC @ CN7 */
         gpio_request(GPIO_FN_PORT42_KEYOUT0, NULL);
@@ -320,7 +320,7 @@ static void __init g3evm_init(void)
         gpio_request(GPIO_FN_WE0_XWR0_FWE, NULL);
         gpio_request(GPIO_FN_FRB, NULL);
         /* FOE, FCDE, FSC on dedicated pins */
-        __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
+        __raw_writel(__raw_readl(IOMEM(0xe6158048)) & ~(1 << 15), IOMEM(0xe6158048));
 
         /* IrDA */
         gpio_request(GPIO_FN_IRDA_OUT, NULL);
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index fa5dfc5c8ed6..35c126caa4d8 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -42,6 +42,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "sh-gpio.h"
+
 /*
  * SDHI
  *
@@ -126,7 +128,7 @@ static void usb_host_port_power(int port, int power)
                 return;
 
         /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-        __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+        __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
 }
 
 static struct r8a66597_platdata usb_host_data = {
@@ -270,17 +272,17 @@ static struct platform_device *g4evm_devices[] __initdata = {
         &sdhi1_device,
 };
 
-#define GPIO_SDHID0_D0  0xe60520fc
-#define GPIO_SDHID0_D1  0xe60520fd
-#define GPIO_SDHID0_D2  0xe60520fe
-#define GPIO_SDHID0_D3  0xe60520ff
-#define GPIO_SDHICMD0   0xe6052100
+#define GPIO_SDHID0_D0  IOMEM(0xe60520fc)
+#define GPIO_SDHID0_D1  IOMEM(0xe60520fd)
+#define GPIO_SDHID0_D2  IOMEM(0xe60520fe)
+#define GPIO_SDHID0_D3  IOMEM(0xe60520ff)
+#define GPIO_SDHICMD0   IOMEM(0xe6052100)
 
-#define GPIO_SDHID1_D0  0xe6052103
-#define GPIO_SDHID1_D1  0xe6052104
-#define GPIO_SDHID1_D2  0xe6052105
-#define GPIO_SDHID1_D3  0xe6052106
-#define GPIO_SDHICMD1   0xe6052107
+#define GPIO_SDHID1_D0  IOMEM(0xe6052103)
+#define GPIO_SDHID1_D1  IOMEM(0xe6052104)
+#define GPIO_SDHID1_D2  IOMEM(0xe6052105)
+#define GPIO_SDHID1_D3  IOMEM(0xe6052106)
+#define GPIO_SDHICMD1   IOMEM(0xe6052107)
 
 static void __init g4evm_init(void)
 {
@@ -318,10 +320,10 @@ static void __init g4evm_init(void)
         gpio_request(GPIO_FN_IDIN, NULL);
 
         /* setup USB phy */
-        __raw_writew(0x0200, 0xe605810a);       /* USBCR1 */
-        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
-        __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
-        __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+        __raw_writew(0x0200, IOMEM(0xe605810a));       /* USBCR1 */
+        __raw_writew(0x00e0, IOMEM(0xe60581c0));       /* CPFCH */
+        __raw_writew(0x6010, IOMEM(0xe60581c6));       /* CGPOSR */
+        __raw_writew(0x8a0a, IOMEM(0xe605810c));       /* USBCR2 */
 
         /* KEYSC @ CN31 */
         gpio_request(GPIO_FN_PORT60_KEYOUT5, NULL);
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 21dbe54304d5..bf88f9a8b7ac 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -545,6 +545,7 @@ static void __init kota2_init(void)
 }
 
 MACHINE_START(KOTA2, "kota2")
+        .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
         .init_early     = sh73a0_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index 2c986eaae7b4..b52bc0d1273f 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -84,6 +84,7 @@ static const char *kzm9d_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(KZM9D_DT, "kzm9d")
+        .smp            = smp_ops(emev2_smp_ops),
         .map_io         = emev2_map_io,
         .init_early     = emev2_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 53b7ea92c32c..6525835abc0a 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -133,8 +133,8 @@ static struct platform_device usb_host_device = {
 
 /* USB Func CN17 */
 struct usbhs_private {
-        unsigned int phy;
-        unsigned int cr2;
+        void __iomem *phy;
+        void __iomem *cr2;
         struct renesas_usbhs_platform_info info;
 };
 
@@ -232,8 +232,8 @@ static u32 usbhs_pipe_cfg[] = {
 };
 
 static struct usbhs_private usbhs_private = {
-        .phy    = 0xe60781e0,           /* USBPHYINT */
-        .cr2    = 0xe605810c,           /* USBCR2 */
+        .phy    = IOMEM(0xe60781e0),            /* USBPHYINT */
+        .cr2    = IOMEM(0xe605810c),            /* USBCR2 */
         .info = {
                 .platform_callback = {
                         .hardware_init  = usbhs_hardware_init,
@@ -763,12 +763,20 @@ static void __init kzm_init(void)
         platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));
 }
 
+static void kzm9g_restart(char mode, const char *cmd)
+{
+#define RESCNT2 0xe6188020
+        /* Do soft power on reset */
+        writel((1 << 31), RESCNT2);
+}
+
 static const char *kzm9g_boards_compat_dt[] __initdata = {
         "renesas,kzm9g",
         NULL,
 };
 
 DT_MACHINE_START(KZM9G_DT, "kzm9g")
+        .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
         .init_early     = sh73a0_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
@@ -777,5 +785,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
         .init_machine   = kzm_init,
         .init_late      = shmobile_init_late,
         .timer          = &shmobile_timer,
+        .restart        = kzm9g_restart,
         .dt_compat      = kzm9g_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index c129542f6aed..62783b5d8813 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -64,6 +64,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include "sh-gpio.h"
+
 /*
  * Address      Interface               BusWidth        note
  * ------------------------------------------------------------------
@@ -583,8 +585,8 @@ out:
 #define USBHS0_POLL_INTERVAL (HZ * 5)
 
 struct usbhs_private {
-        unsigned int usbphyaddr;
-        unsigned int usbcrcaddr;
+        void __iomem *usbphyaddr;
+        void __iomem *usbcrcaddr;
         struct renesas_usbhs_platform_info info;
         struct delayed_work work;
         struct platform_device *pdev;
@@ -642,7 +644,7 @@ static void usbhs0_hardware_exit(struct platform_device *pdev)
 }
 
 static struct usbhs_private usbhs0_private = {
-        .usbcrcaddr     = 0xe605810c,           /* USBCR2 */
+        .usbcrcaddr     = IOMEM(0xe605810c),            /* USBCR2 */
         .info = {
                 .platform_callback = {
                         .hardware_init  = usbhs0_hardware_init,
@@ -776,8 +778,8 @@ static u32 usbhs1_pipe_cfg[] = {
 };
 
 static struct usbhs_private usbhs1_private = {
-        .usbphyaddr     = 0xe60581e2,           /* USBPHY1INTAP */
-        .usbcrcaddr     = 0xe6058130,           /* USBCR4 */
+        .usbphyaddr     = IOMEM(0xe60581e2),    /* USBPHY1INTAP */
+        .usbcrcaddr     = IOMEM(0xe6058130),    /* USBCR4 */
         .info = {
                 .platform_callback = {
                         .hardware_init  = usbhs1_hardware_init,
@@ -1402,12 +1404,12 @@ static struct i2c_board_info i2c1_devices[] = {
         },
 };
 
-#define GPIO_PORT9CR    0xE6051009
-#define GPIO_PORT10CR   0xE605100A
-#define GPIO_PORT167CR  0xE60520A7
-#define GPIO_PORT168CR  0xE60520A8
-#define SRCR4           0xe61580bc
-#define USCCR1          0xE6058144
+#define GPIO_PORT9CR    IOMEM(0xE6051009)
+#define GPIO_PORT10CR   IOMEM(0xE605100A)
+#define GPIO_PORT167CR  IOMEM(0xE60520A7)
+#define GPIO_PORT168CR  IOMEM(0xE60520A8)
+#define SRCR4           IOMEM(0xe61580bc)
+#define USCCR1          IOMEM(0xE6058144)
 static void __init mackerel_init(void)
 {
         u32 srcr4;
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index fcf5a47f4772..01ce3f15c6a3 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -102,6 +102,7 @@ static void __init marzen_init(void)
 }
 
 MACHINE_START(MARZEN, "marzen")
+        .smp            = smp_ops(r8a7779_smp_ops),
         .map_io         = r8a7779_map_io,
         .init_early     = r8a7779_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index ad5fccc7b5e7..6729e0032180 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -41,29 +41,29 @@
  */
 
 /* CPG registers */
-#define FRQCRA          0xe6150000
-#define FRQCRB          0xe6150004
-#define VCLKCR1         0xE6150008
-#define VCLKCR2         0xE615000c
-#define FRQCRC          0xe61500e0
-#define FSIACKCR        0xe6150018
-#define PLLC01CR        0xe6150028
-
-#define SUBCKCR         0xe6150080
-#define USBCKCR         0xe615008c
-
-#define MSTPSR0         0xe6150030
-#define MSTPSR1         0xe6150038
-#define MSTPSR2         0xe6150040
-#define MSTPSR3         0xe6150048
-#define MSTPSR4         0xe615004c
-#define FSIBCKCR        0xe6150090
-#define HDMICKCR        0xe6150094
-#define SMSTPCR0        0xe6150130
-#define SMSTPCR1        0xe6150134
-#define SMSTPCR2        0xe6150138
-#define SMSTPCR3        0xe615013c
-#define SMSTPCR4        0xe6150140
+#define FRQCRA          IOMEM(0xe6150000)
+#define FRQCRB          IOMEM(0xe6150004)
+#define VCLKCR1         IOMEM(0xE6150008)
+#define VCLKCR2         IOMEM(0xE615000c)
+#define FRQCRC          IOMEM(0xe61500e0)
+#define FSIACKCR        IOMEM(0xe6150018)
+#define PLLC01CR        IOMEM(0xe6150028)
+
+#define SUBCKCR         IOMEM(0xe6150080)
+#define USBCKCR         IOMEM(0xe615008c)
+
+#define MSTPSR0         IOMEM(0xe6150030)
+#define MSTPSR1         IOMEM(0xe6150038)
+#define MSTPSR2         IOMEM(0xe6150040)
+#define MSTPSR3         IOMEM(0xe6150048)
+#define MSTPSR4         IOMEM(0xe615004c)
+#define FSIBCKCR        IOMEM(0xe6150090)
+#define HDMICKCR        IOMEM(0xe6150094)
+#define SMSTPCR0        IOMEM(0xe6150130)
+#define SMSTPCR1        IOMEM(0xe6150134)
+#define SMSTPCR2        IOMEM(0xe6150138)
+#define SMSTPCR3        IOMEM(0xe615013c)
+#define SMSTPCR4        IOMEM(0xe6150140)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk extalr_clk = {
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 339c62c824d5..3cafb6ab5e9a 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -86,11 +86,16 @@ static struct clk div4_clks[DIV4_NR] = {
                                       0x0300, CLK_ENABLE_ON_INIT),
 };
 
-enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+enum { MSTP323, MSTP322, MSTP321, MSTP320,
+        MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015, MSTP014,
         MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */
+        [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
+        [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
+        [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
         [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
         [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
         [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -149,6 +154,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
 };
 
 void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 162b791b8984..ef0a95e592c4 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -24,28 +24,28 @@
 #include <mach/common.h>
 
 /* SH7367 registers */
-#define RTFRQCR    0xe6150000
-#define SYFRQCR    0xe6150004
-#define CMFRQCR    0xe61500E0
-#define VCLKCR1    0xe6150008
-#define VCLKCR2    0xe615000C
-#define VCLKCR3    0xe615001C
-#define SCLKACR    0xe6150010
-#define SCLKBCR    0xe6150014
-#define SUBUSBCKCR 0xe6158080
-#define SPUCKCR    0xe6150084
-#define MSUCKCR    0xe6150088
-#define MVI3CKCR   0xe6150090
-#define VOUCKCR    0xe6150094
-#define MFCK1CR    0xe6150098
-#define MFCK2CR    0xe615009C
-#define PLLC1CR    0xe6150028
-#define PLLC2CR    0xe615002C
-#define RTMSTPCR0  0xe6158030
-#define RTMSTPCR2  0xe6158038
-#define SYMSTPCR0  0xe6158040
-#define SYMSTPCR2  0xe6158048
-#define CMMSTPCR0  0xe615804c
+#define RTFRQCR    IOMEM(0xe6150000)
+#define SYFRQCR    IOMEM(0xe6150004)
+#define CMFRQCR    IOMEM(0xe61500E0)
+#define VCLKCR1    IOMEM(0xe6150008)
+#define VCLKCR2    IOMEM(0xe615000C)
+#define VCLKCR3    IOMEM(0xe615001C)
+#define SCLKACR    IOMEM(0xe6150010)
+#define SCLKBCR    IOMEM(0xe6150014)
+#define SUBUSBCKCR IOMEM(0xe6158080)
+#define SPUCKCR    IOMEM(0xe6150084)
+#define MSUCKCR    IOMEM(0xe6150088)
+#define MVI3CKCR   IOMEM(0xe6150090)
+#define VOUCKCR    IOMEM(0xe6150094)
+#define MFCK1CR    IOMEM(0xe6150098)
+#define MFCK2CR    IOMEM(0xe615009C)
+#define PLLC1CR    IOMEM(0xe6150028)
+#define PLLC2CR    IOMEM(0xe615002C)
+#define RTMSTPCR0  IOMEM(0xe6158030)
+#define RTMSTPCR2  IOMEM(0xe6158038)
+#define SYMSTPCR0  IOMEM(0xe6158040)
+#define SYMSTPCR2  IOMEM(0xe6158048)
+#define CMMSTPCR0  IOMEM(0xe615804c)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 5a2894b1c965..430a90ffa120 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -24,36 +24,36 @@
 #include <mach/common.h>
 
 /* SH7372 registers */
-#define FRQCRA          0xe6150000
-#define FRQCRB          0xe6150004
-#define FRQCRC          0xe61500e0
-#define FRQCRD          0xe61500e4
-#define VCLKCR1         0xe6150008
-#define VCLKCR2         0xe615000c
-#define VCLKCR3         0xe615001c
-#define FMSICKCR        0xe6150010
-#define FMSOCKCR        0xe6150014
-#define FSIACKCR        0xe6150018
-#define FSIBCKCR        0xe6150090
-#define SUBCKCR         0xe6150080
-#define SPUCKCR         0xe6150084
-#define VOUCKCR         0xe6150088
-#define HDMICKCR        0xe6150094
-#define DSITCKCR        0xe6150060
-#define DSI0PCKCR       0xe6150064
-#define DSI1PCKCR       0xe6150098
-#define PLLC01CR        0xe6150028
-#define PLLC2CR         0xe615002c
-#define RMSTPCR0        0xe6150110
-#define RMSTPCR1        0xe6150114
-#define RMSTPCR2        0xe6150118
-#define RMSTPCR3        0xe615011c
-#define RMSTPCR4        0xe6150120
-#define SMSTPCR0        0xe6150130
-#define SMSTPCR1        0xe6150134
-#define SMSTPCR2        0xe6150138
-#define SMSTPCR3        0xe615013c
-#define SMSTPCR4        0xe6150140
+#define FRQCRA          IOMEM(0xe6150000)
+#define FRQCRB          IOMEM(0xe6150004)
+#define FRQCRC          IOMEM(0xe61500e0)
+#define FRQCRD          IOMEM(0xe61500e4)
+#define VCLKCR1         IOMEM(0xe6150008)
+#define VCLKCR2         IOMEM(0xe615000c)
+#define VCLKCR3         IOMEM(0xe615001c)
+#define FMSICKCR        IOMEM(0xe6150010)
+#define FMSOCKCR        IOMEM(0xe6150014)
+#define FSIACKCR        IOMEM(0xe6150018)
+#define FSIBCKCR        IOMEM(0xe6150090)
+#define SUBCKCR         IOMEM(0xe6150080)
+#define SPUCKCR         IOMEM(0xe6150084)
+#define VOUCKCR         IOMEM(0xe6150088)
+#define HDMICKCR        IOMEM(0xe6150094)
+#define DSITCKCR        IOMEM(0xe6150060)
+#define DSI0PCKCR       IOMEM(0xe6150064)
+#define DSI1PCKCR       IOMEM(0xe6150098)
+#define PLLC01CR        IOMEM(0xe6150028)
+#define PLLC2CR         IOMEM(0xe615002c)
+#define RMSTPCR0        IOMEM(0xe6150110)
+#define RMSTPCR1        IOMEM(0xe6150114)
+#define RMSTPCR2        IOMEM(0xe6150118)
+#define RMSTPCR3        IOMEM(0xe615011c)
+#define RMSTPCR4        IOMEM(0xe6150120)
+#define SMSTPCR0        IOMEM(0xe6150130)
+#define SMSTPCR1        IOMEM(0xe6150134)
+#define SMSTPCR2        IOMEM(0xe6150138)
+#define SMSTPCR3        IOMEM(0xe615013c)
+#define SMSTPCR4        IOMEM(0xe6150140)
 
 #define FSIDIVA         0xFE1F8000
 #define FSIDIVB         0xFE1F8008
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index 85f2a3ec2c44..b8480d19e1c8 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -24,31 +24,31 @@
 #include <mach/common.h>
 
 /* SH7377 registers */
-#define RTFRQCR    0xe6150000
-#define SYFRQCR    0xe6150004
-#define CMFRQCR    0xe61500E0
-#define VCLKCR1    0xe6150008
-#define VCLKCR2    0xe615000C
-#define VCLKCR3    0xe615001C
-#define FMSICKCR   0xe6150010
-#define FMSOCKCR   0xe6150014
-#define FSICKCR    0xe6150018
-#define PLLC1CR    0xe6150028
-#define PLLC2CR    0xe615002C
-#define SUBUSBCKCR 0xe6150080
-#define SPUCKCR    0xe6150084
-#define MSUCKCR    0xe6150088
-#define MVI3CKCR   0xe6150090
-#define HDMICKCR   0xe6150094
-#define MFCK1CR    0xe6150098
-#define MFCK2CR    0xe615009C
-#define DSITCKCR   0xe6150060
-#define DSIPCKCR   0xe6150064
-#define SMSTPCR0   0xe6150130
-#define SMSTPCR1   0xe6150134
-#define SMSTPCR2   0xe6150138
-#define SMSTPCR3   0xe615013C
-#define SMSTPCR4   0xe6150140
+#define RTFRQCR    IOMEM(0xe6150000)
+#define SYFRQCR    IOMEM(0xe6150004)
+#define CMFRQCR    IOMEM(0xe61500E0)
+#define VCLKCR1    IOMEM(0xe6150008)
+#define VCLKCR2    IOMEM(0xe615000C)
+#define VCLKCR3    IOMEM(0xe615001C)
+#define FMSICKCR   IOMEM(0xe6150010)
+#define FMSOCKCR   IOMEM(0xe6150014)
+#define FSICKCR    IOMEM(0xe6150018)
+#define PLLC1CR    IOMEM(0xe6150028)
+#define PLLC2CR    IOMEM(0xe615002C)
+#define SUBUSBCKCR IOMEM(0xe6150080)
+#define SPUCKCR    IOMEM(0xe6150084)
+#define MSUCKCR    IOMEM(0xe6150088)
+#define MVI3CKCR   IOMEM(0xe6150090)
+#define HDMICKCR   IOMEM(0xe6150094)
+#define MFCK1CR    IOMEM(0xe6150098)
+#define MFCK2CR    IOMEM(0xe615009C)
+#define DSITCKCR   IOMEM(0xe6150060)
+#define DSIPCKCR   IOMEM(0xe6150064)
+#define SMSTPCR0   IOMEM(0xe6150130)
+#define SMSTPCR1   IOMEM(0xe6150134)
+#define SMSTPCR2   IOMEM(0xe6150138)
+#define SMSTPCR3   IOMEM(0xe615013C)
+#define SMSTPCR4   IOMEM(0xe6150140)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 7f8da18a8580..516ff7f3e434 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -23,43 +23,43 @@
 #include <linux/clkdev.h>
 #include <mach/common.h>
 
-#define FRQCRA          0xe6150000
-#define FRQCRB          0xe6150004
-#define FRQCRD          0xe61500e4
-#define VCLKCR1         0xe6150008
-#define VCLKCR2         0xe615000C
-#define VCLKCR3         0xe615001C
-#define ZBCKCR          0xe6150010
-#define FLCKCR          0xe6150014
-#define SD0CKCR         0xe6150074
-#define SD1CKCR         0xe6150078
-#define SD2CKCR         0xe615007C
-#define FSIACKCR        0xe6150018
-#define FSIBCKCR        0xe6150090
-#define SUBCKCR         0xe6150080
-#define SPUACKCR        0xe6150084
-#define SPUVCKCR        0xe6150094
-#define MSUCKCR         0xe6150088
-#define HSICKCR         0xe615008C
-#define MFCK1CR         0xe6150098
-#define MFCK2CR         0xe615009C
-#define DSITCKCR        0xe6150060
-#define DSI0PCKCR       0xe6150064
-#define DSI1PCKCR       0xe6150068
+#define FRQCRA          IOMEM(0xe6150000)
+#define FRQCRB          IOMEM(0xe6150004)
+#define FRQCRD          IOMEM(0xe61500e4)
+#define VCLKCR1         IOMEM(0xe6150008)
+#define VCLKCR2         IOMEM(0xe615000C)
+#define VCLKCR3         IOMEM(0xe615001C)
+#define ZBCKCR          IOMEM(0xe6150010)
+#define FLCKCR          IOMEM(0xe6150014)
+#define SD0CKCR         IOMEM(0xe6150074)
+#define SD1CKCR         IOMEM(0xe6150078)
+#define SD2CKCR         IOMEM(0xe615007C)
+#define FSIACKCR        IOMEM(0xe6150018)
+#define FSIBCKCR        IOMEM(0xe6150090)
+#define SUBCKCR         IOMEM(0xe6150080)
+#define SPUACKCR        IOMEM(0xe6150084)
+#define SPUVCKCR        IOMEM(0xe6150094)
+#define MSUCKCR         IOMEM(0xe6150088)
+#define HSICKCR         IOMEM(0xe615008C)
+#define MFCK1CR         IOMEM(0xe6150098)
+#define MFCK2CR         IOMEM(0xe615009C)
+#define DSITCKCR        IOMEM(0xe6150060)
+#define DSI0PCKCR       IOMEM(0xe6150064)
+#define DSI1PCKCR       IOMEM(0xe6150068)
 #define DSI0PHYCR       0xe615006C
 #define DSI1PHYCR       0xe6150070
-#define PLLECR          0xe61500d0
-#define PLL0CR          0xe61500d8
-#define PLL1CR          0xe6150028
-#define PLL2CR          0xe615002c
-#define PLL3CR          0xe61500dc
-#define SMSTPCR0        0xe6150130
-#define SMSTPCR1        0xe6150134
-#define SMSTPCR2        0xe6150138
-#define SMSTPCR3        0xe615013c
-#define SMSTPCR4        0xe6150140
-#define SMSTPCR5        0xe6150144
-#define CKSCR           0xe61500c0
+#define PLLECR          IOMEM(0xe61500d0)
+#define PLL0CR          IOMEM(0xe61500d8)
+#define PLL1CR          IOMEM(0xe6150028)
+#define PLL2CR          IOMEM(0xe615002c)
+#define PLL3CR          IOMEM(0xe61500dc)
+#define SMSTPCR0        IOMEM(0xe6150130)
+#define SMSTPCR1        IOMEM(0xe6150134)
+#define SMSTPCR2        IOMEM(0xe6150138)
+#define SMSTPCR3        IOMEM(0xe615013c)
+#define SMSTPCR4        IOMEM(0xe6150140)
+#define SMSTPCR5        IOMEM(0xe6150144)
+#define CKSCR           IOMEM(0xe61500c0)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
index 828d22f3af57..b09a0bdbf813 100644
--- a/arch/arm/mach-shmobile/hotplug.c
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -14,30 +14,16 @@
 #include <linux/smp.h>
 #include <linux/cpumask.h>
 #include <linux/delay.h>
+#include <linux/of.h>
 #include <mach/common.h>
+#include <mach/r8a7779.h>
+#include <mach/emev2.h>
 #include <asm/cacheflush.h>
+#include <asm/mach-types.h>
 
 static cpumask_t dead_cpus;
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        int k;
-
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (cpumask_test_cpu(cpu, &dead_cpus))
-                        return shmobile_platform_cpu_kill(cpu);
-
-                mdelay(1);
-        }
-
-        return 0;
-}
-
-void platform_cpu_die(unsigned int cpu)
+void shmobile_cpu_die(unsigned int cpu)
 {
         /* hardware shutdown code running on the CPU that is being offlined */
         flush_cache_all();
@@ -60,7 +46,7 @@ void platform_cpu_die(unsigned int cpu)
         }
 }
 
-int platform_cpu_disable(unsigned int cpu)
+int shmobile_cpu_disable(unsigned int cpu)
 {
         cpumask_clear_cpu(cpu, &dead_cpus);
         /*
@@ -69,3 +55,8 @@ int platform_cpu_disable(unsigned int cpu)
          */
         return cpu == 0 ? -EPERM : 0;
 }
+
+int shmobile_cpu_is_dead(unsigned int cpu)
+{
+        return cpumask_test_cpu(cpu, &dead_cpus);
+}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 45e61dada030..f80f9c549393 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -4,11 +4,10 @@
 extern void shmobile_earlytimer_init(void);
 extern struct sys_timer shmobile_timer;
 extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
-                                 unsigned int mult, unsigned int div);
+                         unsigned int mult, unsigned int div);
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
-extern int shmobile_platform_cpu_kill(unsigned int cpu);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -58,11 +57,6 @@ extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;
 extern struct clk sh73a0_extalr_clk;
 
-extern unsigned int sh73a0_get_core_count(void);
-extern void sh73a0_secondary_init(unsigned int cpu);
-extern int sh73a0_boot_secondary(unsigned int cpu);
-extern void sh73a0_smp_prepare_cpus(void);
-
 extern void r8a7740_init_irq(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
@@ -79,11 +73,6 @@ extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
 extern void r8a7740_meram_workaround(void);
 
-extern unsigned int r8a7779_get_core_count(void);
-extern int r8a7779_platform_cpu_kill(unsigned int cpu);
-extern void r8a7779_secondary_init(unsigned int cpu);
-extern int r8a7779_boot_secondary(unsigned int cpu);
-extern void r8a7779_smp_prepare_cpus(void);
 extern void r8a7779_register_twd(void);
 
 extern void shmobile_init_late(void);
@@ -100,4 +89,15 @@ int shmobile_cpuidle_init(void);
 static inline int shmobile_cpuidle_init(void) { return 0; }
 #endif
 
+extern void shmobile_cpu_die(unsigned int cpu);
+extern int shmobile_cpu_disable(unsigned int cpu);
+
+#ifdef CONFIG_HOTPLUG_CPU
+extern int shmobile_cpu_is_dead(unsigned int cpu);
+#else
+static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
+#endif
+
+extern void shmobile_smp_init_cpus(unsigned int ncores);
+
 #endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index e6b0c1bf4b7e..ac3751705cab 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -7,13 +7,10 @@ extern void emev2_add_early_devices(void);
 extern void emev2_add_standard_devices(void);
 extern void emev2_clock_init(void);
 extern void emev2_set_boot_vector(unsigned long value);
-extern unsigned int emev2_get_core_count(void);
-extern int emev2_platform_cpu_kill(unsigned int cpu);
-extern void emev2_secondary_init(unsigned int cpu);
-extern int emev2_boot_secondary(unsigned int cpu);
-extern void emev2_smp_prepare_cpus(void);
 
 #define EMEV2_GPIO_BASE 200
 #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
 
+extern struct smp_operations emev2_smp_ops;
+
 #endif /* __ASM_EMEV2_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index b07ad318eb2e..f504c5e81b47 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -360,4 +360,6 @@ extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
 #define r8a7779_add_device_to_domain(pd, pdev) do { } while (0)
 #endif /* CONFIG_PM */
 
+extern struct smp_operations r8a7779_smp_ops;
+
 #endif /* __ASM_R8A7779_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index fe950f25d793..606d31d02a4e 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -557,4 +557,6 @@ enum {
 #define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
 #define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
 
+extern struct smp_operations sh73a0_smp_ops;
+
 #endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index f04fad4ec4fb..ef66f1a8aa2e 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -29,14 +29,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#define INT2SMSKCR0 0xfe7822a0
-#define INT2SMSKCR1 0xfe7822a4
-#define INT2SMSKCR2 0xfe7822a8
-#define INT2SMSKCR3 0xfe7822ac
-#define INT2SMSKCR4 0xfe7822b0
+#define INT2SMSKCR0 IOMEM(0xfe7822a0)
+#define INT2SMSKCR1 IOMEM(0xfe7822a4)
+#define INT2SMSKCR2 IOMEM(0xfe7822a8)
+#define INT2SMSKCR3 IOMEM(0xfe7822ac)
+#define INT2SMSKCR4 IOMEM(0xfe7822b0)
 
-#define INT2NTSR0 0xfe700060
-#define INT2NTSR1 0xfe700064
+#define INT2NTSR0 IOMEM(0xfe700060)
+#define INT2NTSR1 IOMEM(0xfe700064)
 
 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 {
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 2587a22842f2..a91caad7db7c 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -624,6 +624,9 @@ void sh7372_intcs_resume(void)
                 __raw_writeb(ffd5[k], intcs_ffd5 + k);
 }
 
+#define E694_BASE IOMEM(0xe6940000)
+#define E695_BASE IOMEM(0xe6950000)
+
 static unsigned short e694[0x200];
 static unsigned short e695[0x200];
 
@@ -632,22 +635,22 @@ void sh7372_intca_suspend(void)
         int k;
 
         for (k = 0x00; k <= 0x38; k += 4)
-                e694[k] = __raw_readw(0xe6940000 + k);
+                e694[k] = __raw_readw(E694_BASE + k);
 
         for (k = 0x80; k <= 0xb4; k += 4)
-                e694[k] = __raw_readb(0xe6940000 + k);
+                e694[k] = __raw_readb(E694_BASE + k);
 
         for (k = 0x180; k <= 0x1b4; k += 4)
-                e694[k] = __raw_readb(0xe6940000 + k);
+                e694[k] = __raw_readb(E694_BASE + k);
 
         for (k = 0x00; k <= 0x50; k += 4)
-                e695[k] = __raw_readw(0xe6950000 + k);
+                e695[k] = __raw_readw(E695_BASE + k);
 
         for (k = 0x80; k <= 0xa8; k += 4)
-                e695[k] = __raw_readb(0xe6950000 + k);
+                e695[k] = __raw_readb(E695_BASE + k);
 
         for (k = 0x180; k <= 0x1a8; k += 4)
-                e695[k] = __raw_readb(0xe6950000 + k);
+                e695[k] = __raw_readb(E695_BASE + k);
 }
 
 void sh7372_intca_resume(void)
@@ -655,20 +658,20 @@ void sh7372_intca_resume(void)
         int k;
 
         for (k = 0x00; k <= 0x38; k += 4)
-                __raw_writew(e694[k], 0xe6940000 + k);
+                __raw_writew(e694[k], E694_BASE + k);
 
         for (k = 0x80; k <= 0xb4; k += 4)
-                __raw_writeb(e694[k], 0xe6940000 + k);
+                __raw_writeb(e694[k], E694_BASE + k);
 
         for (k = 0x180; k <= 0x1b4; k += 4)
-                __raw_writeb(e694[k], 0xe6940000 + k);
+                __raw_writeb(e694[k], E694_BASE + k);
 
         for (k = 0x00; k <= 0x50; k += 4)
-                __raw_writew(e695[k], 0xe6950000 + k);
+                __raw_writew(e695[k], E695_BASE + k);
 
         for (k = 0x80; k <= 0xa8; k += 4)
-                __raw_writeb(e695[k], 0xe6950000 + k);
+                __raw_writeb(e695[k], E695_BASE + k);
 
         for (k = 0x180; k <= 0x1a8; k += 4)
-                __raw_writeb(e695[k], 0xe6950000 + k);
+                __raw_writeb(e695[k], E695_BASE + k);
 }
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 588555a67d9c..f0c5e5190601 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -366,10 +366,12 @@ static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
 
 static struct irqaction sh73a0_irq_pin_cascade[32];
 
-#define PINTER0 0xe69000a0
-#define PINTER1 0xe69000a4
-#define PINTRR0 0xe69000d0
-#define PINTRR1 0xe69000d4
+#define PINTER0_PHYS 0xe69000a0
+#define PINTER1_PHYS 0xe69000a4
+#define PINTER0_VIRT IOMEM(0xe69000a0)
+#define PINTER1_VIRT IOMEM(0xe69000a4)
+#define PINTRR0 IOMEM(0xe69000d0)
+#define PINTRR1 IOMEM(0xe69000d4)
 
 #define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
 #define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
@@ -377,14 +379,14 @@ static struct irqaction sh73a0_irq_pin_cascade[32];
 #define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
 #define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
 
-INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0",              \
+INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0",         \
   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
   INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ),               \
   INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ),               \
   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
 
-INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1",              \
+INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1",         \
   INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
   INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE,                         \
   INTC_PINT_V_NONE, INTC_PINT_V_NONE,                                   \
@@ -394,7 +396,7 @@ INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1",		\
 static struct irqaction sh73a0_pint0_cascade;
 static struct irqaction sh73a0_pint1_cascade;
 
-static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
+static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq)
 {
         unsigned long value =  ioread32(rr) & ioread32(er);
         int k;
@@ -409,13 +411,13 @@ static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
 
 static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
 {
-        pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0));
+        pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0));
         return IRQ_HANDLED;
 }
 
 static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
 {
-        pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0));
+        pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0));
         return IRQ_HANDLED;
 }
 
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
index ce9e7fa5cc8a..134d1b9a8821 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7740.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -20,7 +20,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/r8a7740.h>
 #include <mach/irqs.h>
 
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index d14c9b048077..cbc26ba2a0a2 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -19,7 +19,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <linux/ioport.h>
 #include <mach/r8a7779.h>
 
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
index e6e524654e67..c0c137f39052 100644
--- a/arch/arm/mach-shmobile/pfc-sh7367.c
+++ b/arch/arm/mach-shmobile/pfc-sh7367.c
@@ -18,7 +18,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/sh7367.h>
 
 #define CPU_ALL_PORT(fn, pfx, sfx)                              \
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
index 336093f9210a..7a1525fd6ada 100644
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ b/arch/arm/mach-shmobile/pfc-sh7372.c
@@ -22,7 +22,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
 
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c
index 2f10511946ad..f3117f67fa25 100644
--- a/arch/arm/mach-shmobile/pfc-sh7377.c
+++ b/arch/arm/mach-shmobile/pfc-sh7377.c
@@ -19,7 +19,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/sh7377.h>
 
 #define CPU_ALL_PORT(fn, pfx, sfx)                              \
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
index 4a547b803268..b442f9d8c716 100644
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -20,7 +20,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/sh73a0.h>
 #include <mach/irqs.h>
 
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index fde0d23121dc..ed8d2351915e 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -11,100 +11,11 @@
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
 #include <linux/smp.h>
-#include <linux/io.h>
-#include <linux/of.h>
 #include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <mach/common.h>
-#include <mach/emev2.h>
 
-#ifdef CONFIG_ARCH_SH73A0
-#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \
-                        of_machine_is_compatible("renesas,sh73a0"))
-#else
-#define is_sh73a0() (0)
-#endif
-
-#define is_r8a7779() machine_is_marzen()
-
-#ifdef CONFIG_ARCH_EMEV2
-#define is_emev2() of_machine_is_compatible("renesas,emev2")
-#else
-#define is_emev2() (0)
-#endif
-
-static unsigned int __init shmobile_smp_get_core_count(void)
-{
-        if (is_sh73a0())
-                return sh73a0_get_core_count();
-
-        if (is_r8a7779())
-                return r8a7779_get_core_count();
-
-        if (is_emev2())
-                return emev2_get_core_count();
-
-        return 1;
-}
-
-static void __init shmobile_smp_prepare_cpus(void)
-{
-        if (is_sh73a0())
-                sh73a0_smp_prepare_cpus();
-
-        if (is_r8a7779())
-                r8a7779_smp_prepare_cpus();
-
-        if (is_emev2())
-                emev2_smp_prepare_cpus();
-}
-
-int shmobile_platform_cpu_kill(unsigned int cpu)
-{
-        if (is_r8a7779())
-                return r8a7779_platform_cpu_kill(cpu);
-
-        if (is_emev2())
-                return emev2_platform_cpu_kill(cpu);
-
-        return 1;
-}
-
-void __cpuinit platform_secondary_init(unsigned int cpu)
+void __init shmobile_smp_init_cpus(unsigned int ncores)
 {
-        trace_hardirqs_off();
-
-        if (is_sh73a0())
-                sh73a0_secondary_init(cpu);
-
-        if (is_r8a7779())
-                r8a7779_secondary_init(cpu);
-
-        if (is_emev2())
-                emev2_secondary_init(cpu);
-}
-
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        if (is_sh73a0())
-                return sh73a0_boot_secondary(cpu);
-
-        if (is_r8a7779())
-                return r8a7779_boot_secondary(cpu);
-
-        if (is_emev2())
-                return emev2_boot_secondary(cpu);
-
-        return -ENOSYS;
-}
-
-void __init smp_init_cpus(void)
-{
-        unsigned int ncores = shmobile_smp_get_core_count();
         unsigned int i;
 
         if (ncores > nr_cpu_ids) {
@@ -118,8 +29,3 @@ void __init smp_init_cpus(void)
 
         set_smp_cross_call(gic_raise_softirq);
 }
-
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
-{
-        shmobile_smp_prepare_cpus();
-}
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index a8562540f1d6..32e177275e47 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -20,9 +20,9 @@
 #include <mach/pm-rmobile.h>
 
 /* SYSC */
-#define SPDCR           0xe6180008
-#define SWUCR           0xe6180014
-#define PSTR            0xe6180080
+#define SPDCR           IOMEM(0xe6180008)
+#define SWUCR           IOMEM(0xe6180014)
+#define PSTR            IOMEM(0xe6180080)
 
 #define PSTR_RETRIES    100
 #define PSTR_DELAY_US   10
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 792037069226..162121842a2b 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -29,45 +29,46 @@
 #include <mach/pm-rmobile.h>
 
 /* DBG */
-#define DBGREG1 0xe6100020
-#define DBGREG9 0xe6100040
+#define DBGREG1 IOMEM(0xe6100020)
+#define DBGREG9 IOMEM(0xe6100040)
 
 /* CPGA */
-#define SYSTBCR 0xe6150024
-#define MSTPSR0 0xe6150030
-#define MSTPSR1 0xe6150038
-#define MSTPSR2 0xe6150040
-#define MSTPSR3 0xe6150048
-#define MSTPSR4 0xe615004c
-#define PLLC01STPCR 0xe61500c8
+#define SYSTBCR IOMEM(0xe6150024)
+#define MSTPSR0 IOMEM(0xe6150030)
+#define MSTPSR1 IOMEM(0xe6150038)
+#define MSTPSR2 IOMEM(0xe6150040)
+#define MSTPSR3 IOMEM(0xe6150048)
+#define MSTPSR4 IOMEM(0xe615004c)
+#define PLLC01STPCR IOMEM(0xe61500c8)
 
 /* SYSC */
-#define SBAR 0xe6180020
-#define WUPRMSK 0xe6180028
-#define WUPSMSK 0xe618002c
-#define WUPSMSK2 0xe6180048
-#define WUPSFAC 0xe6180098
-#define IRQCR 0xe618022c
-#define IRQCR2 0xe6180238
-#define IRQCR3 0xe6180244
-#define IRQCR4 0xe6180248
-#define PDNSEL 0xe6180254
+#define SBAR IOMEM(0xe6180020)
+#define WUPRMSK IOMEM(0xe6180028)
+#define WUPSMSK IOMEM(0xe618002c)
+#define WUPSMSK2 IOMEM(0xe6180048)
+#define WUPSFAC IOMEM(0xe6180098)
+#define IRQCR IOMEM(0xe618022c)
+#define IRQCR2 IOMEM(0xe6180238)
+#define IRQCR3 IOMEM(0xe6180244)
+#define IRQCR4 IOMEM(0xe6180248)
+#define PDNSEL IOMEM(0xe6180254)
 
 /* INTC */
-#define ICR1A 0xe6900000
-#define ICR2A 0xe6900004
-#define ICR3A 0xe6900008
-#define ICR4A 0xe690000c
-#define INTMSK00A 0xe6900040
-#define INTMSK10A 0xe6900044
-#define INTMSK20A 0xe6900048
-#define INTMSK30A 0xe690004c
+#define ICR1A IOMEM(0xe6900000)
+#define ICR2A IOMEM(0xe6900004)
+#define ICR3A IOMEM(0xe6900008)
+#define ICR4A IOMEM(0xe690000c)
+#define INTMSK00A IOMEM(0xe6900040)
+#define INTMSK10A IOMEM(0xe6900044)
+#define INTMSK20A IOMEM(0xe6900048)
+#define INTMSK30A IOMEM(0xe690004c)
 
 /* MFIS */
+/* FIXME: pointing where? */
 #define SMFRAM 0xe6a70000
 
 /* AP-System Core */
-#define APARMBAREA 0xe6f10020
+#define APARMBAREA IOMEM(0xe6f10020)
 
 #ifdef CONFIG_PM
 
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index dae9aa68bb09..a47beeb18283 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -356,6 +356,26 @@ static struct platform_device gio4_device = {
         },
 };
 
+static struct resource pmu_resources[] = {
+        [0] = {
+                .start  = 152,
+                .end    = 152,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start  = 153,
+                .end    = 153,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device pmu_device = {
+        .name           = "arm-pmu",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pmu_resources),
+        .resource       = pmu_resources,
+};
+
 static struct platform_device *emev2_early_devices[] __initdata = {
         &uart0_device,
         &uart1_device,
@@ -370,6 +390,7 @@ static struct platform_device *emev2_late_devices[] __initdata = {
         &gio2_device,
         &gio3_device,
         &gio4_device,
+        &pmu_device,
 };
 
 void __init emev2_add_standard_devices(void)
@@ -440,6 +461,7 @@ void __init emev2_init_irq_dt(void)
 }
 
 DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
+        .smp            = smp_ops(emev2_smp_ops),
         .init_early     = emev2_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = emev2_init_irq_dt,
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index 2e3074ab75b3..e647f5410879 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -462,7 +462,7 @@ static void __init sh7367_earlytimer_init(void)
         shmobile_earlytimer_init();
 }
 
-#define SYMSTPCR2 0xe6158048
+#define SYMSTPCR2 IOMEM(0xe6158048)
 #define SYMSTPCR2_CMT1 (1 << 29)
 
 void __init sh7367_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index 855b1506caf8..edcf98bb7012 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -484,7 +484,7 @@ static void __init sh7377_earlytimer_init(void)
         shmobile_earlytimer_init();
 }
 
-#define SMSTPCR3 0xe615013c
+#define SMSTPCR3 IOMEM(0xe615013c)
 #define SMSTPCR3_CMT1 (1 << 29)
 
 void __init sh7377_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index d230af656fc9..db99a4ade80c 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -734,6 +734,26 @@ static struct platform_device mpdma0_device = {
         },
 };
 
+static struct resource pmu_resources[] = {
+        [0] = {
+                .start  = gic_spi(55),
+                .end    = gic_spi(55),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start  = gic_spi(56),
+                .end    = gic_spi(56),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device pmu_device = {
+        .name           = "arm-pmu",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pmu_resources),
+        .resource       = pmu_resources,
+};
+
 static struct platform_device *sh73a0_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -757,9 +777,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &i2c4_device,
         &dma0_device,
         &mpdma0_device,
+        &pmu_device,
 };
 
-#define SRCR2          0xe61580b0
+#define SRCR2          IOMEM(0xe61580b0)
 
 void __init sh73a0_add_standard_devices(void)
 {
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/sh-gpio.h
index 844507d937cb..e834763ac2a5 100644
--- a/arch/arm/mach-shmobile/include/mach/gpio.h
+++ b/arch/arm/mach-shmobile/sh-gpio.h
@@ -12,22 +12,8 @@
 
 #include <linux/kernel.h>
 #include <linux/errno.h>
-#include <linux/sh_pfc.h>
 #include <linux/io.h>
 
-#ifdef CONFIG_GPIOLIB
-
-static inline int irq_to_gpio(unsigned int irq)
-{
-        return -ENOSYS;
-}
-
-#else
-
-#define __ARM_GPIOLIB_COMPLEX
-
-#endif /* CONFIG_GPIOLIB */
-
 /*
  * FIXME !!
  *
@@ -35,12 +21,12 @@ static inline int irq_to_gpio(unsigned int irq)
  * the method to control only pull up/down/free.
  * this function should be replaced by correct gpio function
  */
-static inline void __init gpio_direction_none(u32 addr)
+static inline void __init gpio_direction_none(void __iomem * addr)
 {
         __raw_writeb(0x00, addr);
 }
 
-static inline void __init gpio_request_pullup(u32 addr)
+static inline void __init gpio_request_pullup(void __iomem * addr)
 {
         u8 data = __raw_readb(addr);
 
@@ -49,7 +35,7 @@ static inline void __init gpio_request_pullup(u32 addr)
         __raw_writeb(data, addr);
 }
 
-static inline void __init gpio_request_pulldown(u32 addr)
+static inline void __init gpio_request_pulldown(void __iomem * addr)
 {
         u8 data = __raw_readb(addr);
 
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 6a35c4a31e6c..f978c5d0e1ae 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -50,7 +50,7 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 
 }
 
-unsigned int __init emev2_get_core_count(void)
+static unsigned int __init emev2_get_core_count(void)
 {
         if (!scu_base) {
                 scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
@@ -62,17 +62,35 @@ unsigned int __init emev2_get_core_count(void)
         return scu_base ? scu_get_core_count(scu_base) : 1;
 }
 
-int emev2_platform_cpu_kill(unsigned int cpu)
+static int emev2_platform_cpu_kill(unsigned int cpu)
 {
         return 0; /* not supported yet */
 }
 
-void __cpuinit emev2_secondary_init(unsigned int cpu)
+static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
+{
+        int k;
+
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (shmobile_cpu_is_dead(cpu))
+                        return emev2_platform_cpu_kill(cpu);
+                mdelay(1);
+        }
+
+        return 0;
+}
+
+
+static void __cpuinit emev2_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
 }
 
-int __cpuinit emev2_boot_secondary(unsigned int cpu)
+static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         cpu = cpu_logical_map(cpu);
 
@@ -86,7 +104,7 @@ int __cpuinit emev2_boot_secondary(unsigned int cpu)
         return 0;
 }
 
-void __init emev2_smp_prepare_cpus(void)
+static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
         int cpu = cpu_logical_map(0);
 
@@ -95,3 +113,22 @@ void __init emev2_smp_prepare_cpus(void)
         /* enable cache coherency on CPU0 */
         modify_scu_cpu_psr(0, 3 << (cpu * 8));
 }
+
+static void __init emev2_smp_init_cpus(void)
+{
+        unsigned int ncores = emev2_get_core_count();
+
+        shmobile_smp_init_cpus(ncores);
+}
+
+struct smp_operations emev2_smp_ops __initdata = {
+        .smp_init_cpus          = emev2_smp_init_cpus,
+        .smp_prepare_cpus       = emev2_smp_prepare_cpus,
+        .smp_secondary_init     = emev2_secondary_init,
+        .smp_boot_secondary     = emev2_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = emev2_cpu_kill,
+        .cpu_die                = shmobile_cpu_die,
+        .cpu_disable            = shmobile_cpu_disable,
+#endif
+};
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 6d1d0238cbf7..2ce6af9a6a37 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -87,14 +87,14 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
         __raw_writel(tmp, scu_base + 8);
 }
 
-unsigned int __init r8a7779_get_core_count(void)
+static unsigned int __init r8a7779_get_core_count(void)
 {
         void __iomem *scu_base = scu_base_addr();
 
         return scu_get_core_count(scu_base);
 }
 
-int r8a7779_platform_cpu_kill(unsigned int cpu)
+static int r8a7779_platform_cpu_kill(unsigned int cpu)
 {
         struct r8a7779_pm_ch *ch = NULL;
         int ret = -EIO;
@@ -113,12 +113,31 @@ int r8a7779_platform_cpu_kill(unsigned int cpu)
         return ret ? ret : 1;
 }
 
-void __cpuinit r8a7779_secondary_init(unsigned int cpu)
+static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
+{
+        int k;
+
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (shmobile_cpu_is_dead(cpu))
+                        return r8a7779_platform_cpu_kill(cpu);
+
+                mdelay(1);
+        }
+
+        return 0;
+}
+
+
+static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
 }
 
-int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
+static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         struct r8a7779_pm_ch *ch = NULL;
         int ret = -EIO;
@@ -137,7 +156,7 @@ int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
         return ret;
 }
 
-void __init r8a7779_smp_prepare_cpus(void)
+static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
         int cpu = cpu_logical_map(0);
 
@@ -156,3 +175,22 @@ void __init r8a7779_smp_prepare_cpus(void)
         r8a7779_platform_cpu_kill(2);
         r8a7779_platform_cpu_kill(3);
 }
+
+static void __init r8a7779_smp_init_cpus(void)
+{
+        unsigned int ncores = r8a7779_get_core_count();
+
+        shmobile_smp_init_cpus(ncores);
+}
+
+struct smp_operations r8a7779_smp_ops  __initdata = {
+        .smp_init_cpus          = r8a7779_smp_init_cpus,
+        .smp_prepare_cpus       = r8a7779_smp_prepare_cpus,
+        .smp_secondary_init     = r8a7779_secondary_init,
+        .smp_boot_secondary     = r8a7779_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = r8a7779_cpu_kill,
+        .cpu_die                = shmobile_cpu_die,
+        .cpu_disable            = shmobile_cpu_disable,
+#endif
+};
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index e36c41c4ab40..624f00f70abf 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -22,8 +22,10 @@
 #include <linux/smp.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/delay.h>
 #include <mach/common.h>
 #include <asm/smp_plat.h>
+#include <mach/sh73a0.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/gic.h>
@@ -64,19 +66,19 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
         __raw_writel(tmp, scu_base + 8);
 }
 
-unsigned int __init sh73a0_get_core_count(void)
+static unsigned int __init sh73a0_get_core_count(void)
 {
         void __iomem *scu_base = scu_base_addr();
 
         return scu_get_core_count(scu_base);
 }
 
-void __cpuinit sh73a0_secondary_init(unsigned int cpu)
+static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
 }
 
-int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
+static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         cpu = cpu_logical_map(cpu);
 
@@ -91,7 +93,7 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
         return 0;
 }
 
-void __init sh73a0_smp_prepare_cpus(void)
+static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
         int cpu = cpu_logical_map(0);
 
@@ -104,3 +106,41 @@ void __init sh73a0_smp_prepare_cpus(void)
         /* enable cache coherency on CPU0 */
         modify_scu_cpu_psr(0, 3 << (cpu * 8));
 }
+
+static void __init sh73a0_smp_init_cpus(void)
+{
+        unsigned int ncores = sh73a0_get_core_count();
+
+        shmobile_smp_init_cpus(ncores);
+}
+
+static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu)
+{
+        int k;
+
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (shmobile_cpu_is_dead(cpu))
+                        return 1;
+
+                mdelay(1);
+        }
+
+        return 0;
+}
+
+
+struct smp_operations sh73a0_smp_ops __initdata = {
+        .smp_init_cpus          = sh73a0_smp_init_cpus,
+        .smp_prepare_cpus       = sh73a0_smp_prepare_cpus,
+        .smp_secondary_init     = sh73a0_secondary_init,
+        .smp_boot_secondary     = sh73a0_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = sh73a0_cpu_kill,
+        .cpu_die                = shmobile_cpu_die,
+        .cpu_disable            = shmobile_cpu_disable,
+#endif
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
new file mode 100644
index 000000000000..803a3281feb5
--- /dev/null
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_SOCFPGA
+        bool "Altera SOCFPGA family" if ARCH_MULTI_V7
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_AMBA
+        select ARM_GIC
+        select CACHE_L2X0
+        select CLKDEV_LOOKUP
+        select COMMON_CLK
+        select CPU_V7
+        select DW_APB_TIMER
+        select DW_APB_TIMER_OF
+        select GENERIC_CLOCKEVENTS
+        select GPIO_PL061 if GPIOLIB
+        select HAVE_ARM_SCU
+        select SPARSE_IRQ
+        select USE_OF
diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot
deleted file mode 100644
index dae9661a7689..000000000000
--- a/arch/arm/mach-socfpga/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y      := 0x00008000
diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h
deleted file mode 100644
index bbe20e696325..000000000000
--- a/arch/arm/mach-socfpga/include/mach/uncompress.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-
-#define putc(c)
-#define flush()
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
-
-#endif
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
index 403efd7e6d27..4674a4c221db 100644
--- a/arch/arm/mach-spear13xx/Makefile.boot
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -1,6 +1,3 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-
-dtb-$(CONFIG_MACH_SPEAR1310)    += spear1310-evb.dtb
-dtb-$(CONFIG_MACH_SPEAR1340)    += spear1340-evb.dtb
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
index 5c6867b46d09..a7d2dd11a4f2 100644
--- a/arch/arm/mach-spear13xx/hotplug.c
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -17,8 +17,6 @@
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
 
-extern volatile int pen_release;
-
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -56,7 +54,7 @@ static inline void cpu_leave_lowpower(void)
         : "cc");
 }
 
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious)
 {
         for (;;) {
                 wfi();
@@ -79,17 +77,12 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
         }
 }
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
  * Called with IRQs disabled
  */
-void __cpuinit platform_cpu_die(unsigned int cpu)
+void __ref spear13xx_cpu_die(unsigned int cpu)
 {
         int spurious = 0;
 
@@ -97,7 +90,7 @@ void __cpuinit platform_cpu_die(unsigned int cpu)
          * we're ready for shutdown now, so do it
          */
         cpu_enter_lowpower();
-        platform_do_lowpower(cpu, &spurious);
+        spear13xx_do_lowpower(cpu, &spurious);
 
         /*
          * bring this CPU back into the world of cache
@@ -108,12 +101,3 @@ void __cpuinit platform_cpu_die(unsigned int cpu)
         if (spurious)
                 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index dac57fd0cdfd..c33f4d9361bd 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -33,6 +33,9 @@ void __init spear13xx_l2x0_init(void);
 bool dw_dma_filter(struct dma_chan *chan, void *slave);
 void spear_restart(char, const char *);
 void spear13xx_secondary_startup(void);
+void __cpuinit spear13xx_cpu_die(unsigned int cpu);
+
+extern struct smp_operations spear13xx_smp_ops;
 
 #ifdef CONFIG_MACH_SPEAR1310
 void __init spear1310_clk_init(void);
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
deleted file mode 100644
index 85f176311f63..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/gpio.h
- *
- * GPIO macros for SPEAr13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-
-#include <plat/gpio.h>
-
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 65f27def239b..07d90acc92c8 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -17,26 +17,26 @@
 #include <asm/memory.h>
 
 #define PERIP_GRP2_BASE                         UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE                      UL(0xFE000000)
+#define VA_PERIP_GRP2_BASE                      IOMEM(0xFE000000)
 #define MCIF_SDHCI_BASE                         UL(0xB3000000)
 #define SYSRAM0_BASE                            UL(0xB3800000)
-#define VA_SYSRAM0_BASE                         UL(0xFE800000)
+#define VA_SYSRAM0_BASE                         IOMEM(0xFE800000)
 #define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
 
 #define PERIP_GRP1_BASE                         UL(0xE0000000)
-#define VA_PERIP_GRP1_BASE                      UL(0xFD000000)
+#define VA_PERIP_GRP1_BASE                      IOMEM(0xFD000000)
 #define UART_BASE                               UL(0xE0000000)
-#define VA_UART_BASE                            UL(0xFD000000)
+#define VA_UART_BASE                            IOMEM(0xFD000000)
 #define SSP_BASE                                UL(0xE0100000)
 #define MISC_BASE                               UL(0xE0700000)
-#define VA_MISC_BASE                            IOMEM(UL(0xFD700000))
+#define VA_MISC_BASE                            IOMEM(0xFD700000)
 
 #define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
-#define VA_A9SM_AND_MPMC_BASE                   UL(0xFC000000)
+#define VA_A9SM_AND_MPMC_BASE                   IOMEM(0xFC000000)
 
 /* A9SM peripheral offsets */
 #define A9SM_PERIP_BASE                         UL(0xEC800000)
-#define VA_A9SM_PERIP_BASE                      UL(0xFC800000)
+#define VA_A9SM_PERIP_BASE                      IOMEM(0xFC800000)
 #define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
 
 #define L2CC_BASE                               UL(0xED000000)
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
index f5d07f2663d7..2eaa3fa7b432 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -19,18 +19,13 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <mach/spear.h>
+#include <mach/generic.h>
 
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
 static DEFINE_SPINLOCK(boot_lock);
 
 static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
-extern void spear13xx_secondary_startup(void);
 
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
 {
         /*
          * if any interrupts are already enabled for the primary
@@ -53,7 +48,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         spin_unlock(&boot_lock);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned long timeout;
 
@@ -97,7 +92,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
-void __init smp_init_cpus(void)
+static void __init spear13xx_smp_init_cpus(void)
 {
         unsigned int i, ncores = scu_get_core_count(scu_base);
 
@@ -113,7 +108,7 @@ void __init smp_init_cpus(void)
         set_smp_cross_call(gic_raise_softirq);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
 {
 
         scu_enable(scu_base);
@@ -125,3 +120,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          */
         __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
 }
+
+struct smp_operations spear13xx_smp_ops __initdata = {
+       .smp_init_cpus           = spear13xx_smp_init_cpus,
+       .smp_prepare_cpus        = spear13xx_smp_prepare_cpus,
+       .smp_secondary_init      = spear13xx_secondary_init,
+       .smp_boot_secondary      = spear13xx_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+       .cpu_die                 = spear13xx_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 732d29bc7330..9fbbfc5650aa 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -78,6 +78,7 @@ static void __init spear1310_map_io(void)
 }
 
 DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
+        .smp            =       smp_ops(spear13xx_smp_ops),
         .map_io         =       spear1310_map_io,
         .init_irq       =       spear13xx_dt_init_irq,
         .handle_irq     =       gic_handle_irq,
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
index 81e4ed76ad06..081014fb314a 100644
--- a/arch/arm/mach-spear13xx/spear1340.c
+++ b/arch/arm/mach-spear13xx/spear1340.c
@@ -182,6 +182,7 @@ static const char * const spear1340_dt_board_compat[] = {
 };
 
 DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
+        .smp            =       smp_ops(spear13xx_smp_ops),
         .map_io         =       spear13xx_map_io,
         .init_irq       =       spear13xx_dt_init_irq,
         .handle_irq     =       gic_handle_irq,
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index cf936b106e27..e10648801b2e 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -114,17 +114,17 @@ void __init spear13xx_l2x0_init(void)
  */
 struct map_desc spear13xx_io_desc[] __initdata = {
         {
-                .virtual        = VA_PERIP_GRP2_BASE,
+                .virtual        = (unsigned long)VA_PERIP_GRP2_BASE,
                 .pfn            = __phys_to_pfn(PERIP_GRP2_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_PERIP_GRP1_BASE,
+                .virtual        = (unsigned long)VA_PERIP_GRP1_BASE,
                 .pfn            = __phys_to_pfn(PERIP_GRP1_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_A9SM_AND_MPMC_BASE,
+                .virtual        = (unsigned long)VA_A9SM_AND_MPMC_BASE,
                 .pfn            = __phys_to_pfn(A9SM_AND_MPMC_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index d93e2177e6ec..4674a4c221db 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,7 +1,3 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-
-dtb-$(CONFIG_MACH_SPEAR300)     += spear300-evb.dtb
-dtb-$(CONFIG_MACH_SPEAR310)     += spear310-evb.dtb
-dtb-$(CONFIG_MACH_SPEAR320)     += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
deleted file mode 100644
index 2ac74c6db7f1..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/gpio.h
- *
- * GPIO macros for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-
-#include <plat/gpio.h>
-
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index af493da37ab6..4674a4c221db 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,5 +1,3 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-
-dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/include/mach/gpio.h b/arch/arm/mach-spear6xx/include/mach/gpio.h
deleted file mode 100644
index d42cefc0356d..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/gpio.h
- *
- * GPIO macros for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-
-#include <plat/gpio.h>
-
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 9077aaa398d9..5f3c03b61f8e 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -34,7 +34,6 @@ config ARCH_TEGRA_3x_SOC
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select USB_ULPI if USB
         select USB_ULPI_VIEWPORT if USB_SUPPORT
-        select USE_OF
         select ARM_ERRATA_743622
         select ARM_ERRATA_751472
         select ARM_ERRATA_754322
@@ -60,25 +59,6 @@ config TEGRA_AHB
 
 comment "Tegra board type"
 
-config MACH_HARMONY
-       bool "Harmony board"
-       depends on ARCH_TEGRA_2x_SOC
-       help
-         Support for nVidia Harmony development platform
-
-config MACH_PAZ00
-       bool "Paz00 board"
-       depends on ARCH_TEGRA_2x_SOC
-       help
-         Support for the Toshiba AC100/Dynabook AZ netbook
-
-config MACH_TRIMSLICE
-       bool "TrimSlice board"
-       depends on ARCH_TEGRA_2x_SOC
-       select TEGRA_PCI
-       help
-         Support for CompuLab TrimSlice platform
-
 choice
         prompt "Default low-level debug console UART"
         default TEGRA_DEBUG_UART_NONE
@@ -130,13 +110,6 @@ config TEGRA_DEBUG_UART_AUTO_SCRATCH
 
 endchoice
 
-config TEGRA_SYSTEM_DMA
-        bool "Enable system DMA driver for NVIDIA Tegra SoCs"
-        default y
-        help
-          Adds system DMA functionality for NVIDIA Tegra SoCs, used by
-          several Tegra device drivers
-
 config TEGRA_EMC_SCALING_ENABLE
         bool "Enable scaling the memory frequency"
 
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c3d7303b9ac8..04eb74e3f601 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,13 +12,16 @@ obj-y					+= powergate.o
 obj-y                                   += apbio.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_CPU_IDLE)                  += sleep.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-t20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-t30.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
@@ -26,13 +29,6 @@ obj-$(CONFIG_USB_SUPPORT)		+= usb_phy.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
 
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pinmux.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pcie.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-harmony-pcie.o
 
-obj-$(CONFIG_MACH_PAZ00)                += board-paz00.o
-obj-$(CONFIG_MACH_PAZ00)                += board-paz00-pinmux.o
-
-obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice.o
-obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice-pinmux.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-paz00.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 7a1bb62ddcf0..29433816233c 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -1,11 +1,3 @@
 zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC)    += 0x00008000
 params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
-
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb
-dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index dc0fe389be56..b5015d0f1912 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -28,7 +28,7 @@
 
 #include "apbio.h"
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA)
+#if defined(CONFIG_TEGRA20_APB_DMA)
 static DEFINE_MUTEX(tegra_apb_dma_lock);
 static u32 *tegra_apb_bb;
 static dma_addr_t tegra_apb_bb_phys;
@@ -37,121 +37,6 @@ static DECLARE_COMPLETION(tegra_apb_wait);
 static u32 tegra_apb_readl_direct(unsigned long offset);
 static void tegra_apb_writel_direct(u32 value, unsigned long offset);
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static struct tegra_dma_channel *tegra_apb_dma;
-
-bool tegra_apb_init(void)
-{
-        struct tegra_dma_channel *ch;
-
-        mutex_lock(&tegra_apb_dma_lock);
-
-        /* Check to see if we raced to setup */
-        if (tegra_apb_dma)
-                goto out;
-
-        ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
-                TEGRA_DMA_SHARED);
-
-        if (!ch)
-                goto out_fail;
-
-        tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
-                &tegra_apb_bb_phys, GFP_KERNEL);
-        if (!tegra_apb_bb) {
-                pr_err("%s: can not allocate bounce buffer\n", __func__);
-                tegra_dma_free_channel(ch);
-                goto out_fail;
-        }
-
-        tegra_apb_dma = ch;
-out:
-        mutex_unlock(&tegra_apb_dma_lock);
-        return true;
-
-out_fail:
-        mutex_unlock(&tegra_apb_dma_lock);
-        return false;
-}
-
-static void apb_dma_complete(struct tegra_dma_req *req)
-{
-        complete(&tegra_apb_wait);
-}
-
-static u32 tegra_apb_readl_using_dma(unsigned long offset)
-{
-        struct tegra_dma_req req;
-        int ret;
-
-        if (!tegra_apb_dma && !tegra_apb_init())
-                return tegra_apb_readl_direct(offset);
-
-        mutex_lock(&tegra_apb_dma_lock);
-        req.complete = apb_dma_complete;
-        req.to_memory = 1;
-        req.dest_addr = tegra_apb_bb_phys;
-        req.dest_bus_width = 32;
-        req.dest_wrap = 1;
-        req.source_addr = offset;
-        req.source_bus_width = 32;
-        req.source_wrap = 4;
-        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
-        req.size = 4;
-
-        INIT_COMPLETION(tegra_apb_wait);
-
-        tegra_dma_enqueue_req(tegra_apb_dma, &req);
-
-        ret = wait_for_completion_timeout(&tegra_apb_wait,
-                msecs_to_jiffies(50));
-
-        if (WARN(ret == 0, "apb read dma timed out")) {
-                tegra_dma_dequeue_req(tegra_apb_dma, &req);
-                *(u32 *)tegra_apb_bb = 0;
-        }
-
-        mutex_unlock(&tegra_apb_dma_lock);
-        return *((u32 *)tegra_apb_bb);
-}
-
-static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
-{
-        struct tegra_dma_req req;
-        int ret;
-
-        if (!tegra_apb_dma && !tegra_apb_init()) {
-                tegra_apb_writel_direct(value, offset);
-                return;
-        }
-
-        mutex_lock(&tegra_apb_dma_lock);
-        *((u32 *)tegra_apb_bb) = value;
-        req.complete = apb_dma_complete;
-        req.to_memory = 0;
-        req.dest_addr = offset;
-        req.dest_wrap = 4;
-        req.dest_bus_width = 32;
-        req.source_addr = tegra_apb_bb_phys;
-        req.source_bus_width = 32;
-        req.source_wrap = 1;
-        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
-        req.size = 4;
-
-        INIT_COMPLETION(tegra_apb_wait);
-
-        tegra_dma_enqueue_req(tegra_apb_dma, &req);
-
-        ret = wait_for_completion_timeout(&tegra_apb_wait,
-                msecs_to_jiffies(50));
-
-        if (WARN(ret == 0, "apb write dma timed out"))
-                tegra_dma_dequeue_req(tegra_apb_dma, &req);
-
-        mutex_unlock(&tegra_apb_dma_lock);
-}
-
-#else
 static struct dma_chan *tegra_apb_dma_chan;
 static struct dma_slave_config dma_sconfig;
 
@@ -279,7 +164,6 @@ static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
                 pr_err("error in writing offset 0x%08lx using dma\n", offset);
         mutex_unlock(&tegra_apb_dma_lock);
 }
-#endif
 #else
 #define tegra_apb_readl_using_dma tegra_apb_readl_direct
 #define tegra_apb_writel_using_dma tegra_apb_writel_direct
@@ -293,12 +177,12 @@ static apbio_write_fptr apbio_write;
 
 static u32 tegra_apb_readl_direct(unsigned long offset)
 {
-        return readl(IO_TO_VIRT(offset));
+        return readl(IO_ADDRESS(offset));
 }
 
 static void tegra_apb_writel_direct(u32 value, unsigned long offset)
 {
-        writel(value, IO_TO_VIRT(offset));
+        writel(value, IO_ADDRESS(offset));
 }
 
 void tegra_apb_io_init(void)
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index c0999633a9ab..5d8c8fb060b0 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -42,9 +42,9 @@
 #include <mach/irqs.h>
 
 #include "board.h"
-#include "board-harmony.h"
 #include "clock.h"
 #include "devices.h"
+#include "common.h"
 
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
@@ -71,6 +71,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 
 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
         /* name         parent          rate            enabled */
+        { "uarta",      "pll_p",        216000000,      true },
         { "uartd",      "pll_p",        216000000,      true },
         { "usbd",       "clk_m",        12000000,       false },
         { "usb2",       "clk_m",        12000000,       false },
@@ -95,54 +96,40 @@ static void __init tegra_dt_init(void)
                                 tegra20_auxdata_lookup, NULL);
 }
 
-#ifdef CONFIG_MACH_TRIMSLICE
 static void __init trimslice_init(void)
 {
+#ifdef CONFIG_TEGRA_PCI
         int ret;
 
         ret = tegra_pcie_init(true, true);
         if (ret)
                 pr_err("tegra_pci_init() failed: %d\n", ret);
-}
 #endif
+}
 
-#ifdef CONFIG_MACH_HARMONY
 static void __init harmony_init(void)
 {
+#ifdef CONFIG_TEGRA_PCI
         int ret;
 
-        ret = harmony_regulator_init();
-        if (ret) {
-                pr_err("harmony_regulator_init() failed: %d\n", ret);
-                return;
-        }
-
         ret = harmony_pcie_init();
         if (ret)
                 pr_err("harmony_pcie_init() failed: %d\n", ret);
-}
 #endif
+}
 
-#ifdef CONFIG_MACH_PAZ00
 static void __init paz00_init(void)
 {
         tegra_paz00_wifikill_init();
 }
-#endif
 
 static struct {
         char *machine;
         void (*init)(void);
 } board_init_funcs[] = {
-#ifdef CONFIG_MACH_TRIMSLICE
         { "compulab,trimslice", trimslice_init },
-#endif
-#ifdef CONFIG_MACH_HARMONY
         { "nvidia,harmony", harmony_init },
-#endif
-#ifdef CONFIG_MACH_PAZ00
         { "compal,paz00", paz00_init },
-#endif
 };
 
 static void __init tegra_dt_init_late(void)
@@ -166,6 +153,7 @@ static const char *tegra20_dt_board_compat[] = {
 
 DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
         .map_io         = tegra_map_common_io,
+        .smp            = smp_ops(tegra_smp_ops),
         .init_early     = tegra20_init_early,
         .init_irq       = tegra_dt_init_irq,
         .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 53bf60f11580..e4a676d4ddf7 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -37,6 +37,7 @@
 
 #include "board.h"
 #include "clock.h"
+#include "common.h"
 
 struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
@@ -83,6 +84,7 @@ static const char *tegra30_dt_board_compat[] = {
 };
 
 DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
+        .smp            = smp_ops(tegra_smp_ops),
         .map_io         = tegra_map_common_io,
         .init_early     = tegra30_init_early,
         .init_irq       = tegra_dt_init_irq,
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index e8c3fda9bec2..3cdc1bb8254c 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -18,35 +18,57 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <linux/err.h>
+#include <linux/of_gpio.h>
 #include <linux/regulator/consumer.h>
 
 #include <asm/mach-types.h>
 
 #include "board.h"
-#include "board-harmony.h"
 
 #ifdef CONFIG_TEGRA_PCI
 
 int __init harmony_pcie_init(void)
 {
+        struct device_node *np;
+        int en_vdd_1v05;
         struct regulator *regulator = NULL;
         int err;
 
-        err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
-        if (err)
+        np = of_find_node_by_path("/regulators/regulator@3");
+        if (!np) {
+                pr_err("%s: of_find_node_by_path failed\n", __func__);
+                return -ENODEV;
+        }
+
+        en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0);
+        if (en_vdd_1v05 < 0) {
+                pr_err("%s: of_get_named_gpio failed: %d\n", __func__,
+                       en_vdd_1v05);
+                return en_vdd_1v05;
+        }
+
+        err = gpio_request(en_vdd_1v05, "EN_VDD_1V05");
+        if (err) {
+                pr_err("%s: gpio_request failed: %d\n", __func__, err);
                 return err;
+        }
 
-        gpio_direction_output(TEGRA_GPIO_EN_VDD_1V05_GPIO, 1);
+        gpio_direction_output(en_vdd_1v05, 1);
 
-        regulator = regulator_get(NULL, "pex_clk");
-        if (IS_ERR_OR_NULL(regulator))
+        regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
+        if (IS_ERR_OR_NULL(regulator)) {
+                pr_err("%s: regulator_get failed: %d\n", __func__,
+                       (int)PTR_ERR(regulator));
                 goto err_reg;
+        }
 
         regulator_enable(regulator);
 
         err = tegra_pcie_init(true, true);
-        if (err)
+        if (err) {
+                pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err);
                 goto err_pcie;
+        }
 
         return 0;
 
@@ -54,20 +76,9 @@ err_pcie:
         regulator_disable(regulator);
         regulator_put(regulator);
 err_reg:
-        gpio_free(TEGRA_GPIO_EN_VDD_1V05_GPIO);
+        gpio_free(en_vdd_1v05);
 
         return err;
 }
 
-static int __init harmony_pcie_initcall(void)
-{
-        if (!machine_is_harmony())
-                return 0;
-
-        return harmony_pcie_init();
-}
-
-/* PCI should be initialized after I2C, mfd and regulators */
-subsys_initcall_sync(harmony_pcie_initcall);
-
 #endif
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
deleted file mode 100644
index 83d420fbc58c..000000000000
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony-pinmux.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include "board-harmony.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map harmony_map[] = {
-        TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
-        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
-        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-        TEGRA_MAP_MUXCONF("dta",   "sdio2",         up,   driven),
-        TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, driven),
-        TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtd",   "sdio2",         up,   driven),
-        TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, tristate),
-        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
-        TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gpu",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-        TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   tristate),
-        TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   tristate),
-        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         na,   tristate),
-        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-        TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("spia",  "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("spib",  "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   tristate),
-        TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-        TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
-        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-        TEGRA_MAP_CONF("ck32",    none, na),
-        TEGRA_MAP_CONF("ddrc",    none, na),
-        TEGRA_MAP_CONF("pmca",    none, na),
-        TEGRA_MAP_CONF("pmcb",    none, na),
-        TEGRA_MAP_CONF("pmcc",    none, na),
-        TEGRA_MAP_CONF("pmcd",    none, na),
-        TEGRA_MAP_CONF("pmce",    none, na),
-        TEGRA_MAP_CONF("xm2c",    none, na),
-        TEGRA_MAP_CONF("xm2d",    none, na),
-        TEGRA_MAP_CONF("ls",      up,   na),
-        TEGRA_MAP_CONF("lc",      up,   na),
-        TEGRA_MAP_CONF("ld17_0",  down, na),
-        TEGRA_MAP_CONF("ld19_18", down, na),
-        TEGRA_MAP_CONF("ld21_20", down, na),
-        TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
-        .maps = harmony_map,
-        .map_count = ARRAY_SIZE(harmony_map),
-};
-
-void harmony_pinmux_init(void)
-{
-        tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
deleted file mode 100644
index b7344beec102..000000000000
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2010 NVIDIA, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- * 02111-1307, USA
- */
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/tps6586x.h>
-#include <linux/of.h>
-#include <linux/of_i2c.h>
-
-#include <asm/mach-types.h>
-
-#include <mach/irqs.h>
-
-#include "board-harmony.h"
-
-static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
-        REGULATOR_SUPPLY("pex_clk", NULL),
-};
-
-static struct regulator_init_data ldo0_data = {
-        .supply_regulator = "vdd_sm2",
-        .constraints = {
-                .name = "vdd_ldo0",
-                .min_uV = 3300 * 1000,
-                .max_uV = 3300 * 1000,
-                .valid_modes_mask = (REGULATOR_MODE_NORMAL |
-                                     REGULATOR_MODE_STANDBY),
-                .valid_ops_mask = (REGULATOR_CHANGE_MODE |
-                                   REGULATOR_CHANGE_STATUS |
-                                   REGULATOR_CHANGE_VOLTAGE),
-                .apply_uV = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply),
-        .consumer_supplies = tps658621_ldo0_supply,
-};
-
-#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\
-        static struct regulator_init_data _id##_data = {                \
-                .supply_regulator = _supply,                            \
-                .constraints = {                                        \
-                        .name = _name,                                  \
-                        .min_uV = (_minmv)*1000,                        \
-                        .max_uV = (_maxmv)*1000,                        \
-                        .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
-                                             REGULATOR_MODE_STANDBY),   \
-                        .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
-                                           REGULATOR_CHANGE_STATUS |    \
-                                           REGULATOR_CHANGE_VOLTAGE),   \
-                        .always_on = _on,                               \
-                },                                                      \
-        }
-
-HARMONY_REGULATOR_INIT(sm0,  "vdd_sm0",  "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm1,  "vdd_sm1",  "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm2,  "vdd_sm2",  "vdd_sys", 3000, 4550, 1);
-HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0);
-HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1);
-HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL,      1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1);
-
-#define TPS_REG(_id, _data)                     \
-        {                                       \
-                .id = TPS6586X_ID_##_id,        \
-                .name = "tps6586x-regulator",   \
-                .platform_data = _data,         \
-        }
-
-static struct tps6586x_subdev_info tps_devs[] = {
-        TPS_REG(SM_0, &sm0_data),
-        TPS_REG(SM_1, &sm1_data),
-        TPS_REG(SM_2, &sm2_data),
-        TPS_REG(LDO_0, &ldo0_data),
-        TPS_REG(LDO_1, &ldo1_data),
-        TPS_REG(LDO_2, &ldo2_data),
-        TPS_REG(LDO_3, &ldo3_data),
-        TPS_REG(LDO_4, &ldo4_data),
-        TPS_REG(LDO_5, &ldo5_data),
-        TPS_REG(LDO_6, &ldo6_data),
-        TPS_REG(LDO_7, &ldo7_data),
-        TPS_REG(LDO_8, &ldo8_data),
-        TPS_REG(LDO_9, &ldo9_data),
-};
-
-static struct tps6586x_platform_data tps_platform = {
-        .irq_base       = TEGRA_NR_IRQS,
-        .num_subdevs    = ARRAY_SIZE(tps_devs),
-        .subdevs        = tps_devs,
-        .gpio_base      = HARMONY_GPIO_TPS6586X(0),
-};
-
-static struct i2c_board_info __initdata harmony_regulators[] = {
-        {
-                I2C_BOARD_INFO("tps6586x", 0x34),
-                .irq            = INT_EXTERNAL_PMU,
-                .platform_data  = &tps_platform,
-        },
-};
-
-int __init harmony_regulator_init(void)
-{
-        regulator_register_always_on(0, "vdd_sys",
-                NULL, 0, 5000000);
-
-        if (machine_is_harmony()) {
-                i2c_register_board_info(3, harmony_regulators, 1);
-        } else { /* Harmony, booted using device tree */
-                struct device_node *np;
-                struct i2c_adapter *adapter;
-
-                np = of_find_node_by_path("/i2c@7000d000");
-                if (np == NULL) {
-                        pr_err("Could not find device_node for DVC I2C\n");
-                        return -ENODEV;
-                }
-
-                adapter = of_find_i2c_adapter_by_node(np);
-                if (!adapter) {
-                        pr_err("Could not find i2c_adapter for DVC I2C\n");
-                        return -ENODEV;
-                }
-
-                i2c_new_device(adapter, harmony_regulators);
-        }
-
-        return 0;
-}
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
deleted file mode 100644
index e65e837f4013..000000000000
--- a/arch/arm/mach-tegra/board-harmony.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011 NVIDIA, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-
-#include <sound/wm8903.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-
-#include <mach/tegra_wm8903_pdata.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
-#include "board-harmony.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-        {
-                .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
-                .mapbase        = TEGRA_UARTD_BASE,
-                .irq            = INT_UARTD,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-                .type           = PORT_TEGRA,
-                .handle_break   = tegra_serial_handle_break,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 216000000,
-        }, {
-                .flags          = 0
-        }
-};
-
-static struct platform_device debug_uart = {
-        .name = "serial8250",
-        .id = PLAT8250_DEV_PLATFORM,
-        .dev = {
-                .platform_data = debug_uart_platform_data,
-        },
-};
-
-static struct tegra_wm8903_platform_data harmony_audio_pdata = {
-        .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
-        .gpio_hp_det            = TEGRA_GPIO_HP_DET,
-        .gpio_hp_mute           = -1,
-        .gpio_int_mic_en        = TEGRA_GPIO_INT_MIC_EN,
-        .gpio_ext_mic_en        = TEGRA_GPIO_EXT_MIC_EN,
-};
-
-static struct platform_device harmony_audio_device = {
-        .name   = "tegra-snd-wm8903",
-        .id     = 0,
-        .dev    = {
-                .platform_data  = &harmony_audio_pdata,
-        },
-};
-
-static struct wm8903_platform_data harmony_wm8903_pdata = {
-        .irq_active_low = 0,
-        .micdet_cfg = 0,
-        .micdet_delay = 100,
-        .gpio_base = HARMONY_GPIO_WM8903(0),
-        .gpio_cfg = {
-                0,
-                0,
-                WM8903_GPIO_CONFIG_ZERO,
-                0,
-                0,
-        },
-};
-
-static struct i2c_board_info __initdata wm8903_board_info = {
-        I2C_BOARD_INFO("wm8903", 0x1a),
-        .platform_data = &harmony_wm8903_pdata,
-};
-
-static void __init harmony_i2c_init(void)
-{
-        platform_device_register(&tegra_i2c_device1);
-        platform_device_register(&tegra_i2c_device2);
-        platform_device_register(&tegra_i2c_device3);
-        platform_device_register(&tegra_i2c_device4);
-
-        wm8903_board_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
-        i2c_register_board_info(0, &wm8903_board_info, 1);
-}
-
-static struct platform_device *harmony_devices[] __initdata = {
-        &debug_uart,
-        &tegra_sdhci_device1,
-        &tegra_sdhci_device2,
-        &tegra_sdhci_device4,
-        &tegra_ehci3_device,
-        &tegra_i2s_device1,
-        &tegra_das_device,
-        &harmony_audio_device,
-};
-
-static void __init tegra_harmony_fixup(struct tag *tags, char **cmdline,
-        struct meminfo *mi)
-{
-        mi->nr_banks = 2;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size = 448 * SZ_1M;
-        mi->bank[1].start = SZ_512M;
-        mi->bank[1].size = SZ_512M;
-}
-
-static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uartd",      "pll_p",        216000000,      true },
-        { "pll_a",      "pll_p_out1",   56448000,       true },
-        { "pll_a_out0", "pll_a",        11289600,       true },
-        { "cdev1",      NULL,           0,              true },
-        { "i2s1",       "pll_a_out0",   11289600,       false},
-        { "usb3",       "clk_m",        12000000,       true },
-        { NULL,         NULL,           0,              0},
-};
-
-
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-        .cd_gpio        = -1,
-        .wp_gpio        = -1,
-        .power_gpio     = -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata2 = {
-        .cd_gpio        = TEGRA_GPIO_SD2_CD,
-        .wp_gpio        = TEGRA_GPIO_SD2_WP,
-        .power_gpio     = TEGRA_GPIO_SD2_POWER,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-        .cd_gpio        = TEGRA_GPIO_SD4_CD,
-        .wp_gpio        = TEGRA_GPIO_SD4_WP,
-        .power_gpio     = TEGRA_GPIO_SD4_POWER,
-        .is_8bit        = 1,
-};
-
-static void __init tegra_harmony_init(void)
-{
-        tegra_clk_init_from_table(harmony_clk_init_table);
-
-        harmony_pinmux_init();
-
-        tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-        tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
-        tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-        platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
-        harmony_i2c_init();
-        harmony_regulator_init();
-}
-
-MACHINE_START(HARMONY, "harmony")
-        .atag_offset    = 0x100,
-        .fixup          = tegra_harmony_fixup,
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra20_init_early,
-        .init_irq       = tegra_init_irq,
-        .handle_irq     = gic_handle_irq,
-        .timer          = &tegra_timer,
-        .init_machine   = tegra_harmony_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
deleted file mode 100644
index 139d96c93843..000000000000
--- a/arch/arm/mach-tegra/board-harmony.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_BOARD_HARMONY_H
-#define _MACH_TEGRA_BOARD_HARMONY_H
-
-#include <mach/gpio-tegra.h>
-
-#define HARMONY_GPIO_TPS6586X(_x_)      (TEGRA_NR_GPIOS + (_x_))
-#define HARMONY_GPIO_WM8903(_x_)        (HARMONY_GPIO_TPS6586X(4) + (_x_))
-
-#define TEGRA_GPIO_SD2_CD               TEGRA_GPIO_PI5
-#define TEGRA_GPIO_SD2_WP               TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD2_POWER            TEGRA_GPIO_PT3
-#define TEGRA_GPIO_SD4_CD               TEGRA_GPIO_PH2
-#define TEGRA_GPIO_SD4_WP               TEGRA_GPIO_PH3
-#define TEGRA_GPIO_SD4_POWER            TEGRA_GPIO_PI6
-#define TEGRA_GPIO_CDC_IRQ              TEGRA_GPIO_PX3
-#define TEGRA_GPIO_SPKR_EN              HARMONY_GPIO_WM8903(2)
-#define TEGRA_GPIO_HP_DET               TEGRA_GPIO_PW2
-#define TEGRA_GPIO_INT_MIC_EN           TEGRA_GPIO_PX0
-#define TEGRA_GPIO_EXT_MIC_EN           TEGRA_GPIO_PX1
-#define TEGRA_GPIO_EN_VDD_1V05_GPIO     HARMONY_GPIO_TPS6586X(2)
-
-void harmony_pinmux_init(void);
-int harmony_regulator_init(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
deleted file mode 100644
index 6f1111b48e7c..000000000000
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-paz00-pinmux.c
- *
- * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include "board-paz00.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map paz00_map[] = {
-        TEGRA_MAP_MUXCONF("ata",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("atc",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, driven),
-        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-        TEGRA_MAP_MUXCONF("csus",  "pllc_out1",     down, tristate),
-        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        TEGRA_MAP_MUXCONF("dap2",  "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-        TEGRA_MAP_MUXCONF("dta",   "rsvd1",         up,   tristate),
-        TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtd",   "rsvd1",         up,   tristate),
-        TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
-        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gmc",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
-        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   driven),
-        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-        TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   driven),
-        TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   driven),
-        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcb",  "sdio2",         up,   driven),
-        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcd",  "sdio2",         up,   driven),
-        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("owc",   "owr",           up,   tristate),
-        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-        TEGRA_MAP_MUXCONF("sdc",   "twc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, tristate),
-        TEGRA_MAP_MUXCONF("slxc",  "spi4",          none, tristate),
-        TEGRA_MAP_MUXCONF("slxd",  "spi4",          none, tristate),
-        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
-        TEGRA_MAP_MUXCONF("spia",  "gmi",           down, tristate),
-        TEGRA_MAP_MUXCONF("spib",  "gmi",           down, tristate),
-        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
-        TEGRA_MAP_MUXCONF("spid",  "gmi",           down, tristate),
-        TEGRA_MAP_MUXCONF("spie",  "gmi",           up,   tristate),
-        TEGRA_MAP_MUXCONF("spif",  "rsvd4",         down, tristate),
-        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   driven),
-        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
-        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
-        TEGRA_MAP_MUXCONF("uac",   "rsvd4",         none, driven),
-        TEGRA_MAP_MUXCONF("uad",   "spdif",         up,   tristate),
-        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
-        TEGRA_MAP_CONF("ck32",    none, na),
-        TEGRA_MAP_CONF("ddrc",    none, na),
-        TEGRA_MAP_CONF("pmca",    none, na),
-        TEGRA_MAP_CONF("pmcb",    none, na),
-        TEGRA_MAP_CONF("pmcc",    none, na),
-        TEGRA_MAP_CONF("pmcd",    none, na),
-        TEGRA_MAP_CONF("pmce",    none, na),
-        TEGRA_MAP_CONF("xm2c",    none, na),
-        TEGRA_MAP_CONF("xm2d",    none, na),
-        TEGRA_MAP_CONF("ls",      up,   na),
-        TEGRA_MAP_CONF("lc",      up,   na),
-        TEGRA_MAP_CONF("ld17_0",  down, na),
-        TEGRA_MAP_CONF("ld19_18", down, na),
-        TEGRA_MAP_CONF("ld21_20", down, na),
-        TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
-        .maps = paz00_map,
-        .map_count = ARRAY_SIZE(paz00_map),
-};
-
-void paz00_pinmux_init(void)
-{
-        tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 4b64af5cab27..740e16f64728 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -17,72 +17,10 @@
  *
  */
 
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio_keys.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
 #include <linux/rfkill-gpio.h>
-
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/setup.h>
-
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-
 #include "board.h"
 #include "board-paz00.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-        {
-                /* serial port on JP1 */
-                .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
-                .mapbase        = TEGRA_UARTA_BASE,
-                .irq            = INT_UARTA,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-                .type           = PORT_TEGRA,
-                .handle_break   = tegra_serial_handle_break,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 216000000,
-        }, {
-                /* serial port on mini-pcie */
-                .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
-                .mapbase        = TEGRA_UARTC_BASE,
-                .irq            = INT_UARTC,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-                .type           = PORT_TEGRA,
-                .handle_break   = tegra_serial_handle_break,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 216000000,
-        }, {
-                .flags          = 0
-        }
-};
-
-static struct platform_device debug_uart = {
-        .name = "serial8250",
-        .id = PLAT8250_DEV_PLATFORM,
-        .dev = {
-                .platform_data = debug_uart_platform_data,
-        },
-};
 
 static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
         .name           = "wifi_rfkill",
@@ -99,137 +37,7 @@ static struct platform_device wifi_rfkill_device = {
         },
 };
 
-static struct gpio_led gpio_leds[] = {
-        {
-                .name                   = "wifi-led",
-                .default_trigger        = "rfkill0",
-                .gpio                   = TEGRA_WIFI_LED,
-        },
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
-        .leds           = gpio_leds,
-        .num_leds       = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &gpio_led_info,
-        },
-};
-
-static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
-        {
-                .code           = KEY_POWER,
-                .gpio           = TEGRA_GPIO_POWERKEY,
-                .active_low     = 1,
-                .desc           = "Power",
-                .type           = EV_KEY,
-                .wakeup         = 1,
-        },
-};
-
-static struct gpio_keys_platform_data paz00_gpio_keys = {
-        .buttons        = paz00_gpio_keys_buttons,
-        .nbuttons       = ARRAY_SIZE(paz00_gpio_keys_buttons),
-};
-
-static struct platform_device gpio_keys_device = {
-        .name   = "gpio-keys",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &paz00_gpio_keys,
-        },
-};
-
-static struct platform_device *paz00_devices[] __initdata = {
-        &debug_uart,
-        &tegra_sdhci_device4,
-        &tegra_sdhci_device1,
-        &leds_gpio,
-        &gpio_keys_device,
-};
-
-static void paz00_i2c_init(void)
-{
-        platform_device_register(&tegra_i2c_device1);
-        platform_device_register(&tegra_i2c_device2);
-        platform_device_register(&tegra_i2c_device4);
-}
-
-static void paz00_usb_init(void)
-{
-        tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST;
-
-        platform_device_register(&tegra_ehci2_device);
-        platform_device_register(&tegra_ehci3_device);
-}
-
-static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
-        struct meminfo *mi)
-{
-        mi->nr_banks = 1;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size = 448 * SZ_1M;
-}
-
-static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uarta",      "pll_p",        216000000,      true },
-        { "uartc",      "pll_p",        216000000,      true },
-
-        { "usbd",       "clk_m",        12000000,       false },
-        { "usb2",       "clk_m",        12000000,       false },
-        { "usb3",       "clk_m",        12000000,       false },
-
-        { NULL,         NULL,           0,              0},
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-        .cd_gpio        = TEGRA_GPIO_SD1_CD,
-        .wp_gpio        = TEGRA_GPIO_SD1_WP,
-        .power_gpio     = TEGRA_GPIO_SD1_POWER,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-        .cd_gpio        = -1,
-        .wp_gpio        = -1,
-        .power_gpio     = -1,
-        .is_8bit        = 1,
-};
-
 void __init tegra_paz00_wifikill_init(void)
 {
         platform_device_register(&wifi_rfkill_device);
 }
-
-static void __init tegra_paz00_init(void)
-{
-        tegra_clk_init_from_table(paz00_clk_init_table);
-
-        paz00_pinmux_init();
-
-        tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-        tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-        platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
-        tegra_paz00_wifikill_init();
-
-        paz00_i2c_init();
-        paz00_usb_init();
-}
-
-MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
-        .atag_offset    = 0x100,
-        .fixup          = tegra_paz00_fixup,
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra20_init_early,
-        .init_irq       = tegra_init_irq,
-        .handle_irq     = gic_handle_irq,
-        .timer          = &tegra_timer,
-        .init_machine   = tegra_paz00_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index 3c9f8da37ea3..25c08ecef52f 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -17,24 +17,9 @@
 #ifndef _MACH_TEGRA_BOARD_PAZ00_H
 #define _MACH_TEGRA_BOARD_PAZ00_H
 
-#include <mach/gpio-tegra.h>
+#include "gpio-names.h"
 
-/* SDCARD */
-#define TEGRA_GPIO_SD1_CD               TEGRA_GPIO_PV5
-#define TEGRA_GPIO_SD1_WP               TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD1_POWER            TEGRA_GPIO_PV1
-
-/* ULPI */
-#define TEGRA_ULPI_RST                  TEGRA_GPIO_PV0
-
-/* WIFI */
 #define TEGRA_WIFI_PWRN                 TEGRA_GPIO_PK5
 #define TEGRA_WIFI_RST                  TEGRA_GPIO_PD1
-#define TEGRA_WIFI_LED                  TEGRA_GPIO_PD0
-
-/* WakeUp */
-#define TEGRA_GPIO_POWERKEY     TEGRA_GPIO_PJ7
-
-void paz00_pinmux_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
deleted file mode 100644
index 7b39511c0d4d..000000000000
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice-pinmux.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-
-#include "board-trimslice.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map trimslice_map[] = {
-        TEGRA_MAP_MUXCONF("ata",   "ide",           none, tristate),
-        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("atc",   "nand",          none, tristate),
-        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-        TEGRA_MAP_MUXCONF("dta",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dtb",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dtc",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dtd",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dte",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          up,   driven),
-        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gmb",   "nand",          none, tristate),
-        TEGRA_MAP_MUXCONF("gmc",   "sflash",        none, driven),
-        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
-        TEGRA_MAP_MUXCONF("gme",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("gpu",   "uarta",         none, driven),
-        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, tristate),
-        TEGRA_MAP_MUXCONF("irrx",  "uartb",         up,   tristate),
-        TEGRA_MAP_MUXCONF("irtx",  "uartb",         up,   tristate),
-        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         up,   tristate),
-        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   tristate),
-        TEGRA_MAP_MUXCONF("pta",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("rm",    "i2c1",          up,   driven),
-        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   driven),
-        TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   driven),
-        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxd",  "sdio3",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("spdi",  "spdif",         none, tristate),
-        TEGRA_MAP_MUXCONF("spdo",  "spdif",         none, tristate),
-        TEGRA_MAP_MUXCONF("spia",  "spi2",          down, tristate),
-        TEGRA_MAP_MUXCONF("spib",  "spi2",          down, tristate),
-        TEGRA_MAP_MUXCONF("spic",  "spi2",          up,   tristate),
-        TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-        TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
-        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
-        TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-        TEGRA_MAP_CONF("ck32",    none, na),
-        TEGRA_MAP_CONF("ddrc",    none, na),
-        TEGRA_MAP_CONF("pmca",    none, na),
-        TEGRA_MAP_CONF("pmcb",    none, na),
-        TEGRA_MAP_CONF("pmcc",    none, na),
-        TEGRA_MAP_CONF("pmcd",    none, na),
-        TEGRA_MAP_CONF("pmce",    none, na),
-        TEGRA_MAP_CONF("xm2c",    none, na),
-        TEGRA_MAP_CONF("xm2d",    none, na),
-        TEGRA_MAP_CONF("ls",      up,   na),
-        TEGRA_MAP_CONF("lc",      up,   na),
-        TEGRA_MAP_CONF("ld17_0",  down, na),
-        TEGRA_MAP_CONF("ld19_18", down, na),
-        TEGRA_MAP_CONF("ld21_20", down, na),
-        TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
-        .maps = trimslice_map,
-        .map_count = ARRAY_SIZE(trimslice_map),
-};
-
-void trimslice_pinmux_init(void)
-{
-        tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
deleted file mode 100644
index 776aa9564d5d..000000000000
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Author: Mike Rapoport <mike@compulab.co.il>
- *
- * Based on board-harmony.c
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/tegra_usb.h>
-
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-
-#include <mach/iomap.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-#include "board-trimslice.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-        {
-                .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
-                .mapbase        = TEGRA_UARTA_BASE,
-                .irq            = INT_UARTA,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-                .type           = PORT_TEGRA,
-                .handle_break   = tegra_serial_handle_break,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 216000000,
-        }, {
-                .flags          = 0
-        }
-};
-
-static struct platform_device debug_uart = {
-        .name   = "serial8250",
-        .id     = PLAT8250_DEV_PLATFORM,
-        .dev    = {
-                .platform_data  = debug_uart_platform_data,
-        },
-};
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-        .cd_gpio        = -1,
-        .wp_gpio        = -1,
-        .power_gpio     = -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-        .cd_gpio        = TRIMSLICE_GPIO_SD4_CD,
-        .wp_gpio        = TRIMSLICE_GPIO_SD4_WP,
-        .power_gpio     = -1,
-};
-
-static struct platform_device trimslice_audio_device = {
-        .name   = "tegra-snd-trimslice",
-        .id     = 0,
-};
-
-static struct platform_device *trimslice_devices[] __initdata = {
-        &debug_uart,
-        &tegra_sdhci_device1,
-        &tegra_sdhci_device4,
-        &tegra_i2s_device1,
-        &tegra_das_device,
-        &trimslice_audio_device,
-};
-
-static struct i2c_board_info trimslice_i2c3_board_info[] = {
-        {
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        },
-        {
-                I2C_BOARD_INFO("em3027", 0x56),
-        },
-};
-
-static void trimslice_i2c_init(void)
-{
-        platform_device_register(&tegra_i2c_device1);
-        platform_device_register(&tegra_i2c_device2);
-        platform_device_register(&tegra_i2c_device3);
-
-        i2c_register_board_info(2, trimslice_i2c3_board_info,
-                                ARRAY_SIZE(trimslice_i2c3_board_info));
-}
-
-static void trimslice_usb_init(void)
-{
-        struct tegra_ehci_platform_data *pdata;
-
-        pdata = tegra_ehci1_device.dev.platform_data;
-        pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
-
-        tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0;
-
-        platform_device_register(&tegra_ehci3_device);
-        platform_device_register(&tegra_ehci2_device);
-        platform_device_register(&tegra_ehci1_device);
-}
-
-static void __init tegra_trimslice_fixup(struct tag *tags, char **cmdline,
-        struct meminfo *mi)
-{
-        mi->nr_banks = 2;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size = 448 * SZ_1M;
-        mi->bank[1].start = SZ_512M;
-        mi->bank[1].size = SZ_512M;
-}
-
-static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uarta",      "pll_p",        216000000,      true },
-        { "pll_a",      "pll_p_out1",   56448000,       true },
-        { "pll_a_out0", "pll_a",        11289600,       true },
-        { "cdev1",      NULL,           0,              true },
-        { "i2s1",       "pll_a_out0",   11289600,       false},
-        { NULL,         NULL,           0,              0},
-};
-
-static int __init tegra_trimslice_pci_init(void)
-{
-        if (!machine_is_trimslice())
-                return 0;
-
-        return tegra_pcie_init(true, true);
-}
-subsys_initcall(tegra_trimslice_pci_init);
-
-static void __init tegra_trimslice_init(void)
-{
-        tegra_clk_init_from_table(trimslice_clk_init_table);
-
-        trimslice_pinmux_init();
-
-        tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-        tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-        platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
-
-        trimslice_i2c_init();
-        trimslice_usb_init();
-}
-
-MACHINE_START(TRIMSLICE, "trimslice")
-        .atag_offset    = 0x100,
-        .fixup          = tegra_trimslice_fixup,
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra20_init_early,
-        .init_irq       = tegra_init_irq,
-        .handle_irq     = gic_handle_irq,
-        .timer          = &tegra_timer,
-        .init_machine   = tegra_trimslice_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h
deleted file mode 100644
index 50f128d87779..000000000000
--- a/arch/arm/mach-tegra/board-trimslice.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.h
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H
-#define _MACH_TEGRA_BOARD_TRIMSLICE_H
-
-#include <mach/gpio-tegra.h>
-
-#define TRIMSLICE_GPIO_SD4_CD   TEGRA_GPIO_PP1  /* mmc4 cd */
-#define TRIMSLICE_GPIO_SD4_WP   TEGRA_GPIO_PP2  /* mmc4 wp */
-
-#define TRIMSLICE_GPIO_USB1_MODE        TEGRA_GPIO_PV2 /* USB1 mode */
-#define TRIMSLICE_GPIO_USB2_RST         TEGRA_GPIO_PV0 /* USB2 PHY reset */
-
-void trimslice_pinmux_init(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 58f981c0819c..fd82085eca5d 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,6 +1,7 @@
 /*
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@google.com>
@@ -19,8 +20,6 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/module.h>
@@ -32,325 +31,75 @@
 
 #include "board.h"
 #include "clock.h"
+#include "tegra_cpu_car.h"
+
+/* Global data of Tegra CPU CAR ops */
+struct tegra_cpu_car_ops *tegra_cpu_car_ops;
 
 /*
  * Locking:
  *
- * Each struct clk has a spinlock.
- *
- * To avoid AB-BA locking problems, locks must always be traversed from child
- * clock to parent clock.  For example, when enabling a clock, the clock's lock
- * is taken, and then clk_enable is called on the parent, which take's the
- * parent clock's lock.  There is one exceptions to this ordering: When dumping
- * the clock tree through debugfs.  In this case, clk_lock_all is called,
- * which attemps to iterate through the entire list of clocks and take every
- * clock lock.  If any call to spin_trylock fails, all locked clocks are
- * unlocked, and the process is retried.  When all the locks are held,
- * the only clock operation that can be called is clk_get_rate_all_locked.
- *
- * Within a single clock, no clock operation can call another clock operation
- * on itself, except for clk_get_rate_locked and clk_set_rate_locked.  Any
- * clock operation can call any other clock operation on any of it's possible
- * parents.
- *
  * An additional mutex, clock_list_lock, is used to protect the list of all
  * clocks.
  *
- * The clock operations must lock internally to protect against
- * read-modify-write on registers that are shared by multiple clocks
  */
 static DEFINE_MUTEX(clock_list_lock);
 static LIST_HEAD(clocks);
 
-struct clk *tegra_get_clock_by_name(const char *name)
-{
-        struct clk *c;
-        struct clk *ret = NULL;
-        mutex_lock(&clock_list_lock);
-        list_for_each_entry(c, &clocks, node) {
-                if (strcmp(c->name, name) == 0) {
-                        ret = c;
-                        break;
-                }
-        }
-        mutex_unlock(&clock_list_lock);
-        return ret;
-}
-
-/* Must be called with c->spinlock held */
-static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
-{
-        u64 rate;
-
-        rate = clk_get_rate(p);
-
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-
-        return rate;
-}
-
-/* Must be called with c->spinlock held */
-unsigned long clk_get_rate_locked(struct clk *c)
-{
-        unsigned long rate;
-
-        if (c->parent)
-                rate = clk_predict_rate_from_parent(c, c->parent);
-        else
-                rate = c->rate;
-
-        return rate;
-}
-
-unsigned long clk_get_rate(struct clk *c)
+void tegra_clk_add(struct clk *clk)
 {
-        unsigned long flags;
-        unsigned long rate;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        rate = clk_get_rate_locked(c);
-
-        spin_unlock_irqrestore(&c->spinlock, flags);
-
-        return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_reparent(struct clk *c, struct clk *parent)
-{
-        c->parent = parent;
-        return 0;
-}
-
-void clk_init(struct clk *c)
-{
-        spin_lock_init(&c->spinlock);
-
-        if (c->ops && c->ops->init)
-                c->ops->init(c);
-
-        if (!c->ops || !c->ops->enable) {
-                c->refcnt++;
-                c->set = true;
-                if (c->parent)
-                        c->state = c->parent->state;
-                else
-                        c->state = ON;
-        }
+        struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
 
         mutex_lock(&clock_list_lock);
         list_add(&c->node, &clocks);
         mutex_unlock(&clock_list_lock);
 }
 
-int clk_enable(struct clk *c)
-{
-        int ret = 0;
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (c->refcnt == 0) {
-                if (c->parent) {
-                        ret = clk_enable(c->parent);
-                        if (ret)
-                                goto out;
-                }
-
-                if (c->ops && c->ops->enable) {
-                        ret = c->ops->enable(c);
-                        if (ret) {
-                                if (c->parent)
-                                        clk_disable(c->parent);
-                                goto out;
-                        }
-                        c->state = ON;
-                        c->set = true;
-                }
-        }
-        c->refcnt++;
-out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *c)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (c->refcnt == 0) {
-                WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
-                spin_unlock_irqrestore(&c->spinlock, flags);
-                return;
-        }
-        if (c->refcnt == 1) {
-                if (c->ops && c->ops->disable)
-                        c->ops->disable(c);
-
-                if (c->parent)
-                        clk_disable(c->parent);
-
-                c->state = OFF;
-        }
-        c->refcnt--;
-
-        spin_unlock_irqrestore(&c->spinlock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-int clk_set_parent(struct clk *c, struct clk *parent)
-{
-        int ret;
-        unsigned long flags;
-        unsigned long new_rate;
-        unsigned long old_rate;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (!c->ops || !c->ops->set_parent) {
-                ret = -ENOSYS;
-                goto out;
-        }
-
-        new_rate = clk_predict_rate_from_parent(c, parent);
-        old_rate = clk_get_rate_locked(c);
-
-        ret = c->ops->set_parent(c, parent);
-        if (ret)
-                goto out;
-
-out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *c)
-{
-        return c->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_rate_locked(struct clk *c, unsigned long rate)
-{
-        long new_rate;
-
-        if (!c->ops || !c->ops->set_rate)
-                return -ENOSYS;
-
-        if (rate > c->max_rate)
-                rate = c->max_rate;
-
-        if (c->ops && c->ops->round_rate) {
-                new_rate = c->ops->round_rate(c, rate);
-
-                if (new_rate < 0)
-                        return new_rate;
-
-                rate = new_rate;
-        }
-
-        return c->ops->set_rate(c, rate);
-}
-
-int clk_set_rate(struct clk *c, unsigned long rate)
-{
-        int ret;
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        ret = clk_set_rate_locked(c, rate);
-
-        spin_unlock_irqrestore(&c->spinlock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-
-/* Must be called with clocks lock and all indvidual clock locks held */
-unsigned long clk_get_rate_all_locked(struct clk *c)
+struct clk *tegra_get_clock_by_name(const char *name)
 {
-        u64 rate;
-        int mul = 1;
-        int div = 1;
-        struct clk *p = c;
-
-        while (p) {
-                c = p;
-                if (c->mul != 0 && c->div != 0) {
-                        mul *= c->mul;
-                        div *= c->div;
+        struct clk_tegra *c;
+        struct clk *ret = NULL;
+        mutex_lock(&clock_list_lock);
+        list_for_each_entry(c, &clocks, node) {
+                if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
+                        ret = c->hw.clk;
+                        break;
                 }
-                p = c->parent;
-        }
-
-        rate = c->rate;
-        rate *= mul;
-        do_div(rate, div);
-
-        return rate;
-}
-
-long clk_round_rate(struct clk *c, unsigned long rate)
-{
-        unsigned long flags;
-        long ret;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (!c->ops || !c->ops->round_rate) {
-                ret = -ENOSYS;
-                goto out;
         }
-
-        if (rate > c->max_rate)
-                rate = c->max_rate;
-
-        ret = c->ops->round_rate(c, rate);
-
-out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
+        mutex_unlock(&clock_list_lock);
         return ret;
 }
-EXPORT_SYMBOL(clk_round_rate);
 
 static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
 {
         struct clk *c;
         struct clk *p;
+        struct clk *parent;
 
         int ret = 0;
 
         c = tegra_get_clock_by_name(table->name);
 
         if (!c) {
-                pr_warning("Unable to initialize clock %s\n",
+                pr_warn("Unable to initialize clock %s\n",
                         table->name);
                 return -ENODEV;
         }
 
+        parent = clk_get_parent(c);
+
         if (table->parent) {
                 p = tegra_get_clock_by_name(table->parent);
                 if (!p) {
-                        pr_warning("Unable to find parent %s of clock %s\n",
+                        pr_warn("Unable to find parent %s of clock %s\n",
                                 table->parent, table->name);
                         return -ENODEV;
                 }
 
-                if (c->parent != p) {
+                if (parent != p) {
                         ret = clk_set_parent(c, p);
                         if (ret) {
-                                pr_warning("Unable to set parent %s of clock %s: %d\n",
+                                pr_warn("Unable to set parent %s of clock %s: %d\n",
                                         table->parent, table->name, ret);
                                 return -EINVAL;
                         }
@@ -360,16 +109,16 @@ static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
         if (table->rate && table->rate != clk_get_rate(c)) {
                 ret = clk_set_rate(c, table->rate);
                 if (ret) {
-                        pr_warning("Unable to set clock %s to rate %lu: %d\n",
+                        pr_warn("Unable to set clock %s to rate %lu: %d\n",
                                 table->name, table->rate, ret);
                         return -EINVAL;
                 }
         }
 
         if (table->enabled) {
-                ret = clk_enable(c);
+                ret = clk_prepare_enable(c);
                 if (ret) {
-                        pr_warning("Unable to enable clock %s: %d\n",
+                        pr_warn("Unable to enable clock %s: %d\n",
                                 table->name, ret);
                         return -EINVAL;
                 }
@@ -383,19 +132,20 @@ void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
         for (; table->name; table++)
                 tegra_clk_init_one_from_table(table);
 }
-EXPORT_SYMBOL(tegra_clk_init_from_table);
 
 void tegra_periph_reset_deassert(struct clk *c)
 {
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, false);
+        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
+        BUG_ON(!clk->reset);
+        clk->reset(__clk_get_hw(c), false);
 }
 EXPORT_SYMBOL(tegra_periph_reset_deassert);
 
 void tegra_periph_reset_assert(struct clk *c)
 {
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, true);
+        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
+        BUG_ON(!clk->reset);
+        clk->reset(__clk_get_hw(c), true);
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
 
@@ -405,268 +155,14 @@ EXPORT_SYMBOL(tegra_periph_reset_assert);
 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 {
         int ret = 0;
-        unsigned long flags;
+        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
 
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (!c->ops || !c->ops->clk_cfg_ex) {
+        if (!clk->clk_cfg_ex) {
                 ret = -ENOSYS;
                 goto out;
         }
-        ret = c->ops->clk_cfg_ex(c, p, setting);
+        ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
 
 out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
-
         return ret;
 }
-
-#ifdef CONFIG_DEBUG_FS
-
-static int __clk_lock_all_spinlocks(void)
-{
-        struct clk *c;
-
-        list_for_each_entry(c, &clocks, node)
-                if (!spin_trylock(&c->spinlock))
-                        goto unlock_spinlocks;
-
-        return 0;
-
-unlock_spinlocks:
-        list_for_each_entry_continue_reverse(c, &clocks, node)
-                spin_unlock(&c->spinlock);
-
-        return -EAGAIN;
-}
-
-static void __clk_unlock_all_spinlocks(void)
-{
-        struct clk *c;
-
-        list_for_each_entry_reverse(c, &clocks, node)
-                spin_unlock(&c->spinlock);
-}
-
-/*
- * This function retries until it can take all locks, and may take
- * an arbitrarily long time to complete.
- * Must be called with irqs enabled, returns with irqs disabled
- * Must be called with clock_list_lock held
- */
-static void clk_lock_all(void)
-{
-        int ret;
-retry:
-        local_irq_disable();
-
-        ret = __clk_lock_all_spinlocks();
-        if (ret)
-                goto failed_spinlocks;
-
-        /* All locks taken successfully, return */
-        return;
-
-failed_spinlocks:
-        local_irq_enable();
-        yield();
-        goto retry;
-}
-
-/*
- * Unlocks all clocks after a clk_lock_all
- * Must be called with irqs disabled, returns with irqs enabled
- * Must be called with clock_list_lock held
- */
-static void clk_unlock_all(void)
-{
-        __clk_unlock_all_spinlocks();
-
-        local_irq_enable();
-}
-
-static struct dentry *clk_debugfs_root;
-
-
-static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
-{
-        struct clk *child;
-        const char *state = "uninit";
-        char div[8] = {0};
-
-        if (c->state == ON)
-                state = "on";
-        else if (c->state == OFF)
-                state = "off";
-
-        if (c->mul != 0 && c->div != 0) {
-                if (c->mul > c->div) {
-                        int mul = c->mul / c->div;
-                        int mul2 = (c->mul * 10 / c->div) % 10;
-                        int mul3 = (c->mul * 10) % c->div;
-                        if (mul2 == 0 && mul3 == 0)
-                                snprintf(div, sizeof(div), "x%d", mul);
-                        else if (mul3 == 0)
-                                snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
-                        else
-                                snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
-                } else {
-                        snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
-                                (c->div % c->mul) ? ".5" : "");
-                }
-        }
-
-        seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
-                level * 3 + 1, "",
-                c->rate > c->max_rate ? '!' : ' ',
-                !c->set ? '*' : ' ',
-                30 - level * 3, c->name,
-                state, c->refcnt, div, clk_get_rate_all_locked(c));
-
-        list_for_each_entry(child, &clocks, node) {
-                if (child->parent != c)
-                        continue;
-
-                clock_tree_show_one(s, child, level + 1);
-        }
-}
-
-static int clock_tree_show(struct seq_file *s, void *data)
-{
-        struct clk *c;
-        seq_printf(s, "   clock                          state  ref div      rate\n");
-        seq_printf(s, "--------------------------------------------------------------\n");
-
-        mutex_lock(&clock_list_lock);
-
-        clk_lock_all();
-
-        list_for_each_entry(c, &clocks, node)
-                if (c->parent == NULL)
-                        clock_tree_show_one(s, c, 0);
-
-        clk_unlock_all();
-
-        mutex_unlock(&clock_list_lock);
-        return 0;
-}
-
-static int clock_tree_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, clock_tree_show, inode->i_private);
-}
-
-static const struct file_operations clock_tree_fops = {
-        .open           = clock_tree_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int possible_parents_show(struct seq_file *s, void *data)
-{
-        struct clk *c = s->private;
-        int i;
-
-        for (i = 0; c->inputs[i].input; i++) {
-                char *first = (i == 0) ? "" : " ";
-                seq_printf(s, "%s%s", first, c->inputs[i].input->name);
-        }
-        seq_printf(s, "\n");
-        return 0;
-}
-
-static int possible_parents_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, possible_parents_show, inode->i_private);
-}
-
-static const struct file_operations possible_parents_fops = {
-        .open           = possible_parents_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int clk_debugfs_register_one(struct clk *c)
-{
-        struct dentry *d;
-
-        d = debugfs_create_dir(c->name, clk_debugfs_root);
-        if (!d)
-                return -ENOMEM;
-        c->dent = d;
-
-        d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
-        if (!d)
-                goto err_out;
-
-        if (c->inputs) {
-                d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
-                        c, &possible_parents_fops);
-                if (!d)
-                        goto err_out;
-        }
-
-        return 0;
-
-err_out:
-        debugfs_remove_recursive(c->dent);
-        return -ENOMEM;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->parent;
-
-        if (pa && !pa->dent) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-
-        if (!c->dent) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-
-int __init tegra_clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err = -ENOMEM;
-
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-
-        d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
-                &clock_tree_fops);
-        if (!d)
-                goto err_out;
-
-        list_for_each_entry(c, &clocks, node) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-
-#endif
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index bc300657deba..2aa37f5c44c0 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/include/mach/clock.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@google.com>
@@ -20,9 +21,9 @@
 #ifndef __MACH_TEGRA_CLOCK_H
 #define __MACH_TEGRA_CLOCK_H
 
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/list.h>
-#include <linux/spinlock.h>
 
 #include <mach/clk.h>
 
@@ -52,7 +53,8 @@
 #define ENABLE_ON_INIT          (1 << 28)
 #define PERIPH_ON_APB           (1 << 29)
 
-struct clk;
+struct clk_tegra;
+#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
 
 struct clk_mux_sel {
         struct clk      *input;
@@ -68,47 +70,29 @@ struct clk_pll_freq_table {
         u8              cpcon;
 };
 
-struct clk_ops {
-        void            (*init)(struct clk *);
-        int             (*enable)(struct clk *);
-        void            (*disable)(struct clk *);
-        int             (*set_parent)(struct clk *, struct clk *);
-        int             (*set_rate)(struct clk *, unsigned long);
-        long            (*round_rate)(struct clk *, unsigned long);
-        void            (*reset)(struct clk *, bool);
-        int             (*clk_cfg_ex)(struct clk *,
-                                enum tegra_clk_ex_param, u32);
-};
-
 enum clk_state {
         UNINITIALIZED = 0,
         ON,
         OFF,
 };
 
-struct clk {
+struct clk_tegra {
         /* node for master clocks list */
-        struct list_head        node;           /* node for list of all clocks */
+        struct list_head        node;   /* node for list of all clocks */
         struct clk_lookup       lookup;
+        struct clk_hw           hw;
 
-#ifdef CONFIG_DEBUG_FS
-        struct dentry           *dent;
-#endif
         bool                    set;
-        struct clk_ops          *ops;
-        unsigned long           rate;
+        unsigned long           fixed_rate;
         unsigned long           max_rate;
         unsigned long           min_rate;
         u32                     flags;
         const char              *name;
 
-        u32                     refcnt;
         enum clk_state          state;
-        struct clk              *parent;
         u32                     div;
         u32                     mul;
 
-        const struct clk_mux_sel        *inputs;
         u32                             reg;
         u32                             reg_shift;
 
@@ -144,7 +128,8 @@ struct clk {
                 } shared_bus_user;
         } u;
 
-        spinlock_t spinlock;
+        void (*reset)(struct clk_hw *, bool);
+        int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
 };
 
 struct clk_duplicate {
@@ -159,13 +144,10 @@ struct tegra_clk_init_table {
         bool enabled;
 };
 
+void tegra_clk_add(struct clk *c);
 void tegra2_init_clocks(void);
 void tegra30_init_clocks(void);
-void clk_init(struct clk *clk);
 struct clk *tegra_get_clock_by_name(const char *name);
-int clk_reparent(struct clk *c, struct clk *parent);
 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
-unsigned long clk_get_rate_locked(struct clk *c);
-int clk_set_rate_locked(struct clk *c, unsigned long rate);
 
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 96fef6bcc651..0b0a5f556d34 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -31,9 +31,11 @@
 
 #include "board.h"
 #include "clock.h"
+#include "common.h"
 #include "fuse.h"
 #include "pmc.h"
 #include "apbio.h"
+#include "sleep.h"
 
 /*
  * Storage for debug-macro.S's state.
@@ -135,6 +137,7 @@ void __init tegra20_init_early(void)
         tegra_init_cache(0x331, 0x441);
         tegra_pmc_init();
         tegra_powergate_init();
+        tegra20_hotplug_init();
 }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -147,11 +150,11 @@ void __init tegra30_init_early(void)
         tegra_init_cache(0x441, 0x551);
         tegra_pmc_init();
         tegra_powergate_init();
+        tegra30_hotplug_init();
 }
 #endif
 
 void __init tegra_init_late(void)
 {
-        tegra_clk_debugfs_init();
         tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
new file mode 100644
index 000000000000..02f71b4f1e51
--- /dev/null
+++ b/arch/arm/mach-tegra/common.h
@@ -0,0 +1,4 @@
+extern struct smp_operations tegra_smp_ops;
+
+extern void tegra_cpu_die(unsigned int cpu);
+extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index ceb52db1e2f1..627bf0f4262e 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -49,6 +49,8 @@ static struct cpufreq_frequency_table freq_table[] = {
 #define NUM_CPUS        2
 
 static struct clk *cpu_clk;
+static struct clk *pll_x_clk;
+static struct clk *pll_p_clk;
 static struct clk *emc_clk;
 
 static unsigned long target_cpu_speed[NUM_CPUS];
@@ -71,6 +73,42 @@ static unsigned int tegra_getspeed(unsigned int cpu)
         return rate;
 }
 
+static int tegra_cpu_clk_set_rate(unsigned long rate)
+{
+        int ret;
+
+        /*
+         * Take an extra reference to the main pll so it doesn't turn
+         * off when we move the cpu off of it
+         */
+        clk_prepare_enable(pll_x_clk);
+
+        ret = clk_set_parent(cpu_clk, pll_p_clk);
+        if (ret) {
+                pr_err("Failed to switch cpu to clock pll_p\n");
+                goto out;
+        }
+
+        if (rate == clk_get_rate(pll_p_clk))
+                goto out;
+
+        ret = clk_set_rate(pll_x_clk, rate);
+        if (ret) {
+                pr_err("Failed to change pll_x to %lu\n", rate);
+                goto out;
+        }
+
+        ret = clk_set_parent(cpu_clk, pll_x_clk);
+        if (ret) {
+                pr_err("Failed to switch cpu to clock pll_x\n");
+                goto out;
+        }
+
+out:
+        clk_disable_unprepare(pll_x_clk);
+        return ret;
+}
+
 static int tegra_update_cpu_speed(unsigned long rate)
 {
         int ret = 0;
@@ -101,7 +139,7 @@ static int tegra_update_cpu_speed(unsigned long rate)
                freqs.old, freqs.new);
 #endif
 
-        ret = clk_set_rate(cpu_clk, freqs.new * 1000);
+        ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
         if (ret) {
                 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
                         freqs.new);
@@ -183,6 +221,14 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
         if (IS_ERR(cpu_clk))
                 return PTR_ERR(cpu_clk);
 
+        pll_x_clk = clk_get_sys(NULL, "pll_x");
+        if (IS_ERR(pll_x_clk))
+                return PTR_ERR(pll_x_clk);
+
+        pll_p_clk = clk_get_sys(NULL, "pll_p");
+        if (IS_ERR(pll_p_clk))
+                return PTR_ERR(pll_p_clk);
+
         emc_clk = clk_get_sys("cpu", "emc");
         if (IS_ERR(emc_clk)) {
                 clk_put(cpu_clk);
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index c70e65ffa36b..61e9603744a7 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -23,7 +23,6 @@
 #include <linux/fsl_devices.h>
 #include <linux/serial_8250.h>
 #include <linux/i2c-tegra.h>
-#include <asm/pmu.h>
 #include <mach/irqs.h>
 #include <mach/iomap.h>
 #include <mach/dma.h>
@@ -516,7 +515,7 @@ static struct resource tegra_pmu_resources[] = {
 
 struct platform_device tegra_pmu_device = {
         .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
         .resource       = tegra_pmu_resources,
 };
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
deleted file mode 100644
index 29c5114d607c..000000000000
--- a/arch/arm/mach-tegra/dma.c
+++ /dev/null
@@ -1,823 +0,0 @@
-/*
- * arch/arm/mach-tegra/dma.c
- *
- * System DMA driver for NVIDIA Tegra SoCs
- *
- * Copyright (c) 2008-2009, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/err.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
-#include "apbio.h"
-
-#define APB_DMA_GEN                             0x000
-#define GEN_ENABLE                              (1<<31)
-
-#define APB_DMA_CNTRL                           0x010
-
-#define APB_DMA_IRQ_MASK                        0x01c
-
-#define APB_DMA_IRQ_MASK_SET                    0x020
-
-#define APB_DMA_CHAN_CSR                        0x000
-#define CSR_ENB                                 (1<<31)
-#define CSR_IE_EOC                              (1<<30)
-#define CSR_HOLD                                (1<<29)
-#define CSR_DIR                                 (1<<28)
-#define CSR_ONCE                                (1<<27)
-#define CSR_FLOW                                (1<<21)
-#define CSR_REQ_SEL_SHIFT                       16
-#define CSR_WCOUNT_SHIFT                        2
-#define CSR_WCOUNT_MASK                         0xFFFC
-
-#define APB_DMA_CHAN_STA                                0x004
-#define STA_BUSY                                (1<<31)
-#define STA_ISE_EOC                             (1<<30)
-#define STA_HALT                                (1<<29)
-#define STA_PING_PONG                           (1<<28)
-#define STA_COUNT_SHIFT                         2
-#define STA_COUNT_MASK                          0xFFFC
-
-#define APB_DMA_CHAN_AHB_PTR                            0x010
-
-#define APB_DMA_CHAN_AHB_SEQ                            0x014
-#define AHB_SEQ_INTR_ENB                        (1<<31)
-#define AHB_SEQ_BUS_WIDTH_SHIFT                 28
-#define AHB_SEQ_BUS_WIDTH_MASK                  (0x7<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_8                     (0<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_16                    (1<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_32                    (2<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_64                    (3<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_128                   (4<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_DATA_SWAP                       (1<<27)
-#define AHB_SEQ_BURST_MASK                      (0x7<<24)
-#define AHB_SEQ_BURST_1                         (4<<24)
-#define AHB_SEQ_BURST_4                         (5<<24)
-#define AHB_SEQ_BURST_8                         (6<<24)
-#define AHB_SEQ_DBL_BUF                         (1<<19)
-#define AHB_SEQ_WRAP_SHIFT                      16
-#define AHB_SEQ_WRAP_MASK                       (0x7<<AHB_SEQ_WRAP_SHIFT)
-
-#define APB_DMA_CHAN_APB_PTR                            0x018
-
-#define APB_DMA_CHAN_APB_SEQ                            0x01c
-#define APB_SEQ_BUS_WIDTH_SHIFT                 28
-#define APB_SEQ_BUS_WIDTH_MASK                  (0x7<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_8                     (0<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_16                    (1<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_32                    (2<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_64                    (3<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_128                   (4<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_DATA_SWAP                       (1<<27)
-#define APB_SEQ_WRAP_SHIFT                      16
-#define APB_SEQ_WRAP_MASK                       (0x7<<APB_SEQ_WRAP_SHIFT)
-
-#define TEGRA_SYSTEM_DMA_CH_NR                  16
-#define TEGRA_SYSTEM_DMA_AVP_CH_NUM             4
-#define TEGRA_SYSTEM_DMA_CH_MIN                 0
-#define TEGRA_SYSTEM_DMA_CH_MAX \
-        (TEGRA_SYSTEM_DMA_CH_NR - TEGRA_SYSTEM_DMA_AVP_CH_NUM - 1)
-
-#define NV_DMA_MAX_TRASFER_SIZE 0x10000
-
-static const unsigned int ahb_addr_wrap_table[8] = {
-        0, 32, 64, 128, 256, 512, 1024, 2048
-};
-
-static const unsigned int apb_addr_wrap_table[8] = {
-        0, 1, 2, 4, 8, 16, 32, 64
-};
-
-static const unsigned int bus_width_table[5] = {
-        8, 16, 32, 64, 128
-};
-
-#define TEGRA_DMA_NAME_SIZE 16
-struct tegra_dma_channel {
-        struct list_head        list;
-        int                     id;
-        spinlock_t              lock;
-        char                    name[TEGRA_DMA_NAME_SIZE];
-        void  __iomem           *addr;
-        int                     mode;
-        int                     irq;
-        int                     req_transfer_count;
-};
-
-#define  NV_DMA_MAX_CHANNELS  32
-
-static bool tegra_dma_initialized;
-static DEFINE_MUTEX(tegra_dma_lock);
-static DEFINE_SPINLOCK(enable_lock);
-
-static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS);
-static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS];
-
-static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-static void tegra_dma_stop(struct tegra_dma_channel *ch);
-
-void tegra_dma_flush(struct tegra_dma_channel *ch)
-{
-}
-EXPORT_SYMBOL(tegra_dma_flush);
-
-void tegra_dma_dequeue(struct tegra_dma_channel *ch)
-{
-        struct tegra_dma_req *req;
-
-        if (tegra_dma_is_empty(ch))
-                return;
-
-        req = list_entry(ch->list.next, typeof(*req), node);
-
-        tegra_dma_dequeue_req(ch, req);
-        return;
-}
-
-static void tegra_dma_stop(struct tegra_dma_channel *ch)
-{
-        u32 csr;
-        u32 status;
-
-        csr = readl(ch->addr + APB_DMA_CHAN_CSR);
-        csr &= ~CSR_IE_EOC;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-        csr &= ~CSR_ENB;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-        status = readl(ch->addr + APB_DMA_CHAN_STA);
-        if (status & STA_ISE_EOC)
-                writel(status, ch->addr + APB_DMA_CHAN_STA);
-}
-
-static int tegra_dma_cancel(struct tegra_dma_channel *ch)
-{
-        unsigned long irq_flags;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        while (!list_empty(&ch->list))
-                list_del(ch->list.next);
-
-        tegra_dma_stop(ch);
-
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return 0;
-}
-
-static unsigned int get_channel_status(struct tegra_dma_channel *ch,
-                        struct tegra_dma_req *req, bool is_stop_dma)
-{
-        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        unsigned int status;
-
-        if (is_stop_dma) {
-                /*
-                 * STOP the DMA and get the transfer count.
-                 * Getting the transfer count is tricky.
-                 *  - Globally disable DMA on all channels
-                 *  - Read the channel's status register to know the number
-                 *    of pending bytes to be transfered.
-                 *  - Stop the dma channel
-                 *  - Globally re-enable DMA to resume other transfers
-                 */
-                spin_lock(&enable_lock);
-                writel(0, addr + APB_DMA_GEN);
-                udelay(20);
-                status = readl(ch->addr + APB_DMA_CHAN_STA);
-                tegra_dma_stop(ch);
-                writel(GEN_ENABLE, addr + APB_DMA_GEN);
-                spin_unlock(&enable_lock);
-                if (status & STA_ISE_EOC) {
-                        pr_err("Got Dma Int here clearing");
-                        writel(status, ch->addr + APB_DMA_CHAN_STA);
-                }
-                req->status = TEGRA_DMA_REQ_ERROR_ABORTED;
-        } else {
-                status = readl(ch->addr + APB_DMA_CHAN_STA);
-        }
-        return status;
-}
-
-/* should be called with the channel lock held */
-static unsigned int dma_active_count(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req, unsigned int status)
-{
-        unsigned int to_transfer;
-        unsigned int req_transfer_count;
-        unsigned int bytes_transferred;
-
-        to_transfer = ((status & STA_COUNT_MASK) >> STA_COUNT_SHIFT) + 1;
-        req_transfer_count = ch->req_transfer_count + 1;
-        bytes_transferred = req_transfer_count;
-        if (status & STA_BUSY)
-                bytes_transferred -= to_transfer;
-        /*
-         * In continuous transfer mode, DMA only tracks the count of the
-         * half DMA buffer. So, if the DMA already finished half the DMA
-         * then add the half buffer to the completed count.
-         */
-        if (ch->mode & TEGRA_DMA_MODE_CONTINOUS) {
-                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
-                        bytes_transferred += req_transfer_count;
-                if (status & STA_ISE_EOC)
-                        bytes_transferred += req_transfer_count;
-        }
-        bytes_transferred *= 4;
-        return bytes_transferred;
-}
-
-int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *_req)
-{
-        unsigned int status;
-        struct tegra_dma_req *req = NULL;
-        int found = 0;
-        unsigned long irq_flags;
-        int stop = 0;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-
-        if (list_entry(ch->list.next, struct tegra_dma_req, node) == _req)
-                stop = 1;
-
-        list_for_each_entry(req, &ch->list, node) {
-                if (req == _req) {
-                        list_del(&req->node);
-                        found = 1;
-                        break;
-                }
-        }
-        if (!found) {
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                return 0;
-        }
-
-        if (!stop)
-                goto skip_stop_dma;
-
-        status = get_channel_status(ch, req, true);
-        req->bytes_transferred = dma_active_count(ch, req, status);
-
-        if (!list_empty(&ch->list)) {
-                /* if the list is not empty, queue the next request */
-                struct tegra_dma_req *next_req;
-                next_req = list_entry(ch->list.next,
-                        typeof(*next_req), node);
-                tegra_dma_update_hw(ch, next_req);
-        }
-
-skip_stop_dma:
-        req->status = -TEGRA_DMA_REQ_ERROR_ABORTED;
-
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-
-        /* Callback should be called without any lock */
-        req->complete(req);
-        return 0;
-}
-EXPORT_SYMBOL(tegra_dma_dequeue_req);
-
-bool tegra_dma_is_empty(struct tegra_dma_channel *ch)
-{
-        unsigned long irq_flags;
-        bool is_empty;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_empty(&ch->list))
-                is_empty = true;
-        else
-                is_empty = false;
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return is_empty;
-}
-EXPORT_SYMBOL(tegra_dma_is_empty);
-
-bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *_req)
-{
-        unsigned long irq_flags;
-        struct tegra_dma_req *req;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        list_for_each_entry(req, &ch->list, node) {
-                if (req == _req) {
-                        spin_unlock_irqrestore(&ch->lock, irq_flags);
-                        return true;
-                }
-        }
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return false;
-}
-EXPORT_SYMBOL(tegra_dma_is_req_inflight);
-
-int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req)
-{
-        unsigned long irq_flags;
-        struct tegra_dma_req *_req;
-        int start_dma = 0;
-
-        if (req->size > NV_DMA_MAX_TRASFER_SIZE ||
-                req->source_addr & 0x3 || req->dest_addr & 0x3) {
-                pr_err("Invalid DMA request for channel %d\n", ch->id);
-                return -EINVAL;
-        }
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-
-        list_for_each_entry(_req, &ch->list, node) {
-                if (req == _req) {
-                    spin_unlock_irqrestore(&ch->lock, irq_flags);
-                    return -EEXIST;
-                }
-        }
-
-        req->bytes_transferred = 0;
-        req->status = 0;
-        req->buffer_status = 0;
-        if (list_empty(&ch->list))
-                start_dma = 1;
-
-        list_add_tail(&req->node, &ch->list);
-
-        if (start_dma)
-                tegra_dma_update_hw(ch, req);
-
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(tegra_dma_enqueue_req);
-
-struct tegra_dma_channel *tegra_dma_allocate_channel(int mode)
-{
-        int channel;
-        struct tegra_dma_channel *ch = NULL;
-
-        if (!tegra_dma_initialized)
-                return NULL;
-
-        mutex_lock(&tegra_dma_lock);
-
-        /* first channel is the shared channel */
-        if (mode & TEGRA_DMA_SHARED) {
-                channel = TEGRA_SYSTEM_DMA_CH_MIN;
-        } else {
-                channel = find_first_zero_bit(channel_usage,
-                        ARRAY_SIZE(dma_channels));
-                if (channel >= ARRAY_SIZE(dma_channels))
-                        goto out;
-        }
-        __set_bit(channel, channel_usage);
-        ch = &dma_channels[channel];
-        ch->mode = mode;
-
-out:
-        mutex_unlock(&tegra_dma_lock);
-        return ch;
-}
-EXPORT_SYMBOL(tegra_dma_allocate_channel);
-
-void tegra_dma_free_channel(struct tegra_dma_channel *ch)
-{
-        if (ch->mode & TEGRA_DMA_SHARED)
-                return;
-        tegra_dma_cancel(ch);
-        mutex_lock(&tegra_dma_lock);
-        __clear_bit(ch->id, channel_usage);
-        mutex_unlock(&tegra_dma_lock);
-}
-EXPORT_SYMBOL(tegra_dma_free_channel);
-
-static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req)
-{
-        u32 apb_ptr;
-        u32 ahb_ptr;
-
-        if (req->to_memory) {
-                apb_ptr = req->source_addr;
-                ahb_ptr = req->dest_addr;
-        } else {
-                apb_ptr = req->dest_addr;
-                ahb_ptr = req->source_addr;
-        }
-        writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
-        writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
-
-        req->status = TEGRA_DMA_REQ_INFLIGHT;
-        return;
-}
-
-static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req)
-{
-        int ahb_addr_wrap;
-        int apb_addr_wrap;
-        int ahb_bus_width;
-        int apb_bus_width;
-        int index;
-
-        u32 ahb_seq;
-        u32 apb_seq;
-        u32 ahb_ptr;
-        u32 apb_ptr;
-        u32 csr;
-
-        csr = CSR_IE_EOC | CSR_FLOW;
-        ahb_seq = AHB_SEQ_INTR_ENB | AHB_SEQ_BURST_1;
-        apb_seq = 0;
-
-        csr |= req->req_sel << CSR_REQ_SEL_SHIFT;
-
-        /* One shot mode is always single buffered,
-         * continuous mode is always double buffered
-         * */
-        if (ch->mode & TEGRA_DMA_MODE_ONESHOT) {
-                csr |= CSR_ONCE;
-                ch->req_transfer_count = (req->size >> 2) - 1;
-        } else {
-                ahb_seq |= AHB_SEQ_DBL_BUF;
-
-                /* In double buffered mode, we set the size to half the
-                 * requested size and interrupt when half the buffer
-                 * is full */
-                ch->req_transfer_count = (req->size >> 3) - 1;
-        }
-
-        csr |= ch->req_transfer_count << CSR_WCOUNT_SHIFT;
-
-        if (req->to_memory) {
-                apb_ptr = req->source_addr;
-                ahb_ptr = req->dest_addr;
-
-                apb_addr_wrap = req->source_wrap;
-                ahb_addr_wrap = req->dest_wrap;
-                apb_bus_width = req->source_bus_width;
-                ahb_bus_width = req->dest_bus_width;
-
-        } else {
-                csr |= CSR_DIR;
-                apb_ptr = req->dest_addr;
-                ahb_ptr = req->source_addr;
-
-                apb_addr_wrap = req->dest_wrap;
-                ahb_addr_wrap = req->source_wrap;
-                apb_bus_width = req->dest_bus_width;
-                ahb_bus_width = req->source_bus_width;
-        }
-
-        apb_addr_wrap >>= 2;
-        ahb_addr_wrap >>= 2;
-
-        /* set address wrap for APB size */
-        index = 0;
-        do  {
-                if (apb_addr_wrap_table[index] == apb_addr_wrap)
-                        break;
-                index++;
-        } while (index < ARRAY_SIZE(apb_addr_wrap_table));
-        BUG_ON(index == ARRAY_SIZE(apb_addr_wrap_table));
-        apb_seq |= index << APB_SEQ_WRAP_SHIFT;
-
-        /* set address wrap for AHB size */
-        index = 0;
-        do  {
-                if (ahb_addr_wrap_table[index] == ahb_addr_wrap)
-                        break;
-                index++;
-        } while (index < ARRAY_SIZE(ahb_addr_wrap_table));
-        BUG_ON(index == ARRAY_SIZE(ahb_addr_wrap_table));
-        ahb_seq |= index << AHB_SEQ_WRAP_SHIFT;
-
-        for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
-                if (bus_width_table[index] == ahb_bus_width)
-                        break;
-        }
-        BUG_ON(index == ARRAY_SIZE(bus_width_table));
-        ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT;
-
-        for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
-                if (bus_width_table[index] == apb_bus_width)
-                        break;
-        }
-        BUG_ON(index == ARRAY_SIZE(bus_width_table));
-        apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT;
-
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-        writel(apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ);
-        writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
-        writel(ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ);
-        writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
-
-        csr |= CSR_ENB;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-        req->status = TEGRA_DMA_REQ_INFLIGHT;
-}
-
-static void handle_oneshot_dma(struct tegra_dma_channel *ch)
-{
-        struct tegra_dma_req *req;
-        unsigned long irq_flags;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_empty(&ch->list)) {
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                return;
-        }
-
-        req = list_entry(ch->list.next, typeof(*req), node);
-        if (req) {
-                int bytes_transferred;
-
-                bytes_transferred = ch->req_transfer_count;
-                bytes_transferred += 1;
-                bytes_transferred <<= 2;
-
-                list_del(&req->node);
-                req->bytes_transferred = bytes_transferred;
-                req->status = TEGRA_DMA_REQ_SUCCESS;
-
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                /* Callback should be called without any lock */
-                pr_debug("%s: transferred %d bytes\n", __func__,
-                        req->bytes_transferred);
-                req->complete(req);
-                spin_lock_irqsave(&ch->lock, irq_flags);
-        }
-
-        if (!list_empty(&ch->list)) {
-                req = list_entry(ch->list.next, typeof(*req), node);
-                /* the complete function we just called may have enqueued
-                   another req, in which case dma has already started */
-                if (req->status != TEGRA_DMA_REQ_INFLIGHT)
-                        tegra_dma_update_hw(ch, req);
-        }
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-}
-
-static void handle_continuous_dma(struct tegra_dma_channel *ch)
-{
-        struct tegra_dma_req *req;
-        unsigned long irq_flags;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_empty(&ch->list)) {
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                return;
-        }
-
-        req = list_entry(ch->list.next, typeof(*req), node);
-        if (req) {
-                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_EMPTY) {
-                        bool is_dma_ping_complete;
-                        is_dma_ping_complete = (readl(ch->addr + APB_DMA_CHAN_STA)
-                                                & STA_PING_PONG) ? true : false;
-                        if (req->to_memory)
-                                is_dma_ping_complete = !is_dma_ping_complete;
-                        /* Out of sync - Release current buffer */
-                        if (!is_dma_ping_complete) {
-                                int bytes_transferred;
-
-                                bytes_transferred = ch->req_transfer_count;
-                                bytes_transferred += 1;
-                                bytes_transferred <<= 3;
-                                req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
-                                req->bytes_transferred = bytes_transferred;
-                                req->status = TEGRA_DMA_REQ_SUCCESS;
-                                tegra_dma_stop(ch);
-
-                                if (!list_is_last(&req->node, &ch->list)) {
-                                        struct tegra_dma_req *next_req;
-
-                                        next_req = list_entry(req->node.next,
-                                                typeof(*next_req), node);
-                                        tegra_dma_update_hw(ch, next_req);
-                                }
-
-                                list_del(&req->node);
-
-                                /* DMA lock is NOT held when callbak is called */
-                                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                                req->complete(req);
-                                return;
-                        }
-                        /* Load the next request into the hardware, if available
-                         * */
-                        if (!list_is_last(&req->node, &ch->list)) {
-                                struct tegra_dma_req *next_req;
-
-                                next_req = list_entry(req->node.next,
-                                        typeof(*next_req), node);
-                                tegra_dma_update_hw_partial(ch, next_req);
-                        }
-                        req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL;
-                        req->status = TEGRA_DMA_REQ_SUCCESS;
-                        /* DMA lock is NOT held when callback is called */
-                        spin_unlock_irqrestore(&ch->lock, irq_flags);
-                        if (likely(req->threshold))
-                                req->threshold(req);
-                        return;
-
-                } else if (req->buffer_status ==
-                        TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL) {
-                        /* Callback when the buffer is completely full (i.e on
-                         * the second  interrupt */
-                        int bytes_transferred;
-
-                        bytes_transferred = ch->req_transfer_count;
-                        bytes_transferred += 1;
-                        bytes_transferred <<= 3;
-
-                        req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
-                        req->bytes_transferred = bytes_transferred;
-                        req->status = TEGRA_DMA_REQ_SUCCESS;
-                        list_del(&req->node);
-
-                        /* DMA lock is NOT held when callbak is called */
-                        spin_unlock_irqrestore(&ch->lock, irq_flags);
-                        req->complete(req);
-                        return;
-
-                } else {
-                        BUG();
-                }
-        }
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-}
-
-static irqreturn_t dma_isr(int irq, void *data)
-{
-        struct tegra_dma_channel *ch = data;
-        unsigned long status;
-
-        status = readl(ch->addr + APB_DMA_CHAN_STA);
-        if (status & STA_ISE_EOC)
-                writel(status, ch->addr + APB_DMA_CHAN_STA);
-        else {
-                pr_warning("Got a spurious ISR for DMA channel %d\n", ch->id);
-                return IRQ_HANDLED;
-        }
-        return IRQ_WAKE_THREAD;
-}
-
-static irqreturn_t dma_thread_fn(int irq, void *data)
-{
-        struct tegra_dma_channel *ch = data;
-
-        if (ch->mode & TEGRA_DMA_MODE_ONESHOT)
-                handle_oneshot_dma(ch);
-        else
-                handle_continuous_dma(ch);
-
-
-        return IRQ_HANDLED;
-}
-
-int __init tegra_dma_init(void)
-{
-        int ret = 0;
-        int i;
-        unsigned int irq;
-        void __iomem *addr;
-        struct clk *c;
-
-        bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS);
-
-        c = clk_get_sys("tegra-apbdma", NULL);
-        if (IS_ERR(c)) {
-                pr_err("Unable to get clock for APB DMA\n");
-                ret = PTR_ERR(c);
-                goto fail;
-        }
-        ret = clk_prepare_enable(c);
-        if (ret != 0) {
-                pr_err("Unable to enable clock for APB DMA\n");
-                goto fail;
-        }
-
-        addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        writel(GEN_ENABLE, addr + APB_DMA_GEN);
-        writel(0, addr + APB_DMA_CNTRL);
-        writel(0xFFFFFFFFul >> (31 - TEGRA_SYSTEM_DMA_CH_MAX),
-               addr + APB_DMA_IRQ_MASK_SET);
-
-        for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
-                struct tegra_dma_channel *ch = &dma_channels[i];
-
-                ch->id = i;
-                snprintf(ch->name, TEGRA_DMA_NAME_SIZE, "dma_channel_%d", i);
-
-                ch->addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                        TEGRA_APB_DMA_CH0_SIZE * i);
-
-                spin_lock_init(&ch->lock);
-                INIT_LIST_HEAD(&ch->list);
-
-                irq = INT_APB_DMA_CH0 + i;
-                ret = request_threaded_irq(irq, dma_isr, dma_thread_fn, 0,
-                        dma_channels[i].name, ch);
-                if (ret) {
-                        pr_err("Failed to register IRQ %d for DMA %d\n",
-                                irq, i);
-                        goto fail;
-                }
-                ch->irq = irq;
-
-                __clear_bit(i, channel_usage);
-        }
-        /* mark the shared channel allocated */
-        __set_bit(TEGRA_SYSTEM_DMA_CH_MIN, channel_usage);
-
-        tegra_dma_initialized = true;
-
-        return 0;
-fail:
-        writel(0, addr + APB_DMA_GEN);
-        for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
-                struct tegra_dma_channel *ch = &dma_channels[i];
-                if (ch->irq)
-                        free_irq(ch->irq, ch);
-        }
-        return ret;
-}
-postcore_initcall(tegra_dma_init);
-
-#ifdef CONFIG_PM
-static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3];
-
-void tegra_dma_suspend(void)
-{
-        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        u32 *ctx = apb_dma;
-        int i;
-
-        *ctx++ = readl(addr + APB_DMA_GEN);
-        *ctx++ = readl(addr + APB_DMA_CNTRL);
-        *ctx++ = readl(addr + APB_DMA_IRQ_MASK);
-
-        for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
-                addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                                  TEGRA_APB_DMA_CH0_SIZE * i);
-
-                *ctx++ = readl(addr + APB_DMA_CHAN_CSR);
-                *ctx++ = readl(addr + APB_DMA_CHAN_AHB_PTR);
-                *ctx++ = readl(addr + APB_DMA_CHAN_AHB_SEQ);
-                *ctx++ = readl(addr + APB_DMA_CHAN_APB_PTR);
-                *ctx++ = readl(addr + APB_DMA_CHAN_APB_SEQ);
-        }
-}
-
-void tegra_dma_resume(void)
-{
-        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        u32 *ctx = apb_dma;
-        int i;
-
-        writel(*ctx++, addr + APB_DMA_GEN);
-        writel(*ctx++, addr + APB_DMA_CNTRL);
-        writel(*ctx++, addr + APB_DMA_IRQ_MASK);
-
-        for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
-                addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                                  TEGRA_APB_DMA_CH0_SIZE * i);
-
-                writel(*ctx++, addr + APB_DMA_CHAN_CSR);
-                writel(*ctx++, addr + APB_DMA_CHAN_AHB_PTR);
-                writel(*ctx++, addr + APB_DMA_CHAN_AHB_SEQ);
-                writel(*ctx++, addr + APB_DMA_CHAN_APB_PTR);
-                writel(*ctx++, addr + APB_DMA_CHAN_APB_SEQ);
-        }
-}
-
-#endif
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f946d129423c..0b7db174a5de 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -93,9 +93,9 @@ void tegra_init_fuse(void)
 {
         u32 id;
 
-        u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+        u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
         reg |= 1 << 28;
-        writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+        writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 
         reg = tegra_fuse_readl(FUSE_SKU_INFO);
         tegra_sku_id = reg & 0xFF;
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fef9c2c51370..6addc78cb6b2 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,17 +7,13 @@
 
 #include "flowctrl.h"
 #include "reset.h"
+#include "sleep.h"
 
 #define APB_MISC_GP_HIDREV      0x804
 #define PMC_SCRATCH41   0x140
 
 #define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
 
-        .macro mov32, reg, val
-        movw    \reg, #:lower16:\val
-        movt    \reg, #:upper16:\val
-        .endm
-
         .section ".text.head", "ax"
         __CPUINIT
 
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d8dc9ddd6d18..dca5141a2c31 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,123 +1,48 @@
 /*
- *  linux/arch/arm/mach-realview/hotplug.c
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
+ *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
-#include <linux/errno.h>
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/cp15.h>
+#include <asm/smp_plat.h>
 
-static inline void cpu_enter_lowpower(void)
-{
-        unsigned int v;
-
-        flush_cache_all();
-        asm volatile(
-        "       mcr     p15, 0, %1, c7, c5, 0\n"
-        "       mcr     p15, 0, %1, c7, c10, 4\n"
-        /*
-         * Turn off coherency
-         */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, #0x20\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "r" (0), "Ir" (CR_C)
-          : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-        unsigned int v;
+#include "sleep.h"
+#include "tegra_cpu_car.h"
 
-        asm volatile(
-        "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       orr     %0, %0, #0x20\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-          : "=&r" (v)
-          : "Ir" (CR_C)
-          : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-        /*
-         * there is no power-control hardware on this platform, so all
-         * we can do is put the core into WFI; this is safe as the calling
-         * code will have already disabled interrupts
-         */
-        for (;;) {
-                /*
-                 * here's the WFI
-                 */
-                asm(".word      0xe320f003\n"
-                    :
-                    :
-                    : "memory", "cc");
-
-                /*if (pen_release == cpu) {*/
-                        /*
-                         * OK, proper wakeup, we're done
-                         */
-                        break;
-                /*}*/
-
-                /*
-                 * Getting here, means that we have come out of WFI without
-                 * having been woken up - this shouldn't happen
-                 *
-                 * Just note it happening - when we're woken, we can report
-                 * its occurrence.
-                 */
-                (*spurious)++;
-        }
-}
-
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
+static void (*tegra_hotplug_shutdown)(void);
 
 /*
  * platform-specific code to shutdown a CPU
  *
  * Called with IRQs disabled
  */
-void platform_cpu_die(unsigned int cpu)
+void __ref tegra_cpu_die(unsigned int cpu)
 {
-        int spurious = 0;
+        cpu = cpu_logical_map(cpu);
 
-        /*
-         * we're ready for shutdown now, so do it
-         */
-        cpu_enter_lowpower();
-        platform_do_lowpower(cpu, &spurious);
+        /* Flush the L1 data cache. */
+        flush_cache_all();
 
-        /*
-         * bring this CPU back into the world of cache
-         * coherency, and then restore interrupts
-         */
-        cpu_leave_lowpower();
+        /* Shut down the current CPU. */
+        tegra_hotplug_shutdown();
 
-        if (spurious)
-                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+        /* Clock gate the CPU */
+        tegra_wait_cpu_in_reset(cpu);
+        tegra_disable_cpu_clock(cpu);
+
+        /* Should never return here. */
+        BUG();
 }
 
-int platform_cpu_disable(unsigned int cpu)
+int tegra_cpu_disable(unsigned int cpu)
 {
         /*
          * we don't allow CPU 0 to be shutdown (it is still too special
@@ -125,3 +50,19 @@ int platform_cpu_disable(unsigned int cpu)
          */
         return cpu == 0 ? -EPERM : 0;
 }
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+extern void tegra20_hotplug_shutdown(void);
+void __init tegra20_hotplug_init(void)
+{
+        tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+}
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+extern void tegra30_hotplug_shutdown(void);
+void __init tegra30_hotplug_init(void)
+{
+        tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+}
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index d97e403303a0..95f3a547c770 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -34,7 +34,10 @@ enum tegra_clk_ex_param {
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
+#ifndef CONFIG_COMMON_CLK
 unsigned long clk_get_rate_all_locked(struct clk *c);
+#endif
+
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
 
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 9077092812c0..3081cc6dda3b 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -51,101 +51,4 @@
 #define TEGRA_DMA_REQ_SEL_OWR                   25
 #define TEGRA_DMA_REQ_SEL_INVALID               31
 
-struct tegra_dma_req;
-struct tegra_dma_channel;
-
-enum tegra_dma_mode {
-        TEGRA_DMA_SHARED = 1,
-        TEGRA_DMA_MODE_CONTINOUS = 2,
-        TEGRA_DMA_MODE_ONESHOT = 4,
-};
-
-enum tegra_dma_req_error {
-        TEGRA_DMA_REQ_SUCCESS = 0,
-        TEGRA_DMA_REQ_ERROR_ABORTED,
-        TEGRA_DMA_REQ_INFLIGHT,
-};
-
-enum tegra_dma_req_buff_status {
-        TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0,
-        TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL,
-        TEGRA_DMA_REQ_BUF_STATUS_FULL,
-};
-
-struct tegra_dma_req {
-        struct list_head node;
-        unsigned int modid;
-        int instance;
-
-        /* Called when the req is complete and from the DMA ISR context.
-         * When this is called the req structure is no longer queued by
-         * the DMA channel.
-         *
-         * State of the DMA depends on the number of req it has. If there are
-         * no DMA requests queued up, then it will STOP the DMA. It there are
-         * more requests in the DMA, then it will queue the next request.
-         */
-        void (*complete)(struct tegra_dma_req *req);
-
-        /*  This is a called from the DMA ISR context when the DMA is still in
-         *  progress and is actively filling same buffer.
-         *
-         *  In case of continuous mode receive, this threshold is 1/2 the buffer
-         *  size. In other cases, this will not even be called as there is no
-         *  hardware support for it.
-         *
-         * In the case of continuous mode receive, if there is next req already
-         * queued, DMA programs the HW to use that req when this req is
-         * completed. If there is no "next req" queued, then DMA ISR doesn't do
-         * anything before calling this callback.
-         *
-         *      This is mainly used by the cases, where the clients has queued
-         *      only one req and want to get some sort of DMA threshold
-         *      callback to program the next buffer.
-         *
-         */
-        void (*threshold)(struct tegra_dma_req *req);
-
-        /* 1 to copy to memory.
-         * 0 to copy from the memory to device FIFO */
-        int to_memory;
-
-        void *virt_addr;
-
-        unsigned long source_addr;
-        unsigned long dest_addr;
-        unsigned long dest_wrap;
-        unsigned long source_wrap;
-        unsigned long source_bus_width;
-        unsigned long dest_bus_width;
-        unsigned long req_sel;
-        unsigned int size;
-
-        /* Updated by the DMA driver on the conpletion of the request. */
-        int bytes_transferred;
-        int status;
-
-        /* DMA completion tracking information */
-        int buffer_status;
-
-        /* Client specific data */
-        void *dev;
-};
-
-int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-void tegra_dma_dequeue(struct tegra_dma_channel *ch);
-void tegra_dma_flush(struct tegra_dma_channel *ch);
-
-bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
-
-struct tegra_dma_channel *tegra_dma_allocate_channel(int mode);
-void tegra_dma_free_channel(struct tegra_dma_channel *ch);
-
-int __init tegra_dma_init(void);
-
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-tegra/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
deleted file mode 100644
index fe700f9ce7dc..000000000000
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/io.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_IO_H
-#define __MACH_TEGRA_IO_H
-
-#define IO_SPACE_LIMIT 0xffff
-
-#ifndef __ASSEMBLER__
-
-#ifdef CONFIG_TEGRA_PCI
-extern void __iomem *tegra_pcie_io_base;
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
-}
-#else
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-#endif
-
-#define __io(a)         __io(a)
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 7e76da73121c..fee3a94c4549 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -303,6 +303,9 @@
 #define IO_APB_VIRT     IOMEM(0xFE300000)
 #define IO_APB_SIZE     SZ_1M
 
+#define TEGRA_PCIE_BASE         0x80000000
+#define TEGRA_PCIE_IO_BASE      (TEGRA_PCIE_BASE + SZ_4M)
+
 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
 #define IO_TO_VIRT_XLATE(p, pst, vst)   (((p) - (pst) + (vst)))
 
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index d3ad5150d660..3463fb5b79c7 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -171,8 +171,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
  * 0x90000000 - 0x9fffffff - non-prefetchable memory
  * 0xa0000000 - 0xbfffffff - prefetchable memory
  */
-#define TEGRA_PCIE_BASE         0x80000000
-
 #define PCIE_REGS_SZ            SZ_16K
 #define PCIE_CFG_OFF            PCIE_REGS_SZ
 #define PCIE_CFG_SZ             SZ_1M
@@ -180,8 +178,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 #define PCIE_EXT_CFG_SZ         SZ_1M
 #define PCIE_IOMAP_SZ           (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
 
-#define MMIO_BASE               (TEGRA_PCIE_BASE + SZ_4M)
-#define MMIO_SIZE               SZ_64K
 #define MEM_BASE_0              (TEGRA_PCIE_BASE + SZ_256M)
 #define MEM_SIZE_0              SZ_128M
 #define MEM_BASE_1              (MEM_BASE_0 + MEM_SIZE_0)
@@ -204,10 +200,9 @@ struct tegra_pcie_port {
 
         bool                    link_up;
 
-        char                    io_space_name[16];
         char                    mem_space_name[16];
         char                    prefetch_space_name[20];
-        struct resource         res[3];
+        struct resource         res[2];
 };
 
 struct tegra_pcie_info {
@@ -223,17 +218,7 @@ struct tegra_pcie_info {
         struct clk              *pll_e;
 };
 
-static struct tegra_pcie_info tegra_pcie = {
-        .res_mmio = {
-                .name = "PCI IO",
-                .start = MMIO_BASE,
-                .end = MMIO_BASE + MMIO_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-void __iomem *tegra_pcie_io_base;
-EXPORT_SYMBOL(tegra_pcie_io_base);
+static struct tegra_pcie_info tegra_pcie;
 
 static inline void afi_writel(u32 value, unsigned long offset)
 {
@@ -391,24 +376,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp = tegra_pcie.port + nr;
         pp->root_bus_nr = sys->busnr;
 
-        /*
-         * IORESOURCE_IO
-         */
-        snprintf(pp->io_space_name, sizeof(pp->io_space_name),
-                 "PCIe %d I/O", pp->index);
-        pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
-        pp->res[0].name = pp->io_space_name;
-        if (pp->index == 0) {
-                pp->res[0].start = PCIBIOS_MIN_IO;
-                pp->res[0].end = pp->res[0].start + SZ_32K - 1;
-        } else {
-                pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
-                pp->res[0].end = IO_SPACE_LIMIT;
-        }
-        pp->res[0].flags = IORESOURCE_IO;
-        if (request_resource(&ioport_resource, &pp->res[0]))
-                panic("Request PCIe IO resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+        pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
 
         /*
          * IORESOURCE_MEM
@@ -416,18 +384,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                  "PCIe %d MEM", pp->index);
         pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-        pp->res[1].name = pp->mem_space_name;
+        pp->res[0].name = pp->mem_space_name;
         if (pp->index == 0) {
-                pp->res[1].start = MEM_BASE_0;
-                pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1;
+                pp->res[0].start = MEM_BASE_0;
+                pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
         } else {
-                pp->res[1].start = MEM_BASE_1;
-                pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1;
+                pp->res[0].start = MEM_BASE_1;
+                pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
         }
-        pp->res[1].flags = IORESOURCE_MEM;
-        if (request_resource(&iomem_resource, &pp->res[1]))
+        pp->res[0].flags = IORESOURCE_MEM;
+        if (request_resource(&iomem_resource, &pp->res[0]))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
 
         /*
          * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -435,18 +403,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
                  "PCIe %d PREFETCH MEM", pp->index);
         pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
-        pp->res[2].name = pp->prefetch_space_name;
+        pp->res[1].name = pp->prefetch_space_name;
         if (pp->index == 0) {
-                pp->res[2].start = PREFETCH_MEM_BASE_0;
-                pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1;
+                pp->res[1].start = PREFETCH_MEM_BASE_0;
+                pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
         } else {
-                pp->res[2].start = PREFETCH_MEM_BASE_1;
-                pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1;
+                pp->res[1].start = PREFETCH_MEM_BASE_1;
+                pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
         }
-        pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-        if (request_resource(&iomem_resource, &pp->res[2]))
+        pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+        if (request_resource(&iomem_resource, &pp->res[1]))
                 panic("Request PCIe Prefetch Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         return 1;
 }
@@ -541,8 +509,8 @@ static void tegra_pcie_setup_translations(void)
 
         /* Bar 2: downstream IO bar */
         fpci_bar = ((__u32)0xfdfc << 16);
-        size = MMIO_SIZE;
-        axi_address = MMIO_BASE;
+        size = SZ_128K;
+        axi_address = TEGRA_PCIE_IO_BASE;
         afi_writel(axi_address, AFI_AXI_BAR2_START);
         afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
         afi_writel(fpci_bar, AFI_FPCI_BAR2);
@@ -776,7 +744,6 @@ static void tegra_pcie_clocks_put(void)
 
 static int __init tegra_pcie_get_resources(void)
 {
-        struct resource *res_mmio = &tegra_pcie.res_mmio;
         int err;
 
         err = tegra_pcie_clocks_get();
@@ -798,34 +765,16 @@ static int __init tegra_pcie_get_resources(void)
                 goto err_map_reg;
         }
 
-        err = request_resource(&iomem_resource, res_mmio);
-        if (err) {
-                pr_err("PCIE: Failed to request resources: %d\n", err);
-                goto err_req_io;
-        }
-
-        tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
-                                             resource_size(res_mmio));
-        if (tegra_pcie_io_base == NULL) {
-                pr_err("PCIE: Failed to map IO\n");
-                err = -ENOMEM;
-                goto err_map_io;
-        }
-
         err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
                           IRQF_SHARED, "PCIE", &tegra_pcie);
         if (err) {
                 pr_err("PCIE: Failed to register IRQ: %d\n", err);
-                goto err_irq;
+                goto err_req_io;
         }
         set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
 
         return 0;
 
-err_irq:
-        iounmap(tegra_pcie_io_base);
-err_map_io:
-        release_resource(&tegra_pcie.res_mmio);
 err_req_io:
         iounmap(tegra_pcie.regs);
 err_map_reg:
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1a208dbf682f..81cb26591acf 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -31,6 +31,9 @@
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "tegra_cpu_car.h"
+
+#include "common.h"
 
 extern void tegra_secondary_startup(void);
 
@@ -38,19 +41,8 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 
 #define EVP_CPU_RESET_VECTOR \
         (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
-
-#define CPU_CLOCK(cpu)  (0x1<<(8+cpu))
-#define CPU_RESET(cpu)  (0x1111ul<<(cpu))
-
-void __cpuinit platform_secondary_init(unsigned int cpu)
+
+static void __cpuinit tegra_secondary_init(unsigned int cpu)
 {
         /*
          * if any interrupts are already enabled for the primary
@@ -63,13 +55,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 static int tegra20_power_up_cpu(unsigned int cpu)
 {
-        u32 reg;
-
         /* Enable the CPU clock. */
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        barrier();
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        tegra_enable_cpu_clock(cpu);
 
         /* Clear flow controller CSR. */
         flowctrl_write_cpu_csr(cpu, 0);
@@ -79,7 +66,6 @@ static int tegra20_power_up_cpu(unsigned int cpu)
 
 static int tegra30_power_up_cpu(unsigned int cpu)
 {
-        u32 reg;
         int ret, pwrgateid;
         unsigned long timeout;
 
@@ -103,8 +89,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
         }
 
         /* CPU partition is powered. Enable the CPU clock. */
-        writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        tegra_enable_cpu_clock(cpu);
         udelay(10);
 
         /* Remove I/O clamps. */
@@ -117,7 +102,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
         return 0;
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         int status;
 
@@ -128,8 +113,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * via the flow controller). This will have no effect on first boot
          * of the CPU since it should already be in reset.
          */
-        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
-        dmb();
+        tegra_put_cpu_in_reset(cpu);
 
         /*
          * Unhalt the CPU. If the flow controller was used to power-gate the
@@ -155,8 +139,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
                 goto done;
 
         /* Take the CPU out of reset. */
-        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
-        wmb();
+        tegra_cpu_out_of_reset(cpu);
 done:
         return status;
 }
@@ -165,7 +148,7 @@ done:
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
-void __init smp_init_cpus(void)
+static void __init tegra_smp_init_cpus(void)
 {
         unsigned int i, ncores = scu_get_core_count(scu_base);
 
@@ -181,8 +164,19 @@ void __init smp_init_cpus(void)
         set_smp_cross_call(gic_raise_softirq);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
 {
         tegra_cpu_reset_handler_init();
         scu_enable(scu_base);
 }
+
+struct smp_operations tegra_smp_ops __initdata = {
+        .smp_init_cpus          = tegra_smp_init_cpus,
+        .smp_prepare_cpus       = tegra_smp_prepare_cpus,
+        .smp_secondary_init     = tegra_secondary_init,
+        .smp_boot_secondary     = tegra_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = tegra_cpu_die,
+        .cpu_disable            = tegra_cpu_disable,
+#endif
+};
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
new file mode 100644
index 000000000000..a36ae413e2b8
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra20_hotplug_shutdown(void)
+ *
+ * puts the current cpu in reset
+ * should never return
+ */
+ENTRY(tegra20_hotplug_shutdown)
+        /* Turn off SMP coherency */
+        exit_smp r4, r5
+
+        /* Put this CPU down */
+        cpu_id  r0
+        bl      tegra20_cpu_shutdown
+        mov     pc, lr                  @ should never get here
+ENDPROC(tegra20_hotplug_shutdown)
+
+/*
+ * tegra20_cpu_shutdown(int cpu)
+ *
+ * r0 is cpu to reset
+ *
+ * puts the specified CPU in wait-for-event mode on the flow controller
+ * and puts the CPU in reset
+ * can be called on the current cpu or another cpu
+ * if called on the current cpu, does not return
+ * MUST NOT BE CALLED FOR CPU 0.
+ *
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra20_cpu_shutdown)
+        cmp     r0, #0
+        moveq   pc, lr                  @ must not be called for CPU 0
+
+        cpu_to_halt_reg r1, r0
+        ldr     r3, =TEGRA_FLOW_CTRL_VIRT
+        mov     r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
+        str     r2, [r3, r1]            @ put flow controller in wait event mode
+        ldr     r2, [r3, r1]
+        isb
+        dsb
+        movw    r1, 0x1011
+        mov     r1, r1, lsl r0
+        ldr     r3, =TEGRA_CLK_RESET_VIRT
+        str     r1, [r3, #0x340]        @ put slave CPU in reset
+        isb
+        dsb
+        cpu_id  r3
+        cmp     r3, r0
+        beq     .
+        mov     pc, lr
+ENDPROC(tegra20_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
new file mode 100644
index 000000000000..777d9cee8b90
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#define TEGRA30_POWER_HOTPLUG_SHUTDOWN  (1 << 27) /* Hotplug shutdown */
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra30_hotplug_shutdown(void)
+ *
+ * Powergates the current CPU.
+ * Should never return.
+ */
+ENTRY(tegra30_hotplug_shutdown)
+        /* Turn off SMP coherency */
+        exit_smp r4, r5
+
+        /* Powergate this CPU */
+        mov     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        bl      tegra30_cpu_shutdown
+        mov     pc, lr                  @ should never get here
+ENDPROC(tegra30_hotplug_shutdown)
+
+/*
+ * tegra30_cpu_shutdown(unsigned long flags)
+ *
+ * Puts the current CPU in wait-for-event mode on the flow controller
+ * and powergates it -- flags (in R0) indicate the request type.
+ * Must never be called for CPU 0.
+ *
+ * corrupts r0-r4, r12
+ */
+ENTRY(tegra30_cpu_shutdown)
+        cpu_id  r3
+        cmp     r3, #0
+        moveq   pc, lr          @ Must never be called for CPU 0
+
+        ldr     r12, =TEGRA_FLOW_CTRL_VIRT
+        cpu_to_csr_reg r1, r3
+        add     r1, r1, r12     @ virtual CSR address for this CPU
+        cpu_to_halt_reg r2, r3
+        add     r2, r2, r12     @ virtual HALT_EVENTS address for this CPU
+
+        /*
+         * Clear this CPU's "event" and "interrupt" flags and power gate
+         * it when halting but not before it is in the "WFE" state.
+         */
+        movw    r12, \
+                FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
+                FLOW_CTRL_CSR_ENABLE
+        mov     r4, #(1 << 4)
+        orr     r12, r12, r4, lsl r3
+        str     r12, [r1]
+
+        /* Halt this CPU. */
+        mov     r3, #0x400
+delay_1:
+        subs    r3, r3, #1                      @ delay as a part of wfe war.
+        bge     delay_1;
+        cpsid   a                               @ disable imprecise aborts.
+        ldr     r3, [r1]                        @ read CSR
+        str     r3, [r1]                        @ clear CSR
+        tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
+        str     r3, [r2]
+        ldr     r0, [r2]
+        b       wfe_war
+
+__cpu_reset_again:
+        dsb
+        .align 5
+        wfe                                     @ CPU should be power gated here
+wfe_war:
+        b       __cpu_reset_again
+
+        /*
+         * 38 nop's, which fills reset of wfe cache line and
+         * 4 more cachelines with nop
+         */
+        .rept 38
+        nop
+        .endr
+        b       .                               @ should never get here
+
+ENDPROC(tegra30_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156a8011..ea81554c4833 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
 #include <mach/iomap.h>
 
 #include "flowctrl.h"
+#include "sleep.h"
 
-#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
-                                        + IO_PPSB_VIRT)
-
-/* returns the offset of the flow controller halt register for a cpu */
-.macro cpu_to_halt_reg rd, rcpu
-        cmp     \rcpu, #0
-        subne   \rd, \rcpu, #1
-        movne   \rd, \rd, lsl #3
-        addne   \rd, \rd, #0x14
-        moveq   \rd, #0
-.endm
-
-/* returns the offset of the flow controller csr register for a cpu */
-.macro cpu_to_csr_reg rd, rcpu
-        cmp     \rcpu, #0
-        subne   \rd, \rcpu, #1
-        movne   \rd, \rd, lsl #3
-        addne   \rd, \rd, #0x18
-        moveq   \rd, #8
-.endm
-
-/* returns the ID of the current processor */
-.macro cpu_id, rd
-        mrc     p15, 0, \rd, c0, c0, 5
-        and     \rd, \rd, #0xF
-.endm
-
-/* loads a 32-bit value into a register without a data access */
-.macro mov32, reg, val
-        movw    \reg, #:lower16:\val
-        movt    \reg, #:upper16:\val
-.endm
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 000000000000..e25a7cd703d9
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_SLEEP_H
+#define __MACH_TEGRA_SLEEP_H
+
+#include <mach/iomap.h>
+
+#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
+                                        + IO_CPU_VIRT)
+#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
+                                        + IO_PPSB_VIRT)
+#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+                                        + IO_PPSB_VIRT)
+
+#ifdef __ASSEMBLY__
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x14
+        moveq   \rd, #0
+.endm
+
+/* returns the offset of the flow controller csr register for a cpu */
+.macro cpu_to_csr_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x18
+        moveq   \rd, #8
+.endm
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+        mrc     p15, 0, \rd, c0, c0, 5
+        and     \rd, \rd, #0xF
+.endm
+
+/* loads a 32-bit value into a register without a data access */
+.macro mov32, reg, val
+        movw    \reg, #:lower16:\val
+        movt    \reg, #:upper16:\val
+.endm
+
+/* Macro to exit SMP coherency. */
+.macro exit_smp, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
+        bic     \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
+        mcr     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
+        isb
+        cpu_id  \tmp1
+        mov     \tmp1, \tmp1, lsl #2
+        mov     \tmp2, #0xf
+        mov     \tmp2, \tmp2, lsl \tmp1
+        mov32   \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
+        str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
+        dsb
+.endm
+#else
+
+#ifdef CONFIG_HOTPLUG_CPU
+void tegra20_hotplug_init(void);
+void tegra30_hotplug_init(void);
+#else
+static inline void tegra20_hotplug_init(void) {}
+static inline void tegra30_hotplug_init(void) {}
+#endif
+
+#endif
+#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
new file mode 100644
index 000000000000..9273b0dffc66
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -0,0 +1,1625 @@
+/*
+ * arch/arm/mach-tegra/tegra20_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+
+#include <mach/iomap.h>
+#include <mach/suspend.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra2_emc.h"
+#include "tegra_cpu_car.h"
+
+#define RST_DEVICES                     0x004
+#define RST_DEVICES_SET                 0x300
+#define RST_DEVICES_CLR                 0x304
+#define RST_DEVICES_NUM                 3
+
+#define CLK_OUT_ENB                     0x010
+#define CLK_OUT_ENB_SET                 0x320
+#define CLK_OUT_ENB_CLR                 0x324
+#define CLK_OUT_ENB_NUM                 3
+
+#define CLK_MASK_ARM                    0x44
+#define MISC_CLK_ENB                    0x48
+
+#define OSC_CTRL                        0x50
+#define OSC_CTRL_OSC_FREQ_MASK          (3<<30)
+#define OSC_CTRL_OSC_FREQ_13MHZ         (0<<30)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ       (1<<30)
+#define OSC_CTRL_OSC_FREQ_12MHZ         (2<<30)
+#define OSC_CTRL_OSC_FREQ_26MHZ         (3<<30)
+#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
+
+#define OSC_FREQ_DET                    0x58
+#define OSC_FREQ_DET_TRIG               (1<<31)
+
+#define OSC_FREQ_DET_STATUS             0x5C
+#define OSC_FREQ_DET_BUSY               (1<<31)
+#define OSC_FREQ_DET_CNT_MASK           0xFFFF
+
+#define PERIPH_CLK_SOURCE_I2S1          0x100
+#define PERIPH_CLK_SOURCE_EMC           0x19c
+#define PERIPH_CLK_SOURCE_OSC           0x1fc
+#define PERIPH_CLK_SOURCE_NUM \
+        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
+
+#define PERIPH_CLK_SOURCE_MASK          (3<<30)
+#define PERIPH_CLK_SOURCE_SHIFT         30
+#define PERIPH_CLK_SOURCE_PWM_MASK      (7<<28)
+#define PERIPH_CLK_SOURCE_PWM_SHIFT     28
+#define PERIPH_CLK_SOURCE_ENABLE        (1<<28)
+#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
+#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
+#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
+
+#define SDMMC_CLK_INT_FB_SEL            (1 << 23)
+#define SDMMC_CLK_INT_FB_DLY_SHIFT      16
+#define SDMMC_CLK_INT_FB_DLY_MASK       (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
+
+#define PLL_BASE                        0x0
+#define PLL_BASE_BYPASS                 (1<<31)
+#define PLL_BASE_ENABLE                 (1<<30)
+#define PLL_BASE_REF_ENABLE             (1<<29)
+#define PLL_BASE_OVERRIDE               (1<<28)
+#define PLL_BASE_DIVP_MASK              (0x7<<20)
+#define PLL_BASE_DIVP_SHIFT             20
+#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
+#define PLL_BASE_DIVN_SHIFT             8
+#define PLL_BASE_DIVM_MASK              (0x1F)
+#define PLL_BASE_DIVM_SHIFT             0
+
+#define PLL_OUT_RATIO_MASK              (0xFF<<8)
+#define PLL_OUT_RATIO_SHIFT             8
+#define PLL_OUT_OVERRIDE                (1<<2)
+#define PLL_OUT_CLKEN                   (1<<1)
+#define PLL_OUT_RESET_DISABLE           (1<<0)
+
+#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
+
+#define PLL_MISC_DCCON_SHIFT            20
+#define PLL_MISC_CPCON_SHIFT            8
+#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
+#define PLL_MISC_LFCON_SHIFT            4
+#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
+#define PLL_MISC_VCOCON_SHIFT           0
+#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
+
+#define PLLU_BASE_POST_DIV              (1<<20)
+
+#define PLLD_MISC_CLKENABLE             (1<<30)
+#define PLLD_MISC_DIV_RST               (1<<23)
+#define PLLD_MISC_DCCON_SHIFT           12
+
+#define PLLE_MISC_READY                 (1 << 15)
+
+#define PERIPH_CLK_TO_ENB_REG(c)        ((c->u.periph.clk_num / 32) * 4)
+#define PERIPH_CLK_TO_ENB_SET_REG(c)    ((c->u.periph.clk_num / 32) * 8)
+#define PERIPH_CLK_TO_ENB_BIT(c)        (1 << (c->u.periph.clk_num % 32))
+
+#define SUPER_CLK_MUX                   0x00
+#define SUPER_STATE_SHIFT               28
+#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
+#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
+#define SUPER_SOURCE_MASK               0xF
+#define SUPER_FIQ_SOURCE_SHIFT          12
+#define SUPER_IRQ_SOURCE_SHIFT          8
+#define SUPER_RUN_SOURCE_SHIFT          4
+#define SUPER_IDLE_SOURCE_SHIFT         0
+
+#define SUPER_CLK_DIVIDER               0x04
+
+#define BUS_CLK_DISABLE                 (1<<3)
+#define BUS_CLK_DIV_MASK                0x3
+
+#define PMC_CTRL                        0x0
+ #define PMC_CTRL_BLINK_ENB             (1 << 7)
+
+#define PMC_DPD_PADS_ORIDE              0x1c
+ #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
+
+#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
+#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
+#define PMC_BLINK_TIMER_ENB             (1 << 15)
+#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
+#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
+
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
+
+#define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
+#define CPU_RESET(cpu)  (0x1111ul << (cpu))
+
+static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+
+/*
+ * Some clocks share a register with other clocks.  Any clock op that
+ * non-atomically modifies a register used by another clock must lock
+ * clock_register_lock first.
+ */
+static DEFINE_SPINLOCK(clock_register_lock);
+
+/*
+ * Some peripheral clocks share an enable bit, so refcount the enable bits
+ * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
+ */
+static int tegra_periph_clk_enable_refcount[3 * 32];
+
+#define clk_writel(value, reg) \
+        __raw_writel(value, reg_clk_base + (reg))
+#define clk_readl(reg) \
+        __raw_readl(reg_clk_base + (reg))
+#define pmc_writel(value, reg) \
+        __raw_writel(value, reg_pmc_base + (reg))
+#define pmc_readl(reg) \
+        __raw_readl(reg_pmc_base + (reg))
+
+static unsigned long clk_measure_input_freq(void)
+{
+        u32 clock_autodetect;
+        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
+        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
+        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
+        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
+                return 12000000;
+        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
+                return 13000000;
+        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
+                return 19200000;
+        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
+                return 26000000;
+        } else {
+                pr_err("%s: Unexpected clock autodetect value %d",
+                                                __func__, clock_autodetect);
+                BUG();
+                return 0;
+        }
+}
+
+static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+        s64 divider_u71 = parent_rate * 2;
+        divider_u71 += rate - 1;
+        do_div(divider_u71, rate);
+
+        if (divider_u71 - 2 < 0)
+                return 0;
+
+        if (divider_u71 - 2 > 255)
+                return -EINVAL;
+
+        return divider_u71 - 2;
+}
+
+static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+        s64 divider_u16;
+
+        divider_u16 = parent_rate;
+        divider_u16 += rate - 1;
+        do_div(divider_u16, rate);
+
+        if (divider_u16 - 1 < 0)
+                return 0;
+
+        if (divider_u16 - 1 > 0xFFFF)
+                return -EINVAL;
+
+        return divider_u16 - 1;
+}
+
+static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra_clk_32k_ops = {
+        .recalc_rate = tegra_clk_fixed_recalc_rate,
+};
+
+/* clk_m functions */
+static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        if (!to_clk_tegra(hw)->fixed_rate)
+                to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+static void tegra20_clk_m_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 osc_ctrl = clk_readl(OSC_CTRL);
+        u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
+
+        switch (c->fixed_rate) {
+        case 12000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
+                break;
+        case 13000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
+                break;
+        case 19200000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
+                break;
+        case 26000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
+                break;
+        default:
+                BUG();
+        }
+        clk_writel(auto_clock_control, OSC_CTRL);
+}
+
+struct clk_ops tegra_clk_m_ops = {
+        .init = tegra20_clk_m_init,
+        .recalc_rate = tegra20_clk_m_recalc_rate,
+};
+
+/* super clock functions */
+/* "super clocks" on tegra have two-stage muxes and a clock skipping
+ * super divider.  We will ignore the clock skipping divider, since we
+ * can't lower the voltage when using the clock skip, but we can if we
+ * lower the PLL frequency.
+ */
+static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        c->state = ON;
+        return c->state;
+}
+
+static int tegra20_super_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+        return 0;
+}
+
+static void tegra20_super_clk_disable(struct clk_hw *hw)
+{
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        /* oops - don't disable the CPU clock! */
+        BUG();
+}
+
+static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        int val = clk_readl(c->reg + SUPER_CLK_MUX);
+        int source;
+        int shift;
+
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        source = (val >> shift) & SUPER_SOURCE_MASK;
+        return source;
+}
+
+static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
+        int shift;
+
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        val &= ~(SUPER_SOURCE_MASK << shift);
+        val |= index << shift;
+
+        clk_writel(val, c->reg);
+
+        return 0;
+}
+
+/* FIX ME: Need to switch parents to change the source PLL rate */
+static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        return prate;
+}
+
+static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        return *prate;
+}
+
+static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        return 0;
+}
+
+struct clk_ops tegra_super_ops = {
+        .is_enabled = tegra20_super_clk_is_enabled,
+        .enable = tegra20_super_clk_enable,
+        .disable = tegra20_super_clk_disable,
+        .set_parent = tegra20_super_clk_set_parent,
+        .get_parent = tegra20_super_clk_get_parent,
+        .set_rate = tegra20_super_clk_set_rate,
+        .round_rate = tegra20_super_clk_round_rate,
+        .recalc_rate = tegra20_super_clk_recalc_rate,
+};
+
+static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+struct clk_ops tegra_twd_ops = {
+        .recalc_rate = tegra20_twd_clk_recalc_rate,
+};
+
+static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
+{
+        return 0;
+}
+
+struct clk_ops tegra_cop_ops = {
+        .get_parent = tegra20_cop_clk_get_parent,
+};
+
+/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
+ * reset the COP block (i.e. AVP) */
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
+{
+        unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
+
+        pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
+        clk_writel(1 << 1, reg);
+}
+
+/* bus clock functions */
+static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+
+        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
+        return c->state;
+}
+
+static int tegra20_bus_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 val;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        val = clk_readl(c->reg);
+        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
+        clk_writel(val, c->reg);
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+
+        return 0;
+}
+
+static void tegra20_bus_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 val;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        val = clk_readl(c->reg);
+        val |= BUS_CLK_DISABLE << c->reg_shift;
+        clk_writel(val, c->reg);
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+}
+
+static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        u64 rate = prate;
+
+        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
+        c->mul = 1;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+
+static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        int ret = -EINVAL;
+        unsigned long flags;
+        u32 val;
+        int i;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        val = clk_readl(c->reg);
+        for (i = 1; i <= 4; i++) {
+                if (rate == parent_rate / i) {
+                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
+                        val |= (i - 1) << c->reg_shift;
+                        clk_writel(val, c->reg);
+                        c->div = i;
+                        c->mul = 1;
+                        ret = 0;
+                        break;
+                }
+        }
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+
+        return ret;
+}
+
+static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        unsigned long parent_rate = *prate;
+        s64 divider;
+
+        if (rate >= parent_rate)
+                return rate;
+
+        divider = parent_rate;
+        divider += rate - 1;
+        do_div(divider, rate);
+
+        if (divider < 0)
+                return divider;
+
+        if (divider > 4)
+                divider = 4;
+        do_div(parent_rate, divider);
+
+        return parent_rate;
+}
+
+struct clk_ops tegra_bus_ops = {
+        .is_enabled = tegra20_bus_clk_is_enabled,
+        .enable = tegra20_bus_clk_enable,
+        .disable = tegra20_bus_clk_disable,
+        .set_rate = tegra20_bus_clk_set_rate,
+        .round_rate = tegra20_bus_clk_round_rate,
+        .recalc_rate = tegra20_bus_clk_recalc_rate,
+};
+
+/* Blink output functions */
+static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        val = pmc_readl(PMC_CTRL);
+        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
+        return c->state;
+}
+
+static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = prate;
+        u32 val;
+
+        c->mul = 1;
+        val = pmc_readl(c->reg);
+
+        if (val & PMC_BLINK_TIMER_ENB) {
+                unsigned int on_off;
+
+                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+                        PMC_BLINK_TIMER_DATA_ON_MASK;
+                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off += val;
+                /* each tick in the blink timer is 4 32KHz clocks */
+                c->div = on_off * 4;
+        } else {
+                c->div = 1;
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+
+static int tegra20_blink_clk_enable(struct clk_hw *hw)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+        return 0;
+}
+
+static void tegra20_blink_clk_disable(struct clk_hw *hw)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+}
+
+static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        if (rate >= parent_rate) {
+                c->div = 1;
+                pmc_writel(0, c->reg);
+        } else {
+                unsigned int on_off;
+                u32 val;
+
+                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
+                c->div = on_off * 8;
+
+                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
+                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
+                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val |= on_off;
+                val |= PMC_BLINK_TIMER_ENB;
+                pmc_writel(val, c->reg);
+        }
+
+        return 0;
+}
+
+static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        int div;
+        int mul;
+        long round_rate = *prate;
+
+        mul = 1;
+
+        if (rate >= *prate) {
+                div = 1;
+        } else {
+                div = DIV_ROUND_UP(*prate / 8, rate);
+                div *= 8;
+        }
+
+        round_rate *= mul;
+        round_rate += div - 1;
+        do_div(round_rate, div);
+
+        return round_rate;
+}
+
+struct clk_ops tegra_blink_clk_ops = {
+        .is_enabled = tegra20_blink_clk_is_enabled,
+        .enable = tegra20_blink_clk_enable,
+        .disable = tegra20_blink_clk_disable,
+        .set_rate = tegra20_blink_clk_set_rate,
+        .round_rate = tegra20_blink_clk_round_rate,
+        .recalc_rate = tegra20_blink_clk_recalc_rate,
+};
+
+/* PLL Functions */
+static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
+{
+        udelay(c->u.pll.lock_delay);
+        return 0;
+}
+
+static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg + PLL_BASE);
+
+        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+        return c->state;
+}
+
+static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
+                                unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg + PLL_BASE);
+        u64 rate = prate;
+
+        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+                const struct clk_pll_freq_table *sel;
+                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                        if (sel->input_rate == prate &&
+                                sel->output_rate == c->u.pll.fixed_rate) {
+                                c->mul = sel->n;
+                                c->div = sel->m * sel->p;
+                                break;
+                        }
+                }
+                pr_err("Clock %s has unknown fixed frequency\n",
+                        __clk_get_name(hw->clk));
+                BUG();
+        } else if (val & PLL_BASE_BYPASS) {
+                c->mul = 1;
+                c->div = 1;
+        } else {
+                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+                if (c->flags & PLLU)
+                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+                else
+                        c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+
+static int tegra20_pll_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        val = clk_readl(c->reg + PLL_BASE);
+        val &= ~PLL_BASE_BYPASS;
+        val |= PLL_BASE_ENABLE;
+        clk_writel(val, c->reg + PLL_BASE);
+
+        tegra20_pll_clk_wait_for_lock(c);
+
+        return 0;
+}
+
+static void tegra20_pll_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        val = clk_readl(c->reg);
+        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+        clk_writel(val, c->reg);
+}
+
+static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long input_rate = parent_rate;
+        const struct clk_pll_freq_table *sel;
+        u32 val;
+
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+        if (c->flags & PLL_FIXED) {
+                int ret = 0;
+                if (rate != c->u.pll.fixed_rate) {
+                        pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
+                                __func__, __clk_get_name(hw->clk),
+                                c->u.pll.fixed_rate, rate);
+                        ret = -EINVAL;
+                }
+                return ret;
+        }
+
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        c->mul = sel->n;
+                        c->div = sel->m * sel->p;
+
+                        val = clk_readl(c->reg + PLL_BASE);
+                        if (c->flags & PLL_FIXED)
+                                val |= PLL_BASE_OVERRIDE;
+                        val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
+                                 PLL_BASE_DIVM_MASK);
+                        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
+                                (sel->n << PLL_BASE_DIVN_SHIFT);
+                        BUG_ON(sel->p < 1 || sel->p > 2);
+                        if (c->flags & PLLU) {
+                                if (sel->p == 1)
+                                        val |= PLLU_BASE_POST_DIV;
+                        } else {
+                                if (sel->p == 2)
+                                        val |= 1 << PLL_BASE_DIVP_SHIFT;
+                        }
+                        clk_writel(val, c->reg + PLL_BASE);
+
+                        if (c->flags & PLL_HAS_CPCON) {
+                                val = clk_readl(c->reg + PLL_MISC(c));
+                                val &= ~PLL_MISC_CPCON_MASK;
+                                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
+                                clk_writel(val, c->reg + PLL_MISC(c));
+                        }
+
+                        if (c->state == ON)
+                                tegra20_pll_clk_enable(hw);
+                        return 0;
+                }
+        }
+        return -EINVAL;
+}
+
+static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        const struct clk_pll_freq_table *sel;
+        unsigned long input_rate = *prate;
+        u64 output_rate = *prate;
+        int mul;
+        int div;
+
+        if (c->flags & PLL_FIXED)
+                return c->u.pll.fixed_rate;
+
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        mul = sel->n;
+                        div = sel->m * sel->p;
+                        break;
+                }
+
+        if (sel->input_rate == 0)
+                return -EINVAL;
+
+        output_rate *= mul;
+        output_rate += div - 1; /* round up */
+        do_div(output_rate, div);
+
+        return output_rate;
+}
+
+struct clk_ops tegra_pll_ops = {
+        .is_enabled = tegra20_pll_clk_is_enabled,
+        .enable = tegra20_pll_clk_enable,
+        .disable = tegra20_pll_clk_disable,
+        .set_rate = tegra20_pll_clk_set_rate,
+        .recalc_rate = tegra20_pll_clk_recalc_rate,
+        .round_rate = tegra20_pll_clk_round_rate,
+};
+
+static void tegra20_pllx_clk_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        if (tegra_sku_id == 7)
+                c->max_rate = 750000000;
+}
+
+struct clk_ops tegra_pllx_ops = {
+        .init = tegra20_pllx_clk_init,
+        .is_enabled = tegra20_pll_clk_is_enabled,
+        .enable = tegra20_pll_clk_enable,
+        .disable = tegra20_pll_clk_disable,
+        .set_rate = tegra20_pll_clk_set_rate,
+        .recalc_rate = tegra20_pll_clk_recalc_rate,
+        .round_rate = tegra20_pll_clk_round_rate,
+};
+
+static int tegra20_plle_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        mdelay(1);
+
+        val = clk_readl(c->reg + PLL_BASE);
+        if (!(val & PLLE_MISC_READY))
+                return -EBUSY;
+
+        val = clk_readl(c->reg + PLL_BASE);
+        val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
+        clk_writel(val, c->reg + PLL_BASE);
+
+        return 0;
+}
+
+struct clk_ops tegra_plle_ops = {
+        .is_enabled = tegra20_pll_clk_is_enabled,
+        .enable = tegra20_plle_clk_enable,
+        .set_rate = tegra20_pll_clk_set_rate,
+        .recalc_rate = tegra20_pll_clk_recalc_rate,
+        .round_rate = tegra20_pll_clk_round_rate,
+};
+
+/* Clock divider ops */
+static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+
+        val >>= c->reg_shift;
+        c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
+        if (!(val & PLL_OUT_RESET_DISABLE))
+                c->state = OFF;
+        return c->state;
+}
+
+static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = prate;
+        u32 val = clk_readl(c->reg);
+        u32 divu71;
+
+        val >>= c->reg_shift;
+
+        if (c->flags & DIV_U71) {
+                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+                c->div = (divu71 + 2);
+                c->mul = 2;
+        } else if (c->flags & DIV_2) {
+                c->div = 2;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+
+        rate *= c->mul;
+        rate += c->div - 1; /* round up */
+        do_div(rate, c->div);
+
+        return rate;
+}
+
+static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 new_val;
+        u32 val;
+
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+
+        if (c->flags & DIV_U71) {
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+
+                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+                return 0;
+        } else if (c->flags & DIV_2) {
+                BUG_ON(!(c->flags & PLLD));
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                val &= ~PLLD_MISC_DIV_RST;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 new_val;
+        u32 val;
+
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+
+        if (c->flags & DIV_U71) {
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+
+                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
+
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+        } else if (c->flags & DIV_2) {
+                BUG_ON(!(c->flags & PLLD));
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                val |= PLLD_MISC_DIV_RST;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+        }
+}
+
+static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        int divider_u71;
+        u32 new_val;
+        u32 val;
+
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+        if (c->flags & DIV_U71) {
+                divider_u71 = clk_div71_get_divider(parent_rate, rate);
+                if (divider_u71 >= 0) {
+                        spin_lock_irqsave(&clock_register_lock, flags);
+                        val = clk_readl(c->reg);
+                        new_val = val >> c->reg_shift;
+                        new_val &= 0xFFFF;
+                        if (c->flags & DIV_U71_FIXED)
+                                new_val |= PLL_OUT_OVERRIDE;
+                        new_val &= ~PLL_OUT_RATIO_MASK;
+                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
+
+                        val &= ~(0xFFFF << c->reg_shift);
+                        val |= new_val << c->reg_shift;
+                        clk_writel(val, c->reg);
+                        c->div = divider_u71 + 2;
+                        c->mul = 2;
+                        spin_unlock_irqrestore(&clock_register_lock, flags);
+                        return 0;
+                }
+        } else if (c->flags & DIV_2) {
+                if (parent_rate == rate * 2)
+                        return 0;
+        }
+        return -EINVAL;
+}
+
+static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = *prate;
+        int divider;
+
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_2) {
+                return DIV_ROUND_UP(parent_rate, 2);
+        }
+        return -EINVAL;
+}
+
+struct clk_ops tegra_pll_div_ops = {
+        .is_enabled = tegra20_pll_div_clk_is_enabled,
+        .enable = tegra20_pll_div_clk_enable,
+        .disable = tegra20_pll_div_clk_disable,
+        .set_rate = tegra20_pll_div_clk_set_rate,
+        .round_rate = tegra20_pll_div_clk_round_rate,
+        .recalc_rate = tegra20_pll_div_clk_recalc_rate,
+};
+
+/* Periph clk ops */
+
+static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        c->state = ON;
+
+        if (!c->u.periph.clk_num)
+                goto out;
+
+        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+                        PERIPH_CLK_TO_ENB_BIT(c)))
+                c->state = OFF;
+
+        if (!(c->flags & PERIPH_NO_RESET))
+                if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
+                                PERIPH_CLK_TO_ENB_BIT(c))
+                        c->state = OFF;
+
+out:
+        return c->state;
+}
+
+static int tegra20_periph_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 val;
+
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        if (!c->u.periph.clk_num)
+                return 0;
+
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
+                return 0;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+        if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
+                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                        RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+        if (c->flags & PERIPH_EMC_ENB) {
+                /* The EMC peripheral clock has 2 extra enable bits */
+                /* FIXME: Do they need to be disabled? */
+                val = clk_readl(c->reg);
+                val |= 0x3 << 24;
+                clk_writel(val, c->reg);
+        }
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+
+        return 0;
+}
+
+static void tegra20_periph_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        if (!c->u.periph.clk_num)
+                return;
+
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+                return;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+}
+
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
+
+        pr_debug("%s %s on clock %s\n", __func__,
+                assert ? "assert" : "deassert", __clk_get_name(hw->clk));
+
+        BUG_ON(!c->u.periph.clk_num);
+
+        if (!(c->flags & PERIPH_NO_RESET))
+                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                           base + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        u32 mask;
+        u32 shift;
+
+        pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
+
+        if (c->flags & MUX_PWM) {
+                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+                mask = PERIPH_CLK_SOURCE_PWM_MASK;
+        } else {
+                shift = PERIPH_CLK_SOURCE_SHIFT;
+                mask = PERIPH_CLK_SOURCE_MASK;
+        }
+
+        val = clk_readl(c->reg);
+        val &= ~mask;
+        val |= (index) << shift;
+
+        clk_writel(val, c->reg);
+
+        return 0;
+}
+
+static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        u32 mask;
+        u32 shift;
+
+        if (c->flags & MUX_PWM) {
+                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+                mask = PERIPH_CLK_SOURCE_PWM_MASK;
+        } else {
+                shift = PERIPH_CLK_SOURCE_SHIFT;
+                mask = PERIPH_CLK_SOURCE_MASK;
+        }
+
+        if (c->flags & MUX)
+                return (val & mask) >> shift;
+        else
+                return 0;
+}
+
+static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long rate = prate;
+        u32 val = clk_readl(c->reg);
+
+        if (c->flags & DIV_U71) {
+                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+                c->div = divu71 + 2;
+                c->mul = 2;
+        } else if (c->flags & DIV_U16) {
+                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+                c->div = divu16 + 1;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+                return rate;
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        int divider;
+
+        val = clk_readl(c->reg);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(parent_rate, rate);
+
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
+                        val |= divider;
+                        clk_writel(val, c->reg);
+                        c->div = divider + 2;
+                        c->mul = 2;
+                        return 0;
+                }
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
+                        val |= divider;
+                        clk_writel(val, c->reg);
+                        c->div = divider + 1;
+                        c->mul = 1;
+                        return 0;
+                }
+        } else if (parent_rate <= rate) {
+                c->div = 1;
+                c->mul = 1;
+                return 0;
+        }
+
+        return -EINVAL;
+}
+
+static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
+        unsigned long rate, unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+        int divider;
+
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+        if (prate)
+                parent_rate = *prate;
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate, divider + 1);
+        }
+        return -EINVAL;
+}
+
+struct clk_ops tegra_periph_clk_ops = {
+        .is_enabled = tegra20_periph_clk_is_enabled,
+        .enable = tegra20_periph_clk_enable,
+        .disable = tegra20_periph_clk_disable,
+        .set_parent = tegra20_periph_clk_set_parent,
+        .get_parent = tegra20_periph_clk_get_parent,
+        .set_rate = tegra20_periph_clk_set_rate,
+        .round_rate = tegra20_periph_clk_round_rate,
+        .recalc_rate = tegra20_periph_clk_recalc_rate,
+};
+
+/* External memory controller clock ops */
+static void tegra20_emc_clk_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        c->max_rate = __clk_get_rate(hw->clk);
+}
+
+static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        long emc_rate;
+        long clk_rate;
+
+        /*
+         * The slowest entry in the EMC clock table that is at least as
+         * fast as rate.
+         */
+        emc_rate = tegra_emc_round_rate(rate);
+        if (emc_rate < 0)
+                return c->max_rate;
+
+        /*
+         * The fastest rate the PLL will generate that is at most the
+         * requested rate.
+         */
+        clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
+
+        /*
+         * If this fails, and emc_rate > clk_rate, it's because the maximum
+         * rate in the EMC tables is larger than the maximum rate of the EMC
+         * clock. The EMC clock's max rate is the rate it was running when the
+         * kernel booted. Such a mismatch is probably due to using the wrong
+         * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
+         */
+        WARN_ONCE(emc_rate != clk_rate,
+                "emc_rate %ld != clk_rate %ld",
+                emc_rate, clk_rate);
+
+        return emc_rate;
+}
+
+static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        int ret;
+
+        /*
+         * The Tegra2 memory controller has an interlock with the clock
+         * block that allows memory shadowed registers to be updated,
+         * and then transfer them to the main registers at the same
+         * time as the clock update without glitches.
+         */
+        ret = tegra_emc_set_rate(rate);
+        if (ret < 0)
+                return ret;
+
+        ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
+        udelay(1);
+
+        return ret;
+}
+
+struct clk_ops tegra_emc_clk_ops = {
+        .init = tegra20_emc_clk_init,
+        .is_enabled = tegra20_periph_clk_is_enabled,
+        .enable = tegra20_periph_clk_enable,
+        .disable = tegra20_periph_clk_disable,
+        .set_parent = tegra20_periph_clk_set_parent,
+        .get_parent = tegra20_periph_clk_get_parent,
+        .set_rate = tegra20_emc_clk_set_rate,
+        .round_rate = tegra20_emc_clk_round_rate,
+        .recalc_rate = tegra20_periph_clk_recalc_rate,
+};
+
+/* Clock doubler ops */
+static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        c->state = ON;
+
+        if (!c->u.periph.clk_num)
+                goto out;
+
+        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+                        PERIPH_CLK_TO_ENB_BIT(c)))
+                c->state = OFF;
+
+out:
+        return c->state;
+};
+
+static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = prate;
+
+        c->mul = 2;
+        c->div = 1;
+
+        rate *= c->mul;
+        rate += c->div - 1; /* round up */
+        do_div(rate, c->div);
+
+        return rate;
+}
+
+static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        unsigned long output_rate = *prate;
+
+        do_div(output_rate, 2);
+        return output_rate;
+}
+
+static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        if (rate != 2 * parent_rate)
+                return -EINVAL;
+        return 0;
+}
+
+struct clk_ops tegra_clk_double_ops = {
+        .is_enabled = tegra20_clk_double_is_enabled,
+        .enable = tegra20_periph_clk_enable,
+        .disable = tegra20_periph_clk_disable,
+        .set_rate = tegra20_clk_double_set_rate,
+        .recalc_rate = tegra20_clk_double_recalc_rate,
+        .round_rate = tegra20_clk_double_round_rate,
+};
+
+/* Audio sync clock ops */
+static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+
+        c->state = (val & (1<<4)) ? OFF : ON;
+        return c->state;
+}
+
+static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        clk_writel(0, c->reg);
+        return 0;
+}
+
+static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        clk_writel(1, c->reg);
+}
+
+static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        int source;
+
+        source = val & 0xf;
+        return source;
+}
+
+static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        val = clk_readl(c->reg);
+        val &= ~0xf;
+        val |= index;
+
+        clk_writel(val, c->reg);
+
+        return 0;
+}
+
+struct clk_ops tegra_audio_sync_clk_ops = {
+        .is_enabled = tegra20_audio_sync_clk_is_enabled,
+        .enable = tegra20_audio_sync_clk_enable,
+        .disable = tegra20_audio_sync_clk_disable,
+        .set_parent = tegra20_audio_sync_clk_set_parent,
+        .get_parent = tegra20_audio_sync_clk_get_parent,
+};
+
+/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
+
+static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
+         * currently done in the pinmux code. */
+        c->state = ON;
+
+        BUG_ON(!c->u.periph.clk_num);
+
+        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+                        PERIPH_CLK_TO_ENB_BIT(c)))
+                c->state = OFF;
+        return c->state;
+}
+
+static int tegra20_cdev_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        BUG_ON(!c->u.periph.clk_num);
+
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+        return 0;
+}
+
+static void tegra20_cdev_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        BUG_ON(!c->u.periph.clk_num);
+
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra_cdev_clk_ops = {
+        .is_enabled = tegra20_cdev_clk_is_enabled,
+        .enable = tegra20_cdev_clk_enable,
+        .disable = tegra20_cdev_clk_disable,
+        .recalc_rate = tegra20_cdev_recalc_rate,
+};
+
+/* Tegra20 CPU clock and reset control functions */
+static void tegra20_wait_cpu_in_reset(u32 cpu)
+{
+        unsigned int reg;
+
+        do {
+                reg = readl(reg_clk_base +
+                            TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+                cpu_relax();
+        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+
+        return;
+}
+
+static void tegra20_put_cpu_in_reset(u32 cpu)
+{
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+        dmb();
+}
+
+static void tegra20_cpu_out_of_reset(u32 cpu)
+{
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        wmb();
+}
+
+static void tegra20_enable_cpu_clock(u32 cpu)
+{
+        unsigned int reg;
+
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg & ~CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        barrier();
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static void tegra20_disable_cpu_clock(u32 cpu)
+{
+        unsigned int reg;
+
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg | CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
+        .wait_for_reset = tegra20_wait_cpu_in_reset,
+        .put_in_reset   = tegra20_put_cpu_in_reset,
+        .out_of_reset   = tegra20_cpu_out_of_reset,
+        .enable_clock   = tegra20_enable_cpu_clock,
+        .disable_clock  = tegra20_disable_cpu_clock,
+};
+
+void __init tegra20_cpu_car_ops_init(void)
+{
+        tegra_cpu_car_ops = &tegra20_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
new file mode 100644
index 000000000000..8bfd31bcc490
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA20_CLOCK_H
+#define __MACH_TEGRA20_CLOCK_H
+
+extern struct clk_ops tegra_clk_32k_ops;
+extern struct clk_ops tegra_pll_ops;
+extern struct clk_ops tegra_clk_m_ops;
+extern struct clk_ops tegra_pll_div_ops;
+extern struct clk_ops tegra_pllx_ops;
+extern struct clk_ops tegra_plle_ops;
+extern struct clk_ops tegra_clk_double_ops;
+extern struct clk_ops tegra_cdev_clk_ops;
+extern struct clk_ops tegra_audio_sync_clk_ops;
+extern struct clk_ops tegra_super_ops;
+extern struct clk_ops tegra_cpu_ops;
+extern struct clk_ops tegra_twd_ops;
+extern struct clk_ops tegra_cop_ops;
+extern struct clk_ops tegra_bus_ops;
+extern struct clk_ops tegra_blink_clk_ops;
+extern struct clk_ops tegra_emc_clk_ops;
+extern struct clk_ops tegra_periph_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
new file mode 100644
index 000000000000..e81dcd239c95
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -0,0 +1,1144 @@
+/*
+ * arch/arm/mach-tegra/tegra2_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk-private.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/iomap.h>
+#include <mach/suspend.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra2_emc.h"
+#include "tegra20_clocks.h"
+#include "tegra_cpu_car.h"
+
+/* Clock definitions */
+
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,            \
+                   _parent_names, _parents, _parent)            \
+        static struct clk tegra_##_name = {                     \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .name = #_name,                                 \
+                .rate = _rate,                                  \
+                .ops = _ops,                                    \
+                .flags = _flags,                                \
+                .parent_names = _parent_names,                  \
+                .parents = _parents,                            \
+                .num_parents = ARRAY_SIZE(_parent_names),       \
+                .parent = _parent,                              \
+        };
+
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+        .hw = {
+                .clk = &tegra_clk_32k,
+        },
+        .fixed_rate = 32768,
+};
+
+static struct clk tegra_clk_32k = {
+        .name = "clk_32k",
+        .rate = 32768,
+        .ops = &tegra_clk_32k_ops,
+        .hw = &tegra_clk_32k_hw.hw,
+        .flags = CLK_IS_ROOT,
+};
+
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+        .hw = {
+                .clk = &tegra_clk_m,
+        },
+        .flags = ENABLE_ON_INIT,
+        .reg = 0x1fc,
+        .reg_shift = 28,
+        .max_rate = 26000000,
+        .fixed_rate = 0,
+};
+
+static struct clk tegra_clk_m = {
+        .name = "clk_m",
+        .ops = &tegra_clk_m_ops,
+        .hw = &tegra_clk_m_hw.hw,
+        .flags = CLK_IS_ROOT,
+};
+
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,  \
+                   _input_max, _cf_min, _cf_max, _vco_min,      \
+                   _vco_max, _freq_table, _lock_delay, _ops,    \
+                   _fixed_rate, _parent)                        \
+        static const char *tegra_##_name##_parent_names[] = {   \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *tegra_##_name##_parents[] = {        \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .u.pll = {                                      \
+                        .input_min = _input_min,                \
+                        .input_max = _input_max,                \
+                        .cf_min = _cf_min,                      \
+                        .cf_max = _cf_max,                      \
+                        .vco_min = _vco_min,                    \
+                        .vco_max = _vco_max,                    \
+                        .freq_table = _freq_table,              \
+                        .lock_delay = _lock_delay,              \
+                        .fixed_rate = _fixed_rate,              \
+                },                                              \
+        };                                                      \
+        static struct clk tegra_##_name = {                     \
+                .name = #_name,                                 \
+                .ops = &_ops,                                   \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .parent = &tegra_##_parent,                     \
+                .parent_names = tegra_##_name##_parent_names,   \
+                .parents = tegra_##_name##_parents,             \
+                .num_parents = 1,                               \
+        };
+
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,         \
+                _max_rate, _ops, _parent, _clk_flags)           \
+        static const char *tegra_##_name##_parent_names[] = {   \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *tegra_##_name##_parents[] = {        \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .reg_shift = _reg_shift,                        \
+        };                                                      \
+        static struct clk tegra_##_name = {                     \
+                .name = #_name,                                 \
+                .ops = &tegra_pll_div_ops,                      \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .parent = &tegra_##_parent,                     \
+                .parent_names = tegra_##_name##_parent_names,   \
+                .parents = tegra_##_name##_parents,             \
+                .num_parents = 1,                               \
+                .flags = _clk_flags,                            \
+        };
+
+
+static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
+        {32768, 12000000, 366, 1, 1, 0},
+        {32768, 13000000, 397, 1, 1, 0},
+        {32768, 19200000, 586, 1, 1, 0},
+        {32768, 26000000, 793, 1, 1, 0},
+        {0, 0, 0, 0, 0, 0},
+};
+
+DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
+                0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
+                tegra_pll_ops, 0, clk_32k);
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+        { 12000000, 600000000, 600, 12, 1, 8 },
+        { 13000000, 600000000, 600, 13, 1, 8 },
+        { 19200000, 600000000, 500, 16, 1, 6 },
+        { 26000000, 600000000, 600, 26, 1, 8 },
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+                tegra_pll_ops, 0, clk_m);
+
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
+                tegra_pll_div_ops, pll_c, 0);
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+        { 12000000, 666000000, 666, 12, 1, 8},
+        { 13000000, 666000000, 666, 13, 1, 8},
+        { 19200000, 666000000, 555, 16, 1, 8},
+        { 26000000, 666000000, 666, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
+                tegra_pll_ops, 0, clk_m);
+
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+                tegra_pll_div_ops, pll_m, 0);
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+        { 12000000, 216000000, 432, 12, 2, 8},
+        { 13000000, 216000000, 432, 13, 2, 8},
+        { 19200000, 216000000, 90,   4, 2, 1},
+        { 26000000, 216000000, 432, 26, 2, 8},
+        { 12000000, 432000000, 432, 12, 1, 8},
+        { 13000000, 432000000, 432, 13, 1, 8},
+        { 19200000, 432000000, 90,   4, 1, 1},
+        { 26000000, 432000000, 432, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+                2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+                tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
+
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+        { 28800000, 56448000, 49, 25, 1, 1},
+        { 28800000, 73728000, 64, 25, 1, 1},
+        { 28800000, 24000000,  5,  6, 1, 1},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
+                tegra_pll_ops, 0, pll_p_out1);
+
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
+                tegra_pll_div_ops, pll_a, 0);
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+        { 12000000, 216000000, 216, 12, 1, 4},
+        { 13000000, 216000000, 216, 13, 1, 4},
+        { 19200000, 216000000, 135, 12, 1, 3},
+        { 26000000, 216000000, 216, 26, 1, 4},
+
+        { 12000000, 594000000, 594, 12, 1, 8},
+        { 13000000, 594000000, 594, 13, 1, 8},
+        { 19200000, 594000000, 495, 16, 1, 8},
+        { 26000000, 594000000, 594, 26, 1, 8},
+
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+                1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+                1000, tegra_pll_ops, 0, clk_m);
+
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
+                tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+        { 12000000, 480000000, 960, 12, 2, 0},
+        { 13000000, 480000000, 960, 13, 2, 0},
+        { 19200000, 480000000, 200, 4,  2, 0},
+        { 26000000, 480000000, 960, 26, 2, 0},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
+                48000000, 960000000, tegra_pll_u_freq_table, 1000,
+                tegra_pll_ops, 0, clk_m);
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+        /* 1 GHz */
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+
+        /* 912 MHz */
+        { 12000000, 912000000,  912,  12, 1, 12},
+        { 13000000, 912000000,  912,  13, 1, 12},
+        { 19200000, 912000000,  760,  16, 1, 8},
+        { 26000000, 912000000,  912,  26, 1, 12},
+
+        /* 816 MHz */
+        { 12000000, 816000000,  816,  12, 1, 12},
+        { 13000000, 816000000,  816,  13, 1, 12},
+        { 19200000, 816000000,  680,  16, 1, 8},
+        { 26000000, 816000000,  816,  26, 1, 12},
+
+        /* 760 MHz */
+        { 12000000, 760000000,  760,  12, 1, 12},
+        { 13000000, 760000000,  760,  13, 1, 12},
+        { 19200000, 760000000,  950,  24, 1, 8},
+        { 26000000, 760000000,  760,  26, 1, 12},
+
+        /* 750 MHz */
+        { 12000000, 750000000,  750,  12, 1, 12},
+        { 13000000, 750000000,  750,  13, 1, 12},
+        { 19200000, 750000000,  625,  16, 1, 8},
+        { 26000000, 750000000,  750,  26, 1, 12},
+
+        /* 608 MHz */
+        { 12000000, 608000000,  608,  12, 1, 12},
+        { 13000000, 608000000,  608,  13, 1, 12},
+        { 19200000, 608000000,  380,  12, 1, 8},
+        { 26000000, 608000000,  608,  26, 1, 12},
+
+        /* 456 MHz */
+        { 12000000, 456000000,  456,  12, 1, 12},
+        { 13000000, 456000000,  456,  13, 1, 12},
+        { 19200000, 456000000,  380,  16, 1, 8},
+        { 26000000, 456000000,  456,  26, 1, 12},
+
+        /* 312 MHz */
+        { 12000000, 312000000,  312,  12, 1, 12},
+        { 13000000, 312000000,  312,  13, 1, 12},
+        { 19200000, 312000000,  260,  16, 1, 8},
+        { 26000000, 312000000,  312,  26, 1, 12},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
+                31000000, 1000000, 6000000, 20000000, 1200000000,
+                tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+        { 12000000, 100000000,  200,  24, 1, 0 },
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
+                0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
+
+static const char *tegra_common_parent_names[] = {
+        "clk_m",
+};
+
+static struct clk *tegra_common_parents[] = {
+        &tegra_clk_m,
+};
+
+static struct clk tegra_clk_d;
+static struct clk_tegra tegra_clk_d_hw = {
+        .hw = {
+                .clk = &tegra_clk_d,
+        },
+        .flags = PERIPH_NO_RESET,
+        .reg = 0x34,
+        .reg_shift = 12,
+        .max_rate = 52000000,
+        .u.periph = {
+                .clk_num = 90,
+        },
+};
+
+static struct clk tegra_clk_d = {
+        .name = "clk_d",
+        .hw = &tegra_clk_d_hw.hw,
+        .ops = &tegra_clk_double_ops,
+        .parent = &tegra_clk_m,
+        .parent_names = tegra_common_parent_names,
+        .parents = tegra_common_parents,
+        .num_parents = ARRAY_SIZE(tegra_common_parent_names),
+};
+
+static struct clk tegra_cdev1;
+static struct clk_tegra tegra_cdev1_hw = {
+        .hw = {
+                .clk = &tegra_cdev1,
+        },
+        .fixed_rate = 26000000,
+        .u.periph = {
+                .clk_num = 94,
+        },
+};
+static struct clk tegra_cdev1 = {
+        .name = "cdev1",
+        .hw = &tegra_cdev1_hw.hw,
+        .ops = &tegra_cdev_clk_ops,
+        .flags = CLK_IS_ROOT,
+};
+
+/* dap_mclk2, belongs to the cdev2 pingroup. */
+static struct clk tegra_cdev2;
+static struct clk_tegra tegra_cdev2_hw = {
+        .hw = {
+                .clk = &tegra_cdev2,
+        },
+        .fixed_rate = 26000000,
+        .u.periph = {
+                .clk_num  = 93,
+        },
+};
+static struct clk tegra_cdev2 = {
+        .name = "cdev2",
+        .hw = &tegra_cdev2_hw.hw,
+        .ops = &tegra_cdev_clk_ops,
+        .flags = CLK_IS_ROOT,
+};
+
+/* initialized before peripheral clocks */
+static struct clk_mux_sel mux_audio_sync_clk[8+1];
+static const struct audio_sources {
+        const char *name;
+        int value;
+} mux_audio_sync_clk_sources[] = {
+        { .name = "spdif_in", .value = 0 },
+        { .name = "i2s1", .value = 1 },
+        { .name = "i2s2", .value = 2 },
+        { .name = "pll_a_out0", .value = 4 },
+#if 0 /* FIXME: not implemented */
+        { .name = "ac97", .value = 3 },
+        { .name = "ext_audio_clk2", .value = 5 },
+        { .name = "ext_audio_clk1", .value = 6 },
+        { .name = "ext_vimclk", .value = 7 },
+#endif
+        { NULL, 0 }
+};
+
+static const char *audio_parent_names[] = {
+        "spdif_in",
+        "i2s1",
+        "i2s2",
+        "dummy",
+        "pll_a_out0",
+        "dummy",
+        "dummy",
+        "dummy",
+};
+
+static struct clk *audio_parents[] = {
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+};
+
+static struct clk tegra_audio;
+static struct clk_tegra tegra_audio_hw = {
+        .hw = {
+                .clk = &tegra_audio,
+        },
+        .reg = 0x38,
+        .max_rate = 73728000,
+};
+DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
+                audio_parents, NULL);
+
+static const char *audio_2x_parent_names[] = {
+        "audio",
+};
+
+static struct clk *audio_2x_parents[] = {
+        &tegra_audio,
+};
+
+static struct clk tegra_audio_2x;
+static struct clk_tegra tegra_audio_2x_hw = {
+        .hw = {
+                .clk = &tegra_audio_2x,
+        },
+        .flags = PERIPH_NO_RESET,
+        .max_rate = 48000000,
+        .reg = 0x34,
+        .reg_shift = 8,
+        .u.periph = {
+                .clk_num = 89,
+        },
+};
+DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
+                audio_2x_parents, &tegra_audio);
+
+static struct clk_lookup tegra_audio_clk_lookups[] = {
+        { .con_id = "audio", .clk = &tegra_audio },
+        { .con_id = "audio_2x", .clk = &tegra_audio_2x }
+};
+
+/* This is called after peripheral clocks are initialized, as the
+ * audio_sync clock depends on some of the peripheral clocks.
+ */
+
+static void init_audio_sync_clock_mux(void)
+{
+        int i;
+        struct clk_mux_sel *sel = mux_audio_sync_clk;
+        const struct audio_sources *src = mux_audio_sync_clk_sources;
+        struct clk_lookup *lookup;
+
+        for (i = 0; src->name; i++, sel++, src++) {
+                sel->input = tegra_get_clock_by_name(src->name);
+                if (!sel->input)
+                        pr_err("%s: could not find clk %s\n", __func__,
+                                src->name);
+                audio_parents[src->value] = sel->input;
+                sel->value = src->value;
+        }
+
+        lookup = tegra_audio_clk_lookups;
+        for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
+                struct clk *c = lookup->clk;
+                struct clk_tegra *clk = to_clk_tegra(c->hw);
+                __clk_init(NULL, c);
+                INIT_LIST_HEAD(&clk->shared_bus_list);
+                clk->lookup.con_id = lookup->con_id;
+                clk->lookup.clk = c;
+                clkdev_add(&clk->lookup);
+                tegra_clk_add(c);
+        }
+}
+
+static const char *mux_cclk[] = {
+        "clk_m",
+        "pll_c",
+        "clk_32k",
+        "pll_m",
+        "pll_p",
+        "pll_p_out4",
+        "pll_p_out3",
+        "clk_d",
+        "pll_x",
+};
+
+
+static struct clk *mux_cclk_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c,
+        &tegra_clk_32k,
+        &tegra_pll_m,
+        &tegra_pll_p,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        &tegra_clk_d,
+        &tegra_pll_x,
+};
+
+static const char *mux_sclk[] = {
+        "clk_m",
+        "pll_c_out1",
+        "pll_p_out4",
+        "pllp_p_out3",
+        "pll_p_out2",
+        "clk_d",
+        "clk_32k",
+        "pll_m_out1",
+};
+
+static struct clk *mux_sclk_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c_out1,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out2,
+        &tegra_clk_d,
+        &tegra_clk_32k,
+        &tegra_pll_m_out1,
+};
+
+static struct clk tegra_cclk;
+static struct clk_tegra tegra_cclk_hw = {
+        .hw = {
+                .clk = &tegra_cclk,
+        },
+        .reg = 0x20,
+        .max_rate = 1000000000,
+};
+DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
+                mux_cclk_p, NULL);
+
+static const char *mux_twd[] = {
+        "cclk",
+};
+
+static struct clk *mux_twd_p[] = {
+        &tegra_cclk,
+};
+
+static struct clk tegra_clk_twd;
+static struct clk_tegra tegra_clk_twd_hw = {
+        .hw = {
+                .clk = &tegra_clk_twd,
+        },
+        .max_rate = 1000000000,
+        .mul = 1,
+        .div = 4,
+};
+
+static struct clk tegra_clk_twd = {
+        .name = "twd",
+        .ops = &tegra_twd_ops,
+        .hw = &tegra_clk_twd_hw.hw,
+        .parent = &tegra_cclk,
+        .parent_names = mux_twd,
+        .parents = mux_twd_p,
+        .num_parents = ARRAY_SIZE(mux_twd),
+};
+
+static struct clk tegra_sclk;
+static struct clk_tegra tegra_sclk_hw = {
+        .hw = {
+                .clk = &tegra_sclk,
+        },
+        .reg = 0x28,
+        .max_rate = 240000000,
+        .min_rate = 120000000,
+};
+DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
+                mux_sclk_p, NULL);
+
+static const char *tegra_cop_parent_names[] = {
+        "tegra_sclk",
+};
+
+static struct clk *tegra_cop_parents[] = {
+        &tegra_sclk,
+};
+
+static struct clk tegra_cop;
+static struct clk_tegra tegra_cop_hw = {
+        .hw = {
+                .clk = &tegra_cop,
+        },
+        .max_rate  = 240000000,
+        .reset = &tegra2_cop_clk_reset,
+};
+DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
+                tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
+
+static const char *tegra_hclk_parent_names[] = {
+        "tegra_sclk",
+};
+
+static struct clk *tegra_hclk_parents[] = {
+        &tegra_sclk,
+};
+
+static struct clk tegra_hclk;
+static struct clk_tegra tegra_hclk_hw = {
+        .hw = {
+                .clk = &tegra_hclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 4,
+        .max_rate = 240000000,
+};
+DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
+                tegra_hclk_parents, &tegra_sclk);
+
+static const char *tegra_pclk_parent_names[] = {
+        "tegra_hclk",
+};
+
+static struct clk *tegra_pclk_parents[] = {
+        &tegra_hclk,
+};
+
+static struct clk tegra_pclk;
+static struct clk_tegra tegra_pclk_hw = {
+        .hw = {
+                .clk = &tegra_pclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 0,
+        .max_rate = 120000000,
+};
+DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
+                tegra_pclk_parents, &tegra_hclk);
+
+static const char *tegra_blink_parent_names[] = {
+        "clk_32k",
+};
+
+static struct clk *tegra_blink_parents[] = {
+        &tegra_clk_32k,
+};
+
+static struct clk tegra_blink;
+static struct clk_tegra tegra_blink_hw = {
+        .hw = {
+                .clk = &tegra_blink,
+        },
+        .reg = 0x40,
+        .max_rate = 32768,
+};
+DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
+                tegra_blink_parents, &tegra_clk_32k);
+
+static const char *mux_pllm_pllc_pllp_plla[] = {
+        "pll_m",
+        "pll_c",
+        "pll_p",
+        "pll_a_out0",
+};
+
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+        &tegra_pll_m,
+        &tegra_pll_c,
+        &tegra_pll_p,
+        &tegra_pll_a_out0,
+};
+
+static const char *mux_pllm_pllc_pllp_clkm[] = {
+        "pll_m",
+        "pll_c",
+        "pll_p",
+        "clk_m",
+};
+
+static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
+        &tegra_pll_m,
+        &tegra_pll_c,
+        &tegra_pll_p,
+        &tegra_clk_m,
+};
+
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m",
+        "clk_m",
+};
+
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+        &tegra_clk_m,
+};
+
+static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
+        "pll_a_out0",
+        "audio_2x",
+        "pll_p",
+        "clk_m",
+};
+
+static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
+        &tegra_pll_a_out0,
+        &tegra_audio_2x,
+        &tegra_pll_p,
+        &tegra_clk_m,
+};
+
+static const char *mux_pllp_plld_pllc_clkm[] = {
+        "pllp",
+        "pll_d_out0",
+        "pll_c",
+        "clk_m",
+};
+
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_d_out0,
+        &tegra_pll_c,
+        &tegra_clk_m,
+};
+
+static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
+        "pll_p",
+        "pll_c",
+        "audio",
+        "clk_m",
+        "clk_32k",
+};
+
+static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_audio,
+        &tegra_clk_m,
+        &tegra_clk_32k,
+};
+
+static const char *mux_pllp_pllc_pllm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m"
+};
+
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+};
+
+static const char *mux_clk_m[] = {
+        "clk_m",
+};
+
+static struct clk *mux_clk_m_p[] = {
+        &tegra_clk_m,
+};
+
+static const char *mux_pllp_out3[] = {
+        "pll_p_out3",
+};
+
+static struct clk *mux_pllp_out3_p[] = {
+        &tegra_pll_p_out3,
+};
+
+static const char *mux_plld[] = {
+        "pll_d",
+};
+
+static struct clk *mux_plld_p[] = {
+        &tegra_pll_d,
+};
+
+static const char *mux_clk_32k[] = {
+        "clk_32k",
+};
+
+static struct clk *mux_clk_32k_p[] = {
+        &tegra_clk_32k,
+};
+
+static const char *mux_pclk[] = {
+        "pclk",
+};
+
+static struct clk *mux_pclk_p[] = {
+        &tegra_pclk,
+};
+
+static struct clk tegra_emc;
+static struct clk_tegra tegra_emc_hw = {
+        .hw = {
+                .clk = &tegra_emc,
+        },
+        .reg = 0x19c,
+        .max_rate = 800000000,
+        .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
+        .reset = &tegra2_periph_clk_reset,
+        .u.periph = {
+                .clk_num = 57,
+        },
+};
+DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
+                mux_pllm_pllc_pllp_clkm_p, NULL);
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,   \
+                _max, _inputs, _flags)                  \
+        static struct clk tegra_##_name;                \
+        static struct clk_tegra tegra_##_name##_hw = {  \
+                .hw = {                                 \
+                        .clk = &tegra_##_name,          \
+                },                                      \
+                .lookup = {                             \
+                        .dev_id = _dev,                 \
+                        .con_id = _con,                 \
+                },                                      \
+                .reg = _reg,                            \
+                .flags = _flags,                        \
+                .max_rate = _max,                       \
+                .u.periph = {                           \
+                        .clk_num = _clk_num,            \
+                },                                      \
+                .reset = tegra2_periph_clk_reset,       \
+        };                                              \
+        static struct clk tegra_##_name = {             \
+                .name = #_name,                         \
+                .ops = &tegra_periph_clk_ops,           \
+                .hw = &tegra_##_name##_hw.hw,           \
+                .parent_names = _inputs,                \
+                .parents = _inputs##_p,                 \
+                .num_parents = ARRAY_SIZE(_inputs),     \
+        };
+
+PERIPH_CLK(apbdma,      "tegra-apbdma",         NULL,   34,     0,      108000000, mux_pclk,                    0);
+PERIPH_CLK(rtc,         "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET);
+PERIPH_CLK(timer,       "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(i2s1,        "tegra20-i2s.0",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
+PERIPH_CLK(i2s2,        "tegra20-i2s.1",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
+PERIPH_CLK(spdif_out,   "spdif_out",            NULL,   10,     0x108,  100000000, mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
+PERIPH_CLK(spdif_in,    "spdif_in",             NULL,   10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71);
+PERIPH_CLK(pwm,         "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71 | MUX_PWM);
+PERIPH_CLK(spi,         "spi",                  NULL,   43,     0x114,  40000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(xio,         "xio",                  NULL,   45,     0x120,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(twc,         "twc",                  NULL,   16,     0x12c,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc1,        "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc2,        "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc3,        "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc4,        "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(ide,         "ide",                  NULL,   25,     0x144,  100000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(ndflash,     "tegra_nand",           NULL,   13,     0x160,  164000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vfir,        "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sdmmc1,      "sdhci-tegra.0",        NULL,   14,     0x150,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2,      "sdhci-tegra.1",        NULL,   9,      0x154,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3,      "sdhci-tegra.2",        NULL,   69,     0x1bc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4,      "sdhci-tegra.3",        NULL,   15,     0x164,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp,         "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsea,        "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsev,        "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(vde,         "tegra-avp",            "vde",  61,     0x1c8,  250000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(csite,       "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* max rate ??? */
+/* FIXME: what is la? */
+PERIPH_CLK(la,          "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  92000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(i2c1,        "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c2,        "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c3,        "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(dvc,         "tegra-i2c.3",          NULL,   47,     0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c1_i2c,    "tegra-i2c.0",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
+PERIPH_CLK(i2c2_i2c,    "tegra-i2c.1",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
+PERIPH_CLK(i2c3_i2c,    "tegra-i2c.2",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
+PERIPH_CLK(dvc_i2c,     "tegra-i2c.3",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
+PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uartd,       "tegra-uart.3",         NULL,   65,     0x1c0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uarte,       "tegra-uart.4",         NULL,   66,     0x1c4,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(3d,          "3d",                   NULL,   24,     0x158,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(2d,          "2d",                   NULL,   21,     0x15c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi,          "tegra_camera",         "vi",   20,     0x148,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi_sensor,   "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(epp,         "epp",                  NULL,   19,     0x16c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(mpe,         "mpe",                  NULL,   60,     0x170,  250000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(host1x,      "host1x",               NULL,   28,     0x180,  166000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(cve,         "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo,         "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(hdmi,        "hdmi",                 NULL,   51,     0x18c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvdac,       "tvdac",                NULL,   53,     0x194,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1,       "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX); /* scales with voltage and process_id */
+PERIPH_CLK(disp2,       "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX); /* scales with voltage and process_id */
+PERIPH_CLK(usbd,        "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb2,        "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb3,        "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(dsi,         "dsi",                  NULL,   48,     0,      500000000, mux_plld,                    0); /* scales with voltage */
+PERIPH_CLK(csi,         "tegra_camera",         "csi",  52,     0,      72000000,  mux_pllp_out3,               0);
+PERIPH_CLK(isp,         "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0); /* same frequency as VI */
+PERIPH_CLK(csus,        "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET);
+PERIPH_CLK(pex,         NULL,                   "pex",  70,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
+PERIPH_CLK(afi,         NULL,                   "afi",  72,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
+PERIPH_CLK(pcie_xclk,   NULL,             "pcie_xclk",  74,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
+
+static struct clk *tegra_list_clks[] = {
+        &tegra_apbdma,
+        &tegra_rtc,
+        &tegra_i2s1,
+        &tegra_i2s2,
+        &tegra_spdif_out,
+        &tegra_spdif_in,
+        &tegra_pwm,
+        &tegra_spi,
+        &tegra_xio,
+        &tegra_twc,
+        &tegra_sbc1,
+        &tegra_sbc2,
+        &tegra_sbc3,
+        &tegra_sbc4,
+        &tegra_ide,
+        &tegra_ndflash,
+        &tegra_vfir,
+        &tegra_sdmmc1,
+        &tegra_sdmmc2,
+        &tegra_sdmmc3,
+        &tegra_sdmmc4,
+        &tegra_vcp,
+        &tegra_bsea,
+        &tegra_bsev,
+        &tegra_vde,
+        &tegra_csite,
+        &tegra_la,
+        &tegra_owr,
+        &tegra_nor,
+        &tegra_mipi,
+        &tegra_i2c1,
+        &tegra_i2c2,
+        &tegra_i2c3,
+        &tegra_dvc,
+        &tegra_i2c1_i2c,
+        &tegra_i2c2_i2c,
+        &tegra_i2c3_i2c,
+        &tegra_dvc_i2c,
+        &tegra_uarta,
+        &tegra_uartb,
+        &tegra_uartc,
+        &tegra_uartd,
+        &tegra_uarte,
+        &tegra_3d,
+        &tegra_2d,
+        &tegra_vi,
+        &tegra_vi_sensor,
+        &tegra_epp,
+        &tegra_mpe,
+        &tegra_host1x,
+        &tegra_cve,
+        &tegra_tvo,
+        &tegra_hdmi,
+        &tegra_tvdac,
+        &tegra_disp1,
+        &tegra_disp2,
+        &tegra_usbd,
+        &tegra_usb2,
+        &tegra_usb3,
+        &tegra_dsi,
+        &tegra_csi,
+        &tegra_isp,
+        &tegra_csus,
+        &tegra_pex,
+        &tegra_afi,
+        &tegra_pcie_xclk,
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)        \
+        {                                       \
+                .name   = _name,                \
+                .lookup = {                     \
+                        .dev_id = _dev,         \
+                        .con_id = _con,         \
+                },                              \
+        }
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+static struct clk_duplicate tegra_clk_duplicates[] = {
+        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
+        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
+        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
+        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
+        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
+        CLK_DUPLICATE("usbd",   "utmip-pad",    NULL),
+        CLK_DUPLICATE("usbd",   "tegra-ehci.0", NULL),
+        CLK_DUPLICATE("usbd",   "tegra-otg",    NULL),
+        CLK_DUPLICATE("hdmi",   "tegradc.0",    "hdmi"),
+        CLK_DUPLICATE("hdmi",   "tegradc.1",    "hdmi"),
+        CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
+        CLK_DUPLICATE("2d",     "tegra_grhost", "gr2d"),
+        CLK_DUPLICATE("3d",     "tegra_grhost", "gr3d"),
+        CLK_DUPLICATE("epp",    "tegra_grhost", "epp"),
+        CLK_DUPLICATE("mpe",    "tegra_grhost", "mpe"),
+        CLK_DUPLICATE("cop",    "tegra-avp",    "cop"),
+        CLK_DUPLICATE("vde",    "tegra-aes",    "vde"),
+        CLK_DUPLICATE("cclk",   NULL,           "cpu"),
+        CLK_DUPLICATE("twd",    "smp_twd",      NULL),
+};
+
+#define CLK(dev, con, ck)       \
+        {                       \
+                .dev_id = dev,  \
+                .con_id = con,  \
+                .clk    = ck,   \
+        }
+
+static struct clk *tegra_ptr_clks[] = {
+        &tegra_clk_32k,
+        &tegra_pll_s,
+        &tegra_clk_m,
+        &tegra_pll_m,
+        &tegra_pll_m_out1,
+        &tegra_pll_c,
+        &tegra_pll_c_out1,
+        &tegra_pll_p,
+        &tegra_pll_p_out1,
+        &tegra_pll_p_out2,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out4,
+        &tegra_pll_a,
+        &tegra_pll_a_out0,
+        &tegra_pll_d,
+        &tegra_pll_d_out0,
+        &tegra_pll_u,
+        &tegra_pll_x,
+        &tegra_pll_e,
+        &tegra_cclk,
+        &tegra_clk_twd,
+        &tegra_sclk,
+        &tegra_hclk,
+        &tegra_pclk,
+        &tegra_clk_d,
+        &tegra_cdev1,
+        &tegra_cdev2,
+        &tegra_blink,
+        &tegra_cop,
+        &tegra_emc,
+};
+
+static void tegra2_init_one_clock(struct clk *c)
+{
+        struct clk_tegra *clk = to_clk_tegra(c->hw);
+        int ret;
+
+        ret = __clk_init(NULL, c);
+        if (ret)
+                pr_err("clk init failed %s\n", __clk_get_name(c));
+
+        INIT_LIST_HEAD(&clk->shared_bus_list);
+        if (!clk->lookup.dev_id && !clk->lookup.con_id)
+                clk->lookup.con_id = c->name;
+        clk->lookup.clk = c;
+        clkdev_add(&clk->lookup);
+        tegra_clk_add(c);
+}
+
+void __init tegra2_init_clocks(void)
+{
+        int i;
+        struct clk *c;
+
+        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+                tegra2_init_one_clock(tegra_ptr_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+                tegra2_init_one_clock(tegra_list_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+                if (!c) {
+                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                                tegra_clk_duplicates[i].name);
+                        continue;
+                }
+
+                tegra_clk_duplicates[i].lookup.clk = c;
+                clkdev_add(&tegra_clk_duplicates[i].lookup);
+        }
+
+        init_audio_sync_clock_mux();
+        tegra20_cpu_car_ops_init();
+}
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
deleted file mode 100644
index a703844b2061..000000000000
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ /dev/null
@@ -1,2484 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra2_clocks.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
-#include "clock.h"
-#include "fuse.h"
-#include "tegra2_emc.h"
-
-#define RST_DEVICES                     0x004
-#define RST_DEVICES_SET                 0x300
-#define RST_DEVICES_CLR                 0x304
-#define RST_DEVICES_NUM                 3
-
-#define CLK_OUT_ENB                     0x010
-#define CLK_OUT_ENB_SET                 0x320
-#define CLK_OUT_ENB_CLR                 0x324
-#define CLK_OUT_ENB_NUM                 3
-
-#define CLK_MASK_ARM                    0x44
-#define MISC_CLK_ENB                    0x48
-
-#define OSC_CTRL                        0x50
-#define OSC_CTRL_OSC_FREQ_MASK          (3<<30)
-#define OSC_CTRL_OSC_FREQ_13MHZ         (0<<30)
-#define OSC_CTRL_OSC_FREQ_19_2MHZ       (1<<30)
-#define OSC_CTRL_OSC_FREQ_12MHZ         (2<<30)
-#define OSC_CTRL_OSC_FREQ_26MHZ         (3<<30)
-#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
-
-#define OSC_FREQ_DET                    0x58
-#define OSC_FREQ_DET_TRIG               (1<<31)
-
-#define OSC_FREQ_DET_STATUS             0x5C
-#define OSC_FREQ_DET_BUSY               (1<<31)
-#define OSC_FREQ_DET_CNT_MASK           0xFFFF
-
-#define PERIPH_CLK_SOURCE_I2S1          0x100
-#define PERIPH_CLK_SOURCE_EMC           0x19c
-#define PERIPH_CLK_SOURCE_OSC           0x1fc
-#define PERIPH_CLK_SOURCE_NUM \
-        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
-
-#define PERIPH_CLK_SOURCE_MASK          (3<<30)
-#define PERIPH_CLK_SOURCE_SHIFT         30
-#define PERIPH_CLK_SOURCE_PWM_MASK      (7<<28)
-#define PERIPH_CLK_SOURCE_PWM_SHIFT     28
-#define PERIPH_CLK_SOURCE_ENABLE        (1<<28)
-#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
-#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
-#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
-
-#define SDMMC_CLK_INT_FB_SEL            (1 << 23)
-#define SDMMC_CLK_INT_FB_DLY_SHIFT      16
-#define SDMMC_CLK_INT_FB_DLY_MASK       (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
-
-#define PLL_BASE                        0x0
-#define PLL_BASE_BYPASS                 (1<<31)
-#define PLL_BASE_ENABLE                 (1<<30)
-#define PLL_BASE_REF_ENABLE             (1<<29)
-#define PLL_BASE_OVERRIDE               (1<<28)
-#define PLL_BASE_DIVP_MASK              (0x7<<20)
-#define PLL_BASE_DIVP_SHIFT             20
-#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
-#define PLL_BASE_DIVN_SHIFT             8
-#define PLL_BASE_DIVM_MASK              (0x1F)
-#define PLL_BASE_DIVM_SHIFT             0
-
-#define PLL_OUT_RATIO_MASK              (0xFF<<8)
-#define PLL_OUT_RATIO_SHIFT             8
-#define PLL_OUT_OVERRIDE                (1<<2)
-#define PLL_OUT_CLKEN                   (1<<1)
-#define PLL_OUT_RESET_DISABLE           (1<<0)
-
-#define PLL_MISC(c)                     (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
-
-#define PLL_MISC_DCCON_SHIFT            20
-#define PLL_MISC_CPCON_SHIFT            8
-#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
-#define PLL_MISC_LFCON_SHIFT            4
-#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
-#define PLL_MISC_VCOCON_SHIFT           0
-#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
-
-#define PLLU_BASE_POST_DIV              (1<<20)
-
-#define PLLD_MISC_CLKENABLE             (1<<30)
-#define PLLD_MISC_DIV_RST               (1<<23)
-#define PLLD_MISC_DCCON_SHIFT           12
-
-#define PLLE_MISC_READY                 (1 << 15)
-
-#define PERIPH_CLK_TO_ENB_REG(c)        ((c->u.periph.clk_num / 32) * 4)
-#define PERIPH_CLK_TO_ENB_SET_REG(c)    ((c->u.periph.clk_num / 32) * 8)
-#define PERIPH_CLK_TO_ENB_BIT(c)        (1 << (c->u.periph.clk_num % 32))
-
-#define SUPER_CLK_MUX                   0x00
-#define SUPER_STATE_SHIFT               28
-#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
-#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
-#define SUPER_SOURCE_MASK               0xF
-#define SUPER_FIQ_SOURCE_SHIFT          12
-#define SUPER_IRQ_SOURCE_SHIFT          8
-#define SUPER_RUN_SOURCE_SHIFT          4
-#define SUPER_IDLE_SOURCE_SHIFT         0
-
-#define SUPER_CLK_DIVIDER               0x04
-
-#define BUS_CLK_DISABLE                 (1<<3)
-#define BUS_CLK_DIV_MASK                0x3
-
-#define PMC_CTRL                        0x0
- #define PMC_CTRL_BLINK_ENB             (1 << 7)
-
-#define PMC_DPD_PADS_ORIDE              0x1c
- #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
-
-#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
-#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
-#define PMC_BLINK_TIMER_ENB             (1 << 15)
-#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
-#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
-
-static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
-static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-
-/*
- * Some clocks share a register with other clocks.  Any clock op that
- * non-atomically modifies a register used by another clock must lock
- * clock_register_lock first.
- */
-static DEFINE_SPINLOCK(clock_register_lock);
-
-/*
- * Some peripheral clocks share an enable bit, so refcount the enable bits
- * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
- */
-static int tegra_periph_clk_enable_refcount[3 * 32];
-
-#define clk_writel(value, reg) \
-        __raw_writel(value, reg_clk_base + (reg))
-#define clk_readl(reg) \
-        __raw_readl(reg_clk_base + (reg))
-#define pmc_writel(value, reg) \
-        __raw_writel(value, reg_pmc_base + (reg))
-#define pmc_readl(reg) \
-        __raw_readl(reg_pmc_base + (reg))
-
-static unsigned long clk_measure_input_freq(void)
-{
-        u32 clock_autodetect;
-        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
-        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
-        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
-        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
-                return 12000000;
-        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
-                return 13000000;
-        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
-                return 19200000;
-        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
-                return 26000000;
-        } else {
-                pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
-                BUG();
-                return 0;
-        }
-}
-
-static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
-{
-        s64 divider_u71 = parent_rate * 2;
-        divider_u71 += rate - 1;
-        do_div(divider_u71, rate);
-
-        if (divider_u71 - 2 < 0)
-                return 0;
-
-        if (divider_u71 - 2 > 255)
-                return -EINVAL;
-
-        return divider_u71 - 2;
-}
-
-static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
-{
-        s64 divider_u16;
-
-        divider_u16 = parent_rate;
-        divider_u16 += rate - 1;
-        do_div(divider_u16, rate);
-
-        if (divider_u16 - 1 < 0)
-                return 0;
-
-        if (divider_u16 - 1 > 255)
-                return -EINVAL;
-
-        return divider_u16 - 1;
-}
-
-/* clk_m functions */
-static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
-{
-        u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
-
-        c->rate = clk_measure_input_freq();
-        switch (c->rate) {
-        case 12000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
-                break;
-        case 13000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
-                break;
-        case 19200000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
-                break;
-        case 26000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
-                break;
-        default:
-                pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
-                BUG();
-        }
-        clk_writel(auto_clock_control, OSC_CTRL);
-        return c->rate;
-}
-
-static void tegra2_clk_m_init(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        tegra2_clk_m_autodetect_rate(c);
-}
-
-static int tegra2_clk_m_enable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        return 0;
-}
-
-static void tegra2_clk_m_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        BUG();
-}
-
-static struct clk_ops tegra_clk_m_ops = {
-        .init           = tegra2_clk_m_init,
-        .enable         = tegra2_clk_m_enable,
-        .disable        = tegra2_clk_m_disable,
-};
-
-/* super clock functions */
-/* "super clocks" on tegra have two-stage muxes and a clock skipping
- * super divider.  We will ignore the clock skipping divider, since we
- * can't lower the voltage when using the clock skip, but we can if we
- * lower the PLL frequency.
- */
-static void tegra2_super_clk_init(struct clk *c)
-{
-        u32 val;
-        int source;
-        int shift;
-        const struct clk_mux_sel *sel;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        c->state = ON;
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        source = (val >> shift) & SUPER_SOURCE_MASK;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->value == source)
-                        break;
-        }
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
-}
-
-static int tegra2_super_clk_enable(struct clk *c)
-{
-        clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
-        return 0;
-}
-
-static void tegra2_super_clk_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        /* oops - don't disable the CPU clock! */
-        BUG();
-}
-
-static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
-{
-        u32 val;
-        const struct clk_mux_sel *sel;
-        int shift;
-
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val &= ~(SUPER_SOURCE_MASK << shift);
-                        val |= sel->value << shift;
-
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        clk_writel(val, c->reg);
-
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-
-/*
- * Super clocks have "clock skippers" instead of dividers.  Dividing using
- * a clock skipper does not allow the voltage to be scaled down, so instead
- * adjust the rate of the parent clock.  This requires that the parent of a
- * super clock have no other children, otherwise the rate will change
- * underneath the other children.
- */
-static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        return clk_set_rate(c->parent, rate);
-}
-
-static struct clk_ops tegra_super_ops = {
-        .init                   = tegra2_super_clk_init,
-        .enable                 = tegra2_super_clk_enable,
-        .disable                = tegra2_super_clk_disable,
-        .set_parent             = tegra2_super_clk_set_parent,
-        .set_rate               = tegra2_super_clk_set_rate,
-};
-
-/* virtual cpu clock functions */
-/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
-   To change the frequency of these clocks, the parent pll may need to be
-   reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
-   and then the clock moved back to the pll.  To hide this sequence, a virtual
-   clock handles it.
- */
-static void tegra2_cpu_clk_init(struct clk *c)
-{
-}
-
-static int tegra2_cpu_clk_enable(struct clk *c)
-{
-        return 0;
-}
-
-static void tegra2_cpu_clk_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        /* oops - don't disable the CPU clock! */
-        BUG();
-}
-
-static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        int ret;
-        /*
-         * Take an extra reference to the main pll so it doesn't turn
-         * off when we move the cpu off of it
-         */
-        clk_enable(c->u.cpu.main);
-
-        ret = clk_set_parent(c->parent, c->u.cpu.backup);
-        if (ret) {
-                pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
-                goto out;
-        }
-
-        if (rate == clk_get_rate(c->u.cpu.backup))
-                goto out;
-
-        ret = clk_set_rate(c->u.cpu.main, rate);
-        if (ret) {
-                pr_err("Failed to change cpu pll to %lu\n", rate);
-                goto out;
-        }
-
-        ret = clk_set_parent(c->parent, c->u.cpu.main);
-        if (ret) {
-                pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
-                goto out;
-        }
-
-out:
-        clk_disable(c->u.cpu.main);
-        return ret;
-}
-
-static struct clk_ops tegra_cpu_ops = {
-        .init     = tegra2_cpu_clk_init,
-        .enable   = tegra2_cpu_clk_enable,
-        .disable  = tegra2_cpu_clk_disable,
-        .set_rate = tegra2_cpu_clk_set_rate,
-};
-
-/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
- * reset the COP block (i.e. AVP) */
-static void tegra2_cop_clk_reset(struct clk *c, bool assert)
-{
-        unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-
-        pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
-        clk_writel(1 << 1, reg);
-}
-
-static struct clk_ops tegra_cop_ops = {
-        .reset    = tegra2_cop_clk_reset,
-};
-
-/* bus clock functions */
-static void tegra2_bus_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg);
-        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
-        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
-        c->mul = 1;
-}
-
-static int tegra2_bus_clk_enable(struct clk *c)
-{
-        u32 val;
-        unsigned long flags;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        val = clk_readl(c->reg);
-        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
-        clk_writel(val, c->reg);
-
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-
-        return 0;
-}
-
-static void tegra2_bus_clk_disable(struct clk *c)
-{
-        u32 val;
-        unsigned long flags;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        val = clk_readl(c->reg);
-        val |= BUS_CLK_DISABLE << c->reg_shift;
-        clk_writel(val, c->reg);
-
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-
-static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        unsigned long flags;
-        int ret = -EINVAL;
-        int i;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        val = clk_readl(c->reg);
-        for (i = 1; i <= 4; i++) {
-                if (rate == parent_rate / i) {
-                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
-                        val |= (i - 1) << c->reg_shift;
-                        clk_writel(val, c->reg);
-                        c->div = i;
-                        c->mul = 1;
-                        ret = 0;
-                        break;
-                }
-        }
-
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-
-        return ret;
-}
-
-static struct clk_ops tegra_bus_ops = {
-        .init                   = tegra2_bus_clk_init,
-        .enable                 = tegra2_bus_clk_enable,
-        .disable                = tegra2_bus_clk_disable,
-        .set_rate               = tegra2_bus_clk_set_rate,
-};
-
-/* Blink output functions */
-
-static void tegra2_blink_clk_init(struct clk *c)
-{
-        u32 val;
-
-        val = pmc_readl(PMC_CTRL);
-        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
-        c->mul = 1;
-        val = pmc_readl(c->reg);
-
-        if (val & PMC_BLINK_TIMER_ENB) {
-                unsigned int on_off;
-
-                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
-                        PMC_BLINK_TIMER_DATA_ON_MASK;
-                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off += val;
-                /* each tick in the blink timer is 4 32KHz clocks */
-                c->div = on_off * 4;
-        } else {
-                c->div = 1;
-        }
-}
-
-static int tegra2_blink_clk_enable(struct clk *c)
-{
-        u32 val;
-
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
-
-        return 0;
-}
-
-static void tegra2_blink_clk_disable(struct clk *c)
-{
-        u32 val;
-
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
-
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-}
-
-static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        if (rate >= parent_rate) {
-                c->div = 1;
-                pmc_writel(0, c->reg);
-        } else {
-                unsigned int on_off;
-                u32 val;
-
-                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
-                c->div = on_off * 8;
-
-                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
-                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
-                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val |= on_off;
-                val |= PMC_BLINK_TIMER_ENB;
-                pmc_writel(val, c->reg);
-        }
-
-        return 0;
-}
-
-static struct clk_ops tegra_blink_clk_ops = {
-        .init                   = &tegra2_blink_clk_init,
-        .enable                 = &tegra2_blink_clk_enable,
-        .disable                = &tegra2_blink_clk_disable,
-        .set_rate               = &tegra2_blink_clk_set_rate,
-};
-
-/* PLL Functions */
-static int tegra2_pll_clk_wait_for_lock(struct clk *c)
-{
-        udelay(c->u.pll.lock_delay);
-
-        return 0;
-}
-
-static void tegra2_pll_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg + PLL_BASE);
-
-        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
-
-        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
-                pr_warning("Clock %s has unknown fixed frequency\n", c->name);
-                c->mul = 1;
-                c->div = 1;
-        } else if (val & PLL_BASE_BYPASS) {
-                c->mul = 1;
-                c->div = 1;
-        } else {
-                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-                if (c->flags & PLLU)
-                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
-                else
-                        c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
-        }
-}
-
-static int tegra2_pll_clk_enable(struct clk *c)
-{
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        val = clk_readl(c->reg + PLL_BASE);
-        val &= ~PLL_BASE_BYPASS;
-        val |= PLL_BASE_ENABLE;
-        clk_writel(val, c->reg + PLL_BASE);
-
-        tegra2_pll_clk_wait_for_lock(c);
-
-        return 0;
-}
-
-static void tegra2_pll_clk_disable(struct clk *c)
-{
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        val = clk_readl(c->reg);
-        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
-        clk_writel(val, c->reg);
-}
-
-static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        unsigned long input_rate;
-        const struct clk_pll_freq_table *sel;
-
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
-        input_rate = clk_get_rate(c->parent);
-        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                if (sel->input_rate == input_rate && sel->output_rate == rate) {
-                        c->mul = sel->n;
-                        c->div = sel->m * sel->p;
-
-                        val = clk_readl(c->reg + PLL_BASE);
-                        if (c->flags & PLL_FIXED)
-                                val |= PLL_BASE_OVERRIDE;
-                        val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
-                                 PLL_BASE_DIVM_MASK);
-                        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
-                                (sel->n << PLL_BASE_DIVN_SHIFT);
-                        BUG_ON(sel->p < 1 || sel->p > 2);
-                        if (c->flags & PLLU) {
-                                if (sel->p == 1)
-                                        val |= PLLU_BASE_POST_DIV;
-                        } else {
-                                if (sel->p == 2)
-                                        val |= 1 << PLL_BASE_DIVP_SHIFT;
-                        }
-                        clk_writel(val, c->reg + PLL_BASE);
-
-                        if (c->flags & PLL_HAS_CPCON) {
-                                val = clk_readl(c->reg + PLL_MISC(c));
-                                val &= ~PLL_MISC_CPCON_MASK;
-                                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
-                                clk_writel(val, c->reg + PLL_MISC(c));
-                        }
-
-                        if (c->state == ON)
-                                tegra2_pll_clk_enable(c);
-
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_pll_ops = {
-        .init                   = tegra2_pll_clk_init,
-        .enable                 = tegra2_pll_clk_enable,
-        .disable                = tegra2_pll_clk_disable,
-        .set_rate               = tegra2_pll_clk_set_rate,
-};
-
-static void tegra2_pllx_clk_init(struct clk *c)
-{
-        tegra2_pll_clk_init(c);
-
-        if (tegra_sku_id == 7)
-                c->max_rate = 750000000;
-}
-
-static struct clk_ops tegra_pllx_ops = {
-        .init     = tegra2_pllx_clk_init,
-        .enable   = tegra2_pll_clk_enable,
-        .disable  = tegra2_pll_clk_disable,
-        .set_rate = tegra2_pll_clk_set_rate,
-};
-
-static int tegra2_plle_clk_enable(struct clk *c)
-{
-        u32 val;
-
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        mdelay(1);
-
-        val = clk_readl(c->reg + PLL_BASE);
-        if (!(val & PLLE_MISC_READY))
-                return -EBUSY;
-
-        val = clk_readl(c->reg + PLL_BASE);
-        val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
-        clk_writel(val, c->reg + PLL_BASE);
-
-        return 0;
-}
-
-static struct clk_ops tegra_plle_ops = {
-        .init       = tegra2_pll_clk_init,
-        .enable     = tegra2_plle_clk_enable,
-        .set_rate   = tegra2_pll_clk_set_rate,
-};
-
-/* Clock divider ops */
-static void tegra2_pll_div_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg);
-        u32 divu71;
-        val >>= c->reg_shift;
-        c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
-        if (!(val & PLL_OUT_RESET_DISABLE))
-                c->state = OFF;
-
-        if (c->flags & DIV_U71) {
-                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
-                c->div = (divu71 + 2);
-                c->mul = 2;
-        } else if (c->flags & DIV_2) {
-                c->div = 2;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
-}
-
-static int tegra2_pll_div_clk_enable(struct clk *c)
-{
-        u32 val;
-        u32 new_val;
-        unsigned long flags;
-
-        pr_debug("%s: %s\n", __func__, c->name);
-        if (c->flags & DIV_U71) {
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-
-                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
-
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-                return 0;
-        } else if (c->flags & DIV_2) {
-                BUG_ON(!(c->flags & PLLD));
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                val &= ~PLLD_MISC_DIV_RST;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-                return 0;
-        }
-        return -EINVAL;
-}
-
-static void tegra2_pll_div_clk_disable(struct clk *c)
-{
-        u32 val;
-        u32 new_val;
-        unsigned long flags;
-
-        pr_debug("%s: %s\n", __func__, c->name);
-        if (c->flags & DIV_U71) {
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-
-                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
-
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-        } else if (c->flags & DIV_2) {
-                BUG_ON(!(c->flags & PLLD));
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                val |= PLLD_MISC_DIV_RST;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-        }
-}
-
-static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        u32 new_val;
-        int divider_u71;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        unsigned long flags;
-
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-        if (c->flags & DIV_U71) {
-                divider_u71 = clk_div71_get_divider(parent_rate, rate);
-                if (divider_u71 >= 0) {
-                        spin_lock_irqsave(&clock_register_lock, flags);
-                        val = clk_readl(c->reg);
-                        new_val = val >> c->reg_shift;
-                        new_val &= 0xFFFF;
-                        if (c->flags & DIV_U71_FIXED)
-                                new_val |= PLL_OUT_OVERRIDE;
-                        new_val &= ~PLL_OUT_RATIO_MASK;
-                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
-
-                        val &= ~(0xFFFF << c->reg_shift);
-                        val |= new_val << c->reg_shift;
-                        clk_writel(val, c->reg);
-                        c->div = divider_u71 + 2;
-                        c->mul = 2;
-                        spin_unlock_irqrestore(&clock_register_lock, flags);
-                        return 0;
-                }
-        } else if (c->flags & DIV_2) {
-                if (parent_rate == rate * 2)
-                        return 0;
-        }
-        return -EINVAL;
-}
-
-static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
-{
-        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_2) {
-                return DIV_ROUND_UP(parent_rate, 2);
-        }
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_pll_div_ops = {
-        .init                   = tegra2_pll_div_clk_init,
-        .enable                 = tegra2_pll_div_clk_enable,
-        .disable                = tegra2_pll_div_clk_disable,
-        .set_rate               = tegra2_pll_div_clk_set_rate,
-        .round_rate             = tegra2_pll_div_clk_round_rate,
-};
-
-/* Periph clk ops */
-
-static void tegra2_periph_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg);
-        const struct clk_mux_sel *mux = NULL;
-        const struct clk_mux_sel *sel;
-        u32 shift;
-        u32 mask;
-
-        if (c->flags & MUX_PWM) {
-                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
-                mask = PERIPH_CLK_SOURCE_PWM_MASK;
-        } else {
-                shift = PERIPH_CLK_SOURCE_SHIFT;
-                mask = PERIPH_CLK_SOURCE_MASK;
-        }
-
-        if (c->flags & MUX) {
-                for (sel = c->inputs; sel->input != NULL; sel++) {
-                        if ((val & mask) >> shift == sel->value)
-                                mux = sel;
-                }
-                BUG_ON(!mux);
-
-                c->parent = mux->input;
-        } else {
-                c->parent = c->inputs[0].input;
-        }
-
-        if (c->flags & DIV_U71) {
-                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-                c->div = divu71 + 2;
-                c->mul = 2;
-        } else if (c->flags & DIV_U16) {
-                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-                c->div = divu16 + 1;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
-
-        c->state = ON;
-
-        if (!c->u.periph.clk_num)
-                return;
-
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-
-        if (!(c->flags & PERIPH_NO_RESET))
-                if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
-                                PERIPH_CLK_TO_ENB_BIT(c))
-                        c->state = OFF;
-}
-
-static int tegra2_periph_clk_enable(struct clk *c)
-{
-        u32 val;
-        unsigned long flags;
-        int refcount;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        if (!c->u.periph.clk_num)
-                return 0;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
-
-        if (refcount > 1)
-                goto out;
-
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
-        if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                        RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-        if (c->flags & PERIPH_EMC_ENB) {
-                /* The EMC peripheral clock has 2 extra enable bits */
-                /* FIXME: Do they need to be disabled? */
-                val = clk_readl(c->reg);
-                val |= 0x3 << 24;
-                clk_writel(val, c->reg);
-        }
-
-out:
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-
-        return 0;
-}
-
-static void tegra2_periph_clk_disable(struct clk *c)
-{
-        unsigned long flags;
-
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        if (!c->u.periph.clk_num)
-                return;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        if (c->refcnt)
-                tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
-
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                        CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-
-static void tegra2_periph_clk_reset(struct clk *c, bool assert)
-{
-        unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-
-        pr_debug("%s %s on clock %s\n", __func__,
-                 assert ? "assert" : "deassert", c->name);
-
-        BUG_ON(!c->u.periph.clk_num);
-
-        if (!(c->flags & PERIPH_NO_RESET))
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                           base + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-
-static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
-{
-        u32 val;
-        const struct clk_mux_sel *sel;
-        u32 mask, shift;
-
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
-        if (c->flags & MUX_PWM) {
-                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
-                mask = PERIPH_CLK_SOURCE_PWM_MASK;
-        } else {
-                shift = PERIPH_CLK_SOURCE_SHIFT;
-                mask = PERIPH_CLK_SOURCE_MASK;
-        }
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~mask;
-                        val |= (sel->value) << shift;
-
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        clk_writel(val, c->reg);
-
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-
-        return -EINVAL;
-}
-
-static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
-                        val |= divider;
-                        clk_writel(val, c->reg);
-                        c->div = divider + 2;
-                        c->mul = 2;
-                        return 0;
-                }
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
-                        val |= divider;
-                        clk_writel(val, c->reg);
-                        c->div = divider + 1;
-                        c->mul = 1;
-                        return 0;
-                }
-        } else if (parent_rate <= rate) {
-                c->div = 1;
-                c->mul = 1;
-                return 0;
-        }
-        return -EINVAL;
-}
-
-static long tegra2_periph_clk_round_rate(struct clk *c,
-        unsigned long rate)
-{
-        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate, divider + 1);
-        }
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_periph_clk_ops = {
-        .init                   = &tegra2_periph_clk_init,
-        .enable                 = &tegra2_periph_clk_enable,
-        .disable                = &tegra2_periph_clk_disable,
-        .set_parent             = &tegra2_periph_clk_set_parent,
-        .set_rate               = &tegra2_periph_clk_set_rate,
-        .round_rate             = &tegra2_periph_clk_round_rate,
-        .reset                  = &tegra2_periph_clk_reset,
-};
-
-/* The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB. */
-void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
-{
-        u32 reg;
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        delay = clamp(delay, 0, 15);
-        reg = clk_readl(c->reg);
-        reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
-        reg |= SDMMC_CLK_INT_FB_SEL;
-        reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
-        clk_writel(reg, c->reg);
-
-        spin_unlock_irqrestore(&c->spinlock, flags);
-}
-
-/* External memory controller clock ops */
-static void tegra2_emc_clk_init(struct clk *c)
-{
-        tegra2_periph_clk_init(c);
-        c->max_rate = clk_get_rate_locked(c);
-}
-
-static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
-{
-        long emc_rate;
-        long clk_rate;
-
-        /*
-         * The slowest entry in the EMC clock table that is at least as
-         * fast as rate.
-         */
-        emc_rate = tegra_emc_round_rate(rate);
-        if (emc_rate < 0)
-                return c->max_rate;
-
-        /*
-         * The fastest rate the PLL will generate that is at most the
-         * requested rate.
-         */
-        clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
-
-        /*
-         * If this fails, and emc_rate > clk_rate, it's because the maximum
-         * rate in the EMC tables is larger than the maximum rate of the EMC
-         * clock. The EMC clock's max rate is the rate it was running when the
-         * kernel booted. Such a mismatch is probably due to using the wrong
-         * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
-         */
-        WARN_ONCE(emc_rate != clk_rate,
-                "emc_rate %ld != clk_rate %ld",
-                emc_rate, clk_rate);
-
-        return emc_rate;
-}
-
-static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        int ret;
-        /*
-         * The Tegra2 memory controller has an interlock with the clock
-         * block that allows memory shadowed registers to be updated,
-         * and then transfer them to the main registers at the same
-         * time as the clock update without glitches.
-         */
-        ret = tegra_emc_set_rate(rate);
-        if (ret < 0)
-                return ret;
-
-        ret = tegra2_periph_clk_set_rate(c, rate);
-        udelay(1);
-
-        return ret;
-}
-
-static struct clk_ops tegra_emc_clk_ops = {
-        .init                   = &tegra2_emc_clk_init,
-        .enable                 = &tegra2_periph_clk_enable,
-        .disable                = &tegra2_periph_clk_disable,
-        .set_parent             = &tegra2_periph_clk_set_parent,
-        .set_rate               = &tegra2_emc_clk_set_rate,
-        .round_rate             = &tegra2_emc_clk_round_rate,
-        .reset                  = &tegra2_periph_clk_reset,
-};
-
-/* Clock doubler ops */
-static void tegra2_clk_double_init(struct clk *c)
-{
-        c->mul = 2;
-        c->div = 1;
-        c->state = ON;
-
-        if (!c->u.periph.clk_num)
-                return;
-
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-};
-
-static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
-{
-        if (rate != 2 * clk_get_rate(c->parent))
-                return -EINVAL;
-        c->mul = 2;
-        c->div = 1;
-        return 0;
-}
-
-static struct clk_ops tegra_clk_double_ops = {
-        .init                   = &tegra2_clk_double_init,
-        .enable                 = &tegra2_periph_clk_enable,
-        .disable                = &tegra2_periph_clk_disable,
-        .set_rate               = &tegra2_clk_double_set_rate,
-};
-
-/* Audio sync clock ops */
-static void tegra2_audio_sync_clk_init(struct clk *c)
-{
-        int source;
-        const struct clk_mux_sel *sel;
-        u32 val = clk_readl(c->reg);
-        c->state = (val & (1<<4)) ? OFF : ON;
-        source = val & 0xf;
-        for (sel = c->inputs; sel->input != NULL; sel++)
-                if (sel->value == source)
-                        break;
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
-}
-
-static int tegra2_audio_sync_clk_enable(struct clk *c)
-{
-        clk_writel(0, c->reg);
-        return 0;
-}
-
-static void tegra2_audio_sync_clk_disable(struct clk *c)
-{
-        clk_writel(1, c->reg);
-}
-
-static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
-{
-        u32 val;
-        const struct clk_mux_sel *sel;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~0xf;
-                        val |= sel->value;
-
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        clk_writel(val, c->reg);
-
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_audio_sync_clk_ops = {
-        .init       = tegra2_audio_sync_clk_init,
-        .enable     = tegra2_audio_sync_clk_enable,
-        .disable    = tegra2_audio_sync_clk_disable,
-        .set_parent = tegra2_audio_sync_clk_set_parent,
-};
-
-/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
-
-static void tegra2_cdev_clk_init(struct clk *c)
-{
-        /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
-         * currently done in the pinmux code. */
-        c->state = ON;
-
-        BUG_ON(!c->u.periph.clk_num);
-
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-}
-
-static int tegra2_cdev_clk_enable(struct clk *c)
-{
-        BUG_ON(!c->u.periph.clk_num);
-
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
-        return 0;
-}
-
-static void tegra2_cdev_clk_disable(struct clk *c)
-{
-        BUG_ON(!c->u.periph.clk_num);
-
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-
-static struct clk_ops tegra_cdev_clk_ops = {
-        .init                   = &tegra2_cdev_clk_init,
-        .enable                 = &tegra2_cdev_clk_enable,
-        .disable                = &tegra2_cdev_clk_disable,
-};
-
-/* shared bus ops */
-/*
- * Some clocks may have multiple downstream users that need to request a
- * higher clock rate.  Shared bus clocks provide a unique shared_bus_user
- * clock to each user.  The frequency of the bus is set to the highest
- * enabled shared_bus_user clock, with a minimum value set by the
- * shared bus.
- */
-static int tegra_clk_shared_bus_update(struct clk *bus)
-{
-        struct clk *c;
-        unsigned long rate = bus->min_rate;
-
-        list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
-                if (c->u.shared_bus_user.enabled)
-                        rate = max(c->u.shared_bus_user.rate, rate);
-
-        if (rate == clk_get_rate_locked(bus))
-                return 0;
-
-        return clk_set_rate_locked(bus, rate);
-};
-
-static void tegra_clk_shared_bus_init(struct clk *c)
-{
-        unsigned long flags;
-
-        c->max_rate = c->parent->max_rate;
-        c->u.shared_bus_user.rate = c->parent->max_rate;
-        c->state = OFF;
-        c->set = true;
-
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-
-        list_add_tail(&c->u.shared_bus_user.node,
-                &c->parent->shared_bus_list);
-
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-
-static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
-{
-        unsigned long flags;
-        int ret;
-        long new_rate = rate;
-
-        new_rate = clk_round_rate(c->parent, new_rate);
-        if (new_rate < 0)
-                return new_rate;
-
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-
-        c->u.shared_bus_user.rate = new_rate;
-        ret = tegra_clk_shared_bus_update(c->parent);
-
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-
-        return ret;
-}
-
-static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
-{
-        return clk_round_rate(c->parent, rate);
-}
-
-static int tegra_clk_shared_bus_enable(struct clk *c)
-{
-        unsigned long flags;
-        int ret;
-
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-
-        c->u.shared_bus_user.enabled = true;
-        ret = tegra_clk_shared_bus_update(c->parent);
-
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-
-        return ret;
-}
-
-static void tegra_clk_shared_bus_disable(struct clk *c)
-{
-        unsigned long flags;
-        int ret;
-
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-
-        c->u.shared_bus_user.enabled = false;
-        ret = tegra_clk_shared_bus_update(c->parent);
-        WARN_ON_ONCE(ret);
-
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-
-static struct clk_ops tegra_clk_shared_bus_ops = {
-        .init = tegra_clk_shared_bus_init,
-        .enable = tegra_clk_shared_bus_enable,
-        .disable = tegra_clk_shared_bus_disable,
-        .set_rate = tegra_clk_shared_bus_set_rate,
-        .round_rate = tegra_clk_shared_bus_round_rate,
-};
-
-
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
-        .name = "clk_32k",
-        .rate = 32768,
-        .ops  = NULL,
-        .max_rate = 32768,
-};
-
-static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
-        {32768, 12000000, 366, 1, 1, 0},
-        {32768, 13000000, 397, 1, 1, 0},
-        {32768, 19200000, 586, 1, 1, 0},
-        {32768, 26000000, 793, 1, 1, 0},
-        {0, 0, 0, 0, 0, 0},
-};
-
-static struct clk tegra_pll_s = {
-        .name      = "pll_s",
-        .flags     = PLL_ALT_MISC_REG,
-        .ops       = &tegra_pll_ops,
-        .parent    = &tegra_clk_32k,
-        .max_rate  = 26000000,
-        .reg       = 0xf0,
-        .u.pll = {
-                .input_min = 32768,
-                .input_max = 32768,
-                .cf_min    = 0, /* FIXME */
-                .cf_max    = 0, /* FIXME */
-                .vco_min   = 12000000,
-                .vco_max   = 26000000,
-                .freq_table = tegra_pll_s_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk_mux_sel tegra_clk_m_sel[] = {
-        { .input = &tegra_clk_32k, .value = 0},
-        { .input = &tegra_pll_s,  .value = 1},
-        { NULL , 0},
-};
-
-static struct clk tegra_clk_m = {
-        .name      = "clk_m",
-        .flags     = ENABLE_ON_INIT,
-        .ops       = &tegra_clk_m_ops,
-        .inputs    = tegra_clk_m_sel,
-        .reg       = 0x1fc,
-        .reg_shift = 28,
-        .max_rate  = 26000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-        { 12000000, 600000000, 600, 12, 1, 8 },
-        { 13000000, 600000000, 600, 13, 1, 8 },
-        { 19200000, 600000000, 500, 16, 1, 6 },
-        { 26000000, 600000000, 600, 26, 1, 8 },
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_c = {
-        .name      = "pll_c",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x80,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 600000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_c_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_c_out1 = {
-        .name      = "pll_c_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_c,
-        .reg       = 0x84,
-        .reg_shift = 0,
-        .max_rate  = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_m = {
-        .name      = "pll_m",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x90,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 800000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1200000000,
-                .freq_table = tegra_pll_m_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_m_out1 = {
-        .name      = "pll_m_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_m,
-        .reg       = 0x94,
-        .reg_shift = 0,
-        .max_rate  = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 19200000, 216000000, 90,   4, 2, 1},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 12000000, 432000000, 432, 12, 1, 8},
-        { 13000000, 432000000, 432, 13, 1, 8},
-        { 19200000, 432000000, 90,   4, 1, 1},
-        { 26000000, 432000000, 432, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_p = {
-        .name      = "pll_p",
-        .flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xa0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 432000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_p_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_p_out1 = {
-        .name      = "pll_p_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
-        .name      = "pll_p_out2",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
-        .name      = "pll_p_out3",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
-        .name      = "pll_p_out4",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_a = {
-        .name      = "pll_a",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xb0,
-        .parent    = &tegra_pll_p_out1,
-        .max_rate  = 73728000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_a_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_a_out0 = {
-        .name      = "pll_a_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_a,
-        .reg       = 0xb4,
-        .reg_shift = 0,
-        .max_rate  = 73728000,
-};
-
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 19200000, 216000000, 135, 12, 1, 3},
-        { 26000000, 216000000, 216, 26, 1, 4},
-
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_d = {
-        .name      = "pll_d",
-        .flags     = PLL_HAS_CPCON | PLLD,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xd0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 40000000,
-                .vco_max   = 1000000000,
-                .freq_table = tegra_pll_d_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk tegra_pll_d_out0 = {
-        .name      = "pll_d_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLD,
-        .parent    = &tegra_pll_d,
-        .max_rate  = 500000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 0},
-        { 13000000, 480000000, 960, 13, 2, 0},
-        { 19200000, 480000000, 200, 4,  2, 0},
-        { 26000000, 480000000, 960, 26, 2, 0},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_u = {
-        .name      = "pll_u",
-        .flags     = PLLU,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xc0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 480000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 480000000,
-                .vco_max   = 960000000,
-                .freq_table = tegra_pll_u_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-        /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-
-        /* 912 MHz */
-        { 12000000, 912000000,  912,  12, 1, 12},
-        { 13000000, 912000000,  912,  13, 1, 12},
-        { 19200000, 912000000,  760,  16, 1, 8},
-        { 26000000, 912000000,  912,  26, 1, 12},
-
-        /* 816 MHz */
-        { 12000000, 816000000,  816,  12, 1, 12},
-        { 13000000, 816000000,  816,  13, 1, 12},
-        { 19200000, 816000000,  680,  16, 1, 8},
-        { 26000000, 816000000,  816,  26, 1, 12},
-
-        /* 760 MHz */
-        { 12000000, 760000000,  760,  12, 1, 12},
-        { 13000000, 760000000,  760,  13, 1, 12},
-        { 19200000, 760000000,  950,  24, 1, 8},
-        { 26000000, 760000000,  760,  26, 1, 12},
-
-        /* 750 MHz */
-        { 12000000, 750000000,  750,  12, 1, 12},
-        { 13000000, 750000000,  750,  13, 1, 12},
-        { 19200000, 750000000,  625,  16, 1, 8},
-        { 26000000, 750000000,  750,  26, 1, 12},
-
-        /* 608 MHz */
-        { 12000000, 608000000,  608,  12, 1, 12},
-        { 13000000, 608000000,  608,  13, 1, 12},
-        { 19200000, 608000000,  380,  12, 1, 8},
-        { 26000000, 608000000,  608,  26, 1, 12},
-
-        /* 456 MHz */
-        { 12000000, 456000000,  456,  12, 1, 12},
-        { 13000000, 456000000,  456,  13, 1, 12},
-        { 19200000, 456000000,  380,  16, 1, 8},
-        { 26000000, 456000000,  456,  26, 1, 12},
-
-        /* 312 MHz */
-        { 12000000, 312000000,  312,  12, 1, 12},
-        { 13000000, 312000000,  312,  13, 1, 12},
-        { 19200000, 312000000,  260,  16, 1, 8},
-        { 26000000, 312000000,  312,  26, 1, 12},
-
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_x = {
-        .name      = "pll_x",
-        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
-        .ops       = &tegra_pllx_ops,
-        .reg       = 0xe0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1200000000,
-                .freq_table = tegra_pll_x_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-        { 12000000, 100000000,  200,  24, 1, 0 },
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_e = {
-        .name      = "pll_e",
-        .flags     = PLL_ALT_MISC_REG,
-        .ops       = &tegra_plle_ops,
-        .parent    = &tegra_clk_m,
-        .reg       = 0xe8,
-        .max_rate  = 100000000,
-        .u.pll = {
-                .input_min = 12000000,
-                .input_max = 12000000,
-                .freq_table = tegra_pll_e_freq_table,
-        },
-};
-
-static struct clk tegra_clk_d = {
-        .name      = "clk_d",
-        .flags     = PERIPH_NO_RESET,
-        .ops       = &tegra_clk_double_ops,
-        .reg       = 0x34,
-        .reg_shift = 12,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 52000000,
-        .u.periph  = {
-                .clk_num = 90,
-        },
-};
-
-/* dap_mclk1, belongs to the cdev1 pingroup. */
-static struct clk tegra_clk_cdev1 = {
-        .name      = "cdev1",
-        .ops       = &tegra_cdev_clk_ops,
-        .rate      = 26000000,
-        .max_rate  = 26000000,
-        .u.periph  = {
-                .clk_num = 94,
-        },
-};
-
-/* dap_mclk2, belongs to the cdev2 pingroup. */
-static struct clk tegra_clk_cdev2 = {
-        .name      = "cdev2",
-        .ops       = &tegra_cdev_clk_ops,
-        .rate      = 26000000,
-        .max_rate  = 26000000,
-        .u.periph  = {
-                .clk_num   = 93,
-        },
-};
-
-/* initialized before peripheral clocks */
-static struct clk_mux_sel mux_audio_sync_clk[8+1];
-static const struct audio_sources {
-        const char *name;
-        int value;
-} mux_audio_sync_clk_sources[] = {
-        { .name = "spdif_in", .value = 0 },
-        { .name = "i2s1", .value = 1 },
-        { .name = "i2s2", .value = 2 },
-        { .name = "pll_a_out0", .value = 4 },
-#if 0 /* FIXME: not implemented */
-        { .name = "ac97", .value = 3 },
-        { .name = "ext_audio_clk2", .value = 5 },
-        { .name = "ext_audio_clk1", .value = 6 },
-        { .name = "ext_vimclk", .value = 7 },
-#endif
-        { NULL, 0 }
-};
-
-static struct clk tegra_clk_audio = {
-        .name      = "audio",
-        .inputs    = mux_audio_sync_clk,
-        .reg       = 0x38,
-        .max_rate  = 73728000,
-        .ops       = &tegra_audio_sync_clk_ops
-};
-
-static struct clk tegra_clk_audio_2x = {
-        .name      = "audio_2x",
-        .flags     = PERIPH_NO_RESET,
-        .max_rate  = 48000000,
-        .ops       = &tegra_clk_double_ops,
-        .reg       = 0x34,
-        .reg_shift = 8,
-        .parent    = &tegra_clk_audio,
-        .u.periph = {
-                .clk_num = 89,
-        },
-};
-
-static struct clk_lookup tegra_audio_clk_lookups[] = {
-        { .con_id = "audio", .clk = &tegra_clk_audio },
-        { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
-};
-
-/* This is called after peripheral clocks are initialized, as the
- * audio_sync clock depends on some of the peripheral clocks.
- */
-
-static void init_audio_sync_clock_mux(void)
-{
-        int i;
-        struct clk_mux_sel *sel = mux_audio_sync_clk;
-        const struct audio_sources *src = mux_audio_sync_clk_sources;
-        struct clk_lookup *lookup;
-
-        for (i = 0; src->name; i++, sel++, src++) {
-                sel->input = tegra_get_clock_by_name(src->name);
-                if (!sel->input)
-                        pr_err("%s: could not find clk %s\n", __func__,
-                                src->name);
-                sel->value = src->value;
-        }
-
-        lookup = tegra_audio_clk_lookups;
-        for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
-                clk_init(lookup->clk);
-                clkdev_add(lookup);
-        }
-}
-
-static struct clk_mux_sel mux_cclk[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c,        .value = 1},
-        { .input = &tegra_clk_32k,      .value = 2},
-        { .input = &tegra_pll_m,        .value = 3},
-        { .input = &tegra_pll_p,        .value = 4},
-        { .input = &tegra_pll_p_out4,   .value = 5},
-        { .input = &tegra_pll_p_out3,   .value = 6},
-        { .input = &tegra_clk_d,        .value = 7},
-        { .input = &tegra_pll_x,        .value = 8},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_sclk[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c_out1,   .value = 1},
-        { .input = &tegra_pll_p_out4,   .value = 2},
-        { .input = &tegra_pll_p_out3,   .value = 3},
-        { .input = &tegra_pll_p_out2,   .value = 4},
-        { .input = &tegra_clk_d,        .value = 5},
-        { .input = &tegra_clk_32k,      .value = 6},
-        { .input = &tegra_pll_m_out1,   .value = 7},
-        { NULL, 0},
-};
-
-static struct clk tegra_clk_cclk = {
-        .name   = "cclk",
-        .inputs = mux_cclk,
-        .reg    = 0x20,
-        .ops    = &tegra_super_ops,
-        .max_rate = 1000000000,
-};
-
-static struct clk tegra_clk_sclk = {
-        .name   = "sclk",
-        .inputs = mux_sclk,
-        .reg    = 0x28,
-        .ops    = &tegra_super_ops,
-        .max_rate = 240000000,
-        .min_rate = 120000000,
-};
-
-static struct clk tegra_clk_virtual_cpu = {
-        .name      = "cpu",
-        .parent    = &tegra_clk_cclk,
-        .ops       = &tegra_cpu_ops,
-        .max_rate  = 1000000000,
-        .u.cpu = {
-                .main      = &tegra_pll_x,
-                .backup    = &tegra_pll_p,
-        },
-};
-
-static struct clk tegra_clk_cop = {
-        .name      = "cop",
-        .parent    = &tegra_clk_sclk,
-        .ops       = &tegra_cop_ops,
-        .max_rate  = 240000000,
-};
-
-static struct clk tegra_clk_hclk = {
-        .name           = "hclk",
-        .flags          = DIV_BUS,
-        .parent         = &tegra_clk_sclk,
-        .reg            = 0x30,
-        .reg_shift      = 4,
-        .ops            = &tegra_bus_ops,
-        .max_rate       = 240000000,
-};
-
-static struct clk tegra_clk_pclk = {
-        .name           = "pclk",
-        .flags          = DIV_BUS,
-        .parent         = &tegra_clk_hclk,
-        .reg            = 0x30,
-        .reg_shift      = 0,
-        .ops            = &tegra_bus_ops,
-        .max_rate       = 120000000,
-};
-
-static struct clk tegra_clk_blink = {
-        .name           = "blink",
-        .parent         = &tegra_clk_32k,
-        .reg            = 0x40,
-        .ops            = &tegra_blink_clk_ops,
-        .max_rate       = 32768,
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-        { .input = &tegra_pll_m, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_pll_a_out0, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
-        { .input = &tegra_pll_m, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-        { .input = &tegra_pll_p, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_m, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
-        {.input = &tegra_pll_a_out0, .value = 0},
-        {.input = &tegra_clk_audio_2x, .value = 1},
-        {.input = &tegra_pll_p, .value = 2},
-        {.input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-        {.input = &tegra_pll_p, .value = 0},
-        {.input = &tegra_pll_d_out0, .value = 1},
-        {.input = &tegra_pll_c, .value = 2},
-        {.input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_clk_audio,     .value = 2},
-        {.input = &tegra_clk_m,     .value = 3},
-        {.input = &tegra_clk_32k,   .value = 4},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_pll_m,     .value = 2},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_clk_m[] = {
-        { .input = &tegra_clk_m, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_out3[] = {
-        { .input = &tegra_pll_p_out3, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_plld[] = {
-        { .input = &tegra_pll_d, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_clk_32k[] = {
-        { .input = &tegra_clk_32k, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pclk[] = {
-        { .input = &tegra_clk_pclk, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk tegra_clk_emc = {
-        .name = "emc",
-        .ops = &tegra_emc_clk_ops,
-        .reg = 0x19c,
-        .max_rate = 800000000,
-        .inputs = mux_pllm_pllc_pllp_clkm,
-        .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
-        .u.periph = {
-                .clk_num = 57,
-        },
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_periph_clk_ops,     \
-                .reg       = _reg,                      \
-                .inputs    = _inputs,                   \
-                .flags     = _flags,                    \
-                .max_rate  = _max,                      \
-                .u.periph = {                           \
-                        .clk_num   = _clk_num,          \
-                },                                      \
-        }
-
-#define SHARED_CLK(_name, _dev, _con, _parent)          \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_clk_shared_bus_ops, \
-                .parent = _parent,                      \
-        }
-
-static struct clk tegra_list_clks[] = {
-        PERIPH_CLK("apbdma",    "tegra-apbdma",         NULL,   34,     0,      108000000, mux_pclk,                    0),
-        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET),
-        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("i2s1",      "tegra20-i2s.0",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
-        PERIPH_CLK("i2s2",      "tegra20-i2s.1",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
-        PERIPH_CLK("spdif_out", "spdif_out",            NULL,   10,     0x108,  100000000, mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
-        PERIPH_CLK("spdif_in",  "spdif_in",             NULL,   10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71),
-        PERIPH_CLK("pwm",       "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71 | MUX_PWM),
-        PERIPH_CLK("spi",       "spi",                  NULL,   43,     0x114,  40000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("xio",       "xio",                  NULL,   45,     0x120,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("twc",       "twc",                  NULL,   16,     0x12c,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("ide",       "ide",                  NULL,   25,     0x144,  100000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("ndflash",   "tegra_nand",           NULL,   13,     0x160,  164000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x164,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("vde",       "tegra-avp",            "vde",  61,     0x1c8,  250000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
-        /* FIXME: what is la? */
-        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  92000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("dvc",       "tegra-i2c.3",          NULL,   47,     0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("i2c1_i2c",  "tegra-i2c.0",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("i2c2_i2c",  "tegra-i2c.1",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("i2c3_i2c",  "tegra-i2c.2",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("dvc_i2c",   "tegra-i2c.3",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("uarta",     "tegra-uart.0",         NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartb",     "tegra-uart.1",         NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartc",     "tegra-uart.2",         NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartd",     "tegra-uart.3",         NULL,   65,     0x1c0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uarte",     "tegra-uart.4",         NULL,   66,     0x1c4,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
-        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("vi",        "tegra_camera",         "vi",   20,     0x148,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
-        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  250000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  166000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage and process_id */
-        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage and process_id */
-        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("dsi",       "dsi",                  NULL,   48,     0,      500000000, mux_plld,                    0), /* scales with voltage */
-        PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      72000000,  mux_pllp_out3,               0),
-        PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
-        PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-        PERIPH_CLK("pex",       NULL,                   "pex",  70,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
-        PERIPH_CLK("afi",       NULL,                   "afi",  72,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
-        PERIPH_CLK("pcie_xclk", NULL,             "pcie_xclk",  74,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
-
-        SHARED_CLK("avp.sclk",  "tegra-avp",            "sclk", &tegra_clk_sclk),
-        SHARED_CLK("avp.emc",   "tegra-avp",            "emc",  &tegra_clk_emc),
-        SHARED_CLK("cpu.emc",   "cpu",                  "emc",  &tegra_clk_emc),
-        SHARED_CLK("disp1.emc", "tegradc.0",            "emc",  &tegra_clk_emc),
-        SHARED_CLK("disp2.emc", "tegradc.1",            "emc",  &tegra_clk_emc),
-        SHARED_CLK("hdmi.emc",  "hdmi",                 "emc",  &tegra_clk_emc),
-        SHARED_CLK("host.emc",  "tegra_grhost",         "emc",  &tegra_clk_emc),
-        SHARED_CLK("usbd.emc",  "fsl-tegra-udc",        "emc",  &tegra_clk_emc),
-        SHARED_CLK("usb1.emc",  "tegra-ehci.0",         "emc",  &tegra_clk_emc),
-        SHARED_CLK("usb2.emc",  "tegra-ehci.1",         "emc",  &tegra_clk_emc),
-        SHARED_CLK("usb3.emc",  "tegra-ehci.2",         "emc",  &tegra_clk_emc),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con)                \
-        {                                               \
-                .name   = _name,                        \
-                .lookup = {                             \
-                        .dev_id = _dev,                 \
-                        .con_id         = _con,         \
-                },                                      \
-        }
-
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-static struct clk_duplicate tegra_clk_duplicates[] = {
-        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-        CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
-        CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
-        CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
-        CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
-        CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
-        CLK_DUPLICATE("cop", "tegra-avp", "cop"),
-        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-};
-
-#define CLK(dev, con, ck)       \
-        {                       \
-                .dev_id = dev,  \
-                .con_id = con,  \
-                .clk = ck,      \
-        }
-
-static struct clk *tegra_ptr_clks[] = {
-        &tegra_clk_32k,
-        &tegra_pll_s,
-        &tegra_clk_m,
-        &tegra_pll_m,
-        &tegra_pll_m_out1,
-        &tegra_pll_c,
-        &tegra_pll_c_out1,
-        &tegra_pll_p,
-        &tegra_pll_p_out1,
-        &tegra_pll_p_out2,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out4,
-        &tegra_pll_a,
-        &tegra_pll_a_out0,
-        &tegra_pll_d,
-        &tegra_pll_d_out0,
-        &tegra_pll_u,
-        &tegra_pll_x,
-        &tegra_pll_e,
-        &tegra_clk_cclk,
-        &tegra_clk_sclk,
-        &tegra_clk_hclk,
-        &tegra_clk_pclk,
-        &tegra_clk_d,
-        &tegra_clk_cdev1,
-        &tegra_clk_cdev2,
-        &tegra_clk_virtual_cpu,
-        &tegra_clk_blink,
-        &tegra_clk_cop,
-        &tegra_clk_emc,
-};
-
-static void tegra2_init_one_clock(struct clk *c)
-{
-        clk_init(c);
-        INIT_LIST_HEAD(&c->shared_bus_list);
-        if (!c->lookup.dev_id && !c->lookup.con_id)
-                c->lookup.con_id = c->name;
-        c->lookup.clk = c;
-        clkdev_add(&c->lookup);
-}
-
-void __init tegra2_init_clocks(void)
-{
-        int i;
-        struct clk *c;
-
-        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
-                tegra2_init_one_clock(tegra_ptr_clks[i]);
-
-        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-                tegra2_init_one_clock(&tegra_list_clks[i]);
-
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-                if (!c) {
-                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                                tegra_clk_duplicates[i].name);
-                        continue;
-                }
-
-                tegra_clk_duplicates[i].lookup.clk = c;
-                clkdev_add(&tegra_clk_duplicates[i].lookup);
-        }
-
-        init_audio_sync_clock_mux();
-}
-
-#ifdef CONFIG_PM
-static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
-                           PERIPH_CLK_SOURCE_NUM + 22];
-
-void tegra_clk_suspend(void)
-{
-        unsigned long off, i;
-        u32 *ctx = clk_rst_suspend;
-
-        *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
-        *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
-        *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
-        *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
-        *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
-        *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
-
-        *ctx++ = clk_readl(tegra_pll_m_out1.reg);
-        *ctx++ = clk_readl(tegra_pll_a_out0.reg);
-        *ctx++ = clk_readl(tegra_pll_c_out1.reg);
-
-        *ctx++ = clk_readl(tegra_clk_cclk.reg);
-        *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-
-        *ctx++ = clk_readl(tegra_clk_sclk.reg);
-        *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
-        *ctx++ = clk_readl(tegra_clk_pclk.reg);
-
-        *ctx++ = clk_readl(tegra_clk_audio.reg);
-
-        for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
-                        off += 4) {
-                if (off == PERIPH_CLK_SOURCE_EMC)
-                        continue;
-                *ctx++ = clk_readl(off);
-        }
-
-        off = RST_DEVICES;
-        for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
-                *ctx++ = clk_readl(off);
-
-        off = CLK_OUT_ENB;
-        for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
-                *ctx++ = clk_readl(off);
-
-        *ctx++ = clk_readl(MISC_CLK_ENB);
-        *ctx++ = clk_readl(CLK_MASK_ARM);
-
-        BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
-}
-
-void tegra_clk_resume(void)
-{
-        unsigned long off, i;
-        const u32 *ctx = clk_rst_suspend;
-        u32 val;
-
-        val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
-        val |= *ctx++;
-        clk_writel(val, OSC_CTRL);
-
-        clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
-        clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
-        clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
-        clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
-        clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
-        udelay(1000);
-
-        clk_writel(*ctx++, tegra_pll_m_out1.reg);
-        clk_writel(*ctx++, tegra_pll_a_out0.reg);
-        clk_writel(*ctx++, tegra_pll_c_out1.reg);
-
-        clk_writel(*ctx++, tegra_clk_cclk.reg);
-        clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-
-        clk_writel(*ctx++, tegra_clk_sclk.reg);
-        clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
-        clk_writel(*ctx++, tegra_clk_pclk.reg);
-
-        clk_writel(*ctx++, tegra_clk_audio.reg);
-
-        /* enable all clocks before configuring clock sources */
-        clk_writel(0xbffffff9ul, CLK_OUT_ENB);
-        clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
-        clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
-        wmb();
-
-        for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
-                        off += 4) {
-                if (off == PERIPH_CLK_SOURCE_EMC)
-                        continue;
-                clk_writel(*ctx++, off);
-        }
-        wmb();
-
-        off = RST_DEVICES;
-        for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
-                clk_writel(*ctx++, off);
-        wmb();
-
-        off = CLK_OUT_ENB;
-        for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
-                clk_writel(*ctx++, off);
-        wmb();
-
-        clk_writel(*ctx++, MISC_CLK_ENB);
-        clk_writel(*ctx++, CLK_MASK_ARM);
-}
-#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6674f100e16f..5cd502c27163 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra30_clocks.c
  *
- * Copyright (c) 2010-2011 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -35,6 +35,7 @@
 
 #include "clock.h"
 #include "fuse.h"
+#include "tegra_cpu_car.h"
 
 #define USE_PLL_LOCK_BITS 0
 
@@ -299,6 +300,16 @@
 /* FIXME: recommended safety delay after lock is detected */
 #define PLL_POST_LOCK_DELAY             100
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR    0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
+
+#define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
+#define CPU_RESET(cpu)  (0x1111ul << (cpu))
+
 /**
 * Structure defining the fields for USB UTMI clocks Parameters.
 */
@@ -365,30 +376,32 @@ static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 
 #define clk_writel(value, reg) \
-        __raw_writel(value, (u32)reg_clk_base + (reg))
+        __raw_writel(value, reg_clk_base + (reg))
 #define clk_readl(reg) \
-        __raw_readl((u32)reg_clk_base + (reg))
+        __raw_readl(reg_clk_base + (reg))
 #define pmc_writel(value, reg) \
-        __raw_writel(value, (u32)reg_pmc_base + (reg))
+        __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
-        __raw_readl((u32)reg_pmc_base + (reg))
+        __raw_readl(reg_pmc_base + (reg))
 #define chipid_readl() \
-        __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
+        __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
 
 #define clk_writel_delay(value, reg)                                    \
         do {                                                            \
-                __raw_writel((value), (u32)reg_clk_base + (reg));       \
+                __raw_writel((value), reg_clk_base + (reg));    \
                 udelay(2);                                              \
         } while (0)
 
-
-static inline int clk_set_div(struct clk *c, u32 n)
+static inline int clk_set_div(struct clk_tegra *c, u32 n)
 {
-        return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
+        struct clk *clk = c->hw.clk;
+
+        return clk_set_rate(clk,
+                        (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
 }
 
 static inline u32 periph_clk_to_reg(
-        struct clk *c, u32 reg_L, u32 reg_V, int offs)
+        struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
 {
         u32 reg = c->u.periph.clk_num / 32;
         BUG_ON(reg >= RST_DEVICES_NUM);
@@ -470,15 +483,32 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
         return divider_u16 - 1;
 }
 
+static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra30_clk_32k_ops = {
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
+};
+
 /* clk_m functions */
-static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
+static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        if (!to_clk_tegra(hw)->fixed_rate)
+                to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+static void tegra30_clk_m_init(struct clk_hw *hw)
 {
         u32 osc_ctrl = clk_readl(OSC_CTRL);
         u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
         u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
 
-        c->rate = clk_measure_input_freq();
-        switch (c->rate) {
+        switch (to_clk_tegra(hw)->fixed_rate) {
         case 12000000:
                 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
@@ -508,46 +538,44 @@ static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
                 break;
         default:
-                pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
+                pr_err("%s: Unexpected clock rate %ld", __func__,
+                                to_clk_tegra(hw)->fixed_rate);
                 BUG();
         }
         clk_writel(auto_clock_control, OSC_CTRL);
-        return c->rate;
 }
 
-static void tegra30_clk_m_init(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        tegra30_clk_m_autodetect_rate(c);
-}
+struct clk_ops tegra30_clk_m_ops = {
+        .init = tegra30_clk_m_init,
+        .recalc_rate = tegra30_clk_m_recalc_rate,
+};
 
-static int tegra30_clk_m_enable(struct clk *c)
+static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
 {
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        return 0;
-}
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
 
-static void tegra30_clk_m_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        WARN(1, "Attempting to disable main SoC clock\n");
-}
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
 
-static struct clk_ops tegra_clk_m_ops = {
-        .init           = tegra30_clk_m_init,
-        .enable         = tegra30_clk_m_enable,
-        .disable        = tegra30_clk_m_disable,
-};
+        return rate;
+}
 
-static struct clk_ops tegra_clk_m_div_ops = {
-        .enable         = tegra30_clk_m_enable,
+struct clk_ops tegra_clk_m_div_ops = {
+        .recalc_rate = tegra30_clk_m_div_recalc_rate,
 };
 
 /* PLL reference divider functions */
-static void tegra30_pll_ref_init(struct clk *c)
+static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
+                        unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long rate = parent_rate;
         u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
-        pr_debug("%s on clock %s\n", __func__, c->name);
 
         switch (pll_ref_div) {
         case OSC_CTRL_PLL_REF_DIV_1:
@@ -564,13 +592,18 @@ static void tegra30_pll_ref_init(struct clk *c)
                 BUG();
         }
         c->mul = 1;
-        c->state = ON;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
 }
 
-static struct clk_ops tegra_pll_ref_ops = {
-        .init           = tegra30_pll_ref_init,
-        .enable         = tegra30_clk_m_enable,
-        .disable        = tegra30_clk_m_disable,
+struct clk_ops tegra_pll_ref_ops = {
+        .recalc_rate = tegra30_pll_ref_recalc_rate,
 };
 
 /* super clock functions */
@@ -581,56 +614,50 @@ static struct clk_ops tegra_pll_ref_ops = {
  * only when its parent is a fixed rate PLL, since we can't change PLL rate
  * in this case.
  */
-static void tegra30_super_clk_init(struct clk *c)
+static void tegra30_super_clk_init(struct clk_hw *hw)
 {
-        u32 val;
-        int source;
-        int shift;
-        const struct clk_mux_sel *sel;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        c->state = ON;
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        source = (val >> shift) & SUPER_SOURCE_MASK;
-        if (c->flags & DIV_2)
-                source |= val & SUPER_LP_DIV2_BYPASS;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->value == source)
-                        break;
-        }
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk_tegra *p =
+                        to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
 
+        c->state = ON;
         if (c->flags & DIV_U71) {
                 /* Init safe 7.1 divider value (does not affect PLLX path) */
                 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
                            c->reg + SUPER_CLK_DIVIDER);
                 c->mul = 2;
                 c->div = 2;
-                if (!(c->parent->flags & PLLX))
+                if (!(p->flags & PLLX))
                         c->div += SUPER_CLOCK_DIV_U71_MIN;
         } else
                 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
 }
 
-static int tegra30_super_clk_enable(struct clk *c)
+static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
 {
-        return 0;
-}
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        int source;
+        int shift;
 
-static void tegra30_super_clk_disable(struct clk *c)
-{
-        /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
-           geared up g-mode super clock - mode switch may request to disable
-           either of them; accept request with no affect on h/w */
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        source = (val >> shift) & SUPER_SOURCE_MASK;
+        if (c->flags & DIV_2)
+                source |= val & SUPER_LP_DIV2_BYPASS;
+
+        return source;
 }
 
-static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk_tegra *p =
+                        to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
         u32 val;
-        const struct clk_mux_sel *sel;
         int shift;
 
         val = clk_readl(c->reg + SUPER_CLK_MUX);
@@ -638,48 +665,36 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
                 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
         shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
                 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        /* For LP mode super-clock switch between PLLX direct
-                           and divided-by-2 outputs is allowed only when other
-                           than PLLX clock source is current parent */
-                        if ((c->flags & DIV_2) && (p->flags & PLLX) &&
-                            ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
-                                if (c->parent->flags & PLLX)
-                                        return -EINVAL;
-                                val ^= SUPER_LP_DIV2_BYPASS;
-                                clk_writel_delay(val, c->reg);
-                        }
-                        val &= ~(SUPER_SOURCE_MASK << shift);
-                        val |= (sel->value & SUPER_SOURCE_MASK) << shift;
-
-                        /* 7.1 divider for CPU super-clock does not affect
-                           PLLX path */
-                        if (c->flags & DIV_U71) {
-                                u32 div = 0;
-                                if (!(p->flags & PLLX)) {
-                                        div = clk_readl(c->reg +
-                                                        SUPER_CLK_DIVIDER);
-                                        div &= SUPER_CLOCK_DIV_U71_MASK;
-                                        div >>= SUPER_CLOCK_DIV_U71_SHIFT;
-                                }
-                                c->div = div + 2;
-                                c->mul = 2;
-                        }
-
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        clk_writel_delay(val, c->reg);
 
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
+        /* For LP mode super-clock switch between PLLX direct
+           and divided-by-2 outputs is allowed only when other
+           than PLLX clock source is current parent */
+        if ((c->flags & DIV_2) && (p->flags & PLLX) &&
+            ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
+                if (p->flags & PLLX)
+                        return -EINVAL;
+                val ^= SUPER_LP_DIV2_BYPASS;
+                clk_writel_delay(val, c->reg);
+        }
+        val &= ~(SUPER_SOURCE_MASK << shift);
+        val |= (index & SUPER_SOURCE_MASK) << shift;
 
-                        clk_reparent(c, p);
-                        return 0;
+        /* 7.1 divider for CPU super-clock does not affect
+           PLLX path */
+        if (c->flags & DIV_U71) {
+                u32 div = 0;
+                if (!(p->flags & PLLX)) {
+                        div = clk_readl(c->reg +
+                                        SUPER_CLK_DIVIDER);
+                        div &= SUPER_CLOCK_DIV_U71_MASK;
+                        div >>= SUPER_CLOCK_DIV_U71_SHIFT;
                 }
+                c->div = div + 2;
+                c->mul = 2;
         }
-        return -EINVAL;
+        clk_writel_delay(val, c->reg);
+
+        return 0;
 }
 
 /*
@@ -691,10 +706,15 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
  * rate of this PLL can't be changed, and it has many other children. In
  * this case use 7.1 fractional divider to adjust the super clock rate.
  */
-static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
-        if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) {
-                int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate,
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk *parent = __clk_get_parent(hw->clk);
+        struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+
+        if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+                int div = clk_div71_get_divider(parent_rate,
                                         rate, c->flags, ROUND_DIVIDER_DOWN);
                 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
 
@@ -704,55 +724,86 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
                 c->mul = 2;
                 return 0;
         }
-        return clk_set_rate(c->parent, rate);
+        return 0;
+}
+
+static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
 }
 
-static struct clk_ops tegra_super_ops = {
-        .init                   = tegra30_super_clk_init,
-        .enable                 = tegra30_super_clk_enable,
-        .disable                = tegra30_super_clk_disable,
-        .set_parent             = tegra30_super_clk_set_parent,
-        .set_rate               = tegra30_super_clk_set_rate,
+static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk *parent = __clk_get_parent(hw->clk);
+        struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+        int mul = 2;
+        int div;
+
+        if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+                div = clk_div71_get_divider(*prate,
+                                rate, c->flags, ROUND_DIVIDER_DOWN);
+                div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
+                rate = *prate * mul;
+                rate += div - 1; /* round up */
+                do_div(rate, c->div);
+
+                return rate;
+        }
+        return *prate;
+}
+
+struct clk_ops tegra30_super_ops = {
+        .init = tegra30_super_clk_init,
+        .set_parent = tegra30_super_clk_set_parent,
+        .get_parent = tegra30_super_clk_get_parent,
+        .recalc_rate = tegra30_super_clk_recalc_rate,
+        .round_rate = tegra30_super_clk_round_rate,
+        .set_rate = tegra30_super_clk_set_rate,
 };
 
-static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
 {
-        /* The input value 'rate' is the clock rate of the CPU complex. */
-        c->rate = (rate * c->mul) / c->div;
-        return 0;
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
 }
 
-static struct clk_ops tegra30_twd_ops = {
-        .set_rate       = tegra30_twd_clk_set_rate,
+struct clk_ops tegra30_twd_ops = {
+        .recalc_rate = tegra30_twd_clk_recalc_rate,
 };
 
 /* Blink output functions */
-
-static void tegra30_blink_clk_init(struct clk *c)
+static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
 
         val = pmc_readl(PMC_CTRL);
         c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
-        c->mul = 1;
-        val = pmc_readl(c->reg);
-
-        if (val & PMC_BLINK_TIMER_ENB) {
-                unsigned int on_off;
-
-                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
-                        PMC_BLINK_TIMER_DATA_ON_MASK;
-                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off += val;
-                /* each tick in the blink timer is 4 32KHz clocks */
-                c->div = on_off * 4;
-        } else {
-                c->div = 1;
-        }
+        return c->state;
 }
 
-static int tegra30_blink_clk_enable(struct clk *c)
+static int tegra30_blink_clk_enable(struct clk_hw *hw)
 {
         u32 val;
 
@@ -765,7 +816,7 @@ static int tegra30_blink_clk_enable(struct clk *c)
         return 0;
 }
 
-static void tegra30_blink_clk_disable(struct clk *c)
+static void tegra30_blink_clk_disable(struct clk_hw *hw)
 {
         u32 val;
 
@@ -776,9 +827,11 @@ static void tegra30_blink_clk_disable(struct clk *c)
         pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
 }
 
-static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
-        unsigned long parent_rate = clk_get_rate(c->parent);
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (rate >= parent_rate) {
                 c->div = 1;
                 pmc_writel(0, c->reg);
@@ -801,41 +854,77 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
         return 0;
 }
 
-static struct clk_ops tegra_blink_clk_ops = {
-        .init                   = &tegra30_blink_clk_init,
-        .enable                 = &tegra30_blink_clk_enable,
-        .disable                = &tegra30_blink_clk_disable,
-        .set_rate               = &tegra30_blink_clk_set_rate,
-};
+static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        u32 val;
+        u32 mul;
+        u32 div;
+        u32 on_off;
 
-/* PLL Functions */
-static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
-                                         u32 lock_bit)
+        mul = 1;
+        val = pmc_readl(c->reg);
+
+        if (val & PMC_BLINK_TIMER_ENB) {
+                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+                        PMC_BLINK_TIMER_DATA_ON_MASK;
+                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off += val;
+                /* each tick in the blink timer is 4 32KHz clocks */
+                div = on_off * 4;
+        } else {
+                div = 1;
+        }
+
+        if (mul != 0 && div != 0) {
+                rate *= mul;
+                rate += div - 1; /* round up */
+                do_div(rate, div);
+        }
+        return rate;
+}
+
+static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
 {
-#if USE_PLL_LOCK_BITS
-        int i;
-        for (i = 0; i < c->u.pll.lock_delay; i++) {
-                if (clk_readl(lock_reg) & lock_bit) {
-                        udelay(PLL_POST_LOCK_DELAY);
-                        return 0;
-                }
-                udelay(2);              /* timeout = 2 * lock time */
+        int div;
+        int mul;
+        long round_rate = *prate;
+
+        mul = 1;
+
+        if (rate >= *prate) {
+                div = 1;
+        } else {
+                div = DIV_ROUND_UP(*prate / 8, rate);
+                div *= 8;
         }
-        pr_err("Timed out waiting for lock bit on pll %s", c->name);
-        return -1;
-#endif
-        udelay(c->u.pll.lock_delay);
 
-        return 0;
+        round_rate *= mul;
+        round_rate += div - 1;
+        do_div(round_rate, div);
+
+        return round_rate;
 }
 
+struct clk_ops tegra30_blink_clk_ops = {
+        .is_enabled = tegra30_blink_clk_is_enabled,
+        .enable = tegra30_blink_clk_enable,
+        .disable = tegra30_blink_clk_disable,
+        .recalc_rate = tegra30_blink_clk_recalc_rate,
+        .round_rate = tegra30_blink_clk_round_rate,
+        .set_rate = tegra30_blink_clk_set_rate,
+};
 
-static void tegra30_utmi_param_configure(struct clk *c)
+static void tegra30_utmi_param_configure(struct clk_hw *hw)
 {
+        unsigned long main_rate =
+                __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
         u32 reg;
         int i;
-        unsigned long main_rate =
-                clk_get_rate(c->parent->parent);
 
         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
                 if (main_rate == utmi_parameters[i].osc_frequency)
@@ -886,50 +975,52 @@ static void tegra30_utmi_param_configure(struct clk *c)
         clk_writel(reg, UTMIP_PLL_CFG1);
 }
 
-static void tegra30_pll_clk_init(struct clk *c)
+/* PLL Functions */
+static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
+                                         u32 lock_bit)
+{
+        int ret = 0;
+
+#if USE_PLL_LOCK_BITS
+        int i;
+        for (i = 0; i < c->u.pll.lock_delay; i++) {
+                if (clk_readl(lock_reg) & lock_bit) {
+                        udelay(PLL_POST_LOCK_DELAY);
+                        return 0;
+                }
+                udelay(2);      /* timeout = 2 * lock time */
+        }
+        pr_err("Timed out waiting for lock bit on pll %s",
+                                        __clk_get_name(hw->clk));
+        ret = -1;
+#else
+        udelay(c->u.pll.lock_delay);
+#endif
+        return ret;
+}
+
+static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg + PLL_BASE);
 
         c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+        return c->state;
+}
 
-        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
-                const struct clk_pll_freq_table *sel;
-                unsigned long input_rate = clk_get_rate(c->parent);
-                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                        if (sel->input_rate == input_rate &&
-                                sel->output_rate == c->u.pll.fixed_rate) {
-                                c->mul = sel->n;
-                                c->div = sel->m * sel->p;
-                                return;
-                        }
-                }
-                pr_err("Clock %s has unknown fixed frequency\n", c->name);
-                BUG();
-        } else if (val & PLL_BASE_BYPASS) {
-                c->mul = 1;
-                c->div = 1;
-        } else {
-                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-                if (c->flags & PLLU)
-                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
-                else
-                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
-                                        PLL_BASE_DIVP_SHIFT));
-                if (c->flags & PLL_FIXED) {
-                        unsigned long rate = clk_get_rate_locked(c);
-                        BUG_ON(rate != c->u.pll.fixed_rate);
-                }
-        }
+static void tegra30_pll_clk_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
 
         if (c->flags & PLLU)
-                tegra30_utmi_param_configure(c);
+                tegra30_utmi_param_configure(hw);
 }
 
-static int tegra30_pll_clk_enable(struct clk *c)
+static int tegra30_pll_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 #if USE_PLL_LOCK_BITS
         val = clk_readl(c->reg + PLL_MISC(c));
@@ -952,10 +1043,11 @@ static int tegra30_pll_clk_enable(struct clk *c)
         return 0;
 }
 
-static void tegra30_pll_clk_disable(struct clk *c)
+static void tegra30_pll_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
         val = clk_readl(c->reg);
         val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
@@ -968,36 +1060,36 @@ static void tegra30_pll_clk_disable(struct clk *c)
         }
 }
 
-static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val, p_div, old_base;
         unsigned long input_rate;
         const struct clk_pll_freq_table *sel;
         struct clk_pll_freq_table cfg;
 
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
         if (c->flags & PLL_FIXED) {
                 int ret = 0;
                 if (rate != c->u.pll.fixed_rate) {
                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
-                               __func__, c->name, c->u.pll.fixed_rate, rate);
+                               __func__, __clk_get_name(hw->clk),
+                                c->u.pll.fixed_rate, rate);
                         ret = -EINVAL;
                 }
                 return ret;
         }
 
         if (c->flags & PLLM) {
-                if (rate != clk_get_rate_locked(c)) {
+                if (rate != __clk_get_rate(hw->clk)) {
                         pr_err("%s: Can not change memory %s rate in flight\n",
-                               __func__, c->name);
+                                __func__, __clk_get_name(hw->clk));
                         return -EINVAL;
                 }
-                return 0;
         }
 
         p_div = 0;
-        input_rate = clk_get_rate(c->parent);
+        input_rate = parent_rate;
 
         /* Check if the target rate is tabulated */
         for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
@@ -1055,7 +1147,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
                     (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
                     (cfg.output_rate > c->u.pll.vco_max)) {
                         pr_err("%s: Failed to set %s out-of-table rate %lu\n",
-                               __func__, c->name, rate);
+                               __func__, __clk_get_name(hw->clk), rate);
                         return -EINVAL;
                 }
                 p_div <<= PLL_BASE_DIVP_SHIFT;
@@ -1073,7 +1165,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
                 return 0;
 
         if (c->state == ON) {
-                tegra30_pll_clk_disable(c);
+                tegra30_pll_clk_disable(hw);
                 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
         }
         clk_writel(val, c->reg + PLL_BASE);
@@ -1095,21 +1187,149 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
         }
 
         if (c->state == ON)
-                tegra30_pll_clk_enable(c);
+                tegra30_pll_clk_enable(hw);
+
+        c->u.pll.fixed_rate = rate;
 
         return 0;
 }
 
-static struct clk_ops tegra_pll_ops = {
-        .init                   = tegra30_pll_clk_init,
-        .enable                 = tegra30_pll_clk_enable,
-        .disable                = tegra30_pll_clk_disable,
-        .set_rate               = tegra30_pll_clk_set_rate,
+static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long input_rate = *prate;
+        unsigned long output_rate = *prate;
+        const struct clk_pll_freq_table *sel;
+        struct clk_pll_freq_table cfg;
+        int mul;
+        int div;
+        u32 p_div;
+        u32 val;
+
+        if (c->flags & PLL_FIXED)
+                return c->u.pll.fixed_rate;
+
+        if (c->flags & PLLM)
+                return __clk_get_rate(hw->clk);
+
+        p_div = 0;
+        /* Check if the target rate is tabulated */
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        if (c->flags & PLLU) {
+                                BUG_ON(sel->p < 1 || sel->p > 2);
+                                if (sel->p == 1)
+                                        p_div = PLLU_BASE_POST_DIV;
+                        } else {
+                                BUG_ON(sel->p < 1);
+                                for (val = sel->p; val > 1; val >>= 1)
+                                        p_div++;
+                                p_div <<= PLL_BASE_DIVP_SHIFT;
+                        }
+                        break;
+                }
+        }
+
+        if (sel->input_rate == 0) {
+                unsigned long cfreq;
+                BUG_ON(c->flags & PLLU);
+                sel = &cfg;
+
+                switch (input_rate) {
+                case 12000000:
+                case 26000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+                        break;
+                case 13000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+                        break;
+                case 16800000:
+                case 19200000:
+                        cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+                        break;
+                default:
+                        pr_err("%s: Unexpected reference rate %lu\n",
+                               __func__, input_rate);
+                        BUG();
+                }
+
+                /* Raise VCO to guarantee 0.5% accuracy */
+                for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
+                      cfg.output_rate <<= 1)
+                        p_div++;
+
+                cfg.p = 0x1 << p_div;
+                cfg.m = input_rate / cfreq;
+                cfg.n = cfg.output_rate / cfreq;
+        }
+
+        mul = sel->n;
+        div = sel->m * sel->p;
+
+        output_rate *= mul;
+        output_rate += div - 1; /* round up */
+        do_div(output_rate, div);
+
+        return output_rate;
+}
+
+static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        u32 val = clk_readl(c->reg + PLL_BASE);
+
+        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+                const struct clk_pll_freq_table *sel;
+                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                        if (sel->input_rate == parent_rate &&
+                                sel->output_rate == c->u.pll.fixed_rate) {
+                                c->mul = sel->n;
+                                c->div = sel->m * sel->p;
+                                break;
+                        }
+                }
+                pr_err("Clock %s has unknown fixed frequency\n",
+                                                __clk_get_name(hw->clk));
+                BUG();
+        } else if (val & PLL_BASE_BYPASS) {
+                c->mul = 1;
+                c->div = 1;
+        } else {
+                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+                if (c->flags & PLLU)
+                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+                else
+                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
+                                        PLL_BASE_DIVP_SHIFT));
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+struct clk_ops tegra30_pll_ops = {
+        .is_enabled = tegra30_pll_clk_is_enabled,
+        .init = tegra30_pll_clk_init,
+        .enable = tegra30_pll_clk_enable,
+        .disable = tegra30_pll_clk_disable,
+        .recalc_rate = tegra30_pll_recalc_rate,
+        .round_rate = tegra30_pll_round_rate,
+        .set_rate = tegra30_pll_clk_set_rate,
 };
 
-static int
-tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val, mask, reg;
 
         switch (p) {
@@ -1141,41 +1361,27 @@ tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
         return 0;
 }
 
-static struct clk_ops tegra_plld_ops = {
-        .init                   = tegra30_pll_clk_init,
-        .enable                 = tegra30_pll_clk_enable,
-        .disable                = tegra30_pll_clk_disable,
-        .set_rate               = tegra30_pll_clk_set_rate,
-        .clk_cfg_ex             = tegra30_plld_clk_cfg_ex,
-};
-
-static void tegra30_plle_clk_init(struct clk *c)
+static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
 
-        val = clk_readl(PLLE_AUX);
-        c->parent = (val & PLLE_AUX_PLLP_SEL) ?
-                tegra_get_clock_by_name("pll_p") :
-                tegra_get_clock_by_name("pll_ref");
-
         val = clk_readl(c->reg + PLL_BASE);
         c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
-        c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
-        c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
-        c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+        return c->state;
 }
 
-static void tegra30_plle_clk_disable(struct clk *c)
+static void tegra30_plle_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
 
         val = clk_readl(c->reg + PLL_BASE);
         val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
         clk_writel(val, c->reg + PLL_BASE);
 }
 
-static void tegra30_plle_training(struct clk *c)
+static void tegra30_plle_training(struct clk_tegra *c)
 {
         u32 val;
 
@@ -1198,12 +1404,15 @@ static void tegra30_plle_training(struct clk *c)
         } while (!(val & PLLE_MISC_READY));
 }
 
-static int tegra30_plle_configure(struct clk *c, bool force_training)
+static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
 {
-        u32 val;
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk *parent = __clk_get_parent(hw->clk);
         const struct clk_pll_freq_table *sel;
+        u32 val;
+
         unsigned long rate = c->u.pll.fixed_rate;
-        unsigned long input_rate = clk_get_rate(c->parent);
+        unsigned long input_rate = __clk_get_rate(parent);
 
         for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
                 if (sel->input_rate == input_rate && sel->output_rate == rate)
@@ -1214,7 +1423,7 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
                 return -ENOSYS;
 
         /* disable PLLE, clear setup fiels */
-        tegra30_plle_clk_disable(c);
+        tegra30_plle_clk_disable(hw);
 
         val = clk_readl(c->reg + PLL_MISC(c));
         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
@@ -1252,52 +1461,64 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
         return 0;
 }
 
-static int tegra30_plle_clk_enable(struct clk *c)
+static int tegra30_plle_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        return tegra30_plle_configure(hw, !c->set);
+}
+
+static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long parent_rate)
 {
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        return tegra30_plle_configure(c, !c->set);
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long rate = parent_rate;
+        u32 val;
+
+        val = clk_readl(c->reg + PLL_BASE);
+        c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
+        c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
+        c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
 }
 
-static struct clk_ops tegra_plle_ops = {
-        .init                   = tegra30_plle_clk_init,
-        .enable                 = tegra30_plle_clk_enable,
-        .disable                = tegra30_plle_clk_disable,
+struct clk_ops tegra30_plle_ops = {
+        .is_enabled = tegra30_plle_clk_is_enabled,
+        .enable = tegra30_plle_clk_enable,
+        .disable = tegra30_plle_clk_disable,
+        .recalc_rate = tegra30_plle_clk_recalc_rate,
 };
 
 /* Clock divider ops */
-static void tegra30_pll_div_clk_init(struct clk *c)
+static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (c->flags & DIV_U71) {
-                u32 divu71;
                 u32 val = clk_readl(c->reg);
                 val >>= c->reg_shift;
                 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
                 if (!(val & PLL_OUT_RESET_DISABLE))
                         c->state = OFF;
-
-                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
-                c->div = (divu71 + 2);
-                c->mul = 2;
-        } else if (c->flags & DIV_2) {
-                c->state = ON;
-                if (c->flags & (PLLD | PLLX)) {
-                        c->div = 2;
-                        c->mul = 1;
-                } else
-                        BUG();
         } else {
                 c->state = ON;
-                c->div = 1;
-                c->mul = 1;
         }
+        return c->state;
 }
 
-static int tegra30_pll_div_clk_enable(struct clk *c)
+static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         u32 new_val;
 
-        pr_debug("%s: %s\n", __func__, c->name);
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
         if (c->flags & DIV_U71) {
                 val = clk_readl(c->reg);
                 new_val = val >> c->reg_shift;
@@ -1315,12 +1536,13 @@ static int tegra30_pll_div_clk_enable(struct clk *c)
         return -EINVAL;
 }
 
-static void tegra30_pll_div_clk_disable(struct clk *c)
+static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         u32 new_val;
 
-        pr_debug("%s: %s\n", __func__, c->name);
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
         if (c->flags & DIV_U71) {
                 val = clk_readl(c->reg);
                 new_val = val >> c->reg_shift;
@@ -1334,14 +1556,14 @@ static void tegra30_pll_div_clk_disable(struct clk *c)
         }
 }
 
-static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         u32 new_val;
         int divider_u71;
-        unsigned long parent_rate = clk_get_rate(c->parent);
 
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
         if (c->flags & DIV_U71) {
                 divider_u71 = clk_div71_get_divider(
                         parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
@@ -1359,19 +1581,59 @@ static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
                         clk_writel_delay(val, c->reg);
                         c->div = divider_u71 + 2;
                         c->mul = 2;
+                        c->fixed_rate = rate;
                         return 0;
                 }
-        } else if (c->flags & DIV_2)
-                return clk_set_rate(c->parent, rate * 2);
+        } else if (c->flags & DIV_2) {
+                c->fixed_rate = rate;
+                return 0;
+        }
 
         return -EINVAL;
 }
 
-static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+
+        if (c->flags & DIV_U71) {
+                u32 divu71;
+                u32 val = clk_readl(c->reg);
+                val >>= c->reg_shift;
+
+                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+                c->div = (divu71 + 2);
+                c->mul = 2;
+        } else if (c->flags & DIV_2) {
+                if (c->flags & (PLLD | PLLX)) {
+                        c->div = 2;
+                        c->mul = 1;
+                } else
+                        BUG();
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
+                                unsigned long rate, unsigned long *prate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
         int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (prate)
+                parent_rate = *prate;
 
         if (c->flags & DIV_U71) {
                 divider = clk_div71_get_divider(
@@ -1379,23 +1641,25 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
                 if (divider < 0)
                         return divider;
                 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_2)
-                /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
+        } else if (c->flags & DIV_2) {
+                *prate = rate * 2;
                 return rate;
+        }
 
         return -EINVAL;
 }
 
-static struct clk_ops tegra_pll_div_ops = {
-        .init                   = tegra30_pll_div_clk_init,
-        .enable                 = tegra30_pll_div_clk_enable,
-        .disable                = tegra30_pll_div_clk_disable,
-        .set_rate               = tegra30_pll_div_clk_set_rate,
-        .round_rate             = tegra30_pll_div_clk_round_rate,
+struct clk_ops tegra30_pll_div_ops = {
+        .is_enabled = tegra30_pll_div_clk_is_enabled,
+        .enable = tegra30_pll_div_clk_enable,
+        .disable = tegra30_pll_div_clk_disable,
+        .set_rate = tegra30_pll_div_clk_set_rate,
+        .recalc_rate = tegra30_pll_div_clk_recalc_rate,
+        .round_rate = tegra30_pll_div_clk_round_rate,
 };
 
 /* Periph clk ops */
-static inline u32 periph_clk_source_mask(struct clk *c)
+static inline u32 periph_clk_source_mask(struct clk_tegra *c)
 {
         if (c->flags & MUX8)
                 return 7 << 29;
@@ -1409,7 +1673,7 @@ static inline u32 periph_clk_source_mask(struct clk *c)
                 return 3 << 30;
 }
 
-static inline u32 periph_clk_source_shift(struct clk *c)
+static inline u32 periph_clk_source_shift(struct clk_tegra *c)
 {
         if (c->flags & MUX8)
                 return 29;
@@ -1423,47 +1687,9 @@ static inline u32 periph_clk_source_shift(struct clk *c)
                 return 30;
 }
 
-static void tegra30_periph_clk_init(struct clk *c)
+static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
 {
-        u32 val = clk_readl(c->reg);
-        const struct clk_mux_sel *mux = 0;
-        const struct clk_mux_sel *sel;
-        if (c->flags & MUX) {
-                for (sel = c->inputs; sel->input != NULL; sel++) {
-                        if (((val & periph_clk_source_mask(c)) >>
-                            periph_clk_source_shift(c)) == sel->value)
-                                mux = sel;
-                }
-                BUG_ON(!mux);
-
-                c->parent = mux->input;
-        } else {
-                c->parent = c->inputs[0].input;
-        }
-
-        if (c->flags & DIV_U71) {
-                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-                if ((c->flags & DIV_U71_UART) &&
-                    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
-                        divu71 = 0;
-                }
-                if (c->flags & DIV_U71_IDLE) {
-                        val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
-                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-                        val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
-                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-                        clk_writel(val, c->reg);
-                }
-                c->div = divu71 + 2;
-                c->mul = 2;
-        } else if (c->flags & DIV_U16) {
-                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-                c->div = divu16 + 1;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
+        struct clk_tegra *c = to_clk_tegra(hw);
 
         c->state = ON;
         if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
@@ -1471,11 +1697,12 @@ static void tegra30_periph_clk_init(struct clk *c)
         if (!(c->flags & PERIPH_NO_RESET))
                 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
                         c->state = OFF;
+        return c->state;
 }
 
-static int tegra30_periph_clk_enable(struct clk *c)
+static int tegra30_periph_clk_enable(struct clk_hw *hw)
 {
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        struct clk_tegra *c = to_clk_tegra(hw);
 
         tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
         if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
@@ -1494,31 +1721,29 @@ static int tegra30_periph_clk_enable(struct clk *c)
         return 0;
 }
 
-static void tegra30_periph_clk_disable(struct clk *c)
+static void tegra30_periph_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         unsigned long val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
 
-        if (c->refcnt)
-                tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+                return;
 
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
-                /* If peripheral is in the APB bus then read the APB bus to
-                 * flush the write operation in apb bus. This will avoid the
-                 * peripheral access after disabling clock*/
-                if (c->flags & PERIPH_ON_APB)
-                        val = chipid_readl();
+        /* If peripheral is in the APB bus then read the APB bus to
+         * flush the write operation in apb bus. This will avoid the
+         * peripheral access after disabling clock*/
+        if (c->flags & PERIPH_ON_APB)
+                val = chipid_readl();
 
-                clk_writel_delay(
-                        PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
-        }
+        clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
 }
 
-static void tegra30_periph_clk_reset(struct clk *c, bool assert)
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         unsigned long val;
-        pr_debug("%s %s on clock %s\n", __func__,
-                 assert ? "assert" : "deassert", c->name);
 
         if (!(c->flags & PERIPH_NO_RESET)) {
                 if (assert) {
@@ -1537,42 +1762,40 @@ static void tegra30_periph_clk_reset(struct clk *c, bool assert)
         }
 }
 
-static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        const struct clk_mux_sel *sel;
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
 
         if (!(c->flags & MUX))
-                return (p == c->parent) ? 0 : (-EINVAL);
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~periph_clk_source_mask(c);
-                        val |= (sel->value << periph_clk_source_shift(c));
-
-                        if (c->refcnt)
-                                clk_enable(p);
+                return (index == 0) ? 0 : (-EINVAL);
 
-                        clk_writel_delay(val, c->reg);
+        val = clk_readl(c->reg);
+        val &= ~periph_clk_source_mask(c);
+        val |= (index << periph_clk_source_shift(c));
+        clk_writel_delay(val, c->reg);
+        return 0;
+}
 
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
+static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        int source  = (val & periph_clk_source_mask(c)) >>
+                                        periph_clk_source_shift(c);
 
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
+        if (!(c->flags & MUX))
+                return 0;
 
-        return -EINVAL;
+        return source;
 }
 
-static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
 
         if (c->flags & DIV_U71) {
                 divider = clk_div71_get_divider(
@@ -1611,12 +1834,15 @@ static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
         return -EINVAL;
 }
 
-static long tegra30_periph_clk_round_rate(struct clk *c,
-        unsigned long rate)
+static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
         int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (prate)
+                parent_rate = *prate;
 
         if (c->flags & DIV_U71) {
                 divider = clk_div71_get_divider(
@@ -1634,21 +1860,85 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
         return -EINVAL;
 }
 
-static struct clk_ops tegra_periph_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
+static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        u32 val = clk_readl(c->reg);
+
+        if (c->flags & DIV_U71) {
+                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+                if ((c->flags & DIV_U71_UART) &&
+                    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
+                        divu71 = 0;
+                }
+                if (c->flags & DIV_U71_IDLE) {
+                        val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        clk_writel(val, c->reg);
+                }
+                c->div = divu71 + 2;
+                c->mul = 2;
+        } else if (c->flags & DIV_U16) {
+                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+                c->div = divu16 + 1;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+
+struct clk_ops tegra30_periph_clk_ops = {
+        .is_enabled = tegra30_periph_clk_is_enabled,
+        .enable = tegra30_periph_clk_enable,
+        .disable = tegra30_periph_clk_disable,
+        .set_parent = tegra30_periph_clk_set_parent,
+        .get_parent = tegra30_periph_clk_get_parent,
+        .set_rate = tegra30_periph_clk_set_rate,
+        .round_rate = tegra30_periph_clk_round_rate,
+        .recalc_rate = tegra30_periph_clk_recalc_rate,
+};
+
+static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk *d = clk_get_sys(NULL, "pll_d");
+        /* The DSIB parent selection bit is in PLLD base
+           register - can not do direct r-m-w, must be
+           protected by PLLD lock */
+        tegra_clk_cfg_ex(
+                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
+
+        return 0;
+}
+
+struct clk_ops tegra30_dsib_clk_ops = {
+        .is_enabled = tegra30_periph_clk_is_enabled,
         .enable                 = &tegra30_periph_clk_enable,
         .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_parent             = &tegra30_dsib_clk_set_parent,
+        .get_parent             = &tegra30_periph_clk_get_parent,
         .set_rate               = &tegra30_periph_clk_set_rate,
         .round_rate             = &tegra30_periph_clk_round_rate,
-        .reset                  = &tegra30_periph_clk_reset,
+        .recalc_rate            = &tegra30_periph_clk_recalc_rate,
 };
 
-
 /* Periph extended clock configuration ops */
-static int
-tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (p == TEGRA_CLK_VI_INP_SEL) {
                 u32 val = clk_readl(c->reg);
                 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
@@ -1660,20 +1950,11 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
         return -EINVAL;
 }
 
-static struct clk_ops tegra_vi_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .clk_cfg_ex             = &tegra30_vi_clk_cfg_ex,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-
-static int
-tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
                 u32 val = clk_readl(c->reg);
                 if (setting)
@@ -1686,21 +1967,11 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
         return -EINVAL;
 }
 
-static struct clk_ops tegra_nand_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .clk_cfg_ex             = &tegra30_nand_clk_cfg_ex,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-
-
-static int
-tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (p == TEGRA_CLK_DTV_INVERT) {
                 u32 val = clk_readl(c->reg);
                 if (setting)
@@ -1713,91 +1984,27 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
         return -EINVAL;
 }
 
-static struct clk_ops tegra_dtv_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .clk_cfg_ex             = &tegra30_dtv_clk_cfg_ex,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-
-static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
-{
-        const struct clk_mux_sel *sel;
-        struct clk *d = tegra_get_clock_by_name("pll_d");
-
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        /* The DSIB parent selection bit is in PLLD base
-                           register - can not do direct r-m-w, must be
-                           protected by PLLD lock */
-                        tegra_clk_cfg_ex(
-                                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
-
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_dsib_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_dsib_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-
-/* pciex clock support only reset function */
-static struct clk_ops tegra_pciex_clk_ops = {
-        .reset    = tegra30_periph_clk_reset,
-};
-
 /* Output clock ops */
 
 static DEFINE_SPINLOCK(clk_out_lock);
 
-static void tegra30_clk_out_init(struct clk *c)
+static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
 {
-        const struct clk_mux_sel *mux = 0;
-        const struct clk_mux_sel *sel;
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = pmc_readl(c->reg);
 
         c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
         c->mul = 1;
         c->div = 1;
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (((val & periph_clk_source_mask(c)) >>
-                     periph_clk_source_shift(c)) == sel->value)
-                        mux = sel;
-        }
-        BUG_ON(!mux);
-        c->parent = mux->input;
+        return c->state;
 }
 
-static int tegra30_clk_out_enable(struct clk *c)
+static int tegra30_clk_out_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         unsigned long flags;
 
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
         spin_lock_irqsave(&clk_out_lock, flags);
         val = pmc_readl(c->reg);
         val |= (0x1 << c->u.periph.clk_num);
@@ -1807,13 +2014,12 @@ static int tegra30_clk_out_enable(struct clk *c)
         return 0;
 }
 
-static void tegra30_clk_out_disable(struct clk *c)
+static void tegra30_clk_out_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         unsigned long flags;
 
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
         spin_lock_irqsave(&clk_out_lock, flags);
         val = pmc_readl(c->reg);
         val &= ~(0x1 << c->u.periph.clk_num);
@@ -1821,59 +2027,59 @@ static void tegra30_clk_out_disable(struct clk *c)
         spin_unlock_irqrestore(&clk_out_lock, flags);
 }
 
-static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
+static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         unsigned long flags;
-        const struct clk_mux_sel *sel;
 
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        if (c->refcnt)
-                                clk_enable(p);
+        spin_lock_irqsave(&clk_out_lock, flags);
+        val = pmc_readl(c->reg);
+        val &= ~periph_clk_source_mask(c);
+        val |= (index << periph_clk_source_shift(c));
+        pmc_writel(val, c->reg);
+        spin_unlock_irqrestore(&clk_out_lock, flags);
 
-                        spin_lock_irqsave(&clk_out_lock, flags);
-                        val = pmc_readl(c->reg);
-                        val &= ~periph_clk_source_mask(c);
-                        val |= (sel->value << periph_clk_source_shift(c));
-                        pmc_writel(val, c->reg);
-                        spin_unlock_irqrestore(&clk_out_lock, flags);
+        return 0;
+}
 
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
+static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = pmc_readl(c->reg);
+        int source;
 
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-        return -EINVAL;
+        source = (val & periph_clk_source_mask(c)) >>
+                                periph_clk_source_shift(c);
+        return source;
 }
 
-static struct clk_ops tegra_clk_out_ops = {
-        .init                   = &tegra30_clk_out_init,
-        .enable                 = &tegra30_clk_out_enable,
-        .disable                = &tegra30_clk_out_disable,
-        .set_parent             = &tegra30_clk_out_set_parent,
+struct clk_ops tegra_clk_out_ops = {
+        .is_enabled = tegra30_clk_out_is_enabled,
+        .enable = tegra30_clk_out_enable,
+        .disable = tegra30_clk_out_disable,
+        .set_parent = tegra30_clk_out_set_parent,
+        .get_parent = tegra30_clk_out_get_parent,
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
-
 /* Clock doubler ops */
-static void tegra30_clk_double_init(struct clk *c)
+static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
 {
-        u32 val = clk_readl(c->reg);
-        c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
-        c->div = 1;
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         c->state = ON;
         if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
                 c->state = OFF;
+        return c->state;
 };
 
-static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        unsigned long parent_rate = clk_get_rate(c->parent);
+
         if (rate == parent_rate) {
                 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
                 clk_writel(val, c->reg);
@@ -1890,1215 +2096,200 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
         return -EINVAL;
 }
 
-static struct clk_ops tegra_clk_double_ops = {
-        .init                   = &tegra30_clk_double_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_rate               = &tegra30_clk_double_set_rate,
-};
+static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
 
-/* Audio sync clock ops */
-static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
+        u32 val = clk_readl(c->reg);
+        c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
+        c->div = 1;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
 {
-        c->rate = rate;
-        return 0;
+        unsigned long output_rate = *prate;
+
+        do_div(output_rate, 2);
+        return output_rate;
 }
 
-static struct clk_ops tegra_sync_source_ops = {
-        .set_rate               = &tegra30_sync_source_set_rate,
+struct clk_ops tegra30_clk_double_ops = {
+        .is_enabled = tegra30_clk_double_is_enabled,
+        .enable = tegra30_periph_clk_enable,
+        .disable = tegra30_periph_clk_disable,
+        .recalc_rate = tegra30_clk_double_recalc_rate,
+        .round_rate = tegra30_clk_double_round_rate,
+        .set_rate = tegra30_clk_double_set_rate,
+};
+
+/* Audio sync clock ops */
+struct clk_ops tegra_sync_source_ops = {
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
-static void tegra30_audio_sync_clk_init(struct clk *c)
+static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
 {
-        int source;
-        const struct clk_mux_sel *sel;
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg);
         c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
-        source = val & AUDIO_SYNC_SOURCE_MASK;
-        for (sel = c->inputs; sel->input != NULL; sel++)
-                if (sel->value == source)
-                        break;
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
+        return c->state;
 }
 
-static int tegra30_audio_sync_clk_enable(struct clk *c)
+static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg);
         clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
         return 0;
 }
 
-static void tegra30_audio_sync_clk_disable(struct clk *c)
+static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg);
         clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
 }
 
-static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        const struct clk_mux_sel *sel;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~AUDIO_SYNC_SOURCE_MASK;
-                        val |= sel->value;
-
-                        if (c->refcnt)
-                                clk_enable(p);
 
-                        clk_writel(val, c->reg);
+        val = clk_readl(c->reg);
+        val &= ~AUDIO_SYNC_SOURCE_MASK;
+        val |= index;
 
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
+        clk_writel(val, c->reg);
+        return 0;
+}
 
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
+static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        int source;
 
-        return -EINVAL;
+        source = val & AUDIO_SYNC_SOURCE_MASK;
+        return source;
 }
 
-static struct clk_ops tegra_audio_sync_clk_ops = {
-        .init       = tegra30_audio_sync_clk_init,
-        .enable     = tegra30_audio_sync_clk_enable,
-        .disable    = tegra30_audio_sync_clk_disable,
+struct clk_ops tegra30_audio_sync_clk_ops = {
+        .is_enabled = tegra30_audio_sync_clk_is_enabled,
+        .enable = tegra30_audio_sync_clk_enable,
+        .disable = tegra30_audio_sync_clk_disable,
         .set_parent = tegra30_audio_sync_clk_set_parent,
+        .get_parent = tegra30_audio_sync_clk_get_parent,
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
 /* cml0 (pcie), and cml1 (sata) clock ops */
-static void tegra30_cml_clk_init(struct clk *c)
+static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg);
         c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
+        return c->state;
 }
 
-static int tegra30_cml_clk_enable(struct clk *c)
+static int tegra30_cml_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         u32 val = clk_readl(c->reg);
         val |= (0x1 << c->u.periph.clk_num);
         clk_writel(val, c->reg);
+
         return 0;
 }
 
-static void tegra30_cml_clk_disable(struct clk *c)
+static void tegra30_cml_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         u32 val = clk_readl(c->reg);
         val &= ~(0x1 << c->u.periph.clk_num);
         clk_writel(val, c->reg);
 }
 
-static struct clk_ops tegra_cml_clk_ops = {
-        .init                   = &tegra30_cml_clk_init,
-        .enable                 = &tegra30_cml_clk_enable,
-        .disable                = &tegra30_cml_clk_disable,
-};
-
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
-        .name = "clk_32k",
-        .rate = 32768,
-        .ops  = NULL,
-        .max_rate = 32768,
-};
-
-static struct clk tegra_clk_m = {
-        .name      = "clk_m",
-        .flags     = ENABLE_ON_INIT,
-        .ops       = &tegra_clk_m_ops,
-        .reg       = 0x1fc,
-        .reg_shift = 28,
-        .max_rate  = 48000000,
-};
-
-static struct clk tegra_clk_m_div2 = {
-        .name      = "clk_m_div2",
-        .ops       = &tegra_clk_m_div_ops,
-        .parent    = &tegra_clk_m,
-        .mul       = 1,
-        .div       = 2,
-        .state     = ON,
-        .max_rate  = 24000000,
-};
-
-static struct clk tegra_clk_m_div4 = {
-        .name      = "clk_m_div4",
-        .ops       = &tegra_clk_m_div_ops,
-        .parent    = &tegra_clk_m,
-        .mul       = 1,
-        .div       = 4,
-        .state     = ON,
-        .max_rate  = 12000000,
-};
-
-static struct clk tegra_pll_ref = {
-        .name      = "pll_ref",
-        .flags     = ENABLE_ON_INIT,
-        .ops       = &tegra_pll_ref_ops,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 26000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-        { 12000000, 1040000000, 520,  6, 1, 8},
-        { 13000000, 1040000000, 480,  6, 1, 8},
-        { 16800000, 1040000000, 495,  8, 1, 8},         /* actual: 1039.5 MHz */
-        { 19200000, 1040000000, 325,  6, 1, 6},
-        { 26000000, 1040000000, 520, 13, 1, 8},
-
-        { 12000000, 832000000, 416,  6, 1, 8},
-        { 13000000, 832000000, 832, 13, 1, 8},
-        { 16800000, 832000000, 396,  8, 1, 8},          /* actual: 831.6 MHz */
-        { 19200000, 832000000, 260,  6, 1, 8},
-        { 26000000, 832000000, 416, 13, 1, 8},
-
-        { 12000000, 624000000, 624, 12, 1, 8},
-        { 13000000, 624000000, 624, 13, 1, 8},
-        { 16800000, 600000000, 520, 14, 1, 8},
-        { 19200000, 624000000, 520, 16, 1, 8},
-        { 26000000, 624000000, 624, 26, 1, 8},
-
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-
-        { 12000000, 520000000, 520, 12, 1, 8},
-        { 13000000, 520000000, 520, 13, 1, 8},
-        { 16800000, 520000000, 495, 16, 1, 8},          /* actual: 519.75 MHz */
-        { 19200000, 520000000, 325, 12, 1, 6},
-        { 26000000, 520000000, 520, 26, 1, 8},
-
-        { 12000000, 416000000, 416, 12, 1, 8},
-        { 13000000, 416000000, 416, 13, 1, 8},
-        { 16800000, 416000000, 396, 16, 1, 8},          /* actual: 415.8 MHz */
-        { 19200000, 416000000, 260, 12, 1, 6},
-        { 26000000, 416000000, 416, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_c = {
-        .name      = "pll_c",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x80,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1400000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_c_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_c_out1 = {
-        .name      = "pll_c_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_c,
-        .reg       = 0x84,
-        .reg_shift = 0,
-        .max_rate  = 700000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 16800000, 666000000, 555, 14, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_m = {
-        .name      = "pll_m",
-        .flags     = PLL_HAS_CPCON | PLLM,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x90,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 800000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1200000000,
-                .freq_table = tegra_pll_m_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_m_out1 = {
-        .name      = "pll_m_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_m,
-        .reg       = 0x94,
-        .reg_shift = 0,
-        .max_rate  = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 16800000, 216000000, 360, 14, 2, 8},
-        { 19200000, 216000000, 360, 16, 2, 8},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_p = {
-        .name      = "pll_p",
-        .flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xa0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 432000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_p_freq_table,
-                .lock_delay = 300,
-                .fixed_rate = 408000000,
-        },
-};
-
-static struct clk tegra_pll_p_out1 = {
-        .name      = "pll_p_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
-        .name      = "pll_p_out2",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
-        .name      = "pll_p_out3",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
-        .name      = "pll_p_out4",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-        { 9600000, 564480000, 294, 5, 1, 4},
-        { 9600000, 552960000, 288, 5, 1, 4},
-        { 9600000, 24000000,  5,   2, 1, 1},
-
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_a = {
-        .name      = "pll_a",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xb0,
-        .parent    = &tegra_pll_p_out1,
-        .max_rate  = 700000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_a_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_a_out0 = {
-        .name      = "pll_a_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_a,
-        .reg       = 0xb4,
-        .reg_shift = 0,
-        .max_rate  = 100000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 16800000, 216000000, 180, 14, 1, 4},
-        { 19200000, 216000000, 180, 16, 1, 4},
-        { 26000000, 216000000, 216, 26, 1, 4},
-
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 16800000, 594000000, 495, 14, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_d = {
-        .name      = "pll_d",
-        .flags     = PLL_HAS_CPCON | PLLD,
-        .ops       = &tegra_plld_ops,
-        .reg       = 0xd0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 40000000,
-                .vco_max   = 1000000000,
-                .freq_table = tegra_pll_d_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk tegra_pll_d_out0 = {
-        .name      = "pll_d_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLD,
-        .parent    = &tegra_pll_d,
-        .max_rate  = 500000000,
-};
-
-static struct clk tegra_pll_d2 = {
-        .name      = "pll_d2",
-        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
-        .ops       = &tegra_plld_ops,
-        .reg       = 0x4b8,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 40000000,
-                .vco_max   = 1000000000,
-                .freq_table = tegra_pll_d_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk tegra_pll_d2_out0 = {
-        .name      = "pll_d2_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLD,
-        .parent    = &tegra_pll_d2,
-        .max_rate  = 500000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 12},
-        { 13000000, 480000000, 960, 13, 2, 12},
-        { 16800000, 480000000, 400, 7,  2, 5},
-        { 19200000, 480000000, 200, 4,  2, 3},
-        { 26000000, 480000000, 960, 26, 2, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_u = {
-        .name      = "pll_u",
-        .flags     = PLL_HAS_CPCON | PLLU,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xc0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 480000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 480000000,
-                .vco_max   = 960000000,
-                .freq_table = tegra_pll_u_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-        /* 1.7 GHz */
-        { 12000000, 1700000000, 850,  6,  1, 8},
-        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
-        { 26000000, 1700000000, 850,  13, 1, 8},
-
-        /* 1.6 GHz */
-        { 12000000, 1600000000, 800,  6,  1, 8},
-        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
-        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
-        { 19200000, 1600000000, 500,  6,  1, 8},
-        { 26000000, 1600000000, 800,  13, 1, 8},
-
-        /* 1.5 GHz */
-        { 12000000, 1500000000, 750,  6,  1, 8},
-        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
-        { 16800000, 1500000000, 625,  7,  1, 8},
-        { 19200000, 1500000000, 625,  8,  1, 8},
-        { 26000000, 1500000000, 750,  13, 1, 8},
-
-        /* 1.4 GHz */
-        { 12000000, 1400000000, 700,  6,  1, 8},
-        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
-        { 16800000, 1400000000, 1000, 12, 1, 8},
-        { 19200000, 1400000000, 875,  12, 1, 8},
-        { 26000000, 1400000000, 700,  13, 1, 8},
-
-        /* 1.3 GHz */
-        { 12000000, 1300000000, 975,  9,  1, 8},
-        { 13000000, 1300000000, 1000, 10, 1, 8},
-        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 26000000, 1300000000, 650,  13, 1, 8},
-
-        /* 1.2 GHz */
-        { 12000000, 1200000000, 1000, 10, 1, 8},
-        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
-        { 16800000, 1200000000, 1000, 14, 1, 8},
-        { 19200000, 1200000000, 1000, 16, 1, 8},
-        { 26000000, 1200000000, 600,  13, 1, 8},
-
-        /* 1.1 GHz */
-        { 12000000, 1100000000, 825,  9,  1, 8},
-        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
-        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
-        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
-        { 26000000, 1100000000, 550,  13, 1, 8},
-
-        /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 8},
-        { 13000000, 1000000000, 1000, 13, 1, 8},
-        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 8},
-
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_x = {
-        .name      = "pll_x",
-        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xe0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1700000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1700000000,
-                .freq_table = tegra_pll_x_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_x_out0 = {
-        .name      = "pll_x_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLX,
-        .parent    = &tegra_pll_x,
-        .max_rate  = 850000000,
-};
-
-
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-        /* PLLE special case: use cpcon field to store cml divider value */
-        { 12000000,  100000000, 150, 1,  18, 11},
-        { 216000000, 100000000, 200, 18, 24, 13},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_e = {
-        .name      = "pll_e",
-        .flags     = PLL_ALT_MISC_REG,
-        .ops       = &tegra_plle_ops,
-        .reg       = 0xe8,
-        .max_rate  = 100000000,
-        .u.pll = {
-                .input_min = 12000000,
-                .input_max = 216000000,
-                .cf_min    = 12000000,
-                .cf_max    = 12000000,
-                .vco_min   = 1200000000,
-                .vco_max   = 2400000000U,
-                .freq_table = tegra_pll_e_freq_table,
-                .lock_delay = 300,
-                .fixed_rate = 100000000,
-        },
-};
-
-static struct clk tegra_cml0_clk = {
-        .name      = "cml0",
-        .parent    = &tegra_pll_e,
-        .ops       = &tegra_cml_clk_ops,
-        .reg       = PLLE_AUX,
-        .max_rate  = 100000000,
-        .u.periph  = {
-                .clk_num = 0,
-        },
-};
-
-static struct clk tegra_cml1_clk = {
-        .name      = "cml1",
-        .parent    = &tegra_pll_e,
-        .ops       = &tegra_cml_clk_ops,
-        .reg       = PLLE_AUX,
-        .max_rate  = 100000000,
-        .u.periph  = {
-                .clk_num   = 1,
-        },
-};
-
-static struct clk tegra_pciex_clk = {
-        .name      = "pciex",
-        .parent    = &tegra_pll_e,
-        .ops       = &tegra_pciex_clk_ops,
-        .max_rate  = 100000000,
-        .u.periph  = {
-                .clk_num   = 74,
-        },
-};
-
-/* Audio sync clocks */
-#define SYNC_SOURCE(_id)                                \
-        {                                               \
-                .name      = #_id "_sync",              \
-                .rate      = 24000000,                  \
-                .max_rate  = 24000000,                  \
-                .ops       = &tegra_sync_source_ops     \
-        }
-static struct clk tegra_sync_source_list[] = {
-        SYNC_SOURCE(spdif_in),
-        SYNC_SOURCE(i2s0),
-        SYNC_SOURCE(i2s1),
-        SYNC_SOURCE(i2s2),
-        SYNC_SOURCE(i2s3),
-        SYNC_SOURCE(i2s4),
-        SYNC_SOURCE(vimclk),
-};
-
-static struct clk_mux_sel mux_audio_sync_clk[] = {
-        { .input = &tegra_sync_source_list[0],  .value = 0},
-        { .input = &tegra_sync_source_list[1],  .value = 1},
-        { .input = &tegra_sync_source_list[2],  .value = 2},
-        { .input = &tegra_sync_source_list[3],  .value = 3},
-        { .input = &tegra_sync_source_list[4],  .value = 4},
-        { .input = &tegra_sync_source_list[5],  .value = 5},
-        { .input = &tegra_pll_a_out0,           .value = 6},
-        { .input = &tegra_sync_source_list[6],  .value = 7},
-        { 0, 0 }
+struct clk_ops tegra_cml_clk_ops = {
+        .is_enabled = tegra30_cml_clk_is_enabled,
+        .enable = tegra30_cml_clk_enable,
+        .disable = tegra30_cml_clk_disable,
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
-#define AUDIO_SYNC_CLK(_id, _index)                     \
-        {                                               \
-                .name      = #_id,                      \
-                .inputs    = mux_audio_sync_clk,        \
-                .reg       = 0x4A0 + (_index) * 4,      \
-                .max_rate  = 24000000,                  \
-                .ops       = &tegra_audio_sync_clk_ops  \
-        }
-static struct clk tegra_clk_audio_list[] = {
-        AUDIO_SYNC_CLK(audio0, 0),
-        AUDIO_SYNC_CLK(audio1, 1),
-        AUDIO_SYNC_CLK(audio2, 2),
-        AUDIO_SYNC_CLK(audio3, 3),
-        AUDIO_SYNC_CLK(audio4, 4),
-        AUDIO_SYNC_CLK(audio, 5),       /* SPDIF */
+struct clk_ops tegra_pciex_clk_ops = {
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
-#define AUDIO_SYNC_2X_CLK(_id, _index)                          \
-        {                                                       \
-                .name      = #_id "_2x",                        \
-                .flags     = PERIPH_NO_RESET,                   \
-                .max_rate  = 48000000,                          \
-                .ops       = &tegra_clk_double_ops,             \
-                .reg       = 0x49C,                             \
-                .reg_shift = 24 + (_index),                     \
-                .parent    = &tegra_clk_audio_list[(_index)],   \
-                .u.periph = {                                   \
-                        .clk_num = 113 + (_index),              \
-                },                                              \
-        }
-static struct clk tegra_clk_audio_2x_list[] = {
-        AUDIO_SYNC_2X_CLK(audio0, 0),
-        AUDIO_SYNC_2X_CLK(audio1, 1),
-        AUDIO_SYNC_2X_CLK(audio2, 2),
-        AUDIO_SYNC_2X_CLK(audio3, 3),
-        AUDIO_SYNC_2X_CLK(audio4, 4),
-        AUDIO_SYNC_2X_CLK(audio, 5),    /* SPDIF */
-};
+/* Tegra30 CPU clock and reset control functions */
+static void tegra30_wait_cpu_in_reset(u32 cpu)
+{
+        unsigned int reg;
 
-#define MUX_I2S_SPDIF(_id, _index)                                      \
-static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = {       \
-        {.input = &tegra_pll_a_out0, .value = 0},                       \
-        {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1},      \
-        {.input = &tegra_pll_p, .value = 2},                            \
-        {.input = &tegra_clk_m, .value = 3},                            \
-        { 0, 0},                                                        \
-}
-MUX_I2S_SPDIF(audio0, 0);
-MUX_I2S_SPDIF(audio1, 1);
-MUX_I2S_SPDIF(audio2, 2);
-MUX_I2S_SPDIF(audio3, 3);
-MUX_I2S_SPDIF(audio4, 4);
-MUX_I2S_SPDIF(audio, 5);                /* SPDIF */
-
-/* External clock outputs (through PMC) */
-#define MUX_EXTERN_OUT(_id)                                             \
-static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = {        \
-        {.input = &tegra_clk_m,         .value = 0},                    \
-        {.input = &tegra_clk_m_div2,    .value = 1},                    \
-        {.input = &tegra_clk_m_div4,    .value = 2},                    \
-        {.input = NULL,                 .value = 3}, /* placeholder */  \
-        { 0, 0},                                                        \
-}
-MUX_EXTERN_OUT(1);
-MUX_EXTERN_OUT(2);
-MUX_EXTERN_OUT(3);
-
-static struct clk_mux_sel *mux_extern_out_list[] = {
-        mux_clkm_clkm2_clkm4_extern1,
-        mux_clkm_clkm2_clkm4_extern2,
-        mux_clkm_clkm2_clkm4_extern3,
-};
+        do {
+                reg = readl(reg_clk_base +
+                            TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+                cpu_relax();
+        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
 
-#define CLK_OUT_CLK(_id)                                        \
-        {                                                       \
-                .name      = "clk_out_" #_id,                   \
-                .lookup    = {                                  \
-                        .dev_id    = "clk_out_" #_id,           \
-                        .con_id    = "extern" #_id,             \
-                },                                              \
-                .ops       = &tegra_clk_out_ops,                \
-                .reg       = 0x1a8,                             \
-                .inputs    = mux_clkm_clkm2_clkm4_extern##_id,  \
-                .flags     = MUX_CLK_OUT,                       \
-                .max_rate  = 216000000,                         \
-                .u.periph = {                                   \
-                        .clk_num   = (_id - 1) * 8 + 2,         \
-                },                                              \
-        }
-static struct clk tegra_clk_out_list[] = {
-        CLK_OUT_CLK(1),
-        CLK_OUT_CLK(2),
-        CLK_OUT_CLK(3),
-};
+        return;
+}
 
-/* called after peripheral external clocks are initialized */
-static void init_clk_out_mux(void)
+static void tegra30_put_cpu_in_reset(u32 cpu)
 {
-        int i;
-        struct clk *c;
-
-        /* output clock con_id is the name of peripheral
-           external clock connected to input 3 of the output mux */
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
-                c = tegra_get_clock_by_name(
-                        tegra_clk_out_list[i].lookup.con_id);
-                if (!c)
-                        pr_err("%s: could not find clk %s\n", __func__,
-                               tegra_clk_out_list[i].lookup.con_id);
-                mux_extern_out_list[i][3].input = c;
-        }
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+        dmb();
 }
 
-/* Peripheral muxes */
-static struct clk_mux_sel mux_sclk[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c_out1,   .value = 1},
-        { .input = &tegra_pll_p_out4,   .value = 2},
-        { .input = &tegra_pll_p_out3,   .value = 3},
-        { .input = &tegra_pll_p_out2,   .value = 4},
-        /* { .input = &tegra_clk_d,     .value = 5}, - no use on tegra30 */
-        { .input = &tegra_clk_32k,      .value = 6},
-        { .input = &tegra_pll_m_out1,   .value = 7},
-        { 0, 0},
-};
-
-static struct clk tegra_clk_sclk = {
-        .name   = "sclk",
-        .inputs = mux_sclk,
-        .reg    = 0x28,
-        .ops    = &tegra_super_ops,
-        .max_rate = 334000000,
-        .min_rate = 40000000,
-};
-
-static struct clk tegra_clk_blink = {
-        .name           = "blink",
-        .parent         = &tegra_clk_32k,
-        .reg            = 0x40,
-        .ops            = &tegra_blink_clk_ops,
-        .max_rate       = 32768,
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-        { .input = &tegra_pll_m, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_pll_a_out0, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-        { .input = &tegra_pll_p, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_m, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_clkm[] = {
-        { .input = &tegra_pll_p, .value = 0},
-        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-        {.input = &tegra_pll_p, .value = 0},
-        {.input = &tegra_pll_d_out0, .value = 1},
-        {.input = &tegra_pll_c, .value = 2},
-        {.input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
-        {.input = &tegra_pll_p, .value = 0},
-        {.input = &tegra_pll_m, .value = 1},
-        {.input = &tegra_pll_d_out0, .value = 2},
-        {.input = &tegra_pll_a_out0, .value = 3},
-        {.input = &tegra_pll_c, .value = 4},
-        {.input = &tegra_pll_d2_out0, .value = 5},
-        {.input = &tegra_clk_m, .value = 6},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
-        { .input = &tegra_pll_a_out0, .value = 0},
-        /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_clk_32k,   .value = 2},
-        {.input = &tegra_clk_m,     .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_clk_m,     .value = 2},
-        {.input = &tegra_clk_32k,   .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_pll_m,     .value = 2},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_clk_m[] = {
-        { .input = &tegra_clk_m, .value = 0},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_out3[] = {
-        { .input = &tegra_pll_p_out3, .value = 0},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_plld_out0[] = {
-        { .input = &tegra_pll_d_out0, .value = 0},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
-        { .input = &tegra_pll_d_out0,  .value = 0},
-        { .input = &tegra_pll_d2_out0, .value = 1},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_clk_32k[] = {
-        { .input = &tegra_clk_32k, .value = 0},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
-        { .input = &tegra_pll_a_out0, .value = 0},
-        { .input = &tegra_clk_32k,    .value = 1},
-        { .input = &tegra_pll_p,      .value = 2},
-        { .input = &tegra_clk_m,      .value = 3},
-        { .input = &tegra_pll_e,      .value = 4},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_cclk_g[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c,        .value = 1},
-        { .input = &tegra_clk_32k,      .value = 2},
-        { .input = &tegra_pll_m,        .value = 3},
-        { .input = &tegra_pll_p,        .value = 4},
-        { .input = &tegra_pll_p_out4,   .value = 5},
-        { .input = &tegra_pll_p_out3,   .value = 6},
-        { .input = &tegra_pll_x,        .value = 8},
-        { 0, 0},
-};
-
-static struct clk tegra_clk_cclk_g = {
-        .name   = "cclk_g",
-        .flags  = DIV_U71 | DIV_U71_INT,
-        .inputs = mux_cclk_g,
-        .reg    = 0x368,
-        .ops    = &tegra_super_ops,
-        .max_rate = 1700000000,
-};
-
-static struct clk tegra30_clk_twd = {
-        .parent   = &tegra_clk_cclk_g,
-        .name     = "twd",
-        .ops      = &tegra30_twd_ops,
-        .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
-        .mul      = 1,
-        .div      = 2,
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_periph_clk_ops,     \
-                .reg       = _reg,                      \
-                .inputs    = _inputs,                   \
-                .flags     = _flags,                    \
-                .max_rate  = _max,                      \
-                .u.periph = {                           \
-                        .clk_num   = _clk_num,          \
-                },                                      \
-        }
-
-#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
-                        _flags, _ops)                                   \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = _ops,                      \
-                .reg       = _reg,                      \
-                .inputs    = _inputs,                   \
-                .flags     = _flags,                    \
-                .max_rate  = _max,                      \
-                .u.periph = {                           \
-                        .clk_num   = _clk_num,          \
-                },                                      \
-        }
-
-#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_clk_shared_bus_ops, \
-                .parent = _parent,                      \
-                .u.shared_bus_user = {                  \
-                        .client_id = _id,               \
-                        .client_div = _div,             \
-                        .mode = _mode,                  \
-                },                                      \
-        }
-struct clk tegra_list_clks[] = {
-        PERIPH_CLK("apbdma",    "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
-        PERIPH_CLK("kbc",       "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
-        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("kfuse",     "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("fuse",      "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB),
-        PERIPH_CLK("fuse_burn", "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB),
-        PERIPH_CLK("apbif",     "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("i2s0",      "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s1",      "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s2",      "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s3",      "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s4",      "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("spdif_out", "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio_2x_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("spdif_in",  "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("pwm",       "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("d_audio",   "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("dam0",      "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("dam1",      "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("dam2",      "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("hda",       "tegra30-hda",          "hda",   125,   0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("hda2codec_2x",      "tegra30-hda",  "hda2codec",   111,     0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("hda2hdmi",  "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0),
-        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc5",      "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc6",      "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0),
-        PERIPH_CLK_EX("ndflash", "tegra_nand",          NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71,  &tegra_nand_clk_ops),
-        PERIPH_CLK("ndspeed",   "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("vde",       "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
-        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
-        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c4",      "tegra-i2c.3",          NULL,   103,    0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c5",      "tegra-i2c.4",          NULL,   47,     0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("uarta",     "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartb",     "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartc",     "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartd",     "tegra-uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uarte",     "tegra-uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT,    &tegra_vi_clk_ops),
-        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-        PERIPH_CLK("3d2",       "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
-        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK_EX("dtv",    "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0,              &tegra_dtv_clk_ops),
-        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
-        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
-        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("dsia",      "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0),
-        PERIPH_CLK_EX("dsib",   "tegradc.1",            "dsib", 82,     0xd0,   500000000, mux_plld_out0_plld2_out0,    MUX | PLLD,     &tegra_dsib_clk_ops),
-        PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0),
-        PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
-        PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-
-        PERIPH_CLK("tsensor",   "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71),
-        PERIPH_CLK("actmon",    "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71),
-        PERIPH_CLK("extern1",   "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("extern2",   "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("extern3",   "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("i2cslow",   "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("pcie",      "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("afi",       "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("se",        "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con)                \
-        {                                               \
-                .name   = _name,                        \
-                .lookup = {                             \
-                        .dev_id = _dev,                 \
-                        .con_id         = _con,         \
-                },                                      \
-        }
-
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-struct clk_duplicate tegra_clk_duplicates[] = {
-        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
-        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
-        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
-        CLK_DUPLICATE("bsev", "nvavp", "bsev"),
-        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
-        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
-        CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
-        CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
-        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
-        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
-        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
-        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
-        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
-        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
-        CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
-        CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
-        CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
-        CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
-        CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
-        CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
-        CLK_DUPLICATE("twd", "smp_twd", NULL),
-        CLK_DUPLICATE("vcp", "nvavp", "vcp"),
-        CLK_DUPLICATE("i2s0", NULL, "i2s0"),
-        CLK_DUPLICATE("i2s1", NULL, "i2s1"),
-        CLK_DUPLICATE("i2s2", NULL, "i2s2"),
-        CLK_DUPLICATE("i2s3", NULL, "i2s3"),
-        CLK_DUPLICATE("i2s4", NULL, "i2s4"),
-        CLK_DUPLICATE("dam0", NULL, "dam0"),
-        CLK_DUPLICATE("dam1", NULL, "dam1"),
-        CLK_DUPLICATE("dam2", NULL, "dam2"),
-        CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
-};
-
-struct clk *tegra_ptr_clks[] = {
-        &tegra_clk_32k,
-        &tegra_clk_m,
-        &tegra_clk_m_div2,
-        &tegra_clk_m_div4,
-        &tegra_pll_ref,
-        &tegra_pll_m,
-        &tegra_pll_m_out1,
-        &tegra_pll_c,
-        &tegra_pll_c_out1,
-        &tegra_pll_p,
-        &tegra_pll_p_out1,
-        &tegra_pll_p_out2,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out4,
-        &tegra_pll_a,
-        &tegra_pll_a_out0,
-        &tegra_pll_d,
-        &tegra_pll_d_out0,
-        &tegra_pll_d2,
-        &tegra_pll_d2_out0,
-        &tegra_pll_u,
-        &tegra_pll_x,
-        &tegra_pll_x_out0,
-        &tegra_pll_e,
-        &tegra_clk_cclk_g,
-        &tegra_cml0_clk,
-        &tegra_cml1_clk,
-        &tegra_pciex_clk,
-        &tegra_clk_sclk,
-        &tegra_clk_blink,
-        &tegra30_clk_twd,
-};
-
-
-static void tegra30_init_one_clock(struct clk *c)
+static void tegra30_cpu_out_of_reset(u32 cpu)
 {
-        clk_init(c);
-        INIT_LIST_HEAD(&c->shared_bus_list);
-        if (!c->lookup.dev_id && !c->lookup.con_id)
-                c->lookup.con_id = c->name;
-        c->lookup.clk = c;
-        clkdev_add(&c->lookup);
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        wmb();
 }
 
-void __init tegra30_init_clocks(void)
+static void tegra30_enable_cpu_clock(u32 cpu)
 {
-        int i;
-        struct clk *c;
+        unsigned int reg;
 
-        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
-                tegra30_init_one_clock(tegra_ptr_clks[i]);
-
-        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-                tegra30_init_one_clock(&tegra_list_clks[i]);
+        writel(CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        reg = readl(reg_clk_base +
+                    TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
 
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-                if (!c) {
-                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                                tegra_clk_duplicates[i].name);
-                        continue;
-                }
+static void tegra30_disable_cpu_clock(u32 cpu)
+{
 
-                tegra_clk_duplicates[i].lookup.clk = c;
-                clkdev_add(&tegra_clk_duplicates[i].lookup);
-        }
+        unsigned int reg;
 
-        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
-                tegra30_init_one_clock(&tegra_sync_source_list[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
-                tegra30_init_one_clock(&tegra_clk_audio_list[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
-                tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg | CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
 
-        init_clk_out_mux();
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
-                tegra30_init_one_clock(&tegra_clk_out_list[i]);
+static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
+        .wait_for_reset = tegra30_wait_cpu_in_reset,
+        .put_in_reset   = tegra30_put_cpu_in_reset,
+        .out_of_reset   = tegra30_cpu_out_of_reset,
+        .enable_clock   = tegra30_enable_cpu_clock,
+        .disable_clock  = tegra30_disable_cpu_clock,
+};
 
+void __init tegra30_cpu_car_ops_init(void)
+{
+        tegra_cpu_car_ops = &tegra30_cpu_car_ops;
 }
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
new file mode 100644
index 000000000000..f2f88fef6b8b
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA30_CLOCK_H
+#define __MACH_TEGRA30_CLOCK_H
+
+extern struct clk_ops tegra30_clk_32k_ops;
+extern struct clk_ops tegra30_clk_m_ops;
+extern struct clk_ops tegra_clk_m_div_ops;
+extern struct clk_ops tegra_pll_ref_ops;
+extern struct clk_ops tegra30_pll_ops;
+extern struct clk_ops tegra30_pll_div_ops;
+extern struct clk_ops tegra_plld_ops;
+extern struct clk_ops tegra30_plle_ops;
+extern struct clk_ops tegra_cml_clk_ops;
+extern struct clk_ops tegra_pciex_clk_ops;
+extern struct clk_ops tegra_sync_source_ops;
+extern struct clk_ops tegra30_audio_sync_clk_ops;
+extern struct clk_ops tegra30_clk_double_ops;
+extern struct clk_ops tegra_clk_out_ops;
+extern struct clk_ops tegra30_super_ops;
+extern struct clk_ops tegra30_blink_clk_ops;
+extern struct clk_ops tegra30_twd_ops;
+extern struct clk_ops tegra30_periph_clk_ops;
+extern struct clk_ops tegra30_dsib_clk_ops;
+extern struct clk_ops tegra_nand_clk_ops;
+extern struct clk_ops tegra_vi_clk_ops;
+extern struct clk_ops tegra_dtv_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
new file mode 100644
index 000000000000..c10449603df0
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -0,0 +1,1372 @@
+/*
+ * arch/arm/mach-tegra/tegra30_clocks.c
+ *
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+#include <linux/clk-private.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra30_clocks.h"
+#include "tegra_cpu_car.h"
+
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,            \
+                   _parent_names, _parents, _parent)            \
+        static struct clk tegra_##_name = {                     \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .name = #_name,                                 \
+                .rate = _rate,                                  \
+                .ops = _ops,                                    \
+                .flags = _flags,                                \
+                .parent_names = _parent_names,                  \
+                .parents = _parents,                            \
+                .num_parents = ARRAY_SIZE(_parent_names),       \
+                .parent = _parent,                              \
+        };
+
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+        .hw = {
+                .clk = &tegra_clk_32k,
+        },
+        .fixed_rate = 32768,
+};
+static struct clk tegra_clk_32k = {
+        .name = "clk_32k",
+        .hw = &tegra_clk_32k_hw.hw,
+        .ops = &tegra30_clk_32k_ops,
+        .flags = CLK_IS_ROOT,
+};
+
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+        .hw = {
+                .clk = &tegra_clk_m,
+        },
+        .flags = ENABLE_ON_INIT,
+        .reg = 0x1fc,
+        .reg_shift = 28,
+        .max_rate = 48000000,
+};
+static struct clk tegra_clk_m = {
+        .name = "clk_m",
+        .hw = &tegra_clk_m_hw.hw,
+        .ops = &tegra30_clk_m_ops,
+        .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+};
+
+static const char *clk_m_div_parent_names[] = {
+        "clk_m",
+};
+
+static struct clk *clk_m_div_parents[] = {
+        &tegra_clk_m,
+};
+
+static struct clk tegra_clk_m_div2;
+static struct clk_tegra tegra_clk_m_div2_hw = {
+        .hw = {
+                .clk = &tegra_clk_m_div2,
+        },
+        .mul = 1,
+        .div = 2,
+        .max_rate = 24000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
+                clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_clk_m_div4;
+static struct clk_tegra tegra_clk_m_div4_hw = {
+        .hw = {
+                .clk = &tegra_clk_m_div4,
+        },
+        .mul = 1,
+        .div = 4,
+        .max_rate = 12000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
+                clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_pll_ref;
+static struct clk_tegra tegra_pll_ref_hw = {
+        .hw = {
+                .clk = &tegra_pll_ref,
+        },
+        .flags = ENABLE_ON_INIT,
+        .max_rate = 26000000,
+};
+DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
+                clk_m_div_parents, &tegra_clk_m);
+
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,  \
+                   _input_max, _cf_min, _cf_max, _vco_min,      \
+                   _vco_max, _freq_table, _lock_delay, _ops,    \
+                   _fixed_rate, _clk_cfg_ex, _parent)           \
+        static struct clk tegra_##_name;                        \
+        static const char *_name##_parent_names[] = {           \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .u.pll = {                                      \
+                        .input_min = _input_min,                \
+                        .input_max = _input_max,                \
+                        .cf_min = _cf_min,                      \
+                        .cf_max = _cf_max,                      \
+                        .vco_min = _vco_min,                    \
+                        .vco_max = _vco_max,                    \
+                        .freq_table = _freq_table,              \
+                        .lock_delay = _lock_delay,              \
+                        .fixed_rate = _fixed_rate,              \
+                },                                              \
+                .clk_cfg_ex = _clk_cfg_ex,                      \
+        };                                                      \
+        DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED,    \
+                         _name##_parent_names, _name##_parents, \
+                        &tegra_##_parent);
+
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,         \
+                _max_rate, _ops, _parent, _clk_flags)           \
+        static const char *_name##_parent_names[] = {           \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .reg_shift = _reg_shift,                        \
+        };                                                      \
+        DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops,        \
+                _clk_flags,  _name##_parent_names,              \
+                _name##_parents, &tegra_##_parent);
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+        { 12000000, 1040000000, 520,  6, 1, 8},
+        { 13000000, 1040000000, 480,  6, 1, 8},
+        { 16800000, 1040000000, 495,  8, 1, 8}, /* actual: 1039.5 MHz */
+        { 19200000, 1040000000, 325,  6, 1, 6},
+        { 26000000, 1040000000, 520, 13, 1, 8},
+
+        { 12000000, 832000000, 416,  6, 1, 8},
+        { 13000000, 832000000, 832, 13, 1, 8},
+        { 16800000, 832000000, 396,  8, 1, 8},  /* actual: 831.6 MHz */
+        { 19200000, 832000000, 260,  6, 1, 8},
+        { 26000000, 832000000, 416, 13, 1, 8},
+
+        { 12000000, 624000000, 624, 12, 1, 8},
+        { 13000000, 624000000, 624, 13, 1, 8},
+        { 16800000, 600000000, 520, 14, 1, 8},
+        { 19200000, 624000000, 520, 16, 1, 8},
+        { 26000000, 624000000, 624, 26, 1, 8},
+
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+
+        { 12000000, 520000000, 520, 12, 1, 8},
+        { 13000000, 520000000, 520, 13, 1, 8},
+        { 16800000, 520000000, 495, 16, 1, 8},  /* actual: 519.75 MHz */
+        { 19200000, 520000000, 325, 12, 1, 6},
+        { 26000000, 520000000, 520, 26, 1, 8},
+
+        { 12000000, 416000000, 416, 12, 1, 8},
+        { 13000000, 416000000, 416, 13, 1, 8},
+        { 16800000, 416000000, 396, 16, 1, 8},  /* actual: 415.8 MHz */
+        { 19200000, 416000000, 260, 12, 1, 6},
+        { 26000000, 416000000, 416, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+                tegra30_pll_ops, 0, NULL, pll_ref);
+
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
+                tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+        { 12000000, 666000000, 666, 12, 1, 8},
+        { 13000000, 666000000, 666, 13, 1, 8},
+        { 16800000, 666000000, 555, 14, 1, 8},
+        { 19200000, 666000000, 555, 16, 1, 8},
+        { 26000000, 666000000, 666, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
+                1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
+                300, tegra30_pll_ops, 0, NULL, pll_ref);
+
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+                tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+        { 12000000, 216000000, 432, 12, 2, 8},
+        { 13000000, 216000000, 432, 13, 2, 8},
+        { 16800000, 216000000, 360, 14, 2, 8},
+        { 19200000, 216000000, 360, 16, 2, 8},
+        { 26000000, 216000000, 432, 26, 2, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+                2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+                tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
+                pll_ref);
+
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+                0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+                16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+                0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+                16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+        { 9600000, 564480000, 294, 5, 1, 4},
+        { 9600000, 552960000, 288, 5, 1, 4},
+        { 9600000, 24000000,  5,   2, 1, 1},
+
+        { 28800000, 56448000, 49, 25, 1, 1},
+        { 28800000, 73728000, 64, 25, 1, 1},
+        { 28800000, 24000000,  5,  6, 1, 1},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
+                300, tegra30_pll_ops, 0, NULL, pll_p_out1);
+
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
+                pll_a, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+        { 12000000, 216000000, 216, 12, 1, 4},
+        { 13000000, 216000000, 216, 13, 1, 4},
+        { 16800000, 216000000, 180, 14, 1, 4},
+        { 19200000, 216000000, 180, 16, 1, 4},
+        { 26000000, 216000000, 216, 26, 1, 4},
+
+        { 12000000, 594000000, 594, 12, 1, 8},
+        { 13000000, 594000000, 594, 13, 1, 8},
+        { 16800000, 594000000, 495, 14, 1, 8},
+        { 19200000, 594000000, 495, 16, 1, 8},
+        { 26000000, 594000000, 594, 26, 1, 8},
+
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+                1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+                1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
+
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+                pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+
+DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
+                2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
+                tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
+                pll_ref);
+
+DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+                pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+        { 12000000, 480000000, 960, 12, 2, 12},
+        { 13000000, 480000000, 960, 13, 2, 12},
+        { 16800000, 480000000, 400, 7,  2, 5},
+        { 19200000, 480000000, 200, 4,  2, 3},
+        { 26000000, 480000000, 960, 26, 2, 12},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
+                1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
+                1000, tegra30_pll_ops, 0, NULL, pll_ref);
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+        /* 1.7 GHz */
+        { 12000000, 1700000000, 850,  6,  1, 8},
+        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
+        { 26000000, 1700000000, 850,  13, 1, 8},
+
+        /* 1.6 GHz */
+        { 12000000, 1600000000, 800,  6,  1, 8},
+        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
+        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
+        { 19200000, 1600000000, 500,  6,  1, 8},
+        { 26000000, 1600000000, 800,  13, 1, 8},
+
+        /* 1.5 GHz */
+        { 12000000, 1500000000, 750,  6,  1, 8},
+        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
+        { 16800000, 1500000000, 625,  7,  1, 8},
+        { 19200000, 1500000000, 625,  8,  1, 8},
+        { 26000000, 1500000000, 750,  13, 1, 8},
+
+        /* 1.4 GHz */
+        { 12000000, 1400000000, 700,  6,  1, 8},
+        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
+        { 16800000, 1400000000, 1000, 12, 1, 8},
+        { 19200000, 1400000000, 875,  12, 1, 8},
+        { 26000000, 1400000000, 700,  13, 1, 8},
+
+        /* 1.3 GHz */
+        { 12000000, 1300000000, 975,  9,  1, 8},
+        { 13000000, 1300000000, 1000, 10, 1, 8},
+        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 26000000, 1300000000, 650,  13, 1, 8},
+
+        /* 1.2 GHz */
+        { 12000000, 1200000000, 1000, 10, 1, 8},
+        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
+        { 16800000, 1200000000, 1000, 14, 1, 8},
+        { 19200000, 1200000000, 1000, 16, 1, 8},
+        { 26000000, 1200000000, 600,  13, 1, 8},
+
+        /* 1.1 GHz */
+        { 12000000, 1100000000, 825,  9,  1, 8},
+        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
+        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
+        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
+        { 26000000, 1100000000, 550,  13, 1, 8},
+
+        /* 1 GHz */
+        { 12000000, 1000000000, 1000, 12, 1, 8},
+        { 13000000, 1000000000, 1000, 13, 1, 8},
+        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 8},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
+                2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
+                tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
+
+DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
+                pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+        /* PLLE special case: use cpcon field to store cml divider value */
+        { 12000000,  100000000, 150, 1,  18, 11},
+        { 216000000, 100000000, 200, 18, 24, 13},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
+                12000000, 12000000, 1200000000, 2400000000U,
+                tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
+                pll_ref);
+
+static const char *mux_plle[] = {
+        "pll_e",
+};
+
+static struct clk *mux_plle_p[] = {
+        &tegra_pll_e,
+};
+
+static struct clk tegra_cml0;
+static struct clk_tegra tegra_cml0_hw = {
+        .hw = {
+                .clk = &tegra_cml0,
+        },
+        .reg = 0x48c,
+        .fixed_rate = 100000000,
+        .u.periph = {
+                .clk_num = 0,
+        },
+};
+DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
+                mux_plle_p, &tegra_pll_e);
+
+static struct clk tegra_cml1;
+static struct clk_tegra tegra_cml1_hw = {
+        .hw = {
+                .clk = &tegra_cml1,
+        },
+        .reg = 0x48c,
+        .fixed_rate = 100000000,
+        .u.periph = {
+                .clk_num = 1,
+        },
+};
+DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
+                mux_plle_p, &tegra_pll_e);
+
+static struct clk tegra_pciex;
+static struct clk_tegra tegra_pciex_hw = {
+        .hw = {
+                .clk = &tegra_pciex,
+        },
+        .reg = 0x48c,
+        .fixed_rate = 100000000,
+        .reset = tegra30_periph_clk_reset,
+        .u.periph = {
+                .clk_num = 74,
+        },
+};
+DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
+                mux_plle_p, &tegra_pll_e);
+
+#define SYNC_SOURCE(_name)                                      \
+        static struct clk tegra_##_name##_sync;                 \
+        static struct clk_tegra tegra_##_name##_sync_hw = {     \
+                .hw = {                                         \
+                        .clk = &tegra_##_name##_sync,           \
+                },                                              \
+                .max_rate = 24000000,                           \
+                .fixed_rate = 24000000,                         \
+        };                                                      \
+        static struct clk tegra_##_name##_sync = {              \
+                .name = #_name "_sync",                         \
+                .hw = &tegra_##_name##_sync_hw.hw,              \
+                .ops = &tegra_sync_source_ops,                  \
+                .flags = CLK_IS_ROOT,                           \
+        };
+
+SYNC_SOURCE(spdif_in);
+SYNC_SOURCE(i2s0);
+SYNC_SOURCE(i2s1);
+SYNC_SOURCE(i2s2);
+SYNC_SOURCE(i2s3);
+SYNC_SOURCE(i2s4);
+SYNC_SOURCE(vimclk);
+
+static struct clk *tegra_sync_source_list[] = {
+        &tegra_spdif_in_sync,
+        &tegra_i2s0_sync,
+        &tegra_i2s1_sync,
+        &tegra_i2s2_sync,
+        &tegra_i2s3_sync,
+        &tegra_i2s4_sync,
+        &tegra_vimclk_sync,
+};
+
+static const char *mux_audio_sync_clk[] = {
+        "spdif_in_sync",
+        "i2s0_sync",
+        "i2s1_sync",
+        "i2s2_sync",
+        "i2s3_sync",
+        "i2s4_sync",
+        "vimclk_sync",
+};
+
+#define AUDIO_SYNC_CLK(_name, _index)                           \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .max_rate = 24000000,                           \
+                .reg = 0x4A0 + (_index) * 4,                    \
+        };                                                      \
+        static struct clk tegra_##_name = {                     \
+                .name = #_name,                                 \
+                .ops = &tegra30_audio_sync_clk_ops,             \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .parent_names = mux_audio_sync_clk,             \
+                .parents = tegra_sync_source_list,              \
+                .num_parents = ARRAY_SIZE(mux_audio_sync_clk),  \
+        };
+
+AUDIO_SYNC_CLK(audio0, 0);
+AUDIO_SYNC_CLK(audio1, 1);
+AUDIO_SYNC_CLK(audio2, 2);
+AUDIO_SYNC_CLK(audio3, 3);
+AUDIO_SYNC_CLK(audio4, 4);
+AUDIO_SYNC_CLK(audio5, 5);
+
+static struct clk *tegra_clk_audio_list[] = {
+        &tegra_audio0,
+        &tegra_audio1,
+        &tegra_audio2,
+        &tegra_audio3,
+        &tegra_audio4,
+        &tegra_audio5,  /* SPDIF */
+};
+
+#define AUDIO_SYNC_2X_CLK(_name, _index)                        \
+        static const char *_name##_parent_names[] = {           \
+                "tegra_" #_name,                                \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                &tegra_##_name,                                 \
+        };                                                      \
+        static struct clk tegra_##_name##_2x;                   \
+        static struct clk_tegra tegra_##_name##_2x_hw = {       \
+                .hw = {                                         \
+                        .clk = &tegra_##_name##_2x,             \
+                },                                              \
+                .flags = PERIPH_NO_RESET,                       \
+                .max_rate = 48000000,                           \
+                .reg = 0x49C,                                   \
+                .reg_shift = 24 + (_index),                     \
+                .u.periph = {                                   \
+                        .clk_num = 113 + (_index),              \
+                },                                              \
+        };                                                      \
+        static struct clk tegra_##_name##_2x = {                \
+                .name = #_name "_2x",                           \
+                .ops = &tegra30_clk_double_ops,                 \
+                .hw = &tegra_##_name##_2x_hw.hw,                \
+                .parent_names = _name##_parent_names,           \
+                .parents = _name##_parents,                     \
+                .parent = &tegra_##_name,                       \
+                .num_parents = 1,                               \
+        };
+
+AUDIO_SYNC_2X_CLK(audio0, 0);
+AUDIO_SYNC_2X_CLK(audio1, 1);
+AUDIO_SYNC_2X_CLK(audio2, 2);
+AUDIO_SYNC_2X_CLK(audio3, 3);
+AUDIO_SYNC_2X_CLK(audio4, 4);
+AUDIO_SYNC_2X_CLK(audio5, 5);   /* SPDIF */
+
+static struct clk *tegra_clk_audio_2x_list[] = {
+        &tegra_audio0_2x,
+        &tegra_audio1_2x,
+        &tegra_audio2_2x,
+        &tegra_audio3_2x,
+        &tegra_audio4_2x,
+        &tegra_audio5_2x,       /* SPDIF */
+};
+
+#define MUX_I2S_SPDIF(_id)                                      \
+static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = {      \
+        "pll_a_out0",                                           \
+        #_id "_2x",                                             \
+        "pll_p",                                                \
+        "clk_m",                                                \
+};                                                              \
+static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = {    \
+        &tegra_pll_a_out0,                                      \
+        &tegra_##_id##_2x,                                      \
+        &tegra_pll_p,                                           \
+        &tegra_clk_m,                                           \
+};
+
+MUX_I2S_SPDIF(audio0);
+MUX_I2S_SPDIF(audio1);
+MUX_I2S_SPDIF(audio2);
+MUX_I2S_SPDIF(audio3);
+MUX_I2S_SPDIF(audio4);
+MUX_I2S_SPDIF(audio5);          /* SPDIF */
+
+static struct clk tegra_extern1;
+static struct clk tegra_extern2;
+static struct clk tegra_extern3;
+
+/* External clock outputs (through PMC) */
+#define MUX_EXTERN_OUT(_id)                                     \
+static const char *mux_clkm_clkm2_clkm4_extern##_id[] = {       \
+        "clk_m",                                                \
+        "clk_m_div2",                                           \
+        "clk_m_div4",                                           \
+        "extern" #_id,                                          \
+};                                                              \
+static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = {   \
+        &tegra_clk_m,                                           \
+        &tegra_clk_m_div2,                                      \
+        &tegra_clk_m_div4,                                      \
+        &tegra_extern##_id,                                     \
+};
+
+MUX_EXTERN_OUT(1);
+MUX_EXTERN_OUT(2);
+MUX_EXTERN_OUT(3);
+
+#define CLK_OUT_CLK(_name, _index)                                      \
+        static struct clk tegra_##_name;                                \
+        static struct clk_tegra tegra_##_name##_hw = {                  \
+                .hw = {                                                 \
+                        .clk = &tegra_##_name,                          \
+                },                                                      \
+                .lookup = {                                             \
+                        .dev_id = #_name,                               \
+                        .con_id = "extern" #_index,                     \
+                },                                                      \
+                .flags = MUX_CLK_OUT,                                   \
+                .fixed_rate = 216000000,                                        \
+                .reg = 0x1a8,                                           \
+                .u.periph = {                                           \
+                        .clk_num = (_index - 1) * 8 + 2,                \
+                },                                                      \
+        };                                                              \
+        static struct clk tegra_##_name = {                             \
+                .name = #_name,                                         \
+                .ops = &tegra_clk_out_ops,                              \
+                .hw = &tegra_##_name##_hw.hw,                           \
+                .parent_names = mux_clkm_clkm2_clkm4_extern##_index,    \
+                .parents = mux_clkm_clkm2_clkm4_extern##_index##_p,     \
+                .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
+        };
+
+CLK_OUT_CLK(clk_out_1, 1);
+CLK_OUT_CLK(clk_out_2, 2);
+CLK_OUT_CLK(clk_out_3, 3);
+
+static struct clk *tegra_clk_out_list[] = {
+        &tegra_clk_out_1,
+        &tegra_clk_out_2,
+        &tegra_clk_out_3,
+};
+
+static const char *mux_sclk[] = {
+        "clk_m",
+        "pll_c_out1",
+        "pll_p_out4",
+        "pll_p_out3",
+        "pll_p_out2",
+        "dummy",
+        "clk_32k",
+        "pll_m_out1",
+};
+
+static struct clk *mux_sclk_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c_out1,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out2,
+        NULL,
+        &tegra_clk_32k,
+        &tegra_pll_m_out1,
+};
+
+static struct clk tegra_clk_sclk;
+static struct clk_tegra tegra_clk_sclk_hw = {
+        .hw = {
+                .clk = &tegra_clk_sclk,
+        },
+        .reg = 0x28,
+        .max_rate = 334000000,
+        .min_rate = 40000000,
+};
+
+static struct clk tegra_clk_sclk = {
+        .name = "sclk",
+        .ops = &tegra30_super_ops,
+        .hw = &tegra_clk_sclk_hw.hw,
+        .parent_names = mux_sclk,
+        .parents = mux_sclk_p,
+        .num_parents = ARRAY_SIZE(mux_sclk),
+};
+
+static const char *mux_blink[] = {
+        "clk_32k",
+};
+
+static struct clk *mux_blink_p[] = {
+        &tegra_clk_32k,
+};
+
+static struct clk tegra_clk_blink;
+static struct clk_tegra tegra_clk_blink_hw = {
+        .hw = {
+                .clk = &tegra_clk_blink,
+        },
+        .reg = 0x40,
+        .max_rate = 32768,
+};
+static struct clk tegra_clk_blink = {
+        .name = "blink",
+        .ops = &tegra30_blink_clk_ops,
+        .hw = &tegra_clk_blink_hw.hw,
+        .parent = &tegra_clk_32k,
+        .parent_names = mux_blink,
+        .parents = mux_blink_p,
+        .num_parents = ARRAY_SIZE(mux_blink),
+};
+
+static const char *mux_pllm_pllc_pllp_plla[] = {
+        "pll_m",
+        "pll_c",
+        "pll_p",
+        "pll_a_out0",
+};
+
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m",
+        "clk_m",
+};
+
+static const char *mux_pllp_clkm[] = {
+        "pll_p",
+        "dummy",
+        "dummy",
+        "clk_m",
+};
+
+static const char *mux_pllp_plld_pllc_clkm[] = {
+        "pll_p",
+        "pll_d_out0",
+        "pll_c",
+        "clk_m",
+};
+
+static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+        "pll_p",
+        "pll_m",
+        "pll_d_out0",
+        "pll_a_out0",
+        "pll_c",
+        "pll_d2_out0",
+        "clk_m",
+};
+
+static const char *mux_plla_pllc_pllp_clkm[] = {
+        "pll_a_out0",
+        "dummy",
+        "pll_p",
+        "clk_m"
+};
+
+static const char *mux_pllp_pllc_clk32_clkm[] = {
+        "pll_p",
+        "pll_c",
+        "clk_32k",
+        "clk_m",
+};
+
+static const char *mux_pllp_pllc_clkm_clk32[] = {
+        "pll_p",
+        "pll_c",
+        "clk_m",
+        "clk_32k",
+};
+
+static const char *mux_pllp_pllc_pllm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m",
+};
+
+static const char *mux_clk_m[] = {
+        "clk_m",
+};
+
+static const char *mux_pllp_out3[] = {
+        "pll_p_out3",
+};
+
+static const char *mux_plld_out0[] = {
+        "pll_d_out0",
+};
+
+static const char *mux_plld_out0_plld2_out0[] = {
+        "pll_d_out0",
+        "pll_d2_out0",
+};
+
+static const char *mux_clk_32k[] = {
+        "clk_32k",
+};
+
+static const char *mux_plla_clk32_pllp_clkm_plle[] = {
+        "pll_a_out0",
+        "clk_32k",
+        "pll_p",
+        "clk_m",
+        "pll_e",
+};
+
+static const char *mux_cclk_g[] = {
+        "clk_m",
+        "pll_c",
+        "clk_32k",
+        "pll_m",
+        "pll_p",
+        "pll_p_out4",
+        "pll_p_out3",
+        "dummy",
+        "pll_x",
+};
+
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+        &tegra_pll_m,
+        &tegra_pll_c,
+        &tegra_pll_p,
+        &tegra_pll_a_out0,
+};
+
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_clkm_p[] = {
+        &tegra_pll_p,
+        NULL,
+        NULL,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_d_out0,
+        &tegra_pll_c,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_m,
+        &tegra_pll_d_out0,
+        &tegra_pll_a_out0,
+        &tegra_pll_c,
+        &tegra_pll_d2_out0,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
+        &tegra_pll_a_out0,
+        NULL,
+        &tegra_pll_p,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_clk_32k,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_clk_m,
+        &tegra_clk_32k,
+};
+
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+};
+
+static struct clk *mux_clk_m_p[] = {
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_out3_p[] = {
+        &tegra_pll_p_out3,
+};
+
+static struct clk *mux_plld_out0_p[] = {
+        &tegra_pll_d_out0,
+};
+
+static struct clk *mux_plld_out0_plld2_out0_p[] = {
+        &tegra_pll_d_out0,
+        &tegra_pll_d2_out0,
+};
+
+static struct clk *mux_clk_32k_p[] = {
+        &tegra_clk_32k,
+};
+
+static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
+        &tegra_pll_a_out0,
+        &tegra_clk_32k,
+        &tegra_pll_p,
+        &tegra_clk_m,
+        &tegra_pll_e,
+};
+
+static struct clk *mux_cclk_g_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c,
+        &tegra_clk_32k,
+        &tegra_pll_m,
+        &tegra_pll_p,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        NULL,
+        &tegra_pll_x,
+};
+
+static struct clk tegra_clk_cclk_g;
+static struct clk_tegra tegra_clk_cclk_g_hw = {
+        .hw = {
+                .clk = &tegra_clk_cclk_g,
+        },
+        .flags = DIV_U71 | DIV_U71_INT,
+        .reg = 0x368,
+        .max_rate = 1700000000,
+};
+static struct clk tegra_clk_cclk_g = {
+        .name = "cclk_g",
+        .ops = &tegra30_super_ops,
+        .hw = &tegra_clk_cclk_g_hw.hw,
+        .parent_names = mux_cclk_g,
+        .parents = mux_cclk_g_p,
+        .num_parents = ARRAY_SIZE(mux_cclk_g),
+};
+
+static const char *mux_twd[] = {
+        "cclk_g",
+};
+
+static struct clk *mux_twd_p[] = {
+        &tegra_clk_cclk_g,
+};
+
+static struct clk tegra30_clk_twd;
+static struct clk_tegra tegra30_clk_twd_hw = {
+        .hw = {
+                .clk = &tegra30_clk_twd,
+        },
+        .max_rate = 1400000000,
+        .mul = 1,
+        .div = 2,
+};
+
+static struct clk tegra30_clk_twd = {
+        .name = "twd",
+        .ops = &tegra30_twd_ops,
+        .hw = &tegra30_clk_twd_hw.hw,
+        .parent = &tegra_clk_cclk_g,
+        .parent_names = mux_twd,
+        .parents = mux_twd_p,
+        .num_parents = ARRAY_SIZE(mux_twd),
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,   \
+                _max, _inputs, _flags)                  \
+        static struct clk tegra_##_name;                \
+        static struct clk_tegra tegra_##_name##_hw = {  \
+                .hw = {                                 \
+                        .clk = &tegra_##_name,          \
+                },                                      \
+                .lookup = {                             \
+                        .dev_id = _dev,                 \
+                        .con_id = _con,                 \
+                },                                      \
+                .reg = _reg,                            \
+                .flags = _flags,                        \
+                .max_rate = _max,                       \
+                .u.periph = {                           \
+                        .clk_num = _clk_num,            \
+                },                                      \
+                .reset = &tegra30_periph_clk_reset,     \
+        };                                              \
+        static struct clk tegra_##_name = {             \
+                .name = #_name,                         \
+                .ops = &tegra30_periph_clk_ops,         \
+                .hw = &tegra_##_name##_hw.hw,           \
+                .parent_names = _inputs,                \
+                .parents = _inputs##_p,                 \
+                .num_parents = ARRAY_SIZE(_inputs),     \
+        };
+
+PERIPH_CLK(apbdma,      "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(rtc,         "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(kbc,         "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(timer,       "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(kfuse,       "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(fuse,        "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB);
+PERIPH_CLK(fuse_burn,   "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB);
+PERIPH_CLK(apbif,       "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(i2s0,        "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s1,        "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s2,        "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s3,        "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s4,        "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_out,   "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio5_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_in,    "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pwm,         "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(d_audio,     "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(dam0,        "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(dam1,        "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(dam2,        "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(hda,         "tegra30-hda",          "hda",  125,    0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(hda2codec_2x,        "tegra30-hda",  "hda2codec",    111,    0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(hda2hdmi,    "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0);
+PERIPH_CLK(sbc1,        "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc2,        "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc3,        "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc4,        "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc5,        "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc6,        "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sata_oob,    "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sata,        "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sata_cold,   "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0);
+PERIPH_CLK(ndflash,     "tegra_nand",           NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(ndspeed,     "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(vfir,        "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sdmmc1,      "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2,      "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3,      "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4,      "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp,         "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsea,        "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsev,        "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(vde,         "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(csite,       "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* max rate ??? */
+PERIPH_CLK(la,          "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
+PERIPH_CLK(i2c1,        "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c2,        "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c3,        "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c4,        "tegra-i2c.3",          NULL,   103,    0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c5,        "tegra-i2c.4",          NULL,   47,     0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartd,       "tegra-uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uarte,       "tegra-uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(vi,          "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(3d,          "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(3d2,         "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(2d,          "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
+PERIPH_CLK(vi_sensor,   "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET);
+PERIPH_CLK(epp,         "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(mpe,         "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(host1x,      "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(cve,         "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo,         "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(dtv,         "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0);
+PERIPH_CLK(hdmi,        "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71);
+PERIPH_CLK(tvdac,       "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1,       "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
+PERIPH_CLK(disp2,       "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
+PERIPH_CLK(usbd,        "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb2,        "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb3,        "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(dsia,        "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0);
+PERIPH_CLK(csi,         "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0);
+PERIPH_CLK(isp,         "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0); /* same frequency as VI */
+PERIPH_CLK(csus,        "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET);
+PERIPH_CLK(tsensor,     "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71);
+PERIPH_CLK(actmon,      "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71);
+PERIPH_CLK(extern1,     "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern2,     "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern3,     "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
+PERIPH_CLK(i2cslow,     "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pcie,        "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(afi,         "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(se,          "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
+
+static struct clk tegra_dsib;
+static struct clk_tegra tegra_dsib_hw = {
+        .hw = {
+                .clk = &tegra_dsib,
+        },
+        .lookup = {
+                .dev_id = "tegradc.1",
+                .con_id = "dsib",
+        },
+        .reg = 0xd0,
+        .flags = MUX | PLLD,
+        .max_rate = 500000000,
+        .u.periph = {
+                .clk_num = 82,
+        },
+        .reset = &tegra30_periph_clk_reset,
+};
+static struct clk tegra_dsib = {
+        .name = "dsib",
+        .ops = &tegra30_dsib_clk_ops,
+        .hw = &tegra_dsib_hw.hw,
+        .parent_names = mux_plld_out0_plld2_out0,
+        .parents = mux_plld_out0_plld2_out0_p,
+        .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
+};
+
+struct clk *tegra_list_clks[] = {
+        &tegra_apbdma,
+        &tegra_rtc,
+        &tegra_kbc,
+        &tegra_kfuse,
+        &tegra_fuse,
+        &tegra_fuse_burn,
+        &tegra_apbif,
+        &tegra_i2s0,
+        &tegra_i2s1,
+        &tegra_i2s2,
+        &tegra_i2s3,
+        &tegra_i2s4,
+        &tegra_spdif_out,
+        &tegra_spdif_in,
+        &tegra_pwm,
+        &tegra_d_audio,
+        &tegra_dam0,
+        &tegra_dam1,
+        &tegra_dam2,
+        &tegra_hda,
+        &tegra_hda2codec_2x,
+        &tegra_hda2hdmi,
+        &tegra_sbc1,
+        &tegra_sbc2,
+        &tegra_sbc3,
+        &tegra_sbc4,
+        &tegra_sbc5,
+        &tegra_sbc6,
+        &tegra_sata_oob,
+        &tegra_sata,
+        &tegra_sata_cold,
+        &tegra_ndflash,
+        &tegra_ndspeed,
+        &tegra_vfir,
+        &tegra_sdmmc1,
+        &tegra_sdmmc2,
+        &tegra_sdmmc3,
+        &tegra_sdmmc4,
+        &tegra_vcp,
+        &tegra_bsea,
+        &tegra_bsev,
+        &tegra_vde,
+        &tegra_csite,
+        &tegra_la,
+        &tegra_owr,
+        &tegra_nor,
+        &tegra_mipi,
+        &tegra_i2c1,
+        &tegra_i2c2,
+        &tegra_i2c3,
+        &tegra_i2c4,
+        &tegra_i2c5,
+        &tegra_uarta,
+        &tegra_uartb,
+        &tegra_uartc,
+        &tegra_uartd,
+        &tegra_uarte,
+        &tegra_vi,
+        &tegra_3d,
+        &tegra_3d2,
+        &tegra_2d,
+        &tegra_vi_sensor,
+        &tegra_epp,
+        &tegra_mpe,
+        &tegra_host1x,
+        &tegra_cve,
+        &tegra_tvo,
+        &tegra_dtv,
+        &tegra_hdmi,
+        &tegra_tvdac,
+        &tegra_disp1,
+        &tegra_disp2,
+        &tegra_usbd,
+        &tegra_usb2,
+        &tegra_usb3,
+        &tegra_dsia,
+        &tegra_dsib,
+        &tegra_csi,
+        &tegra_isp,
+        &tegra_csus,
+        &tegra_tsensor,
+        &tegra_actmon,
+        &tegra_extern1,
+        &tegra_extern2,
+        &tegra_extern3,
+        &tegra_i2cslow,
+        &tegra_pcie,
+        &tegra_afi,
+        &tegra_se,
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)        \
+        {                                       \
+                .name   = _name,                \
+                .lookup = {                     \
+                        .dev_id = _dev,         \
+                        .con_id = _con,         \
+                },                              \
+        }
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+struct clk_duplicate tegra_clk_duplicates[] = {
+        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
+        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
+        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
+        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
+        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
+        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
+        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
+        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
+        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
+        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
+        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
+        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
+        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
+        CLK_DUPLICATE("bsev", "nvavp", "bsev"),
+        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
+        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
+        CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
+        CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
+        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
+        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
+        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
+        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
+        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+        CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
+        CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
+        CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
+        CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
+        CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
+        CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
+        CLK_DUPLICATE("twd", "smp_twd", NULL),
+        CLK_DUPLICATE("vcp", "nvavp", "vcp"),
+        CLK_DUPLICATE("i2s0", NULL, "i2s0"),
+        CLK_DUPLICATE("i2s1", NULL, "i2s1"),
+        CLK_DUPLICATE("i2s2", NULL, "i2s2"),
+        CLK_DUPLICATE("i2s3", NULL, "i2s3"),
+        CLK_DUPLICATE("i2s4", NULL, "i2s4"),
+        CLK_DUPLICATE("dam0", NULL, "dam0"),
+        CLK_DUPLICATE("dam1", NULL, "dam1"),
+        CLK_DUPLICATE("dam2", NULL, "dam2"),
+        CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
+};
+
+struct clk *tegra_ptr_clks[] = {
+        &tegra_clk_32k,
+        &tegra_clk_m,
+        &tegra_clk_m_div2,
+        &tegra_clk_m_div4,
+        &tegra_pll_ref,
+        &tegra_pll_m,
+        &tegra_pll_m_out1,
+        &tegra_pll_c,
+        &tegra_pll_c_out1,
+        &tegra_pll_p,
+        &tegra_pll_p_out1,
+        &tegra_pll_p_out2,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out4,
+        &tegra_pll_a,
+        &tegra_pll_a_out0,
+        &tegra_pll_d,
+        &tegra_pll_d_out0,
+        &tegra_pll_d2,
+        &tegra_pll_d2_out0,
+        &tegra_pll_u,
+        &tegra_pll_x,
+        &tegra_pll_x_out0,
+        &tegra_pll_e,
+        &tegra_clk_cclk_g,
+        &tegra_cml0,
+        &tegra_cml1,
+        &tegra_pciex,
+        &tegra_clk_sclk,
+        &tegra_clk_blink,
+        &tegra30_clk_twd,
+};
+
+static void tegra30_init_one_clock(struct clk *c)
+{
+        struct clk_tegra *clk = to_clk_tegra(c->hw);
+        __clk_init(NULL, c);
+        INIT_LIST_HEAD(&clk->shared_bus_list);
+        if (!clk->lookup.dev_id && !clk->lookup.con_id)
+                clk->lookup.con_id = c->name;
+        clk->lookup.clk = c;
+        clkdev_add(&clk->lookup);
+        tegra_clk_add(c);
+}
+
+void __init tegra30_init_clocks(void)
+{
+        int i;
+        struct clk *c;
+
+        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+                tegra30_init_one_clock(tegra_ptr_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+                tegra30_init_one_clock(tegra_list_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+                if (!c) {
+                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                                tegra_clk_duplicates[i].name);
+                        continue;
+                }
+
+                tegra_clk_duplicates[i].lookup.clk = c;
+                clkdev_add(&tegra_clk_duplicates[i].lookup);
+        }
+
+        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
+                tegra30_init_one_clock(tegra_sync_source_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
+                tegra30_init_one_clock(tegra_clk_audio_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
+                tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
+                tegra30_init_one_clock(tegra_clk_out_list[i]);
+
+        tegra30_cpu_car_ops_init();
+}
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
new file mode 100644
index 000000000000..30d063ad2bef
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_CPU_CAR_H
+#define __MACH_TEGRA_CPU_CAR_H
+
+/*
+ * Tegra CPU clock and reset control ops
+ *
+ * wait_for_reset:
+ *      keep waiting until the CPU in reset state
+ * put_in_reset:
+ *      put the CPU in reset state
+ * out_of_reset:
+ *      release the CPU from reset state
+ * enable_clock:
+ *      CPU clock un-gate
+ * disable_clock:
+ *      CPU clock gate
+ */
+struct tegra_cpu_car_ops {
+        void (*wait_for_reset)(u32 cpu);
+        void (*put_in_reset)(u32 cpu);
+        void (*out_of_reset)(u32 cpu);
+        void (*enable_clock)(u32 cpu);
+        void (*disable_clock)(u32 cpu);
+};
+
+extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+
+static inline void tegra_wait_cpu_in_reset(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
+                return;
+
+        tegra_cpu_car_ops->wait_for_reset(cpu);
+}
+
+static inline void tegra_put_cpu_in_reset(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
+                return;
+
+        tegra_cpu_car_ops->put_in_reset(cpu);
+}
+
+static inline void tegra_cpu_out_of_reset(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
+                return;
+
+        tegra_cpu_car_ops->out_of_reset(cpu);
+}
+
+static inline void tegra_enable_cpu_clock(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
+                return;
+
+        tegra_cpu_car_ops->enable_clock(cpu);
+}
+
+static inline void tegra_disable_cpu_clock(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
+                return;
+
+        tegra_cpu_car_ops->disable_clock(cpu);
+}
+
+void tegra20_cpu_car_ops_init(void);
+void tegra30_cpu_car_ops_init(void);
+
+#endif /* __MACH_TEGRA_CPU_CAR_H */
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 54d8f34fdee5..f7e12ede008c 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,6 +1,6 @@
 if ARCH_U300
 
-menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
+menu "ST-Ericsson AB U300/U335 Platform"
 
 comment "ST-Ericsson Mobile Platform Products"
 
@@ -10,46 +10,7 @@ config MACH_U300
         select PINCTRL_U300
         select PINCTRL_COH901
 
-comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
-
-choice
-        prompt "U300/U330/U335/U365 system type"
-        default MACH_U300_BS2X
-        ---help---
-        You need to select the target system, i.e. the
-        U300/U330/U335/U365 board that you want to compile your kernel
-        for.
-
-config MACH_U300_BS2X
-        bool "S26/S26/B25/B26 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S26/S25 test products. (Also works on
-                B26/B25 big boards.)
-
-config MACH_U300_BS330
-        bool "S330/B330 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S330/B330 test products.
-
-config MACH_U300_BS335
-        bool "S335/B335 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S335/B335 test products.
-
-config MACH_U300_BS365
-        bool "S365/B365 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S365/B365 test products.
-
-endchoice
+comment "ST-Ericsson U300/U335 Feature Selections"
 
 config U300_DEBUG
         bool "Debug support for U300"
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 7e47d37aeb0e..5a86c58da396 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,6 @@ obj-m		:=
 obj-n           :=
 obj-            :=
 
-obj-$(CONFIG_ARCH_U300)           += u300.o
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
 obj-$(CONFIG_I2C_STU300)          += i2c.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 03acf1883ec7..ef6f602b7e48 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/core.c
  *
  *
- * Copyright (C) 2007-2010 ST-Ericsson SA
+ * Copyright (C) 2007-2012 ST-Ericsson SA
  * License terms: GNU General Public License (GPL) version 2
  * Core platform support, IRQ handling and device definitions.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -31,23 +31,26 @@
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
 
 #include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
-#include <mach/dma_channels.h>
-#include <mach/gpio-u300.h>
+#include <mach/irqs.h>
 
+#include "timer.h"
 #include "spi.h"
 #include "i2c.h"
 #include "u300-gpio.h"
+#include "dma_channels.h"
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -76,7 +79,7 @@ static struct map_desc u300_io_desc[] __initdata = {
         },
 };
 
-void __init u300_map_io(void)
+static void __init u300_map_io(void)
 {
         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
         /* We enable a real big DMA buffer if need be. */
@@ -101,7 +104,6 @@ static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
         { IRQ_U300_UART0 }, &uart0_plat_data);
 
 /* The U335 have an additional UART1 on the APP CPU */
-#ifdef CONFIG_MACH_U300_BS335
 static struct amba_pl011_data uart1_plat_data = {
 #ifdef CONFIG_COH901318
         .dma_filter = coh901318_filter_id,
@@ -113,7 +115,6 @@ static struct amba_pl011_data uart1_plat_data = {
 /* Fast device at 0x7000 offset */
 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
         { IRQ_U300_UART1 }, &uart1_plat_data);
-#endif
 
 /* AHB device at 0x4000 offset */
 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
@@ -152,9 +153,7 @@ static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
  */
 static struct amba_device *amba_devs[] __initdata = {
         &uart0_device,
-#ifdef CONFIG_MACH_U300_BS335
         &uart1_device,
-#endif
         &pl022_device,
         &pl172_device,
         &mmcsd_device,
@@ -188,7 +187,6 @@ static struct resource gpio_resources[] = {
                 .end   = IRQ_U300_GPIO_PORT2,
                 .flags = IORESOURCE_IRQ,
         },
-#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
         {
                 .name  = "gpio3",
                 .start = IRQ_U300_GPIO_PORT3,
@@ -201,8 +199,6 @@ static struct resource gpio_resources[] = {
                 .end   = IRQ_U300_GPIO_PORT4,
                 .flags = IORESOURCE_IRQ,
         },
-#endif
-#ifdef CONFIG_MACH_U300_BS335
         {
                 .name  = "gpio5",
                 .start = IRQ_U300_GPIO_PORT5,
@@ -215,7 +211,6 @@ static struct resource gpio_resources[] = {
                 .end   = IRQ_U300_GPIO_PORT6,
                 .flags = IORESOURCE_IRQ,
         },
-#endif /* CONFIG_MACH_U300_BS335 */
 };
 
 static struct resource keypad_resources[] = {
@@ -323,7 +318,6 @@ static struct resource dma_resource[] = {
         }
 };
 
-#ifdef CONFIG_MACH_U300_BS335
 /* points out all dma slave channels.
  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
  * Select all channels from A to B, end of list is marked with -1,-1
@@ -336,14 +330,6 @@ static int dma_slave_channels[] = {
 static int dma_memcpy_channels[] = {
         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 
-#else /* CONFIG_MACH_U300_BS335 */
-
-static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
-static int dma_memcpy_channels[] = {
-        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
-
-#endif
-
 /** register dma for memory access
  *
  * active  1 means dma intends to access memory
@@ -1395,7 +1381,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                 .param.ctrl_lli = flags_memcpy_lli,
                 .param.ctrl_lli_last = flags_memcpy_lli_last,
         },
-#ifdef CONFIG_MACH_U300_BS335
         {
                 .number = U300_DMA_UART1_TX,
                 .name = "UART1 TX",
@@ -1406,28 +1391,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                 .name = "UART1 RX",
                 .priority_high = 0,
         }
-#else
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_9,
-                .name = "GENERAL 09",
-                .priority_high = 0,
-
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_10,
-                .name = "GENERAL 10",
-                .priority_high = 0,
-
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        }
-#endif
 };
 
 
@@ -1480,18 +1443,7 @@ static struct platform_device pinctrl_device = {
  * GPIO block, with different number of ports.
  */
 static struct u300_gpio_platform u300_gpio_plat = {
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-        .variant = U300_GPIO_COH901335,
-        .ports = 3,
-#endif
-#ifdef CONFIG_MACH_U300_BS335
-        .variant = U300_GPIO_COH901571_3_BS335,
         .ports = 7,
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-        .variant = U300_GPIO_COH901571_3_BS365,
-        .ports = 5,
-#endif
         .gpio_base = 0,
         .gpio_irq_base = IRQ_U300_GPIO_BASE,
         .pinctrl_device = &pinctrl_device,
@@ -1651,7 +1603,7 @@ static struct platform_device *platform_devs[] __initdata = {
  * together so some interrupts are connected to the first one and some
  * to the second one.
  */
-void __init u300_init_irq(void)
+static void __init u300_init_irq(void)
 {
         u32 mask[2] = {0, 0};
         struct clk *clk;
@@ -1756,29 +1708,11 @@ static void __init u300_init_check_chip(void)
         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
                "(chip ID 0x%04x)\n", chipname, val);
 
-#ifdef CONFIG_MACH_U300_BS330
-        if ((val & 0xFF00U) != 0xd800) {
-                printk(KERN_ERR "Platform configured for BS330 " \
-                       "with DB3200 but %s detected, expect problems!",
-                       chipname);
-        }
-#endif
-#ifdef CONFIG_MACH_U300_BS335
         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
                 printk(KERN_ERR "Platform configured for BS335 " \
                        " with DB3350 but %s detected, expect problems!",
                        chipname);
         }
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-        if ((val & 0xFF00U) != 0xe800) {
-                printk(KERN_ERR "Platform configured for BS365 " \
-                       "with DB3210 but %s detected, expect problems!",
-                       chipname);
-        }
-#endif
-
-
 }
 
 /*
@@ -1811,7 +1745,7 @@ static void __init u300_assign_physmem(void)
         }
 }
 
-void __init u300_init_devices(void)
+static void __init u300_init_machine(void)
 {
         int i;
         u16 val;
@@ -1852,7 +1786,7 @@ void __init u300_init_devices(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
-void u300_restart(char mode, const char *cmd)
+static void u300_restart(char mode, const char *cmd)
 {
         switch (mode) {
         case 's':
@@ -1868,3 +1802,15 @@ void u300_restart(char mode, const char *cmd)
         /* Wait for system do die/reset. */
         while (1);
 }
+
+MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
+        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
+        .atag_offset    = 0x100,
+        .map_io         = u300_map_io,
+        .nr_irqs        = NR_IRQS_U300,
+        .init_irq       = u300_init_irq,
+        .handle_irq     = vic_handle_irq,
+        .timer          = &u300_timer,
+        .init_machine   = u300_init_machine,
+        .restart        = u300_restart,
+MACHINE_END
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/dma_channels.h
index b239149ba0d0..4e8a88fbca49 100644
--- a/arch/arm/mach-u300/include/mach/dma_channels.h
+++ b/arch/arm/mach-u300/dma_channels.h
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/dma_channels.h
  *
  *
- * Copyright (C) 2007-2009 ST-Ericsson
+ * Copyright (C) 2007-2012 ST-Ericsson
  * License terms: GNU General Public License (GPL) version 2
  * Map file for the U300 dma driver.
  * Author: Per Friden <per.friden@stericsson.com>
@@ -50,19 +50,10 @@
 #define U300_DMA_GENERAL_PURPOSE_6    35
 #define U300_DMA_GENERAL_PURPOSE_7    36
 #define U300_DMA_GENERAL_PURPOSE_8    37
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_UART1_TX             38
 #define U300_DMA_UART1_RX             39
-#else
-#define U300_DMA_GENERAL_PURPOSE_9    38
-#define U300_DMA_GENERAL_PURPOSE_10   39
-#endif
 
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_DEVICE_CHANNELS      32
-#else
-#define U300_DMA_DEVICE_CHANNELS      30
-#endif
 #define U300_DMA_CHANNELS             40
 
 
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index cb04bd6ab3e7..0d4620ed853c 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-u300/i2c.c
  *
- * Copyright (C) 2009 ST-Ericsson AB
+ * Copyright (C) 2009-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  *
  * Register board i2c devices
@@ -261,7 +261,6 @@ static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
 };
 
 static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-#ifdef CONFIG_MACH_U300_BS335
         {
                 .type = "fwcam",
                 .addr = 0x10,
@@ -270,9 +269,6 @@ static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
                 .type = "fwcam",
                 .addr = 0x5d,
         },
-#else
-        { },
-#endif
 };
 
 void __init u300_i2c_register_board_devices(void)
diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h
deleted file mode 100644
index 92e3cc872c66..000000000000
--- a/arch/arm/mach-u300/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-int __clk_get(struct clk *clk);
-void __clk_put(struct clk *clk);
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-u300/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ec09c1e07b1a..e27425a63fa1 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/irqs.h
  *
  *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * IRQ channel definitions for the U300 platforms.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -31,10 +31,6 @@
 #define IRQ_U300_XGAM_GAMCON            14
 #define IRQ_U300_XGAM_CDI               15
 #define IRQ_U300_XGAM_CDICON            16
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-/* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC            17
-#endif
 #define IRQ_U300_XGAM_PDI               18
 #define IRQ_U300_XGAM_PDICON            19
 #define IRQ_U300_XGAM_GAMEACC           20
@@ -55,8 +51,6 @@
 #define IRQ_U300_GPIO_PORT1             34
 #define IRQ_U300_GPIO_PORT2             35
 
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
-    defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
 #define IRQ_U300_WDOG                   36
 #define IRQ_U300_EVHIST                 37
@@ -68,15 +62,8 @@
 #define IRQ_U300_RTC                    43
 #define IRQ_U300_NFIF                   44
 #define IRQ_U300_NFIF2                  45
-#endif
-
-/* DB3150 and DB3200 have only 45 IRQs */
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END               46
-#endif
 
 /* The DB3350-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS335
 #define IRQ_U300_ISP_F0                 46
 #define IRQ_U300_ISP_F1                 47
 #define IRQ_U300_ISP_F2                 48
@@ -89,25 +76,6 @@
 #define IRQ_U300_GPIO_PORT5             55
 #define IRQ_U300_GPIO_PORT6             56
 #define U300_VIC_IRQS_END               57
-#endif
-
-/* The DB3210-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3             36
-#define IRQ_U300_GPIO_PORT4             37
-#define IRQ_U300_WDOG                   38
-#define IRQ_U300_EVHIST                 39
-#define IRQ_U300_MSPRO                  40
-#define IRQ_U300_MMCSD_MCIINTR0         41
-#define IRQ_U300_MMCSD_MCIINTR1         42
-#define IRQ_U300_I2C0                   43
-#define IRQ_U300_I2C1                   44
-#define IRQ_U300_RTC                    45
-#define IRQ_U300_NFIF                   46
-#define IRQ_U300_NFIF2                  47
-#define IRQ_U300_SYSCON_PLL_LOCK        48
-#define U300_VIC_IRQS_END               49
-#endif
 
 /* Maximum 8*7 GPIO lines */
 #ifdef CONFIG_PINCTRL_COH901
@@ -117,6 +85,6 @@
 #define IRQ_U300_GPIO_END               (U300_VIC_IRQS_END)
 #endif
 
-#define NR_IRQS                         (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
+#define NR_IRQS_U300                    (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 
 #endif
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
deleted file mode 100644
index 096333f32fc3..000000000000
--- a/arch/arm/mach-u300/include/mach/platform.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/platform.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic platform init and mapping functions.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __ASSEMBLY__
-
-void u300_map_io(void);
-void u300_init_irq(void);
-void u300_init_devices(void);
-void u300_restart(char, const char *);
-extern struct sys_timer u300_timer;
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
index 6e84f07a7c6f..10bdd0be9774 100644
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/syscon.h
  *
  *
- * Copyright (C) 2008 ST-Ericsson AB
+ * Copyright (C) 2008-2012 ST-Ericsson AB
  *
  * Author: Rickard Andersson <rickard.andersson@stericsson.com>
  */
@@ -36,9 +36,7 @@
 #define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
 /* Reset lines for SLOW devices 16bit (R/W) */
 #define U300_SYSCON_RSR                                         (0x0014)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
-#endif
 #define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
 #define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
 #define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
@@ -50,9 +48,7 @@
 #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
 /* Reset lines for FAST devices 16bit (R/W) */
 #define U300_SYSCON_RFR                                         (0x0018)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
-#endif
 #define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
 #define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
 #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
@@ -62,10 +58,8 @@
 #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
 /* Reset lines for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_RRR                                         (0x001c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
 #define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
-#endif
 #define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
 #define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
 #define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
@@ -79,9 +73,7 @@
 #define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
 /* Clock enable for SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CESR                                        (0x0020)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
-#endif
 #define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
 #define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
 #define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
@@ -92,24 +84,20 @@
 #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
 /* Clock enable for FAST peripherals 16bit (R/W) */
 #define U300_SYSCON_CEFR                                        (0x0024)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
-#endif
 #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
 #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
 #define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
 #define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
 #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
 /* Clock enable for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CERR                                        (0x0028)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
 #define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
-#endif
 #define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
 #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
 #define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
@@ -124,9 +112,7 @@
 #define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
 /* Single block clock enable 16bit (-/W) */
 #define U300_SYSCON_SBCER                                       (0x002c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
-#endif
 #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
 #define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
 #define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
@@ -135,9 +121,7 @@
 #define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
 #define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
 #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
-#endif
 #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
 #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
 #define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
@@ -147,10 +131,8 @@
 #define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
 #define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
 #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
 #define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
-#endif
 #define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
 #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
 #define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
@@ -168,9 +150,7 @@
 /* Same values as above for SBCER */
 /* Clock force SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CFSR                                        (0x003c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
-#endif
 #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
 #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
 #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
@@ -184,10 +164,8 @@
 /* Values not defined. Define if you want to use them. */
 /* Clock force the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CFRR                                        (0x44)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
 #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
-#endif
 #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
 #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
 #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 65f87c523892..1e49d901f2c9 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -28,7 +28,6 @@
 #define PLAT_NAND_CLE                   (1 << 16)
 #define PLAT_NAND_ALE                   (1 << 17)
 
-
 /* AHB Peripherals */
 #define U300_AHB_PER_PHYS_BASE          0xa0000000
 #define U300_AHB_PER_VIRT_BASE          0xff010000
@@ -46,11 +45,7 @@
 #define U300_BOOTROM_VIRT_BASE          0xffff0000
 
 /* SEMI config base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SEMI_CONFIG_BASE           0x2FFE0000
-#else
-#define U300_SEMI_CONFIG_BASE           0x30000000
-#endif
 
 /*
  * AHB peripherals
@@ -99,10 +94,8 @@
 /* SPI controller */
 #define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
 
-#ifdef CONFIG_MACH_U300_BS335
 /* Fast UART1 on U335 only */
 #define U300_UART1_BASE                 (U300_SLOW_PER_PHYS_BASE+0x7000)
-#endif
 
 /*
  * SLOW peripherals
@@ -151,10 +144,8 @@
  * REST peripherals
  */
 
-/* ISP (image signal processor) is only available in U335 */
-#ifdef CONFIG_MACH_U300_BS335
+/* ISP (image signal processor) */
 #define U300_ISP_BASE                   (0xA0008000)
-#endif
 
 /* DMA Controller base */
 #define U300_DMAC_BASE                  (0xC0020000)
@@ -166,17 +157,9 @@
 #define U300_APEX_BASE                  (0xc0030000)
 
 /* Video Encoder Base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_VIDEOENC_BASE              (0xc0080000)
-#else
-#define U300_VIDEOENC_BASE              (0xc0040000)
-#endif
 
 /* XGAM Base */
 #define U300_XGAM_BASE                  (0xd0000000)
 
-/*
- * Virtual accessor macros for static devices
- */
-
 #endif
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index a1affacfa59c..02e6659286d5 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -12,7 +12,7 @@
 #include <linux/amba/pl022.h>
 #include <linux/err.h>
 #include <mach/coh901318.h>
-#include <mach/dma_channels.h>
+#include "dma_channels.h"
 
 /*
  * The following is for the actual devices on the SSP/SPI bus
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 56ac06d38ec1..1da10e20e996 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -17,14 +17,17 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/irq.h>
+
+#include "timer.h"
 
 /*
  * APP side special timer registers
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
new file mode 100644
index 000000000000..b5e9791762e0
--- /dev/null
+++ b/arch/arm/mach-u300/timer.h
@@ -0,0 +1 @@
+extern struct sys_timer u300_timer;
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
index 847dc25300c6..83f50772e169 100644
--- a/arch/arm/mach-u300/u300-gpio.h
+++ b/arch/arm/mach-u300/u300-gpio.h
@@ -1,50 +1,11 @@
 /*
- * Individual pin assignments for the B26/S26. Notice that the
- * actual usage of these pins depends on the PAD MUX settings, that
- * is why the same number can potentially appear several times.
- * In the reference design each pin is only used for one purpose.
- * These were determined by inspecting the B26/S26 schematic:
- * 2/1911-ROA 128 1603
- */
-#ifdef CONFIG_MACH_U300_BS2X
-#define U300_GPIO_PIN_UART_RX           0
-#define U300_GPIO_PIN_UART_TX           1
-#define U300_GPIO_PIN_GPIO02            2  /* Unrouted */
-#define U300_GPIO_PIN_GPIO03            3  /* Unrouted */
-#define U300_GPIO_PIN_CAM_SLEEP         4
-#define U300_GPIO_PIN_CAM_REG_EN        5
-#define U300_GPIO_PIN_GPIO06            6  /* Unrouted */
-#define U300_GPIO_PIN_GPIO07            7  /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO08            8  /* Service point SP2321 */
-#define U300_GPIO_PIN_GPIO09            9  /* Service point SP2322 */
-#define U300_GPIO_PIN_PHFSENSE          10 /* Headphone jack sensing */
-#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_FLIPSENSE         13 /* Mechanical flip sensing */
-#define U300_GPIO_PIN_GPIO14            14 /* DSP JTAG Port RTCK */
-#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16            16 /* Unrouted */
-#define U300_GPIO_PIN_GPIO17            17 /* Unrouted */
-#define U300_GPIO_PIN_GPIO18            18 /* Unrouted */
-#define U300_GPIO_PIN_GPIO19            19 /* Unrouted */
-#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
-#endif
-
-/*
- * Individual pin assignments for the B330/S330 and B365/S365.
+ * Individual pin assignments for the B335/S335.
  * Notice that the actual usage of these pins depends on the
  * PAD MUX settings, that is why the same number can potentially
  * appear several times. In the reference design each pin is only
  * used for one purpose. These were determined by inspecting the
  * S365 schematic.
  */
-#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
-    defined(CONFIG_MACH_U300_BS335)
 #define U300_GPIO_PIN_UART_RX           0
 #define U300_GPIO_PIN_UART_TX           1
 #define U300_GPIO_PIN_UART_CTS          2
@@ -90,8 +51,6 @@
 #define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
 #define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
 
-#ifdef CONFIG_MACH_U300_BS335
-
 #define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
 #define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
 #define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
@@ -109,6 +68,3 @@
 #define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
 #define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
 #define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
deleted file mode 100644
index f30c69d91d99..000000000000
--- a/arch/arm/mach-u300/u300.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/u300.c
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform machine definition.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/memblock.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <asm/hardware/vic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/memory.h>
-
-static void __init u300_init_machine(void)
-{
-        u300_init_devices();
-}
-
-#ifdef CONFIG_MACH_U300_BS2X
-#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS330
-#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS335
-#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS365
-#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
-#endif
-
-MACHINE_START(U300, MACH_U300_STRING)
-        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .atag_offset    = 0x100,
-        .map_io         = u300_map_io,
-        .init_irq       = u300_init_irq,
-        .handle_irq     = vic_handle_irq,
-        .timer          = &u300_timer,
-        .init_machine   = u300_init_machine,
-        .restart        = u300_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 53d3d46dec12..a258996d954b 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
         select CACHE_L2X0
         select PINCTRL
         select PINCTRL_NOMADIK
+        select COMMON_CLK
 
 config UX500_SOC_DB8500
         bool
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 026086ff9e6c..5691ef679d01 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel, U8500 machine.
 #
 
-obj-y                           := clock.o cpu.o devices.o devices-common.o \
+obj-y                           := cpu.o devices.o devices-common.o \
                                    id.o usb.o timer.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot
index dd5cd00e2554..760a0efe7580 100644
--- a/arch/arm/mach-ux500/Makefile.boot
+++ b/arch/arm/mach-ux500/Makefile.boot
@@ -1,5 +1,3 @@
    zreladdr-y   += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-
-dtb-$(CONFIG_MACH_SNOWBALL) += snowball.dtb
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 1d2e3c6f8b59..7ebfcc7d7515 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -48,7 +48,7 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
 #include <mach/irqs.h>
-#include <mach/crypto-ux500.h>
+#include <linux/platform_data/crypto-ux500.h>
 
 #include "ste-dma40-db8500.h"
 #include "devices-db8500.h"
@@ -673,6 +673,7 @@ static void __init hrefv60_init_machine(void)
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
         /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
         .atag_offset    = 0x100,
+        .smp            = smp_ops(ux500_smp_ops),
         .map_io         = u8500_map_io,
         .init_irq       = ux500_init_irq,
         /* we re-use nomadik timer here */
@@ -684,6 +685,7 @@ MACHINE_END
 
 MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
         .atag_offset    = 0x100,
+        .smp            = smp_ops(ux500_smp_ops),
         .map_io         = u8500_map_io,
         .init_irq       = ux500_init_irq,
         .timer          = &ux500_timer,
@@ -694,6 +696,7 @@ MACHINE_END
 
 MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
         .atag_offset    = 0x100,
+        .smp            = smp_ops(ux500_smp_ops),
         .map_io         = u8500_map_io,
         .init_irq       = ux500_init_irq,
         /* we re-use nomadik timer here */
@@ -823,6 +826,7 @@ static const char * u8500_dt_board_compat[] = {
 
 
 DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)")
+        .smp            = smp_ops(ux500_smp_ops),
         .map_io         = u8500_map_io,
         .init_irq       = ux500_init_irq,
         /* we re-use nomadik timer here */
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index dc12394295d5..75d5b512a3d5 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -38,7 +38,7 @@ static int __init ux500_l2x0_init(void)
 {
         u32 aux_val = 0x3e000000;
 
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 l2x0_base = __io_address(U8500_L2CC_BASE);
         else
                 ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
deleted file mode 100644
index 8d73b066a18d..000000000000
--- a/arch/arm/mach-ux500/clock.c
+++ /dev/null
@@ -1,715 +0,0 @@
-/*
- *  Copyright (C) 2009 ST-Ericsson
- *  Copyright (C) 2009 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/cpufreq.h>
-
-#include <plat/mtu.h>
-#include <mach/hardware.h>
-#include "clock.h"
-
-#ifdef CONFIG_DEBUG_FS
-#include <linux/debugfs.h>
-#include <linux/uaccess.h>      /* for copy_from_user */
-static LIST_HEAD(clk_list);
-#endif
-
-#define PRCC_PCKEN              0x00
-#define PRCC_PCKDIS             0x04
-#define PRCC_KCKEN              0x08
-#define PRCC_KCKDIS             0x0C
-
-#define PRCM_YYCLKEN0_MGT_SET   0x510
-#define PRCM_YYCLKEN1_MGT_SET   0x514
-#define PRCM_YYCLKEN0_MGT_CLR   0x518
-#define PRCM_YYCLKEN1_MGT_CLR   0x51C
-#define PRCM_YYCLKEN0_MGT_VAL   0x520
-#define PRCM_YYCLKEN1_MGT_VAL   0x524
-
-#define PRCM_SVAMMDSPCLK_MGT    0x008
-#define PRCM_SIAMMDSPCLK_MGT    0x00C
-#define PRCM_SGACLK_MGT         0x014
-#define PRCM_UARTCLK_MGT        0x018
-#define PRCM_MSP02CLK_MGT       0x01C
-#define PRCM_MSP1CLK_MGT        0x288
-#define PRCM_I2CCLK_MGT         0x020
-#define PRCM_SDMMCCLK_MGT       0x024
-#define PRCM_SLIMCLK_MGT        0x028
-#define PRCM_PER1CLK_MGT        0x02C
-#define PRCM_PER2CLK_MGT        0x030
-#define PRCM_PER3CLK_MGT        0x034
-#define PRCM_PER5CLK_MGT        0x038
-#define PRCM_PER6CLK_MGT        0x03C
-#define PRCM_PER7CLK_MGT        0x040
-#define PRCM_LCDCLK_MGT         0x044
-#define PRCM_BMLCLK_MGT         0x04C
-#define PRCM_HSITXCLK_MGT       0x050
-#define PRCM_HSIRXCLK_MGT       0x054
-#define PRCM_HDMICLK_MGT        0x058
-#define PRCM_APEATCLK_MGT       0x05C
-#define PRCM_APETRACECLK_MGT    0x060
-#define PRCM_MCDECLK_MGT        0x064
-#define PRCM_IPI2CCLK_MGT       0x068
-#define PRCM_DSIALTCLK_MGT      0x06C
-#define PRCM_DMACLK_MGT         0x074
-#define PRCM_B2R2CLK_MGT        0x078
-#define PRCM_TVCLK_MGT          0x07C
-#define PRCM_TCR                0x1C8
-#define PRCM_TCR_STOPPED        (1 << 16)
-#define PRCM_TCR_DOZE_MODE      (1 << 17)
-#define PRCM_UNIPROCLK_MGT      0x278
-#define PRCM_SSPCLK_MGT         0x280
-#define PRCM_RNGCLK_MGT         0x284
-#define PRCM_UICCCLK_MGT        0x27C
-
-#define PRCM_MGT_ENABLE         (1 << 8)
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-static void __clk_enable(struct clk *clk)
-{
-        if (clk->enabled++ == 0) {
-                if (clk->parent_cluster)
-                        __clk_enable(clk->parent_cluster);
-
-                if (clk->parent_periph)
-                        __clk_enable(clk->parent_periph);
-
-                if (clk->ops && clk->ops->enable)
-                        clk->ops->enable(clk);
-        }
-}
-
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        __clk_enable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
-        if (--clk->enabled == 0) {
-                if (clk->ops && clk->ops->disable)
-                        clk->ops->disable(clk);
-
-                if (clk->parent_periph)
-                        __clk_disable(clk->parent_periph);
-
-                if (clk->parent_cluster)
-                        __clk_disable(clk->parent_cluster);
-        }
-}
-
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-
-        WARN_ON(!clk->enabled);
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        __clk_disable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/*
- * The MTU has a separate, rather complex muxing setup
- * with alternative parents (peripheral cluster or
- * ULP or fixed 32768 Hz) depending on settings
- */
-static unsigned long clk_mtu_get_rate(struct clk *clk)
-{
-        void __iomem *addr;
-        u32 tcr;
-        int mtu = (int) clk->data;
-        /*
-         * One of these is selected eventually
-         * TODO: Replace the constant with a reference
-         * to the ULP source once this is modeled.
-         */
-        unsigned long clk32k = 32768;
-        unsigned long mturate;
-        unsigned long retclk;
-
-        if (cpu_is_u8500_family())
-                addr = __io_address(U8500_PRCMU_BASE);
-        else
-                ux500_unknown_soc();
-
-        /*
-         * On a startup, always conifgure the TCR to the doze mode;
-         * bootloaders do it for us. Do this in the kernel too.
-         */
-        writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
-
-        tcr = readl(addr + PRCM_TCR);
-
-        /* Get the rate from the parent as a default */
-        if (clk->parent_periph)
-                mturate = clk_get_rate(clk->parent_periph);
-        else if (clk->parent_cluster)
-                mturate = clk_get_rate(clk->parent_cluster);
-        else
-                /* We need to be connected SOMEWHERE */
-                BUG();
-
-        /* Return the clock selected for this MTU */
-        if (tcr & (1 << mtu))
-                retclk = clk32k;
-        else
-                retclk = mturate;
-
-        pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
-        return retclk;
-}
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long rate;
-
-        /*
-         * If there is a custom getrate callback for this clock,
-         * it will take precedence.
-         */
-        if (clk->get_rate)
-                return clk->get_rate(clk);
-
-        if (clk->ops && clk->ops->get_rate)
-                return clk->ops->get_rate(clk);
-
-        rate = clk->rate;
-        if (!rate) {
-                if (clk->parent_periph)
-                        rate = clk_get_rate(clk->parent_periph);
-                else if (clk->parent_cluster)
-                        rate = clk_get_rate(clk->parent_cluster);
-        }
-
-        return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        /*TODO*/
-        return rate;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        clk->rate = rate;
-        return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        /*TODO*/
-        return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-static void clk_prcmu_enable(struct clk *clk)
-{
-        void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
-                                   + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
-
-        writel(1 << clk->prcmu_cg_bit, cg_set_reg);
-}
-
-static void clk_prcmu_disable(struct clk *clk)
-{
-        void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
-                                   + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
-
-        writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
-}
-
-static struct clkops clk_prcmu_ops = {
-        .enable = clk_prcmu_enable,
-        .disable = clk_prcmu_disable,
-};
-
-static unsigned int clkrst_base[] = {
-        [1] = U8500_CLKRST1_BASE,
-        [2] = U8500_CLKRST2_BASE,
-        [3] = U8500_CLKRST3_BASE,
-        [5] = U8500_CLKRST5_BASE,
-        [6] = U8500_CLKRST6_BASE,
-};
-
-static void clk_prcc_enable(struct clk *clk)
-{
-        void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
-
-        if (clk->prcc_kernel != -1)
-                writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
-
-        if (clk->prcc_bus != -1)
-                writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
-}
-
-static void clk_prcc_disable(struct clk *clk)
-{
-        void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
-
-        if (clk->prcc_bus != -1)
-                writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
-
-        if (clk->prcc_kernel != -1)
-                writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
-}
-
-static struct clkops clk_prcc_ops = {
-        .enable = clk_prcc_enable,
-        .disable = clk_prcc_disable,
-};
-
-static struct clk clk_32khz = {
-        .name =  "clk_32khz",
-        .rate = 32000,
-};
-
-/*
- * PRCMU level clock gating
- */
-
-/* Bank 0 */
-static DEFINE_PRCMU_CLK(svaclk,         0x0, 2, SVAMMDSPCLK);
-static DEFINE_PRCMU_CLK(siaclk,         0x0, 3, SIAMMDSPCLK);
-static DEFINE_PRCMU_CLK(sgaclk,         0x0, 4, SGACLK);
-static DEFINE_PRCMU_CLK_RATE(uartclk,   0x0, 5, UARTCLK, 38400000);
-static DEFINE_PRCMU_CLK(msp02clk,       0x0, 6, MSP02CLK);
-static DEFINE_PRCMU_CLK(msp1clk,        0x0, 7, MSP1CLK); /* v1 */
-static DEFINE_PRCMU_CLK_RATE(i2cclk,    0x0, 8, I2CCLK, 48000000);
-static DEFINE_PRCMU_CLK_RATE(sdmmcclk,  0x0, 9, SDMMCCLK, 100000000);
-static DEFINE_PRCMU_CLK(slimclk,        0x0, 10, SLIMCLK);
-static DEFINE_PRCMU_CLK(per1clk,        0x0, 11, PER1CLK);
-static DEFINE_PRCMU_CLK(per2clk,        0x0, 12, PER2CLK);
-static DEFINE_PRCMU_CLK(per3clk,        0x0, 13, PER3CLK);
-static DEFINE_PRCMU_CLK(per5clk,        0x0, 14, PER5CLK);
-static DEFINE_PRCMU_CLK_RATE(per6clk,   0x0, 15, PER6CLK, 133330000);
-static DEFINE_PRCMU_CLK(lcdclk,         0x0, 17, LCDCLK);
-static DEFINE_PRCMU_CLK(bmlclk,         0x0, 18, BMLCLK);
-static DEFINE_PRCMU_CLK(hsitxclk,       0x0, 19, HSITXCLK);
-static DEFINE_PRCMU_CLK(hsirxclk,       0x0, 20, HSIRXCLK);
-static DEFINE_PRCMU_CLK(hdmiclk,        0x0, 21, HDMICLK);
-static DEFINE_PRCMU_CLK(apeatclk,       0x0, 22, APEATCLK);
-static DEFINE_PRCMU_CLK(apetraceclk,    0x0, 23, APETRACECLK);
-static DEFINE_PRCMU_CLK(mcdeclk,        0x0, 24, MCDECLK);
-static DEFINE_PRCMU_CLK(ipi2clk,        0x0, 25, IPI2CCLK);
-static DEFINE_PRCMU_CLK(dsialtclk,      0x0, 26, DSIALTCLK); /* v1 */
-static DEFINE_PRCMU_CLK(dmaclk,         0x0, 27, DMACLK);
-static DEFINE_PRCMU_CLK(b2r2clk,        0x0, 28, B2R2CLK);
-static DEFINE_PRCMU_CLK(tvclk,          0x0, 29, TVCLK);
-static DEFINE_PRCMU_CLK(uniproclk,      0x0, 30, UNIPROCLK); /* v1 */
-static DEFINE_PRCMU_CLK_RATE(sspclk,    0x0, 31, SSPCLK, 48000000); /* v1 */
-
-/* Bank 1 */
-static DEFINE_PRCMU_CLK(rngclk,         0x4, 0, RNGCLK); /* v1 */
-static DEFINE_PRCMU_CLK(uiccclk,        0x4, 1, UICCCLK); /* v1 */
-
-/*
- * PRCC level clock gating
- * Format: per#, clk, PCKEN bit, KCKEN bit, parent
- */
-
-/* Peripheral Cluster #1 */
-static DEFINE_PRCC_CLK(1, msp3,         11, 10, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, gpio0,        9, -1, NULL);
-static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
-static DEFINE_PRCC_CLK(1, spi3,         7, -1, NULL);
-static DEFINE_PRCC_CLK(1, i2c2,         6,  6, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, sdi0,         5,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(1, msp1,         4,  4, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, msp0,         3,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(1, i2c1,         2,  2, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, uart1,        1,  1, &clk_uartclk);
-static DEFINE_PRCC_CLK(1, uart0,        0,  0, &clk_uartclk);
-
-/* Peripheral Cluster #2 */
-static DEFINE_PRCC_CLK(2, gpio1,        11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx,        10,  7, NULL);
-static DEFINE_PRCC_CLK(2, ssirx,         9,  6, NULL);
-static DEFINE_PRCC_CLK(2, spi0,         8, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3,         7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1,         6,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2,         5,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4,         4,  2, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, pwl,          3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1,         2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2,         1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3,         0,  0, &clk_i2cclk);
-
-/* Peripheral Cluster #3 */
-static DEFINE_PRCC_CLK(3, gpio2,        8, -1, NULL);
-static DEFINE_PRCC_CLK(3, sdi5,         7,  7, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, uart2,        6,  6, &clk_uartclk);
-static DEFINE_PRCC_CLK(3, ske,          5,  5, &clk_32khz);
-static DEFINE_PRCC_CLK(3, sdi2,         4,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, i2c0,         3,  3, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1,         2,  2, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, ssp0,         1,  1, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, fsmc,         0, -1, NULL);
-
-/* Peripheral Cluster #4 is in the always on domain */
-
-/* Peripheral Cluster #5 */
-static DEFINE_PRCC_CLK(5, gpio3,        1, -1, NULL);
-static DEFINE_PRCC_CLK(5, usb,          0,  0, NULL);
-
-/* Peripheral Cluster #6 */
-
-/* MTU ID in data */
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(6, cfgreg,       7,  7, NULL);
-static DEFINE_PRCC_CLK(6, hash1,        6, -1, NULL);
-static DEFINE_PRCC_CLK(6, unipro,       5,  1, &clk_uniproclk);
-static DEFINE_PRCC_CLK(6, pka,          4, -1, NULL);
-static DEFINE_PRCC_CLK(6, hash0,        3, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp0,        2, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp1,    1, -1, NULL);
-static DEFINE_PRCC_CLK(6, rng,  0,  0, &clk_rngclk);
-
-static struct clk clk_dummy_apb_pclk = {
-        .name = "apb_pclk",
-};
-
-static struct clk_lookup u8500_clks[] = {
-        CLK(dummy_apb_pclk, NULL,       "apb_pclk"),
-
-        /* Peripheral Cluster #1 */
-        CLK(gpio0,      "gpio.0",       NULL),
-        CLK(gpio0,      "gpio.1",       NULL),
-        CLK(slimbus0,   "slimbus0",     NULL),
-        CLK(i2c2,       "nmk-i2c.2",    NULL),
-        CLK(sdi0,       "sdi0",         NULL),
-        CLK(msp0,       "ux500-msp-i2s.0",      NULL),
-        CLK(i2c1,       "nmk-i2c.1",    NULL),
-        CLK(uart1,      "uart1",        NULL),
-        CLK(uart0,      "uart0",        NULL),
-
-        /* Peripheral Cluster #3 */
-        CLK(gpio2,      "gpio.2",       NULL),
-        CLK(gpio2,      "gpio.3",       NULL),
-        CLK(gpio2,      "gpio.4",       NULL),
-        CLK(gpio2,      "gpio.5",       NULL),
-        CLK(sdi5,       "sdi5",         NULL),
-        CLK(uart2,      "uart2",        NULL),
-        CLK(ske,        "ske",          NULL),
-        CLK(ske,        "nmk-ske-keypad",       NULL),
-        CLK(sdi2,       "sdi2",         NULL),
-        CLK(i2c0,       "nmk-i2c.0",    NULL),
-        CLK(fsmc,       "fsmc",         NULL),
-
-        /* Peripheral Cluster #5 */
-        CLK(gpio3,      "gpio.8",       NULL),
-
-        /* Peripheral Cluster #6 */
-        CLK(hash1,      "hash1",        NULL),
-        CLK(pka,        "pka",          NULL),
-        CLK(hash0,      "hash0",        NULL),
-        CLK(cryp0,      "cryp0",        NULL),
-        CLK(cryp1,  "cryp1",    NULL),
-
-        /* PRCMU level clock gating */
-
-        /* Bank 0 */
-        CLK(svaclk,     "sva",          NULL),
-        CLK(siaclk,     "sia",          NULL),
-        CLK(sgaclk,     "sga",          NULL),
-        CLK(slimclk,    "slim",         NULL),
-        CLK(lcdclk,     "lcd",          NULL),
-        CLK(bmlclk,     "bml",          NULL),
-        CLK(hsitxclk,   "stm-hsi.0",    NULL),
-        CLK(hsirxclk,   "stm-hsi.1",    NULL),
-        CLK(hdmiclk,    "hdmi",         NULL),
-        CLK(apeatclk,   "apeat",        NULL),
-        CLK(apetraceclk,        "apetrace",     NULL),
-        CLK(mcdeclk,    "mcde",         NULL),
-        CLK(ipi2clk,    "ipi2",         NULL),
-        CLK(dmaclk,     "dma40.0",      NULL),
-        CLK(b2r2clk,    "b2r2",         NULL),
-        CLK(tvclk,      "tv",           NULL),
-
-        /* Peripheral Cluster #1 */
-        CLK(i2c4,       "nmk-i2c.4",    NULL),
-        CLK(spi3,       "spi3",         NULL),
-        CLK(msp1,       "ux500-msp-i2s.1",      NULL),
-        CLK(msp3,       "ux500-msp-i2s.3",      NULL),
-
-        /* Peripheral Cluster #2 */
-        CLK(gpio1,      "gpio.6",       NULL),
-        CLK(gpio1,      "gpio.7",       NULL),
-        CLK(ssitx,      "ssitx",        NULL),
-        CLK(ssirx,      "ssirx",        NULL),
-        CLK(spi0,       "spi0",         NULL),
-        CLK(sdi3,       "sdi3",         NULL),
-        CLK(sdi1,       "sdi1",         NULL),
-        CLK(msp2,       "ux500-msp-i2s.2",      NULL),
-        CLK(sdi4,       "sdi4",         NULL),
-        CLK(pwl,        "pwl",          NULL),
-        CLK(spi1,       "spi1",         NULL),
-        CLK(spi2,       "spi2",         NULL),
-        CLK(i2c3,       "nmk-i2c.3",    NULL),
-
-        /* Peripheral Cluster #3 */
-        CLK(ssp1,       "ssp1",         NULL),
-        CLK(ssp0,       "ssp0",         NULL),
-
-        /* Peripheral Cluster #5 */
-        CLK(usb,        "musb-ux500.0", "usb"),
-
-        /* Peripheral Cluster #6 */
-        CLK(mtu1,       "mtu1",         NULL),
-        CLK(mtu0,       "mtu0",         NULL),
-        CLK(cfgreg,     "cfgreg",       NULL),
-        CLK(hash1,      "hash1",        NULL),
-        CLK(unipro,     "unipro",       NULL),
-        CLK(rng,        "rng",          NULL),
-
-        /* PRCMU level clock gating */
-
-        /* Bank 0 */
-        CLK(uniproclk,  "uniproclk",    NULL),
-        CLK(dsialtclk,  "dsialt",       NULL),
-
-        /* Bank 1 */
-        CLK(rngclk,     "rng",          NULL),
-        CLK(uiccclk,    "uicc",         NULL),
-};
-
-#ifdef CONFIG_DEBUG_FS
-/*
- *      debugfs support to trace clock tree hierarchy and attributes with
- *      powerdebug
- */
-static struct dentry *clk_debugfs_root;
-
-void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
-{
-        while (num--) {
-                /* Check that the clock has not been already registered */
-                if (!(cl->clk->list.prev != cl->clk->list.next))
-                        list_add_tail(&cl->clk->list, &clk_list);
-
-                cl++;
-        }
-}
-
-static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
-                                                  size_t size, loff_t *off)
-{
-        struct clk *clk = file->f_dentry->d_inode->i_private;
-        char cusecount[128];
-        unsigned int len;
-
-        len = sprintf(cusecount, "%u\n", clk->enabled);
-        return simple_read_from_buffer(buf, size, off, cusecount, len);
-}
-
-static ssize_t rate_dbg_read(struct file *file, char __user *buf,
-                                          size_t size, loff_t *off)
-{
-        struct clk *clk = file->f_dentry->d_inode->i_private;
-        char crate[128];
-        unsigned int rate;
-        unsigned int len;
-
-        rate = clk_get_rate(clk);
-        len = sprintf(crate, "%u\n", rate);
-        return simple_read_from_buffer(buf, size, off, crate, len);
-}
-
-static const struct file_operations usecount_fops = {
-        .read = usecount_dbg_read,
-};
-
-static const struct file_operations set_rate_fops = {
-        .read = rate_dbg_read,
-};
-
-static struct dentry *clk_debugfs_register_dir(struct clk *c,
-                                                struct dentry *p_dentry)
-{
-        struct dentry *d, *clk_d;
-        const char *p = c->name;
-
-        if (!p)
-                p = "BUG";
-
-        clk_d = debugfs_create_dir(p, p_dentry);
-        if (!clk_d)
-                return NULL;
-
-        d = debugfs_create_file("usecount", S_IRUGO,
-                                clk_d, c, &usecount_fops);
-        if (!d)
-                goto err_out;
-        d = debugfs_create_file("rate", S_IRUGO,
-                                clk_d, c, &set_rate_fops);
-        if (!d)
-                goto err_out;
-        /*
-         * TODO : not currently available in ux500
-         * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
-         * if (!d)
-         *      goto err_out;
-         */
-
-        return clk_d;
-
-err_out:
-        debugfs_remove_recursive(clk_d);
-        return NULL;
-}
-
-static int clk_debugfs_register_one(struct clk *c)
-{
-        struct clk *pa = c->parent_periph;
-        struct clk *bpa = c->parent_cluster;
-
-        if (!(bpa && !pa)) {
-                c->dent = clk_debugfs_register_dir(c,
-                                pa ? pa->dent : clk_debugfs_root);
-                if (!c->dent)
-                        return -ENOMEM;
-        }
-
-        if (bpa) {
-                c->dent_bus = clk_debugfs_register_dir(c,
-                                bpa->dent_bus ? bpa->dent_bus : bpa->dent);
-                if ((!c->dent_bus) &&  (c->dent)) {
-                        debugfs_remove_recursive(c->dent);
-                        c->dent = NULL;
-                        return -ENOMEM;
-                }
-        }
-        return 0;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->parent_periph;
-        struct clk *bpa = c->parent_cluster;
-
-        if (pa && (!pa->dent && !pa->dent_bus)) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-
-        if (bpa && (!bpa->dent && !bpa->dent_bus)) {
-                err = clk_debugfs_register(bpa);
-                if (err)
-                        return err;
-        }
-
-        if ((!c->dent) && (!c->dent_bus)) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-
-int __init clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err;
-
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-
-        list_for_each_entry(c, &clk_list, list) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-
-#endif /* defined(CONFIG_DEBUG_FS) */
-
-unsigned long clk_smp_twd_rate = 500000000;
-
-unsigned long clk_smp_twd_get_rate(struct clk *clk)
-{
-        return clk_smp_twd_rate;
-}
-
-static struct clk clk_smp_twd = {
-        .get_rate = clk_smp_twd_get_rate,
-        .name =  "smp_twd",
-};
-
-static struct clk_lookup clk_smp_twd_lookup = {
-        .dev_id = "smp_twd",
-        .clk = &clk_smp_twd,
-};
-
-#ifdef CONFIG_CPU_FREQ
-
-static int clk_twd_cpufreq_transition(struct notifier_block *nb,
-                                      unsigned long state, void *data)
-{
-        struct cpufreq_freqs *f = data;
-
-        if (state == CPUFREQ_PRECHANGE) {
-                /* Save frequency in simple Hz */
-                clk_smp_twd_rate = (f->new * 1000) / 2;
-        }
-
-        return NOTIFY_OK;
-}
-
-static struct notifier_block clk_twd_cpufreq_nb = {
-        .notifier_call = clk_twd_cpufreq_transition,
-};
-
-int clk_init_smp_twd_cpufreq(void)
-{
-        return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
-                                  CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-#endif
-
-int __init clk_init(void)
-{
-        clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
-        clkdev_add(&clk_smp_twd_lookup);
-
-#ifdef CONFIG_DEBUG_FS
-        clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
-#endif
-        return 0;
-}
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
deleted file mode 100644
index 65d27a13f46d..000000000000
--- a/arch/arm/mach-ux500/clock.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- *  Copyright (C) 2010 ST-Ericsson
- *  Copyright (C) 2009 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/**
- * struct clkops - ux500 clock operations
- * @enable:     function to enable the clock
- * @disable:    function to disable the clock
- * @get_rate:   function to get the current clock rate
- *
- * This structure contains function pointers to functions that will be used to
- * control the clock.  All of these functions are optional.  If get_rate is
- * NULL, the rate in the struct clk will be used.
- */
-struct clkops {
-        void (*enable) (struct clk *);
-        void (*disable) (struct clk *);
-        unsigned long (*get_rate) (struct clk *);
-        int (*set_parent)(struct clk *, struct clk *);
-};
-
-/**
- * struct clk - ux500 clock structure
- * @ops:                pointer to clkops struct used to control this clock
- * @name:               name, for debugging
- * @enabled:            refcount. positive if enabled, zero if disabled
- * @get_rate:           custom callback for getting the clock rate
- * @data:               custom per-clock data for example for the get_rate
- *                      callback
- * @rate:               fixed rate for clocks which don't implement
- *                      ops->getrate
- * @prcmu_cg_off:       address offset of the combined enable/disable register
- *                      (used on u8500v1)
- * @prcmu_cg_bit:       bit in the combined enable/disable register (used on
- *                      u8500v1)
- * @prcmu_cg_mgt:       address of the enable/disable register (used on
- *                      u8500ed)
- * @cluster:            peripheral cluster number
- * @prcc_bus:           bit for the bus clock in the peripheral's CLKRST
- * @prcc_kernel:        bit for the kernel clock in the peripheral's CLKRST.
- *                      -1 if no kernel clock exists.
- * @parent_cluster:     pointer to parent's cluster clk struct
- * @parent_periph:      pointer to parent's peripheral clk struct
- *
- * Peripherals are organised into clusters, and each cluster has an associated
- * bus clock.  Some peripherals also have a parent peripheral clock.
- *
- * In order to enable a clock for a peripheral, we need to enable:
- *      (1) the parent cluster (bus) clock at the PRCMU level
- *      (2) the parent peripheral clock (if any) at the PRCMU level
- *      (3) the peripheral's bus & kernel clock at the PRCC level
- *
- * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
- * of the cluster and peripheral clocks, and hooking these as the parents of
- * the individual peripheral clocks.
- *
- * (3) is handled by specifying the bits in the PRCC control registers required
- * to enable these clocks and modifying them in the ->enable and
- * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
- *
- * This structure describes both the PRCMU-level clocks and PRCC-level clocks.
- * The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
- * prcc, and parent pointers are only used for the PRCC-level clocks.
- */
-struct clk {
-        const struct clkops     *ops;
-        const char              *name;
-        unsigned int            enabled;
-        unsigned long           (*get_rate)(struct clk *);
-        void                    *data;
-
-        unsigned long           rate;
-        struct list_head        list;
-
-        /* These three are only for PRCMU clks */
-
-        unsigned int            prcmu_cg_off;
-        unsigned int            prcmu_cg_bit;
-        unsigned int            prcmu_cg_mgt;
-
-        /* The rest are only for PRCC clks */
-
-        int                     cluster;
-        unsigned int            prcc_bus;
-        unsigned int            prcc_kernel;
-
-        struct clk              *parent_cluster;
-        struct clk              *parent_periph;
-#if defined(CONFIG_DEBUG_FS)
-        struct dentry           *dent;          /* For visible tree hierarchy */
-        struct dentry           *dent_bus;      /* For visible tree hierarchy */
-#endif
-};
-
-#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg)         \
-struct clk clk_##_name = {                                      \
-                .name           = #_name,                       \
-                .ops            = &clk_prcmu_ops,               \
-                .prcmu_cg_off   = _cg_off,                      \
-                .prcmu_cg_bit   = _cg_bit,                      \
-                .prcmu_cg_mgt   = PRCM_##_reg##_MGT             \
-        }
-
-#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate)     \
-struct clk clk_##_name = {                                              \
-                .name           = #_name,                               \
-                .ops            = &clk_prcmu_ops,                       \
-                .prcmu_cg_off   = _cg_off,                              \
-                .prcmu_cg_bit   = _cg_bit,                              \
-                .rate           = _rate,                                \
-                .prcmu_cg_mgt   = PRCM_##_reg##_MGT                     \
-        }
-
-#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk)  \
-struct clk clk_##_name = {                                              \
-                .name           = #_name,                               \
-                .ops            = &clk_prcc_ops,                        \
-                .cluster        = _pclust,                              \
-                .prcc_bus       = _bus_en,                              \
-                .prcc_kernel    = _kernel_en,                           \
-                .parent_cluster = &clk_per##_pclust##clk,               \
-                .parent_periph  = _kernclk                              \
-        }
-
-#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
-struct clk clk_##_name = {                                              \
-                .name           = #_name,                               \
-                .ops            = &clk_prcc_ops,                        \
-                .cluster        = _pclust,                              \
-                .prcc_bus       = _bus_en,                              \
-                .prcc_kernel    = _kernel_en,                           \
-                .parent_cluster = &clk_per##_pclust##clk,               \
-                .parent_periph  = _kernclk,                             \
-                .get_rate       = _callback,                            \
-                .data           = (void *) _data                        \
-        }
-
-
-#define CLK(_clk, _devname, _conname)                   \
-        {                                               \
-                .clk    = &clk_##_clk,                  \
-                .dev_id = _devname,                     \
-                .con_id = _conname,                     \
-        }
-
-int __init clk_db8500_ed_fixup(void);
-int __init clk_init(void);
-
-#ifdef CONFIG_DEBUG_FS
-int clk_debugfs_init(void);
-#else
-static inline int clk_debugfs_init(void) { return 0; }
-#endif
-
-#ifdef CONFIG_CPU_FREQ
-int clk_init_smp_twd_cpufreq(void);
-#else
-static inline int clk_init_smp_twd_cpufreq(void) { return 0; }
-#endif
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index db3c52d56ca4..aef2c68e9ec1 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -19,12 +19,11 @@
 #include <linux/mfd/abx500/ab8500.h>
 
 #include <asm/mach/map.h>
-#include <asm/pmu.h>
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-musb-ux500.h>
 #include <mach/db8500-regs.h>
 
 #include "devices-db8500.h"
@@ -80,7 +79,7 @@ void __init u8500_map_io(void)
 
         iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
 
-        if (cpu_is_u9540())
+        if (cpu_is_ux540_family())
                 iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
         else
                 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
@@ -122,7 +121,7 @@ struct arm_pmu_platdata db8500_pmu_platdata = {
 
 static struct platform_device db8500_pmu_device = {
         .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
         .num_resources          = ARRAY_SIZE(db8500_pmu_resources),
         .resource               = db8500_pmu_resources,
         .dev.platform_data      = &db8500_pmu_platdata,
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e2360e7c770d..3d62c64c84c4 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,7 +8,6 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/clk.h>
 #include <linux/mfd/db8500-prcmu.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/sys_soc.h>
@@ -17,6 +16,7 @@
 #include <linux/stat.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/platform_data/clk-ux500.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
@@ -25,8 +25,6 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
 
-#include "clock.h"
-
 void __iomem *_PRCMU_BASE;
 
 /*
@@ -51,7 +49,7 @@ void __init ux500_init_irq(void)
         void __iomem *dist_base;
         void __iomem *cpu_base;
 
-        if (cpu_is_u8500_family()) {
+        if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
                 dist_base = __io_address(U8500_GIC_DIST_BASE);
                 cpu_base = __io_address(U8500_GIC_CPU_BASE);
         } else
@@ -70,13 +68,17 @@ void __init ux500_init_irq(void)
          */
         if (cpu_is_u8500_family())
                 db8500_prcmu_early_init();
-        clk_init();
+
+        if (cpu_is_u8500_family())
+                u8500_clk_init();
+        else if (cpu_is_u9540())
+                u9540_clk_init();
+        else if (cpu_is_u8540())
+                u8540_clk_init();
 }
 
 void __init ux500_init_late(void)
 {
-        clk_debugfs_init();
-        clk_init_smp_twd_cpufreq();
 }
 
 static const char * __init ux500_get_machine(void)
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index ecdd8386cffb..7fbf0ba336e1 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -13,7 +13,7 @@
 #include <linux/sys_soc.h>
 #include <linux/amba/bus.h>
 #include <linux/platform_data/i2c-nomadik.h>
-#include <mach/crypto-ux500.h>
+#include <linux/platform_data/crypto-ux500.h>
 
 struct spi_master_cntlr;
 
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
index c76f0f456f04..2f6af259015d 100644
--- a/arch/arm/mach-ux500/hotplug.c
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -15,13 +15,18 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 
-extern volatile int pen_release;
+#include <mach/setup.h>
 
-static inline void platform_do_lowpower(unsigned int cpu)
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref ux500_cpu_die(unsigned int cpu)
 {
         flush_cache_all();
 
-        /* we put the platform to just WFI */
+        /* directly enter low power state, skipping secure registers */
         for (;;) {
                 __asm__ __volatile__("dsb\n\t" "wfi\n\t"
                                 : : : "memory");
@@ -33,28 +38,3 @@ static inline void platform_do_lowpower(unsigned int cpu)
                 }
         }
 }
-
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void platform_cpu_die(unsigned int cpu)
-{
-        /* directly enter low power state, skipping secure registers */
-        platform_do_lowpower(cpu);
-}
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
deleted file mode 100644
index c01ef66537f3..000000000000
--- a/arch/arm/mach-ux500/include/mach/gpio.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index c6e2db9e9e51..9c42642ab168 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -41,43 +41,29 @@ static inline bool __attribute_const__ cpu_is_u8500(void)
         return dbx500_partnumber() == 0x8500;
 }
 
-static inline bool __attribute_const__ cpu_is_u9540(void)
+static inline bool __attribute_const__ cpu_is_u8520(void)
 {
-        return dbx500_partnumber() == 0x9540;
+        return dbx500_partnumber() == 0x8520;
 }
 
 static inline bool cpu_is_u8500_family(void)
 {
-        return cpu_is_u8500() || cpu_is_u9540();
-}
-
-static inline bool __attribute_const__ cpu_is_u5500(void)
-{
-        return dbx500_partnumber() == 0x5500;
-}
-
-/*
- * 5500 revisions
- */
-
-static inline bool __attribute_const__ cpu_is_u5500v1(void)
-{
-        return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0;
+        return cpu_is_u8500() || cpu_is_u8520();
 }
 
-static inline bool __attribute_const__ cpu_is_u5500v2(void)
+static inline bool __attribute_const__ cpu_is_u9540(void)
 {
-        return (dbx500_id.revision & 0xf0) == 0xB0;
+        return dbx500_partnumber() == 0x9540;
 }
 
-static inline bool __attribute_const__ cpu_is_u5500v20(void)
+static inline bool __attribute_const__ cpu_is_u8540(void)
 {
-        return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0);
+        return dbx500_partnumber() == 0x8540;
 }
 
-static inline bool __attribute_const__ cpu_is_u5500v21(void)
+static inline bool cpu_is_ux540_family(void)
 {
-        return cpu_is_u5500() && (dbx500_revision() == 0xB1);
+        return cpu_is_u9540() || cpu_is_u8540();
 }
 
 /*
@@ -119,14 +105,14 @@ static inline bool cpu_is_u8500v21(void)
         return cpu_is_u8500() && (dbx500_revision() == 0xB1);
 }
 
+static inline bool cpu_is_u8500v22(void)
+{
+        return cpu_is_u8500() && (dbx500_revision() == 0xB2);
+}
+
 static inline bool cpu_is_u8500v20_or_later(void)
 {
-        /*
-         * U9540 has so much in common with U8500 that is is considered a
-         * U8500 variant.
-         */
-        return cpu_is_u9540() ||
-                (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
+        return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
 }
 
 static inline bool ux500_is_svp(void)
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 7914e5eaa9c7..6be4c4d2ab88 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -45,4 +45,7 @@ extern struct sys_timer ux500_timer;
         .type           = MT_MEMORY,            \
 }
 
+extern struct smp_operations ux500_smp_ops;
+extern void ux500_cpu_die(unsigned int cpu);
+
 #endif /*  __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index da1d5ad5bd45..3db7782f3afb 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -28,12 +28,6 @@
 extern void u8500_secondary_startup(void);
 
 /*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int pen_release = -1;
-
-/*
  * Write pen_release in a way that is guaranteed to be visible to all
  * observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
@@ -48,7 +42,7 @@ static void write_pen_release(int val)
 
 static void __iomem *scu_base_addr(void)
 {
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 return __io_address(U8500_SCU_BASE);
         else
                 ux500_unknown_soc();
@@ -58,7 +52,7 @@ static void __iomem *scu_base_addr(void)
 
 static DEFINE_SPINLOCK(boot_lock);
 
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit ux500_secondary_init(unsigned int cpu)
 {
         /*
          * if any interrupts are already enabled for the primary
@@ -80,7 +74,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         spin_unlock(&boot_lock);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned long timeout;
 
@@ -118,7 +112,7 @@ static void __init wakeup_secondary(void)
 {
         void __iomem *backupram;
 
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 backupram = __io_address(U8500_BACKUPRAM0_BASE);
         else
                 ux500_unknown_soc();
@@ -145,7 +139,7 @@ static void __init wakeup_secondary(void)
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
-void __init smp_init_cpus(void)
+static void __init ux500_smp_init_cpus(void)
 {
         void __iomem *scu_base = scu_base_addr();
         unsigned int i, ncores;
@@ -165,9 +159,19 @@ void __init smp_init_cpus(void)
         set_smp_cross_call(gic_raise_softirq);
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
 {
 
         scu_enable(scu_base_addr());
         wakeup_secondary();
 }
+
+struct smp_operations ux500_smp_ops __initdata = {
+        .smp_init_cpus          = ux500_smp_init_cpus,
+        .smp_prepare_cpus       = ux500_smp_prepare_cpus,
+        .smp_secondary_init     = ux500_secondary_init,
+        .smp_boot_secondary     = ux500_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = ux500_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 66e7f00884ab..6f39731951b0 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -54,7 +54,7 @@ static void __init ux500_timer_init(void)
         void __iomem *tmp_base;
         struct device_node *np;
 
-        if (cpu_is_u8500_family()) {
+        if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
                 mtu_timer_base = __io_address(U8500_MTU0_BASE);
                 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
         } else {
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index a74af389bc63..145482e74418 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -10,7 +10,7 @@
 
 #include <plat/ste_dma40.h>
 #include <mach/hardware.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-musb-ux500.h>
 
 #define MUSB_DMA40_RX_CH { \
                 .mode = STEDMA40_MODE_LOGICAL, \
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index cd8ea3588f93..ca7902c6ed18 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -169,11 +169,6 @@ static struct map_desc versatile_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
                 .type           = MT_DEVICE
-        }, {
-                .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0,
-                .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
-                .length         = IO_SPACE_LIMIT,
-                .type           = MT_DEVICE
         },
 #endif
 };
diff --git a/arch/arm/mach-versatile/include/mach/gpio.h b/arch/arm/mach-versatile/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-versatile/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
index 408e58da46c6..3e5d425e2a92 100644
--- a/arch/arm/mach-versatile/include/mach/hardware.h
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -29,7 +29,6 @@
  */
 #define VERSATILE_PCI_VIRT_BASE         (void __iomem *)0xe8000000ul
 #define VERSATILE_PCI_CFG_VIRT_BASE     (void __iomem *)0xe9000000ul
-#define VERSATILE_PCI_VIRT_MEM_BASE0    (void __iomem *)PCIO_BASE
 
 /* macro to get at MMIO space when running virtually */
 #define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index e95bf84cc837..2f84f4094f13 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -169,13 +169,6 @@ static struct pci_ops pci_versatile_ops = {
         .write  = versatile_write_config,
 };
 
-static struct resource io_port = {
-        .name   = "PCI",
-        .start  = 0,
-        .end    = IO_SPACE_LIMIT,
-        .flags  = IORESOURCE_IO,
-};
-
 static struct resource io_mem = {
         .name   = "PCI I/O space",
         .start  = VERSATILE_PCI_MEM_BASE0,
@@ -207,12 +200,6 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
                        "memory region (%d)\n", ret);
                 goto out;
         }
-        ret = request_resource(&ioport_resource, &io_port);
-        if (ret) {
-                printk(KERN_ERR "PCI: unable to allocate I/O "
-                       "port region (%d)\n", ret);
-                goto out;
-        }
         ret = request_resource(&iomem_resource, &non_mem);
         if (ret) {
                 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
@@ -227,11 +214,9 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
         }
 
         /*
-         * the IO resource for this bus
          * the mem resource for this bus
          * the prefetch mem resource for this bus
          */
-        pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset);
         pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
         pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
 
@@ -260,9 +245,11 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
                 goto out;
         }
 
+        ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0);
+        if (ret)
+                goto out;
+
         if (nr == 0) {
-                sys->mem_offset = 0;
-                sys->io_offset = 0;
                 ret = pci_versatile_setup_resources(sys);
                 if (ret < 0) {
                         printk("pci_versatile_setup: resources... oops?\n");
@@ -319,7 +306,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 
 void __init pci_versatile_preinit(void)
 {
-        pcibios_min_io = 0x44000000;
         pcibios_min_mem = 0x50000000;
 
         __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index fc3730f01650..c95296066203 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,38 +1,23 @@
-menu "Versatile Express platform type"
-        depends on ARCH_VEXPRESS
-
-config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
-        bool "Enable A5 and A9 only errata work-arounds"
-        default y
-        select ARM_ERRATA_720789
-        select ARM_ERRATA_751472
-        select PL310_ERRATA_753970 if CACHE_PL310
-        help
-          Provides common dependencies for Versatile Express platforms
-          based on Cortex-A5 and Cortex-A9 processors. In order to
-          build a working kernel, you must also enable relevant core
-          tile support or Flattened Device Tree based support options.
-
-config ARCH_VEXPRESS_CA9X4
-        bool "Versatile Express Cortex-A9x4 tile"
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
-
-config ARCH_VEXPRESS_DT
-        bool "Device Tree support for Versatile Express platforms"
+config ARCH_VEXPRESS
+        bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_AMBA
         select ARM_GIC
-        select ARM_PATCH_PHYS_VIRT
-        select AUTO_ZRELADDR
+        select ARM_TIMER_SP804
+        select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CLK
+        select HAVE_PATA_PLATFORM
         select HAVE_SMP
+        select ICST
         select MIGHT_HAVE_CACHE_L2X0
-        select USE_OF
+        select NO_IOPORT
+        select PLAT_VERSATILE
+        select PLAT_VERSATILE_CLCD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
-          New Versatile Express platforms require Flattened Device Tree to
-          be passed to the kernel.
-
           This option enables support for systems using Cortex processor based
           ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
           for example:
@@ -48,7 +33,22 @@ config ARCH_VEXPRESS_DT
           platforms. The traditional (ATAGs) boot method is not usable on
           these boards with this option.
 
-          If your bootloader supports Flattened Device Tree based booting,
-          say Y here.
+menu "Versatile Express platform type"
+        depends on ARCH_VEXPRESS
+
+config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+        bool "Enable A5 and A9 only errata work-arounds"
+        default y
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_751472
+        select PL310_ERRATA_753970 if CACHE_PL310
+        help
+          Provides common dependencies for Versatile Express platforms
+          based on Cortex-A5 and Cortex-A9 processors. In order to
+          build a working kernel, you must also enable relevant core
+          tile support or Flattened Device Tree based support options.
+
+config ARCH_VEXPRESS_CA9X4
+        bool "Versatile Express Cortex-A9x4 tile"
 
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 90551b9780ab..42703e8b4d3b 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -1,6 +1,8 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+        -I$(srctree)/arch/arm/plat-versatile/include
 
 obj-y                                   := v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
deleted file mode 100644
index 318d308dfb93..000000000000
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ /dev/null
@@ -1,10 +0,0 @@
-# Those numbers are used only by the non-DT V2P-CA9 platform
-# The DT-enabled ones require CONFIG_AUTO_ZRELADDR=y
-   zreladdr-y   += 0x60008000
-params_phys-y   := 0x60000100
-initrd_phys-y   := 0x60800000
-
-dtb-$(CONFIG_ARCH_VEXPRESS_DT)  += vexpress-v2p-ca5s.dtb \
-                                   vexpress-v2p-ca9.dtb \
-                                   vexpress-v2p-ca15-tc1.dtb \
-                                   vexpress-v2p-ca15_a7.dtb
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index a3a4980770bd..f134cd4a85f1 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -5,3 +5,7 @@
 #define V2T_PERIPH 0xf8200000
 
 void vexpress_dt_smp_map_io(void);
+
+extern struct smp_operations    vexpress_smp_ops;
+
+extern void vexpress_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 61c492403b05..4f471fa3e3c5 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -13,7 +13,6 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
-#include <asm/pmu.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 
@@ -27,6 +26,7 @@
 #include "core.h"
 
 #include <mach/motherboard.h>
+#include <mach/irqs.h>
 
 #include <plat/clcd.h>
 
@@ -144,7 +144,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
         .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
         .num_resources  = ARRAY_SIZE(pmu_resources),
         .resource       = pmu_resources,
 };
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index c504a72b94d6..a141b98d84fe 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -16,8 +16,6 @@
 #include <asm/smp_plat.h>
 #include <asm/cp15.h>
 
-extern volatile int pen_release;
-
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -84,17 +82,12 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
         }
 }
 
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
  * Called with IRQs disabled
  */
-void platform_cpu_die(unsigned int cpu)
+void __ref vexpress_cpu_die(unsigned int cpu)
 {
         int spurious = 0;
 
@@ -113,12 +106,3 @@ void platform_cpu_die(unsigned int cpu)
         if (spurious)
                 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
-
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-vexpress/include/mach/gpio.h b/arch/arm/mach-vexpress/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-vexpress/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h
index 4b10ee7657a6..f8f7f782eb55 100644
--- a/arch/arm/mach-vexpress/include/mach/irqs.h
+++ b/arch/arm/mach-vexpress/include/mach/irqs.h
@@ -1,4 +1,6 @@
 #define IRQ_LOCALTIMER          29
 #define IRQ_LOCALWDOG           30
 
+#ifndef CONFIG_SPARSE_IRQ
 #define NR_IRQS 256
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/timex.h b/arch/arm/mach-vexpress/include/mach/timex.h
deleted file mode 100644
index 00029bacd43c..000000000000
--- a/arch/arm/mach-vexpress/include/mach/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *  arch/arm/mach-vexpress/include/mach/timex.h
- *
- *  RealView architecture timex specifications
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
deleted file mode 100644
index 1e472eb0bbdc..000000000000
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- *  arch/arm/mach-vexpress/include/mach/uncompress.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
-#define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
-#define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
-#define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
-
-#define UART_BASE       0x10009000
-#define UART_BASE_RS1   0x1c090000
-
-static unsigned long get_uart_base(void)
-{
-#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
-        unsigned long mpcore_periph;
-
-        /*
-         * Make an educated guess regarding the memory map:
-         * - the original A9 core tile, which has MPCore peripherals
-         *   located at 0x1e000000, should use UART at 0x10009000
-         * - all other (RS1 complaint) tiles use UART mapped
-         *   at 0x1c090000
-         */
-        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (mpcore_periph));
-
-        if (mpcore_periph == 0x1e000000)
-                return UART_BASE;
-        else
-                return UART_BASE_RS1;
-#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
-        return UART_BASE;
-#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
-        return UART_BASE_RS1;
-#else
-        return 0;
-#endif
-}
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        unsigned long base = get_uart_base();
-
-        if (!base)
-                return;
-
-        while (AMBA_UART_FR(base) & (1 << 5))
-                barrier();
-
-        AMBA_UART_DR(base) = c;
-}
-
-static inline void flush(void)
-{
-        unsigned long base = get_uart_base();
-
-        if (!base)
-                return;
-
-        while (AMBA_UART_FR(base) & (1 << 3))
-                barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 14ba1128ae8d..7db27c8c05cc 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -20,9 +20,9 @@
 
 #include <mach/motherboard.h>
 
-#include "core.h"
+#include <plat/platsmp.h>
 
-extern void versatile_secondary_startup(void);
+#include "core.h"
 
 #if defined(CONFIG_OF)
 
@@ -167,7 +167,7 @@ void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
-void __init smp_init_cpus(void)
+static void __init vexpress_smp_init_cpus(void)
 {
         if (ct_desc)
                 ct_desc->init_cpu_map();
@@ -176,7 +176,7 @@ void __init smp_init_cpus(void)
 
 }
 
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
 {
         /*
          * Initialise the present map, which describes the set of CPUs
@@ -195,3 +195,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          */
         v2m_flags_set(virt_to_phys(versatile_secondary_startup));
 }
+
+struct smp_operations __initdata vexpress_smp_ops = {
+        .smp_init_cpus          = vexpress_smp_init_cpus,
+        .smp_prepare_cpus       = vexpress_smp_prepare_cpus,
+        .smp_secondary_init     = versatile_secondary_init,
+        .smp_boot_secondary     = versatile_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = vexpress_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 37608f22ee31..5f6b7d543e55 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -5,6 +5,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
+#include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
@@ -38,6 +39,7 @@
 #include <mach/motherboard.h>
 
 #include <plat/sched_clock.h>
+#include <plat/platsmp.h>
 
 #include "core.h"
 
@@ -530,6 +532,7 @@ static void __init v2m_init(void)
 
 MACHINE_START(VEXPRESS, "ARM-Versatile Express")
         .atag_offset    = 0x100,
+        .smp            = smp_ops(vexpress_smp_ops),
         .map_io         = v2m_map_io,
         .init_early     = v2m_init_early,
         .init_irq       = v2m_init_irq,
@@ -539,8 +542,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
         .restart        = v2m_restart,
 MACHINE_END
 
-#if defined(CONFIG_ARCH_VEXPRESS_DT)
-
 static struct map_desc v2m_rs1_io_desc __initdata = {
         .virtual        = V2M_PERIPH,
         .pfn            = __phys_to_pfn(0x1c000000),
@@ -663,6 +664,7 @@ const static char *v2m_dt_match[] __initconst = {
 
 DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
         .dt_compat      = v2m_dt_match,
+        .smp            = smp_ops(vexpress_smp_ops),
         .map_io         = v2m_dt_map_io,
         .init_early     = v2m_dt_init_early,
         .init_irq       = v2m_dt_init_irq,
@@ -671,5 +673,3 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
         .handle_irq     = gic_handle_irq,
         .restart        = v2m_restart,
 MACHINE_END
-
-#endif
diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c
index 1fcdc36b358d..82b4bcedffba 100644
--- a/arch/arm/mach-vt8500/devices.c
+++ b/arch/arm/mach-vt8500/devices.c
@@ -23,7 +23,7 @@
 
 #include <asm/mach/arch.h>
 
-#include <mach/vt8500fb.h>
+#include <linux/platform_data/video-vt8500lcdfb.h>
 #include <mach/i8042.h>
 #include "devices.h"
 
diff --git a/arch/arm/mach-vt8500/include/mach/gpio.h b/arch/arm/mach-vt8500/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-vt8500/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 48f5b9fdfb7f..7abdb9645c5b 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -34,11 +34,11 @@
 #include <asm/mach-types.h>
 
 #include <mach/regs-serial.h>
-#include <mach/nuc900_spi.h>
+#include <linux/platform_data/spi-nuc900.h>
 #include <mach/map.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-nuc900fb.h>
 #include <mach/regs-ldm.h>
-#include <mach/w90p910_keypad.h>
+#include <linux/platform_data/keypad-w90p910.h>
 
 #include "cpu.h"
 
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index 067d8f9166dc..500fe5932ce9 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -20,7 +20,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <mach/map.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-nuc900fb.h>
 
 #include "nuc950.h"
 
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 23a7643e9a87..1be0f4e5e6eb 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -15,8 +15,11 @@
  */
 
 #include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
+#include <asm/cputype.h>
 #include <asm/hardware/cache-tauros2.h>
 
 
@@ -144,25 +147,8 @@ static inline void __init write_extra_features(u32 u)
         __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
 }
 
-static void __init disable_l2_prefetch(void)
-{
-        u32 u;
-
-        /*
-         * Read the CPU Extra Features register and verify that the
-         * Disable L2 Prefetch bit is set.
-         */
-        u = read_extra_features();
-        if (!(u & 0x01000000)) {
-                printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
-                write_extra_features(u | 0x01000000);
-        }
-}
-
 static inline int __init cpuid_scheme(void)
 {
-        extern int processor_id;
-
         return !!((processor_id & 0x000f0000) == 0x000f0000);
 }
 
@@ -189,12 +175,36 @@ static inline void __init write_actlr(u32 actlr)
         __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
 }
 
-void __init tauros2_init(void)
+static void enable_extra_feature(unsigned int features)
+{
+        u32 u;
+
+        u = read_extra_features();
+
+        if (features & CACHE_TAUROS2_PREFETCH_ON)
+                u &= ~0x01000000;
+        else
+                u |= 0x01000000;
+        printk(KERN_INFO "Tauros2: %s L2 prefetch.\n",
+                        (features & CACHE_TAUROS2_PREFETCH_ON)
+                        ? "Enabling" : "Disabling");
+
+        if (features & CACHE_TAUROS2_LINEFILL_BURST8)
+                u |= 0x00100000;
+        else
+                u &= ~0x00100000;
+        printk(KERN_INFO "Tauros2: %s line fill burt8.\n",
+                        (features & CACHE_TAUROS2_LINEFILL_BURST8)
+                        ? "Enabling" : "Disabling");
+
+        write_extra_features(u);
+}
+
+static void __init tauros2_internal_init(unsigned int features)
 {
-        extern int processor_id;
-        char *mode;
+        char *mode = NULL;
 
-        disable_l2_prefetch();
+        enable_extra_feature(features);
 
 #ifdef CONFIG_CPU_32v5
         if ((processor_id & 0xff0f0000) == 0x56050000) {
@@ -286,3 +296,34 @@ void __init tauros2_init(void)
         printk(KERN_INFO "Tauros2: L2 cache support initialised "
                          "in %s mode.\n", mode);
 }
+
+#ifdef CONFIG_OF
+static const struct of_device_id tauros2_ids[] __initconst = {
+        { .compatible = "marvell,tauros2-cache"},
+        {}
+};
+#endif
+
+void __init tauros2_init(unsigned int features)
+{
+#ifdef CONFIG_OF
+        struct device_node *node;
+        int ret;
+        unsigned int f;
+
+        node = of_find_matching_node(NULL, tauros2_ids);
+        if (!node) {
+                pr_info("Not found marvell,tauros2-cache, disable it\n");
+                return;
+        }
+
+        ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f);
+        if (ret) {
+                pr_info("Not found marvell,tauros-cache-features property, "
+                        "disable extra features\n");
+                features = 0;
+        } else
+                features = f;
+#endif
+        tauros2_internal_init(features);
+}
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 566750fa57d4..9d869f93a3da 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -36,6 +36,7 @@
 #include <asm/system_info.h>
 
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include "mm.h"
 
 int ioremap_page(unsigned long virt, unsigned long phys,
@@ -383,3 +384,16 @@ void __arm_iounmap(volatile void __iomem *io_addr)
         arch_iounmap(io_addr);
 }
 EXPORT_SYMBOL(__arm_iounmap);
+
+#ifdef CONFIG_PCI
+int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
+{
+        BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT);
+
+        return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
+                                  PCI_IO_VIRT_BASE + offset + SZ_64K,
+                                  phys_addr,
+                                  __pgprot(get_mem_type(MT_DEVICE)->prot_pte));
+}
+EXPORT_SYMBOL_GPL(pci_ioremap_io);
+#endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index c2fa21d0103e..18144e6a3115 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -31,6 +31,7 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 
 #include "mm.h"
 
@@ -216,7 +217,7 @@ static struct mem_type mem_types[] = {
                 .prot_l1        = PMD_TYPE_TABLE,
                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
                 .domain         = DOMAIN_IO,
-        },      
+        },
         [MT_DEVICE_WC] = {      /* ioremap_wc */
                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
                 .prot_l1        = PMD_TYPE_TABLE,
@@ -777,14 +778,27 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
                 create_mapping(md);
                 vm->addr = (void *)(md->virtual & PAGE_MASK);
                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
-                vm->phys_addr = __pfn_to_phys(md->pfn); 
-                vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 
+                vm->phys_addr = __pfn_to_phys(md->pfn);
+                vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
                 vm->flags |= VM_ARM_MTYPE(md->type);
                 vm->caller = iotable_init;
                 vm_area_add_early(vm++);
         }
 }
 
+void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
+                                  void *caller)
+{
+        struct vm_struct *vm;
+
+        vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
+        vm->addr = (void *)addr;
+        vm->size = size;
+        vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
+        vm->caller = caller;
+        vm_area_add_early(vm);
+}
+
 #ifndef CONFIG_ARM_LPAE
 
 /*
@@ -802,14 +816,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
 
 static void __init pmd_empty_section_gap(unsigned long addr)
 {
-        struct vm_struct *vm;
-
-        vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
-        vm->addr = (void *)addr;
-        vm->size = SECTION_SIZE;
-        vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
-        vm->caller = pmd_empty_section_gap;
-        vm_area_add_early(vm);
+        vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
 }
 
 static void __init fill_pmd_gaps(void)
@@ -858,6 +865,28 @@ static void __init fill_pmd_gaps(void)
 #define fill_pmd_gaps() do { } while (0)
 #endif
 
+#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
+static void __init pci_reserve_io(void)
+{
+        struct vm_struct *vm;
+        unsigned long addr;
+
+        /* we're still single threaded hence no lock needed here */
+        for (vm = vmlist; vm; vm = vm->next) {
+                if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+                        continue;
+                addr = (unsigned long)vm->addr;
+                addr &= ~(SZ_2M - 1);
+                if (addr == PCI_IO_VIRT_BASE)
+                        return;
+
+        }
+        vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
+}
+#else
+#define pci_reserve_io() do { } while (0)
+#endif
+
 static void * __initdata vmalloc_min =
         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 
@@ -1141,6 +1170,9 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
                 mdesc->map_io();
         fill_pmd_gaps();
 
+        /* Reserve fixed i/o space in VMALLOC region */
+        pci_reserve_io();
+
         /*
          * Finally flush the caches and tlb to ensure that we're in a
          * consistent state wrt the writebuffer.  This also ensures that
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 8daae9b230ea..362474b5c40d 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -192,30 +192,24 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
         if (nr != 0)
                 return 0;
 
-        res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
+        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
         if (!res)
                 panic("PCI: unable to alloc resources");
 
-        res[0].start = IOP3XX_PCI_LOWER_IO_PA;
-        res[0].end   = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
-        res[0].name  = "IOP3XX PCI I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        request_resource(&ioport_resource, &res[0]);
-
-        res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
-        res[1].end   = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
-        res[1].name  = "IOP3XX PCI Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        request_resource(&iomem_resource, &res[1]);
+        res->start = IOP3XX_PCI_LOWER_MEM_PA;
+        res->end   = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
+        res->name  = "IOP3XX PCI Memory Space";
+        res->flags = IORESOURCE_MEM;
+        request_resource(&iomem_resource, res);
 
         /*
          * Use whatever translation is already setup.
          */
         sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
-        sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
 
-        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
+
+        pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
 
         return 1;
 }
@@ -367,7 +361,6 @@ void __init iop3xx_pci_preinit_cond(void)
 
 void __init iop3xx_pci_preinit(void)
 {
-        pcibios_min_io = 0;
         pcibios_min_mem = 0;
 
         iop3xx_atu_disable();
diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/plat-iop/pmu.c
index a2024b8685a1..ad9f9744a82d 100644
--- a/arch/arm/plat-iop/pmu.c
+++ b/arch/arm/plat-iop/pmu.c
@@ -9,7 +9,6 @@
  */
 
 #include <linux/platform_device.h>
-#include <asm/pmu.h>
 #include <mach/irqs.h>
 
 static struct resource pmu_resource = {
@@ -26,7 +25,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
         .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
         .resource       = &pmu_resource,
         .num_resources  = 1,
 };
diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c
index bade586fed0f..5b217f460f18 100644
--- a/arch/arm/plat-iop/setup.c
+++ b/arch/arm/plat-iop/setup.c
@@ -25,11 +25,6 @@ static struct map_desc iop3xx_std_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
                 .length         = IOP3XX_PERIPHERAL_SIZE,
                 .type           = MT_UNCACHED,
-         }, {   /* PCI IO space */
-                .virtual        = IOP3XX_PCI_LOWER_IO_VA,
-                .pfn            = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA),
-                .length         = IOP3XX_PCI_IO_WINDOW_SIZE,
-                .type           = MT_DEVICE,
          },
 };
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 6ac720031150..149237e24850 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
+obj-y := time.o devices.o cpu.o system.o irq-common.o
 
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
deleted file mode 100644
index 5079787273d2..000000000000
--- a/arch/arm/plat-mxc/clock.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Based on arch/arm/plat-omap/clock.c
- *
- * Copyright (C) 2004 - 2005 Nokia corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-/* #define DEBUG */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/proc_fs.h>
-#include <linux/semaphore.h>
-#include <linux/string.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-
-#ifndef CONFIG_COMMON_CLK
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-/*-------------------------------------------------------------------------
- * Standard clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
-
-static void __clk_disable(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-        WARN_ON(!clk->usecount);
-
-        if (!(--clk->usecount)) {
-                if (clk->disable)
-                        clk->disable(clk);
-                __clk_disable(clk->parent);
-                __clk_disable(clk->secondary);
-        }
-}
-
-static int __clk_enable(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-
-        if (clk->usecount++ == 0) {
-                __clk_enable(clk->parent);
-                __clk_enable(clk->secondary);
-
-                if (clk->enable)
-                        clk->enable(clk);
-        }
-        return 0;
-}
-
-/* This function increments the reference count on the clock and enables the
- * clock if not already enabled. The parent clock tree is recursively enabled
- */
-int clk_enable(struct clk *clk)
-{
-        int ret = 0;
-
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-
-        mutex_lock(&clocks_mutex);
-        ret = __clk_enable(clk);
-        mutex_unlock(&clocks_mutex);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-/* This function decrements the reference count on the clock and disables
- * the clock when reference count is 0. The parent clock tree is
- * recursively disabled
- */
-void clk_disable(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-
-        mutex_lock(&clocks_mutex);
-        __clk_disable(clk);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/* Retrieve the *current* clock rate. If the clock itself
- * does not provide a special calculation routine, ask
- * its parent and so on, until one is able to return
- * a valid clock rate
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return 0UL;
-
-        if (clk->get_rate)
-                return clk->get_rate(clk);
-
-        return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/* Round the requested clock rate to the nearest supported
- * rate that is less than or equal to the requested rate.
- * This is dependent on the clock's current parent.
- */
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
-                return 0;
-
-        return clk->round_rate(clk, rate);
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-/* Set the clock to the requested clock rate. The rate must
- * match a supported rate exactly based on what clk_round_rate returns
- */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        int ret = -EINVAL;
-
-        if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
-                return ret;
-
-        mutex_lock(&clocks_mutex);
-        ret = clk->set_rate(clk, rate);
-        mutex_unlock(&clocks_mutex);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-/* Set the clock's parent to another clock source */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int ret = -EINVAL;
-        struct clk *old;
-
-        if (clk == NULL || IS_ERR(clk) || parent == NULL ||
-            IS_ERR(parent) || clk->set_parent == NULL)
-                return ret;
-
-        if (clk->usecount)
-                clk_enable(parent);
-
-        mutex_lock(&clocks_mutex);
-        ret = clk->set_parent(clk, parent);
-        if (ret == 0) {
-                old = clk->parent;
-                clk->parent = parent;
-        } else {
-                old = parent;
-        }
-        mutex_unlock(&clocks_mutex);
-
-        if (clk->usecount)
-                clk_disable(old);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/* Retrieve the clock's parent clock source */
-struct clk *clk_get_parent(struct clk *clk)
-{
-        struct clk *ret = NULL;
-
-        if (clk == NULL || IS_ERR(clk))
-                return ret;
-
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-#else
-
-/*
- * Lock to protect the clock module (ccm) registers. Used
- * on all i.MXs
- */
-DEFINE_SPINLOCK(imx_ccm_lock);
-
-#endif /* CONFIG_COMMON_CLK */
-
-/*
- * Get the resulting clock rate from a PLL register value and the input
- * frequency. PLLs with this register layout can at least be found on
- * MX1, MX21, MX27 and MX31
- *
- *                  mfi + mfn / (mfd + 1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
-{
-        long long ll;
-        int mfn_abs;
-        unsigned int mfi, mfn, mfd, pd;
-
-        mfi = (reg_val >> 10) & 0xf;
-        mfn = reg_val & 0x3ff;
-        mfd = (reg_val >> 16) & 0x3ff;
-        pd =  (reg_val >> 26) & 0xf;
-
-        mfi = mfi <= 5 ? 5 : mfi;
-
-        mfn_abs = mfn;
-
-        /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
-         * 2's complements number
-         */
-        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-                mfn_abs = 0x400 - mfn;
-
-        freq *= 2;
-        freq /= pd + 1;
-
-        ll = (unsigned long long)freq * mfn_abs;
-
-        do_div(ll, mfd + 1);
-
-        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-                ll = -ll;
-
-        ll = (freq * mfi) + ll;
-
-        return ll;
-}
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 73db34bf588a..b5b6f8083130 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -23,7 +23,6 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <mach/hardware.h>
-#include <mach/clock.h>
 
 #define CLK32_FREQ      32768
 #define NANOSECOND      (1000 * 1000 * 1000)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index 2020d84956c3..d390f00bd294 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -87,7 +87,7 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX35
 const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
 #define imx35_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
+        imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K)
         imx35_imx_uart_data_entry(0, 1),
         imx35_imx_uart_data_entry(1, 2),
         imx35_imx_uart_data_entry(2, 3),
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
index 5955f5da82ee..3793e475cd95 100644
--- a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
@@ -8,7 +8,7 @@
 
 #include <mach/hardware.h>
 #include <mach/devices-common.h>
-#include <mach/esdhc.h>
+#include <linux/platform_data/mmc-esdhc-imx.h>
 
 #define imx_sdhci_esdhc_imx_data_entry_single(soc, _devid, _id, hwid) \
         {                                                               \
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
deleted file mode 100644
index bd940c795cbb..000000000000
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_CLOCK_H__
-#define __ASM_ARCH_MXC_CLOCK_H__
-
-#ifndef __ASSEMBLY__
-#include <linux/list.h>
-
-#ifndef CONFIG_COMMON_CLK
-struct module;
-
-struct clk {
-        int id;
-        /* Source clock this clk depends on */
-        struct clk *parent;
-        /* Secondary clock to enable/disable with this clock */
-        struct clk *secondary;
-        /* Reference count of clock enable/disable */
-        __s8 usecount;
-        /* Register bit position for clock's enable/disable control. */
-        u8 enable_shift;
-        /* Register address for clock's enable/disable control. */
-        void __iomem *enable_reg;
-        u32 flags;
-        /* get the current clock rate (always a fresh value) */
-        unsigned long (*get_rate) (struct clk *);
-        /* Function ptr to set the clock to a new rate. The rate must match a
-           supported rate returned from round_rate. Leave blank if clock is not
-           programmable */
-        int (*set_rate) (struct clk *, unsigned long);
-        /* Function ptr to round the requested clock rate to the nearest
-           supported rate that is less than or equal to the requested rate. */
-        unsigned long (*round_rate) (struct clk *, unsigned long);
-        /* Function ptr to enable the clock. Leave blank if clock can not
-           be gated. */
-        int (*enable) (struct clk *);
-        /* Function ptr to disable the clock. Leave blank if clock can not
-           be gated. */
-        void (*disable) (struct clk *);
-        /* Function ptr to set the parent clock of the clock. */
-        int (*set_parent) (struct clk *, struct clk *);
-};
-
-int clk_register(struct clk *clk);
-void clk_unregister(struct clk *clk);
-#endif /* CONFIG_COMMON_CLK */
-
-extern spinlock_t imx_ccm_lock;
-
-unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7128e9710417..ead901814c0d 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -52,7 +52,6 @@ extern void imx31_soc_init(void);
 extern void imx35_soc_init(void);
 extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
-extern void imx53_soc_init(void);
 extern void imx51_init_late(void);
 extern void imx53_init_late(void);
 extern void epit_timer_init(void __iomem *base, int irq);
@@ -137,14 +136,11 @@ extern void imx_src_prepare_restart(void);
 extern void imx_gpc_init(void);
 extern void imx_gpc_pre_suspend(void);
 extern void imx_gpc_post_resume(void);
-extern void imx51_babbage_common_init(void);
-extern void imx53_ard_common_init(void);
-extern void imx53_evk_common_init(void);
-extern void imx53_qsb_common_init(void);
-extern void imx53_smd_common_init(void);
 extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
 extern void imx6q_clock_map_io(void);
 
+extern void imx_cpu_die(unsigned int cpu);
+
 #ifdef CONFIG_PM
 extern void imx6q_pm_init(void);
 extern void imx51_pm_init(void);
@@ -161,4 +157,6 @@ extern int mx51_neon_fixup(void);
 static inline int mx51_neon_fixup(void) { return 0; }
 #endif
 
+extern struct smp_operations imx_smp_ops;
+
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index a7f5bb1084d7..9e3e3d8ae8c2 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -9,7 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/init.h>
-#include <mach/sdma.h>
+#include <linux/platform_data/dma-imx-sdma.h>
 
 extern struct device mxc_aips_bus;
 extern struct device mxc_ahb_bus;
@@ -74,7 +74,7 @@ struct platform_device *__init imx_add_fsl_usb2_udc(
 struct platform_device *__init imx_add_gpio_keys(
                 const struct gpio_keys_platform_data *pdata);
 
-#include <mach/mx21-usbhost.h>
+#include <linux/platform_data/usb-mx2.h>
 struct imx_imx21_hcd_data {
         resource_size_t iobase;
         resource_size_t irq;
@@ -98,7 +98,7 @@ struct imx_imxdi_rtc_data {
 struct platform_device *__init imx_add_imxdi_rtc(
                 const struct imx_imxdi_rtc_data *data);
 
-#include <mach/imxfb.h>
+#include <linux/platform_data/video-imxfb.h>
 struct imx_imx_fb_data {
         resource_size_t iobase;
         resource_size_t iosize;
@@ -108,7 +108,7 @@ struct platform_device *__init imx_add_imx_fb(
                 const struct imx_imx_fb_data *data,
                 const struct imx_fb_platform_data *pdata);
 
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-imx.h>
 struct imx_imx_i2c_data {
         int id;
         resource_size_t iobase;
@@ -129,7 +129,7 @@ struct platform_device *__init imx_add_imx_keypad(
                 const struct imx_imx_keypad_data *data,
                 const struct matrix_keymap_data *pdata);
 
-#include <mach/ssi.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 struct imx_imx_ssi_data {
         int id;
         resource_size_t iobase;
@@ -144,7 +144,7 @@ struct platform_device *__init imx_add_imx_ssi(
                 const struct imx_imx_ssi_data *data,
                 const struct imx_ssi_platform_data *pdata);
 
-#include <mach/imx-uart.h>
+#include <linux/platform_data/serial-imx.h>
 struct imx_imx_uart_3irq_data {
         int id;
         resource_size_t iobase;
@@ -167,7 +167,7 @@ struct platform_device *__init imx_add_imx_uart_1irq(
                 const struct imx_imx_uart_1irq_data *data,
                 const struct imxuart_platform_data *pdata);
 
-#include <mach/usb.h>
+#include <linux/platform_data/usb-imx_udc.h>
 struct imx_imx_udc_data {
         resource_size_t iobase;
         resource_size_t iosize;
@@ -183,8 +183,8 @@ struct platform_device *__init imx_add_imx_udc(
                 const struct imx_imx_udc_data *data,
                 const struct imxusb_platform_data *pdata);
 
-#include <mach/mx3fb.h>
-#include <mach/mx3_camera.h>
+#include <linux/platform_data/video-mx3fb.h>
+#include <linux/platform_data/camera-mx3.h>
 struct imx_ipu_core_data {
         resource_size_t iobase;
         resource_size_t synirq;
@@ -199,7 +199,7 @@ struct platform_device *__init imx_add_mx3_sdc_fb(
                 const struct imx_ipu_core_data *data,
                 struct mx3fb_platform_data *pdata);
 
-#include <mach/mx1_camera.h>
+#include <linux/platform_data/camera-mx1.h>
 struct imx_mx1_camera_data {
         resource_size_t iobase;
         resource_size_t iosize;
@@ -209,7 +209,7 @@ struct platform_device *__init imx_add_mx1_camera(
                 const struct imx_mx1_camera_data *data,
                 const struct mx1_camera_pdata *pdata);
 
-#include <mach/mx2_cam.h>
+#include <linux/platform_data/camera-mx2.h>
 struct imx_mx2_camera_data {
         resource_size_t iobasecsi;
         resource_size_t iosizecsi;
@@ -224,7 +224,7 @@ struct platform_device *__init imx_add_mx2_camera(
 struct platform_device *__init imx_add_mx2_emmaprp(
                 const struct imx_mx2_camera_data *data);
 
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 struct imx_mxc_ehci_data {
         int id;
         resource_size_t iobase;
@@ -234,7 +234,7 @@ struct platform_device *__init imx_add_mxc_ehci(
                 const struct imx_mxc_ehci_data *data,
                 const struct mxc_usbh_platform_data *pdata);
 
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-mxcmmc.h>
 struct imx_mxc_mmc_data {
         int id;
         resource_size_t iobase;
@@ -246,7 +246,7 @@ struct platform_device *__init imx_add_mxc_mmc(
                 const struct imx_mxc_mmc_data *data,
                 const struct imxmmc_platform_data *pdata);
 
-#include <mach/mxc_nand.h>
+#include <linux/platform_data/mtd-mxc_nand.h>
 struct imx_mxc_nand_data {
         /*
          * id is traditionally 0, but -1 is more appropriate.  We use -1 for new
@@ -295,7 +295,7 @@ struct imx_mxc_w1_data {
 struct platform_device *__init imx_add_mxc_w1(
                 const struct imx_mxc_w1_data *data);
 
-#include <mach/esdhc.h>
+#include <linux/platform_data/mmc-esdhc-imx.h>
 struct imx_sdhci_esdhc_imx_data {
         const char *devid;
         int id;
@@ -306,7 +306,7 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx(
                 const struct imx_sdhci_esdhc_imx_data *data,
                 const struct esdhc_platform_data *pdata);
 
-#include <mach/spi.h>
+#include <linux/platform_data/spi-imx.h>
 struct imx_spi_imx_data {
         const char *devid;
         int id;
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index d8b65b51f2a9..f79f78a1c0ed 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -512,12 +512,16 @@ enum iomux_pins {
 #define MX31_PIN_CSPI3_SPI_RDY__CTS3    IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CTS1__CTS1             IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RTS1__SFS              IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_TXD1__SCK              IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RXD1__STXDA            IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_DCD_DCE1__DCD_DCE1     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RI_DCE1__RI_DCE1       IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_DSR_DCE1__DSR_DCE1     IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_DTR_DCE1__DTR_DCE1     IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DTR_DCE1__SRXDA        IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_CTS2__CTS2             IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RTS2__RTS2             IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_TXD2__TXD2             IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
@@ -721,6 +725,7 @@ enum iomux_pins {
 #define MX31_PIN_KEY_ROW2_KEY_ROW2      IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW3_KEY_ROW3      IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW4_KEY_ROW4      IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW4_GPIO          IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_KEY_ROW5_KEY_ROW5      IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW6_KEY_ROW6      IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW7_KEY_ROW7      IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
deleted file mode 100644
index 9761e003bde2..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ /dev/null
@@ -1,1219 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc..
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_IOMUX_MX53_H__
-#define __MACH_IOMUX_MX53_H__
-
-#include <mach/iomux-v3.h>
-
-/* These 2 defines are for pins that may not have a mux register, but could
- * have a pad setting register, and vice-versa. */
-#define __NA_   0x00
-
-#define MX53_UART_PAD_CTRL              (PAD_CTL_PKE | PAD_CTL_PUE |    \
-                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define MX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_SRE_FAST)
-
-
-#define MX53_PAD_GPIO_19__KPP_COL_5                     IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__GPIO4_5                       IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__CCM_CLKO                      IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SPDIF_OUT1                    IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2          IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__ECSPI1_RDY                    IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__FEC_TDATA_3                   IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SRC_INT_BOOT                  IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__KPP_COL_0                    IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__GPIO4_6                      IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC              IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__ECSPI1_SCLK                  IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__FEC_RDATA_3                  IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST               IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__KPP_ROW_0                    IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__GPIO4_7                      IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI                  IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__FEC_TX_ER                    IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__KPP_COL_1                    IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__GPIO4_8                      IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__ECSPI1_MISO                  IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__FEC_RX_CLK                   IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY              IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__KPP_ROW_1                    IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__GPIO4_9                      IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__ECSPI1_SS0                   IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__FEC_COL                      IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID              IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__KPP_COL_2                    IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__GPIO4_10                     IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__CAN1_TXCAN                   IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_MDIO                     IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__ECSPI1_SS1                   IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_RDATA_2                  IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE             IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__KPP_ROW_2                    IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__GPIO4_11                     IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__CAN1_RXCAN                   IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_MDC                      IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__ECSPI1_SS2                   IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_TDATA_2                  IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR              IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__KPP_COL_3                    IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__GPIO4_12                     IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBOH3_H2_DP                 IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__SPDIF_IN1                    IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__I2C2_SCL                     IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__ECSPI1_SS3                   IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__FEC_CRS                      IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK             IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__KPP_ROW_3                    IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__GPIO4_13                     IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM                 IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK             IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__I2C2_SDA                     IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT               IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP                 IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0          IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__KPP_COL_4                    IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__GPIO4_14                     IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__CAN2_TXCAN                   IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__IPU_SISG_4                   IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__UART5_RTS                    IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC             IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1          IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__KPP_ROW_4                    IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__GPIO4_15                     IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__CAN2_RXCAN                   IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__IPU_SISG_5                   IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__UART5_CTS                    IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID            IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__GPIO4_16                 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR         IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0  IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0          IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID           IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__GPIO4_17                    IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1     IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1             IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID              IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__GPIO4_18                     IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2      IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2              IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION           IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__GPIO4_19                     IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3      IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3              IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__GPIO4_20                     IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__ESDHC1_WP                    IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4              IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT       IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__GPIO4_21                   IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__CSPI_SCLK                  IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0        IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN        IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5            IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY            IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__GPIO4_22                   IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__CSPI_MOSI                  IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1        IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL       \
-                                                        IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6            IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID            IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__GPIO4_23                   IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__CSPI_MISO                  IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2        IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7            IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE           IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__GPIO4_24                   IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__CSPI_SS0                   IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3        IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR       IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8            IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR            IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__GPIO4_25                   IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__CSPI_SS1                   IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4        IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9            IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK           IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__GPIO4_26                   IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__CSPI_SS2                   IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5        IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS   IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10           IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0        IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__GPIO4_27                   IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__CSPI_SS3                   IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6        IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE  IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11           IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1        IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__GPIO4_28                   IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__CSPI_RDY                   IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7        IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12           IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID          IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__GPIO4_29                   IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__PWM1_PWMO                  IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B               IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13           IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID             IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__GPIO4_30                   IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__PWM2_PWMO                  IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B               IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14           IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0          IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__GPIO4_31                  IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP          IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3        \
-                                                        IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15          IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1         IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__GPIO5_5                   IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT          IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4        \
-                                                        IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16          IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2         IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__GPIO5_6                   IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK          IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5        \
-                                                        IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17          IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3         IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__GPIO5_7                   IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0        \
-                                                        IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18          IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4         IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__GPIO5_8                   IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1        \
-                                                        IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19          IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5         IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__GPIO5_9                   IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2        \
-                                                        IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20          IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6         IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__GPIO5_10                  IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI               IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3        \
-                                                        IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21          IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7         IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__GPIO5_11                  IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO               IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4        \
-                                                        IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22          IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__GPIO5_12                  IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5        \
-                                                        IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23          IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2             IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__GPIO5_13                  IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK               IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6        \
-                                                        IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24          IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3             IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__GPIO5_14                  IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK               IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7        \
-                                                        IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25          IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI              IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__GPIO5_15                  IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI               IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0   IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26          IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO              IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__GPIO5_16                  IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO               IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1   IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27          IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK              IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__GPIO5_17                  IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2   IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28          IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS              IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK           IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__GPIO5_18                  IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29          IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC              IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__GPIO5_19                    IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK               IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30            IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL                  IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN         IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__GPIO5_20                 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31         IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK               IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC             IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__GPIO5_21                   IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32           IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0               IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__GPIO5_22                    IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__KPP_COL_5                   IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                 IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP            IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33            IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__GPIO5_23                    IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__KPP_ROW_5                   IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                 IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT            IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34            IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__GPIO5_24                    IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__KPP_COL_6                   IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO                 IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK            IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35            IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__GPIO5_25                    IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__KPP_ROW_6                   IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0                  IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR            IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36            IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__GPIO5_26                    IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__KPP_COL_7                   IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                 IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC             IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__I2C1_SDA                    IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37            IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__GPIO5_27                    IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__KPP_ROW_7                   IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                 IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR            IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__I2C1_SCL                    IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38            IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10              IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__GPIO5_28                   IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX              IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39           IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7               IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11              IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__GPIO5_29                   IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX              IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0                 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40           IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8               IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12              IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__GPIO5_30                   IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX              IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0        IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41           IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9               IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13              IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__GPIO5_31                   IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX              IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1        IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42           IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10              IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14              IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__GPIO6_0                    IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX              IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2        IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43           IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11              IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15              IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__GPIO6_1                    IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX              IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3        IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44           IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12              IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16              IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__GPIO6_2                    IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__UART4_RTS                  IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4        IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45           IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13              IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17              IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__GPIO6_3                    IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__UART4_CTS                  IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5        IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46           IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14              IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18              IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__GPIO6_4                    IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__UART5_RTS                  IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6        IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47           IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15              IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19              IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__GPIO6_5                    IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__UART5_CTS                  IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7        IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48           IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK             IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__EMI_WEIM_A_25                 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__GPIO5_2                       IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__ECSPI2_RDY                    IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI1_PIN12                 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__CSPI_SS1                      IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS                 IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__GPIO2_30                      IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK               IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS              IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__ECSPI1_SS0                    IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__I2C2_SCL                      IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__EMI_WEIM_D_16                 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__GPIO3_16                      IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DI0_PIN5                  IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK            IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__ECSPI1_SCLK                   IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__I2C2_SDA                      IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__EMI_WEIM_D_17                 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__GPIO3_17                      IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DI0_PIN6                  IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN            IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__ECSPI1_MISO                   IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__I2C3_SCL                      IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__EMI_WEIM_D_18                 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__GPIO3_18                      IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI0_PIN7                  IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO            IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__ECSPI1_MOSI                   IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__I2C3_SDA                      IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS                 IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EMI_WEIM_D_19                 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__GPIO3_19                      IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DI0_PIN8                  IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS             IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__ECSPI1_SS1                    IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EPIT1_EPITO                   IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__UART1_CTS                     IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC               IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EMI_WEIM_D_20                 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__GPIO3_20                      IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_DI0_PIN16                 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS              IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__CSPI_SS0                      IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EPIT2_EPITO                   IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__UART1_RTS                     IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR              IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__EMI_WEIM_D_21                 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__GPIO3_21                      IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DI0_PIN17                 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK            IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__CSPI_SCLK                     IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__I2C1_SCL                      IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC              IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__EMI_WEIM_D_22                 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__GPIO3_22                      IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DI0_PIN1                  IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN            IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__CSPI_MISO                     IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR             IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__EMI_WEIM_D_23                 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__GPIO3_23                      IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART3_CTS                     IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART1_DCD                     IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS                 IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN2                  IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN              IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN14                 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__GPIO2_31                      IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART3_RTS                     IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART1_RI                      IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3                  IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16                 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__EMI_WEIM_D_24                 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__GPIO3_24                      IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART3_TXD_MUX                 IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI1_SS2                    IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__CSPI_SS2                      IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS              IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI2_SS2                    IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART1_DTR                     IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__EMI_WEIM_D_25                 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__GPIO3_25                      IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART3_RXD_MUX                 IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI1_SS3                    IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__CSPI_SS3                      IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC               IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI2_SS3                    IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART1_DSR                     IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__EMI_WEIM_D_26                 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__GPIO3_26                      IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__UART2_TXD_MUX                 IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D26__FIRI_RXD                      IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_CSI0_D_1                  IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DI1_PIN11                 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_SISG_2                    IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22              IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__EMI_WEIM_D_27                 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__GPIO3_27                      IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__UART2_RXD_MUX                 IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D27__FIRI_TXD                      IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_CSI0_D_0                  IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DI1_PIN13                 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_SISG_3                    IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23              IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__EMI_WEIM_D_28                 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__GPIO3_28                      IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__UART2_CTS                     IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__CSPI_MOSI                     IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__I2C1_SDA                      IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_EXT_TRIG                  IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DI0_PIN13                 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__EMI_WEIM_D_29                 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__GPIO3_29                      IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__UART2_RTS                     IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS             IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__CSPI_SS0                      IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI1_PIN15                 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI0_PIN14                 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__EMI_WEIM_D_30                 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__GPIO3_30                      IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__UART3_CTS                     IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_CSI0_D_3                  IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DI0_PIN11                 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21              IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC               IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC               IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__EMI_WEIM_D_31                 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__GPIO3_31                      IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__UART3_RTS                     IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_CSI0_D_2                  IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DI0_PIN12                 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20              IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR              IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR              IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__EMI_WEIM_A_24                 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__GPIO5_4                       IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19              IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_CSI1_D_19                 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_SISG_2                    IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__USBPHY2_BVALID                IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__EMI_WEIM_A_23                 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__GPIO6_6                       IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18              IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_CSI1_D_18                 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_SISG_3                    IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION            IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__EMI_WEIM_A_22                 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__GPIO2_16                      IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17              IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_CSI1_D_17                 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7                 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__EMI_WEIM_A_21                 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__GPIO2_17                      IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16              IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_CSI1_D_16                 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6                 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__EMI_WEIM_A_20                 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__GPIO2_18                      IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15              IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_CSI1_D_15                 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5                 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__EMI_WEIM_A_19                 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__GPIO2_19                      IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14              IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_CSI1_D_14                 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4                 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__EMI_WEIM_A_18                 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__GPIO2_20                      IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13              IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_CSI1_D_13                 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3                 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__EMI_WEIM_A_17                 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__GPIO2_21                      IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12              IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_CSI1_D_12                 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2                 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__EMI_WEIM_A_16                 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__GPIO2_22                      IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK              IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK               IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1                 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__GPIO2_23                      IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__ECSPI2_SCLK                   IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5                  IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__GPIO2_24                      IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__ECSPI2_MOSI                   IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6                  IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__EMI_WEIM_OE                    IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__GPIO2_25                       IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__ECSPI2_MISO                    IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__IPU_DI1_PIN7                   IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__USBPHY2_IDDIG                  IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__EMI_WEIM_RW                    IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__GPIO2_26                       IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__ECSPI2_SS0                     IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__IPU_DI1_PIN8                   IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT         IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA                  IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__GPIO2_27                      IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__ECSPI2_SS1                    IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17                 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPIO2_28                      IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11              IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11                 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY                  IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__GPIO2_29                      IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10              IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10                 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0            IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__GPIO3_0                       IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9               IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9                  IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1            IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__GPIO3_1                       IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8               IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8                  IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2            IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__GPIO3_2                       IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7               IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7                  IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3            IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__GPIO3_3                       IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6               IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6                  IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4            IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__GPIO3_4                       IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5               IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5                  IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5            IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__GPIO3_5                       IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4               IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4                  IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6            IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__GPIO3_6                       IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3               IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3                  IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7            IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__GPIO3_7                       IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2               IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2                  IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8            IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__GPIO3_8                       IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1               IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1                  IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9            IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__GPIO3_9                       IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0               IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0                  IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10          IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__GPIO3_10                     IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN             IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11          IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__GPIO3_11                     IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2                 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC               IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12          IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__GPIO3_12                     IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3                 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC               IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13          IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__GPIO3_13                     IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK              IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14          IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__GPIO3_14                     IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK              IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15          IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__GPIO3_15                     IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1                 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4                 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B             IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__GPIO6_12                   IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B             IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__GPIO6_13                   IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__GPIO5_0                      IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B             IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__GPIO6_22                  IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__GPIO6_24                  IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__GPIO6_26                  IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__GPIO6_28                  IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__GPIO6_30                  IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__GPIO7_22                  IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__GPIO7_24                  IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__GPIO7_26                  IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__GPIO7_28                  IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__GPIO7_30                  IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__GPIO4_0                       IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_11__GPIO4_1                       IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_12__GPIO4_2                       IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_13__GPIO4_3                       IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_14__GPIO4_4                       IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE               IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__GPIO6_7                     IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0           IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE               IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__GPIO6_8                     IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1           IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B             IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__GPIO6_9                    IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2          IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0              IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__GPIO6_10                    IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3           IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0              IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__GPIO6_11                    IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4           IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1              IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__GPIO6_14                    IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__MLB_MLBCLK                  IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5           IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2              IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__GPIO6_15                    IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__IPU_SISG_0                  IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__ESAI1_TX0                   IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK               IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__MLB_MLBSIG                  IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6           IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3              IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__GPIO6_16                    IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__IPU_SISG_1                  IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__ESAI1_TX1                   IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26               IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__MLB_MLBDAT                  IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7           IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_MDIO                     IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__GPIO1_22                     IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__ESAI1_SCKR                   IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_COL                      IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2               IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3      IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49             IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__GPIO1_23                  IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR                 IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4   IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50          IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_ER                   IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__GPIO1_24                    IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR                  IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK                  IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3              IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV                  IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__GPIO1_25                   IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                 IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__FEC_RDATA_1                  IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__GPIO1_26                     IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__ESAI1_FST                    IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__MLB_MLBSIG                   IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1               IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__FEC_RDATA_0                  IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__GPIO1_27                     IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__ESAI1_HCKT                   IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT               IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__FEC_TX_EN                   IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__GPIO1_28                    IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2               IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__FEC_TDATA_1                  IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__GPIO1_29                     IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__MLB_MLBCLK                   IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK          IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__FEC_TDATA_0                  IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__GPIO1_30                     IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0            IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__FEC_MDC                       IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__GPIO1_31                      IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__MLB_MLBDAT                    IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG        IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1             IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__PATA_DIOW                   IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__GPIO6_17                    IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX               IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2           IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__PATA_DMACK                 IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__GPIO6_18                   IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX              IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3          IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__PATA_DMARQ                 IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__GPIO7_0                    IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX              IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0              IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4          IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN         IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX          IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1          IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5      IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__PATA_INTRQ                 IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__GPIO7_2                    IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__UART2_CTS                  IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN                 IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2              IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6          IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__PATA_DIOR                   IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__GPIO7_3                     IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__UART2_RTS                   IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__CAN1_RXCAN                  IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7           IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B        IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__GPIO7_4                  IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD               IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__UART1_CTS                IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN               IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0        IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__PATA_IORDY                 IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__GPIO7_5                    IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__ESDHC3_CLK                 IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__UART1_RTS                  IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__CAN2_RXCAN                 IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1          IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__PATA_DA_0                   IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__GPIO7_6                     IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__ESDHC3_RST                  IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__OWIRE_LINE                  IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2           IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__PATA_DA_1                   IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__GPIO7_7                     IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__ESDHC4_CMD                  IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__UART3_CTS                   IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3           IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__PATA_DA_2                   IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__GPIO7_8                     IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__ESDHC4_CLK                  IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__UART3_RTS                   IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4           IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__PATA_CS_0                   IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__GPIO7_9                     IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX               IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5           IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__PATA_CS_1                   IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__GPIO7_10                    IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX               IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6           IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__PATA_DATA_0                IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPIO2_0                    IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0              IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0      IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0             IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7          IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__PATA_DATA_1                IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPIO2_1                    IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1              IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1      IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1             IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__PATA_DATA_2                IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPIO2_2                    IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2              IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2      IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2             IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__PATA_DATA_3                IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPIO2_3                    IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3              IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3      IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3             IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__PATA_DATA_4                IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPIO2_4                    IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4              IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4      IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4             IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__PATA_DATA_5                IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPIO2_5                    IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5              IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5      IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5             IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__PATA_DATA_6                IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPIO2_6                    IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6              IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6      IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6             IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__PATA_DATA_7                IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPIO2_7                    IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7              IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7      IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7             IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__PATA_DATA_8                IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPIO2_8                    IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8              IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8      IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8             IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__PATA_DATA_9                IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPIO2_9                    IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9              IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9      IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9             IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__PATA_DATA_10              IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPIO2_10                  IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6               IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10            IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2               IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10    IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10           IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__PATA_DATA_11              IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPIO2_11                  IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7               IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11            IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3               IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11    IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11           IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__PATA_DATA_12              IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPIO2_12                  IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4               IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12            IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0               IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12    IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12           IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__PATA_DATA_13              IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPIO2_13                  IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5               IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13            IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1               IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13    IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13           IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__PATA_DATA_14              IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPIO2_14                  IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6               IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14            IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2               IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14    IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14           IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__PATA_DATA_15              IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPIO2_15                  IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7               IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15            IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3               IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15    IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15           IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0                 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPIO1_16                    IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPT_CAPIN1                  IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CSPI_MISO                   IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1                 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPIO1_17                    IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPT_CAPIN2                  IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CSPI_SS0                    IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__ESDHC1_CMD                    IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPIO1_18                      IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPT_CMPOUT1                   IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CSPI_MOSI                     IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP                  IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2                 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPIO1_19                    IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2                 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__PWM2_PWMO                   IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CSPI_SS1                    IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB        IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__ESDHC1_CLK                    IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPIO1_20                      IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPT_CLKIN                     IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__CSPI_SCLK                     IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3                 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPIO1_21                    IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3                 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__PWM1_PWMO                   IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__CSPI_SS2                    IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB        IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1              IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__ESDHC2_CLK                    IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__GPIO1_10                      IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__KPP_COL_5                     IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__CSPI_SCLK                     IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__SCC_RANDOM_V                  IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__ESDHC2_CMD                    IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__GPIO1_11                      IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__KPP_ROW_5                     IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC               IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__CSPI_MOSI                     IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__SCC_RANDOM                    IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3                 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__GPIO1_12                    IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__KPP_COL_6                   IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC             IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__CSPI_SS2                    IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__SJC_DONE                    IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2                 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__GPIO1_13                    IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__KPP_ROW_6                   IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD             IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__CSPI_SS1                    IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__SJC_FAIL                    IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1                 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__GPIO1_14                    IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__KPP_COL_7                   IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS            IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__CSPI_SS0                    IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0                 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__GPIO1_15                    IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__KPP_ROW_7                   IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD             IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__CSPI_MISO                   IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT               IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_CLKO                       IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__GPIO1_0                        IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__KPP_COL_5                      IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK               IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__EPIT1_EPITO                    IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB                 IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR               IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CSU_TD                         IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESAI1_SCKR                     IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__GPIO1_1                        IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__KPP_ROW_5                      IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK               IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__PWM2_PWMO                      IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__WDOG2_WDOG_B                   IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESDHC1_CD                      IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__SRC_TESTER_ACK                 IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESAI1_FSR                      IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__GPIO1_9                        IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__KPP_COL_6                      IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__CCM_REF_EN_B                   IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__PWM1_PWMO                      IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__WDOG1_WDOG_B                   IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESDHC1_WP                      IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__SCC_FAIL_STATE                 IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__ESAI1_HCKR                     IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__GPIO1_3                        IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__I2C3_SCL                       IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN                 IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__CCM_CLKO2                      IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0     IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__MLB_MLBCLK                     IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESAI1_SCKT                     IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__GPIO1_6                        IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__I2C3_SDA                       IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0                  IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1     IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESDHC2_LCTL                    IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__MLB_MLBSIG                     IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESAI1_FST                      IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__GPIO1_2                        IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__KPP_ROW_6                      IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1                  IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2     IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESDHC2_WP                      IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__MLB_MLBDAT                     IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESAI1_HCKT                     IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__GPIO1_4                        IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__KPP_COL_7                      IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2                  IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3     IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESDHC2_CD                      IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__SCC_SEC_STATE                  IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3                  IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__GPIO1_5                        IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__KPP_ROW_7                      IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_CLKO                       IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4     IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__I2C3_SCL                       IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_PLL1_BYP                   IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1                  IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__GPIO1_7                        IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__EPIT1_EPITO                    IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CAN1_TXCAN                     IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__UART2_TXD_MUX                  IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_7__FIRI_RXD                       IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__SPDIF_PLOCK                    IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CCM_PLL2_BYP                   IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0                  IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__GPIO1_8                        IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__EPIT2_EPITO                    IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CAN1_RXCAN                     IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__UART2_RXD_MUX                  IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_8__FIRI_TXD                       IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__SPDIF_SRCLK                    IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CCM_PLL3_BYP                   IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2                 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__GPIO7_11                      IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT              IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1          IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SPDIF_IN1                     IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__I2C3_SDA                      IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SJC_DE_B                      IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__ESAI1_TX0                     IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPIO7_12                      IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0              IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPC_PMIC_RDY                  IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG           IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SPDIF_OUT1                    IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__IPU_SNOOP2                    IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SJC_JTAG_ACT                  IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESAI1_TX1                     IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__GPIO7_13                      IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1              IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__OWIRE_LINE                    IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG        IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK              IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESDHC1_LCTL                   IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
-
-#endif  /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index dbced61d9fda..ee9b1f9215df 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -76,7 +76,7 @@
 #define MX31_RTIC_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xec000)
 
 #define MX31_ROMP_BASE_ADDR             0x60000000
-#define MX31_ROMP_BASE_ADDR_VIRT        0xfc500000
+#define MX31_ROMP_BASE_ADDR_VIRT        IOMEM(0xfc500000)
 #define MX31_ROMP_SIZE                  SZ_1M
 
 #define MX31_AVIC_BASE_ADDR             0x68000000
@@ -92,11 +92,11 @@
 #define MX31_CS3_BASE_ADDR              0xb2000000
 
 #define MX31_CS4_BASE_ADDR              0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT         0xf6000000
+#define MX31_CS4_BASE_ADDR_VIRT         IOMEM(0xf6000000)
 #define MX31_CS4_SIZE                   SZ_32M
 
 #define MX31_CS5_BASE_ADDR              0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT         0xf8000000
+#define MX31_CS5_BASE_ADDR_VIRT         IOMEM(0xf8000000)
 #define MX31_CS5_SIZE                   SZ_32M
 
 #define MX31_X_MEMC_BASE_ADDR           0xb8000000
diff --git a/arch/arm/plat-mxc/ssi-fiq-ksym.c b/arch/arm/plat-mxc/ssi-fiq-ksym.c
index b5fad454da78..792090f9a032 100644
--- a/arch/arm/plat-mxc/ssi-fiq-ksym.c
+++ b/arch/arm/plat-mxc/ssi-fiq-ksym.c
@@ -10,7 +10,7 @@
 
 #include <linux/module.h>
 
-#include <mach/ssi.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 
 EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer);
 EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer);
diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
index 8397a2dd19f2..a8b93c5f29b5 100644
--- a/arch/arm/plat-mxc/ssi-fiq.S
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -34,91 +34,98 @@
                 .global imx_ssi_fiq_rx_buffer
                 .global imx_ssi_fiq_tx_buffer
 
+/*
+ * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol
+ * using ENDPROC().  imx_ssi_fiq_start and imx_ssi_fiq_end are used to
+ * mark the function body so that it can be copied to the FIQ vector in
+ * the vectors page.  imx_ssi_fiq_start should only be called as the result
+ * of an FIQ: calling it directly will not work.
+ */
 imx_ssi_fiq_start:
-                ldr r12, imx_ssi_fiq_base
+                ldr r12, .L_imx_ssi_fiq_base
 
                 /* TX */
-                ldr r11, imx_ssi_fiq_tx_buffer
+                ldr r13, .L_imx_ssi_fiq_tx_buffer
 
                 /* shall we send? */
-                ldr r13, [r12, #SSI_SIER]
-                tst r13, #SSI_SIER_TFE0_EN
+                ldr r11, [r12, #SSI_SIER]
+                tst r11, #SSI_SIER_TFE0_EN
                 beq 1f
 
                 /* TX FIFO empty? */
-                ldr r13, [r12, #SSI_SISR]
-                tst r13, #SSI_SISR_TFE0
+                ldr r11, [r12, #SSI_SISR]
+                tst r11, #SSI_SISR_TFE0
                 beq 1f
 
                 mov r10, #0x10000
                 sub r10, #1
                 and r10, r10, r8        /* r10: current buffer offset */
 
-                add r11, r11, r10
+                add r13, r13, r10
 
-                ldrh r13, [r11]
-                strh r13, [r12, #SSI_STX0]
+                ldrh r11, [r13]
+                strh r11, [r12, #SSI_STX0]
 
-                ldrh r13, [r11, #2]
-                strh r13, [r12, #SSI_STX0]
+                ldrh r11, [r13, #2]
+                strh r11, [r12, #SSI_STX0]
 
-                ldrh r13, [r11, #4]
-                strh r13, [r12, #SSI_STX0]
+                ldrh r11, [r13, #4]
+                strh r11, [r12, #SSI_STX0]
 
-                ldrh r13, [r11, #6]
-                strh r13, [r12, #SSI_STX0]
+                ldrh r11, [r13, #6]
+                strh r11, [r12, #SSI_STX0]
 
                 add r10, #8
-                lsr r13, r8, #16        /* r13: buffer size */
-                cmp r10, r13
-                lslgt r8, r13, #16
+                lsr r11, r8, #16        /* r11: buffer size */
+                cmp r10, r11
+                lslgt r8, r11, #16
                 addle r8, #8
 1:
                 /* RX */
 
                 /* shall we receive? */
-                ldr r13, [r12, #SSI_SIER]
-                tst r13, #SSI_SIER_RFF0_EN
+                ldr r11, [r12, #SSI_SIER]
+                tst r11, #SSI_SIER_RFF0_EN
                 beq 1f
 
                 /* RX FIFO full? */
-                ldr r13, [r12, #SSI_SISR]
-                tst r13, #SSI_SISR_RFF0
+                ldr r11, [r12, #SSI_SISR]
+                tst r11, #SSI_SISR_RFF0
                 beq 1f
 
-                ldr r11, imx_ssi_fiq_rx_buffer
+                ldr r13, .L_imx_ssi_fiq_rx_buffer
 
                 mov r10, #0x10000
                 sub r10, #1
                 and r10, r10, r9        /* r10: current buffer offset */
 
-                add r11, r11, r10
+                add r13, r13, r10
 
-                ldr r13, [r12, #SSI_SACNT]
-                tst r13, #SSI_SACNT_AC97EN
+                ldr r11, [r12, #SSI_SACNT]
+                tst r11, #SSI_SACNT_AC97EN
 
-                ldr r13, [r12, #SSI_SRX0]
-                strh r13, [r11]
+                ldr r11, [r12, #SSI_SRX0]
+                strh r11, [r13]
 
-                ldr r13, [r12, #SSI_SRX0]
-                strh r13, [r11, #2]
+                ldr r11, [r12, #SSI_SRX0]
+                strh r11, [r13, #2]
 
                 /* dummy read to skip slot 12 */
-                ldrne r13, [r12, #SSI_SRX0]
+                ldrne r11, [r12, #SSI_SRX0]
 
-                ldr r13, [r12, #SSI_SRX0]
-                strh r13, [r11, #4]
+                ldr r11, [r12, #SSI_SRX0]
+                strh r11, [r13, #4]
 
-                ldr r13, [r12, #SSI_SRX0]
-                strh r13, [r11, #6]
+                ldr r11, [r12, #SSI_SRX0]
+                strh r11, [r13, #6]
 
                 /* dummy read to skip slot 12 */
-                ldrne r13, [r12, #SSI_SRX0]
+                ldrne r11, [r12, #SSI_SRX0]
 
                 add r10, #8
-                lsr r13, r9, #16        /* r13: buffer size */
-                cmp r10, r13
-                lslgt r9, r13, #16
+                lsr r11, r9, #16        /* r11: buffer size */
+                cmp r10, r11
+                lslgt r9, r11, #16
                 addle r9, #8
 
 1:
@@ -126,11 +133,15 @@ imx_ssi_fiq_start:
                 subs    pc, lr, #4
 
                 .align
+.L_imx_ssi_fiq_base:
 imx_ssi_fiq_base:
                 .word 0x0
+.L_imx_ssi_fiq_rx_buffer:
 imx_ssi_fiq_rx_buffer:
                 .word 0x0
+.L_imx_ssi_fiq_tx_buffer:
 imx_ssi_fiq_tx_buffer:
                 .word 0x0
+.L_imx_ssi_fiq_end:
 imx_ssi_fiq_end:
 
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 1996c3e3b8fe..3da78cfc5a94 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <linux/module.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -29,9 +28,6 @@
 #include <asm/proc-fns.h>
 #include <asm/mach-types.h>
 
-void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
-EXPORT_SYMBOL_GPL(imx_ioremap);
-
 static void __iomem *wdog_base;
 
 /*
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index a017e994e006..dacaee009a4e 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := common.o sram.o clock.o dma.o mux.o fb.o counter_32k.o
+obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index e5778ed689d8..111315a69354 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -18,7 +18,7 @@
 
 #include <plat/common.h>
 #include <plat/vram.h>
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 #include <plat/dma.h>
 
 #include <plat/omap-secure.h>
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 40bc06a7ac43..6013831a043e 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -32,7 +32,6 @@
 #include <linux/clk.h>
 
 #include <mach/irqs.h>
-#include <plat/mux.h>
 #include <plat/i2c.h>
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index a531149823bb..b2eac60b6904 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -21,8 +21,6 @@
 #include <linux/device.h>
 #include <linux/pm_qos.h>
 
-#include <plat/mux.h>
-
 #define DRIVER_NAME     "omap_uart"
 
 /*
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 27bcc2441195..106f50665804 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -60,6 +60,7 @@ extern struct dev_pm_domain omap_device_pm_domain;
  * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
  * @_state: one of OMAP_DEVICE_STATE_* (see above)
  * @flags: device flags
+ * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
  *
  * Integrates omap_hwmod data into Linux platform_device.
  *
@@ -73,6 +74,7 @@ struct omap_device {
         struct omap_device_pm_latency   *pm_lats;
         u32                             dev_wakeup_lat;
         u32                             _dev_wakeup_lat_limit;
+        unsigned long                   _driver_status;
         u8                              pm_lats_cnt;
         s8                              pm_lat_level;
         u8                              hwmods_cnt;
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 09e14ce3ec57..b3349f7b1a2c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -630,6 +630,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
 
 int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
 int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
                                    const char *name, struct resource *res);
 
diff --git a/arch/arm/plat-omap/include/plat/param.h b/arch/arm/plat-omap/include/plat/param.h
deleted file mode 100644
index 1eb4dc326979..000000000000
--- a/arch/arm/plat-omap/include/plat/param.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/param.h
- *
- */
-
-#ifdef CONFIG_OMAP_32K_TIMER_HZ
-#define HZ      CONFIG_OMAP_32K_TIMER_HZ
-#endif
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
deleted file mode 100644
index fd0d3aad00ef..000000000000
--- a/arch/arm/plat-omap/mux.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/mux.c
- *
- * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
- *
- * Copyright (C) 2003 - 2008 Nokia Corporation
- *
- * Written by Tony Lindgren
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-
-#include <asm/system.h>
-
-#include <plat/cpu.h>
-#include <plat/mux.h>
-
-#ifdef CONFIG_OMAP_MUX
-
-static struct omap_mux_cfg *mux_cfg;
-
-int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
-{
-        if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
-                        || !arch_mux_cfg->cfg_reg) {
-                printk(KERN_ERR "Invalid pin table\n");
-                return -EINVAL;
-        }
-
-        mux_cfg = arch_mux_cfg;
-
-        return 0;
-}
-
-/*
- * Sets the Omap MUX and PULL_DWN registers based on the table
- */
-int __init_or_module omap_cfg_reg(const unsigned long index)
-{
-        struct pin_config *reg;
-
-        if (!cpu_class_is_omap1()) {
-                printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
-                                index);
-                WARN_ON(1);
-                return -EINVAL;
-        }
-
-        if (mux_cfg == NULL) {
-                printk(KERN_ERR "Pin mux table not initialized\n");
-                return -ENODEV;
-        }
-
-        if (index >= mux_cfg->size) {
-                printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
-                       index, mux_cfg->size);
-                dump_stack();
-                return -ENODEV;
-        }
-
-        reg = &mux_cfg->pins[index];
-
-        if (!mux_cfg->cfg_reg)
-                return -ENODEV;
-
-        return mux_cfg->cfg_reg(reg);
-}
-EXPORT_SYMBOL(omap_cfg_reg);
-#else
-#define omap_mux_init() do {} while(0)
-#define omap_cfg_reg(x) do {} while(0)
-#endif  /* CONFIG_OMAP_MUX */
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 5b6974269107..cee85a55bd82 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -365,6 +365,14 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
                 goto odbfd_exit1;
         }
 
+        /* Fix up missing resource names */
+        for (i = 0; i < pdev->num_resources; i++) {
+                struct resource *r = &pdev->resource[i];
+
+                if (r->name == NULL)
+                        r->name = dev_name(&pdev->dev);
+        }
+
         if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
                 omap_device_disable_idle_on_suspend(pdev);
 
@@ -380,17 +388,21 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
                                       unsigned long event, void *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *od;
 
         switch (event) {
-        case BUS_NOTIFY_ADD_DEVICE:
-                if (pdev->dev.of_node)
-                        omap_device_build_from_dt(pdev);
-                break;
-
         case BUS_NOTIFY_DEL_DEVICE:
                 if (pdev->archdata.od)
                         omap_device_delete(pdev->archdata.od);
                 break;
+        case BUS_NOTIFY_ADD_DEVICE:
+                if (pdev->dev.of_node)
+                        omap_device_build_from_dt(pdev);
+                /* fall through */
+        default:
+                od = to_omap_device(pdev);
+                if (od)
+                        od->_driver_status = event;
         }
 
         return NOTIFY_DONE;
@@ -481,6 +493,33 @@ static int omap_device_fill_resources(struct omap_device *od,
 }
 
 /**
+ * _od_fill_dma_resources - fill in array of struct resource with dma resources
+ * @od: struct omap_device *
+ * @res: pointer to an array of struct resource to be filled in
+ *
+ * Populate one or more empty struct resource pointed to by @res with
+ * the dma resource data for this omap_device @od.  Used by
+ * omap_device_alloc() after calling omap_device_count_resources().
+ *
+ * Ideally this function would not be needed at all.  If we have
+ * mechanism to get dma resources from DT.
+ *
+ * Returns 0.
+ */
+static int _od_fill_dma_resources(struct omap_device *od,
+                                      struct resource *res)
+{
+        int i, r;
+
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                r = omap_hwmod_fill_dma_resources(od->hwmods[i], res);
+                res += r;
+        }
+
+        return 0;
+}
+
+/**
  * omap_device_alloc - allocate an omap_device
  * @pdev: platform_device that will be included in this omap_device
  * @oh: ptr to the single omap_hwmod that backs this omap_device
@@ -519,24 +558,44 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
         od->hwmods = hwmods;
         od->pdev = pdev;
 
+        res_count = omap_device_count_resources(od);
         /*
-         * HACK: Ideally the resources from DT should match, and hwmod
-         * should just add the missing ones. Since the name is not
-         * properly populated by DT, stick to hwmod resources only.
+         * DT Boot:
+         *   OF framework will construct the resource structure (currently
+         *   does for MEM & IRQ resource) and we should respect/use these
+         *   resources, killing hwmod dependency.
+         *   If pdev->num_resources > 0, we assume that MEM & IRQ resources
+         *   have been allocated by OF layer already (through DTB).
+         *
+         * Non-DT Boot:
+         *   Here, pdev->num_resources = 0, and we should get all the
+         *   resources from hwmod.
+         *
+         * TODO: Once DMA resource is available from OF layer, we should
+         *   kill filling any resources from hwmod.
          */
-        if (pdev->num_resources && pdev->resource)
-                dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
-                        __func__, pdev->num_resources);
-
-        res_count = omap_device_count_resources(od);
-        if (res_count > 0) {
-                dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
-                        __func__, res_count);
+        if (res_count > pdev->num_resources) {
+                /* Allocate resources memory to account for new resources */
                 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
                 if (!res)
                         goto oda_exit3;
 
-                omap_device_fill_resources(od, res);
+                /*
+                 * If pdev->num_resources > 0, then assume that,
+                 * MEM and IRQ resources will only come from DT and only
+                 * fill DMA resource from hwmod layer.
+                 */
+                if (pdev->num_resources && pdev->resource) {
+                        dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
+                                __func__, res_count);
+                        memcpy(res, pdev->resource,
+                               sizeof(struct resource) * pdev->num_resources);
+                        _od_fill_dma_resources(od, &res[pdev->num_resources]);
+                } else {
+                        dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
+                                __func__, res_count);
+                        omap_device_fill_resources(od, res);
+                }
 
                 ret = platform_device_add_resources(pdev, res, res_count);
                 kfree(res);
@@ -747,6 +806,10 @@ static int _od_suspend_noirq(struct device *dev)
         struct omap_device *od = to_omap_device(pdev);
         int ret;
 
+        /* Don't attempt late suspend on a driver that is not bound */
+        if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER)
+                return 0;
+
         ret = pm_generic_suspend_noirq(dev);
 
         if (!ret && !pm_runtime_status_suspended(dev)) {
@@ -1175,3 +1238,41 @@ static int __init omap_device_init(void)
         return 0;
 }
 core_initcall(omap_device_init);
+
+/**
+ * omap_device_late_idle - idle devices without drivers
+ * @dev: struct device * associated with omap_device
+ * @data: unused
+ *
+ * Check the driver bound status of this device, and idle it
+ * if there is no driver attached.
+ */
+static int __init omap_device_late_idle(struct device *dev, void *data)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *od = to_omap_device(pdev);
+
+        if (!od)
+                return 0;
+
+        /*
+         * If omap_device state is enabled, but has no driver bound,
+         * idle it.
+         */
+        if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
+                if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
+                        dev_warn(dev, "%s: enabled but no driver.  Idling\n",
+                                 __func__);
+                        omap_device_idle(pdev);
+                }
+        }
+
+        return 0;
+}
+
+static int __init omap_device_late_init(void)
+{
+        bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
+        return 0;
+}
+late_initcall(omap_device_late_init);
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index c20ce0f5ce33..a82cecb84948 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -1,10 +1,10 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
-obj-y   := irq.o pcie.o time.o common.o mpp.o addr-map.o
-obj-m   :=
-obj-n   :=
-obj-    :=
+obj-y                             += addr-map.o
 
-obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index 367ca89ac403..a7b8060c293a 100644
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 static void __init __iomem *
 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
-        return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
+        return cfg->bridge_virt_base + (win << 4);
 }
 
 /*
@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
  * Setup MBUS dram target info.
  */
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-                                        const u32 ddr_window_cpu_base)
+                                        const void __iomem *ddr_window_cpu_base)
 {
-        void __iomem *addr;
         int i;
         int cs;
 
         orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
-        addr = (void __iomem *)ddr_window_cpu_base;
-
         for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+                u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
+                u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
 
                 /*
                  * Chip select enabled?
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index b8b747a9d360..b8a688cad4c2 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -19,8 +19,8 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
 #include <net/dsa.h>
-#include <plat/mv_xor.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/dma-mv_xor.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 #include <mach/bridge-regs.h>
 
 /* Create a clkdev entry for a given device/clk */
@@ -86,13 +86,13 @@ static void __init uart_complete(
         struct platform_device *orion_uart,
         struct plat_serial8250_port *data,
         struct resource *resources,
-        unsigned int membase,
+        void __iomem *membase,
         resource_size_t mapbase,
         unsigned int irq,
         struct clk *clk)
 {
         data->mapbase = mapbase;
-        data->membase = (void __iomem *)membase;
+        data->membase = membase;
         data->irq = irq;
         data->uartclk = uart_get_clk_rate(clk);
         orion_uart->dev.platform_data = data;
@@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = {
         .id                     = PLAT8250_DEV_PLATFORM,
 };
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
@@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = {
         .id                     = PLAT8250_DEV_PLATFORM1,
 };
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
@@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = {
         .id                     = PLAT8250_DEV_PLATFORM2,
 };
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
@@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = {
         .id                     = 3,
 };
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index dfda74fae6f2..c29ee7ea200b 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -23,7 +23,7 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
-#include <plat/gpio.h>
+#include <plat/orion-gpio.h>
 
 /*
  * GPIO unit register offsets.
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index fd556f77562c..ec63e4a627d0 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
         const int num_wins;     /* Total number of windows */
         const int remappable_wins;
-        const u32 bridge_virt_base;
+        void __iomem *bridge_virt_base;
 
         /* If NULL, the default cpu_win_can_remap will be used, using
            the value in remappable_wins */
@@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
                                 const u8 attr, const int remap);
 
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-                                        const u32 ddr_window_cpu_base);
+                                        const void __iomem *ddr_window_cpu_base);
 #endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index ae2377ef63e5..6bbc3fe5f58e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -13,22 +13,22 @@
 
 struct dsa_platform_data;
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
index 723adce99f41..254552fee889 100644
--- a/arch/arm/plat-orion/include/plat/mpp.h
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -29,6 +29,6 @@
 #define MPP_OUTPUT_MASK         GENERIC_MPP(0, 0x0, 0, 1)
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-                           unsigned int mpp_max, unsigned int dev_bus);
+                           unsigned int mpp_max, void __iomem *dev_bus);
 
 #endif
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/orion-gpio.h
index 81c6fc8a7b28..614dcac9dc52 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/orion-gpio.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-orion/include/plat/gpio.h
+ * arch/arm/plat-orion/include/plat/orion-gpio.h
  *
  * Marvell Orion SoC GPIO handling.
  *
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index 4d5f1f6e18df..07527e417c62 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,9 +11,9 @@
 #ifndef __PLAT_TIME_H
 #define __PLAT_TIME_H
 
-void orion_time_set_base(u32 timer_base);
+void orion_time_set_base(void __iomem *timer_base);
 
-void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
                      unsigned int irq, unsigned int tclk);
 
 
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index d751964def4c..1867944415ca 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -16,7 +16,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <plat/irq.h>
-#include <plat/gpio.h>
+#include <plat/orion-gpio.h>
 
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 {
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 3b1e17bd3d17..e686fe76a96b 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -14,18 +14,19 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <mach/hardware.h>
+#include <plat/orion-gpio.h>
 #include <plat/mpp.h>
 
 /* Address of the ith MPP control register */
-static __init unsigned long mpp_ctrl_addr(unsigned int i,
-                                          unsigned long dev_bus)
+static __init void __iomem *mpp_ctrl_addr(unsigned int i,
+                                          void __iomem *dev_bus)
 {
         return dev_bus + (i) * 4;
 }
 
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-                           unsigned int mpp_max, unsigned int dev_bus)
+                           unsigned int mpp_max, void __iomem *dev_bus)
 {
         unsigned int mpp_nr_regs = (1 + mpp_max/8);
         u32 mpp_ctrl[mpp_nr_regs];
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 1ed8d1397fcf..0f4fa863dd55 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = {
 };
 
 void __init
-orion_time_set_base(u32 _timer_base)
+orion_time_set_base(void __iomem *_timer_base)
 {
-        timer_base = (void __iomem *)_timer_base;
+        timer_base = _timer_base;
 }
 
 void __init
-orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
                 unsigned int irq, unsigned int tclk)
 {
         u32 u;
@@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
         /*
          * Set SoC-specific data.
          */
-        bridge_base = (void __iomem *)_bridge_base;
+        bridge_base = _bridge_base;
         bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
 
         ticks_per_jiffy = (tclk + HZ/2) / HZ;
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fc49f3dabd76..b151d4932661 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -35,7 +35,6 @@
 #include <media/s5p_hdmi.h>
 
 #include <asm/irq.h>
-#include <asm/pmu.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -48,24 +47,24 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/adc.h>
-#include <plat/ata.h>
-#include <plat/ehci.h>
+#include <linux/platform_data/ata-samsung_cf.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/fb.h>
 #include <plat/fb-s3c2410.h>
-#include <plat/hwmon.h>
-#include <plat/iic.h>
+#include <linux/platform_data/hwmon-s3c.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
-#include <plat/mci.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mmc-s3cmci.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/sdhci.h>
-#include <plat/ts.h>
-#include <plat/udc.h>
-#include <plat/usb-control.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/usb-phy.h>
 #include <plat/regs-iic.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
-#include <plat/s3c64xx-spi.h>
+#include <linux/platform_data/spi-s3c64xx.h>
 
 static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
 
@@ -1132,7 +1131,7 @@ static struct resource s5p_pmu_resource[] = {
 
 static struct platform_device s5p_device_pmu = {
         .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
         .num_resources  = ARRAY_SIZE(s5p_pmu_resource),
         .resource       = s5p_pmu_resource,
 };
diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h
index bab139201761..d1ecef0e38e0 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-fns.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h
@@ -1,98 +1 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
- *
- * Copyright (c) 2003-2009 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - hardware
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __MACH_GPIO_FNS_H
-#define __MACH_GPIO_FNS_H __FILE__
-
-/* These functions are in the to-be-removed category and it is strongly
- * encouraged not to use these in new code. They will be marked deprecated
- * very soon.
- *
- * Most of the functionality can be either replaced by the gpiocfg calls
- * for the s3c platform or by the generic GPIOlib API.
- *
- * As of 2.6.35-rc, these will be removed, with the few drivers using them
- * either replaced or given a wrapper until the calls can be removed.
-*/
-
 #include <plat/gpio-cfg.h>
-
-static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
-{
-        /* 1:1 mapping between cfgpin and setcfg calls at the moment */
-        s3c_gpio_cfgpin(pin, cfg);
-}
-
-/* external functions for GPIO support
- *
- * These allow various different clients to access the same GPIO
- * registers without conflicting. If your driver only owns the entire
- * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
-*/
-
-extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
-
-/* s3c2410_gpio_getirq
- *
- * turn the given pin number into the corresponding IRQ number
- *
- * returns:
- *      < 0 = no interrupt for this pin
- *      >=0 = interrupt number for the pin
-*/
-
-extern int s3c2410_gpio_getirq(unsigned int pin);
-
-/* s3c2410_gpio_irqfilter
- *
- * set the irq filtering on the given pin
- *
- * on = 0 => disable filtering
- *      1 => enable filtering
- *
- * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
- *          width of filter (0 through 63)
- *
- *
-*/
-
-extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                                  unsigned int config);
-
-/* s3c2410_gpio_pullup
- *
- * This call should be replaced with s3c_gpio_setpull().
- *
- * As a note, there is currently no distinction between pull-up and pull-down
- * in the s3c24xx series devices with only an on/off configuration.
- */
-
-/* s3c2410_gpio_pullup
- *
- * configure the pull-up control on the given pin
- *
- * to = 1 => disable the pull-up
- *      0 => enable the pull-up
- *
- * eg;
- *
- *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
-*/
-
-extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-
-extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
-
-extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
-
-#endif /* __MACH_GPIO_FNS_H */
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
index f9431fe5b06e..23557d30e44c 100644
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c
@@ -24,7 +24,7 @@
 
 #include <asm/mach/irq.h>
 
-#define GPIO_BASE(chip)         (((unsigned long)(chip)->base) & 0xFFFFF000u)
+#define GPIO_BASE(chip)         ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
 
 #define CON_OFFSET              0x700
 #define MASK_OFFSET             0x900
@@ -153,7 +153,7 @@ static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
         bank->chips[group - bank->start] = chip;
 
         gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
-                                    (void __iomem *)GPIO_BASE(chip),
+                                    GPIO_BASE(chip),
                                     handle_level_irq);
         if (!gc)
                 return -ENOMEM;
diff --git a/arch/arm/plat-spear/include/plat/gpio.h b/arch/arm/plat-spear/include/plat/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/plat-spear/include/plat/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 272769a8a7d6..74cfd94cbf80 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,3 +1,5 @@
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
diff --git a/arch/arm/plat-versatile/include/plat/platsmp.h b/arch/arm/plat-versatile/include/plat/platsmp.h
new file mode 100644
index 000000000000..50fb830192e0
--- /dev/null
+++ b/arch/arm/plat-versatile/include/plat/platsmp.h
@@ -0,0 +1,14 @@
+/*
+ *  linux/arch/arm/plat-versatile/include/plat/platsmp.h
+ *
+ *  Copyright (C) 2011 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extern void versatile_secondary_startup(void);
+extern void versatile_secondary_init(unsigned int cpu);
+extern int  versatile_boot_secondary(unsigned int cpu, struct task_struct *idle);
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index d7c5c171f5aa..04ca4937d8ca 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -20,12 +20,6 @@
 #include <asm/hardware/gic.h>
 
 /*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
-
-/*
  * Write pen_release in a way that is guaranteed to be visible to all
  * observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
@@ -40,7 +34,7 @@ static void __cpuinit write_pen_release(int val)
 
 static DEFINE_SPINLOCK(boot_lock);
 
-void __cpuinit platform_secondary_init(unsigned int cpu)
+void __cpuinit versatile_secondary_init(unsigned int cpu)
 {
         /*
          * if any interrupts are already enabled for the primary
@@ -62,7 +56,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         spin_unlock(&boot_lock);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned long timeout;
 
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2997e56ce0dd..7bc7948c5432 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -158,7 +158,6 @@ edb9315a		MACH_EDB9315A		EDB9315A		772
 stargate2               MACH_STARGATE2          STARGATE2               774
 intelmote2              MACH_INTELMOTE2         INTELMOTE2              775
 trizeps4                MACH_TRIZEPS4           TRIZEPS4                776
-pnx4008                 MACH_PNX4008            PNX4008                 782
 cpuat91                 MACH_CPUAT91            CPUAT91                 787
 iq81340sc               MACH_IQ81340SC          IQ81340SC               799
 iq81340mc               MACH_IQ81340MC          IQ81340MC               801
diff --git a/drivers/Kconfig b/drivers/Kconfig
index ece958d3762e..36d3daa19a74 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -152,4 +152,6 @@ source "drivers/vme/Kconfig"
 
 source "drivers/pwm/Kconfig"
 
+source "drivers/irqchip/Kconfig"
+
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 5b421840c48d..8c30e73cd94c 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -5,6 +5,8 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+obj-y                           += irqchip/
+
 # GPIO must come after pinctrl as gpios may need to mux pins etc
 obj-y                           += pinctrl/
 obj-y                           += gpio/
diff --git a/drivers/ata/pata_ep93xx.c b/drivers/ata/pata_ep93xx.c
index 6ef2e3741f76..e056406d6a11 100644
--- a/drivers/ata/pata_ep93xx.c
+++ b/drivers/ata/pata_ep93xx.c
@@ -43,7 +43,7 @@
 #include <linux/dmaengine.h>
 #include <linux/ktime.h>
 
-#include <mach/dma.h>
+#include <linux/platform_data/dma-ep93xx.h>
 #include <mach/platform.h>
 
 #define DRV_NAME        "ep93xx-ide"
diff --git a/drivers/ata/pata_pxa.c b/drivers/ata/pata_pxa.c
index 0bb0fb7b26bc..4b8ba559fe24 100644
--- a/drivers/ata/pata_pxa.c
+++ b/drivers/ata/pata_pxa.c
@@ -32,7 +32,7 @@
 #include <scsi/scsi_host.h>
 
 #include <mach/pxa2xx-regs.h>
-#include <mach/pata_pxa.h>
+#include <linux/platform_data/ata-pxa.h>
 #include <mach/dma.h>
 
 #define DRV_NAME        "pata_pxa"
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
index 1b372c297195..63ffb002ec67 100644
--- a/drivers/ata/pata_samsung_cf.c
+++ b/drivers/ata/pata_samsung_cf.c
@@ -23,7 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <plat/ata.h>
+#include <linux/platform_data/ata-samsung_cf.h>
 #include <plat/regs-ata.h>
 
 #define DRV_NAME "pata_samsung_cf"
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7f0b5ca78516..bace9e98f75d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -40,4 +40,17 @@ config COMMON_CLK_WM831X
           Supports the clocking subsystem of the WM831x/2x series of
           PMICs from Wolfson Microlectronics.
 
+config COMMON_CLK_VERSATILE
+        bool "Clock driver for ARM Reference designs"
+        depends on ARCH_INTEGRATOR || ARCH_REALVIEW
+        ---help---
+          Supports clocking on ARM Reference designs Integrator/AP,
+          Integrator/CP, RealView PB1176, EB, PB11MP and PBX.
+
+config COMMON_CLK_MAX77686
+        tristate "Clock driver for Maxim 77686 MFD"
+        depends on MFD_MAX77686
+        ---help---
+          This driver supports Maxim 77686 crystal oscillator clock. 
+
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea387054..9184b5e19edf 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -3,13 +3,21 @@ obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 obj-$(CONFIG_COMMON_CLK)        += clk.o clk-fixed-rate.o clk-gate.o \
                                    clk-mux.o clk-divider.o clk-fixed-factor.o
 # SoCs specific
+obj-$(CONFIG_ARCH_BCM2835)      += clk-bcm2835.o
 obj-$(CONFIG_ARCH_NOMADIK)      += clk-nomadik.o
 obj-$(CONFIG_ARCH_HIGHBANK)     += clk-highbank.o
 obj-$(CONFIG_ARCH_MXS)          += mxs/
 obj-$(CONFIG_ARCH_SOCFPGA)      += socfpga/
 obj-$(CONFIG_PLAT_SPEAR)        += spear/
 obj-$(CONFIG_ARCH_U300)         += clk-u300.o
-obj-$(CONFIG_ARCH_INTEGRATOR)   += versatile/
+obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
+obj-$(CONFIG_ARCH_PRIMA2)       += clk-prima2.o
+ifeq ($(CONFIG_COMMON_CLK), y)
+obj-$(CONFIG_ARCH_MMP)          += mmp/
+endif
+obj-$(CONFIG_MACH_LOONGSON1)    += clk-ls1x.o
+obj-$(CONFIG_ARCH_U8500)        += ux500/
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
+obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c
new file mode 100644
index 000000000000..67ad16b20b81
--- /dev/null
+++ b/drivers/clk/clk-bcm2835.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 2012 Stephen Warren
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/bcm2835.h>
+
+/*
+ * These are fixed clocks. They're probably not all root clocks and it may
+ * be possible to turn them on and off but until this is mapped out better
+ * it's the only way they can be used.
+ */
+void __init bcm2835_init_clocks(void)
+{
+        struct clk *clk;
+        int ret;
+
+        clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT,
+                                        250000000);
+        if (!clk)
+                pr_err("sys_pclk not registered\n");
+
+        clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT,
+                                        126000000);
+        if (!clk)
+                pr_err("apb_pclk not registered\n");
+
+        clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT,
+                                        3000000);
+        if (!clk)
+                pr_err("uart0_pclk not registered\n");
+        ret = clk_register_clkdev(clk, NULL, "20201000.uart");
+        if (ret)
+                pr_err("uart0_pclk alias not registered\n");
+
+        clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT,
+                                        125000000);
+        if (!clk)
+                pr_err("uart1_pclk not registered\n");
+        ret = clk_register_clkdev(clk, NULL, "20215000.uart");
+        if (ret)
+                pr_err("uart0_pclk alias not registered\n");
+}
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000000000000..f20b750235f6
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include <loongson1.h>
+
+#define OSC     33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+        return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+        u32 pll, rate;
+
+        pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+        rate = ((12 + (pll & 0x3f)) * 1000000) +
+                ((((pll >> 8) & 0x3ff) * 1000000) >> 10);
+        rate *= OSC;
+        rate >>= 1;
+
+        return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+        .enable = ls1x_pll_clk_enable,
+        .disable = ls1x_pll_clk_disable,
+        .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+         const char *name, const char *parent_name, unsigned long flags)
+{
+        struct clk_hw *hw;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        /* allocate the divider */
+        hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+        if (!hw) {
+                pr_err("%s: could not allocate clk_hw\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        init.name = name;
+        init.ops = &ls1x_pll_clk_ops;
+        init.flags = flags | CLK_IS_BASIC;
+        init.parent_names = (parent_name ? &parent_name : NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+        hw->init = &init;
+
+        /* register the clock */
+        clk = clk_register(dev, hw);
+
+        if (IS_ERR(clk))
+                kfree(hw);
+
+        return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+        struct clk *clk;
+
+        clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
+        clk_prepare_enable(clk);
+
+        clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
+                        CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+                        DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+        clk_prepare_enable(clk);
+        clk_register_clkdev(clk, "cpu", NULL);
+
+        clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
+                        CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+                        DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+        clk_prepare_enable(clk);
+        clk_register_clkdev(clk, "dc", NULL);
+
+        clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
+                        CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+                        DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+        clk_prepare_enable(clk);
+        clk_register_clkdev(clk, "ahb", NULL);
+        clk_register_clkdev(clk, "stmmaceth", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2);
+        clk_prepare_enable(clk);
+        clk_register_clkdev(clk, "apb", NULL);
+        clk_register_clkdev(clk, "serial8250", NULL);
+}
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
new file mode 100644
index 000000000000..ac5f5434cb9a
--- /dev/null
+++ b/drivers/clk/clk-max77686.c
@@ -0,0 +1,244 @@
+/*
+ * clk-max77686.c - Clock driver for Maxim 77686
+ *
+ * Copyright (C) 2012 Samsung Electornics
+ * Jonghwa Lee <jonghwa3.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/max77686.h>
+#include <linux/mfd/max77686-private.h>
+#include <linux/clk-provider.h>
+#include <linux/mutex.h>
+#include <linux/clkdev.h>
+
+enum {
+        MAX77686_CLK_AP = 0,
+        MAX77686_CLK_CP,
+        MAX77686_CLK_PMIC,
+        MAX77686_CLKS_NUM,
+};
+
+struct max77686_clk {
+        struct max77686_dev *iodev;
+        u32 mask;
+        struct clk_hw hw;
+        struct clk_lookup *lookup;
+};
+
+static struct max77686_clk *get_max77686_clk(struct clk_hw *hw)
+{
+        return container_of(hw, struct max77686_clk, hw);
+}
+
+static int max77686_clk_prepare(struct clk_hw *hw)
+{
+        struct max77686_clk *max77686;
+        int ret;
+
+        max77686 = get_max77686_clk(hw);
+        if (!max77686)
+                return -ENOMEM;
+
+        ret = regmap_update_bits(max77686->iodev->regmap,
+                MAX77686_REG_32KHZ, max77686->mask, max77686->mask);
+
+        return ret;
+}
+
+static void max77686_clk_unprepare(struct clk_hw *hw)
+{
+        struct max77686_clk *max77686;
+
+        max77686 = get_max77686_clk(hw);
+        if (!max77686)
+                return;
+
+        regmap_update_bits(max77686->iodev->regmap,
+                MAX77686_REG_32KHZ, max77686->mask, ~max77686->mask);
+}
+
+static int max77686_clk_is_enabled(struct clk_hw *hw)
+{
+        struct max77686_clk *max77686;
+        int ret;
+        u32 val;
+
+        max77686 = get_max77686_clk(hw);
+        if (!max77686)
+                return -ENOMEM;
+
+        ret = regmap_read(max77686->iodev->regmap,
+                                MAX77686_REG_32KHZ, &val);
+
+        if (ret < 0)
+                return -EINVAL;
+
+        return val & max77686->mask;
+}
+
+static struct clk_ops max77686_clk_ops = {
+        .prepare        = max77686_clk_prepare,
+        .unprepare      = max77686_clk_unprepare,
+        .is_enabled     = max77686_clk_is_enabled,
+};
+
+static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = {
+        [MAX77686_CLK_AP] = {
+                .name = "32khz_ap",
+                .ops = &max77686_clk_ops,
+                .flags = CLK_IS_ROOT,
+        },
+        [MAX77686_CLK_CP] = {
+                .name = "32khz_cp",
+                .ops = &max77686_clk_ops,
+                .flags = CLK_IS_ROOT,
+        },
+        [MAX77686_CLK_PMIC] = {
+                .name = "32khz_pmic",
+                .ops = &max77686_clk_ops,
+                .flags = CLK_IS_ROOT,
+        },
+};
+
+static int max77686_clk_register(struct device *dev,
+                                struct max77686_clk *max77686)
+{
+        struct clk *clk;
+        struct clk_hw *hw = &max77686->hw;
+
+        clk = clk_register(dev, hw);
+
+        if (IS_ERR(clk))
+                return -ENOMEM;
+
+        max77686->lookup = devm_kzalloc(dev, sizeof(struct clk_lookup),
+                                        GFP_KERNEL);
+        if (IS_ERR(max77686->lookup))
+                return -ENOMEM;
+
+        max77686->lookup->con_id = hw->init->name;
+        max77686->lookup->clk = clk;
+
+        clkdev_add(max77686->lookup);
+
+        return 0;
+}
+
+static __devinit int max77686_clk_probe(struct platform_device *pdev)
+{
+        struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent);
+        struct max77686_clk **max77686_clks;
+        int i, ret;
+
+        max77686_clks = devm_kzalloc(&pdev->dev, sizeof(struct max77686_clk *)
+                                        * MAX77686_CLKS_NUM, GFP_KERNEL);
+        if (IS_ERR(max77686_clks))
+                return -ENOMEM;
+
+        for (i = 0; i < MAX77686_CLKS_NUM; i++) {
+                max77686_clks[i] = devm_kzalloc(&pdev->dev,
+                                        sizeof(struct max77686_clk), GFP_KERNEL);
+                if (IS_ERR(max77686_clks[i]))
+                        return -ENOMEM;
+        }
+
+        for (i = 0; i < MAX77686_CLKS_NUM; i++) {
+                max77686_clks[i]->iodev = iodev;
+                max77686_clks[i]->mask = 1 << i;
+                max77686_clks[i]->hw.init = &max77686_clks_init[i];
+
+                ret = max77686_clk_register(&pdev->dev, max77686_clks[i]);
+                if (ret) {
+                        switch (i) {
+                        case MAX77686_CLK_AP:
+                                dev_err(&pdev->dev, "Fail to register CLK_AP\n");
+                                goto err_clk_ap;
+                                break;
+                        case MAX77686_CLK_CP:
+                                dev_err(&pdev->dev, "Fail to register CLK_CP\n");
+                                goto err_clk_cp;
+                                break;
+                        case MAX77686_CLK_PMIC:
+                                dev_err(&pdev->dev, "Fail to register CLK_PMIC\n");
+                                goto err_clk_pmic;
+                        }
+                }
+        }
+
+        platform_set_drvdata(pdev, max77686_clks);
+
+        goto out;
+
+err_clk_pmic:
+        clkdev_drop(max77686_clks[MAX77686_CLK_CP]->lookup);
+        kfree(max77686_clks[MAX77686_CLK_CP]->hw.clk);
+err_clk_cp:
+        clkdev_drop(max77686_clks[MAX77686_CLK_AP]->lookup);
+        kfree(max77686_clks[MAX77686_CLK_AP]->hw.clk);
+err_clk_ap:
+out:
+        return ret;
+}
+
+static int __devexit max77686_clk_remove(struct platform_device *pdev)
+{
+        struct max77686_clk **max77686_clks = platform_get_drvdata(pdev);
+        int i;
+
+        for (i = 0; i < MAX77686_CLKS_NUM; i++) {
+                clkdev_drop(max77686_clks[i]->lookup);
+                kfree(max77686_clks[i]->hw.clk);
+        }
+        return 0;
+}
+
+static const struct platform_device_id max77686_clk_id[] = {
+        { "max77686-clk", 0},
+        { },
+};
+MODULE_DEVICE_TABLE(platform, max77686_clk_id);
+
+static struct platform_driver max77686_clk_driver = {
+        .driver = {
+                .name  = "max77686-clk",
+                .owner = THIS_MODULE,
+        },
+        .probe = max77686_clk_probe,
+        .remove = __devexit_p(max77686_clk_remove),
+        .id_table = max77686_clk_id,
+};
+
+static int __init max77686_clk_init(void)
+{
+        return platform_driver_register(&max77686_clk_driver);
+}
+subsys_initcall(max77686_clk_init);
+
+static void __init max77686_clk_cleanup(void)
+{
+        platform_driver_unregister(&max77686_clk_driver);
+}
+module_exit(max77686_clk_cleanup);
+
+MODULE_DESCRIPTION("MAXIM 77686 Clock Driver");
+MODULE_AUTHOR("Jonghwa Lee <jonghwa3.lee@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/clk-prima2.c
new file mode 100644
index 000000000000..517874fa6858
--- /dev/null
+++ b/drivers/clk/clk-prima2.c
@@ -0,0 +1,1171 @@
+/*
+ * Clock tree for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#define SIRFSOC_CLKC_CLK_EN0    0x0000
+#define SIRFSOC_CLKC_CLK_EN1    0x0004
+#define SIRFSOC_CLKC_REF_CFG    0x0014
+#define SIRFSOC_CLKC_CPU_CFG    0x0018
+#define SIRFSOC_CLKC_MEM_CFG    0x001c
+#define SIRFSOC_CLKC_SYS_CFG    0x0020
+#define SIRFSOC_CLKC_IO_CFG     0x0024
+#define SIRFSOC_CLKC_DSP_CFG    0x0028
+#define SIRFSOC_CLKC_GFX_CFG    0x002c
+#define SIRFSOC_CLKC_MM_CFG     0x0030
+#define SIRFSOC_CLKC_LCD_CFG     0x0034
+#define SIRFSOC_CLKC_MMC_CFG    0x0038
+#define SIRFSOC_CLKC_PLL1_CFG0  0x0040
+#define SIRFSOC_CLKC_PLL2_CFG0  0x0044
+#define SIRFSOC_CLKC_PLL3_CFG0  0x0048
+#define SIRFSOC_CLKC_PLL1_CFG1  0x004c
+#define SIRFSOC_CLKC_PLL2_CFG1  0x0050
+#define SIRFSOC_CLKC_PLL3_CFG1  0x0054
+#define SIRFSOC_CLKC_PLL1_CFG2  0x0058
+#define SIRFSOC_CLKC_PLL2_CFG2  0x005c
+#define SIRFSOC_CLKC_PLL3_CFG2  0x0060
+#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
+#define SIRFSOC_USBPHY_PLL_POWERDOWN  BIT(1)
+#define SIRFSOC_USBPHY_PLL_BYPASS     BIT(2)
+#define SIRFSOC_USBPHY_PLL_LOCK       BIT(3)
+
+static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase;
+
+#define KHZ     1000
+#define MHZ     (KHZ * KHZ)
+
+/*
+ * SiRFprimaII clock controller
+ * - 2 oscillators: osc-26MHz, rtc-32.768KHz
+ * - 3 standard configurable plls: pll1, pll2 & pll3
+ * - 2 exclusive plls: usb phy pll and sata phy pll
+ * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
+ *     display and sdphy.
+ *     Each clock domain can select its own clock source from five clock sources,
+ *     X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
+ *     clock of the group clock.
+ *     - dsp domain: gps, mf
+ *     - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
+ *     - sys domain: security
+ */
+
+struct clk_pll {
+        struct clk_hw hw;
+        unsigned short regofs;  /* register offset */
+};
+
+#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
+
+struct clk_dmn {
+        struct clk_hw hw;
+        signed char enable_bit; /* enable bit: 0 ~ 63 */
+        unsigned short regofs;  /* register offset */
+};
+
+#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
+
+struct clk_std {
+        struct clk_hw hw;
+        signed char enable_bit; /* enable bit: 0 ~ 63 */
+};
+
+#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
+
+static int std_clk_is_enabled(struct clk_hw *hw);
+static int std_clk_enable(struct clk_hw *hw);
+static void std_clk_disable(struct clk_hw *hw);
+
+static inline unsigned long clkc_readl(unsigned reg)
+{
+        return readl(sirfsoc_clk_vbase + reg);
+}
+
+static inline void clkc_writel(u32 val, unsigned reg)
+{
+        writel(val, sirfsoc_clk_vbase + reg);
+}
+
+/*
+ * std pll
+ */
+
+static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
+        unsigned long parent_rate)
+{
+        unsigned long fin = parent_rate;
+        struct clk_pll *clk = to_pllclk(hw);
+        u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
+                SIRFSOC_CLKC_PLL1_CFG0;
+
+        if (clkc_readl(regcfg2) & BIT(2)) {
+                /* pll bypass mode */
+                return fin;
+        } else {
+                /* fout = fin * nf / nr / od */
+                u32 cfg0 = clkc_readl(clk->regofs);
+                u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
+                u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
+                u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
+                WARN_ON(fin % MHZ);
+                return fin / MHZ * nf / nr / od * MHZ;
+        }
+}
+
+static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+        unsigned long *parent_rate)
+{
+        unsigned long fin, nf, nr, od;
+
+        /*
+         * fout = fin * nf / (nr * od);
+         * set od = 1, nr = fin/MHz, so fout = nf * MHz
+         */
+        rate = rate - rate % MHZ;
+
+        nf = rate / MHZ;
+        if (nf > BIT(13))
+                nf = BIT(13);
+        if (nf < 1)
+                nf = 1;
+
+        fin = *parent_rate;
+
+        nr = fin / MHZ;
+        if (nr > BIT(6))
+                nr = BIT(6);
+        od = 1;
+
+        return fin * nf / (nr * od);
+}
+
+static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+        unsigned long parent_rate)
+{
+        struct clk_pll *clk = to_pllclk(hw);
+        unsigned long fin, nf, nr, od, reg;
+
+        /*
+         * fout = fin * nf / (nr * od);
+         * set od = 1, nr = fin/MHz, so fout = nf * MHz
+         */
+
+        nf = rate / MHZ;
+        if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
+                return -EINVAL;
+
+        fin = parent_rate;
+        BUG_ON(fin < MHZ);
+
+        nr = fin / MHZ;
+        BUG_ON((fin % MHZ) || nr > BIT(6));
+
+        od = 1;
+
+        reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
+        clkc_writel(reg, clk->regofs);
+
+        reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
+        clkc_writel((nf >> 1) - 1, reg);
+
+        reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
+        while (!(clkc_readl(reg) & BIT(6)))
+                cpu_relax();
+
+        return 0;
+}
+
+static struct clk_ops std_pll_ops = {
+        .recalc_rate = pll_clk_recalc_rate,
+        .round_rate = pll_clk_round_rate,
+        .set_rate = pll_clk_set_rate,
+};
+
+static const char *pll_clk_parents[] = {
+        "osc",
+};
+
+static struct clk_init_data clk_pll1_init = {
+        .name = "pll1",
+        .ops = &std_pll_ops,
+        .parent_names = pll_clk_parents,
+        .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_init_data clk_pll2_init = {
+        .name = "pll2",
+        .ops = &std_pll_ops,
+        .parent_names = pll_clk_parents,
+        .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_init_data clk_pll3_init = {
+        .name = "pll3",
+        .ops = &std_pll_ops,
+        .parent_names = pll_clk_parents,
+        .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_pll clk_pll1 = {
+        .regofs = SIRFSOC_CLKC_PLL1_CFG0,
+        .hw = {
+                .init = &clk_pll1_init,
+        },
+};
+
+static struct clk_pll clk_pll2 = {
+        .regofs = SIRFSOC_CLKC_PLL2_CFG0,
+        .hw = {
+                .init = &clk_pll2_init,
+        },
+};
+
+static struct clk_pll clk_pll3 = {
+        .regofs = SIRFSOC_CLKC_PLL3_CFG0,
+        .hw = {
+                .init = &clk_pll3_init,
+        },
+};
+
+/*
+ * usb uses specified pll
+ */
+
+static int usb_pll_clk_enable(struct clk_hw *hw)
+{
+        u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+        reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+        writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+        while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
+                        SIRFSOC_USBPHY_PLL_LOCK))
+                cpu_relax();
+
+        return 0;
+}
+
+static void usb_pll_clk_disable(struct clk_hw *clk)
+{
+        u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+        reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+        writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+}
+
+static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+        u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+        return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
+}
+
+static struct clk_ops usb_pll_ops = {
+        .enable = usb_pll_clk_enable,
+        .disable = usb_pll_clk_disable,
+        .recalc_rate = usb_pll_clk_recalc_rate,
+};
+
+static struct clk_init_data clk_usb_pll_init = {
+        .name = "usb_pll",
+        .ops = &usb_pll_ops,
+        .parent_names = pll_clk_parents,
+        .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_hw usb_pll_clk_hw = {
+        .init = &clk_usb_pll_init,
+};
+
+/*
+ * clock domains - cpu, mem, sys/io, dsp, gfx
+ */
+
+static const char *dmn_clk_parents[] = {
+        "rtc",
+        "osc",
+        "pll1",
+        "pll2",
+        "pll3",
+};
+
+static u8 dmn_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_dmn *clk = to_dmnclk(hw);
+        u32 cfg = clkc_readl(clk->regofs);
+
+        /* parent of io domain can only be pll3 */
+        if (strcmp(hw->init->name, "io") == 0)
+                return 4;
+
+        WARN_ON((cfg & (BIT(3) - 1)) > 4);
+
+        return cfg & (BIT(3) - 1);
+}
+
+static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
+{
+        struct clk_dmn *clk = to_dmnclk(hw);
+        u32 cfg = clkc_readl(clk->regofs);
+
+        /* parent of io domain can only be pll3 */
+        if (strcmp(hw->init->name, "io") == 0)
+                return -EINVAL;
+
+        cfg &= ~(BIT(3) - 1);
+        clkc_writel(cfg | parent, clk->regofs);
+        /* BIT(3) - switching status: 1 - busy, 0 - done */
+        while (clkc_readl(clk->regofs) & BIT(3))
+                cpu_relax();
+
+        return 0;
+}
+
+static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
+        unsigned long parent_rate)
+
+{
+        unsigned long fin = parent_rate;
+        struct clk_dmn *clk = to_dmnclk(hw);
+
+        u32 cfg = clkc_readl(clk->regofs);
+
+        if (cfg & BIT(24)) {
+                /* fcd bypass mode */
+                return fin;
+        } else {
+                /*
+                 * wait count: bit[19:16], hold count: bit[23:20]
+                 */
+                u32 wait = (cfg >> 16) & (BIT(4) - 1);
+                u32 hold = (cfg >> 20) & (BIT(4) - 1);
+
+                return fin / (wait + hold + 2);
+        }
+}
+
+static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+        unsigned long *parent_rate)
+{
+        unsigned long fin;
+        unsigned ratio, wait, hold;
+        unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
+
+        fin = *parent_rate;
+        ratio = fin / rate;
+
+        if (ratio < 2)
+                ratio = 2;
+        if (ratio > BIT(bits + 1))
+                ratio = BIT(bits + 1);
+
+        wait = (ratio >> 1) - 1;
+        hold = ratio - wait - 2;
+
+        return fin / (wait + hold + 2);
+}
+
+static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+        unsigned long parent_rate)
+{
+        struct clk_dmn *clk = to_dmnclk(hw);
+        unsigned long fin;
+        unsigned ratio, wait, hold, reg;
+        unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
+
+        fin = parent_rate;
+        ratio = fin / rate;
+
+        if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
+                return -EINVAL;
+
+        WARN_ON(fin % rate);
+
+        wait = (ratio >> 1) - 1;
+        hold = ratio - wait - 2;
+
+        reg = clkc_readl(clk->regofs);
+        reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
+        reg |= (wait << 16) | (hold << 20) | BIT(25);
+        clkc_writel(reg, clk->regofs);
+
+        /* waiting FCD been effective */
+        while (clkc_readl(clk->regofs) & BIT(25))
+                cpu_relax();
+
+        return 0;
+}
+
+static struct clk_ops msi_ops = {
+        .set_rate = dmn_clk_set_rate,
+        .round_rate = dmn_clk_round_rate,
+        .recalc_rate = dmn_clk_recalc_rate,
+        .set_parent = dmn_clk_set_parent,
+        .get_parent = dmn_clk_get_parent,
+};
+
+static struct clk_init_data clk_mem_init = {
+        .name = "mem",
+        .ops = &msi_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mem = {
+        .regofs = SIRFSOC_CLKC_MEM_CFG,
+        .hw = {
+                .init = &clk_mem_init,
+        },
+};
+
+static struct clk_init_data clk_sys_init = {
+        .name = "sys",
+        .ops = &msi_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+        .flags = CLK_SET_RATE_GATE,
+};
+
+static struct clk_dmn clk_sys = {
+        .regofs = SIRFSOC_CLKC_SYS_CFG,
+        .hw = {
+                .init = &clk_sys_init,
+        },
+};
+
+static struct clk_init_data clk_io_init = {
+        .name = "io",
+        .ops = &msi_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_io = {
+        .regofs = SIRFSOC_CLKC_IO_CFG,
+        .hw = {
+                .init = &clk_io_init,
+        },
+};
+
+static struct clk_ops cpu_ops = {
+        .set_parent = dmn_clk_set_parent,
+        .get_parent = dmn_clk_get_parent,
+};
+
+static struct clk_init_data clk_cpu_init = {
+        .name = "cpu",
+        .ops = &cpu_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+        .flags = CLK_SET_RATE_PARENT,
+};
+
+static struct clk_dmn clk_cpu = {
+        .regofs = SIRFSOC_CLKC_CPU_CFG,
+        .hw = {
+                .init = &clk_cpu_init,
+        },
+};
+
+static struct clk_ops dmn_ops = {
+        .is_enabled = std_clk_is_enabled,
+        .enable = std_clk_enable,
+        .disable = std_clk_disable,
+        .set_rate = dmn_clk_set_rate,
+        .round_rate = dmn_clk_round_rate,
+        .recalc_rate = dmn_clk_recalc_rate,
+        .set_parent = dmn_clk_set_parent,
+        .get_parent = dmn_clk_get_parent,
+};
+
+/* dsp, gfx, mm, lcd and vpp domain */
+
+static struct clk_init_data clk_dsp_init = {
+        .name = "dsp",
+        .ops = &dmn_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_dsp = {
+        .regofs = SIRFSOC_CLKC_DSP_CFG,
+        .enable_bit = 0,
+        .hw = {
+                .init = &clk_dsp_init,
+        },
+};
+
+static struct clk_init_data clk_gfx_init = {
+        .name = "gfx",
+        .ops = &dmn_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_gfx = {
+        .regofs = SIRFSOC_CLKC_GFX_CFG,
+        .enable_bit = 8,
+        .hw = {
+                .init = &clk_gfx_init,
+        },
+};
+
+static struct clk_init_data clk_mm_init = {
+        .name = "mm",
+        .ops = &dmn_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mm = {
+        .regofs = SIRFSOC_CLKC_MM_CFG,
+        .enable_bit = 9,
+        .hw = {
+                .init = &clk_mm_init,
+        },
+};
+
+static struct clk_init_data clk_lcd_init = {
+        .name = "lcd",
+        .ops = &dmn_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_lcd = {
+        .regofs = SIRFSOC_CLKC_LCD_CFG,
+        .enable_bit = 10,
+        .hw = {
+                .init = &clk_lcd_init,
+        },
+};
+
+static struct clk_init_data clk_vpp_init = {
+        .name = "vpp",
+        .ops = &dmn_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_vpp = {
+        .regofs = SIRFSOC_CLKC_LCD_CFG,
+        .enable_bit = 11,
+        .hw = {
+                .init = &clk_vpp_init,
+        },
+};
+
+static struct clk_init_data clk_mmc01_init = {
+        .name = "mmc01",
+        .ops = &dmn_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mmc01 = {
+        .regofs = SIRFSOC_CLKC_MMC_CFG,
+        .enable_bit = 59,
+        .hw = {
+                .init = &clk_mmc01_init,
+        },
+};
+
+static struct clk_init_data clk_mmc23_init = {
+        .name = "mmc23",
+        .ops = &dmn_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mmc23 = {
+        .regofs = SIRFSOC_CLKC_MMC_CFG,
+        .enable_bit = 60,
+        .hw = {
+                .init = &clk_mmc23_init,
+        },
+};
+
+static struct clk_init_data clk_mmc45_init = {
+        .name = "mmc45",
+        .ops = &dmn_ops,
+        .parent_names = dmn_clk_parents,
+        .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mmc45 = {
+        .regofs = SIRFSOC_CLKC_MMC_CFG,
+        .enable_bit = 61,
+        .hw = {
+                .init = &clk_mmc45_init,
+        },
+};
+
+/*
+ * peripheral controllers in io domain
+ */
+
+static int std_clk_is_enabled(struct clk_hw *hw)
+{
+        u32 reg;
+        int bit;
+        struct clk_std *clk = to_stdclk(hw);
+
+        bit = clk->enable_bit % 32;
+        reg = clk->enable_bit / 32;
+        reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
+
+        return !!(clkc_readl(reg) & BIT(bit));
+}
+
+static int std_clk_enable(struct clk_hw *hw)
+{
+        u32 val, reg;
+        int bit;
+        struct clk_std *clk = to_stdclk(hw);
+
+        BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
+
+        bit = clk->enable_bit % 32;
+        reg = clk->enable_bit / 32;
+        reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
+
+        val = clkc_readl(reg) | BIT(bit);
+        clkc_writel(val, reg);
+        return 0;
+}
+
+static void std_clk_disable(struct clk_hw *hw)
+{
+        u32 val, reg;
+        int bit;
+        struct clk_std *clk = to_stdclk(hw);
+
+        BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
+
+        bit = clk->enable_bit % 32;
+        reg = clk->enable_bit / 32;
+        reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
+
+        val = clkc_readl(reg) & ~BIT(bit);
+        clkc_writel(val, reg);
+}
+
+static const char *std_clk_io_parents[] = {
+        "io",
+};
+
+static struct clk_ops ios_ops = {
+        .is_enabled = std_clk_is_enabled,
+        .enable = std_clk_enable,
+        .disable = std_clk_disable,
+};
+
+static struct clk_init_data clk_dmac0_init = {
+        .name = "dmac0",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_dmac0 = {
+        .enable_bit = 32,
+        .hw = {
+                .init = &clk_dmac0_init,
+        },
+};
+
+static struct clk_init_data clk_dmac1_init = {
+        .name = "dmac1",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_dmac1 = {
+        .enable_bit = 33,
+        .hw = {
+                .init = &clk_dmac1_init,
+        },
+};
+
+static struct clk_init_data clk_nand_init = {
+        .name = "nand",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_nand = {
+        .enable_bit = 34,
+        .hw = {
+                .init = &clk_nand_init,
+        },
+};
+
+static struct clk_init_data clk_audio_init = {
+        .name = "audio",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_audio = {
+        .enable_bit = 35,
+        .hw = {
+                .init = &clk_audio_init,
+        },
+};
+
+static struct clk_init_data clk_uart0_init = {
+        .name = "uart0",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart0 = {
+        .enable_bit = 36,
+        .hw = {
+                .init = &clk_uart0_init,
+        },
+};
+
+static struct clk_init_data clk_uart1_init = {
+        .name = "uart1",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart1 = {
+        .enable_bit = 37,
+        .hw = {
+                .init = &clk_uart1_init,
+        },
+};
+
+static struct clk_init_data clk_uart2_init = {
+        .name = "uart2",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart2 = {
+        .enable_bit = 38,
+        .hw = {
+                .init = &clk_uart2_init,
+        },
+};
+
+static struct clk_init_data clk_usp0_init = {
+        .name = "usp0",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp0 = {
+        .enable_bit = 39,
+        .hw = {
+                .init = &clk_usp0_init,
+        },
+};
+
+static struct clk_init_data clk_usp1_init = {
+        .name = "usp1",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp1 = {
+        .enable_bit = 40,
+        .hw = {
+                .init = &clk_usp1_init,
+        },
+};
+
+static struct clk_init_data clk_usp2_init = {
+        .name = "usp2",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp2 = {
+        .enable_bit = 41,
+        .hw = {
+                .init = &clk_usp2_init,
+        },
+};
+
+static struct clk_init_data clk_vip_init = {
+        .name = "vip",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_vip = {
+        .enable_bit = 42,
+        .hw = {
+                .init = &clk_vip_init,
+        },
+};
+
+static struct clk_init_data clk_spi0_init = {
+        .name = "spi0",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi0 = {
+        .enable_bit = 43,
+        .hw = {
+                .init = &clk_spi0_init,
+        },
+};
+
+static struct clk_init_data clk_spi1_init = {
+        .name = "spi1",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi1 = {
+        .enable_bit = 44,
+        .hw = {
+                .init = &clk_spi1_init,
+        },
+};
+
+static struct clk_init_data clk_tsc_init = {
+        .name = "tsc",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_tsc = {
+        .enable_bit = 45,
+        .hw = {
+                .init = &clk_tsc_init,
+        },
+};
+
+static struct clk_init_data clk_i2c0_init = {
+        .name = "i2c0",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c0 = {
+        .enable_bit = 46,
+        .hw = {
+                .init = &clk_i2c0_init,
+        },
+};
+
+static struct clk_init_data clk_i2c1_init = {
+        .name = "i2c1",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c1 = {
+        .enable_bit = 47,
+        .hw = {
+                .init = &clk_i2c1_init,
+        },
+};
+
+static struct clk_init_data clk_pwmc_init = {
+        .name = "pwmc",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pwmc = {
+        .enable_bit = 48,
+        .hw = {
+                .init = &clk_pwmc_init,
+        },
+};
+
+static struct clk_init_data clk_efuse_init = {
+        .name = "efuse",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_efuse = {
+        .enable_bit = 49,
+        .hw = {
+                .init = &clk_efuse_init,
+        },
+};
+
+static struct clk_init_data clk_pulse_init = {
+        .name = "pulse",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pulse = {
+        .enable_bit = 50,
+        .hw = {
+                .init = &clk_pulse_init,
+        },
+};
+
+static const char *std_clk_dsp_parents[] = {
+        "dsp",
+};
+
+static struct clk_init_data clk_gps_init = {
+        .name = "gps",
+        .ops = &ios_ops,
+        .parent_names = std_clk_dsp_parents,
+        .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
+};
+
+static struct clk_std clk_gps = {
+        .enable_bit = 1,
+        .hw = {
+                .init = &clk_gps_init,
+        },
+};
+
+static struct clk_init_data clk_mf_init = {
+        .name = "mf",
+        .ops = &ios_ops,
+        .parent_names = std_clk_io_parents,
+        .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_mf = {
+        .enable_bit = 2,
+        .hw = {
+                .init = &clk_mf_init,
+        },
+};
+
+static const char *std_clk_sys_parents[] = {
+        "sys",
+};
+
+static struct clk_init_data clk_security_init = {
+        .name = "mf",
+        .ops = &ios_ops,
+        .parent_names = std_clk_sys_parents,
+        .num_parents = ARRAY_SIZE(std_clk_sys_parents),
+};
+
+static struct clk_std clk_security = {
+        .enable_bit = 19,
+        .hw = {
+                .init = &clk_security_init,
+        },
+};
+
+static const char *std_clk_usb_parents[] = {
+        "usb_pll",
+};
+
+static struct clk_init_data clk_usb0_init = {
+        .name = "usb0",
+        .ops = &ios_ops,
+        .parent_names = std_clk_usb_parents,
+        .num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb0 = {
+        .enable_bit = 16,
+        .hw = {
+                .init = &clk_usb0_init,
+        },
+};
+
+static struct clk_init_data clk_usb1_init = {
+        .name = "usb1",
+        .ops = &ios_ops,
+        .parent_names = std_clk_usb_parents,
+        .num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb1 = {
+        .enable_bit = 17,
+        .hw = {
+                .init = &clk_usb1_init,
+        },
+};
+
+static struct of_device_id clkc_ids[] = {
+        { .compatible = "sirf,prima2-clkc" },
+        {},
+};
+
+static struct of_device_id rsc_ids[] = {
+        { .compatible = "sirf,prima2-rsc" },
+        {},
+};
+
+void __init sirfsoc_of_clk_init(void)
+{
+        struct clk *clk;
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, clkc_ids);
+        if (!np)
+                panic("unable to find compatible clkc node in dtb\n");
+
+        sirfsoc_clk_vbase = of_iomap(np, 0);
+        if (!sirfsoc_clk_vbase)
+                panic("unable to map clkc registers\n");
+
+        of_node_put(np);
+
+        np = of_find_matching_node(NULL, rsc_ids);
+        if (!np)
+                panic("unable to find compatible rsc node in dtb\n");
+
+        sirfsoc_rsc_vbase = of_iomap(np, 0);
+        if (!sirfsoc_rsc_vbase)
+                panic("unable to map rsc registers\n");
+
+        of_node_put(np);
+
+
+        /* These are always available (RTC and 26MHz OSC)*/
+        clk = clk_register_fixed_rate(NULL, "rtc", NULL,
+                CLK_IS_ROOT, 32768);
+        BUG_ON(!clk);
+        clk = clk_register_fixed_rate(NULL, "osc", NULL,
+                CLK_IS_ROOT, 26000000);
+        BUG_ON(!clk);
+
+        clk = clk_register(NULL, &clk_pll1.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_pll2.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_pll3.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_mem.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_sys.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_security.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b8030000.security");
+        clk = clk_register(NULL, &clk_dsp.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_gps.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "a8010000.gps");
+        clk = clk_register(NULL, &clk_mf.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_io.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "io");
+        clk = clk_register(NULL, &clk_cpu.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "cpu");
+        clk = clk_register(NULL, &clk_uart0.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0050000.uart");
+        clk = clk_register(NULL, &clk_uart1.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0060000.uart");
+        clk = clk_register(NULL, &clk_uart2.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0070000.uart");
+        clk = clk_register(NULL, &clk_tsc.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0110000.tsc");
+        clk = clk_register(NULL, &clk_i2c0.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b00e0000.i2c");
+        clk = clk_register(NULL, &clk_i2c1.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b00f0000.i2c");
+        clk = clk_register(NULL, &clk_spi0.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b00d0000.spi");
+        clk = clk_register(NULL, &clk_spi1.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0170000.spi");
+        clk = clk_register(NULL, &clk_pwmc.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0130000.pwm");
+        clk = clk_register(NULL, &clk_efuse.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0140000.efusesys");
+        clk = clk_register(NULL, &clk_pulse.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0150000.pulsec");
+        clk = clk_register(NULL, &clk_dmac0.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
+        clk = clk_register(NULL, &clk_dmac1.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
+        clk = clk_register(NULL, &clk_nand.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0030000.nand");
+        clk = clk_register(NULL, &clk_audio.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0040000.audio");
+        clk = clk_register(NULL, &clk_usp0.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0080000.usp");
+        clk = clk_register(NULL, &clk_usp1.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b0090000.usp");
+        clk = clk_register(NULL, &clk_usp2.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b00a0000.usp");
+        clk = clk_register(NULL, &clk_vip.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b00c0000.vip");
+        clk = clk_register(NULL, &clk_gfx.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "98000000.graphics");
+        clk = clk_register(NULL, &clk_mm.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "a0000000.multimedia");
+        clk = clk_register(NULL, &clk_lcd.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "90010000.display");
+        clk = clk_register(NULL, &clk_vpp.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "90020000.vpp");
+        clk = clk_register(NULL, &clk_mmc01.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_mmc23.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_mmc45.hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &usb_pll_clk_hw);
+        BUG_ON(!clk);
+        clk = clk_register(NULL, &clk_usb0.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b00e0000.usb");
+        clk = clk_register(NULL, &clk_usb1.hw);
+        BUG_ON(!clk);
+        clk_register_clkdev(clk, NULL, "b00f0000.usb");
+}
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index efdfd009c270..56e4495ebeb1 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -558,25 +558,6 @@ int clk_enable(struct clk *clk)
 EXPORT_SYMBOL_GPL(clk_enable);
 
 /**
- * clk_get_rate - return the rate of clk
- * @clk: the clk whose rate is being returned
- *
- * Simply returns the cached rate of the clk.  Does not query the hardware.  If
- * clk is NULL then returns 0.
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long rate;
-
-        mutex_lock(&prepare_lock);
-        rate = __clk_get_rate(clk);
-        mutex_unlock(&prepare_lock);
-
-        return rate;
-}
-EXPORT_SYMBOL_GPL(clk_get_rate);
-
-/**
  * __clk_round_rate - round the given rate for a clk
  * @clk: round the rate of this clock
  *
@@ -702,6 +683,30 @@ static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
 }
 
 /**
+ * clk_get_rate - return the rate of clk
+ * @clk: the clk whose rate is being returned
+ *
+ * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
+ * is set, which means a recalc_rate will be issued.
+ * If clk is NULL then returns 0.
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long rate;
+
+        mutex_lock(&prepare_lock);
+
+        if (clk && (clk->flags & CLK_GET_RATE_NOCACHE))
+                __clk_recalc_rates(clk, 0);
+
+        rate = __clk_get_rate(clk);
+        mutex_unlock(&prepare_lock);
+
+        return rate;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/**
  * __clk_speculate_rates
  * @clk: first clk in the subtree
  * @parent_rate: the "future" rate of clk's parent
@@ -1582,6 +1587,20 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
 }
 EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
 
+struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
+{
+        struct clk_onecell_data *clk_data = data;
+        unsigned int idx = clkspec->args[0];
+
+        if (idx >= clk_data->clk_num) {
+                pr_err("%s: invalid clock index %d\n", __func__, idx);
+                return ERR_PTR(-EINVAL);
+        }
+
+        return clk_data->clks[idx];
+}
+EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
+
 /**
  * of_clk_add_provider() - Register a clock provider for a node
  * @np: Device node pointer associated with clock provider
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
new file mode 100644
index 000000000000..392d78044ce3
--- /dev/null
+++ b/drivers/clk/mmp/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for mmp specific clk
+#
+
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o
+
+obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
+obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
+obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c
new file mode 100644
index 000000000000..d14120eaa71f
--- /dev/null
+++ b/drivers/clk/mmp/clk-apbc.c
@@ -0,0 +1,152 @@
+/*
+ * mmp APB clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1 << 0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1 << 1)  /* Functional Clock Enable */
+#define APBC_RST        (1 << 2)  /* Reset Generation */
+#define APBC_POWER      (1 << 7)  /* Reset Generation */
+
+#define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw)
+struct clk_apbc {
+        struct clk_hw           hw;
+        void __iomem            *base;
+        unsigned int            delay;
+        unsigned int            flags;
+        spinlock_t              *lock;
+};
+
+static int clk_apbc_prepare(struct clk_hw *hw)
+{
+        struct clk_apbc *apbc = to_clk_apbc(hw);
+        unsigned int data;
+        unsigned long flags = 0;
+
+        /*
+         * It may share same register as MUX clock,
+         * and it will impact FNCLK enable. Spinlock is needed
+         */
+        if (apbc->lock)
+                spin_lock_irqsave(apbc->lock, flags);
+
+        data = readl_relaxed(apbc->base);
+        if (apbc->flags & APBC_POWER_CTRL)
+                data |= APBC_POWER;
+        data |= APBC_FNCLK;
+        writel_relaxed(data, apbc->base);
+
+        if (apbc->lock)
+                spin_unlock_irqrestore(apbc->lock, flags);
+
+        udelay(apbc->delay);
+
+        if (apbc->lock)
+                spin_lock_irqsave(apbc->lock, flags);
+
+        data = readl_relaxed(apbc->base);
+        data |= APBC_APBCLK;
+        writel_relaxed(data, apbc->base);
+
+        if (apbc->lock)
+                spin_unlock_irqrestore(apbc->lock, flags);
+
+        udelay(apbc->delay);
+
+        if (!(apbc->flags & APBC_NO_BUS_CTRL)) {
+                if (apbc->lock)
+                        spin_lock_irqsave(apbc->lock, flags);
+
+                data = readl_relaxed(apbc->base);
+                data &= ~APBC_RST;
+                writel_relaxed(data, apbc->base);
+
+                if (apbc->lock)
+                        spin_unlock_irqrestore(apbc->lock, flags);
+        }
+
+        return 0;
+}
+
+static void clk_apbc_unprepare(struct clk_hw *hw)
+{
+        struct clk_apbc *apbc = to_clk_apbc(hw);
+        unsigned long data;
+        unsigned long flags = 0;
+
+        if (apbc->lock)
+                spin_lock_irqsave(apbc->lock, flags);
+
+        data = readl_relaxed(apbc->base);
+        if (apbc->flags & APBC_POWER_CTRL)
+                data &= ~APBC_POWER;
+        data &= ~APBC_FNCLK;
+        writel_relaxed(data, apbc->base);
+
+        if (apbc->lock)
+                spin_unlock_irqrestore(apbc->lock, flags);
+
+        udelay(10);
+
+        if (apbc->lock)
+                spin_lock_irqsave(apbc->lock, flags);
+
+        data = readl_relaxed(apbc->base);
+        data &= ~APBC_APBCLK;
+        writel_relaxed(data, apbc->base);
+
+        if (apbc->lock)
+                spin_unlock_irqrestore(apbc->lock, flags);
+}
+
+struct clk_ops clk_apbc_ops = {
+        .prepare = clk_apbc_prepare,
+        .unprepare = clk_apbc_unprepare,
+};
+
+struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name,
+                void __iomem *base, unsigned int delay,
+                unsigned int apbc_flags, spinlock_t *lock)
+{
+        struct clk_apbc *apbc;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        apbc = kzalloc(sizeof(*apbc), GFP_KERNEL);
+        if (!apbc)
+                return NULL;
+
+        init.name = name;
+        init.ops = &clk_apbc_ops;
+        init.flags = CLK_SET_RATE_PARENT;
+        init.parent_names = (parent_name ? &parent_name : NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+
+        apbc->base = base;
+        apbc->delay = delay;
+        apbc->flags = apbc_flags;
+        apbc->lock = lock;
+        apbc->hw.init = &init;
+
+        clk = clk_register(NULL, &apbc->hw);
+        if (IS_ERR(clk))
+                kfree(apbc);
+
+        return clk;
+}
diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c
new file mode 100644
index 000000000000..abe182b2377f
--- /dev/null
+++ b/drivers/clk/mmp/clk-apmu.c
@@ -0,0 +1,97 @@
+/*
+ * mmp AXI peripharal clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+#define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
+struct clk_apmu {
+        struct clk_hw   hw;
+        void __iomem    *base;
+        u32             rst_mask;
+        u32             enable_mask;
+        spinlock_t      *lock;
+};
+
+static int clk_apmu_enable(struct clk_hw *hw)
+{
+        struct clk_apmu *apmu = to_clk_apmu(hw);
+        unsigned long data;
+        unsigned long flags = 0;
+
+        if (apmu->lock)
+                spin_lock_irqsave(apmu->lock, flags);
+
+        data = readl_relaxed(apmu->base) | apmu->enable_mask;
+        writel_relaxed(data, apmu->base);
+
+        if (apmu->lock)
+                spin_unlock_irqrestore(apmu->lock, flags);
+
+        return 0;
+}
+
+static void clk_apmu_disable(struct clk_hw *hw)
+{
+        struct clk_apmu *apmu = to_clk_apmu(hw);
+        unsigned long data;
+        unsigned long flags = 0;
+
+        if (apmu->lock)
+                spin_lock_irqsave(apmu->lock, flags);
+
+        data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
+        writel_relaxed(data, apmu->base);
+
+        if (apmu->lock)
+                spin_unlock_irqrestore(apmu->lock, flags);
+}
+
+struct clk_ops clk_apmu_ops = {
+        .enable = clk_apmu_enable,
+        .disable = clk_apmu_disable,
+};
+
+struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name,
+                void __iomem *base, u32 enable_mask, spinlock_t *lock)
+{
+        struct clk_apmu *apmu;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        apmu = kzalloc(sizeof(*apmu), GFP_KERNEL);
+        if (!apmu)
+                return NULL;
+
+        init.name = name;
+        init.ops = &clk_apmu_ops;
+        init.flags = CLK_SET_RATE_PARENT;
+        init.parent_names = (parent_name ? &parent_name : NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+
+        apmu->base = base;
+        apmu->enable_mask = enable_mask;
+        apmu->lock = lock;
+        apmu->hw.init = &init;
+
+        clk = clk_register(NULL, &apmu->hw);
+
+        if (IS_ERR(clk))
+                kfree(apmu);
+
+        return clk;
+}
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
new file mode 100644
index 000000000000..80c1dd15d15c
--- /dev/null
+++ b/drivers/clk/mmp/clk-frac.c
@@ -0,0 +1,153 @@
+/*
+ * mmp factor clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include "clk.h"
+/*
+ * It is M/N clock
+ *
+ * Fout from synthesizer can be given from two equations:
+ * numerator/denominator = Fin / (Fout * factor)
+ */
+
+#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
+struct clk_factor {
+        struct clk_hw           hw;
+        void __iomem            *base;
+        struct clk_factor_masks *masks;
+        struct clk_factor_tbl   *ftbl;
+        unsigned int            ftbl_cnt;
+};
+
+static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
+                unsigned long *prate)
+{
+        struct clk_factor *factor = to_clk_factor(hw);
+        unsigned long rate = 0, prev_rate;
+        int i;
+
+        for (i = 0; i < factor->ftbl_cnt; i++) {
+                prev_rate = rate;
+                rate = (((*prate / 10000) * factor->ftbl[i].num) /
+                        (factor->ftbl[i].den * factor->masks->factor)) * 10000;
+                if (rate > drate)
+                        break;
+        }
+        if (i == 0)
+                return rate;
+        else
+                return prev_rate;
+}
+
+static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_factor *factor = to_clk_factor(hw);
+        struct clk_factor_masks *masks = factor->masks;
+        unsigned int val, num, den;
+
+        val = readl_relaxed(factor->base);
+
+        /* calculate numerator */
+        num = (val >> masks->num_shift) & masks->num_mask;
+
+        /* calculate denominator */
+        den = (val >> masks->den_shift) & masks->num_mask;
+
+        if (!den)
+                return 0;
+
+        return (((parent_rate / 10000)  * den) /
+                        (num * factor->masks->factor)) * 10000;
+}
+
+/* Configures new clock rate*/
+static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
+                                unsigned long prate)
+{
+        struct clk_factor *factor = to_clk_factor(hw);
+        struct clk_factor_masks *masks = factor->masks;
+        int i;
+        unsigned long val;
+        unsigned long prev_rate, rate = 0;
+
+        for (i = 0; i < factor->ftbl_cnt; i++) {
+                prev_rate = rate;
+                rate = (((prate / 10000) * factor->ftbl[i].num) /
+                        (factor->ftbl[i].den * factor->masks->factor)) * 10000;
+                if (rate > drate)
+                        break;
+        }
+        if (i > 0)
+                i--;
+
+        val = readl_relaxed(factor->base);
+
+        val &= ~(masks->num_mask << masks->num_shift);
+        val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift;
+
+        val &= ~(masks->den_mask << masks->den_shift);
+        val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift;
+
+        writel_relaxed(val, factor->base);
+
+        return 0;
+}
+
+static struct clk_ops clk_factor_ops = {
+        .recalc_rate = clk_factor_recalc_rate,
+        .round_rate = clk_factor_round_rate,
+        .set_rate = clk_factor_set_rate,
+};
+
+struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
+                unsigned long flags, void __iomem *base,
+                struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
+                unsigned int ftbl_cnt)
+{
+        struct clk_factor *factor;
+        struct clk_init_data init;
+        struct clk *clk;
+
+        if (!masks) {
+                pr_err("%s: must pass a clk_factor_mask\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        factor = kzalloc(sizeof(*factor), GFP_KERNEL);
+        if (!factor) {
+                pr_err("%s: could not allocate factor  clk\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        /* struct clk_aux assignments */
+        factor->base = base;
+        factor->masks = masks;
+        factor->ftbl = ftbl;
+        factor->ftbl_cnt = ftbl_cnt;
+        factor->hw.init = &init;
+
+        init.name = name;
+        init.ops = &clk_factor_ops;
+        init.flags = flags;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        clk = clk_register(NULL, &factor->hw);
+        if (IS_ERR_OR_NULL(clk))
+                kfree(factor);
+
+        return clk;
+}
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
new file mode 100644
index 000000000000..ade435820c7e
--- /dev/null
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -0,0 +1,449 @@
+/*
+ * mmp2 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC        0x0
+#define APBC_TWSI0      0x4
+#define APBC_TWSI1      0x8
+#define APBC_TWSI2      0xc
+#define APBC_TWSI3      0x10
+#define APBC_TWSI4      0x7c
+#define APBC_TWSI5      0x80
+#define APBC_KPC        0x18
+#define APBC_UART0      0x2c
+#define APBC_UART1      0x30
+#define APBC_UART2      0x34
+#define APBC_UART3      0x88
+#define APBC_GPIO       0x38
+#define APBC_PWM0       0x3c
+#define APBC_PWM1       0x40
+#define APBC_PWM2       0x44
+#define APBC_PWM3       0x48
+#define APBC_SSP0       0x50
+#define APBC_SSP1       0x54
+#define APBC_SSP2       0x58
+#define APBC_SSP3       0x5c
+#define APMU_SDH0       0x54
+#define APMU_SDH1       0x58
+#define APMU_SDH2       0xe8
+#define APMU_SDH3       0xec
+#define APMU_USB        0x5c
+#define APMU_DISP0      0x4c
+#define APMU_DISP1      0x110
+#define APMU_CCIC0      0x50
+#define APMU_CCIC1      0xf4
+#define MPMU_UART_PLL   0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct clk_factor_masks uart_factor_masks = {
+        .factor = 2,
+        .num_mask = 0x1fff,
+        .den_mask = 0x1fff,
+        .num_shift = 16,
+        .den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+        {.num = 14634, .den = 2165},    /*14.745MHZ */
+        {.num = 3521, .den = 689},      /*19.23MHZ */
+        {.num = 9679, .den = 5728},     /*58.9824MHZ */
+        {.num = 15850, .den = 9451},    /*59.429MHZ */
+};
+
+static const char *uart_parent[] = {"uart_pll", "vctcxo"};
+static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
+static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
+static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
+
+void __init mmp2_clk_init(void)
+{
+        struct clk *clk;
+        struct clk *vctcxo;
+        void __iomem *mpmu_base;
+        void __iomem *apmu_base;
+        void __iomem *apbc_base;
+
+        mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+        if (mpmu_base == NULL) {
+                pr_err("error to ioremap MPMU base\n");
+                return;
+        }
+
+        apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+        if (apmu_base == NULL) {
+                pr_err("error to ioremap APMU base\n");
+                return;
+        }
+
+        apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+        if (apbc_base == NULL) {
+                pr_err("error to ioremap APBC base\n");
+                return;
+        }
+
+        clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+        clk_register_clkdev(clk, "clk32", NULL);
+
+        vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+                                26000000);
+        clk_register_clkdev(vctcxo, "vctcxo", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
+                                800000000);
+        clk_register_clkdev(clk, "pll1", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
+                                480000000);
+        clk_register_clkdev(clk, "usb_pll", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT,
+                                960000000);
+        clk_register_clkdev(clk, "pll2", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_2", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_4", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_8", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_16", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
+                                CLK_SET_RATE_PARENT, 1, 5);
+        clk_register_clkdev(clk, "pll1_20", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
+                                CLK_SET_RATE_PARENT, 1, 3);
+        clk_register_clkdev(clk, "pll1_3", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_6", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_12", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll2_2", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll2_4", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll2_8", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll2_16", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
+                                CLK_SET_RATE_PARENT, 1, 3);
+        clk_register_clkdev(clk, "pll2_3", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll2_6", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll2_12", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "vctcxo_2", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "vctcxo_4", NULL);
+
+        clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+                                mpmu_base + MPMU_UART_PLL,
+                                &uart_factor_masks, uart_factor_tbl,
+                                ARRAY_SIZE(uart_factor_tbl));
+        clk_set_rate(clk, 14745600);
+        clk_register_clkdev(clk, "uart_pll", NULL);
+
+        clk = mmp_clk_register_apbc("twsi0", "vctcxo",
+                                apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
+
+        clk = mmp_clk_register_apbc("twsi1", "vctcxo",
+                                apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
+
+        clk = mmp_clk_register_apbc("twsi2", "vctcxo",
+                                apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
+
+        clk = mmp_clk_register_apbc("twsi3", "vctcxo",
+                                apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
+
+        clk = mmp_clk_register_apbc("twsi4", "vctcxo",
+                                apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
+
+        clk = mmp_clk_register_apbc("twsi5", "vctcxo",
+                                apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
+
+        clk = mmp_clk_register_apbc("gpio", "vctcxo",
+                                apbc_base + APBC_GPIO, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa-gpio");
+
+        clk = mmp_clk_register_apbc("kpc", "clk32",
+                                apbc_base + APBC_KPC, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa27x-keypad");
+
+        clk = mmp_clk_register_apbc("rtc", "clk32",
+                                apbc_base + APBC_RTC, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-rtc");
+
+        clk = mmp_clk_register_apbc("pwm0", "vctcxo",
+                                apbc_base + APBC_PWM0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
+
+        clk = mmp_clk_register_apbc("pwm1", "vctcxo",
+                                apbc_base + APBC_PWM1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
+
+        clk = mmp_clk_register_apbc("pwm2", "vctcxo",
+                                apbc_base + APBC_PWM2, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
+
+        clk = mmp_clk_register_apbc("pwm3", "vctcxo",
+                                apbc_base + APBC_PWM3, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
+
+        clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, vctcxo);
+        clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+        clk = mmp_clk_register_apbc("uart0", "uart0_mux",
+                                apbc_base + APBC_UART0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
+
+        clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, vctcxo);
+        clk_register_clkdev(clk, "uart_mux.1", NULL);
+
+        clk = mmp_clk_register_apbc("uart1", "uart1_mux",
+                                apbc_base + APBC_UART1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
+
+        clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, vctcxo);
+        clk_register_clkdev(clk, "uart_mux.2", NULL);
+
+        clk = mmp_clk_register_apbc("uart2", "uart2_mux",
+                                apbc_base + APBC_UART2, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
+
+        clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, vctcxo);
+        clk_register_clkdev(clk, "uart_mux.3", NULL);
+
+        clk = mmp_clk_register_apbc("uart3", "uart3_mux",
+                                apbc_base + APBC_UART3, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
+
+        clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+        clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
+                                apbc_base + APBC_SSP0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.0");
+
+        clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "ssp_mux.1", NULL);
+
+        clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
+                                apbc_base + APBC_SSP1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.1");
+
+        clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "ssp_mux.2", NULL);
+
+        clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
+                                apbc_base + APBC_SSP2, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.2");
+
+        clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "ssp_mux.3", NULL);
+
+        clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
+                                apbc_base + APBC_SSP3, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.3");
+
+        clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
+                                ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
+        clk_register_clkdev(clk, "sdh_mux", NULL);
+
+        clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
+                                10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+        clk_register_clkdev(clk, "sdh_div", NULL);
+
+        clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
+                                0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
+
+        clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
+                                0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
+
+        clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
+                                0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
+
+        clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
+                                0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
+
+        clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
+                                0x9, &clk_lock);
+        clk_register_clkdev(clk, "usb_clk", NULL);
+
+        clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
+                                ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
+        clk_register_clkdev(clk, "disp_mux.0", NULL);
+
+        clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
+                                8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+        clk_register_clkdev(clk, "disp_div.0", NULL);
+
+        clk = mmp_clk_register_apmu("disp0", "disp0_div",
+                                apmu_base + APMU_DISP0, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-disp.0");
+
+        clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
+                                apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
+        clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
+
+        clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
+                                apmu_base + APMU_DISP0, 0x1024, &clk_lock);
+        clk_register_clkdev(clk, "disp_sphy.0", NULL);
+
+        clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
+                                ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
+        clk_register_clkdev(clk, "disp_mux.1", NULL);
+
+        clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
+                                8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+        clk_register_clkdev(clk, "disp_div.1", NULL);
+
+        clk = mmp_clk_register_apmu("disp1", "disp1_div",
+                                apmu_base + APMU_DISP1, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-disp.1");
+
+        clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
+                                apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
+        clk_register_clkdev(clk, "ccic_arbiter", NULL);
+
+        clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+                                ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
+        clk_register_clkdev(clk, "ccic_mux.0", NULL);
+
+        clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+                                17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+        clk_register_clkdev(clk, "ccic_div.0", NULL);
+
+        clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
+                                apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
+
+        clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
+                                apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+        clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
+
+        clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+                                10, 5, 0, &clk_lock);
+        clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
+
+        clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+                                apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+        clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
+
+        clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
+                                ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
+        clk_register_clkdev(clk, "ccic_mux.1", NULL);
+
+        clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
+                                16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+        clk_register_clkdev(clk, "ccic_div.1", NULL);
+
+        clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
+                                apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
+
+        clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
+                                apmu_base + APMU_CCIC1, 0x24, &clk_lock);
+        clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
+
+        clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
+                                10, 5, 0, &clk_lock);
+        clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
+
+        clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
+                                apmu_base + APMU_CCIC1, 0x300, &clk_lock);
+        clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
+}
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
new file mode 100644
index 000000000000..e8d036c12cbf
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -0,0 +1,346 @@
+/*
+ * pxa168 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC        0x28
+#define APBC_TWSI0      0x2c
+#define APBC_KPC        0x30
+#define APBC_UART0      0x0
+#define APBC_UART1      0x4
+#define APBC_GPIO       0x8
+#define APBC_PWM0       0xc
+#define APBC_PWM1       0x10
+#define APBC_PWM2       0x14
+#define APBC_PWM3       0x18
+#define APBC_SSP0       0x81c
+#define APBC_SSP1       0x820
+#define APBC_SSP2       0x84c
+#define APBC_SSP3       0x858
+#define APBC_SSP4       0x85c
+#define APBC_TWSI1      0x6c
+#define APBC_UART2      0x70
+#define APMU_SDH0       0x54
+#define APMU_SDH1       0x58
+#define APMU_USB        0x5c
+#define APMU_DISP0      0x4c
+#define APMU_CCIC0      0x50
+#define APMU_DFC        0x60
+#define MPMU_UART_PLL   0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct clk_factor_masks uart_factor_masks = {
+        .factor = 2,
+        .num_mask = 0x1fff,
+        .den_mask = 0x1fff,
+        .num_shift = 16,
+        .den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+        {.num = 8125, .den = 1536},     /*14.745MHZ */
+};
+
+static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
+static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
+static const char *disp_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
+
+void __init pxa168_clk_init(void)
+{
+        struct clk *clk;
+        struct clk *uart_pll;
+        void __iomem *mpmu_base;
+        void __iomem *apmu_base;
+        void __iomem *apbc_base;
+
+        mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+        if (mpmu_base == NULL) {
+                pr_err("error to ioremap MPMU base\n");
+                return;
+        }
+
+        apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+        if (apmu_base == NULL) {
+                pr_err("error to ioremap APMU base\n");
+                return;
+        }
+
+        apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+        if (apbc_base == NULL) {
+                pr_err("error to ioremap APBC base\n");
+                return;
+        }
+
+        clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+        clk_register_clkdev(clk, "clk32", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+                                26000000);
+        clk_register_clkdev(clk, "vctcxo", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
+                                624000000);
+        clk_register_clkdev(clk, "pll1", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_2", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_4", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_8", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_16", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
+                                CLK_SET_RATE_PARENT, 1, 3);
+        clk_register_clkdev(clk, "pll1_6", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_12", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_24", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_48", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_96", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
+                                CLK_SET_RATE_PARENT, 1, 13);
+        clk_register_clkdev(clk, "pll1_13", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
+                                CLK_SET_RATE_PARENT, 2, 3);
+        clk_register_clkdev(clk, "pll1_13_1_5", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
+                                CLK_SET_RATE_PARENT, 2, 3);
+        clk_register_clkdev(clk, "pll1_2_1_5", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
+                                CLK_SET_RATE_PARENT, 3, 16);
+        clk_register_clkdev(clk, "pll1_3_16", NULL);
+
+        uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+                                mpmu_base + MPMU_UART_PLL,
+                                &uart_factor_masks, uart_factor_tbl,
+                                ARRAY_SIZE(uart_factor_tbl));
+        clk_set_rate(uart_pll, 14745600);
+        clk_register_clkdev(uart_pll, "uart_pll", NULL);
+
+        clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
+                                apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
+
+        clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
+                                apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
+
+        clk = mmp_clk_register_apbc("gpio", "vctcxo",
+                                apbc_base + APBC_GPIO, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa-gpio");
+
+        clk = mmp_clk_register_apbc("kpc", "clk32",
+                                apbc_base + APBC_KPC, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa27x-keypad");
+
+        clk = mmp_clk_register_apbc("rtc", "clk32",
+                                apbc_base + APBC_RTC, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sa1100-rtc");
+
+        clk = mmp_clk_register_apbc("pwm0", "pll1_48",
+                                apbc_base + APBC_PWM0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
+
+        clk = mmp_clk_register_apbc("pwm1", "pll1_48",
+                                apbc_base + APBC_PWM1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
+
+        clk = mmp_clk_register_apbc("pwm2", "pll1_48",
+                                apbc_base + APBC_PWM2, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
+
+        clk = mmp_clk_register_apbc("pwm3", "pll1_48",
+                                apbc_base + APBC_PWM3, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
+
+        clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, uart_pll);
+        clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+        clk = mmp_clk_register_apbc("uart0", "uart0_mux",
+                                apbc_base + APBC_UART0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
+
+        clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, uart_pll);
+        clk_register_clkdev(clk, "uart_mux.1", NULL);
+
+        clk = mmp_clk_register_apbc("uart1", "uart1_mux",
+                                apbc_base + APBC_UART1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
+
+        clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, uart_pll);
+        clk_register_clkdev(clk, "uart_mux.2", NULL);
+
+        clk = mmp_clk_register_apbc("uart2", "uart2_mux",
+                                apbc_base + APBC_UART2, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
+
+        clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+        clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
+                                10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.0");
+
+        clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "ssp_mux.1", NULL);
+
+        clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
+                                10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.1");
+
+        clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "ssp_mux.2", NULL);
+
+        clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
+                                10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.2");
+
+        clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "ssp_mux.3", NULL);
+
+        clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
+                                10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.3");
+
+        clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "ssp_mux.4", NULL);
+
+        clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
+                                10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.4");
+
+        clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
+                                0x19b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
+
+        clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
+                                ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "sdh0_mux", NULL);
+
+        clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
+                                0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
+
+        clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
+                                ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "sdh1_mux", NULL);
+
+        clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
+                                0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
+
+        clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
+                                0x9, &clk_lock);
+        clk_register_clkdev(clk, "usb_clk", NULL);
+
+        clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
+                                0x12, &clk_lock);
+        clk_register_clkdev(clk, "sph_clk", NULL);
+
+        clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
+                                ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "disp_mux.0", NULL);
+
+        clk = mmp_clk_register_apmu("disp0", "disp0_mux",
+                                apmu_base + APMU_DISP0, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
+
+        clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
+                                apmu_base + APMU_DISP0, 0x24, &clk_lock);
+        clk_register_clkdev(clk, "hclk", "mmp-disp.0");
+
+        clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+                                ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "ccic_mux.0", NULL);
+
+        clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
+                                apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
+
+        clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
+                                ARRAY_SIZE(ccic_phy_parent),
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+                                7, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
+
+        clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
+                                apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+        clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
+
+        clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+                                10, 5, 0, &clk_lock);
+        clk_register_clkdev(clk, "sphyclk_div", NULL);
+
+        clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+                                apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+        clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
+}
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
new file mode 100644
index 000000000000..7048c31d6e7e
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -0,0 +1,320 @@
+/*
+ * pxa910 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC        0x28
+#define APBC_TWSI0      0x2c
+#define APBC_KPC        0x18
+#define APBC_UART0      0x0
+#define APBC_UART1      0x4
+#define APBC_GPIO       0x8
+#define APBC_PWM0       0xc
+#define APBC_PWM1       0x10
+#define APBC_PWM2       0x14
+#define APBC_PWM3       0x18
+#define APBC_SSP0       0x1c
+#define APBC_SSP1       0x20
+#define APBC_SSP2       0x4c
+#define APBCP_TWSI1     0x28
+#define APBCP_UART2     0x1c
+#define APMU_SDH0       0x54
+#define APMU_SDH1       0x58
+#define APMU_USB        0x5c
+#define APMU_DISP0      0x4c
+#define APMU_CCIC0      0x50
+#define APMU_DFC        0x60
+#define MPMU_UART_PLL   0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct clk_factor_masks uart_factor_masks = {
+        .factor = 2,
+        .num_mask = 0x1fff,
+        .den_mask = 0x1fff,
+        .num_shift = 16,
+        .den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+        {.num = 8125, .den = 1536},     /*14.745MHZ */
+};
+
+static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
+static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
+static const char *disp_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
+
+void __init pxa910_clk_init(void)
+{
+        struct clk *clk;
+        struct clk *uart_pll;
+        void __iomem *mpmu_base;
+        void __iomem *apmu_base;
+        void __iomem *apbcp_base;
+        void __iomem *apbc_base;
+
+        mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+        if (mpmu_base == NULL) {
+                pr_err("error to ioremap MPMU base\n");
+                return;
+        }
+
+        apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+        if (apmu_base == NULL) {
+                pr_err("error to ioremap APMU base\n");
+                return;
+        }
+
+        apbcp_base = ioremap(APB_PHYS_BASE + 0x3b000, SZ_4K);
+        if (apbcp_base == NULL) {
+                pr_err("error to ioremap APBC extension base\n");
+                return;
+        }
+
+        apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+        if (apbc_base == NULL) {
+                pr_err("error to ioremap APBC base\n");
+                return;
+        }
+
+        clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+        clk_register_clkdev(clk, "clk32", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+                                26000000);
+        clk_register_clkdev(clk, "vctcxo", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
+                                624000000);
+        clk_register_clkdev(clk, "pll1", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_2", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_4", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_8", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_16", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
+                                CLK_SET_RATE_PARENT, 1, 3);
+        clk_register_clkdev(clk, "pll1_6", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_12", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_24", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_48", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
+                                CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll1_96", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
+                                CLK_SET_RATE_PARENT, 1, 13);
+        clk_register_clkdev(clk, "pll1_13", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
+                                CLK_SET_RATE_PARENT, 2, 3);
+        clk_register_clkdev(clk, "pll1_13_1_5", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
+                                CLK_SET_RATE_PARENT, 2, 3);
+        clk_register_clkdev(clk, "pll1_2_1_5", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
+                                CLK_SET_RATE_PARENT, 3, 16);
+        clk_register_clkdev(clk, "pll1_3_16", NULL);
+
+        uart_pll =  mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+                                mpmu_base + MPMU_UART_PLL,
+                                &uart_factor_masks, uart_factor_tbl,
+                                ARRAY_SIZE(uart_factor_tbl));
+        clk_set_rate(uart_pll, 14745600);
+        clk_register_clkdev(uart_pll, "uart_pll", NULL);
+
+        clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
+                                apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
+
+        clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
+                                apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
+
+        clk = mmp_clk_register_apbc("gpio", "vctcxo",
+                                apbc_base + APBC_GPIO, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa-gpio");
+
+        clk = mmp_clk_register_apbc("kpc", "clk32",
+                                apbc_base + APBC_KPC, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa27x-keypad");
+
+        clk = mmp_clk_register_apbc("rtc", "clk32",
+                                apbc_base + APBC_RTC, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sa1100-rtc");
+
+        clk = mmp_clk_register_apbc("pwm0", "pll1_48",
+                                apbc_base + APBC_PWM0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
+
+        clk = mmp_clk_register_apbc("pwm1", "pll1_48",
+                                apbc_base + APBC_PWM1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
+
+        clk = mmp_clk_register_apbc("pwm2", "pll1_48",
+                                apbc_base + APBC_PWM2, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
+
+        clk = mmp_clk_register_apbc("pwm3", "pll1_48",
+                                apbc_base + APBC_PWM3, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
+
+        clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, uart_pll);
+        clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+        clk = mmp_clk_register_apbc("uart0", "uart0_mux",
+                                apbc_base + APBC_UART0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
+
+        clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, uart_pll);
+        clk_register_clkdev(clk, "uart_mux.1", NULL);
+
+        clk = mmp_clk_register_apbc("uart1", "uart1_mux",
+                                apbc_base + APBC_UART1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
+
+        clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
+                                ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+                                apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
+        clk_set_parent(clk, uart_pll);
+        clk_register_clkdev(clk, "uart_mux.2", NULL);
+
+        clk = mmp_clk_register_apbc("uart2", "uart2_mux",
+                                apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
+
+        clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+        clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
+                                apbc_base + APBC_SSP0, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.0");
+
+        clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+                                ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+                                apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+        clk_register_clkdev(clk, "ssp_mux.1", NULL);
+
+        clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
+                                apbc_base + APBC_SSP1, 10, 0, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-ssp.1");
+
+        clk = mmp_clk_register_apmu("dfc", "pll1_4",
+                                apmu_base + APMU_DFC, 0x19b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
+
+        clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
+                                ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "sdh0_mux", NULL);
+
+        clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
+                                apmu_base + APMU_SDH0, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
+
+        clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
+                                ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "sdh1_mux", NULL);
+
+        clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
+                                apmu_base + APMU_SDH1, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
+
+        clk = mmp_clk_register_apmu("usb", "usb_pll",
+                                apmu_base + APMU_USB, 0x9, &clk_lock);
+        clk_register_clkdev(clk, "usb_clk", NULL);
+
+        clk = mmp_clk_register_apmu("sph", "usb_pll",
+                                apmu_base + APMU_USB, 0x12, &clk_lock);
+        clk_register_clkdev(clk, "sph_clk", NULL);
+
+        clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
+                                ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "disp_mux.0", NULL);
+
+        clk = mmp_clk_register_apmu("disp0", "disp0_mux",
+                                apmu_base + APMU_DISP0, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, NULL, "mmp-disp.0");
+
+        clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+                                ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+                                apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "ccic_mux.0", NULL);
+
+        clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
+                                apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
+        clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
+
+        clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
+                                ARRAY_SIZE(ccic_phy_parent),
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+                                7, 1, 0, &clk_lock);
+        clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
+
+        clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
+                                apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+        clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
+
+        clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
+                                CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+                                10, 5, 0, &clk_lock);
+        clk_register_clkdev(clk, "sphyclk_div", NULL);
+
+        clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+                                apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+        clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
+}
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
new file mode 100644
index 000000000000..ab86dd4a416a
--- /dev/null
+++ b/drivers/clk/mmp/clk.h
@@ -0,0 +1,35 @@
+#ifndef __MACH_MMP_CLK_H
+#define __MACH_MMP_CLK_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+#define APBC_NO_BUS_CTRL        BIT(0)
+#define APBC_POWER_CTRL         BIT(1)
+
+struct clk_factor_masks {
+        unsigned int    factor;
+        unsigned int    num_mask;
+        unsigned int    den_mask;
+        unsigned int    num_shift;
+        unsigned int    den_shift;
+};
+
+struct clk_factor_tbl {
+        unsigned int num;
+        unsigned int den;
+};
+
+extern struct clk *mmp_clk_register_pll2(const char *name,
+                const char *parent_name, unsigned long flags);
+extern struct clk *mmp_clk_register_apbc(const char *name,
+                const char *parent_name, void __iomem *base,
+                unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
+extern struct clk *mmp_clk_register_apmu(const char *name,
+                const char *parent_name, void __iomem *base, u32 enable_mask,
+                spinlock_t *lock);
+extern struct clk *mmp_clk_register_factor(const char *name,
+                const char *parent_name, unsigned long flags,
+                void __iomem *base, struct clk_factor_masks *masks,
+                struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
+#endif
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 844043ad0fe4..9f6d15546cbe 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <mach/common.h>
 #include <mach/mx23.h>
 #include "clk.h"
@@ -71,44 +72,6 @@ static void __init clk_misc_init(void)
         __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
 }
 
-static struct clk_lookup uart_lookups[] = {
-        { .dev_id = "duart", },
-        { .dev_id = "mxs-auart.0", },
-        { .dev_id = "mxs-auart.1", },
-        { .dev_id = "8006c000.serial", },
-        { .dev_id = "8006e000.serial", },
-        { .dev_id = "80070000.serial", },
-};
-
-static struct clk_lookup hbus_lookups[] = {
-        { .dev_id = "imx23-dma-apbh", },
-        { .dev_id = "80004000.dma-apbh", },
-};
-
-static struct clk_lookup xbus_lookups[] = {
-        { .dev_id = "duart", .con_id = "apb_pclk"},
-        { .dev_id = "80070000.serial", .con_id = "apb_pclk"},
-        { .dev_id = "imx23-dma-apbx", },
-        { .dev_id = "80024000.dma-apbx", },
-};
-
-static struct clk_lookup ssp_lookups[] = {
-        { .dev_id = "imx23-mmc.0", },
-        { .dev_id = "imx23-mmc.1", },
-        { .dev_id = "80010000.ssp", },
-        { .dev_id = "80034000.ssp", },
-};
-
-static struct clk_lookup lcdif_lookups[] = {
-        { .dev_id = "imx23-fb", },
-        { .dev_id = "80030000.lcdif", },
-};
-
-static struct clk_lookup gpmi_lookups[] = {
-        { .dev_id = "imx23-gpmi-nand", },
-        { .dev_id = "8000c000.gpmi-nand", },
-};
-
 static const char *sel_pll[]  __initconst = { "pll", "ref_xtal", };
 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
@@ -127,6 +90,7 @@ enum imx23_clk {
 };
 
 static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
 
 static enum imx23_clk clks_init_on[] __initdata = {
         cpu, hbus, xbus, emi, uart,
@@ -134,6 +98,7 @@ static enum imx23_clk clks_init_on[] __initdata = {
 
 int __init mx23_clocks_init(void)
 {
+        struct device_node *np;
         int i;
 
         clk_misc_init();
@@ -188,14 +153,14 @@ int __init mx23_clocks_init(void)
                         return PTR_ERR(clks[i]);
                 }
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
+        if (np) {
+                clk_data.clks = clks;
+                clk_data.clk_num = ARRAY_SIZE(clks);
+                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        }
+
         clk_register_clkdev(clks[clk32k], NULL, "timrot");
-        clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
-        clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
-        clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
-        clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
-        clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups));
-        clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
-        clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
 
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clks[clks_init_on[i]]);
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index e3aab67b3eb7..613e76f3758e 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <mach/common.h>
 #include <mach/mx28.h>
 #include "clk.h"
@@ -120,90 +121,6 @@ static void __init clk_misc_init(void)
         writel_relaxed(val, FRAC0);
 }
 
-static struct clk_lookup uart_lookups[] = {
-        { .dev_id = "duart", },
-        { .dev_id = "mxs-auart.0", },
-        { .dev_id = "mxs-auart.1", },
-        { .dev_id = "mxs-auart.2", },
-        { .dev_id = "mxs-auart.3", },
-        { .dev_id = "mxs-auart.4", },
-        { .dev_id = "8006a000.serial", },
-        { .dev_id = "8006c000.serial", },
-        { .dev_id = "8006e000.serial", },
-        { .dev_id = "80070000.serial", },
-        { .dev_id = "80072000.serial", },
-        { .dev_id = "80074000.serial", },
-};
-
-static struct clk_lookup hbus_lookups[] = {
-        { .dev_id = "imx28-dma-apbh", },
-        { .dev_id = "80004000.dma-apbh", },
-};
-
-static struct clk_lookup xbus_lookups[] = {
-        { .dev_id = "duart", .con_id = "apb_pclk"},
-        { .dev_id = "80074000.serial", .con_id = "apb_pclk"},
-        { .dev_id = "imx28-dma-apbx", },
-        { .dev_id = "80024000.dma-apbx", },
-};
-
-static struct clk_lookup ssp0_lookups[] = {
-        { .dev_id = "imx28-mmc.0", },
-        { .dev_id = "80010000.ssp", },
-};
-
-static struct clk_lookup ssp1_lookups[] = {
-        { .dev_id = "imx28-mmc.1", },
-        { .dev_id = "80012000.ssp", },
-};
-
-static struct clk_lookup ssp2_lookups[] = {
-        { .dev_id = "imx28-mmc.2", },
-        { .dev_id = "80014000.ssp", },
-};
-
-static struct clk_lookup ssp3_lookups[] = {
-        { .dev_id = "imx28-mmc.3", },
-        { .dev_id = "80016000.ssp", },
-};
-
-static struct clk_lookup lcdif_lookups[] = {
-        { .dev_id = "imx28-fb", },
-        { .dev_id = "80030000.lcdif", },
-};
-
-static struct clk_lookup gpmi_lookups[] = {
-        { .dev_id = "imx28-gpmi-nand", },
-        { .dev_id = "8000c000.gpmi-nand", },
-};
-
-static struct clk_lookup fec_lookups[] = {
-        { .dev_id = "imx28-fec.0", },
-        { .dev_id = "imx28-fec.1", },
-        { .dev_id = "800f0000.ethernet", },
-        { .dev_id = "800f4000.ethernet", },
-};
-
-static struct clk_lookup can0_lookups[] = {
-        { .dev_id = "flexcan.0", },
-        { .dev_id = "80032000.can", },
-};
-
-static struct clk_lookup can1_lookups[] = {
-        { .dev_id = "flexcan.1", },
-        { .dev_id = "80034000.can", },
-};
-
-static struct clk_lookup saif0_lookups[] = {
-        { .dev_id = "mxs-saif.0", },
-        { .dev_id = "80042000.saif", },
-};
-
-static struct clk_lookup saif1_lookups[] = {
-        { .dev_id = "mxs-saif.1", },
-        { .dev_id = "80046000.saif", },
-};
-
 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 static const char *sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
 static const char *sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
@@ -228,6 +145,7 @@ enum imx28_clk {
 };
 
 static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
 
 static enum imx28_clk clks_init_on[] __initdata = {
         cpu, hbus, xbus, emi, uart,
@@ -235,6 +153,7 @@ static enum imx28_clk clks_init_on[] __initdata = {
 
 int __init mx28_clocks_init(void)
 {
+        struct device_node *np;
         int i;
 
         clk_misc_init();
@@ -312,27 +231,15 @@ int __init mx28_clocks_init(void)
                         return PTR_ERR(clks[i]);
                 }
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
+        if (np) {
+                clk_data.clks = clks;
+                clk_data.clk_num = ARRAY_SIZE(clks);
+                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        }
+
         clk_register_clkdev(clks[clk32k], NULL, "timrot");
         clk_register_clkdev(clks[enet_out], NULL, "enet_out");
-        clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
-        clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
-        clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
-        clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
-        clk_register_clkdevs(clks[ssp0], ssp0_lookups, ARRAY_SIZE(ssp0_lookups));
-        clk_register_clkdevs(clks[ssp1], ssp1_lookups, ARRAY_SIZE(ssp1_lookups));
-        clk_register_clkdevs(clks[ssp2], ssp2_lookups, ARRAY_SIZE(ssp2_lookups));
-        clk_register_clkdevs(clks[ssp3], ssp3_lookups, ARRAY_SIZE(ssp3_lookups));
-        clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
-        clk_register_clkdevs(clks[saif0], saif0_lookups, ARRAY_SIZE(saif0_lookups));
-        clk_register_clkdevs(clks[saif1], saif1_lookups, ARRAY_SIZE(saif1_lookups));
-        clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
-        clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups));
-        clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups));
-        clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups));
-        clk_register_clkdev(clks[usb0_pwr], NULL, "8007c000.usbphy");
-        clk_register_clkdev(clks[usb1_pwr], NULL, "8007e000.usbphy");
-        clk_register_clkdev(clks[usb0], NULL, "80080000.usb");
-        clk_register_clkdev(clks[usb1], NULL, "80090000.usb");
 
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clks[clks_init_on[i]]);
diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
new file mode 100644
index 000000000000..858fbfe66281
--- /dev/null
+++ b/drivers/clk/ux500/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for ux500 clocks
+#
+
+# Clock types
+obj-y += clk-prcc.o
+obj-y += clk-prcmu.o
+
+# Clock definitions
+obj-y += u8500_clk.o
+obj-y += u9540_clk.o
+obj-y += u8540_clk.o
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
new file mode 100644
index 000000000000..7eee7f768355
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -0,0 +1,164 @@
+/*
+ * PRCC clock implementation for ux500 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk-private.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <mach/hardware.h>
+
+#include "clk.h"
+
+#define PRCC_PCKEN                      0x000
+#define PRCC_PCKDIS                     0x004
+#define PRCC_KCKEN                      0x008
+#define PRCC_KCKDIS                     0x00C
+#define PRCC_PCKSR                      0x010
+#define PRCC_KCKSR                      0x014
+
+#define to_clk_prcc(_hw) container_of(_hw, struct clk_prcc, hw)
+
+struct clk_prcc {
+        struct clk_hw hw;
+        void __iomem *base;
+        u32 cg_sel;
+        int is_enabled;
+};
+
+/* PRCC clock operations. */
+
+static int clk_prcc_pclk_enable(struct clk_hw *hw)
+{
+        struct clk_prcc *clk = to_clk_prcc(hw);
+
+        writel(clk->cg_sel, (clk->base + PRCC_PCKEN));
+        while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel))
+                cpu_relax();
+
+        clk->is_enabled = 1;
+        return 0;
+}
+
+static void clk_prcc_pclk_disable(struct clk_hw *hw)
+{
+        struct clk_prcc *clk = to_clk_prcc(hw);
+
+        writel(clk->cg_sel, (clk->base + PRCC_PCKDIS));
+        clk->is_enabled = 0;
+}
+
+static int clk_prcc_kclk_enable(struct clk_hw *hw)
+{
+        struct clk_prcc *clk = to_clk_prcc(hw);
+
+        writel(clk->cg_sel, (clk->base + PRCC_KCKEN));
+        while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel))
+                cpu_relax();
+
+        clk->is_enabled = 1;
+        return 0;
+}
+
+static void clk_prcc_kclk_disable(struct clk_hw *hw)
+{
+        struct clk_prcc *clk = to_clk_prcc(hw);
+
+        writel(clk->cg_sel, (clk->base + PRCC_KCKDIS));
+        clk->is_enabled = 0;
+}
+
+static int clk_prcc_is_enabled(struct clk_hw *hw)
+{
+        struct clk_prcc *clk = to_clk_prcc(hw);
+        return clk->is_enabled;
+}
+
+static struct clk_ops clk_prcc_pclk_ops = {
+        .enable = clk_prcc_pclk_enable,
+        .disable = clk_prcc_pclk_disable,
+        .is_enabled = clk_prcc_is_enabled,
+};
+
+static struct clk_ops clk_prcc_kclk_ops = {
+        .enable = clk_prcc_kclk_enable,
+        .disable = clk_prcc_kclk_disable,
+        .is_enabled = clk_prcc_is_enabled,
+};
+
+static struct clk *clk_reg_prcc(const char *name,
+                                const char *parent_name,
+                                resource_size_t phy_base,
+                                u32 cg_sel,
+                                unsigned long flags,
+                                struct clk_ops *clk_prcc_ops)
+{
+        struct clk_prcc *clk;
+        struct clk_init_data clk_prcc_init;
+        struct clk *clk_reg;
+
+        if (!name) {
+                pr_err("clk_prcc: %s invalid arguments passed\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL);
+        if (!clk) {
+                pr_err("clk_prcc: %s could not allocate clk\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        clk->base = ioremap(phy_base, SZ_4K);
+        if (!clk->base)
+                goto free_clk;
+
+        clk->cg_sel = cg_sel;
+        clk->is_enabled = 1;
+
+        clk_prcc_init.name = name;
+        clk_prcc_init.ops = clk_prcc_ops;
+        clk_prcc_init.flags = flags;
+        clk_prcc_init.parent_names = (parent_name ? &parent_name : NULL);
+        clk_prcc_init.num_parents = (parent_name ? 1 : 0);
+        clk->hw.init = &clk_prcc_init;
+
+        clk_reg = clk_register(NULL, &clk->hw);
+        if (IS_ERR_OR_NULL(clk_reg))
+                goto unmap_clk;
+
+        return clk_reg;
+
+unmap_clk:
+        iounmap(clk->base);
+free_clk:
+        kfree(clk);
+        pr_err("clk_prcc: %s failed to register clk\n", __func__);
+        return ERR_PTR(-ENOMEM);
+}
+
+struct clk *clk_reg_prcc_pclk(const char *name,
+                              const char *parent_name,
+                              resource_size_t phy_base,
+                              u32 cg_sel,
+                              unsigned long flags)
+{
+        return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
+                        &clk_prcc_pclk_ops);
+}
+
+struct clk *clk_reg_prcc_kclk(const char *name,
+                              const char *parent_name,
+                              resource_size_t phy_base,
+                              u32 cg_sel,
+                              unsigned long flags)
+{
+        return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
+                        &clk_prcc_kclk_ops);
+}
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
new file mode 100644
index 000000000000..930cdfeb47ab
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -0,0 +1,252 @@
+/*
+ * PRCMU clock implementation for ux500 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk-private.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+#define to_clk_prcmu(_hw) container_of(_hw, struct clk_prcmu, hw)
+
+struct clk_prcmu {
+        struct clk_hw hw;
+        u8 cg_sel;
+        int is_enabled;
+};
+
+/* PRCMU clock operations. */
+
+static int clk_prcmu_prepare(struct clk_hw *hw)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+        return prcmu_request_clock(clk->cg_sel, true);
+}
+
+static void clk_prcmu_unprepare(struct clk_hw *hw)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+        if (prcmu_request_clock(clk->cg_sel, false))
+                pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
+                        hw->init->name);
+}
+
+static int clk_prcmu_enable(struct clk_hw *hw)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+        clk->is_enabled = 1;
+        return 0;
+}
+
+static void clk_prcmu_disable(struct clk_hw *hw)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+        clk->is_enabled = 0;
+}
+
+static int clk_prcmu_is_enabled(struct clk_hw *hw)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+        return clk->is_enabled;
+}
+
+static unsigned long clk_prcmu_recalc_rate(struct clk_hw *hw,
+                                           unsigned long parent_rate)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+        return prcmu_clock_rate(clk->cg_sel);
+}
+
+static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *parent_rate)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+        return prcmu_round_clock_rate(clk->cg_sel, rate);
+}
+
+static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long parent_rate)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+        return prcmu_set_clock_rate(clk->cg_sel, rate);
+}
+
+static int request_ape_opp100(bool enable)
+{
+        static int reqs;
+        int err = 0;
+
+        if (enable) {
+                if (!reqs)
+                        err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
+                                                        "clock", 100);
+                if (!err)
+                        reqs++;
+        } else {
+                reqs--;
+                if (!reqs)
+                        prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
+                                                "clock");
+        }
+        return err;
+}
+
+static int clk_prcmu_opp_prepare(struct clk_hw *hw)
+{
+        int err;
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+
+        err = request_ape_opp100(true);
+        if (err) {
+                pr_err("clk_prcmu: %s failed to request APE OPP100 for %s.\n",
+                        __func__, hw->init->name);
+                return err;
+        }
+
+        err = prcmu_request_clock(clk->cg_sel, true);
+        if (err)
+                request_ape_opp100(false);
+
+        return err;
+}
+
+static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+
+        if (prcmu_request_clock(clk->cg_sel, false))
+                goto out_error;
+        if (request_ape_opp100(false))
+                goto out_error;
+        return;
+
+out_error:
+        pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
+                hw->init->name);
+}
+
+static struct clk_ops clk_prcmu_scalable_ops = {
+        .prepare = clk_prcmu_prepare,
+        .unprepare = clk_prcmu_unprepare,
+        .enable = clk_prcmu_enable,
+        .disable = clk_prcmu_disable,
+        .is_enabled = clk_prcmu_is_enabled,
+        .recalc_rate = clk_prcmu_recalc_rate,
+        .round_rate = clk_prcmu_round_rate,
+        .set_rate = clk_prcmu_set_rate,
+};
+
+static struct clk_ops clk_prcmu_gate_ops = {
+        .prepare = clk_prcmu_prepare,
+        .unprepare = clk_prcmu_unprepare,
+        .enable = clk_prcmu_enable,
+        .disable = clk_prcmu_disable,
+        .is_enabled = clk_prcmu_is_enabled,
+        .recalc_rate = clk_prcmu_recalc_rate,
+};
+
+static struct clk_ops clk_prcmu_rate_ops = {
+        .is_enabled = clk_prcmu_is_enabled,
+        .recalc_rate = clk_prcmu_recalc_rate,
+};
+
+static struct clk_ops clk_prcmu_opp_gate_ops = {
+        .prepare = clk_prcmu_opp_prepare,
+        .unprepare = clk_prcmu_opp_unprepare,
+        .enable = clk_prcmu_enable,
+        .disable = clk_prcmu_disable,
+        .is_enabled = clk_prcmu_is_enabled,
+        .recalc_rate = clk_prcmu_recalc_rate,
+};
+
+static struct clk *clk_reg_prcmu(const char *name,
+                                 const char *parent_name,
+                                 u8 cg_sel,
+                                 unsigned long rate,
+                                 unsigned long flags,
+                                 struct clk_ops *clk_prcmu_ops)
+{
+        struct clk_prcmu *clk;
+        struct clk_init_data clk_prcmu_init;
+        struct clk *clk_reg;
+
+        if (!name) {
+                pr_err("clk_prcmu: %s invalid arguments passed\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL);
+        if (!clk) {
+                pr_err("clk_prcmu: %s could not allocate clk\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        clk->cg_sel = cg_sel;
+        clk->is_enabled = 1;
+        /* "rate" can be used for changing the initial frequency */
+        if (rate)
+                prcmu_set_clock_rate(cg_sel, rate);
+
+        clk_prcmu_init.name = name;
+        clk_prcmu_init.ops = clk_prcmu_ops;
+        clk_prcmu_init.flags = flags;
+        clk_prcmu_init.parent_names = (parent_name ? &parent_name : NULL);
+        clk_prcmu_init.num_parents = (parent_name ? 1 : 0);
+        clk->hw.init = &clk_prcmu_init;
+
+        clk_reg = clk_register(NULL, &clk->hw);
+        if (IS_ERR_OR_NULL(clk_reg))
+                goto free_clk;
+
+        return clk_reg;
+
+free_clk:
+        kfree(clk);
+        pr_err("clk_prcmu: %s failed to register clk\n", __func__);
+        return ERR_PTR(-ENOMEM);
+}
+
+struct clk *clk_reg_prcmu_scalable(const char *name,
+                                   const char *parent_name,
+                                   u8 cg_sel,
+                                   unsigned long rate,
+                                   unsigned long flags)
+{
+        return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
+                        &clk_prcmu_scalable_ops);
+}
+
+struct clk *clk_reg_prcmu_gate(const char *name,
+                               const char *parent_name,
+                               u8 cg_sel,
+                               unsigned long flags)
+{
+        return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
+                        &clk_prcmu_gate_ops);
+}
+
+struct clk *clk_reg_prcmu_rate(const char *name,
+                               const char *parent_name,
+                               u8 cg_sel,
+                               unsigned long flags)
+{
+        return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
+                        &clk_prcmu_rate_ops);
+}
+
+struct clk *clk_reg_prcmu_opp_gate(const char *name,
+                                   const char *parent_name,
+                                   u8 cg_sel,
+                                   unsigned long flags)
+{
+        return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
+                        &clk_prcmu_opp_gate_ops);
+}
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
new file mode 100644
index 000000000000..836d7d16751e
--- /dev/null
+++ b/drivers/clk/ux500/clk.h
@@ -0,0 +1,48 @@
+/*
+ * Clocks for ux500 platforms
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __UX500_CLK_H
+#define __UX500_CLK_H
+
+#include <linux/clk.h>
+
+struct clk *clk_reg_prcc_pclk(const char *name,
+                              const char *parent_name,
+                              unsigned int phy_base,
+                              u32 cg_sel,
+                              unsigned long flags);
+
+struct clk *clk_reg_prcc_kclk(const char *name,
+                              const char *parent_name,
+                              unsigned int phy_base,
+                              u32 cg_sel,
+                              unsigned long flags);
+
+struct clk *clk_reg_prcmu_scalable(const char *name,
+                                   const char *parent_name,
+                                   u8 cg_sel,
+                                   unsigned long rate,
+                                   unsigned long flags);
+
+struct clk *clk_reg_prcmu_gate(const char *name,
+                               const char *parent_name,
+                               u8 cg_sel,
+                               unsigned long flags);
+
+struct clk *clk_reg_prcmu_rate(const char *name,
+                               const char *parent_name,
+                               u8 cg_sel,
+                               unsigned long flags);
+
+struct clk *clk_reg_prcmu_opp_gate(const char *name,
+                                   const char *parent_name,
+                                   u8 cg_sel,
+                                   unsigned long flags);
+
+#endif /* __UX500_CLK_H */
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
new file mode 100644
index 000000000000..ca4a25ed844c
--- /dev/null
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -0,0 +1,477 @@
+/*
+ * Clock definitions for u8500 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/clk-ux500.h>
+
+#include "clk.h"
+
+void u8500_clk_init(void)
+{
+        struct prcmu_fw_version *fw_version;
+        const char *sgaclk_parent = NULL;
+        struct clk *clk;
+
+        /* Clock sources */
+        clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
+                                CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+        clk_register_clkdev(clk, "soc0_pll", NULL);
+
+        clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
+                                CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+        clk_register_clkdev(clk, "soc1_pll", NULL);
+
+        clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
+                                CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+        clk_register_clkdev(clk, "ddr_pll", NULL);
+
+        /* FIXME: Add sys, ulp and int clocks here. */
+
+        clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
+                                CLK_IS_ROOT|CLK_IGNORE_UNUSED,
+                                32768);
+        clk_register_clkdev(clk, "clk32k", NULL);
+        clk_register_clkdev(clk, NULL, "rtc-pl031");
+
+        /* PRCMU clocks */
+        fw_version = prcmu_get_fw_version();
+        if (fw_version != NULL) {
+                switch (fw_version->project) {
+                case PRCMU_FW_PROJECT_U8500_C2:
+                case PRCMU_FW_PROJECT_U8520:
+                case PRCMU_FW_PROJECT_U8420:
+                        sgaclk_parent = "soc0_pll";
+                        break;
+                default:
+                        break;
+                }
+        }
+
+        if (sgaclk_parent)
+                clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
+                                        PRCMU_SGACLK, 0);
+        else
+                clk = clk_reg_prcmu_gate("sgclk", NULL,
+                                        PRCMU_SGACLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "mali");
+
+        clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "UART");
+
+        clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "MSP02");
+
+        clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "MSP1");
+
+        clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "I2C");
+
+        clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "slim");
+
+        clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "PERIPH1");
+
+        clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "PERIPH2");
+
+        clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "PERIPH3");
+
+        clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "PERIPH5");
+
+        clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "PERIPH6");
+
+        clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "PERIPH7");
+
+        clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
+                                CLK_IS_ROOT|CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "lcd");
+        clk_register_clkdev(clk, "lcd", "mcde");
+
+        clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "bml");
+
+        clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
+                                CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+        clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
+                                CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+        clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
+                                CLK_IS_ROOT|CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "hdmi");
+        clk_register_clkdev(clk, "hdmi", "mcde");
+
+        clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "apeat");
+
+        clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
+                                CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "apetrace");
+
+        clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "mcde");
+        clk_register_clkdev(clk, "mcde", "mcde");
+        clk_register_clkdev(clk, "dsisys", "dsilink.0");
+        clk_register_clkdev(clk, "dsisys", "dsilink.1");
+        clk_register_clkdev(clk, "dsisys", "dsilink.2");
+
+        clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
+                                CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "ipi2");
+
+        clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
+                                CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "dsialt");
+
+        clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "dma40.0");
+
+        clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "b2r2");
+        clk_register_clkdev(clk, NULL, "b2r2_core");
+        clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
+
+        clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
+                                CLK_IS_ROOT|CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "tv");
+        clk_register_clkdev(clk, "tv", "mcde");
+
+        clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "SSP");
+
+        clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "rngclk");
+
+        clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "uicc");
+
+        /*
+         * FIXME: The MTU clocks might need some kind of "parent muxed join"
+         * and these have no K-clocks. For now, we ignore the missing
+         * connection to the corresponding P-clocks, p6_mtu0_clk and
+         * p6_mtu1_clk. Instead timclk is used which is the valid parent.
+         */
+        clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "mtu0");
+        clk_register_clkdev(clk, NULL, "mtu1");
+
+        clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT);
+        clk_register_clkdev(clk, NULL, "sdmmc");
+
+
+        clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
+                                PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, "dsihs2", "mcde");
+        clk_register_clkdev(clk, "dsihs2", "dsilink.2");
+
+
+        clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
+                                PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, "dsihs0", "mcde");
+        clk_register_clkdev(clk, "dsihs0", "dsilink.0");
+
+        clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
+                                PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, "dsihs1", "mcde");
+        clk_register_clkdev(clk, "dsihs1", "dsilink.1");
+
+        clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
+                                PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, "dsilp0", "dsilink.0");
+        clk_register_clkdev(clk, "dsilp0", "mcde");
+
+        clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
+                                PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, "dsilp1", "dsilink.1");
+        clk_register_clkdev(clk, "dsilp1", "mcde");
+
+        clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
+                                PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, "dsilp2", "dsilink.2");
+        clk_register_clkdev(clk, "dsilp2", "mcde");
+
+        clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS,
+                                CLK_IS_ROOT|CLK_GET_RATE_NOCACHE|
+                                CLK_IGNORE_UNUSED);
+        clk_register_clkdev(clk, NULL, "smp_twd");
+
+        /*
+         * FIXME: Add special handled PRCMU clocks here:
+         * 1. clk_arm, use PRCMU_ARMCLK.
+         * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
+         * 3. ab9540_clkout1yuv, see clkout0yuv
+         */
+
+        /* PRCC P-clocks */
+        clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(0), 0);
+        clk_register_clkdev(clk, "apb_pclk", "uart0");
+
+        clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(1), 0);
+        clk_register_clkdev(clk, "apb_pclk", "uart1");
+
+        clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(2), 0);
+        clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(3), 0);
+        clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(4), 0);
+
+        clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(5), 0);
+        clk_register_clkdev(clk, "apb_pclk", "sdi0");
+
+        clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(6), 0);
+
+        clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(7), 0);
+        clk_register_clkdev(clk, NULL, "spi3");
+
+        clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(8), 0);
+
+        clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(9), 0);
+        clk_register_clkdev(clk, NULL, "gpio.0");
+        clk_register_clkdev(clk, NULL, "gpio.1");
+        clk_register_clkdev(clk, NULL, "gpioblock0");
+
+        clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(10), 0);
+        clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
+                                BIT(11), 0);
+
+        clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(0), 0);
+
+        clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(1), 0);
+        clk_register_clkdev(clk, NULL, "spi2");
+
+        clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(2), 0);
+        clk_register_clkdev(clk, NULL, "spi1");
+
+        clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(3), 0);
+        clk_register_clkdev(clk, NULL, "pwl");
+
+        clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(4), 0);
+        clk_register_clkdev(clk, "apb_pclk", "sdi4");
+
+        clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(5), 0);
+
+        clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(6), 0);
+        clk_register_clkdev(clk, "apb_pclk", "sdi1");
+
+
+        clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(7), 0);
+        clk_register_clkdev(clk, "apb_pclk", "sdi3");
+
+        clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(8), 0);
+        clk_register_clkdev(clk, NULL, "spi0");
+
+        clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(9), 0);
+        clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
+
+        clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(10), 0);
+        clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
+
+        clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(11), 0);
+        clk_register_clkdev(clk, NULL, "gpio.6");
+        clk_register_clkdev(clk, NULL, "gpio.7");
+        clk_register_clkdev(clk, NULL, "gpioblock1");
+
+        clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
+                                BIT(11), 0);
+
+        clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
+                                BIT(0), 0);
+        clk_register_clkdev(clk, NULL, "fsmc");
+
+        clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
+                                BIT(1), 0);
+        clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
+                                BIT(2), 0);
+        clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
+                                BIT(3), 0);
+
+        clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,
+                                BIT(4), 0);
+        clk_register_clkdev(clk, "apb_pclk", "sdi2");
+
+        clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE,
+                                BIT(5), 0);
+
+        clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE,
+                                BIT(6), 0);
+        clk_register_clkdev(clk, "apb_pclk", "uart2");
+
+        clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE,
+                                BIT(7), 0);
+        clk_register_clkdev(clk, "apb_pclk", "sdi5");
+
+        clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE,
+                                BIT(8), 0);
+        clk_register_clkdev(clk, NULL, "gpio.2");
+        clk_register_clkdev(clk, NULL, "gpio.3");
+        clk_register_clkdev(clk, NULL, "gpio.4");
+        clk_register_clkdev(clk, NULL, "gpio.5");
+        clk_register_clkdev(clk, NULL, "gpioblock2");
+
+        clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE,
+                                BIT(0), 0);
+        clk_register_clkdev(clk, "usb", "musb-ux500.0");
+
+        clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE,
+                                BIT(1), 0);
+        clk_register_clkdev(clk, NULL, "gpio.8");
+        clk_register_clkdev(clk, NULL, "gpioblock3");
+
+        clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
+                                BIT(0), 0);
+
+        clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
+                                BIT(1), 0);
+        clk_register_clkdev(clk, NULL, "cryp0");
+        clk_register_clkdev(clk, NULL, "cryp1");
+
+        clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE,
+                                BIT(2), 0);
+        clk_register_clkdev(clk, NULL, "hash0");
+
+        clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE,
+                                BIT(3), 0);
+        clk_register_clkdev(clk, NULL, "pka");
+
+        clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE,
+                                BIT(4), 0);
+        clk_register_clkdev(clk, NULL, "hash1");
+
+        clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE,
+                                BIT(5), 0);
+        clk_register_clkdev(clk, NULL, "cfgreg");
+
+        clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
+                                BIT(6), 0);
+        clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
+                                BIT(7), 0);
+
+        /* PRCC K-clocks
+         *
+         * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
+         * by enabling just the K-clock, even if it is not a valid parent to
+         * the K-clock. Until drivers get fixed we might need some kind of
+         * "parent muxed join".
+         */
+
+        /* Periph1 */
+        clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
+                        U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "uart0");
+
+        clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
+                        U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "uart1");
+
+        clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
+                        U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);
+        clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
+                        U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
+        clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
+                        U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);
+
+        clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
+                        U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "sdi0");
+
+        clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
+                        U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);
+        clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
+                        U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
+        /* FIXME: Redefinition of BIT(3). */
+        clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
+                        U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
+        clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
+                        U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
+
+        /* Periph2 */
+        clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
+                        U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);
+
+        clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
+                        U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "sdi4");
+
+        clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
+                        U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);
+
+        clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
+                        U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "sdi1");
+
+        clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
+                        U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "sdi3");
+
+        /* Note that rate is received from parent. */
+        clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
+                        U8500_CLKRST2_BASE, BIT(6),
+                        CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
+        clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
+                        U8500_CLKRST2_BASE, BIT(7),
+                        CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
+
+        /* Periph3 */
+        clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
+                        U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
+        clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
+                        U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
+        clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
+                        U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
+
+        clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
+                        U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "sdi2");
+
+        clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
+                        U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE);
+
+        clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
+                        U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "uart2");
+
+        clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
+                        U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "sdi5");
+
+        /* Periph6 */
+        clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
+                        U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
+
+}
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
new file mode 100644
index 000000000000..10adfd2ead21
--- /dev/null
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -0,0 +1,21 @@
+/*
+ * Clock definitions for u8540 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/clk-ux500.h>
+
+#include "clk.h"
+
+void u8540_clk_init(void)
+{
+        /* register clocks here */
+}
diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c
new file mode 100644
index 000000000000..dbc0191e16c8
--- /dev/null
+++ b/drivers/clk/ux500/u9540_clk.c
@@ -0,0 +1,21 @@
+/*
+ * Clock definitions for u9540 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/clk-ux500.h>
+
+#include "clk.h"
+
+void u9540_clk_init(void)
+{
+        /* register clocks here */
+}
diff --git a/drivers/clk/versatile/Makefile b/drivers/clk/versatile/Makefile
index 50cf6a2ee693..c0a0f6478798 100644
--- a/drivers/clk/versatile/Makefile
+++ b/drivers/clk/versatile/Makefile
@@ -1,3 +1,4 @@
 # Makefile for Versatile-specific clocks
 obj-$(CONFIG_ICST)              += clk-icst.o
 obj-$(CONFIG_ARCH_INTEGRATOR)   += clk-integrator.o
+obj-$(CONFIG_ARCH_REALVIEW)     += clk-realview.o
diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c
new file mode 100644
index 000000000000..e21a99cef378
--- /dev/null
+++ b/drivers/clk/versatile/clk-realview.c
@@ -0,0 +1,114 @@
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#include "clk-icst.h"
+
+/*
+ * Implementation of the ARM RealView clock trees.
+ */
+
+static void __iomem *sys_lock;
+static void __iomem *sys_vcoreg;
+
+/**
+ * realview_oscvco_get() - get ICST OSC settings for the RealView
+ */
+static struct icst_vco realview_oscvco_get(void)
+{
+        u32 val;
+        struct icst_vco vco;
+
+        val = readl(sys_vcoreg);
+        vco.v = val & 0x1ff;
+        vco.r = (val >> 9) & 0x7f;
+        vco.s = (val >> 16) & 03;
+        return vco;
+}
+
+static void realview_oscvco_set(struct icst_vco vco)
+{
+        u32 val;
+
+        val = readl(sys_vcoreg) & ~0x7ffff;
+        val |= vco.v | (vco.r << 9) | (vco.s << 16);
+
+        /* This magic unlocks the CM VCO so it can be controlled */
+        writel(0xa05f, sys_lock);
+        writel(val, sys_vcoreg);
+        /* This locks the CM again */
+        writel(0, sys_lock);
+}
+
+static const struct icst_params realview_oscvco_params = {
+        .ref            = 24000000,
+        .vco_max        = ICST307_VCO_MAX,
+        .vco_min        = ICST307_VCO_MIN,
+        .vd_min         = 4 + 8,
+        .vd_max         = 511 + 8,
+        .rd_min         = 1 + 2,
+        .rd_max         = 127 + 2,
+        .s2div          = icst307_s2div,
+        .idx2s          = icst307_idx2s,
+};
+
+static const struct clk_icst_desc __initdata realview_icst_desc = {
+        .params = &realview_oscvco_params,
+        .getvco = realview_oscvco_get,
+        .setvco = realview_oscvco_set,
+};
+
+/*
+ * realview_clk_init() - set up the RealView clock tree
+ */
+void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176)
+{
+        struct clk *clk;
+
+        sys_lock = sysbase + REALVIEW_SYS_LOCK_OFFSET;
+        if (is_pb1176)
+                sys_vcoreg = sysbase + REALVIEW_SYS_OSC0_OFFSET;
+        else
+                sys_vcoreg = sysbase + REALVIEW_SYS_OSC4_OFFSET;
+
+
+        /* APB clock dummy */
+        clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+        clk_register_clkdev(clk, "apb_pclk", NULL);
+
+        /* 24 MHz clock */
+        clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
+                                24000000);
+        clk_register_clkdev(clk, NULL, "dev:uart0");
+        clk_register_clkdev(clk, NULL, "dev:uart1");
+        clk_register_clkdev(clk, NULL, "dev:uart2");
+        clk_register_clkdev(clk, NULL, "fpga:kmi0");
+        clk_register_clkdev(clk, NULL, "fpga:kmi1");
+        clk_register_clkdev(clk, NULL, "fpga:mmc0");
+        clk_register_clkdev(clk, NULL, "dev:ssp0");
+        if (is_pb1176) {
+                /*
+                 * UART3 is on the dev chip in PB1176
+                 * UART4 only exists in PB1176
+                 */
+                clk_register_clkdev(clk, NULL, "dev:uart3");
+                clk_register_clkdev(clk, NULL, "dev:uart4");
+        } else
+                clk_register_clkdev(clk, NULL, "fpga:uart3");
+
+
+        /* 1 MHz clock */
+        clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT,
+                                      1000000);
+        clk_register_clkdev(clk, NULL, "sp804");
+
+        /* ICST VCO clock */
+        clk = icst_clk_register(NULL, &realview_icst_desc);
+        clk_register_clkdev(clk, NULL, "dev:clcd");
+        clk_register_clkdev(clk, NULL, "issp:clcd");
+}
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index b65d0c56ab35..d496a55f6bb0 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
 obj-$(CONFIG_DW_APB_TIMER_OF)   += dw_apb_timer_of.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
 obj-$(CONFIG_ARMADA_370_XP_TIMER)       += time-armada-370-xp.o
+obj-$(CONFIG_ARCH_BCM2835)      += bcm2835_timer.o
diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c
new file mode 100644
index 000000000000..bc19f12c20ce
--- /dev/null
+++ b/drivers/clocksource/bcm2835_timer.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2012 Simon Arlott
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/bcm2835_timer.h>
+#include <linux/bitops.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include <asm/sched_clock.h>
+#include <asm/irq.h>
+
+#define REG_CONTROL     0x00
+#define REG_COUNTER_LO  0x04
+#define REG_COUNTER_HI  0x08
+#define REG_COMPARE(n)  (0x0c + (n) * 4)
+#define MAX_TIMER       3
+#define DEFAULT_TIMER   3
+
+struct bcm2835_timer {
+        void __iomem *control;
+        void __iomem *compare;
+        int match_mask;
+        struct clock_event_device evt;
+        struct irqaction act;
+};
+
+static void __iomem *system_clock __read_mostly;
+
+static u32 notrace bcm2835_sched_read(void)
+{
+        return readl_relaxed(system_clock);
+}
+
+static void bcm2835_time_set_mode(enum clock_event_mode mode,
+        struct clock_event_device *evt_dev)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        default:
+                WARN(1, "%s: unhandled event mode %d\n", __func__, mode);
+                break;
+        }
+}
+
+static int bcm2835_time_set_next_event(unsigned long event,
+        struct clock_event_device *evt_dev)
+{
+        struct bcm2835_timer *timer = container_of(evt_dev,
+                struct bcm2835_timer, evt);
+        writel_relaxed(readl_relaxed(system_clock) + event,
+                timer->compare);
+        return 0;
+}
+
+static irqreturn_t bcm2835_time_interrupt(int irq, void *dev_id)
+{
+        struct bcm2835_timer *timer = dev_id;
+        void (*event_handler)(struct clock_event_device *);
+        if (readl_relaxed(timer->control) & timer->match_mask) {
+                writel_relaxed(timer->match_mask, timer->control);
+
+                event_handler = ACCESS_ONCE(timer->evt.event_handler);
+                if (event_handler)
+                        event_handler(&timer->evt);
+                return IRQ_HANDLED;
+        } else {
+                return IRQ_NONE;
+        }
+}
+
+static struct of_device_id bcm2835_time_match[] __initconst = {
+        { .compatible = "brcm,bcm2835-system-timer" },
+        {}
+};
+
+static void __init bcm2835_time_init(void)
+{
+        struct device_node *node;
+        void __iomem *base;
+        u32 freq;
+        int irq;
+        struct bcm2835_timer *timer;
+
+        node = of_find_matching_node(NULL, bcm2835_time_match);
+        if (!node)
+                panic("No bcm2835 timer node");
+
+        base = of_iomap(node, 0);
+        if (!base)
+                panic("Can't remap registers");
+
+        if (of_property_read_u32(node, "clock-frequency", &freq))
+                panic("Can't read clock-frequency");
+
+        system_clock = base + REG_COUNTER_LO;
+        setup_sched_clock(bcm2835_sched_read, 32, freq);
+
+        clocksource_mmio_init(base + REG_COUNTER_LO, node->name,
+                freq, 300, 32, clocksource_mmio_readl_up);
+
+        irq = irq_of_parse_and_map(node, DEFAULT_TIMER);
+        if (irq <= 0)
+                panic("Can't parse IRQ");
+
+        timer = kzalloc(sizeof(*timer), GFP_KERNEL);
+        if (!timer)
+                panic("Can't allocate timer struct\n");
+
+        timer->control = base + REG_CONTROL;
+        timer->compare = base + REG_COMPARE(DEFAULT_TIMER);
+        timer->match_mask = BIT(DEFAULT_TIMER);
+        timer->evt.name = node->name;
+        timer->evt.rating = 300;
+        timer->evt.features = CLOCK_EVT_FEAT_ONESHOT;
+        timer->evt.set_mode = bcm2835_time_set_mode;
+        timer->evt.set_next_event = bcm2835_time_set_next_event;
+        timer->evt.cpumask = cpumask_of(0);
+        timer->act.name = node->name;
+        timer->act.flags = IRQF_TIMER | IRQF_SHARED;
+        timer->act.dev_id = timer;
+        timer->act.handler = bcm2835_time_interrupt;
+
+        if (setup_irq(irq, &timer->act))
+                panic("Can't set up timer IRQ\n");
+
+        clockevents_config_and_register(&timer->evt, freq, 0xf, 0xffffffff);
+
+        pr_info("bcm2835: system timer (irq = %d)\n", irq);
+}
+
+struct sys_timer bcm2835_timer = {
+        .init = bcm2835_time_init,
+};
diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c
index 21c1a87032b7..24ccae453e79 100644
--- a/drivers/crypto/mv_cesa.c
+++ b/drivers/crypto/mv_cesa.c
@@ -19,6 +19,9 @@
 #include <linux/clk.h>
 #include <crypto/internal/hash.h>
 #include <crypto/sha.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
 
 #include "mv_cesa.h"
 
@@ -1062,7 +1065,10 @@ static int mv_probe(struct platform_device *pdev)
                 goto err_unmap_reg;
         }
 
-        irq = platform_get_irq(pdev, 0);
+        if (pdev->dev.of_node)
+                irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+        else
+                irq = platform_get_irq(pdev, 0);
         if (irq < 0 || irq == NO_IRQ) {
                 ret = irq;
                 goto err_unmap_sram;
@@ -1170,12 +1176,19 @@ static int mv_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id mv_cesa_of_match_table[] = {
+        { .compatible = "marvell,orion-crypto", },
+        {}
+};
+MODULE_DEVICE_TABLE(of, mv_cesa_of_match_table);
+
 static struct platform_driver marvell_crypto = {
         .probe          = mv_probe,
-        .remove         = mv_remove,
+        .remove         = __devexit_p(mv_remove),
         .driver         = {
                 .owner  = THIS_MODULE,
                 .name   = "mv_crypto",
+                .of_match_table = of_match_ptr(mv_cesa_of_match_table),
         },
 };
 MODULE_ALIAS("platform:mv_crypto");
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 1c307e1b840c..ef17e3871c71 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -32,7 +32,7 @@
 
 #include <plat/ste_dma40.h>
 
-#include <mach/crypto-ux500.h>
+#include <linux/platform_data/crypto-ux500.h>
 #include <mach/hardware.h>
 
 #include "cryp_p.h"
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 08d5032cb564..08765072a2b3 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -31,7 +31,7 @@
 #include <crypto/scatterwalk.h>
 #include <crypto/algapi.h>
 
-#include <mach/crypto-ux500.h>
+#include <linux/platform_data/crypto-ux500.h>
 #include <mach/hardware.h>
 
 #include "hash_alg.h"
diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
index 8a6c8e8b2940..116e4adffb08 100644
--- a/drivers/dma/at_hdmac_regs.h
+++ b/drivers/dma/at_hdmac_regs.h
@@ -11,7 +11,7 @@
 #ifndef AT_HDMAC_REGS_H
 #define AT_HDMAC_REGS_H
 
-#include <mach/at_hdmac.h>
+#include <linux/platform_data/dma-atmel.h>
 
 #define AT_DMA_MAX_NR_CHANNELS  8
 
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index c64917ec313d..4aeaea77f72e 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -26,7 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <mach/dma.h>
+#include <linux/platform_data/dma-ep93xx.h>
 
 #include "dmaengine.h"
 
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 5084975d793c..b90aaec4ccc4 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -28,7 +28,7 @@
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/dma.h>
+#include <linux/platform_data/dma-imx.h>
 #include <mach/hardware.h>
 
 #include "dmaengine.h"
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1dc2a4ad0026..1b781d6ac425 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -38,8 +38,8 @@
 #include <linux/of_device.h>
 
 #include <asm/irq.h>
-#include <mach/sdma.h>
-#include <mach/dma.h>
+#include <linux/platform_data/dma-imx-sdma.h>
+#include <linux/platform_data/dma-imx.h>
 #include <mach/hardware.h>
 
 #include "dmaengine.h"
diff --git a/drivers/dma/mmp_tdma.c b/drivers/dma/mmp_tdma.c
index 8a15cf2163dc..07fa48688ba9 100644
--- a/drivers/dma/mmp_tdma.c
+++ b/drivers/dma/mmp_tdma.c
@@ -19,7 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/device.h>
 #include <mach/regs-icu.h>
-#include <mach/sram.h>
+#include <linux/platform_data/dma-mmp_tdma.h>
 
 #include "dmaengine.h"
 
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 0b12e68bf79c..e362e2b80efb 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -26,7 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/memory.h>
 #include <linux/clk.h>
-#include <plat/mv_xor.h>
+#include <linux/platform_data/dma-mv_xor.h>
 
 #include "dmaengine.h"
 #include "mv_xor.h"
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index ba7926f5c099..66a59510887f 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -150,6 +150,12 @@ config GPIO_MSM_V2
           Qualcomm MSM chips.  Most of the pins on the MSM can be
           selected for GPIO, and are controlled by this driver.
 
+config GPIO_MVEBU
+        def_bool y
+        depends on ARCH_MVEBU
+        select GPIO_GENERIC
+        select GENERIC_IRQ_CHIP
+
 config GPIO_MXC
         def_bool y
         depends on ARCH_MXC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 153caceeb053..1a33e6716e10 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_GPIO_MPC8XXX)	+= gpio-mpc8xxx.o
 obj-$(CONFIG_GPIO_MSIC)         += gpio-msic.o
 obj-$(CONFIG_GPIO_MSM_V1)       += gpio-msm-v1.o
 obj-$(CONFIG_GPIO_MSM_V2)       += gpio-msm-v2.o
+obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
 obj-$(CONFIG_GPIO_MXC)          += gpio-mxc.o
 obj-$(CONFIG_GPIO_MXS)          += gpio-mxs.o
 obj-$(CONFIG_ARCH_OMAP)         += gpio-omap.o
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
new file mode 100644
index 000000000000..902af437eaf2
--- /dev/null
+++ b/drivers/gpio/gpio-mvebu.c
@@ -0,0 +1,679 @@
+/*
+ * GPIO driver for Marvell SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This driver is a fairly straightforward GPIO driver for the
+ * complete family of Marvell EBU SoC platforms (Orion, Dove,
+ * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
+ * driver is the different register layout that exists between the
+ * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
+ * platforms (MV78200 from the Discovery family and the Armada
+ * XP). Therefore, this driver handles three variants of the GPIO
+ * block:
+ * - the basic variant, called "orion-gpio", with the simplest
+ *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
+ *   non-SMP Discovery systems
+ * - the mv78200 variant for MV78200 Discovery systems. This variant
+ *   turns the edge mask and level mask registers into CPU0 edge
+ *   mask/level mask registers, and adds CPU1 edge mask/level mask
+ *   registers.
+ * - the armadaxp variant for Armada XP systems. This variant keeps
+ *   the normal cause/edge mask/level mask registers when the global
+ *   interrupts are used, but adds per-CPU cause/edge mask/level mask
+ *   registers n a separate memory area for the per-CPU GPIO
+ *   interrupts.
+ */
+
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
+
+/*
+ * GPIO unit register offsets.
+ */
+#define GPIO_OUT_OFF            0x0000
+#define GPIO_IO_CONF_OFF        0x0004
+#define GPIO_BLINK_EN_OFF       0x0008
+#define GPIO_IN_POL_OFF         0x000c
+#define GPIO_DATA_IN_OFF        0x0010
+#define GPIO_EDGE_CAUSE_OFF     0x0014
+#define GPIO_EDGE_MASK_OFF      0x0018
+#define GPIO_LEVEL_MASK_OFF     0x001c
+
+/* The MV78200 has per-CPU registers for edge mask and level mask */
+#define GPIO_EDGE_MASK_MV78200_OFF(cpu)   ((cpu) ? 0x30 : 0x18)
+#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
+
+/* The Armada XP has per-CPU registers for interrupt cause, interrupt
+ * mask and interrupt level mask. Those are relative to the
+ * percpu_membase. */
+#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
+#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
+#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
+
+#define MVEBU_GPIO_SOC_VARIANT_ORION    0x1
+#define MVEBU_GPIO_SOC_VARIANT_MV78200  0x2
+#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
+
+#define MVEBU_MAX_GPIO_PER_BANK         32
+
+struct mvebu_gpio_chip {
+        struct gpio_chip   chip;
+        spinlock_t         lock;
+        void __iomem      *membase;
+        void __iomem      *percpu_membase;
+        unsigned int       irqbase;
+        struct irq_domain *domain;
+        int                soc_variant;
+};
+
+/*
+ * Functions returning addresses of individual registers for a given
+ * GPIO controller.
+ */
+static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
+{
+        return mvchip->membase + GPIO_OUT_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
+{
+        return mvchip->membase + GPIO_IO_CONF_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
+{
+        return mvchip->membase + GPIO_IN_POL_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
+{
+        return mvchip->membase + GPIO_DATA_IN_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
+{
+        int cpu;
+
+        switch(mvchip->soc_variant) {
+        case MVEBU_GPIO_SOC_VARIANT_ORION:
+        case MVEBU_GPIO_SOC_VARIANT_MV78200:
+                return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
+        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+                cpu = smp_processor_id();
+                return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
+        default:
+                BUG();
+        }
+}
+
+static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
+{
+        int cpu;
+
+        switch(mvchip->soc_variant) {
+        case MVEBU_GPIO_SOC_VARIANT_ORION:
+                return mvchip->membase + GPIO_EDGE_MASK_OFF;
+        case MVEBU_GPIO_SOC_VARIANT_MV78200:
+                cpu = smp_processor_id();
+                return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
+        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+                cpu = smp_processor_id();
+                return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
+        default:
+                BUG();
+        }
+}
+
+static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
+{
+        int cpu;
+
+        switch(mvchip->soc_variant) {
+        case MVEBU_GPIO_SOC_VARIANT_ORION:
+                return mvchip->membase + GPIO_LEVEL_MASK_OFF;
+        case MVEBU_GPIO_SOC_VARIANT_MV78200:
+                cpu = smp_processor_id();
+                return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
+        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+                cpu = smp_processor_id();
+                return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
+        default:
+                BUG();
+        }
+}
+
+/*
+ * Functions implementing the gpio_chip methods
+ */
+
+int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+        return pinctrl_request_gpio(chip->base + pin);
+}
+
+void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
+{
+        pinctrl_free_gpio(chip->base + pin);
+}
+
+static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        unsigned long flags;
+        u32 u;
+
+        spin_lock_irqsave(&mvchip->lock, flags);
+        u = readl_relaxed(mvebu_gpioreg_out(mvchip));
+        if (value)
+                u |= 1 << pin;
+        else
+                u &= ~(1 << pin);
+        writel_relaxed(u, mvebu_gpioreg_out(mvchip));
+        spin_unlock_irqrestore(&mvchip->lock, flags);
+}
+
+static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        u32 u;
+
+        if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
+                u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
+                        readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+        } else {
+                u = readl_relaxed(mvebu_gpioreg_out(mvchip));
+        }
+
+        return (u >> pin) & 1;
+}
+
+static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        unsigned long flags;
+        int ret;
+        u32 u;
+
+        /* Check with the pinctrl driver whether this pin is usable as
+         * an input GPIO */
+        ret = pinctrl_gpio_direction_input(chip->base + pin);
+        if (ret)
+                return ret;
+
+        spin_lock_irqsave(&mvchip->lock, flags);
+        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
+        u |= 1 << pin;
+        writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
+        spin_unlock_irqrestore(&mvchip->lock, flags);
+
+        return 0;
+}
+
+static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
+                                       int value)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        unsigned long flags;
+        int ret;
+        u32 u;
+
+        /* Check with the pinctrl driver whether this pin is usable as
+         * an output GPIO */
+        ret = pinctrl_gpio_direction_output(chip->base + pin);
+        if (ret)
+                return ret;
+
+        spin_lock_irqsave(&mvchip->lock, flags);
+        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
+        u &= ~(1 << pin);
+        writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
+        spin_unlock_irqrestore(&mvchip->lock, flags);
+
+        return 0;
+}
+
+static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        return irq_create_mapping(mvchip->domain, pin);
+}
+
+/*
+ * Functions implementing the irq_chip methods
+ */
+static void mvebu_gpio_irq_ack(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = ~(1 << (d->irq - gc->irq_base));
+
+        irq_gc_lock(gc);
+        writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
+        irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = 1 << (d->irq - gc->irq_base);
+
+        irq_gc_lock(gc);
+        gc->mask_cache &= ~mask;
+        writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
+        irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = 1 << (d->irq - gc->irq_base);
+
+        irq_gc_lock(gc);
+        gc->mask_cache |= mask;
+        writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
+        irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_mask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = 1 << (d->irq - gc->irq_base);
+
+        irq_gc_lock(gc);
+        gc->mask_cache &= ~mask;
+        writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
+        irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = 1 << (d->irq - gc->irq_base);
+
+        irq_gc_lock(gc);
+        gc->mask_cache |= mask;
+        writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
+        irq_gc_unlock(gc);
+}
+
+/*****************************************************************************
+ * MVEBU GPIO IRQ
+ *
+ * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
+ * value of the line or the opposite value.
+ *
+ * Level IRQ handlers: DATA_IN is used directly as cause register.
+ *                     Interrupt are masked by LEVEL_MASK registers.
+ * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
+ *                     Interrupt are masked by EDGE_MASK registers.
+ * Both-edge handlers: Similar to regular Edge handlers, but also swaps
+ *                     the polarity to catch the next line transaction.
+ *                     This is a race condition that might not perfectly
+ *                     work on some use cases.
+ *
+ * Every eight GPIO lines are grouped (OR'ed) before going up to main
+ * cause register.
+ *
+ *                    EDGE  cause    mask
+ *        data-in   /--------| |-----| |----\
+ *     -----| |-----                         ---- to main cause reg
+ *           X      \----------------| |----/
+ *        polarity    LEVEL          mask
+ *
+ ****************************************************************************/
+
+static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = irq_data_get_chip_type(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        int pin;
+        u32 u;
+
+        pin = d->hwirq;
+
+        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
+        if (!u) {
+                return -EINVAL;
+        }
+
+        type &= IRQ_TYPE_SENSE_MASK;
+        if (type == IRQ_TYPE_NONE)
+                return -EINVAL;
+
+        /* Check if we need to change chip and handler */
+        if (!(ct->type & type))
+                if (irq_setup_alt_chip(d, type))
+                        return -EINVAL;
+
+        /*
+         * Configure interrupt polarity.
+         */
+        switch(type) {
+        case IRQ_TYPE_EDGE_RISING:
+        case IRQ_TYPE_LEVEL_HIGH:
+                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+                u &= ~(1 << pin);
+                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+        case IRQ_TYPE_EDGE_FALLING:
+        case IRQ_TYPE_LEVEL_LOW:
+                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+                u |= 1 << pin;
+                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+        case IRQ_TYPE_EDGE_BOTH: {
+                u32 v;
+
+                v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
+                        readl_relaxed(mvebu_gpioreg_data_in(mvchip));
+
+                /*
+                 * set initial polarity based on current input level
+                 */
+                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+                if (v & (1 << pin))
+                        u |= 1 << pin;          /* falling */
+                else
+                        u &= ~(1 << pin);       /* rising */
+                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+        }
+        }
+        return 0;
+}
+
+static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
+        u32 cause, type;
+        int i;
+
+        if (mvchip == NULL)
+                return;
+
+        cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
+                readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
+        cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
+                readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
+
+        for (i = 0; i < mvchip->chip.ngpio; i++) {
+                int irq;
+
+                irq = mvchip->irqbase + i;
+
+                if (!(cause & (1 << i)))
+                        continue;
+
+                type = irqd_get_trigger_type(irq_get_irq_data(irq));
+                if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+                        /* Swap polarity (race with GPIO line) */
+                        u32 polarity;
+
+                        polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+                        polarity ^= 1 << i;
+                        writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
+                }
+                generic_handle_irq(irq);
+        }
+}
+
+static struct platform_device_id mvebu_gpio_ids[] = {
+        {
+                .name = "orion-gpio",
+        }, {
+                .name = "mv78200-gpio",
+        }, {
+                .name = "armadaxp-gpio",
+        }, {
+                /* sentinel */
+        },
+};
+MODULE_DEVICE_TABLE(platform, mvebu_gpio_ids);
+
+static struct of_device_id mvebu_gpio_of_match[] __devinitdata = {
+        {
+                .compatible = "marvell,orion-gpio",
+                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_ORION,
+        },
+        {
+                .compatible = "marvell,mv78200-gpio",
+                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200,
+        },
+        {
+                .compatible = "marvell,armadaxp-gpio",
+                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
+        },
+        {
+                /* sentinel */
+        },
+};
+MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
+
+static int __devinit mvebu_gpio_probe(struct platform_device *pdev)
+{
+        struct mvebu_gpio_chip *mvchip;
+        const struct of_device_id *match;
+        struct device_node *np = pdev->dev.of_node;
+        struct resource *res;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        unsigned int ngpios;
+        int soc_variant;
+        int i, cpu, id;
+
+        match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
+        if (match)
+                soc_variant = (int) match->data;
+        else
+                soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (! res) {
+                dev_err(&pdev->dev, "Cannot get memory resource\n");
+                return -ENODEV;
+        }
+
+        mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
+        if (! mvchip){
+                dev_err(&pdev->dev, "Cannot allocate memory\n");
+                return -ENOMEM;
+        }
+
+        if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
+                dev_err(&pdev->dev, "Missing ngpios OF property\n");
+                return -ENODEV;
+        }
+
+        id = of_alias_get_id(pdev->dev.of_node, "gpio");
+        if (id < 0) {
+                dev_err(&pdev->dev, "Couldn't get OF id\n");
+                return id;
+        }
+
+        mvchip->soc_variant = soc_variant;
+        mvchip->chip.label = dev_name(&pdev->dev);
+        mvchip->chip.dev = &pdev->dev;
+        mvchip->chip.request = mvebu_gpio_request;
+        mvchip->chip.direction_input = mvebu_gpio_direction_input;
+        mvchip->chip.get = mvebu_gpio_get;
+        mvchip->chip.direction_output = mvebu_gpio_direction_output;
+        mvchip->chip.set = mvebu_gpio_set;
+        mvchip->chip.to_irq = mvebu_gpio_to_irq;
+        mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
+        mvchip->chip.ngpio = ngpios;
+        mvchip->chip.can_sleep = 0;
+#ifdef CONFIG_OF
+        mvchip->chip.of_node = np;
+#endif
+
+        spin_lock_init(&mvchip->lock);
+        mvchip->membase = devm_request_and_ioremap(&pdev->dev, res);
+        if (! mvchip->membase) {
+                dev_err(&pdev->dev, "Cannot ioremap\n");
+                kfree(mvchip->chip.label);
+                return -ENOMEM;
+        }
+
+        /* The Armada XP has a second range of registers for the
+         * per-CPU registers */
+        if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
+                res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+                if (! res) {
+                        dev_err(&pdev->dev, "Cannot get memory resource\n");
+                        kfree(mvchip->chip.label);
+                        return -ENODEV;
+                }
+
+                mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res);
+                if (! mvchip->percpu_membase) {
+                        dev_err(&pdev->dev, "Cannot ioremap\n");
+                        kfree(mvchip->chip.label);
+                        return -ENOMEM;
+                }
+        }
+
+        /*
+         * Mask and clear GPIO interrupts.
+         */
+        switch(soc_variant) {
+        case MVEBU_GPIO_SOC_VARIANT_ORION:
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+                writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+                break;
+        case MVEBU_GPIO_SOC_VARIANT_MV78200:
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+                for (cpu = 0; cpu < 2; cpu++) {
+                        writel_relaxed(0, mvchip->membase +
+                                       GPIO_EDGE_MASK_MV78200_OFF(cpu));
+                        writel_relaxed(0, mvchip->membase +
+                                       GPIO_LEVEL_MASK_MV78200_OFF(cpu));
+                }
+                break;
+        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+                writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+                for (cpu = 0; cpu < 4; cpu++) {
+                        writel_relaxed(0, mvchip->percpu_membase +
+                                       GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
+                        writel_relaxed(0, mvchip->percpu_membase +
+                                       GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
+                        writel_relaxed(0, mvchip->percpu_membase +
+                                       GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
+                }
+                break;
+        default:
+                BUG();
+        }
+
+        gpiochip_add(&mvchip->chip);
+
+        /* Some gpio controllers do not provide irq support */
+        if (!of_irq_count(np))
+                return 0;
+
+        /* Setup the interrupt handlers. Each chip can have up to 4
+         * interrupt handlers, with each handler dealing with 8 GPIO
+         * pins. */
+        for (i = 0; i < 4; i++) {
+                int irq;
+                irq = platform_get_irq(pdev, i);
+                if (irq < 0)
+                        continue;
+                irq_set_handler_data(irq, mvchip);
+                irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
+        }
+
+        mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
+        if (mvchip->irqbase < 0) {
+                dev_err(&pdev->dev, "no irqs\n");
+                kfree(mvchip->chip.label);
+                return -ENOMEM;
+        }
+
+        gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
+                                    mvchip->membase, handle_level_irq);
+        if (! gc) {
+                dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
+                kfree(mvchip->chip.label);
+                return -ENOMEM;
+        }
+
+        gc->private = mvchip;
+        ct = &gc->chip_types[0];
+        ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
+        ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
+        ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
+        ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+        ct->chip.name = mvchip->chip.label;
+
+        ct = &gc->chip_types[1];
+        ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+        ct->chip.irq_ack = mvebu_gpio_irq_ack;
+        ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
+        ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
+        ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+        ct->handler = handle_edge_irq;
+        ct->chip.name = mvchip->chip.label;
+
+        irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
+
+        /* Setup irq domain on top of the generic chip. */
+        mvchip->domain = irq_domain_add_legacy(np, mvchip->chip.ngpio,
+                                               mvchip->irqbase, 0,
+                                               &irq_domain_simple_ops,
+                                               mvchip);
+        if (!mvchip->domain) {
+                dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
+                        mvchip->chip.label);
+                irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
+                                        IRQ_LEVEL | IRQ_NOPROBE);
+                kfree(gc);
+                kfree(mvchip->chip.label);
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+static struct platform_driver mvebu_gpio_driver = {
+        .driver         = {
+                .name           = "mvebu-gpio",
+                .owner          = THIS_MODULE,
+                .of_match_table = mvebu_gpio_of_match,
+        },
+        .probe          = mvebu_gpio_probe,
+        .id_table       = mvebu_gpio_ids,
+};
+
+static int __init mvebu_gpio_init(void)
+{
+        return platform_driver_register(&mvebu_gpio_driver);
+}
+postcore_initcall(mvebu_gpio_init);
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 9cac88a65f78..9528779ca463 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -26,6 +26,8 @@
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
+#include <asm/mach/irq.h>
+
 #include <mach/irqs.h>
 
 /*
@@ -59,6 +61,7 @@
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 
 int pxa_last_gpio;
+static int irq_base;
 
 #ifdef CONFIG_OF
 static struct irq_domain *domain;
@@ -167,63 +170,14 @@ static inline int __gpio_is_occupied(unsigned gpio)
         return ret;
 }
 
-#ifdef CONFIG_ARCH_PXA
-static inline int __pxa_gpio_to_irq(int gpio)
-{
-        if (gpio_is_pxa_type(gpio_type))
-                return PXA_GPIO_TO_IRQ(gpio);
-        return -1;
-}
-
-static inline int __pxa_irq_to_gpio(int irq)
-{
-        if (gpio_is_pxa_type(gpio_type))
-                return irq - PXA_GPIO_TO_IRQ(0);
-        return -1;
-}
-#else
-static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
-static inline int __pxa_irq_to_gpio(int irq) { return -1; }
-#endif
-
-#ifdef CONFIG_ARCH_MMP
-static inline int __mmp_gpio_to_irq(int gpio)
-{
-        if (gpio_is_mmp_type(gpio_type))
-                return MMP_GPIO_TO_IRQ(gpio);
-        return -1;
-}
-
-static inline int __mmp_irq_to_gpio(int irq)
-{
-        if (gpio_is_mmp_type(gpio_type))
-                return irq - MMP_GPIO_TO_IRQ(0);
-        return -1;
-}
-#else
-static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
-static inline int __mmp_irq_to_gpio(int irq) { return -1; }
-#endif
-
 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
-        int gpio, ret;
-
-        gpio = chip->base + offset;
-        ret = __pxa_gpio_to_irq(gpio);
-        if (ret >= 0)
-                return ret;
-        return __mmp_gpio_to_irq(gpio);
+        return chip->base + offset + irq_base;
 }
 
 int pxa_irq_to_gpio(int irq)
 {
-        int ret;
-
-        ret = __pxa_irq_to_gpio(irq);
-        if (ret >= 0)
-                return ret;
-        return __mmp_irq_to_gpio(irq);
+        return irq - irq_base;
 }
 
 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -403,6 +357,9 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
         struct pxa_gpio_chip *c;
         int loop, gpio, gpio_base, n;
         unsigned long gedr;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+
+        chained_irq_enter(chip, desc);
 
         do {
                 loop = 0;
@@ -422,6 +379,8 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
                         }
                 }
         } while (loop);
+
+        chained_irq_exit(chip, desc);
 }
 
 static void pxa_ack_muxed_gpio(struct irq_data *d)
@@ -535,7 +494,7 @@ const struct irq_domain_ops pxa_irq_domain_ops = {
 
 static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
 {
-        int ret, nr_banks, nr_gpios, irq_base;
+        int ret, nr_banks, nr_gpios;
         struct device_node *prev, *next, *np = pdev->dev.of_node;
         const struct of_device_id *of_id =
                                 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
@@ -590,10 +549,20 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
         int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
 
         ret = pxa_gpio_probe_dt(pdev);
-        if (ret < 0)
+        if (ret < 0) {
                 pxa_last_gpio = pxa_gpio_nums();
-        else
+#ifdef CONFIG_ARCH_PXA
+                if (gpio_is_pxa_type(gpio_type))
+                        irq_base = PXA_GPIO_TO_IRQ(0);
+#endif
+#ifdef CONFIG_ARCH_MMP
+                if (gpio_is_mmp_type(gpio_type))
+                        irq_base = MMP_GPIO_TO_IRQ(0);
+#endif
+        } else {
                 use_of = 1;
+        }
+
         if (!pxa_last_gpio)
                 return -EINVAL;
 
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index ba126cc04073..8af4b06e80f7 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
                 s3c_gpiolib_track(chip);
 }
 
+#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
+static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
+                        const struct of_phandle_args *gpiospec, u32 *flags)
+{
+        unsigned int pin;
+
+        if (WARN_ON(gc->of_gpio_n_cells < 3))
+                return -EINVAL;
+
+        if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
+                return -EINVAL;
+
+        if (gpiospec->args[0] > gc->ngpio)
+                return -EINVAL;
+
+        pin = gc->base + gpiospec->args[0];
+
+        if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
+                pr_warn("gpio_xlate: failed to set pin function\n");
+        if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
+                pr_warn("gpio_xlate: failed to set pin pull up/down\n");
+
+        if (flags)
+                *flags = gpiospec->args[2] >> 16;
+
+        return gpiospec->args[0];
+}
+
+static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
+        { .compatible = "samsung,s3c24xx-gpio", },
+        {}
+};
+
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+                                                 u64 base, u64 offset)
+{
+        struct gpio_chip *gc =  &chip->chip;
+        u64 address;
+
+        if (!of_have_populated_dt())
+                return;
+
+        address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
+        gc->of_node = of_find_matching_node_by_address(NULL,
+                        s3c24xx_gpio_dt_match, address);
+        if (!gc->of_node) {
+                pr_info("gpio: device tree node not found for gpio controller"
+                        " with base address %08llx\n", address);
+                return;
+        }
+        gc->of_gpio_n_cells = 3;
+        gc->of_xlate = s3c24xx_gpio_xlate;
+}
+#else
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+                                                 u64 base, u64 offset)
+{
+        return;
+}
+#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
+
 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
                                              int nr_chips, void __iomem *base)
 {
@@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
                         gc->direction_output = samsung_gpiolib_2bit_output;
 
                 samsung_gpiolib_add(chip);
+
+                s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
         }
 }
 
@@ -3131,46 +3194,6 @@ samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
 }
 EXPORT_SYMBOL(s3c_gpio_getpull);
 
-/* gpiolib wrappers until these are totally eliminated */
-
-void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
-{
-        int ret;
-
-        WARN_ON(to);    /* should be none of these left */
-
-        if (!to) {
-                /* if pull is enabled, try first with up, and if that
-                 * fails, try using down */
-
-                ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
-                if (ret)
-                        s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
-        } else {
-                s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
-        }
-}
-EXPORT_SYMBOL(s3c2410_gpio_pullup);
-
-void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
-{
-        /* do this via gpiolib until all users removed */
-
-        gpio_request(pin, "temporary");
-        gpio_set_value(pin, to);
-        gpio_free(pin);
-}
-EXPORT_SYMBOL(s3c2410_gpio_setpin);
-
-unsigned int s3c2410_gpio_getpin(unsigned int pin)
-{
-        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-        unsigned long offs = pin - chip->chip.base;
-
-        return __raw_readl(chip->base + 0x04) & (1 << offs);
-}
-EXPORT_SYMBOL(s3c2410_gpio_getpin);
-
 #ifdef CONFIG_S5P_GPIO_DRVSTR
 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
 {
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index dc5184d57892..d982593d7563 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -30,9 +30,6 @@
 
 #include <asm/mach/irq.h>
 
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
 #define GPIO_BANK(x)            ((x) >> 5)
 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
 #define GPIO_BIT(x)             ((x) & 0x7)
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index f030880bc9bb..c5f8ca233e1f 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -396,6 +396,29 @@ static int __devinit gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
 
 static int gpio_twl4030_remove(struct platform_device *pdev);
 
+static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev)
+{
+        struct twl4030_gpio_platform_data *omap_twl_info;
+
+        omap_twl_info = devm_kzalloc(dev, sizeof(*omap_twl_info), GFP_KERNEL);
+        if (!omap_twl_info)
+                return NULL;
+
+        omap_twl_info->use_leds = of_property_read_bool(dev->of_node,
+                        "ti,use-leds");
+
+        of_property_read_u32(dev->of_node, "ti,debounce",
+                             &omap_twl_info->debounce);
+        of_property_read_u32(dev->of_node, "ti,mmc-cd",
+                             (u32 *)&omap_twl_info->mmc_cd);
+        of_property_read_u32(dev->of_node, "ti,pullups",
+                             &omap_twl_info->pullups);
+        of_property_read_u32(dev->of_node, "ti,pulldowns",
+                             &omap_twl_info->pulldowns);
+
+        return omap_twl_info;
+}
+
 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
 {
         struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
@@ -428,33 +451,37 @@ no_irqs:
         twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
         twl_gpiochip.dev = &pdev->dev;
 
-        if (pdata) {
-                /*
-                 * NOTE:  boards may waste power if they don't set pullups
-                 * and pulldowns correctly ... default for non-ULPI pins is
-                 * pulldown, and some other pins may have external pullups
-                 * or pulldowns.  Careful!
-                 */
-                ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
-                if (ret)
-                        dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
-                                        pdata->pullups, pdata->pulldowns,
-                                        ret);
-
-                ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
-                if (ret)
-                        dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
-                                        pdata->debounce, pdata->mmc_cd,
-                                        ret);
-
-                /*
-                 * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
-                 * is (still) clear if use_leds is set.
-                 */
-                if (pdata->use_leds)
-                        twl_gpiochip.ngpio += 2;
+        if (node)
+                pdata = of_gpio_twl4030(&pdev->dev);
+
+        if (pdata == NULL) {
+                dev_err(&pdev->dev, "Platform data is missing\n");
+                return -ENXIO;
         }
 
+        /*
+         * NOTE:  boards may waste power if they don't set pullups
+         * and pulldowns correctly ... default for non-ULPI pins is
+         * pulldown, and some other pins may have external pullups
+         * or pulldowns.  Careful!
+         */
+        ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
+        if (ret)
+                dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
+                        pdata->pullups, pdata->pulldowns, ret);
+
+        ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
+        if (ret)
+                dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
+                        pdata->debounce, pdata->mmc_cd, ret);
+
+        /*
+         * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
+         * is (still) clear if use_leds is set.
+         */
+        if (pdata->use_leds)
+                twl_gpiochip.ngpio += 2;
+
         ret = gpiochip_add(&twl_gpiochip);
         if (ret < 0) {
                 dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
diff --git a/drivers/hwmon/gpio-fan.c b/drivers/hwmon/gpio-fan.c
index 2f4b01bda87c..36509ae32083 100644
--- a/drivers/hwmon/gpio-fan.c
+++ b/drivers/hwmon/gpio-fan.c
@@ -31,6 +31,8 @@
 #include <linux/hwmon.h>
 #include <linux/gpio.h>
 #include <linux/gpio-fan.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
 
 struct gpio_fan_data {
         struct platform_device  *pdev;
@@ -400,14 +402,131 @@ static ssize_t show_name(struct device *dev,
 
 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
 
+
+#ifdef CONFIG_OF_GPIO
+/*
+ * Translate OpenFirmware node properties into platform_data
+ */
+static int gpio_fan_get_of_pdata(struct device *dev,
+                            struct gpio_fan_platform_data *pdata)
+{
+        struct device_node *node;
+        struct gpio_fan_speed *speed;
+        unsigned *ctrl;
+        unsigned i;
+        u32 u;
+        struct property *prop;
+        const __be32 *p;
+
+        node = dev->of_node;
+
+        /* Fill GPIO pin array */
+        pdata->num_ctrl = of_gpio_count(node);
+        if (!pdata->num_ctrl) {
+                dev_err(dev, "gpios DT property empty / missing");
+                return -ENODEV;
+        }
+        ctrl = devm_kzalloc(dev, pdata->num_ctrl * sizeof(unsigned),
+                                GFP_KERNEL);
+        if (!ctrl)
+                return -ENOMEM;
+        for (i = 0; i < pdata->num_ctrl; i++) {
+                int val;
+
+                val = of_get_gpio(node, i);
+                if (val < 0)
+                        return val;
+                ctrl[i] = val;
+        }
+        pdata->ctrl = ctrl;
+
+        /* Get number of RPM/ctrl_val pairs in speed map */
+        prop = of_find_property(node, "gpio-fan,speed-map", &i);
+        if (!prop) {
+                dev_err(dev, "gpio-fan,speed-map DT property missing");
+                return -ENODEV;
+        }
+        i = i / sizeof(u32);
+        if (i == 0 || i & 1) {
+                dev_err(dev, "gpio-fan,speed-map contains zero/odd number of entries");
+                return -ENODEV;
+        }
+        pdata->num_speed = i / 2;
+
+        /*
+         * Populate speed map
+         * Speed map is in the form <RPM ctrl_val RPM ctrl_val ...>
+         * this needs splitting into pairs to create gpio_fan_speed structs
+         */
+        speed = devm_kzalloc(dev,
+                        pdata->num_speed * sizeof(struct gpio_fan_speed),
+                        GFP_KERNEL);
+        if (!speed)
+                return -ENOMEM;
+        p = NULL;
+        for (i = 0; i < pdata->num_speed; i++) {
+                p = of_prop_next_u32(prop, p, &u);
+                if (!p)
+                        return -ENODEV;
+                speed[i].rpm = u;
+                p = of_prop_next_u32(prop, p, &u);
+                if (!p)
+                        return -ENODEV;
+                speed[i].ctrl_val = u;
+        }
+        pdata->speed = speed;
+
+        /* Alarm GPIO if one exists */
+        if (of_gpio_named_count(node, "alarm-gpios")) {
+                struct gpio_fan_alarm *alarm;
+                int val;
+                enum of_gpio_flags flags;
+
+                alarm = devm_kzalloc(dev, sizeof(struct gpio_fan_alarm),
+                                        GFP_KERNEL);
+                if (!alarm)
+                        return -ENOMEM;
+
+                val = of_get_named_gpio_flags(node, "alarm-gpios", 0, &flags);
+                if (val < 0)
+                        return val;
+                alarm->gpio = val;
+                alarm->active_low = flags & OF_GPIO_ACTIVE_LOW;
+
+                pdata->alarm = alarm;
+        }
+
+        return 0;
+}
+
+static struct of_device_id of_gpio_fan_match[] __devinitdata = {
+        { .compatible = "gpio-fan", },
+        {},
+};
+#endif /* CONFIG_OF_GPIO */
+
 static int __devinit gpio_fan_probe(struct platform_device *pdev)
 {
         int err;
         struct gpio_fan_data *fan_data;
         struct gpio_fan_platform_data *pdata = pdev->dev.platform_data;
 
+#ifdef CONFIG_OF_GPIO
+        if (!pdata) {
+                pdata = devm_kzalloc(&pdev->dev,
+                                        sizeof(struct gpio_fan_platform_data),
+                                        GFP_KERNEL);
+                if (!pdata)
+                        return -ENOMEM;
+
+                err = gpio_fan_get_of_pdata(&pdev->dev, pdata);
+                if (err)
+                        return err;
+        }
+#else /* CONFIG_OF_GPIO */
         if (!pdata)
                 return -EINVAL;
+#endif /* CONFIG_OF_GPIO */
 
         fan_data = devm_kzalloc(&pdev->dev, sizeof(struct gpio_fan_data),
                                 GFP_KERNEL);
@@ -511,6 +630,7 @@ static struct platform_driver gpio_fan_driver = {
         .driver = {
                 .name   = "gpio-fan",
                 .pm     = GPIO_FAN_PM,
+                .of_match_table = of_match_ptr(of_gpio_fan_match),
         },
 };
 
diff --git a/drivers/hwmon/s3c-hwmon.c b/drivers/hwmon/s3c-hwmon.c
index b7975f858cff..fe11b95670bd 100644
--- a/drivers/hwmon/s3c-hwmon.c
+++ b/drivers/hwmon/s3c-hwmon.c
@@ -34,7 +34,7 @@
 #include <linux/hwmon-sysfs.h>
 
 #include <plat/adc.h>
-#include <plat/hwmon.h>
+#include <linux/platform_data/hwmon-s3c.h>
 
 struct s3c_hwmon_attr {
         struct sensor_device_attribute  in;
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 970a1612e795..42d9fdd63de0 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -551,7 +551,7 @@ config I2C_PMCMSP
 
 config I2C_PNX
         tristate "I2C bus support for Philips PNX and NXP LPC targets"
-        depends on ARCH_PNX4008 || ARCH_LPC32XX
+        depends on ARCH_LPC32XX
         help
           This driver supports the Philips IP3204 I2C IP block master and/or
           slave controller
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 79b4bcb3b85c..79a2542d8c41 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -40,7 +40,7 @@
 #include <linux/gpio.h>
 
 #include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 
 /* ----- global defines ----------------------------------------------- */
 
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 0722f869465c..b7907ba7448a 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -54,7 +54,7 @@
 #include <linux/pinctrl/consumer.h>
 
 #include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-imx.h>
 
 /** Defines ********************************************************************
 *******************************************************************************/
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
index 93f147a96b62..2f99613fd677 100644
--- a/drivers/i2c/busses/i2c-iop3xx.c
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -4,13 +4,13 @@
 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
  *                    <Peter dot Milne at D hyphen TACQ dot com>
  *
- * With acknowledgements to i2c-algo-ibm_ocp.c by 
+ * With acknowledgements to i2c-algo-ibm_ocp.c by
  * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
  *
  * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
  *
  * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
- *  
+ *
  * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
  * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
  *
@@ -39,14 +39,15 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 
 #include "i2c-iop3xx.h"
 
 /* global unit counter */
 static int i2c_id;
 
-static inline unsigned char 
-iic_cook_addr(struct i2c_msg *msg) 
+static inline unsigned char
+iic_cook_addr(struct i2c_msg *msg)
 {
         unsigned char addr;
 
@@ -55,38 +56,38 @@ iic_cook_addr(struct i2c_msg *msg)
         if (msg->flags & I2C_M_RD)
                 addr |= 1;
 
-        return addr;   
+        return addr;
 }
 
-static void 
+static void
 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
 {
         /* Follows devman 9.3 */
         __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
         __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
         __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
-} 
+}
 
-static void 
+static void
 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
 {
         u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
 
-        /* 
+        /*
          * Every time unit enable is asserted, GPOD needs to be cleared
          * on IOP3XX to avoid data corruption on the bus.
          */
 #if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
         if (iop3xx_adap->id == 0) {
-                gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW);
-                gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW);
+                gpio_set_value(7, 0);
+                gpio_set_value(6, 0);
         } else {
-                gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW);
-                gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW);
+                gpio_set_value(5, 0);
+                gpio_set_value(4, 0);
         }
 #endif
         /* NB SR bits not same position as CR IE bits :-( */
-        iop3xx_adap->SR_enabled = 
+        iop3xx_adap->SR_enabled =
                 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
                 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
 
@@ -96,23 +97,23 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
         __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
 }
 
-static void 
+static void
 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
 {
         unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
-        
-        cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | 
+
+        cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
                 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
 
         __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
 }
 
-/* 
- * NB: the handler has to clear the source of the interrupt! 
+/*
+ * NB: the handler has to clear the source of the interrupt!
  * Then it passes the SR flags of interest to BH via adap data
  */
-static irqreturn_t 
-iop3xx_i2c_irq_handler(int this_irq, void *dev_id) 
+static irqreturn_t
+iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
 {
         struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
         u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
@@ -126,7 +127,7 @@ iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
 }
 
 /* check all error conditions, clear them , report most important */
-static int 
+static int
 iop3xx_i2c_error(u32 sr)
 {
         int rc = 0;
@@ -135,12 +136,12 @@ iop3xx_i2c_error(u32 sr)
                 if ( !rc ) rc = -I2C_ERR_BERR;
         }
         if ((sr & IOP3XX_ISR_ALD)) {
-                if ( !rc ) rc = -I2C_ERR_ALD;           
+                if ( !rc ) rc = -I2C_ERR_ALD;
         }
-        return rc;      
+        return rc;
 }
 
-static inline u32 
+static inline u32
 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
 {
         unsigned long flags;
@@ -161,8 +162,8 @@ iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
 typedef int (* compare_func)(unsigned test, unsigned mask);
 /* returns 1 on correct comparison */
 
-static int 
-iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, 
+static int
+iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
                           unsigned flags, unsigned* status,
                           compare_func compare)
 {
@@ -192,47 +193,47 @@ iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
 }
 
 /*
- * Concrete compare_funcs 
+ * Concrete compare_funcs
  */
-static int 
+static int
 all_bits_clear(unsigned test, unsigned mask)
 {
         return (test & mask) == 0;
 }
 
-static int 
+static int
 any_bits_set(unsigned test, unsigned mask)
 {
         return (test & mask) != 0;
 }
 
-static int 
+static int
 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
 {
-        return iop3xx_i2c_wait_event( 
-                iop3xx_adap, 
+        return iop3xx_i2c_wait_event(
+                iop3xx_adap,
                 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
                 status, any_bits_set);
 }
 
-static int 
+static int
 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
 {
-        return iop3xx_i2c_wait_event( 
-                iop3xx_adap, 
+        return iop3xx_i2c_wait_event(
+                iop3xx_adap,
                 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
                 status, any_bits_set);
 }
 
-static int 
+static int
 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
 {
-        return iop3xx_i2c_wait_event( 
+        return iop3xx_i2c_wait_event(
                 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
 }
 
-static int 
-iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, 
+static int
+iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
                                 struct i2c_msg* msg)
 {
         unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -247,7 +248,7 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
         }
 
         __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
-        
+
         cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
         cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
 
@@ -257,8 +258,8 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
         return rc;
 }
 
-static int 
-iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, 
+static int
+iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
                                 int stop)
 {
         unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -277,10 +278,10 @@ iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
         rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
 
         return rc;
-} 
+}
 
-static int 
-iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, 
+static int
+iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
                                 int stop)
 {
         unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -304,19 +305,19 @@ iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
         return rc;
 }
 
-static int 
+static int
 iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
 {
         struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
         int ii;
         int rc = 0;
 
-        for (ii = 0; rc == 0 && ii != count; ++ii) 
+        for (ii = 0; rc == 0 && ii != count; ++ii)
                 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
         return rc;
 }
 
-static int 
+static int
 iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
 {
         struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -325,7 +326,7 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
 
         for (ii = 0; rc == 0 && ii != count; ++ii)
                 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
-        
+
         return rc;
 }
 
@@ -336,8 +337,8 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
  * Each transfer (i.e. a read or a write) is separated by a repeated start
  * condition.
  */
-static int 
-iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) 
+static int
+iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
 {
         struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
         int rc;
@@ -357,8 +358,8 @@ iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
 /*
  * master_xfer() - main read/write entry
  */
-static int 
-iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 
+static int
+iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
                                 int num)
 {
         struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -375,14 +376,14 @@ iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
         }
 
         iop3xx_i2c_transaction_cleanup(iop3xx_adap);
-        
+
         if(ret)
                 return ret;
 
-        return im;   
+        return im;
 }
 
-static u32 
+static u32
 iop3xx_i2c_func(struct i2c_adapter *adap)
 {
         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -393,11 +394,11 @@ static const struct i2c_algorithm iop3xx_i2c_algo = {
         .functionality  = iop3xx_i2c_func,
 };
 
-static int 
+static int
 iop3xx_i2c_remove(struct platform_device *pdev)
 {
         struct i2c_adapter *padapter = platform_get_drvdata(pdev);
-        struct i2c_algo_iop3xx_data *adapter_data = 
+        struct i2c_algo_iop3xx_data *adapter_data =
                 (struct i2c_algo_iop3xx_data *)padapter->algo_data;
         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
@@ -419,7 +420,7 @@ iop3xx_i2c_remove(struct platform_device *pdev)
         return 0;
 }
 
-static int 
+static int
 iop3xx_i2c_probe(struct platform_device *pdev)
 {
         struct resource *res;
diff --git a/drivers/i2c/busses/i2c-nuc900.c b/drivers/i2c/busses/i2c-nuc900.c
index a26dfb8cd586..f41502ef3f55 100644
--- a/drivers/i2c/busses/i2c-nuc900.c
+++ b/drivers/i2c/busses/i2c-nuc900.c
@@ -29,7 +29,7 @@
 #include <linux/io.h>
 
 #include <mach/mfp.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-nuc900.h>
 
 /* nuc900 i2c registers offset */
 
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 5ae3b0236bd3..4d07dea9bca9 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -42,7 +42,7 @@
 #include <asm/irq.h>
 
 #include <plat/regs-iic.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 
 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
 #define QUIRK_S3C2440           (1 << 0)
diff --git a/drivers/input/keyboard/davinci_keyscan.c b/drivers/input/keyboard/davinci_keyscan.c
index 9d82b3aeff5e..d5bacbb479b0 100644
--- a/drivers/input/keyboard/davinci_keyscan.c
+++ b/drivers/input/keyboard/davinci_keyscan.c
@@ -36,7 +36,7 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/keyscan.h>
+#include <linux/platform_data/keyscan-davinci.h>
 
 /* Key scan registers */
 #define DAVINCI_KEYSCAN_KEYCTRL         0x0000
diff --git a/drivers/input/keyboard/ep93xx_keypad.c b/drivers/input/keyboard/ep93xx_keypad.c
index c46fc8185469..7363402de8d4 100644
--- a/drivers/input/keyboard/ep93xx_keypad.c
+++ b/drivers/input/keyboard/ep93xx_keypad.c
@@ -29,7 +29,7 @@
 #include <linux/slab.h>
 
 #include <mach/hardware.h>
-#include <mach/ep93xx_keypad.h>
+#include <linux/platform_data/keypad-ep93xx.h>
 
 /*
  * Keypad Interface Register offsets
diff --git a/drivers/input/keyboard/nomadik-ske-keypad.c b/drivers/input/keyboard/nomadik-ske-keypad.c
index a880e7414202..49f5fa64e0b1 100644
--- a/drivers/input/keyboard/nomadik-ske-keypad.c
+++ b/drivers/input/keyboard/nomadik-ske-keypad.c
@@ -20,7 +20,7 @@
 #include <linux/clk.h>
 #include <linux/module.h>
 
-#include <plat/ske.h>
+#include <linux/platform_data/keypad-nomadik-ske.h>
 
 /* SKE_CR bits */
 #define SKE_KPMLT       (0x1 << 6)
diff --git a/drivers/input/keyboard/omap-keypad.c b/drivers/input/keyboard/omap-keypad.c
index 2bda5f0b9c6e..6d6b1427ae12 100644
--- a/drivers/input/keyboard/omap-keypad.c
+++ b/drivers/input/keyboard/omap-keypad.c
@@ -37,7 +37,7 @@
 #include <linux/slab.h>
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #undef NEW_BOARD_LEARNING_MODE
 
diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index 7f7b72464a37..803ff6fe021e 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -32,7 +32,7 @@
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 /*
  * Keypad Controller registers
  */
diff --git a/drivers/input/keyboard/pxa930_rotary.c b/drivers/input/keyboard/pxa930_rotary.c
index d7f1134b789e..41488f9add20 100644
--- a/drivers/input/keyboard/pxa930_rotary.c
+++ b/drivers/input/keyboard/pxa930_rotary.c
@@ -15,7 +15,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/pxa930_rotary.h>
+#include <linux/platform_data/keyboard-pxa930_rotary.h>
 
 #define SBCR    (0x04)
 #define ERCR    (0x0c)
diff --git a/drivers/input/keyboard/spear-keyboard.c b/drivers/input/keyboard/spear-keyboard.c
index 72ef01be3360..c7ca97f44bfb 100644
--- a/drivers/input/keyboard/spear-keyboard.c
+++ b/drivers/input/keyboard/spear-keyboard.c
@@ -24,7 +24,7 @@
 #include <linux/pm_wakeup.h>
 #include <linux/slab.h>
 #include <linux/types.h>
-#include <plat/keyboard.h>
+#include <linux/platform_data/keyboard-spear.h>
 
 /* Keyboard Registers */
 #define MODE_CTL_REG    0x00
diff --git a/drivers/input/keyboard/w90p910_keypad.c b/drivers/input/keyboard/w90p910_keypad.c
index 085ede4d972d..e0f6cd1ad0fd 100644
--- a/drivers/input/keyboard/w90p910_keypad.c
+++ b/drivers/input/keyboard/w90p910_keypad.c
@@ -21,7 +21,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/w90p910_keypad.h>
+#include <linux/platform_data/keypad-w90p910.h>
 
 /* Keypad Interface Control Registers */
 #define KPI_CONF                0x00
diff --git a/drivers/input/mouse/pxa930_trkball.c b/drivers/input/mouse/pxa930_trkball.c
index a9e4bfdf31f4..4fe055f2c536 100644
--- a/drivers/input/mouse/pxa930_trkball.c
+++ b/drivers/input/mouse/pxa930_trkball.c
@@ -20,7 +20,7 @@
 #include <linux/slab.h>
 
 #include <mach/hardware.h>
-#include <mach/pxa930_trkball.h>
+#include <linux/platform_data/mouse-pxa930_trkball.h>
 
 /* Trackball Controller Register Definitions */
 #define TBCR            (0x000C)
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c
index 272deddc8db6..21c60fea5d31 100644
--- a/drivers/input/mouse/rpcmouse.c
+++ b/drivers/input/mouse/rpcmouse.c
@@ -42,7 +42,7 @@ static irqreturn_t rpcmouse_irq(int irq, void *dev_id)
 
         x = (short) iomd_readl(IOMD_MOUSEX);
         y = (short) iomd_readl(IOMD_MOUSEY);
-        b = (short) (__raw_readl(0xe0310000) ^ 0x70);
+        b = (short) (__raw_readl(IOMEM(0xe0310000)) ^ 0x70);
 
         dx = x - rpcmouse_lastx;
         dy = y - rpcmouse_lasty;
diff --git a/drivers/input/serio/ams_delta_serio.c b/drivers/input/serio/ams_delta_serio.c
index f5fbdf94de3b..45887e31242a 100644
--- a/drivers/input/serio/ams_delta_serio.c
+++ b/drivers/input/serio/ams_delta_serio.c
@@ -27,7 +27,7 @@
 #include <linux/module.h>
 
 #include <asm/mach-types.h>
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <mach/ams-delta-fiq.h>
 
diff --git a/drivers/input/touchscreen/s3c2410_ts.c b/drivers/input/touchscreen/s3c2410_ts.c
index bf1a06400067..df9e816d55e4 100644
--- a/drivers/input/touchscreen/s3c2410_ts.c
+++ b/drivers/input/touchscreen/s3c2410_ts.c
@@ -37,7 +37,7 @@
 
 #include <plat/adc.h>
 #include <plat/regs-adc.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 
 #define TSC_SLEEP  (S3C2410_ADCTSC_PULL_UP_DISABLE | S3C2410_ADCTSC_XY_PST(0))
 
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/drivers/irqchip/Kconfig
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
new file mode 100644
index 000000000000..054321db4350
--- /dev/null
+++ b/drivers/irqchip/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c
new file mode 100644
index 000000000000..dc670ccc6978
--- /dev/null
+++ b/drivers/irqchip/irq-bcm2835.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2010 Broadcom
+ * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
+ *
+ * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
+ * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
+ * to look in the bank 1 status register for more information.
+ *
+ * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
+ * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
+ * status register, but bank 0 bit 8 is _not_ set.
+ *
+ * Quirk 2: You can't mask the register 1/2 pending interrupts
+ *
+ * In a proper cascaded interrupt controller, the interrupt lines with
+ * cascaded interrupt controllers on them are just normal interrupt lines.
+ * You can mask the interrupts and get on with things. With this controller
+ * you can't do that.
+ *
+ * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
+ *
+ * Those interrupts that have shortcuts can only be masked/unmasked in
+ * their respective banks' enable/disable registers. Doing so in the bank 0
+ * enable/disable registers has no effect.
+ *
+ * The FIQ control register:
+ *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
+ *  Bit    7: Enable FIQ generation
+ *  Bits  8+: Unused
+ *
+ * An interrupt must be disabled before configuring it for FIQ generation
+ * otherwise both handlers will fire at the same time!
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/bcm2835.h>
+
+#include <asm/exception.h>
+
+/* Put the bank and irq (32 bits) into the hwirq */
+#define MAKE_HWIRQ(b, n)        ((b << 5) | (n))
+#define HWIRQ_BANK(i)           (i >> 5)
+#define HWIRQ_BIT(i)            BIT(i & 0x1f)
+
+#define NR_IRQS_BANK0           8
+#define BANK0_HWIRQ_MASK        0xff
+/* Shortcuts can't be disabled so any unknown new ones need to be masked */
+#define SHORTCUT1_MASK          0x00007c00
+#define SHORTCUT2_MASK          0x001f8000
+#define SHORTCUT_SHIFT          10
+#define BANK1_HWIRQ             BIT(8)
+#define BANK2_HWIRQ             BIT(9)
+#define BANK0_VALID_MASK        (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
+                                        | SHORTCUT1_MASK | SHORTCUT2_MASK)
+
+#define REG_FIQ_CONTROL         0x0c
+
+#define NR_BANKS                3
+#define IRQS_PER_BANK           32
+
+static int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
+static int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
+static int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
+static int bank_irqs[] __initconst = { 8, 32, 32 };
+
+static const int shortcuts[] = {
+        7, 9, 10, 18, 19,               /* Bank 1 */
+        21, 22, 23, 24, 25, 30          /* Bank 2 */
+};
+
+struct armctrl_ic {
+        void __iomem *base;
+        void __iomem *pending[NR_BANKS];
+        void __iomem *enable[NR_BANKS];
+        void __iomem *disable[NR_BANKS];
+        struct irq_domain *domain;
+};
+
+static struct armctrl_ic intc __read_mostly;
+
+static void armctrl_mask_irq(struct irq_data *d)
+{
+        writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
+}
+
+static void armctrl_unmask_irq(struct irq_data *d)
+{
+        writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
+}
+
+static struct irq_chip armctrl_chip = {
+        .name = "ARMCTRL-level",
+        .irq_mask = armctrl_mask_irq,
+        .irq_unmask = armctrl_unmask_irq
+};
+
+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
+        const u32 *intspec, unsigned int intsize,
+        unsigned long *out_hwirq, unsigned int *out_type)
+{
+        if (WARN_ON(intsize != 2))
+                return -EINVAL;
+
+        if (WARN_ON(intspec[0] >= NR_BANKS))
+                return -EINVAL;
+
+        if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
+                return -EINVAL;
+
+        if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
+                return -EINVAL;
+
+        *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
+        *out_type = IRQ_TYPE_NONE;
+        return 0;
+}
+
+static struct irq_domain_ops armctrl_ops = {
+        .xlate = armctrl_xlate
+};
+
+static int __init armctrl_of_init(struct device_node *node,
+        struct device_node *parent)
+{
+        void __iomem *base;
+        int irq, b, i;
+
+        base = of_iomap(node, 0);
+        if (!base)
+                panic("%s: unable to map IC registers\n",
+                        node->full_name);
+
+        intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
+                        &armctrl_ops, NULL);
+        if (!intc.domain)
+                panic("%s: unable to create IRQ domain\n", node->full_name);
+
+        for (b = 0; b < NR_BANKS; b++) {
+                intc.pending[b] = base + reg_pending[b];
+                intc.enable[b] = base + reg_enable[b];
+                intc.disable[b] = base + reg_disable[b];
+
+                for (i = 0; i < bank_irqs[b]; i++) {
+                        irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
+                        BUG_ON(irq <= 0);
+                        irq_set_chip_and_handler(irq, &armctrl_chip,
+                                handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+        return 0;
+}
+
+static struct of_device_id irq_of_match[] __initconst = {
+        { .compatible = "brcm,bcm2835-armctrl-ic", .data = armctrl_of_init }
+};
+
+void __init bcm2835_init_irq(void)
+{
+        of_irq_init(irq_of_match);
+}
+
+/*
+ * Handle each interrupt across the entire interrupt controller.  This reads the
+ * status register before handling each interrupt, which is necessary given that
+ * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
+ */
+
+static void armctrl_handle_bank(int bank, struct pt_regs *regs)
+{
+        u32 stat, irq;
+
+        while ((stat = readl_relaxed(intc.pending[bank]))) {
+                irq = MAKE_HWIRQ(bank, ffs(stat) - 1);
+                handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
+        }
+}
+
+static void armctrl_handle_shortcut(int bank, struct pt_regs *regs,
+        u32 stat)
+{
+        u32 irq = MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
+        handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
+}
+
+asmlinkage void __exception_irq_entry bcm2835_handle_irq(
+        struct pt_regs *regs)
+{
+        u32 stat, irq;
+
+        while ((stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK)) {
+                if (stat & BANK0_HWIRQ_MASK) {
+                        irq = MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
+                        handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
+                } else if (stat & SHORTCUT1_MASK) {
+                        armctrl_handle_shortcut(1, regs, stat & SHORTCUT1_MASK);
+                } else if (stat & SHORTCUT2_MASK) {
+                        armctrl_handle_shortcut(2, regs, stat & SHORTCUT2_MASK);
+                } else if (stat & BANK1_HWIRQ) {
+                        armctrl_handle_bank(1, regs);
+                } else if (stat & BANK2_HWIRQ) {
+                        armctrl_handle_bank(2, regs);
+                } else {
+                        BUG();
+                }
+        }
+}
diff --git a/drivers/leds/leds-netxbig.c b/drivers/leds/leds-netxbig.c
index e37618e363cf..461bbf9b33fa 100644
--- a/drivers/leds/leds-netxbig.c
+++ b/drivers/leds/leds-netxbig.c
@@ -28,7 +28,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
-#include <mach/leds-netxbig.h>
+#include <linux/platform_data/leds-kirkwood-netxbig.h>
 
 /*
  * GPIO extension bus.
diff --git a/drivers/leds/leds-ns2.c b/drivers/leds/leds-ns2.c
index 10528dafb043..d176ec83f5d9 100644
--- a/drivers/leds/leds-ns2.c
+++ b/drivers/leds/leds-ns2.c
@@ -29,7 +29,7 @@
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <linux/module.h>
-#include <mach/leds-ns2.h>
+#include <linux/platform_data/leds-kirkwood-ns2.h>
 
 /*
  * The Network Space v2 dual-GPIO LED is wired to a CPLD and can blink in
diff --git a/drivers/leds/leds-s3c24xx.c b/drivers/leds/leds-s3c24xx.c
index 942f0ea18178..e1a0df63a37f 100644
--- a/drivers/leds/leds-s3c24xx.c
+++ b/drivers/leds/leds-s3c24xx.c
@@ -21,7 +21,7 @@
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 
 /* our context */
 
diff --git a/drivers/media/video/davinci/vpbe_venc.c b/drivers/media/video/davinci/vpbe_venc.c
index b21ecc8d134d..0302669622d6 100644
--- a/drivers/media/video/davinci/vpbe_venc.c
+++ b/drivers/media/video/davinci/vpbe_venc.c
@@ -27,7 +27,7 @@
 
 #include <mach/hardware.h>
 #include <mach/mux.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 
 #include <linux/io.h>
 
diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
index 560a65aa7038..bbe70991d30b 100644
--- a/drivers/media/video/mx1_camera.c
+++ b/drivers/media/video/mx1_camera.c
@@ -44,7 +44,7 @@
 #include <mach/dma-mx1-mx2.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/mx1_camera.h>
+#include <linux/platform_data/camera-mx1.h>
 
 /*
  * CSI registers
diff --git a/drivers/media/video/mx2_camera.c b/drivers/media/video/mx2_camera.c
index ac175406e582..965427f279a5 100644
--- a/drivers/media/video/mx2_camera.c
+++ b/drivers/media/video/mx2_camera.c
@@ -40,7 +40,7 @@
 
 #include <linux/videodev2.h>
 
-#include <mach/mx2_cam.h>
+#include <linux/platform_data/camera-mx2.h>
 #include <mach/hardware.h>
 
 #include <asm/dma.h>
diff --git a/drivers/media/video/mx3_camera.c b/drivers/media/video/mx3_camera.c
index af2297dd49c8..1481b0d419da 100644
--- a/drivers/media/video/mx3_camera.c
+++ b/drivers/media/video/mx3_camera.c
@@ -25,8 +25,8 @@
 #include <media/soc_mediabus.h>
 
 #include <mach/ipu.h>
-#include <mach/mx3_camera.h>
-#include <mach/dma.h>
+#include <linux/platform_data/camera-mx3.h>
+#include <linux/platform_data/dma-imx.h>
 
 #define MX3_CAM_DRV_NAME "mx3-camera"
 
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index 9c21e01f2c24..1e3776d08dac 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -37,7 +37,7 @@
 #include <linux/videodev2.h>
 
 #include <mach/dma.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 
 #define PXA_CAM_VERSION "0.0.6"
 #define PXA_CAM_DRV_NAME "pxa27x-camera"
diff --git a/drivers/media/video/s5p-fimc/mipi-csis.c b/drivers/media/video/s5p-fimc/mipi-csis.c
index 2f73d9e3d0b7..5e898432883a 100644
--- a/drivers/media/video/s5p-fimc/mipi-csis.c
+++ b/drivers/media/video/s5p-fimc/mipi-csis.c
@@ -26,7 +26,7 @@
 #include <linux/spinlock.h>
 #include <linux/videodev2.h>
 #include <media/v4l2-subdev.h>
-#include <plat/mipi_csis.h>
+#include <linux/platform_data/mipi-csis.h>
 #include "mipi-csis.h"
 
 static int debug;
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 0e63cdd9b52a..6b67edbdbd01 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -418,6 +418,9 @@ static struct {
 
 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 
+/* Functions definition */
+static void compute_armss_rate(void);
+
 /* Spinlocks */
 static DEFINE_SPINLOCK(prcmu_lock);
 static DEFINE_SPINLOCK(clkout_lock);
@@ -517,6 +520,7 @@ static struct dsiescclk dsiescclk[3] = {
         }
 };
 
+
 /*
 * Used by MCDE to setup all necessary PRCMU registers
 */
@@ -1013,6 +1017,7 @@ int db8500_prcmu_set_arm_opp(u8 opp)
                 (mb1_transfer.ack.arm_opp != opp))
                 r = -EIO;
 
+        compute_armss_rate();
         mutex_unlock(&mb1_transfer.lock);
 
         return r;
@@ -1612,6 +1617,7 @@ static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
         if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
                 (val & PRCM_PLL_FREQ_DIV2EN) &&
                 ((reg == PRCM_PLLSOC0_FREQ) ||
+                 (reg == PRCM_PLLARM_FREQ) ||
                  (reg == PRCM_PLLDDR_FREQ))))
                 div *= 2;
 
@@ -1661,6 +1667,39 @@ static unsigned long clock_rate(u8 clock)
         else
                 return 0;
 }
+static unsigned long latest_armss_rate;
+static unsigned long armss_rate(void)
+{
+        return latest_armss_rate;
+}
+
+static void compute_armss_rate(void)
+{
+        u32 r;
+        unsigned long rate;
+
+        r = readl(PRCM_ARM_CHGCLKREQ);
+
+        if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
+                /* External ARMCLKFIX clock */
+
+                rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
+
+                /* Check PRCM_ARM_CHGCLKREQ divider */
+                if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
+                        rate /= 2;
+
+                /* Check PRCM_ARMCLKFIX_MGT divider */
+                r = readl(PRCM_ARMCLKFIX_MGT);
+                r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
+                rate /= r;
+
+        } else {/* ARM PLL */
+                rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
+        }
+
+        latest_armss_rate = rate;
+}
 
 static unsigned long dsiclk_rate(u8 n)
 {
@@ -1707,6 +1746,8 @@ unsigned long prcmu_clock_rate(u8 clock)
                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
         else if (clock == PRCMU_PLLSOC1)
                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
+        else if (clock == PRCMU_ARMSS)
+                return armss_rate();
         else if (clock == PRCMU_PLLDDR)
                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
         else if (clock == PRCMU_PLLDSI)
@@ -2693,6 +2734,7 @@ void __init db8500_prcmu_early_init(void)
                                          handle_simple_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
+        compute_armss_rate();
 }
 
 static void __init init_prcm_registers(void)
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 23108a6e3167..79c76ebdba52 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -61,7 +61,8 @@
 #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3    0x2
 
 #define PRCM_ARM_CHGCLKREQ      (_PRCMU_BASE + 0x114)
-#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ   0x1
+#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ   BIT(0)
+#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL      BIT(16)
 
 #define PRCM_PLLARM_ENABLE      (_PRCMU_BASE + 0x98)
 #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE   0x1
@@ -140,6 +141,7 @@
 /* PRCMU clock/PLL/reset registers */
 #define PRCM_PLLSOC0_FREQ          (_PRCMU_BASE + 0x080)
 #define PRCM_PLLSOC1_FREQ          (_PRCMU_BASE + 0x084)
+#define PRCM_PLLARM_FREQ           (_PRCMU_BASE + 0x088)
 #define PRCM_PLLDDR_FREQ           (_PRCMU_BASE + 0x08C)
 #define PRCM_PLL_FREQ_D_SHIFT   0
 #define PRCM_PLL_FREQ_D_MASK    BITS(0, 7)
diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c
index c54e244ca0cf..f99d6299ec24 100644
--- a/drivers/mfd/mcp-sa11x0.c
+++ b/drivers/mfd/mcp-sa11x0.c
@@ -24,7 +24,7 @@
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 
 #define DRIVER_NAME "sa11x0-mcp"
 
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index 5f58370ccf55..345960ca2fd8 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -25,6 +25,7 @@
 #include <linux/i2c.h>
 #include <linux/regmap.h>
 #include <linux/regulator/of_regulator.h>
+#include <linux/regulator/machine.h>
 
 #include <linux/mfd/core.h>
 #include <linux/mfd/tps6586x.h>
@@ -346,6 +347,7 @@ failed:
 
 #ifdef CONFIG_OF
 static struct of_regulator_match tps6586x_matches[] = {
+        { .name = "sys",     .driver_data = (void *)TPS6586X_ID_SYS     },
         { .name = "sm0",     .driver_data = (void *)TPS6586X_ID_SM_0    },
         { .name = "sm1",     .driver_data = (void *)TPS6586X_ID_SM_1    },
         { .name = "sm2",     .driver_data = (void *)TPS6586X_ID_SM_2    },
@@ -369,6 +371,7 @@ static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *clien
         struct tps6586x_platform_data *pdata;
         struct tps6586x_subdev_info *devs;
         struct device_node *regs;
+        const char *sys_rail_name = NULL;
         unsigned int count;
         unsigned int i, j;
         int err;
@@ -391,12 +394,22 @@ static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *clien
                 return NULL;
 
         for (i = 0, j = 0; i < num && j < count; i++) {
+                struct regulator_init_data *reg_idata;
+
                 if (!tps6586x_matches[i].init_data)
                         continue;
 
+                reg_idata  = tps6586x_matches[i].init_data;
                 devs[j].name = "tps6586x-regulator";
                 devs[j].platform_data = tps6586x_matches[i].init_data;
                 devs[j].id = (int)tps6586x_matches[i].driver_data;
+                if (devs[j].id == TPS6586X_ID_SYS)
+                        sys_rail_name = reg_idata->constraints.name;
+
+                if ((devs[j].id == TPS6586X_ID_LDO_5) ||
+                        (devs[j].id == TPS6586X_ID_LDO_RTC))
+                        reg_idata->supply_regulator = sys_rail_name;
+
                 devs[j].of_node = tps6586x_matches[i].of_node;
                 j++;
         }
diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index 7cf6c624bf73..3dfd3473269d 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -33,7 +33,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/mmc/mmc.h>
 
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-davinci.h>
 #include <mach/edma.h>
 
 /*
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 1d14cda95e56..7c0af0e80047 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -42,7 +42,7 @@
 #include <asm/div64.h>
 #include <asm/sizes.h>
 
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 #include <mach/msm_iomap.h>
 #include <mach/dma.h>
 #include <mach/clk.h>
diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c
index a61cb5fca22d..de4c20b3936c 100644
--- a/drivers/mmc/host/mvsdio.c
+++ b/drivers/mmc/host/mvsdio.c
@@ -25,7 +25,7 @@
 
 #include <asm/sizes.h>
 #include <asm/unaligned.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 
 #include "mvsdio.h"
 
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index 28ed52d58f7f..7b1161de01d6 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -38,9 +38,9 @@
 #include <asm/dma.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-mxcmmc.h>
 
-#include <mach/dma.h>
+#include <linux/platform_data/dma-imx.h>
 #include <mach/hardware.h>
 
 #define DRIVER_NAME "mxc-mmc"
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index 87c0293a1eef..c6259a829544 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -36,7 +36,6 @@
 #include <plat/mmc.h>
 #include <asm/gpio.h>
 #include <plat/dma.h>
-#include <plat/mux.h>
 #include <plat/fpga.h>
 
 #define OMAP_MMC_REG_CMD        0x00
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index cb2dc0e75ba7..ca3915dac03d 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -35,7 +35,7 @@
 
 #include <mach/hardware.h>
 #include <mach/dma.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 
 #include "pxamci.h"
 
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index bd5a5cce122c..4638ddab97b8 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -27,7 +27,7 @@
 
 #include <mach/regs-sdi.h>
 
-#include <plat/mci.h>
+#include <linux/platform_data/mmc-s3cmci.h>
 
 #include "s3cmci.h"
 
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index e23f8134591c..c4c504c4802b 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -25,7 +25,7 @@
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 #include <linux/pinctrl/consumer.h>
-#include <mach/esdhc.h>
+#include <linux/platform_data/mmc-esdhc-imx.h>
 #include "sdhci-pltfm.h"
 #include "sdhci-esdhc.h"
 
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 0810ccc23d7e..d43e7462941f 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -28,7 +28,7 @@
 #include <asm/gpio.h>
 
 #include <mach/gpio-tegra.h>
-#include <mach/sdhci.h>
+#include <linux/platform_data/mmc-sdhci-tegra.h>
 
 #include "sdhci-pltfm.h"
 
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index 78a524b49357..a7040af08536 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -29,7 +29,7 @@
 #include <asm/io.h>
 #include <asm/sizes.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <mach/hardware.h>
 
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
index c855e7cd337b..d0d1bd4d0e7d 100644
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd)
 int bcm_umi_nand_inithw(void)
 {
         /* Configure nand timing parameters */
-        REG_UMI_NAND_TCR &= ~0x7ffff;
-        REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
+        writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
+        writel(readl(&REG_UMI_NAND_TCR) | HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);
 
 #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
         /* enable software control of CS */
-        REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
+        writel(readl(&REG_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
 #endif
 
         /* keep NAND chip select asserted */
-        REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
+        writel(readl(&REG_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);
 
-        REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
+        writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
         /* enable writes to flash */
-        REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
+        writel(readl(&REG_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);
 
         writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
         nand_bcm_umi_wait_till_ready();
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d94b03c207af..f1deb1ee2c95 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -34,8 +34,8 @@
 #include <linux/mtd/partitions.h>
 #include <linux/slab.h>
 
-#include <mach/nand.h>
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
 
 /*
  * This is a device driver for the NAND flash controller found on the
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 6acc790c2fbb..5683604967d7 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -36,7 +36,7 @@
 #include <linux/of_mtd.h>
 
 #include <asm/mach/flash.h>
-#include <mach/mxc_nand.h>
+#include <linux/platform_data/mtd-mxc_nand.h>
 #include <mach/hardware.h>
 
 #define DRIVER_NAME "mxc_nand"
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h
index 198b304d6f72..d90186684db8 100644
--- a/drivers/mtd/nand/nand_bcm_umi.h
+++ b/drivers/mtd/nand/nand_bcm_umi.h
@@ -17,7 +17,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 #include <mach/reg_umi.h>
 #include <mach/reg_nand.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 #if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
@@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
 /* Check in device is ready */
 static inline int nand_bcm_umi_dev_ready(void)
 {
-        return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
+        return readl(&REG_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY;
 }
 
 /* Wait until device is ready */
@@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void)
 static inline void nand_bcm_umi_hamming_enable_hwecc(void)
 {
         /* disable and reset ECC, 512 byte page */
-        REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
-                REG_UMI_NAND_ECC_CSR_256BYTE);
+        writel(readl(&REG_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
+                REG_UMI_NAND_ECC_CSR_256BYTE), &REG_UMI_NAND_ECC_CSR);
         /* enable ECC */
-        REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
+        writel(readl(&REG_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE,
+                &REG_UMI_NAND_ECC_CSR);
 }
 
 #if NAND_ECC_BCH
@@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void)
 static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
 {
         /* disable and reset ECC */
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+        writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
         /* Turn on ECC */
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+        writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Enable BCH Write ECC */
 static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
 {
         /* disable and reset ECC */
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
+        writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
         /* Turn on ECC */
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
+        writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Config number of BCH ECC bytes */
@@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
         uint32_t numBits = numEccBytes * 8;
 
         /* disable and reset ECC */
-        REG_UMI_BCH_CTRL_STATUS =
-            REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
-            REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+        writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
+               REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID,
+               &REG_UMI_BCH_CTRL_STATUS);
 
         /* Every correctible bit requires 13 ECC bits */
         tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
@@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
         kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
 
         /* Write the settings */
-        REG_UMI_BCH_N = nValue;
-        REG_UMI_BCH_T = tValue;
-        REG_UMI_BCH_K = kValue;
+        writel(nValue, &REG_UMI_BCH_N);
+        writel(tValue, &REG_UMI_BCH_T);
+        writel(kValue, &REG_UMI_BCH_K);
 }
 
 /* Pause during ECC read calculation to skip bytes in OOB */
 static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
 {
-        REG_UMI_BCH_CTRL_STATUS =
-            REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
-            REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
+        writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Resume during ECC read calculation after skipping bytes in OOB */
 static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
 {
-        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+        writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Poll read ECC calc to check when hardware completes */
@@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
 
         do {
                 /* wait for ECC to be valid */
-                regVal = REG_UMI_BCH_CTRL_STATUS;
+                regVal = readl(&REG_UMI_BCH_CTRL_STATUS);
         } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
 
         return regVal;
@@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
 static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
 {
         /* wait for ECC to be valid */
-        while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
+        while ((readl(&REG_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
                == 0)
                 ;
 }
@@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
         if (pageSize != NAND_DATA_ACCESS_SIZE) {
                 /* skip BI */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                *oobp++ = REG_NAND_DATA8;
+                *oobp++ = readb(&REG_NAND_DATA8);
 #else
-                REG_NAND_DATA8;
+                readb(&REG_NAND_DATA8);
 #endif
                 numToRead--;
         }
@@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
         while (numToRead > numEccBytes) {
                 /* skip free oob region */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                *oobp++ = REG_NAND_DATA8;
+                *oobp++ = readb(&REG_NAND_DATA8);
 #else
-                REG_NAND_DATA8;
+                readb(&REG_NAND_DATA8);
 #endif
                 numToRead--;
         }
@@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
 
                 while (numToRead > 11) {
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                        *oobp = REG_NAND_DATA8;
+                        *oobp = readb(&REG_NAND_DATA8);
                         eccCalc[eccPos++] = *oobp;
                         oobp++;
 #else
-                        eccCalc[eccPos++] = REG_NAND_DATA8;
+                        eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
 #endif
                         numToRead--;
                 }
@@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
                 if (numToRead == 11) {
                         /* read BI */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                        *oobp++ = REG_NAND_DATA8;
+                        *oobp++ = readb(&REG_NAND_DATA8);
 #else
-                        REG_NAND_DATA8;
+                        readb(&REG_NAND_DATA8);
 #endif
                         numToRead--;
                 }
@@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
         nand_bcm_umi_bch_resume_read_ecc_calc();
         while (numToRead) {
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                *oobp = REG_NAND_DATA8;
+                *oobp = readb(&REG_NAND_DATA8);
                 eccCalc[eccPos++] = *oobp;
                 oobp++;
 #else
-                eccCalc[eccPos++] = REG_NAND_DATA8;
+                eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
 #endif
                 numToRead--;
         }
@@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
         if (pageSize == NAND_DATA_ACCESS_SIZE) {
                 /* Now fill in the ECC bytes */
                 if (numEccBytes >= 13)
-                        eccVal = REG_UMI_BCH_WR_ECC_3;
+                        eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
 
                 /* Usually we skip CM in oob[0,1] */
                 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
@@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                         eccVal & 0xff); /* ECC 12 */
 
                 if (numEccBytes >= 9)
-                        eccVal = REG_UMI_BCH_WR_ECC_2;
+                        eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
 
                 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
                         (eccVal >> 24) & 0xff); /* ECC11 */
@@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
 
                 /* Now fill in the ECC bytes */
                 if (numEccBytes >= 13)
-                        eccVal = REG_UMI_BCH_WR_ECC_3;
+                        eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
 
                 /* Usually skip CM in oob[1,2] */
                 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
@@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                         eccVal & 0xff); /* ECC12 */
 
                 if (numEccBytes >= 9)
-                        eccVal = REG_UMI_BCH_WR_ECC_2;
+                        eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
 
                 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
                         (eccVal >> 24) & 0xff); /* ECC11 */
@@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                 eccVal & 0xff); /* ECC8 */
 
         if (numEccBytes >= 5)
-                eccVal = REG_UMI_BCH_WR_ECC_1;
+                eccVal = readl(&REG_UMI_BCH_WR_ECC_1);
 
         NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
                 (eccVal >> 24) & 0xff); /* ECC7 */
@@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                 eccVal & 0xff); /* ECC4 */
 
         if (numEccBytes >= 1)
-                eccVal = REG_UMI_BCH_WR_ECC_0;
+                eccVal = readl(&REG_UMI_BCH_WR_ECC_0);
 
         NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
                 (eccVal >> 24) & 0xff); /* ECC3 */
diff --git a/drivers/mtd/nand/nomadik_nand.c b/drivers/mtd/nand/nomadik_nand.c
index a86aa812ca13..9ee0c4edfacf 100644
--- a/drivers/mtd/nand/nomadik_nand.c
+++ b/drivers/mtd/nand/nomadik_nand.c
@@ -31,7 +31,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
 #include <linux/slab.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-nomadik-nand.h>
 #include <mach/fsmc.h>
 
 #include <mtd/mtd-abi.h>
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 27293e328517..fc8111278d12 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -29,7 +29,7 @@
 
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #define DRIVER_NAME     "omap2-nand"
 #define OMAP_NAND_TIMEOUT_MS    5000
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index fc5a868c436e..131b58a133f1 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -22,7 +22,7 @@
 #include <asm/io.h>
 #include <asm/sizes.h>
 #include <mach/hardware.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/mtd-orion_nand.h>
 
 static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 252aaefcacfa..c45227173efd 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -22,9 +22,11 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 #include <mach/dma.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 
 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
 #define NAND_STOP_DELAY         (2 * HZ/50)
@@ -1032,7 +1034,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
         struct pxa3xx_nand_platform_data *pdata;
         struct pxa3xx_nand_info *info;
         struct pxa3xx_nand_host *host;
-        struct nand_chip *chip;
+        struct nand_chip *chip = NULL;
         struct mtd_info *mtd;
         struct resource *r;
         int ret, irq, cs;
@@ -1081,21 +1083,31 @@ static int alloc_nand_resource(struct platform_device *pdev)
         }
         clk_enable(info->clk);
 
-        r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "no resource defined for data DMA\n");
-                ret = -ENXIO;
-                goto fail_put_clk;
-        }
-        info->drcmr_dat = r->start;
+        /*
+         * This is a dirty hack to make this driver work from devicetree
+         * bindings. It can be removed once we have a prober DMA controller
+         * framework for DT.
+         */
+        if (pdev->dev.of_node && cpu_is_pxa3xx()) {
+                info->drcmr_dat = 97;
+                info->drcmr_cmd = 99;
+        } else {
+                r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+                if (r == NULL) {
+                        dev_err(&pdev->dev, "no resource defined for data DMA\n");
+                        ret = -ENXIO;
+                        goto fail_put_clk;
+                }
+                info->drcmr_dat = r->start;
 
-        r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "no resource defined for command DMA\n");
-                ret = -ENXIO;
-                goto fail_put_clk;
+                r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+                if (r == NULL) {
+                        dev_err(&pdev->dev, "no resource defined for command DMA\n");
+                        ret = -ENXIO;
+                        goto fail_put_clk;
+                }
+                info->drcmr_cmd = r->start;
         }
-        info->drcmr_cmd = r->start;
 
         irq = platform_get_irq(pdev, 0);
         if (irq < 0) {
@@ -1200,12 +1212,55 @@ static int pxa3xx_nand_remove(struct platform_device *pdev)
         return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id pxa3xx_nand_dt_ids[] = {
+        { .compatible = "marvell,pxa3xx-nand" },
+        {}
+};
+MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
+
+static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
+{
+        struct pxa3xx_nand_platform_data *pdata;
+        struct device_node *np = pdev->dev.of_node;
+        const struct of_device_id *of_id =
+                        of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
+
+        if (!of_id)
+                return 0;
+
+        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+        if (!pdata)
+                return -ENOMEM;
+
+        if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
+                pdata->enable_arbiter = 1;
+        if (of_get_property(np, "marvell,nand-keep-config", NULL))
+                pdata->keep_config = 1;
+        of_property_read_u32(np, "num-cs", &pdata->num_cs);
+
+        pdev->dev.platform_data = pdata;
+
+        return 0;
+}
+#else
+static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
+{
+        return 0;
+}
+#endif
+
 static int pxa3xx_nand_probe(struct platform_device *pdev)
 {
         struct pxa3xx_nand_platform_data *pdata;
+        struct mtd_part_parser_data ppdata = {};
         struct pxa3xx_nand_info *info;
         int ret, cs, probe_success;
 
+        ret = pxa3xx_nand_probe_dt(pdev);
+        if (ret)
+                return ret;
+
         pdata = pdev->dev.platform_data;
         if (!pdata) {
                 dev_err(&pdev->dev, "no platform data defined\n");
@@ -1229,8 +1284,9 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
                         continue;
                 }
 
+                ppdata.of_node = pdev->dev.of_node;
                 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
-                                                NULL, pdata->parts[cs],
+                                                &ppdata, pdata->parts[cs],
                                                 pdata->nr_parts[cs]);
                 if (!ret)
                         probe_success = 1;
@@ -1306,6 +1362,7 @@ static int pxa3xx_nand_resume(struct platform_device *pdev)
 static struct platform_driver pxa3xx_nand_driver = {
         .driver = {
                 .name   = "pxa3xx-nand",
+                .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
         },
         .probe          = pxa3xx_nand_probe,
         .remove         = pxa3xx_nand_remove,
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index 91121f33f743..d8040619ad8d 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -46,7 +46,7 @@
 #include <asm/io.h>
 
 #include <plat/regs-nand.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 
 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
 static int hardware_ecc = 1;
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 9d49b1f4ff53..1961be985171 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -39,7 +39,7 @@
 
 #include <asm/mach/flash.h>
 #include <plat/gpmc.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <asm/gpio.h>
 
 #include <plat/dma.h>
diff --git a/drivers/net/ethernet/netx-eth.c b/drivers/net/ethernet/netx-eth.c
index 9d11ab7521bc..63e7af44366f 100644
--- a/drivers/net/ethernet/netx-eth.c
+++ b/drivers/net/ethernet/netx-eth.c
@@ -34,7 +34,7 @@
 #include <mach/netx-regs.h>
 #include <mach/pfifo.h>
 #include <mach/xc.h>
-#include <mach/eth.h>
+#include <linux/platform_data/eth-netx.h>
 
 /* XC Fifo Offsets */
 #define EMPTY_PTR_FIFO(xcno)    (0 + ((xcno) << 3))     /* Index of the empty pointer FIFO */
diff --git a/drivers/net/ethernet/seeq/ether3.c b/drivers/net/ethernet/seeq/ether3.c
index df808ac8cb65..6a40dd03a32f 100644
--- a/drivers/net/ethernet/seeq/ether3.c
+++ b/drivers/net/ethernet/seeq/ether3.c
@@ -99,13 +99,13 @@ typedef enum {
  * The SEEQ8005 doesn't like us writing to its registers
  * too quickly.
  */
-static inline void ether3_outb(int v, const void __iomem *r)
+static inline void ether3_outb(int v, void __iomem *r)
 {
         writeb(v, r);
         udelay(1);
 }
 
-static inline void ether3_outw(int v, const void __iomem *r)
+static inline void ether3_outw(int v, void __iomem *r)
 {
         writew(v, r);
         udelay(1);
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 8d5476707912..002a442bf73f 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -28,9 +28,9 @@
 #include <net/irda/irda_device.h>
 
 #include <mach/dma.h>
-#include <mach/irda.h>
-#include <mach/regs-uart.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/regs-ost.h>
+#include <mach/regs-uart.h>
 
 #define FICP            __REG(0x40800000)  /* Start of FICP area */
 #define ICCR0           __REG(0x40800000)  /* ICP Control Register 0 */
@@ -112,6 +112,9 @@ struct pxa_irda {
         int                     txdma;
         int                     rxdma;
 
+        int                     uart_irq;
+        int                     icp_irq;
+
         struct irlap_cb         *irlap;
         struct qos_info         qos;
 
@@ -672,19 +675,19 @@ static int pxa_irda_start(struct net_device *dev)
 
         si->speed = 9600;
 
-        err = request_irq(IRQ_STUART, pxa_irda_sir_irq, 0, dev->name, dev);
+        err = request_irq(si->uart_irq, pxa_irda_sir_irq, 0, dev->name, dev);
         if (err)
                 goto err_irq1;
 
-        err = request_irq(IRQ_ICP, pxa_irda_fir_irq, 0, dev->name, dev);
+        err = request_irq(si->icp_irq, pxa_irda_fir_irq, 0, dev->name, dev);
         if (err)
                 goto err_irq2;
 
         /*
          * The interrupt must remain disabled for now.
          */
-        disable_irq(IRQ_STUART);
-        disable_irq(IRQ_ICP);
+        disable_irq(si->uart_irq);
+        disable_irq(si->icp_irq);
 
         err = -EBUSY;
         si->rxdma = pxa_request_dma("FICP_RX",DMA_PRIO_LOW, pxa_irda_fir_dma_rx_irq, dev);
@@ -720,8 +723,8 @@ static int pxa_irda_start(struct net_device *dev)
         /*
          * Now enable the interrupt and start the queue
          */
-        enable_irq(IRQ_STUART);
-        enable_irq(IRQ_ICP);
+        enable_irq(si->uart_irq);
+        enable_irq(si->icp_irq);
         netif_start_queue(dev);
 
         printk(KERN_DEBUG "pxa_ir: irda driver opened\n");
@@ -738,9 +741,9 @@ err_dma_rx_buff:
 err_tx_dma:
         pxa_free_dma(si->rxdma);
 err_rx_dma:
-        free_irq(IRQ_ICP, dev);
+        free_irq(si->icp_irq, dev);
 err_irq2:
-        free_irq(IRQ_STUART, dev);
+        free_irq(si->uart_irq, dev);
 err_irq1:
 
         return err;
@@ -760,8 +763,8 @@ static int pxa_irda_stop(struct net_device *dev)
                 si->irlap = NULL;
         }
 
-        free_irq(IRQ_STUART, dev);
-        free_irq(IRQ_ICP, dev);
+        free_irq(si->uart_irq, dev);
+        free_irq(si->icp_irq, dev);
 
         pxa_free_dma(si->rxdma);
         pxa_free_dma(si->txdma);
@@ -851,6 +854,9 @@ static int pxa_irda_probe(struct platform_device *pdev)
         si->dev = &pdev->dev;
         si->pdata = pdev->dev.platform_data;
 
+        si->uart_irq = platform_get_irq(pdev, 0);
+        si->icp_irq = platform_get_irq(pdev, 1);
+
         si->sir_clk = clk_get(&pdev->dev, "UARTCLK");
         si->fir_clk = clk_get(&pdev->dev, "FICPCLK");
         if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) {
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
index 0ad06a3bd562..fa74efe82206 100644
--- a/drivers/pcmcia/omap_cf.c
+++ b/drivers/pcmcia/omap_cf.c
@@ -24,7 +24,7 @@
 #include <asm/io.h>
 #include <asm/sizes.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 
 
diff --git a/drivers/pcmcia/pxa2xx_viper.c b/drivers/pcmcia/pxa2xx_viper.c
index cb0c37ec7f24..a76f495953ab 100644
--- a/drivers/pcmcia/pxa2xx_viper.c
+++ b/drivers/pcmcia/pxa2xx_viper.c
@@ -25,7 +25,7 @@
 
 #include <asm/irq.h>
 
-#include <mach/arcom-pcmcia.h>
+#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
 
 #include "soc_common.h"
 #include "pxa2xx_base.h"
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588bef62..a75414496369 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -145,6 +145,28 @@ config PINCTRL_COH901
           COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
           ports of 8 GPIO pins each.
 
+config PINCTRL_MVEBU
+        bool
+        depends on ARCH_MVEBU
+        select PINMUX
+        select PINCONF
+
+config PINCTRL_DOVE
+        bool
+        select PINCTRL_MVEBU
+
+config PINCTRL_KIRKWOOD
+        bool
+        select PINCTRL_MVEBU
+
+config PINCTRL_ARMADA_370
+        bool
+        select PINCTRL_MVEBU
+
+config PINCTRL_ARMADA_XP
+        bool
+        select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f81ff2c..f2ea0504efc7 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -29,5 +29,10 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)   += pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)      += pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)    += pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_MVEBU)     += pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE)      += pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD)  += pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 
 obj-$(CONFIG_PLAT_SPEAR)        += spear/
diff --git a/drivers/pinctrl/pinctrl-armada-370.c b/drivers/pinctrl/pinctrl-armada-370.c
new file mode 100644
index 000000000000..c907647de6ad
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-370.c
@@ -0,0 +1,421 @@
+/*
+ * Marvell Armada 370 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
+        MPP_MODE(0,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "uart0", "rxd")),
+        MPP_MODE(1,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "uart0", "txd")),
+        MPP_MODE(2,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "i2c0", "sck"),
+           MPP_FUNCTION(0x2, "uart0", "txd")),
+        MPP_MODE(3,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "i2c0", "sda"),
+           MPP_FUNCTION(0x2, "uart0", "rxd")),
+        MPP_MODE(4,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "cpu_pd", "vdd")),
+        MPP_MODE(5,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txclko"),
+           MPP_FUNCTION(0x2, "uart1", "txd"),
+           MPP_FUNCTION(0x4, "spi1", "clk"),
+           MPP_FUNCTION(0x5, "audio", "mclk")),
+        MPP_MODE(6,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd0"),
+           MPP_FUNCTION(0x2, "sata0", "prsnt"),
+           MPP_FUNCTION(0x4, "tdm", "rst"),
+           MPP_FUNCTION(0x5, "audio", "sdo")),
+        MPP_MODE(7,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd1"),
+           MPP_FUNCTION(0x4, "tdm", "tdx"),
+           MPP_FUNCTION(0x5, "audio", "lrclk")),
+        MPP_MODE(8,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd2"),
+           MPP_FUNCTION(0x2, "uart0", "rts"),
+           MPP_FUNCTION(0x4, "tdm", "drx"),
+           MPP_FUNCTION(0x5, "audio", "bclk")),
+        MPP_MODE(9,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd3"),
+           MPP_FUNCTION(0x2, "uart1", "txd"),
+           MPP_FUNCTION(0x3, "sd0", "clk"),
+           MPP_FUNCTION(0x5, "audio", "spdifo")),
+        MPP_MODE(10,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txctl"),
+           MPP_FUNCTION(0x2, "uart0", "cts"),
+           MPP_FUNCTION(0x4, "tdm", "fsync"),
+           MPP_FUNCTION(0x5, "audio", "sdi")),
+        MPP_MODE(11,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd0"),
+           MPP_FUNCTION(0x2, "uart1", "rxd"),
+           MPP_FUNCTION(0x3, "sd0", "cmd"),
+           MPP_FUNCTION(0x4, "spi0", "cs1"),
+           MPP_FUNCTION(0x5, "sata1", "prsnt"),
+           MPP_FUNCTION(0x6, "spi1", "cs1")),
+        MPP_MODE(12,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd1"),
+           MPP_FUNCTION(0x2, "i2c1", "sda"),
+           MPP_FUNCTION(0x3, "sd0", "d0"),
+           MPP_FUNCTION(0x4, "spi1", "cs0"),
+           MPP_FUNCTION(0x5, "audio", "spdifi")),
+        MPP_MODE(13,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd2"),
+           MPP_FUNCTION(0x2, "i2c1", "sck"),
+           MPP_FUNCTION(0x3, "sd0", "d1"),
+           MPP_FUNCTION(0x4, "tdm", "pclk"),
+           MPP_FUNCTION(0x5, "audio", "rmclk")),
+        MPP_MODE(14,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd3"),
+           MPP_FUNCTION(0x2, "pcie", "clkreq0"),
+           MPP_FUNCTION(0x3, "sd0", "d2"),
+           MPP_FUNCTION(0x4, "spi1", "mosi"),
+           MPP_FUNCTION(0x5, "spi0", "cs2")),
+        MPP_MODE(15,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxctl"),
+           MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+           MPP_FUNCTION(0x3, "sd0", "d3"),
+           MPP_FUNCTION(0x4, "spi1", "miso"),
+           MPP_FUNCTION(0x5, "spi0", "cs3")),
+        MPP_MODE(16,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxclk"),
+           MPP_FUNCTION(0x2, "uart1", "rxd"),
+           MPP_FUNCTION(0x4, "tdm", "int"),
+           MPP_FUNCTION(0x5, "audio", "extclk")),
+        MPP_MODE(17,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge", "mdc")),
+        MPP_MODE(18,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge", "mdio")),
+        MPP_MODE(19,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txclk"),
+           MPP_FUNCTION(0x2, "ge1", "txclkout"),
+           MPP_FUNCTION(0x4, "tdm", "pclk")),
+        MPP_MODE(20,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd4"),
+           MPP_FUNCTION(0x2, "ge1", "txd0")),
+        MPP_MODE(21,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd5"),
+           MPP_FUNCTION(0x2, "ge1", "txd1"),
+           MPP_FUNCTION(0x4, "uart1", "txd")),
+        MPP_MODE(22,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd6"),
+           MPP_FUNCTION(0x2, "ge1", "txd2"),
+           MPP_FUNCTION(0x4, "uart0", "rts")),
+        MPP_MODE(23,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd7"),
+           MPP_FUNCTION(0x2, "ge1", "txd3"),
+           MPP_FUNCTION(0x4, "spi1", "mosi")),
+        MPP_MODE(24,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "col"),
+           MPP_FUNCTION(0x2, "ge1", "txctl"),
+           MPP_FUNCTION(0x4, "spi1", "cs0")),
+        MPP_MODE(25,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxerr"),
+           MPP_FUNCTION(0x2, "ge1", "rxd0"),
+           MPP_FUNCTION(0x4, "uart1", "rxd")),
+        MPP_MODE(26,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "crs"),
+           MPP_FUNCTION(0x2, "ge1", "rxd1"),
+           MPP_FUNCTION(0x4, "spi1", "miso")),
+        MPP_MODE(27,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd4"),
+           MPP_FUNCTION(0x2, "ge1", "rxd2"),
+           MPP_FUNCTION(0x4, "uart0", "cts")),
+        MPP_MODE(28,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd5"),
+           MPP_FUNCTION(0x2, "ge1", "rxd3")),
+        MPP_MODE(29,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd6"),
+           MPP_FUNCTION(0x2, "ge1", "rxctl"),
+           MPP_FUNCTION(0x4, "i2c1", "sda")),
+        MPP_MODE(30,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd7"),
+           MPP_FUNCTION(0x2, "ge1", "rxclk"),
+           MPP_FUNCTION(0x4, "i2c1", "sck")),
+        MPP_MODE(31,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x3, "tclk", NULL),
+           MPP_FUNCTION(0x4, "ge0", "txerr")),
+        MPP_MODE(32,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "spi0", "cs0")),
+        MPP_MODE(33,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "bootcs"),
+           MPP_FUNCTION(0x2, "spi0", "cs0")),
+        MPP_MODE(34,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "wen0"),
+           MPP_FUNCTION(0x2, "spi0", "mosi")),
+        MPP_MODE(35,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "oen"),
+           MPP_FUNCTION(0x2, "spi0", "sck")),
+        MPP_MODE(36,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "a1"),
+           MPP_FUNCTION(0x2, "spi0", "miso")),
+        MPP_MODE(37,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "a0"),
+           MPP_FUNCTION(0x2, "sata0", "prsnt")),
+        MPP_MODE(38,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ready"),
+           MPP_FUNCTION(0x2, "uart1", "cts"),
+           MPP_FUNCTION(0x3, "uart0", "cts")),
+        MPP_MODE(39,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad0"),
+           MPP_FUNCTION(0x2, "audio", "spdifo")),
+        MPP_MODE(40,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad1"),
+           MPP_FUNCTION(0x2, "uart1", "rts"),
+           MPP_FUNCTION(0x3, "uart0", "rts")),
+        MPP_MODE(41,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad2"),
+           MPP_FUNCTION(0x2, "uart1", "rxd")),
+        MPP_MODE(42,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad3"),
+           MPP_FUNCTION(0x2, "uart1", "txd")),
+        MPP_MODE(43,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad4"),
+           MPP_FUNCTION(0x2, "audio", "bclk")),
+        MPP_MODE(44,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad5"),
+           MPP_FUNCTION(0x2, "audio", "mclk")),
+        MPP_MODE(45,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad6"),
+           MPP_FUNCTION(0x2, "audio", "lrclk")),
+        MPP_MODE(46,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad7"),
+           MPP_FUNCTION(0x2, "audio", "sdo")),
+        MPP_MODE(47,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad8"),
+           MPP_FUNCTION(0x3, "sd0", "clk"),
+           MPP_FUNCTION(0x5, "audio", "spdifo")),
+        MPP_MODE(48,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad9"),
+           MPP_FUNCTION(0x2, "uart0", "rts"),
+           MPP_FUNCTION(0x3, "sd0", "cmd"),
+           MPP_FUNCTION(0x4, "sata1", "prsnt"),
+           MPP_FUNCTION(0x5, "spi0", "cs1")),
+        MPP_MODE(49,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad10"),
+           MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+           MPP_FUNCTION(0x3, "sd0", "d0"),
+           MPP_FUNCTION(0x4, "spi1", "cs0"),
+           MPP_FUNCTION(0x5, "audio", "spdifi")),
+        MPP_MODE(50,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad11"),
+           MPP_FUNCTION(0x2, "uart0", "cts"),
+           MPP_FUNCTION(0x3, "sd0", "d1"),
+           MPP_FUNCTION(0x4, "spi1", "miso"),
+           MPP_FUNCTION(0x5, "audio", "rmclk")),
+        MPP_MODE(51,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad12"),
+           MPP_FUNCTION(0x2, "i2c1", "sda"),
+           MPP_FUNCTION(0x3, "sd0", "d2"),
+           MPP_FUNCTION(0x4, "spi1", "mosi")),
+        MPP_MODE(52,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad13"),
+           MPP_FUNCTION(0x2, "i2c1", "sck"),
+           MPP_FUNCTION(0x3, "sd0", "d3"),
+           MPP_FUNCTION(0x4, "spi1", "sck")),
+        MPP_MODE(53,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad14"),
+           MPP_FUNCTION(0x2, "sd0", "clk"),
+           MPP_FUNCTION(0x3, "tdm", "pclk"),
+           MPP_FUNCTION(0x4, "spi0", "cs2"),
+           MPP_FUNCTION(0x5, "pcie", "clkreq1")),
+        MPP_MODE(54,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad15"),
+           MPP_FUNCTION(0x3, "tdm", "dtx")),
+        MPP_MODE(55,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "cs1"),
+           MPP_FUNCTION(0x2, "uart1", "txd"),
+           MPP_FUNCTION(0x3, "tdm", "rst"),
+           MPP_FUNCTION(0x4, "sata1", "prsnt"),
+           MPP_FUNCTION(0x5, "sata0", "prsnt")),
+        MPP_MODE(56,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "cs2"),
+           MPP_FUNCTION(0x2, "uart1", "cts"),
+           MPP_FUNCTION(0x3, "uart0", "cts"),
+           MPP_FUNCTION(0x4, "spi0", "cs3"),
+           MPP_FUNCTION(0x5, "pcie", "clkreq0"),
+           MPP_FUNCTION(0x6, "spi1", "cs1")),
+        MPP_MODE(57,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "cs3"),
+           MPP_FUNCTION(0x2, "uart1", "rxd"),
+           MPP_FUNCTION(0x3, "tdm", "fsync"),
+           MPP_FUNCTION(0x4, "sata0", "prsnt"),
+           MPP_FUNCTION(0x5, "audio", "sdo")),
+        MPP_MODE(58,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "cs0"),
+           MPP_FUNCTION(0x2, "uart1", "rts"),
+           MPP_FUNCTION(0x3, "tdm", "int"),
+           MPP_FUNCTION(0x5, "audio", "extclk"),
+           MPP_FUNCTION(0x6, "uart0", "rts")),
+        MPP_MODE(59,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ale0"),
+           MPP_FUNCTION(0x2, "uart1", "rts"),
+           MPP_FUNCTION(0x3, "uart0", "rts"),
+           MPP_FUNCTION(0x5, "audio", "bclk")),
+        MPP_MODE(60,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ale1"),
+           MPP_FUNCTION(0x2, "uart1", "rxd"),
+           MPP_FUNCTION(0x3, "sata0", "prsnt"),
+           MPP_FUNCTION(0x4, "pcie", "rst-out"),
+           MPP_FUNCTION(0x5, "audio", "sdi")),
+        MPP_MODE(61,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "wen1"),
+           MPP_FUNCTION(0x2, "uart1", "txd"),
+           MPP_FUNCTION(0x5, "audio", "rclk")),
+        MPP_MODE(62,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "a2"),
+           MPP_FUNCTION(0x2, "uart1", "cts"),
+           MPP_FUNCTION(0x3, "tdm", "drx"),
+           MPP_FUNCTION(0x4, "pcie", "clkreq0"),
+           MPP_FUNCTION(0x5, "audio", "mclk"),
+           MPP_FUNCTION(0x6, "uart0", "cts")),
+        MPP_MODE(63,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "spi0", "sck"),
+           MPP_FUNCTION(0x2, "tclk", NULL)),
+        MPP_MODE(64,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "spi0", "miso"),
+           MPP_FUNCTION(0x2, "spi0-1", "cs1")),
+        MPP_MODE(65,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "spi0", "mosi"),
+           MPP_FUNCTION(0x2, "spi0-1", "cs2")),
+};
+
+static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
+
+static struct of_device_id armada_370_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "marvell,mv88f6710-pinctrl" },
+        { },
+};
+
+static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
+        MPP_REG_CTRL(0, 65),
+};
+
+static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,   0,  0, 32),
+        MPP_GPIO_RANGE(1,  32, 32, 32),
+        MPP_GPIO_RANGE(2,  64, 64,  2),
+};
+
+static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
+{
+        struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
+
+        soc->variant = 0; /* no variants for Armada 370 */
+        soc->controls = mv88f6710_mpp_controls;
+        soc->ncontrols = ARRAY_SIZE(mv88f6710_mpp_controls);
+        soc->modes = mv88f6710_mpp_modes;
+        soc->nmodes = ARRAY_SIZE(mv88f6710_mpp_modes);
+        soc->gpioranges = mv88f6710_mpp_gpio_ranges;
+        soc->ngpioranges = ARRAY_SIZE(mv88f6710_mpp_gpio_ranges);
+
+        pdev->dev.platform_data = soc;
+
+        return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_370_pinctrl_remove(struct platform_device *pdev)
+{
+        return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_370_pinctrl_driver = {
+        .driver = {
+                .name = "armada-370-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(armada_370_pinctrl_of_match),
+        },
+        .probe = armada_370_pinctrl_probe,
+        .remove = __devexit_p(armada_370_pinctrl_remove),
+};
+
+module_platform_driver(armada_370_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada 370 pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-armada-xp.c b/drivers/pinctrl/pinctrl-armada-xp.c
new file mode 100644
index 000000000000..40bd52a46b4e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-xp.c
@@ -0,0 +1,468 @@
+/*
+ * Marvell Armada XP pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file supports the three variants of Armada XP SoCs that are
+ * available: mv78230, mv78260 and mv78460. From a pin muxing
+ * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
+ * both have 67 MPP pins (more GPIOs and address lines for the memory
+ * bus mainly). The only difference between the mv78260 and the
+ * mv78460 in terms of pin muxing is the addition of two functions on
+ * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
+ * cores, mv78460 has four cores).
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/bitops.h>
+
+#include "pinctrl-mvebu.h"
+
+enum armada_xp_variant {
+        V_MV78230       = BIT(0),
+        V_MV78260       = BIT(1),
+        V_MV78460       = BIT(2),
+        V_MV78230_PLUS  = (V_MV78230 | V_MV78260 | V_MV78460),
+        V_MV78260_PLUS  = (V_MV78260 | V_MV78460),
+};
+
+static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
+        MPP_MODE(0,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txclko",     V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d0",         V_MV78230_PLUS)),
+        MPP_MODE(1,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d1",         V_MV78230_PLUS)),
+        MPP_MODE(2,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd1",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d2",         V_MV78230_PLUS)),
+        MPP_MODE(3,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d3",         V_MV78230_PLUS)),
+        MPP_MODE(4,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d4",         V_MV78230_PLUS)),
+        MPP_MODE(5,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txctl",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d5",         V_MV78230_PLUS)),
+        MPP_MODE(6,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d6",         V_MV78230_PLUS)),
+        MPP_MODE(7,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd1",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d7",         V_MV78230_PLUS)),
+        MPP_MODE(8,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d8",         V_MV78230_PLUS)),
+        MPP_MODE(9,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d9",         V_MV78230_PLUS)),
+        MPP_MODE(10,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxctl",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d10",        V_MV78230_PLUS)),
+        MPP_MODE(11,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxclk",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d11",        V_MV78230_PLUS)),
+        MPP_MODE(12,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd4",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "clkout",     V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d12",        V_MV78230_PLUS)),
+        MPP_MODE(13,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd5",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txd0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d13",        V_MV78230_PLUS)),
+        MPP_MODE(14,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd6",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txd1",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d14",        V_MV78230_PLUS)),
+        MPP_MODE(15,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd7",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txd2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d15",        V_MV78230_PLUS)),
+        MPP_MODE(16,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txclk",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txd3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d16",        V_MV78230_PLUS)),
+        MPP_MODE(17,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "col",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txctl",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d17",        V_MV78230_PLUS)),
+        MPP_MODE(18,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxerr",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxd0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "ptp", "trig",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d18",        V_MV78230_PLUS)),
+        MPP_MODE(19,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "crs",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxd1",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "ptp", "evreq",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d19",        V_MV78230_PLUS)),
+        MPP_MODE(20,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd4",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxd2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "ptp", "clk",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d20",        V_MV78230_PLUS)),
+        MPP_MODE(21,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd5",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxd3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "mem", "bat",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d21",        V_MV78230_PLUS)),
+        MPP_MODE(22,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd6",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxctl",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "sata0", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d22",        V_MV78230_PLUS)),
+        MPP_MODE(23,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd7",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxclk",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d23",        V_MV78230_PLUS)),
+        MPP_MODE(24,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sata1", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re",   V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "rst",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "hsync",      V_MV78230_PLUS)),
+        MPP_MODE(25,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sata0", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we",   V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "pclk",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "vsync",      V_MV78230_PLUS)),
+        MPP_MODE(26,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "fsync",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "clk",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+        MPP_MODE(27,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ptp", "trig",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "dtx",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "e",          V_MV78230_PLUS)),
+        MPP_MODE(28,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ptp", "evreq",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "drx",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "pwm",        V_MV78230_PLUS)),
+        MPP_MODE(29,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ptp", "clk",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+        MPP_MODE(30,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "clk",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int1",       V_MV78230_PLUS)),
+        MPP_MODE(31,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "cmd",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+        MPP_MODE(32,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "d0",         V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+        MPP_MODE(33,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "d1",         V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int4",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "mem", "bat",        V_MV78230_PLUS)),
+        MPP_MODE(34,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "d2",         V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "sata0", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int5",       V_MV78230_PLUS)),
+        MPP_MODE(35,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "d3",         V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "sata1", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int6",       V_MV78230_PLUS)),
+        MPP_MODE(36,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "mosi",       V_MV78230_PLUS)),
+        MPP_MODE(37,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "miso",       V_MV78230_PLUS)),
+        MPP_MODE(38,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "sck",        V_MV78230_PLUS)),
+        MPP_MODE(39,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "cs0",        V_MV78230_PLUS)),
+        MPP_MODE(40,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "cs1",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart2", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync",  V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0",   V_MV78230_PLUS)),
+        MPP_MODE(41,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "cs2",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart2", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync",  V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1",   V_MV78230_PLUS)),
+        MPP_MODE(42,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart2", "rxd",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart0", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int7",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "tdm-1", "timer",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+        MPP_MODE(43,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart2", "txd",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart0", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs3",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "pcie", "rstout",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd",  V_MV78460)),
+        MPP_MODE(44,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart2", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart3", "rxd",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs4",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "mem", "bat",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2",   V_MV78230_PLUS)),
+        MPP_MODE(45,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart2", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart3", "txd",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs5",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",    V_MV78230_PLUS)),
+        MPP_MODE(46,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart3", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart1", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs6",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",    V_MV78230_PLUS)),
+        MPP_MODE(47,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart3", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart1", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs7",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "ref", "clkout",     V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3",   V_MV78230_PLUS)),
+        MPP_MODE(48,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "tclk", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)),
+        MPP_MODE(49,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "we3",        V_MV78260_PLUS)),
+        MPP_MODE(50,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "we2",        V_MV78260_PLUS)),
+        MPP_MODE(51,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad16",       V_MV78260_PLUS)),
+        MPP_MODE(52,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad17",       V_MV78260_PLUS)),
+        MPP_MODE(53,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad18",       V_MV78260_PLUS)),
+        MPP_MODE(54,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad19",       V_MV78260_PLUS)),
+        MPP_MODE(55,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad20",       V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd",    V_MV78260_PLUS)),
+        MPP_MODE(56,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad21",       V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd",    V_MV78260_PLUS)),
+        MPP_MODE(57,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad22",       V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd",  V_MV78460)),
+        MPP_MODE(58,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad23",       V_MV78260_PLUS)),
+        MPP_MODE(59,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad24",       V_MV78260_PLUS)),
+        MPP_MODE(60,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad25",       V_MV78260_PLUS)),
+        MPP_MODE(61,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad26",       V_MV78260_PLUS)),
+        MPP_MODE(62,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad27",       V_MV78260_PLUS)),
+        MPP_MODE(63,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad28",       V_MV78260_PLUS)),
+        MPP_MODE(64,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad29",       V_MV78260_PLUS)),
+        MPP_MODE(65,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad30",       V_MV78260_PLUS)),
+        MPP_MODE(66,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad31",       V_MV78260_PLUS)),
+};
+
+static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
+
+static struct of_device_id armada_xp_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "marvell,mv78230-pinctrl",
+                .data       = (void *) V_MV78230,
+        },
+        {
+                .compatible = "marvell,mv78260-pinctrl",
+                .data       = (void *) V_MV78260,
+        },
+        {
+                .compatible = "marvell,mv78460-pinctrl",
+                .data       = (void *) V_MV78460,
+        },
+        { },
+};
+
+static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
+        MPP_REG_CTRL(0, 48),
+};
+
+static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,   0,  0, 32),
+        MPP_GPIO_RANGE(1,  32, 32, 17),
+};
+
+static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
+        MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,   0,  0, 32),
+        MPP_GPIO_RANGE(1,  32, 32, 32),
+        MPP_GPIO_RANGE(2,  64, 64,  3),
+};
+
+static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
+        MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,   0,  0, 32),
+        MPP_GPIO_RANGE(1,  32, 32, 32),
+        MPP_GPIO_RANGE(2,  64, 64,  3),
+};
+
+static int __devinit armada_xp_pinctrl_probe(struct platform_device *pdev)
+{
+        struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
+        const struct of_device_id *match =
+                of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
+
+        if (!match)
+                return -ENODEV;
+
+        soc->variant = (unsigned) match->data & 0xff;
+
+        switch (soc->variant) {
+        case V_MV78230:
+                soc->controls = mv78230_mpp_controls;
+                soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
+                soc->modes = armada_xp_mpp_modes;
+                /* We don't necessarily want the full list of the
+                 * armada_xp_mpp_modes, but only the first 'n' ones
+                 * that are available on this SoC */
+                soc->nmodes = mv78230_mpp_controls[0].npins;
+                soc->gpioranges = mv78230_mpp_gpio_ranges;
+                soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
+                break;
+        case V_MV78260:
+                soc->controls = mv78260_mpp_controls;
+                soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
+                soc->modes = armada_xp_mpp_modes;
+                /* We don't necessarily want the full list of the
+                 * armada_xp_mpp_modes, but only the first 'n' ones
+                 * that are available on this SoC */
+                soc->nmodes = mv78260_mpp_controls[0].npins;
+                soc->gpioranges = mv78260_mpp_gpio_ranges;
+                soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
+                break;
+        case V_MV78460:
+                soc->controls = mv78460_mpp_controls;
+                soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
+                soc->modes = armada_xp_mpp_modes;
+                /* We don't necessarily want the full list of the
+                 * armada_xp_mpp_modes, but only the first 'n' ones
+                 * that are available on this SoC */
+                soc->nmodes = mv78460_mpp_controls[0].npins;
+                soc->gpioranges = mv78460_mpp_gpio_ranges;
+                soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
+                break;
+        }
+
+        pdev->dev.platform_data = soc;
+
+        return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_xp_pinctrl_remove(struct platform_device *pdev)
+{
+        return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_xp_pinctrl_driver = {
+        .driver = {
+                .name = "armada-xp-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(armada_xp_pinctrl_of_match),
+        },
+        .probe = armada_xp_pinctrl_probe,
+        .remove = __devexit_p(armada_xp_pinctrl_remove),
+};
+
+module_platform_driver(armada_xp_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada XP pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index cc0f00d73d15..b446c9641212 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -1,11 +1,8 @@
 /*
  * U300 GPIO module.
  *
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
- * This can driver either of the two basic GPIO cores
- * available in the U300 platforms:
- * COH 901 335   - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
  * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
  * Author: Linus Walleij <linus.walleij@linaro.org>
  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
@@ -24,19 +21,22 @@
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <mach/gpio-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
 #include "pinctrl-coh901.h"
 
+#define U300_GPIO_PORT_STRIDE                           (0x30)
 /*
- * Register definitions for COH 901 335 variant
+ * Control Register 32bit (R/W)
+ * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
+ * gives the number of GPIO pins.
+ * bit 8-2  (mask 0x000001FC) contains the core version ID.
  */
-#define U300_335_PORT_STRIDE                            (0x1C)
-/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
-#define U300_335_PXPDIR                                 (0x00)
-#define U300_335_PXPDOR                                 (0x00)
-/* Port X Pin Config Register 32bit (R/W) */
-#define U300_335_PXPCR                                  (0x04)
-/* This register layout is the same in both blocks */
+#define U300_GPIO_CR                                    (0x00)
+#define U300_GPIO_CR_SYNC_SEL_ENABLE                    (0x00000002UL)
+#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE                 (0x00000001UL)
+#define U300_GPIO_PXPDIR                                (0x04)
+#define U300_GPIO_PXPDOR                                (0x08)
+#define U300_GPIO_PXPCR                                 (0x0C)
 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
 #define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
@@ -44,53 +44,17 @@
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
-/* Port X Interrupt Event Register 32bit (R/W) */
-#define U300_335_PXIEV                                  (0x08)
-/* Port X Interrupt Enable Register 32bit (R/W) */
-#define U300_335_PXIEN                                  (0x0C)
-/* Port X Interrupt Force Register 32bit (R/W) */
-#define U300_335_PXIFR                                  (0x10)
-/* Port X Interrupt Config Register 32bit (R/W) */
-#define U300_335_PXICR                                  (0x14)
-/* This register layout is the same in both blocks */
+#define U300_GPIO_PXPER                                 (0x10)
+#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
+#define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
+#define U300_GPIO_PXIEV                                 (0x14)
+#define U300_GPIO_PXIEN                                 (0x18)
+#define U300_GPIO_PXIFR                                 (0x1C)
+#define U300_GPIO_PXICR                                 (0x20)
 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
-/* Port X Pull-up Enable Register 32bit (R/W) */
-#define U300_335_PXPER                                  (0x18)
-/* This register layout is the same in both blocks */
-#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
-#define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
-/* Control Register 32bit (R/W) */
-#define U300_335_CR                                     (0x54)
-#define U300_335_CR_BLOCK_CLOCK_ENABLE                  (0x00000001UL)
-
-/*
- * Register definitions for COH 901 571 / 3 variant
- */
-#define U300_571_PORT_STRIDE                            (0x30)
-/*
- * Control Register 32bit (R/W)
- * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
- * gives the number of GPIO pins.
- * bit 8-2  (mask 0x000001FC) contains the core version ID.
- */
-#define U300_571_CR                                     (0x00)
-#define U300_571_CR_SYNC_SEL_ENABLE                     (0x00000002UL)
-#define U300_571_CR_BLOCK_CLKRQ_ENABLE                  (0x00000001UL)
-/*
- * These registers have the same layout and function as the corresponding
- * COH 901 335 registers, just at different offset.
- */
-#define U300_571_PXPDIR                                 (0x04)
-#define U300_571_PXPDOR                                 (0x08)
-#define U300_571_PXPCR                                  (0x0C)
-#define U300_571_PXPER                                  (0x10)
-#define U300_571_PXIEV                                  (0x14)
-#define U300_571_PXIEN                                  (0x18)
-#define U300_571_PXIFR                                  (0x1C)
-#define U300_571_PXICR                                  (0x20)
 
 /* 8 bits per port, no version has more than 7 ports */
 #define U300_GPIO_PINS_PER_PORT 8
@@ -149,8 +113,6 @@ struct u300_gpio_confdata {
 
 /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
 #define BS335_GPIO_NUM_PORTS 7
-/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
-#define BS365_GPIO_NUM_PORTS 5
 
 #define U300_FLOATING_INPUT { \
         .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
@@ -172,7 +134,6 @@ struct u300_gpio_confdata {
         .outval = 1, \
 }
 
-
 /* Initial configuration */
 static const struct __initconst u300_gpio_confdata
 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
@@ -255,66 +216,6 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         }
 };
 
-static const struct __initconst u300_gpio_confdata
-bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
-        /* Port 0, pins 0-7 */
-        {
-                U300_FLOATING_INPUT,
-                U300_OUTPUT_LOW,
-                U300_FLOATING_INPUT,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_PULL_UP_INPUT,
-                U300_FLOATING_INPUT,
-        },
-        /* Port 1, pins 0-7 */
-        {
-                U300_OUTPUT_LOW,
-                U300_FLOATING_INPUT,
-                U300_OUTPUT_LOW,
-                U300_FLOATING_INPUT,
-                U300_FLOATING_INPUT,
-                U300_OUTPUT_HIGH,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-        },
-        /* Port 2, pins 0-7 */
-        {
-                U300_FLOATING_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-        },
-        /* Port 3, pins 0-7 */
-        {
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-        },
-        /* Port 4, pins 0-7 */
-        {
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                U300_PULL_UP_INPUT,
-                /* These 4 pins doesn't exist on DB3210 */
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-                U300_OUTPUT_LOW,
-        }
-};
-
 /**
  * to_u300_gpio() - get the pointer to u300_gpio
  * @chip: the gpio chip member of the structure u300_gpio
@@ -716,13 +617,7 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
                         const struct u300_gpio_confdata *conf;
                         int offset = (i*8) + j;
 
-                        if (plat->variant == U300_GPIO_COH901571_3_BS335)
-                                conf = &bs335_gpio_config[i][j];
-                        else if (plat->variant == U300_GPIO_COH901571_3_BS365)
-                                conf = &bs365_gpio_config[i][j];
-                        else
-                                break;
-
+                        conf = &bs335_gpio_config[i][j];
                         u300_gpio_init_pin(gpio, offset, conf);
                 }
         }
@@ -796,50 +691,27 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
                 goto err_no_ioremap;
         }
 
-        if (plat->variant == U300_GPIO_COH901335) {
-                dev_info(gpio->dev,
-                         "initializing GPIO Controller COH 901 335\n");
-                gpio->stride = U300_335_PORT_STRIDE;
-                gpio->pcr = U300_335_PXPCR;
-                gpio->dor = U300_335_PXPDOR;
-                gpio->dir = U300_335_PXPDIR;
-                gpio->per = U300_335_PXPER;
-                gpio->icr = U300_335_PXICR;
-                gpio->ien = U300_335_PXIEN;
-                gpio->iev = U300_335_PXIEV;
-                ifr = U300_335_PXIFR;
-
-                /* Turn on the GPIO block */
-                writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
-                       gpio->base + U300_335_CR);
-        } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
-                   plat->variant == U300_GPIO_COH901571_3_BS365) {
-                dev_info(gpio->dev,
-                         "initializing GPIO Controller COH 901 571/3\n");
-                gpio->stride = U300_571_PORT_STRIDE;
-                gpio->pcr = U300_571_PXPCR;
-                gpio->dor = U300_571_PXPDOR;
-                gpio->dir = U300_571_PXPDIR;
-                gpio->per = U300_571_PXPER;
-                gpio->icr = U300_571_PXICR;
-                gpio->ien = U300_571_PXIEN;
-                gpio->iev = U300_571_PXIEV;
-                ifr = U300_571_PXIFR;
-
-                val = readl(gpio->base + U300_571_CR);
-                dev_info(gpio->dev, "COH901571/3 block version: %d, " \
-                         "number of cores: %d totalling %d pins\n",
-                         ((val & 0x000001FC) >> 2),
-                         ((val & 0x0000FE00) >> 9),
-                         ((val & 0x0000FE00) >> 9) * 8);
-                writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
-                       gpio->base + U300_571_CR);
-                u300_gpio_init_coh901571(gpio, plat);
-        } else {
-                dev_err(gpio->dev, "unknown block variant\n");
-                err = -ENODEV;
-                goto err_unknown_variant;
-        }
+        dev_info(gpio->dev,
+                 "initializing GPIO Controller COH 901 571/3\n");
+        gpio->stride = U300_GPIO_PORT_STRIDE;
+        gpio->pcr = U300_GPIO_PXPCR;
+        gpio->dor = U300_GPIO_PXPDOR;
+        gpio->dir = U300_GPIO_PXPDIR;
+        gpio->per = U300_GPIO_PXPER;
+        gpio->icr = U300_GPIO_PXICR;
+        gpio->ien = U300_GPIO_PXIEN;
+        gpio->iev = U300_GPIO_PXIEV;
+        ifr = U300_GPIO_PXIFR;
+
+        val = readl(gpio->base + U300_GPIO_CR);
+        dev_info(gpio->dev, "COH901571/3 block version: %d, " \
+                 "number of cores: %d totalling %d pins\n",
+                 ((val & 0x000001FC) >> 2),
+                 ((val & 0x0000FE00) >> 9),
+                 ((val & 0x0000FE00) >> 9) * 8);
+        writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
+               gpio->base + U300_GPIO_CR);
+        u300_gpio_init_coh901571(gpio, plat);
 
         /* Add each port with its IRQ separately */
         INIT_LIST_HEAD(&gpio->port_list);
@@ -906,7 +778,6 @@ err_no_pinctrl:
 err_no_chip:
 err_no_port:
         u300_gpio_free_ports(gpio);
-err_unknown_variant:
         iounmap(gpio->base);
 err_no_ioremap:
         release_mem_region(gpio->memres->start, resource_size(gpio->memres));
@@ -923,16 +794,11 @@ err_no_clk:
 
 static int __exit u300_gpio_remove(struct platform_device *pdev)
 {
-        struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
         struct u300_gpio *gpio = platform_get_drvdata(pdev);
         int err;
 
         /* Turn off the GPIO block */
-        if (plat->variant == U300_GPIO_COH901335)
-                writel(0x00000000U, gpio->base + U300_335_CR);
-        if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
-            plat->variant == U300_GPIO_COH901571_3_BS365)
-                writel(0x00000000U, gpio->base + U300_571_CR);
+        writel(0x00000000U, gpio->base + U300_GPIO_CR);
 
         err = gpiochip_remove(&gpio->chip);
         if (err < 0) {
diff --git a/drivers/pinctrl/pinctrl-dove.c b/drivers/pinctrl/pinctrl-dove.c
new file mode 100644
index 000000000000..ffe74b27d66d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-dove.c
@@ -0,0 +1,620 @@
+/*
+ * Marvell Dove pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define DOVE_SB_REGS_VIRT_BASE          0xfde00000
+#define DOVE_MPP_VIRT_BASE              (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_PMU_MPP_GENERAL_CTRL       (DOVE_MPP_VIRT_BASE + 0x10)
+#define  DOVE_AU0_AC97_SEL              BIT(16)
+#define DOVE_GLOBAL_CONFIG_1            (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define  DOVE_TWSI_ENABLE_OPTION1       BIT(7)
+#define DOVE_GLOBAL_CONFIG_2            (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define  DOVE_TWSI_ENABLE_OPTION2       BIT(20)
+#define  DOVE_TWSI_ENABLE_OPTION3       BIT(21)
+#define  DOVE_TWSI_OPTION3_GPIO         BIT(22)
+#define DOVE_SSP_CTRL_STATUS_1          (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define  DOVE_SSP_ON_AU1                BIT(0)
+#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define  DOVE_AU1_SPDIFO_GPIO_EN        BIT(1)
+#define  DOVE_NAND_GPIO_EN              BIT(0)
+#define DOVE_GPIO_LO_VIRT_BASE          (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_LO_VIRT_BASE + 0x40)
+#define  DOVE_SPI_GPIO_SEL              BIT(5)
+#define  DOVE_UART1_GPIO_SEL            BIT(4)
+#define  DOVE_AU1_GPIO_SEL              BIT(3)
+#define  DOVE_CAM_GPIO_SEL              BIT(2)
+#define  DOVE_SD1_GPIO_SEL              BIT(1)
+#define  DOVE_SD0_GPIO_SEL              BIT(0)
+
+#define MPPS_PER_REG    8
+#define MPP_BITS        4
+#define MPP_MASK        0xf
+
+#define CONFIG_PMU      BIT(4)
+
+static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                                 unsigned long *config)
+{
+        unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
+        unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
+        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+        if (pmu & (1 << ctrl->pid))
+                *config = CONFIG_PMU;
+        else
+                *config = (mpp >> shift) & MPP_MASK;
+        return 0;
+}
+
+static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                                 unsigned long config)
+{
+        unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
+        unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
+        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+        if (config == CONFIG_PMU)
+                writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+        else {
+                writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+                mpp &= ~(MPP_MASK << shift);
+                mpp |= config << shift;
+                writel(mpp, DOVE_MPP_VIRT_BASE + off);
+        }
+        return 0;
+}
+
+static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long *config)
+{
+        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long mask;
+
+        switch (ctrl->pid) {
+        case 24: /* mpp_camera */
+                mask = DOVE_CAM_GPIO_SEL;
+                break;
+        case 40: /* mpp_sdio0 */
+                mask = DOVE_SD0_GPIO_SEL;
+                break;
+        case 46: /* mpp_sdio1 */
+                mask = DOVE_SD1_GPIO_SEL;
+                break;
+        case 58: /* mpp_spi0 */
+                mask = DOVE_SPI_GPIO_SEL;
+                break;
+        case 62: /* mpp_uart1 */
+                mask = DOVE_UART1_GPIO_SEL;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        *config = ((mpp4 & mask) != 0);
+
+        return 0;
+}
+
+static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long config)
+{
+        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long mask;
+
+        switch (ctrl->pid) {
+        case 24: /* mpp_camera */
+                mask = DOVE_CAM_GPIO_SEL;
+                break;
+        case 40: /* mpp_sdio0 */
+                mask = DOVE_SD0_GPIO_SEL;
+                break;
+        case 46: /* mpp_sdio1 */
+                mask = DOVE_SD1_GPIO_SEL;
+                break;
+        case 58: /* mpp_spi0 */
+                mask = DOVE_SPI_GPIO_SEL;
+                break;
+        case 62: /* mpp_uart1 */
+                mask = DOVE_UART1_GPIO_SEL;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        mpp4 &= ~mask;
+        if (config)
+                mpp4 |= mask;
+
+        writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+
+        return 0;
+}
+
+static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long *config)
+{
+        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+        *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0);
+
+        return 0;
+}
+
+static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long config)
+{
+        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+        gmpp &= ~DOVE_NAND_GPIO_EN;
+        if (config)
+                gmpp |= DOVE_NAND_GPIO_EN;
+
+        writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+
+        return 0;
+}
+
+static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long *config)
+{
+        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+        *config = ((pmu & DOVE_AU0_AC97_SEL) != 0);
+
+        return 0;
+}
+
+static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long config)
+{
+        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+        pmu &= ~DOVE_AU0_AC97_SEL;
+        if (config)
+                pmu |= DOVE_AU0_AC97_SEL;
+        writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL);
+
+        return 0;
+}
+
+static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long *config)
+{
+        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        *config = 0;
+        if (mpp4 & DOVE_AU1_GPIO_SEL)
+                *config |= BIT(3);
+        if (sspc1 & DOVE_SSP_ON_AU1)
+                *config |= BIT(2);
+        if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
+                *config |= BIT(1);
+        if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
+                *config |= BIT(0);
+
+        /* SSP/TWSI only if I2S1 not set*/
+        if ((*config & BIT(3)) == 0)
+                *config &= ~(BIT(2) | BIT(0));
+        /* TWSI only if SPDIFO not set*/
+        if ((*config & BIT(1)) == 0)
+                *config &= ~BIT(0);
+        return 0;
+}
+
+static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long config)
+{
+        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        if (config & BIT(0))
+                gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
+        if (config & BIT(1))
+                gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
+        if (config & BIT(2))
+                sspc1 |= DOVE_SSP_ON_AU1;
+        if (config & BIT(3))
+                mpp4 |= DOVE_AU1_GPIO_SEL;
+
+        writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+        writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
+        writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+        writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+        return 0;
+}
+
+/* mpp[52:57] gpio pins depend heavily on current config;
+ * gpio_req does not try to mux in gpio capabilities to not
+ * break other functions. If you require all mpps as gpio
+ * enforce gpio setting by pinctrl mapping.
+ */
+static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
+{
+        unsigned long config;
+
+        dove_audio1_ctrl_get(ctrl, &config);
+
+        switch (config) {
+        case 0x02: /* i2s1 : gpio[56:57] */
+        case 0x0e: /* ssp  : gpio[56:57] */
+                if (pid >= 56)
+                        return 0;
+                return -ENOTSUPP;
+        case 0x08: /* spdifo : gpio[52:55] */
+        case 0x0b: /* twsi   : gpio[52:55] */
+                if (pid <= 55)
+                        return 0;
+                return -ENOTSUPP;
+        case 0x0a: /* all gpio */
+                return 0;
+        /* 0x00 : i2s1/spdifo : no gpio */
+        /* 0x0c : ssp/spdifo  : no gpio */
+        /* 0x0f : ssp/twsi    : no gpio */
+        }
+        return -ENOTSUPP;
+}
+
+/* mpp[52:57] has gpio pins capable of in and out */
+static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
+                                bool input)
+{
+        if (pid < 52 || pid > 57)
+                return -ENOTSUPP;
+        return 0;
+}
+
+static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long *config)
+{
+        unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        *config = 0;
+        if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1)
+                *config = 1;
+        else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2)
+                *config = 2;
+        else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3)
+                *config = 3;
+
+        return 0;
+}
+
+static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long config)
+{
+        unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
+        gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
+
+        switch (config) {
+        case 1:
+                gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
+                break;
+        case 2:
+                gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
+                break;
+        case 3:
+                gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
+                break;
+        }
+
+        writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
+        writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+        return 0;
+}
+
+static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
+        MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
+        MPP_REG_CTRL(16, 23),
+        MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
+        MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
+        MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
+        MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
+        MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
+        MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
+        MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
+        MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
+        MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
+};
+
+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+        MPP_MODE(0,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "rts"),
+                MPP_FUNCTION(0x03, "sdio0", "cd"),
+                MPP_FUNCTION(0x0f, "lcd0", "pwm"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(1,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "cts"),
+                MPP_FUNCTION(0x03, "sdio0", "wp"),
+                MPP_FUNCTION(0x0f, "lcd1", "pwm"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(2,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "sata", "prsnt"),
+                MPP_FUNCTION(0x02, "uart2", "txd"),
+                MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+                MPP_FUNCTION(0x04, "uart1", "rts"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(3,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "sata", "act"),
+                MPP_FUNCTION(0x02, "uart2", "rxd"),
+                MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+                MPP_FUNCTION(0x04, "uart1", "cts"),
+                MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(4,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "rts"),
+                MPP_FUNCTION(0x03, "sdio1", "cd"),
+                MPP_FUNCTION(0x04, "spi1", "miso"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(5,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "cts"),
+                MPP_FUNCTION(0x03, "sdio1", "wp"),
+                MPP_FUNCTION(0x04, "spi1", "cs"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(6,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "txd"),
+                MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+                MPP_FUNCTION(0x04, "spi1", "mosi"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(7,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "rxd"),
+                MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+                MPP_FUNCTION(0x04, "spi1", "sck"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(8,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "watchdog", "rstout"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(9,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x05, "pex1", "clkreq"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(10,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x05, "ssp", "sclk"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(11,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "sata", "prsnt"),
+                MPP_FUNCTION(0x02, "sata-1", "act"),
+                MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+                MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+                MPP_FUNCTION(0x05, "pex0", "clkreq"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(12,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "sata", "act"),
+                MPP_FUNCTION(0x02, "uart2", "rts"),
+                MPP_FUNCTION(0x03, "audio0", "extclk"),
+                MPP_FUNCTION(0x04, "sdio1", "cd"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(13,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "cts"),
+                MPP_FUNCTION(0x03, "audio1", "extclk"),
+                MPP_FUNCTION(0x04, "sdio1", "wp"),
+                MPP_FUNCTION(0x05, "ssp", "extclk"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(14,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "txd"),
+                MPP_FUNCTION(0x04, "sdio1", "buspwr"),
+                MPP_FUNCTION(0x05, "ssp", "rxd"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(15,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "rxd"),
+                MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+                MPP_FUNCTION(0x05, "ssp", "sfrm"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(16,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "rts"),
+                MPP_FUNCTION(0x03, "sdio0", "cd"),
+                MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
+                MPP_FUNCTION(0x05, "ac97", "sdi1")),
+        MPP_MODE(17,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
+                MPP_FUNCTION(0x02, "uart3", "cts"),
+                MPP_FUNCTION(0x03, "sdio0", "wp"),
+                MPP_FUNCTION(0x04, "twsi", "sda"),
+                MPP_FUNCTION(0x05, "ac97", "sdi2")),
+        MPP_MODE(18,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "txd"),
+                MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+                MPP_FUNCTION(0x04, "lcd0", "pwm"),
+                MPP_FUNCTION(0x05, "ac97", "sdi3")),
+        MPP_MODE(19,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "rxd"),
+                MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+                MPP_FUNCTION(0x04, "twsi", "sck")),
+        MPP_MODE(20,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "ac97", "sysclko"),
+                MPP_FUNCTION(0x02, "lcd-spi", "miso"),
+                MPP_FUNCTION(0x03, "sdio1", "cd"),
+                MPP_FUNCTION(0x05, "sdio0", "cd"),
+                MPP_FUNCTION(0x06, "spi1", "miso")),
+        MPP_MODE(21,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "uart1", "rts"),
+                MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
+                MPP_FUNCTION(0x03, "sdio1", "wp"),
+                MPP_FUNCTION(0x04, "ssp", "sfrm"),
+                MPP_FUNCTION(0x05, "sdio0", "wp"),
+                MPP_FUNCTION(0x06, "spi1", "cs")),
+        MPP_MODE(22,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "uart1", "cts"),
+                MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
+                MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+                MPP_FUNCTION(0x04, "ssp", "txd"),
+                MPP_FUNCTION(0x05, "sdio0", "buspwr"),
+                MPP_FUNCTION(0x06, "spi1", "mosi")),
+        MPP_MODE(23,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "lcd-spi", "sck"),
+                MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+                MPP_FUNCTION(0x04, "ssp", "sclk"),
+                MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
+                MPP_FUNCTION(0x06, "spi1", "sck")),
+        MPP_MODE(24,
+                MPP_FUNCTION(0x00, "camera", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(40,
+                MPP_FUNCTION(0x00, "sdio0", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(46,
+                MPP_FUNCTION(0x00, "sdio1", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(52,
+                MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
+                MPP_FUNCTION(0x02, "i2s1", NULL),
+                MPP_FUNCTION(0x08, "spdifo", NULL),
+                MPP_FUNCTION(0x0a, "gpio", NULL),
+                MPP_FUNCTION(0x0b, "twsi", NULL),
+                MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
+                MPP_FUNCTION(0x0e, "ssp", NULL),
+                MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
+        MPP_MODE(58,
+                MPP_FUNCTION(0x00, "spi0", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(62,
+                MPP_FUNCTION(0x00, "uart1", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(64,
+                MPP_FUNCTION(0x00, "nand", NULL),
+                MPP_FUNCTION(0x01, "gpo", NULL)),
+        MPP_MODE(72,
+                MPP_FUNCTION(0x00, "i2s", NULL),
+                MPP_FUNCTION(0x01, "ac97", NULL)),
+        MPP_MODE(73,
+                MPP_FUNCTION(0x00, "twsi-none", NULL),
+                MPP_FUNCTION(0x01, "twsi-opt1", NULL),
+                MPP_FUNCTION(0x02, "twsi-opt2", NULL),
+                MPP_FUNCTION(0x03, "twsi-opt3", NULL)),
+};
+
+static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,  0,  0, 32),
+        MPP_GPIO_RANGE(1, 32, 32, 32),
+        MPP_GPIO_RANGE(2, 64, 64,  8),
+};
+
+static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
+        .controls = dove_mpp_controls,
+        .ncontrols = ARRAY_SIZE(dove_mpp_controls),
+        .modes = dove_mpp_modes,
+        .nmodes = ARRAY_SIZE(dove_mpp_modes),
+        .gpioranges = dove_mpp_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
+        .variant = 0,
+};
+
+static struct clk *clk;
+
+static struct of_device_id dove_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
+        { }
+};
+
+static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *match =
+                of_match_device(dove_pinctrl_of_match, &pdev->dev);
+        pdev->dev.platform_data = match->data;
+
+        /*
+         * General MPP Configuration Register is part of pdma registers.
+         * grab clk to make sure it is ticking.
+         */
+        clk = devm_clk_get(&pdev->dev, NULL);
+        if (!IS_ERR(clk))
+                clk_prepare_enable(clk);
+
+        return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
+{
+        int ret;
+
+        ret = mvebu_pinctrl_remove(pdev);
+        if (!IS_ERR(clk))
+                clk_disable_unprepare(clk);
+        return ret;
+}
+
+static struct platform_driver dove_pinctrl_driver = {
+        .driver = {
+                .name = "dove-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(dove_pinctrl_of_match),
+        },
+        .probe = dove_pinctrl_probe,
+        .remove = __devexit_p(dove_pinctrl_remove),
+};
+
+module_platform_driver(dove_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>");
+MODULE_DESCRIPTION("Marvell Dove pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-kirkwood.c b/drivers/pinctrl/pinctrl-kirkwood.c
new file mode 100644
index 000000000000..9a74ef674a0e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-kirkwood.c
@@ -0,0 +1,472 @@
+/*
+ * Marvell Kirkwood pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define V(f6180, f6190, f6192, f6281, f6282)            \
+        ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) |   \
+         (f6281 << 3) | (f6282 << 4))
+
+enum kirkwood_variant {
+        VARIANT_MV88F6180 = V(1, 0, 0, 0, 0),
+        VARIANT_MV88F6190 = V(0, 1, 0, 0, 0),
+        VARIANT_MV88F6192 = V(0, 0, 1, 0, 0),
+        VARIANT_MV88F6281 = V(0, 0, 0, 1, 0),
+        VARIANT_MV88F6282 = V(0, 0, 0, 0, 1),
+};
+
+static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
+        MPP_MODE(0,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io2",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1))),
+        MPP_MODE(1,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io3",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "mosi",     V(1, 1, 1, 1, 1))),
+        MPP_MODE(2,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io4",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(3,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io5",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1))),
+        MPP_MODE(4,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io6",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0))),
+        MPP_MODE(5,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io7",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(6,
+                MPP_VAR_FUNCTION(0x0, "sysrst", "out",   V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "spi", "mosi",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+        MPP_MODE(7,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "pex", "rsto",     V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(8,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "twsi0", "sda",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "rts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr",  V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xc, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(9,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "twsi0", "sck",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "cts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xc, "ptp", "evreq",    V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(10,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0X3, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xc, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+        MPP_MODE(11,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq",  V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xc, "ptp-2", "trig",   V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1))),
+        MPP_MODE(12,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 0, 1)),
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "clk",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xb, "spi", "mosi",     V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(13,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "cmd",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xa, "audio", "rmclk",  V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(14,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "d0",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xb, "audio-1", "sdi",  V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(15,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "d1",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "sata0", "act",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "spi", "cs",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(16,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "d2",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "sata1", "act",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "extclk",   V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(17,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "d3",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xa, "sata1", "act",    V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(18,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io0",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "pex", "clkreq",   V(0, 0, 0, 0, 1))),
+        MPP_MODE(19,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io1",     V(1, 1, 1, 1, 1))),
+        MPP_MODE(20,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txd0",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d0",       V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(1, 0, 0, 0, 0))),
+        MPP_MODE(21,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txd1",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d1",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(22,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txd2",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d2",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(23,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txd3",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d3",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(24,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxd0",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d4",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(25,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxd1",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d5",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(26,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxd2",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d6",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(27,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxd3",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d7",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(28,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "col",      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d8",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(29,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txclk",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d9",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(30,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxctl",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d10",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(31,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxclk",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d11",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(32,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txclko",   V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d12",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(33,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txctl",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d13",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(34,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txen",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d14",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(35,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxerr",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d15",      V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(0, 1, 1, 1, 1))),
+        MPP_MODE(36,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(37,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(38,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d18",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(39,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d19",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(40,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d20",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(41,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d21",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(42,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d22",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(43,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d23",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(44,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "clk",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(45,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "e",        V(0, 0, 0, 0, 1))),
+        MPP_MODE(46,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(47,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(48,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d16",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(49,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 0)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "ptp", "clk",      V(0, 0, 0, 1, 0)),
+                MPP_VAR_FUNCTION(0xa, "pex", "clkreq",   V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d17",      V(0, 0, 0, 0, 1))),
+};
+
+static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
+        MPP_REG_CTRL(0, 29),
+};
+
+static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0, 0, 0, 30),
+};
+
+static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
+        MPP_REG_CTRL(0, 35),
+};
+
+static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,  0,  0, 32),
+        MPP_GPIO_RANGE(1, 32, 32,  4),
+};
+
+static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
+        MPP_REG_CTRL(0, 49),
+};
+
+static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,  0,  0, 32),
+        MPP_GPIO_RANGE(1, 32, 32, 18),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6180_info = {
+        .variant = VARIANT_MV88F6180,
+        .controls = mv88f6180_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f6180_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6190_info = {
+        .variant = VARIANT_MV88F6190,
+        .controls = mv88f619x_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f619x_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6192_info = {
+        .variant = VARIANT_MV88F6192,
+        .controls = mv88f619x_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f619x_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6281_info = {
+        .variant = VARIANT_MV88F6281,
+        .controls = mv88f628x_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f628x_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6282_info = {
+        .variant = VARIANT_MV88F6282,
+        .controls = mv88f628x_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f628x_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
+};
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info },
+        { .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info },
+        { .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info },
+        { .compatible = "marvell,88f6281-pinctrl", .data = &mv88f6281_info },
+        { .compatible = "marvell,88f6282-pinctrl", .data = &mv88f6282_info },
+        { }
+};
+
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *match =
+                of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+        pdev->dev.platform_data = match->data;
+        return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit kirkwood_pinctrl_remove(struct platform_device *pdev)
+{
+        return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver kirkwood_pinctrl_driver = {
+        .driver = {
+                .name = "kirkwood-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(kirkwood_pinctrl_of_match),
+        },
+        .probe = kirkwood_pinctrl_probe,
+        .remove = __devexit_p(kirkwood_pinctrl_remove),
+};
+
+module_platform_driver(kirkwood_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>");
+MODULE_DESCRIPTION("Marvell Kirkwood pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-mvebu.c b/drivers/pinctrl/pinctrl-mvebu.c
new file mode 100644
index 000000000000..8e6266c6249a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.c
@@ -0,0 +1,754 @@
+/*
+ * Marvell MVEBU pinctrl core driver
+ *
+ * Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *          Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "core.h"
+#include "pinctrl-mvebu.h"
+
+#define MPPS_PER_REG    8
+#define MPP_BITS        4
+#define MPP_MASK        0xf
+
+struct mvebu_pinctrl_function {
+        const char *name;
+        const char **groups;
+        unsigned num_groups;
+};
+
+struct mvebu_pinctrl_group {
+        const char *name;
+        struct mvebu_mpp_ctrl *ctrl;
+        struct mvebu_mpp_ctrl_setting *settings;
+        unsigned num_settings;
+        unsigned gid;
+        unsigned *pins;
+        unsigned npins;
+};
+
+struct mvebu_pinctrl {
+        struct device *dev;
+        struct pinctrl_dev *pctldev;
+        struct pinctrl_desc desc;
+        void __iomem *base;
+        struct mvebu_pinctrl_group *groups;
+        unsigned num_groups;
+        struct mvebu_pinctrl_function *functions;
+        unsigned num_functions;
+        u8 variant;
+};
+
+static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
+        struct mvebu_pinctrl *pctl, unsigned pid)
+{
+        unsigned n;
+        for (n = 0; n < pctl->num_groups; n++) {
+                if (pid >= pctl->groups[n].pins[0] &&
+                    pid < pctl->groups[n].pins[0] +
+                        pctl->groups[n].npins)
+                        return &pctl->groups[n];
+        }
+        return NULL;
+}
+
+static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
+        struct mvebu_pinctrl *pctl, const char *name)
+{
+        unsigned n;
+        for (n = 0; n < pctl->num_groups; n++) {
+                if (strcmp(name, pctl->groups[n].name) == 0)
+                        return &pctl->groups[n];
+        }
+        return NULL;
+}
+
+static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
+        struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+        unsigned long config)
+{
+        unsigned n;
+        for (n = 0; n < grp->num_settings; n++) {
+                if (config == grp->settings[n].val) {
+                        if (!pctl->variant || (pctl->variant &
+                                               grp->settings[n].variant))
+                                return &grp->settings[n];
+                }
+        }
+        return NULL;
+}
+
+static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
+        struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+        const char *name)
+{
+        unsigned n;
+        for (n = 0; n < grp->num_settings; n++) {
+                if (strcmp(name, grp->settings[n].name) == 0) {
+                        if (!pctl->variant || (pctl->variant &
+                                               grp->settings[n].variant))
+                                return &grp->settings[n];
+                }
+        }
+        return NULL;
+}
+
+static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
+        struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
+{
+        unsigned n;
+        for (n = 0; n < grp->num_settings; n++) {
+                if (grp->settings[n].flags &
+                        (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+                        if (!pctl->variant || (pctl->variant &
+                                                grp->settings[n].variant))
+                                return &grp->settings[n];
+                }
+        }
+        return NULL;
+}
+
+static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
+        struct mvebu_pinctrl *pctl, const char *name)
+{
+        unsigned n;
+        for (n = 0; n < pctl->num_functions; n++) {
+                if (strcmp(name, pctl->functions[n].name) == 0)
+                        return &pctl->functions[n];
+        }
+        return NULL;
+}
+
+/*
+ * Common mpp pin configuration registers on MVEBU are
+ * registers of eight 4-bit values for each mpp setting.
+ * Register offset and bit mask are calculated accordingly below.
+ */
+static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
+                                struct mvebu_pinctrl_group *grp,
+                                unsigned long *config)
+{
+        unsigned pin = grp->gid;
+        unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
+        unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
+
+        *config = readl(pctl->base + off);
+        *config >>= shift;
+        *config &= MPP_MASK;
+
+        return 0;
+}
+
+static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
+                                struct mvebu_pinctrl_group *grp,
+                                unsigned long config)
+{
+        unsigned pin = grp->gid;
+        unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
+        unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
+        unsigned long reg;
+
+        reg = readl(pctl->base + off);
+        reg &= ~(MPP_MASK << shift);
+        reg |= (config << shift);
+        writel(reg, pctl->base + off);
+
+        return 0;
+}
+
+static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
+                                unsigned gid, unsigned long *config)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+        if (!grp->ctrl)
+                return -EINVAL;
+
+        if (grp->ctrl->mpp_get)
+                return grp->ctrl->mpp_get(grp->ctrl, config);
+
+        return mvebu_common_mpp_get(pctl, grp, config);
+}
+
+static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
+                                unsigned gid, unsigned long config)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+        if (!grp->ctrl)
+                return -EINVAL;
+
+        if (grp->ctrl->mpp_set)
+                return grp->ctrl->mpp_set(grp->ctrl, config);
+
+        return mvebu_common_mpp_set(pctl, grp, config);
+}
+
+static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+                                        struct seq_file *s, unsigned gid)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+        struct mvebu_mpp_ctrl_setting *curr;
+        unsigned long config;
+        unsigned n;
+
+        if (mvebu_pinconf_group_get(pctldev, gid, &config))
+                return;
+
+        curr = mvebu_pinctrl_find_setting_by_val(pctl, grp, config);
+
+        if (curr) {
+                seq_printf(s, "current: %s", curr->name);
+                if (curr->subname)
+                        seq_printf(s, "(%s)", curr->subname);
+                if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+                        seq_printf(s, "(");
+                        if (curr->flags & MVEBU_SETTING_GPI)
+                                seq_printf(s, "i");
+                        if (curr->flags & MVEBU_SETTING_GPO)
+                                seq_printf(s, "o");
+                        seq_printf(s, ")");
+                }
+        } else
+                seq_printf(s, "current: UNKNOWN");
+
+        if (grp->num_settings > 1) {
+                seq_printf(s, ", available = [");
+                for (n = 0; n < grp->num_settings; n++) {
+                        if (curr == &grp->settings[n])
+                                continue;
+
+                        /* skip unsupported settings for this variant */
+                        if (pctl->variant &&
+                            !(pctl->variant & grp->settings[n].variant))
+                                continue;
+
+                        seq_printf(s, " %s", grp->settings[n].name);
+                        if (grp->settings[n].subname)
+                                seq_printf(s, "(%s)", grp->settings[n].subname);
+                        if (grp->settings[n].flags &
+                                (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+                                seq_printf(s, "(");
+                                if (grp->settings[n].flags & MVEBU_SETTING_GPI)
+                                        seq_printf(s, "i");
+                                if (grp->settings[n].flags & MVEBU_SETTING_GPO)
+                                        seq_printf(s, "o");
+                                seq_printf(s, ")");
+                        }
+                }
+                seq_printf(s, " ]");
+        }
+        return;
+}
+
+static struct pinconf_ops mvebu_pinconf_ops = {
+        .pin_config_group_get = mvebu_pinconf_group_get,
+        .pin_config_group_set = mvebu_pinconf_group_set,
+        .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
+};
+
+static int mvebu_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->num_functions;
+}
+
+static const char *mvebu_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+                                        unsigned fid)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->functions[fid].name;
+}
+
+static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
+                                const char * const **groups,
+                                unsigned * const num_groups)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        *groups = pctl->functions[fid].groups;
+        *num_groups = pctl->functions[fid].num_groups;
+        return 0;
+}
+
+static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
+                        unsigned gid)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_function *func = &pctl->functions[fid];
+        struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+        struct mvebu_mpp_ctrl_setting *setting;
+        int ret;
+
+        setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
+                                                     func->name);
+        if (!setting) {
+                dev_err(pctl->dev,
+                        "unable to find setting %s in group %s\n",
+                        func->name, func->groups[gid]);
+                return -EINVAL;
+        }
+
+        ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+        if (ret) {
+                dev_err(pctl->dev, "cannot set group %s to %s\n",
+                        func->groups[gid], func->name);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
+                        struct pinctrl_gpio_range *range, unsigned offset)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp;
+        struct mvebu_mpp_ctrl_setting *setting;
+
+        grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+        if (!grp)
+                return -EINVAL;
+
+        if (grp->ctrl->mpp_gpio_req)
+                return grp->ctrl->mpp_gpio_req(grp->ctrl, offset);
+
+        setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+        if (!setting)
+                return -ENOTSUPP;
+
+        return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+}
+
+static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+           struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp;
+        struct mvebu_mpp_ctrl_setting *setting;
+
+        grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+        if (!grp)
+                return -EINVAL;
+
+        if (grp->ctrl->mpp_gpio_dir)
+                return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input);
+
+        setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+        if (!setting)
+                return -ENOTSUPP;
+
+        if ((input && (setting->flags & MVEBU_SETTING_GPI)) ||
+            (!input && (setting->flags & MVEBU_SETTING_GPO)))
+                return 0;
+
+        return -ENOTSUPP;
+}
+
+static struct pinmux_ops mvebu_pinmux_ops = {
+        .get_functions_count = mvebu_pinmux_get_funcs_count,
+        .get_function_name = mvebu_pinmux_get_func_name,
+        .get_function_groups = mvebu_pinmux_get_groups,
+        .gpio_request_enable = mvebu_pinmux_gpio_request_enable,
+        .gpio_set_direction = mvebu_pinmux_gpio_set_direction,
+        .enable = mvebu_pinmux_enable,
+};
+
+static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        return pctl->num_groups;
+}
+
+static const char *mvebu_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+                                                unsigned gid)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        return pctl->groups[gid].name;
+}
+
+static int mvebu_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+                                        unsigned gid, const unsigned **pins,
+                                        unsigned *num_pins)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        *pins = pctl->groups[gid].pins;
+        *num_pins = pctl->groups[gid].npins;
+        return 0;
+}
+
+static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                        struct device_node *np,
+                                        struct pinctrl_map **map,
+                                        unsigned *num_maps)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct property *prop;
+        const char *function;
+        const char *group;
+        int ret, nmaps, n;
+
+        *map = NULL;
+        *num_maps = 0;
+
+        ret = of_property_read_string(np, "marvell,function", &function);
+        if (ret) {
+                dev_err(pctl->dev,
+                        "missing marvell,function in node %s\n", np->name);
+                return 0;
+        }
+
+        nmaps = of_property_count_strings(np, "marvell,pins");
+        if (nmaps < 0) {
+                dev_err(pctl->dev,
+                        "missing marvell,pins in node %s\n", np->name);
+                return 0;
+        }
+
+        *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
+        if (map == NULL) {
+                dev_err(pctl->dev,
+                        "cannot allocate pinctrl_map memory for %s\n",
+                        np->name);
+                return -ENOMEM;
+        }
+
+        n = 0;
+        of_property_for_each_string(np, "marvell,pins", prop, group) {
+                struct mvebu_pinctrl_group *grp =
+                        mvebu_pinctrl_find_group_by_name(pctl, group);
+
+                if (!grp) {
+                        dev_err(pctl->dev, "unknown pin %s", group);
+                        continue;
+                }
+
+                if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
+                        dev_err(pctl->dev, "unsupported function %s on pin %s",
+                                function, group);
+                        continue;
+                }
+
+                (*map)[n].type = PIN_MAP_TYPE_MUX_GROUP;
+                (*map)[n].data.mux.group = group;
+                (*map)[n].data.mux.function = function;
+                n++;
+        }
+
+        *num_maps = nmaps;
+
+        return 0;
+}
+
+static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                                struct pinctrl_map *map, unsigned num_maps)
+{
+        kfree(map);
+}
+
+static struct pinctrl_ops mvebu_pinctrl_ops = {
+        .get_groups_count = mvebu_pinctrl_get_groups_count,
+        .get_group_name = mvebu_pinctrl_get_group_name,
+        .get_group_pins = mvebu_pinctrl_get_group_pins,
+        .dt_node_to_map = mvebu_pinctrl_dt_node_to_map,
+        .dt_free_map = mvebu_pinctrl_dt_free_map,
+};
+
+static int __devinit _add_function(struct mvebu_pinctrl_function *funcs,
+                                   const char *name)
+{
+        while (funcs->num_groups) {
+                /* function already there */
+                if (strcmp(funcs->name, name) == 0) {
+                        funcs->num_groups++;
+                        return -EEXIST;
+                }
+                funcs++;
+        }
+        funcs->name = name;
+        funcs->num_groups = 1;
+        return 0;
+}
+
+static int __devinit mvebu_pinctrl_build_functions(struct platform_device *pdev,
+                                                   struct mvebu_pinctrl *pctl)
+{
+        struct mvebu_pinctrl_function *funcs;
+        int num = 0;
+        int n, s;
+
+        /* we allocate functions for number of pins and hope
+         * there are less unique functions than pins available */
+        funcs = devm_kzalloc(&pdev->dev, pctl->desc.npins *
+                             sizeof(struct mvebu_pinctrl_function), GFP_KERNEL);
+        if (!funcs)
+                return -ENOMEM;
+
+        for (n = 0; n < pctl->num_groups; n++) {
+                struct mvebu_pinctrl_group *grp = &pctl->groups[n];
+                for (s = 0; s < grp->num_settings; s++) {
+                        /* skip unsupported settings on this variant */
+                        if (pctl->variant &&
+                            !(pctl->variant & grp->settings[s].variant))
+                                continue;
+
+                        /* check for unique functions and count groups */
+                        if (_add_function(funcs, grp->settings[s].name))
+                                continue;
+
+                        num++;
+                }
+        }
+
+        /* with the number of unique functions and it's groups known,
+           reallocate functions and assign group names */
+        funcs = krealloc(funcs, num * sizeof(struct mvebu_pinctrl_function),
+                         GFP_KERNEL);
+        if (!funcs)
+                return -ENOMEM;
+
+        pctl->num_functions = num;
+        pctl->functions = funcs;
+
+        for (n = 0; n < pctl->num_groups; n++) {
+                struct mvebu_pinctrl_group *grp = &pctl->groups[n];
+                for (s = 0; s < grp->num_settings; s++) {
+                        struct mvebu_pinctrl_function *f;
+                        const char **groups;
+
+                        /* skip unsupported settings on this variant */
+                        if (pctl->variant &&
+                            !(pctl->variant & grp->settings[s].variant))
+                                continue;
+
+                        f = mvebu_pinctrl_find_function_by_name(pctl,
+                                                        grp->settings[s].name);
+
+                        /* allocate group name array if not done already */
+                        if (!f->groups) {
+                                f->groups = devm_kzalloc(&pdev->dev,
+                                                 f->num_groups * sizeof(char *),
+                                                 GFP_KERNEL);
+                                if (!f->groups)
+                                        return -ENOMEM;
+                        }
+
+                        /* find next free group name and assign current name */
+                        groups = f->groups;
+                        while (*groups)
+                                groups++;
+                        *groups = grp->name;
+                }
+        }
+
+        return 0;
+}
+
+int __devinit mvebu_pinctrl_probe(struct platform_device *pdev)
+{
+        struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
+        struct device_node *np = pdev->dev.of_node;
+        struct mvebu_pinctrl *pctl;
+        void __iomem *base;
+        struct pinctrl_pin_desc *pdesc;
+        unsigned gid, n, k;
+        int ret;
+
+        if (!soc || !soc->controls || !soc->modes) {
+                dev_err(&pdev->dev, "wrong pinctrl soc info\n");
+                return -EINVAL;
+        }
+
+        base = of_iomap(np, 0);
+        if (!base) {
+                dev_err(&pdev->dev, "unable to get base address\n");
+                return -ENODEV;
+        }
+
+        pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
+                        GFP_KERNEL);
+        if (!pctl) {
+                dev_err(&pdev->dev, "unable to alloc driver\n");
+                return -ENOMEM;
+        }
+
+        pctl->desc.name = dev_name(&pdev->dev);
+        pctl->desc.owner = THIS_MODULE;
+        pctl->desc.pctlops = &mvebu_pinctrl_ops;
+        pctl->desc.pmxops = &mvebu_pinmux_ops;
+        pctl->desc.confops = &mvebu_pinconf_ops;
+        pctl->variant = soc->variant;
+        pctl->base = base;
+        pctl->dev = &pdev->dev;
+        platform_set_drvdata(pdev, pctl);
+
+        /* count controls and create names for mvebu generic
+           register controls; also does sanity checks */
+        pctl->num_groups = 0;
+        pctl->desc.npins = 0;
+        for (n = 0; n < soc->ncontrols; n++) {
+                struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+                char *names;
+
+                pctl->desc.npins += ctrl->npins;
+                /* initial control pins */
+                for (k = 0; k < ctrl->npins; k++)
+                        ctrl->pins[k] = ctrl->pid + k;
+
+                /* special soc specific control */
+                if (ctrl->mpp_get || ctrl->mpp_set) {
+                        if (!ctrl->name || !ctrl->mpp_set || !ctrl->mpp_set) {
+                                dev_err(&pdev->dev, "wrong soc control info\n");
+                                return -EINVAL;
+                        }
+                        pctl->num_groups += 1;
+                        continue;
+                }
+
+                /* generic mvebu register control */
+                names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
+                if (!names) {
+                        dev_err(&pdev->dev, "failed to alloc mpp names\n");
+                        return -ENOMEM;
+                }
+                for (k = 0; k < ctrl->npins; k++)
+                        sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
+                ctrl->name = names;
+                pctl->num_groups += ctrl->npins;
+        }
+
+        pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
+                             sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
+        if (!pdesc) {
+                dev_err(&pdev->dev, "failed to alloc pinctrl pins\n");
+                return -ENOMEM;
+        }
+
+        for (n = 0; n < pctl->desc.npins; n++)
+                pdesc[n].number = n;
+        pctl->desc.pins = pdesc;
+
+        pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups *
+                             sizeof(struct mvebu_pinctrl_group), GFP_KERNEL);
+        if (!pctl->groups) {
+                dev_err(&pdev->dev, "failed to alloc pinctrl groups\n");
+                return -ENOMEM;
+        }
+
+        /* assign mpp controls to groups */
+        gid = 0;
+        for (n = 0; n < soc->ncontrols; n++) {
+                struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+                pctl->groups[gid].gid = gid;
+                pctl->groups[gid].ctrl = ctrl;
+                pctl->groups[gid].name = ctrl->name;
+                pctl->groups[gid].pins = ctrl->pins;
+                pctl->groups[gid].npins = ctrl->npins;
+
+                /* generic mvebu register control maps to a number of groups */
+                if (!ctrl->mpp_get && !ctrl->mpp_set) {
+                        pctl->groups[gid].npins = 1;
+
+                        for (k = 1; k < ctrl->npins; k++) {
+                                gid++;
+                                pctl->groups[gid].gid = gid;
+                                pctl->groups[gid].ctrl = ctrl;
+                                pctl->groups[gid].name = &ctrl->name[8*k];
+                                pctl->groups[gid].pins = &ctrl->pins[k];
+                                pctl->groups[gid].npins = 1;
+                        }
+                }
+                gid++;
+        }
+
+        /* assign mpp modes to groups */
+        for (n = 0; n < soc->nmodes; n++) {
+                struct mvebu_mpp_mode *mode = &soc->modes[n];
+                struct mvebu_pinctrl_group *grp =
+                        mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
+                unsigned num_settings;
+
+                if (!grp) {
+                        dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
+                                mode->pid);
+                        continue;
+                }
+
+                for (num_settings = 0; ;) {
+                        struct mvebu_mpp_ctrl_setting *set =
+                                &mode->settings[num_settings];
+
+                        if (!set->name)
+                                break;
+                        num_settings++;
+
+                        /* skip unsupported settings for this variant */
+                        if (pctl->variant && !(pctl->variant & set->variant))
+                                continue;
+
+                        /* find gpio/gpo/gpi settings */
+                        if (strcmp(set->name, "gpio") == 0)
+                                set->flags = MVEBU_SETTING_GPI |
+                                        MVEBU_SETTING_GPO;
+                        else if (strcmp(set->name, "gpo") == 0)
+                                set->flags = MVEBU_SETTING_GPO;
+                        else if (strcmp(set->name, "gpi") == 0)
+                                set->flags = MVEBU_SETTING_GPI;
+                }
+
+                grp->settings = mode->settings;
+                grp->num_settings = num_settings;
+        }
+
+        ret = mvebu_pinctrl_build_functions(pdev, pctl);
+        if (ret) {
+                dev_err(&pdev->dev, "unable to build functions\n");
+                return ret;
+        }
+
+        pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
+        if (!pctl->pctldev) {
+                dev_err(&pdev->dev, "unable to register pinctrl driver\n");
+                return -EINVAL;
+        }
+
+        dev_info(&pdev->dev, "registered pinctrl driver\n");
+
+        /* register gpio ranges */
+        for (n = 0; n < soc->ngpioranges; n++)
+                pinctrl_add_gpio_range(pctl->pctldev, &soc->gpioranges[n]);
+
+        return 0;
+}
+
+int __devexit mvebu_pinctrl_remove(struct platform_device *pdev)
+{
+        struct mvebu_pinctrl *pctl = platform_get_drvdata(pdev);
+        pinctrl_unregister(pctl->pctldev);
+        return 0;
+}
diff --git a/drivers/pinctrl/pinctrl-mvebu.h b/drivers/pinctrl/pinctrl-mvebu.h
new file mode 100644
index 000000000000..90bd3beee860
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.h
@@ -0,0 +1,192 @@
+/*
+ * Marvell MVEBU pinctrl driver
+ *
+ * Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *          Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PINCTRL_MVEBU_H__
+#define __PINCTRL_MVEBU_H__
+
+/**
+ * struct mvebu_mpp_ctrl - describe a mpp control
+ * @name: name of the control group
+ * @pid: first pin id handled by this control
+ * @npins: number of pins controlled by this control
+ * @mpp_get: (optional) special function to get mpp setting
+ * @mpp_set: (optional) special function to set mpp setting
+ * @mpp_gpio_req: (optional) special function to request gpio
+ * @mpp_gpio_dir: (optional) special function to set gpio direction
+ *
+ * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
+ * internal function, inside the SoC. Each muxable unit can be switched
+ * between two or more different settings, e.g. assign mpp pin 13 to
+ * uart1 or sata.
+ *
+ * If optional mpp_get/_set functions are set these are used to get/set
+ * a specific mode. Otherwise it is assumed that the mpp control is based
+ * on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir
+ * functions can be used to allow pin settings with varying gpio pins.
+ */
+struct mvebu_mpp_ctrl {
+        const char *name;
+        u8 pid;
+        u8 npins;
+        unsigned *pins;
+        int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
+        int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
+        int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
+        int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
+};
+
+/**
+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value
+ * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
+ * @subname: (optional) additional ctrl setting name, e.g. rts, cts
+ * @variant: (optional) variant identifier mask
+ * @flags: (private) flags to store gpi/gpo/gpio capabilities
+ *
+ * A ctrl_setting describes a specific internal mux function that a mpp pin
+ * can be switched to. The value (val) will be written in the corresponding
+ * register for common mpp pin configuration registers on MVEBU. SoC specific
+ * mpp_get/_set function may use val to distinguish between different settings.
+ *
+ * The name will be used to switch to this setting in DT description, e.g.
+ * marvell,function = "uart2". subname is only for debugging purposes.
+ *
+ * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
+ * parsed during initialization and stored in flags.
+ *
+ * The variant can be used to combine different revisions of one SoC to a
+ * common pinctrl driver. It is matched (AND) with variant of soc_info to
+ * determine if a setting is available on the current SoC revision.
+ */
+struct mvebu_mpp_ctrl_setting {
+        u8 val;
+        const char *name;
+        const char *subname;
+        u8 variant;
+        u8 flags;
+#define  MVEBU_SETTING_GPO      (1 << 0)
+#define  MVEBU_SETTING_GPI      (1 << 1)
+};
+
+/**
+ * struct mvebu_mpp_mode - link ctrl and settings
+ * @pid: first pin id handled by this mode
+ * @settings: list of settings available for this mode
+ *
+ * A mode connects all available settings with the corresponding mpp_ctrl
+ * given by pid.
+ */
+struct mvebu_mpp_mode {
+        u8 pid;
+        struct mvebu_mpp_ctrl_setting *settings;
+};
+
+/**
+ * struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu
+ * @variant: variant mask of soc_info
+ * @controls: list of available mvebu_mpp_ctrls
+ * @ncontrols: number of available mvebu_mpp_ctrls
+ * @modes: list of available mvebu_mpp_modes
+ * @nmodes: number of available mvebu_mpp_modes
+ * @gpioranges: list of pinctrl_gpio_ranges
+ * @ngpioranges: number of available pinctrl_gpio_ranges
+ *
+ * This struct describes all pinctrl related information for a specific SoC.
+ * If variant is unequal 0 it will be matched (AND) with variant of each
+ * setting and allows to distinguish between different revisions of one SoC.
+ */
+struct mvebu_pinctrl_soc_info {
+        u8 variant;
+        struct mvebu_mpp_ctrl *controls;
+        int ncontrols;
+        struct mvebu_mpp_mode *modes;
+        int nmodes;
+        struct pinctrl_gpio_range *gpioranges;
+        int ngpioranges;
+};
+
+#define MPP_REG_CTRL(_idl, _idh)                                \
+        {                                                       \
+                .name = NULL,                                   \
+                .pid = _idl,                                    \
+                .npins = _idh - _idl + 1,                       \
+                .pins = (unsigned[_idh - _idl + 1]) { },        \
+                .mpp_get = NULL,                                \
+                .mpp_set = NULL,                                \
+                .mpp_gpio_req = NULL,                           \
+                .mpp_gpio_dir = NULL,                           \
+        }
+
+#define MPP_FUNC_CTRL(_idl, _idh, _name, _func)                 \
+        {                                                       \
+                .name = _name,                                  \
+                .pid = _idl,                                    \
+                .npins = _idh - _idl + 1,                       \
+                .pins = (unsigned[_idh - _idl + 1]) { },        \
+                .mpp_get = _func ## _get,                       \
+                .mpp_set = _func ## _set,                       \
+                .mpp_gpio_req = NULL,                           \
+                .mpp_gpio_dir = NULL,                           \
+        }
+
+#define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func)            \
+        {                                                       \
+                .name = _name,                                  \
+                .pid = _idl,                                    \
+                .npins = _idh - _idl + 1,                       \
+                .pins = (unsigned[_idh - _idl + 1]) { },        \
+                .mpp_get = _func ## _get,                       \
+                .mpp_set = _func ## _set,                       \
+                .mpp_gpio_req = _func ## _gpio_req,             \
+                .mpp_gpio_dir = _func ## _gpio_dir,             \
+        }
+
+#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
+        {                                                       \
+                .val = _val,                                    \
+                .name = _name,                                  \
+                .subname = _subname,                            \
+                .variant = _mask,                               \
+                .flags = 0,                                     \
+        }
+
+#if defined(CONFIG_DEBUG_FS)
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)          \
+        _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
+#else
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)          \
+        _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
+#endif
+
+#define MPP_FUNCTION(_val, _name, _subname)                     \
+        MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
+
+#define MPP_MODE(_id, ...)                                      \
+        {                                                       \
+                .pid = _id,                                     \
+                .settings = (struct mvebu_mpp_ctrl_setting[]){  \
+                        __VA_ARGS__, { } },                     \
+        }
+
+#define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins)        \
+        {                                                       \
+                .name = "mvebu-gpio",                           \
+                .id = _id,                                      \
+                .pin_base = _pinbase,                           \
+                .base = _gpiobase,                              \
+                .npins = _npins,                                \
+        }
+
+int mvebu_pinctrl_probe(struct platform_device *pdev);
+int mvebu_pinctrl_remove(struct platform_device *pdev);
+
+#endif
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 7fca6ce5952b..304360cd213e 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -17,6 +17,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
@@ -916,11 +917,66 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
         seq_printf(s, " " DRIVER_NAME);
 }
 
+static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                 struct device_node *np_config,
+                                 struct pinctrl_map **map, unsigned *num_maps)
+{
+        struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
+        struct device_node *np;
+        struct property *prop;
+        const char *function, *group;
+        int ret, index = 0, count = 0;
+
+        /* calculate number of maps required */
+        for_each_child_of_node(np_config, np) {
+                ret = of_property_read_string(np, "sirf,function", &function);
+                if (ret < 0)
+                        return ret;
+
+                ret = of_property_count_strings(np, "sirf,pins");
+                if (ret < 0)
+                        return ret;
+
+                count += ret;
+        }
+
+        if (!count) {
+                dev_err(spmx->dev, "No child nodes passed via DT\n");
+                return -ENODEV;
+        }
+
+        *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
+        if (!*map)
+                return -ENOMEM;
+
+        for_each_child_of_node(np_config, np) {
+                of_property_read_string(np, "sirf,function", &function);
+                of_property_for_each_string(np, "sirf,pins", prop, group) {
+                        (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
+                        (*map)[index].data.mux.group = group;
+                        (*map)[index].data.mux.function = function;
+                        index++;
+                }
+        }
+
+        *num_maps = count;
+
+        return 0;
+}
+
+static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
+                struct pinctrl_map *map, unsigned num_maps)
+{
+        kfree(map);
+}
+
 static struct pinctrl_ops sirfsoc_pctrl_ops = {
         .get_groups_count = sirfsoc_get_groups_count,
         .get_group_name = sirfsoc_get_group_name,
         .get_group_pins = sirfsoc_get_group_pins,
         .pin_dbg_show = sirfsoc_pin_dbg_show,
+        .dt_node_to_map = sirfsoc_dt_node_to_map,
+        .dt_free_map = sirfsoc_dt_free_map,
 };
 
 struct sirfsoc_pmx_func {
@@ -1221,7 +1277,7 @@ out_no_gpio_remap:
 }
 
 static const struct of_device_id pinmux_ids[] __devinitconst = {
-        { .compatible = "sirf,prima2-gpio-pinmux" },
+        { .compatible = "sirf,prima2-pinctrl" },
         {}
 };
 
diff --git a/drivers/regulator/tps6586x-regulator.c b/drivers/regulator/tps6586x-regulator.c
index 19241fc30050..82125269b667 100644
--- a/drivers/regulator/tps6586x-regulator.c
+++ b/drivers/regulator/tps6586x-regulator.c
@@ -162,6 +162,9 @@ static struct regulator_ops tps6586x_regulator_ops = {
         .disable = tps6586x_regulator_disable,
 };
 
+static struct regulator_ops tps6586x_sys_regulator_ops = {
+};
+
 static const unsigned int tps6586x_ldo0_voltages[] = {
         1200000, 1500000, 1800000, 2500000, 2700000, 2850000, 3100000, 3300000,
 };
@@ -230,15 +233,28 @@ static const unsigned int tps6586x_dvm_voltages[] = {
         TPS6586X_REGULATOR_DVM_GOREG(goreg, gobit)                      \
 }
 
+#define TPS6586X_SYS_REGULATOR()                                        \
+{                                                                       \
+        .desc   = {                                                     \
+                .supply_name = "sys",                                   \
+                .name   = "REG-SYS",                                    \
+                .ops    = &tps6586x_sys_regulator_ops,                  \
+                .type   = REGULATOR_VOLTAGE,                            \
+                .id     = TPS6586X_ID_SYS,                              \
+                .owner  = THIS_MODULE,                                  \
+        },                                                              \
+}
+
 static struct tps6586x_regulator tps6586x_regulator[] = {
+        TPS6586X_SYS_REGULATOR(),
         TPS6586X_LDO(LDO_0, "vinldo01", ldo0, SUPPLYV1, 5, 3, ENC, 0, END, 0),
         TPS6586X_LDO(LDO_3, "vinldo23", ldo, SUPPLYV4, 0, 3, ENC, 2, END, 2),
-        TPS6586X_LDO(LDO_5, NULL, ldo, SUPPLYV6, 0, 3, ENE, 6, ENE, 6),
+        TPS6586X_LDO(LDO_5, "REG-SYS", ldo, SUPPLYV6, 0, 3, ENE, 6, ENE, 6),
         TPS6586X_LDO(LDO_6, "vinldo678", ldo, SUPPLYV3, 0, 3, ENC, 4, END, 4),
         TPS6586X_LDO(LDO_7, "vinldo678", ldo, SUPPLYV3, 3, 3, ENC, 5, END, 5),
         TPS6586X_LDO(LDO_8, "vinldo678", ldo, SUPPLYV2, 5, 3, ENC, 6, END, 6),
         TPS6586X_LDO(LDO_9, "vinldo9", ldo, SUPPLYV6, 3, 3, ENE, 7, ENE, 7),
-        TPS6586X_LDO(LDO_RTC, NULL, ldo, SUPPLYV4, 3, 3, V4, 7, V4, 7),
+        TPS6586X_LDO(LDO_RTC, "REG-SYS", ldo, SUPPLYV4, 3, 3, V4, 7, V4, 7),
         TPS6586X_LDO(LDO_1, "vinldo01", dvm, SUPPLYV1, 0, 5, ENC, 1, END, 1),
         TPS6586X_LDO(SM_2, "vin-sm2", sm2, SUPPLYV2, 0, 5, ENC, 7, END, 7),
 
diff --git a/drivers/remoteproc/omap_remoteproc.c b/drivers/remoteproc/omap_remoteproc.c
index a1f7ac1f8cf6..b54504ee61f1 100644
--- a/drivers/remoteproc/omap_remoteproc.c
+++ b/drivers/remoteproc/omap_remoteproc.c
@@ -29,7 +29,7 @@
 #include <linux/remoteproc.h>
 
 #include <plat/mailbox.h>
-#include <plat/remoteproc.h>
+#include <linux/platform_data/remoteproc-omap.h>
 
 #include "omap_remoteproc.h"
 #include "remoteproc_internal.h"
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index 0075c8fd93d8..f771b2ee4b18 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -27,6 +27,8 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 #include <mach/hardware.h>
 
@@ -396,6 +398,14 @@ static int __exit pxa_rtc_remove(struct platform_device *pdev)
         return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id pxa_rtc_dt_ids[] = {
+        { .compatible = "marvell,pxa-rtc" },
+        {}
+};
+MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
+#endif
+
 #ifdef CONFIG_PM
 static int pxa_rtc_suspend(struct device *dev)
 {
@@ -425,6 +435,7 @@ static struct platform_driver pxa_rtc_driver = {
         .remove         = __exit_p(pxa_rtc_remove),
         .driver         = {
                 .name   = "pxa-rtc",
+                .of_match_table = of_match_ptr(pxa_rtc_dt_ids),
 #ifdef CONFIG_PM
                 .pm     = &pxa_rtc_pm_ops,
 #endif
diff --git a/drivers/scsi/arm/eesox.c b/drivers/scsi/arm/eesox.c
index edfd12b48c28..968d08358d20 100644
--- a/drivers/scsi/arm/eesox.c
+++ b/drivers/scsi/arm/eesox.c
@@ -273,7 +273,7 @@ static void eesoxscsi_buffer_out(void *buf, int length, void __iomem *base)
 {
         const void __iomem *reg_fas = base + EESOX_FAS216_OFFSET;
         const void __iomem *reg_dmastat = base + EESOX_DMASTAT;
-        const void __iomem *reg_dmadata = base + EESOX_DMADATA;
+        void __iomem *reg_dmadata = base + EESOX_DMADATA;
 
         do {
                 unsigned int status;
diff --git a/drivers/sh/pfc/gpio.c b/drivers/sh/pfc/gpio.c
index 62bca98474a9..038fa071382a 100644
--- a/drivers/sh/pfc/gpio.c
+++ b/drivers/sh/pfc/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/sh_pfc.h>
 
 struct sh_pfc_chip {
         struct sh_pfc           *pfc;
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5f84b5563c2d..2d198a01a410 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -366,7 +366,7 @@ config SPI_STMP3XXX
 
 config SPI_TEGRA
         tristate "Nvidia Tegra SPI controller"
-        depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA)
+        depends on ARCH_TEGRA && TEGRA20_APB_DMA
         help
           SPI driver for NVidia Tegra SoCs
 
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 9b2901feaf78..3afe2f4f5b8e 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -30,7 +30,7 @@
 #include <linux/spi/spi_bitbang.h>
 #include <linux/slab.h>
 
-#include <mach/spi.h>
+#include <linux/platform_data/spi-davinci.h>
 #include <mach/edma.h>
 
 #define SPI_NO_RESOURCE         ((resource_size_t)-1)
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index f97f1d248800..3a219599612a 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -31,8 +31,8 @@
 #include <linux/scatterlist.h>
 #include <linux/spi/spi.h>
 
-#include <mach/dma.h>
-#include <mach/ep93xx_spi.h>
+#include <linux/platform_data/dma-ep93xx.h>
+#include <linux/platform_data/spi-ep93xx.h>
 
 #define SSPCR0                  0x0000
 #define SSPCR0_MODE_SHIFT       6
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index e834ff8c0188..63e7fc9801cd 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -39,7 +39,7 @@
 #include <linux/of_gpio.h>
 #include <linux/pinctrl/consumer.h>
 
-#include <mach/spi.h>
+#include <linux/platform_data/spi-imx.h>
 
 #define DRIVER_NAME "spi_imx"
 
diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c
index dae8be229c5d..a6eca6ffdabe 100644
--- a/drivers/spi/spi-nuc900.c
+++ b/drivers/spi/spi-nuc900.c
@@ -26,7 +26,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
 
-#include <mach/nuc900_spi.h>
+#include <linux/platform_data/spi-nuc900.h>
 
 /* usi registers offset */
 #define USI_CNT         0x00
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index a3996a1c6345..0a94d9dc9c31 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -52,7 +52,7 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #include <mach/omap7xx.h>       /* OMAP7XX_IO_CONF registers */
 
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index b5d6994c8ba3..d3d62f1e894c 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -41,7 +41,7 @@
 
 #include <linux/spi/spi.h>
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #define OMAP2_MCSPI_MAX_FREQ            48000000
 #define SPI_AUTOSUSPEND_TIMEOUT         2000
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index d1c8441f638c..0e2a02228d5e 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -32,7 +32,7 @@
 #include <linux/of_gpio.h>
 
 #include <mach/dma.h>
-#include <plat/s3c64xx-spi.h>
+#include <linux/platform_data/spi-s3c64xx.h>
 
 #define MAX_SPI_PORTS           3
 
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index ef52c1c6f5c5..488d9b6e9cbe 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -164,23 +164,15 @@ struct spi_tegra_data {
          * for the generic case.
          */
         int                     dma_req_len;
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-        struct tegra_dma_req    rx_dma_req;
-        struct tegra_dma_channel *rx_dma;
-#else
         struct dma_chan         *rx_dma;
         struct dma_slave_config sconfig;
         struct dma_async_tx_descriptor  *rx_dma_desc;
         dma_cookie_t            rx_cookie;
-#endif
         u32                     *rx_bb;
         dma_addr_t              rx_bb_phys;
 };
 
-#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
 static void tegra_spi_rx_dma_complete(void *args);
-#endif
-
 static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
                                             unsigned long reg)
 {
@@ -204,10 +196,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
         val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
         val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1);
         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-        tspi->rx_dma_req.size = tspi->dma_req_len;
-        tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
-#else
         tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma,
                                 tspi->rx_bb_phys, tspi->dma_req_len,
                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
@@ -219,7 +207,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
         tspi->rx_dma_desc->callback_param = tspi;
         tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc);
         dma_async_issue_pending(tspi->rx_dma);
-#endif
 
         val |= SLINK_DMA_EN;
         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
@@ -405,19 +392,12 @@ static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi)
 
         spin_unlock_irqrestore(&tspi->lock, flags);
 }
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
-{
-        struct spi_tegra_data *tspi = req->dev;
-        handle_spi_rx_dma_complete(tspi);
-}
-#else
+
 static void tegra_spi_rx_dma_complete(void *args)
 {
         struct spi_tegra_data *tspi = args;
         handle_spi_rx_dma_complete(tspi);
 }
-#endif
 
 static int spi_tegra_setup(struct spi_device *spi)
 {
@@ -509,9 +489,7 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
         struct spi_tegra_data   *tspi;
         struct resource         *r;
         int ret;
-#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
         dma_cap_mask_t mask;
-#endif
 
         master = spi_alloc_master(&pdev->dev, sizeof *tspi);
         if (master == NULL) {
@@ -563,14 +541,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
 
         INIT_LIST_HEAD(&tspi->queue);
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-        tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
-        if (!tspi->rx_dma) {
-                dev_err(&pdev->dev, "can not allocate rx dma channel\n");
-                ret = -ENODEV;
-                goto err3;
-        }
-#else
         dma_cap_zero(mask);
         dma_cap_set(DMA_SLAVE, mask);
         tspi->rx_dma = dma_request_channel(mask, NULL, NULL);
@@ -580,8 +550,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
                 goto err3;
         }
 
-#endif
-
         tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
                                          &tspi->rx_bb_phys, GFP_KERNEL);
         if (!tspi->rx_bb) {
@@ -590,17 +558,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
                 goto err4;
         }
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-        tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
-        tspi->rx_dma_req.to_memory = 1;
-        tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
-        tspi->rx_dma_req.dest_bus_width = 32;
-        tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
-        tspi->rx_dma_req.source_bus_width = 32;
-        tspi->rx_dma_req.source_wrap = 4;
-        tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
-        tspi->rx_dma_req.dev = tspi;
-#else
         /* Dmaengine Dma slave config */
         tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
         tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO;
@@ -616,7 +573,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
                         ret);
                 goto err4;
         }
-#endif
 
         master->dev.of_node = pdev->dev.of_node;
         ret = spi_register_master(master);
@@ -630,11 +586,7 @@ err5:
         dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
                           tspi->rx_bb, tspi->rx_bb_phys);
 err4:
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-        tegra_dma_free_channel(tspi->rx_dma);
-#else
         dma_release_channel(tspi->rx_dma);
-#endif
 err3:
         clk_put(tspi->clk);
 err2:
@@ -656,12 +608,7 @@ static int __devexit spi_tegra_remove(struct platform_device *pdev)
         tspi = spi_master_get_devdata(master);
 
         spi_unregister_master(master);
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-        tegra_dma_free_channel(tspi->rx_dma);
-#else
         dma_release_channel(tspi->rx_dma);
-#endif
-
         dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
                           tspi->rx_bb, tspi->rx_bb_phys);
 
diff --git a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
index a272e488e5b9..47439c3f7258 100644
--- a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
+++ b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
@@ -5,7 +5,6 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
-#include <mach/gpio.h>
 #include <mach/irqs.h>
 #include "synaptics_i2c_rmi4.h"
 
diff --git a/drivers/staging/tidspbridge/core/dsp-clock.c b/drivers/staging/tidspbridge/core/dsp-clock.c
index c7df34e6b60b..7d056bd1eaad 100644
--- a/drivers/staging/tidspbridge/core/dsp-clock.c
+++ b/drivers/staging/tidspbridge/core/dsp-clock.c
@@ -21,7 +21,7 @@
 /*  ----------------------------------- Host OS */
 #include <dspbridge/host_os.h>
 #include <plat/dmtimer.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 /*  ----------------------------------- DSP/BIOS Bridge */
 #include <dspbridge/dbdefs.h>
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c
index f9609ce2c163..7bf55c40944e 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -16,7 +16,7 @@
  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  */
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 #include <linux/types.h>
 /*  ----------------------------------- Host OS */
diff --git a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
index 16a4aafa86ae..55675b7b9b66 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
@@ -19,7 +19,7 @@
 /*  ----------------------------------- Host OS */
 #include <dspbridge/host_os.h>
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 /*  ----------------------------------- DSP/BIOS Bridge */
 #include <dspbridge/dbdefs.h>
diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c
index 7fda10c36862..f53ed98d18c1 100644
--- a/drivers/staging/tidspbridge/core/tiomap_io.c
+++ b/drivers/staging/tidspbridge/core/tiomap_io.c
@@ -16,7 +16,7 @@
  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  */
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 /*  ----------------------------------- DSP/BIOS Bridge */
 #include <dspbridge/dbdefs.h>
diff --git a/drivers/staging/tidspbridge/rmgr/drv_interface.c b/drivers/staging/tidspbridge/rmgr/drv_interface.c
index 3cac01492063..49c9b662392f 100644
--- a/drivers/staging/tidspbridge/rmgr/drv_interface.c
+++ b/drivers/staging/tidspbridge/rmgr/drv_interface.c
@@ -16,7 +16,7 @@
  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  */
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 #include <linux/types.h>
 #include <linux/platform_device.h>
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 5952b25c288e..2a093a42512f 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -51,7 +51,7 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <mach/imx-uart.h>
+#include <linux/platform_data/serial-imx.h>
 
 /* Register definitions */
 #define URXD0 0x0  /* Receiver Register */
diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
index 7c13639c597e..9bd004f9da89 100644
--- a/drivers/tty/serial/serial_ks8695.c
+++ b/drivers/tty/serial/serial_ks8695.c
@@ -548,8 +548,8 @@ static struct uart_ops ks8695uart_pops = {
 
 static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = {
         {
-                .membase        = (void *) KS8695_UART_VA,
-                .mapbase        = KS8695_UART_VA,
+                .membase        = KS8695_UART_VA,
+                .mapbase        = KS8695_UART_PA,
                 .iotype         = SERIAL_IO_MEM,
                 .irq            = KS8695_IRQ_UART_TX,
                 .uartclk        = KS8695_CLOCK_RATE * 16,
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 7065df6036ca..7de2285d9fa9 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -13,7 +13,6 @@ config USB_ARCH_HAS_OHCI
         default y if PXA3xx
         default y if ARCH_EP93XX
         default y if ARCH_AT91
-        default y if ARCH_PNX4008
         default y if MFD_TC6393XB
         default y if ARCH_W90X900
         default y if ARCH_DAVINCI_DA8XX
diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
index dc5334856afe..a0eb85794fd4 100644
--- a/drivers/usb/gadget/imx_udc.c
+++ b/drivers/usb/gadget/imx_udc.c
@@ -35,7 +35,7 @@
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 
-#include <mach/usb.h>
+#include <linux/platform_data/usb-imx_udc.h>
 #include <mach/hardware.h>
 
 #include "imx_udc.h"
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 644b4305cb99..7a8713cda945 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -2508,7 +2508,7 @@ static int __init pxa_udc_probe(struct platform_device *pdev)
                         IRQF_SHARED, driver_name, udc);
         if (retval != 0) {
                 dev_err(udc->dev, "%s: can't get irq %i, err %d\n",
-                        driver_name, IRQ_USB, retval);
+                        driver_name, udc->irq, retval);
                 goto err_irq;
         }
         retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c
index f2e51f50e528..f006045fc44c 100644
--- a/drivers/usb/gadget/s3c2410_udc.c
+++ b/drivers/usb/gadget/s3c2410_udc.c
@@ -43,7 +43,7 @@
 #include <mach/hardware.h>
 
 #include <plat/regs-udc.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 
 
 #include "s3c2410_udc.h"
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 075d2eca8108..276add2358a1 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -292,7 +292,7 @@ config USB_OHCI_HCD
         depends on USB && USB_ARCH_HAS_OHCI
         select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
         select USB_OTG_UTILS if ARCH_OMAP
-        select USB_ISP1301 if ARCH_LPC32XX || ARCH_PNX4008
+        select USB_ISP1301 if ARCH_LPC32XX
         ---help---
           The Open Host Controller Interface (OHCI) is a standard for accessing
           USB 1.1 host controller hardware.  It does more in hardware than Intel's
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 34201372c85f..a6e2ea4ef8fd 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -25,7 +25,7 @@
 #include <linux/slab.h>
 
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 
 #include <asm/mach-types.h>
 
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index 8892d3642cef..8e7eca62f169 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/mbus.h>
 #include <linux/clk.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 
 #define rdl(off)        __raw_readl(hcd->regs + (off))
 #define wrl(off, val)   __raw_writel((val), hcd->regs + (off))
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 9d8f1dd57cb3..dfb14c7a61e2 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -16,7 +16,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/of_gpio.h>
-#include <plat/ehci.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/usb-phy.h>
 
 #define EHCI_INSNREG00(base)                    (base + 0x90)
diff --git a/drivers/usb/host/imx21-hcd.h b/drivers/usb/host/imx21-hcd.h
index 87b29fd971b4..c005770a73e9 100644
--- a/drivers/usb/host/imx21-hcd.h
+++ b/drivers/usb/host/imx21-hcd.h
@@ -24,7 +24,7 @@
 #ifndef __LINUX_IMX21_HCD_H__
 #define __LINUX_IMX21_HCD_H__
 
-#include <mach/mx21-usbhost.h>
+#include <linux/platform_data/usb-mx2.h>
 
 #define NUM_ISO_ETDS    2
 #define USB_NUM_ETD     32
diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
index 269b1e0f7691..0b815a856811 100644
--- a/drivers/usb/host/ohci-da8xx.c
+++ b/drivers/usb/host/ohci-da8xx.c
@@ -17,7 +17,7 @@
 #include <linux/clk.h>
 
 #include <mach/da8xx.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
 
 #ifndef CONFIG_ARCH_DAVINCI_DA8XX
 #error "This file is DA8xx bus glue.  Define CONFIG_ARCH_DAVINCI_DA8XX."
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index fc3091bd2379..20a50081f922 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -14,7 +14,7 @@
 #include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-exynos.h>
 #include <plat/usb-phy.h>
 
 struct exynos_ohci_hcd {
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 2b1e8d84c873..6780010e9c3c 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1049,7 +1049,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER         ohci_hcd_at91_driver
 #endif
 
-#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)
+#ifdef CONFIG_ARCH_LPC32XX
 #include "ohci-nxp.c"
 #define PLATFORM_DRIVER         usb_hcd_nxp_driver
 #endif
diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
index a446386bf779..119966603d8d 100644
--- a/drivers/usb/host/ohci-nxp.c
+++ b/drivers/usb/host/ohci-nxp.c
@@ -2,7 +2,6 @@
  * driver for NXP USB Host devices
  *
  * Currently supported OHCI host devices:
- * - Philips PNX4008
  * - NXP LPC32xx
  *
  * Authors: Dmitry Chigirev <source@mvista.com>
@@ -66,38 +65,6 @@ static struct clk *usb_pll_clk;
 static struct clk *usb_dev_clk;
 static struct clk *usb_otg_clk;
 
-static void isp1301_configure_pnx4008(void)
-{
-        /* PNX4008 only supports DAT_SE0 USB mode */
-        /* PNX4008 R2A requires setting the MAX603 to output 3.6V */
-        /* Power up externel charge-pump */
-
-        i2c_smbus_write_byte_data(isp1301_i2c_client,
-                ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG);
-        i2c_smbus_write_byte_data(isp1301_i2c_client,
-                ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
-                ~(MC1_DAT_SE0 | MC1_SPEED_REG));
-        i2c_smbus_write_byte_data(isp1301_i2c_client,
-                ISP1301_I2C_MODE_CONTROL_2,
-                MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
-        i2c_smbus_write_byte_data(isp1301_i2c_client,
-                ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
-                ~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
-        i2c_smbus_write_byte_data(isp1301_i2c_client,
-                ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
-        i2c_smbus_write_byte_data(isp1301_i2c_client,
-                ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
-                ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
-        i2c_smbus_write_byte_data(isp1301_i2c_client,
-                ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF);
-        i2c_smbus_write_byte_data(isp1301_i2c_client,
-                ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
-                0xFF);
-        i2c_smbus_write_byte_data(isp1301_i2c_client,
-                ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
-                0xFF);
-}
-
 static void isp1301_configure_lpc32xx(void)
 {
         /* LPC32XX only supports DAT_SE0 USB mode */
@@ -149,10 +116,7 @@ static void isp1301_configure_lpc32xx(void)
 
 static void isp1301_configure(void)
 {
-        if (machine_is_pnx4008())
-                isp1301_configure_pnx4008();
-        else
-                isp1301_configure_lpc32xx();
+        isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -241,47 +205,6 @@ static const struct hc_driver ohci_nxp_hc_driver = {
         .start_port_reset = ohci_start_port_reset,
 };
 
-static void nxp_set_usb_bits(void)
-{
-        if (machine_is_pnx4008()) {
-                start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-                start_int_ack(SE_USB_OTG_ATX_INT_N);
-                start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-                start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-                start_int_ack(SE_USB_OTG_TIMER_INT);
-                start_int_umask(SE_USB_OTG_TIMER_INT);
-
-                start_int_set_rising_edge(SE_USB_I2C_INT);
-                start_int_ack(SE_USB_I2C_INT);
-                start_int_umask(SE_USB_I2C_INT);
-
-                start_int_set_rising_edge(SE_USB_INT);
-                start_int_ack(SE_USB_INT);
-                start_int_umask(SE_USB_INT);
-
-                start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-                start_int_ack(SE_USB_NEED_CLK_INT);
-                start_int_umask(SE_USB_NEED_CLK_INT);
-
-                start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-                start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-                start_int_umask(SE_USB_AHB_NEED_CLK_INT);
-        }
-}
-
-static void nxp_unset_usb_bits(void)
-{
-        if (machine_is_pnx4008()) {
-                start_int_mask(SE_USB_OTG_ATX_INT_N);
-                start_int_mask(SE_USB_OTG_TIMER_INT);
-                start_int_mask(SE_USB_I2C_INT);
-                start_int_mask(SE_USB_INT);
-                start_int_mask(SE_USB_NEED_CLK_INT);
-                start_int_mask(SE_USB_AHB_NEED_CLK_INT);
-        }
-}
-
 static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
         struct usb_hcd *hcd = 0;
@@ -376,9 +299,6 @@ static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
                 goto out8;
         }
 
-        /* Set all USB bits in the Start Enable register */
-        nxp_set_usb_bits();
-
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!res) {
                 dev_err(&pdev->dev, "Failed to get MEM resource\n");
@@ -413,7 +333,6 @@ static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 
         nxp_stop_hc();
 out8:
-        nxp_unset_usb_bits();
         usb_put_hcd(hcd);
 out7:
         clk_disable(usb_otg_clk);
@@ -441,7 +360,6 @@ static int usb_hcd_nxp_remove(struct platform_device *pdev)
         nxp_stop_hc();
         release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
         usb_put_hcd(hcd);
-        nxp_unset_usb_bits();
         clk_disable(usb_pll_clk);
         clk_put(usb_pll_clk);
         clk_disable(usb_dev_clk);
diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
index f8b2d91851f7..4531d03503c3 100644
--- a/drivers/usb/host/ohci-omap.c
+++ b/drivers/usb/host/ohci-omap.c
@@ -24,7 +24,7 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/fpga.h>
 
 #include <mach/hardware.h>
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index e1a3cc6d28dc..955c410d59b6 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -24,8 +24,8 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <mach/hardware.h>
-#include <mach/ohci.h>
-#include <mach/pxa3xx-u2d.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/usb-pxa3xx-ulpi.h>
 
 /*
  * UHC: USB Host Controller (OHCI-like) register definitions
diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
index 664c869eb096..0d2309ca471e 100644
--- a/drivers/usb/host/ohci-s3c2410.c
+++ b/drivers/usb/host/ohci-s3c2410.c
@@ -21,7 +21,7 @@
 
 #include <linux/platform_device.h>
 #include <linux/clk.h>
-#include <plat/usb-control.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
 
 #define valid_port(idx) ((idx) == 1 || (idx) == 2)
 
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index 0f9fcec4e1d3..15a262754150 100644
--- a/drivers/usb/musb/da8xx.c
+++ b/drivers/usb/musb/da8xx.c
@@ -35,7 +35,7 @@
 #include <linux/dma-mapping.h>
 
 #include <mach/da8xx.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
 
 #include "musb_core.h"
 
diff --git a/drivers/usb/musb/tusb6010_omap.c b/drivers/usb/musb/tusb6010_omap.c
index b67b4bc596c1..89f0709f8935 100644
--- a/drivers/usb/musb/tusb6010_omap.c
+++ b/drivers/usb/musb/tusb6010_omap.c
@@ -17,7 +17,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <plat/dma.h>
-#include <plat/mux.h>
 
 #include "musb_core.h"
 #include "tusb6010.h"
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index d05c7fbbb703..f82246d2fd16 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -30,7 +30,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
 #include <linux/pfn.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-musb-ux500.h>
 #include "musb_core.h"
 
 struct ux500_dma_channel {
diff --git a/drivers/usb/otg/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c
index 7a88667742b6..81f1f9a0be8f 100644
--- a/drivers/usb/otg/isp1301_omap.c
+++ b/drivers/usb/otg/isp1301_omap.c
@@ -36,7 +36,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #include <mach/usb.h>
 
diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
index 92257ef19403..9a046a4c98f5 100644
--- a/drivers/video/backlight/omap1_bl.c
+++ b/drivers/video/backlight/omap1_bl.c
@@ -30,7 +30,7 @@
 #include <linux/platform_data/omap1_bl.h>
 
 #include <mach/hardware.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #define OMAPBL_MAX_INTENSITY            0xff
 
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 7ae9d53f2bf1..113d43a16f54 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -131,7 +131,7 @@
 #define UPPER_MARGIN    32
 #define LOWER_MARGIN    32
 
-static resource_size_t da8xx_fb_reg_base;
+static void __iomem *da8xx_fb_reg_base;
 static struct resource *lcdc_regs;
 static unsigned int lcd_revision;
 static irq_handler_t lcdc_irq_handler;
@@ -951,7 +951,7 @@ static int __devexit fb_remove(struct platform_device *dev)
                 clk_disable(par->lcdc_clk);
                 clk_put(par->lcdc_clk);
                 framebuffer_release(info);
-                iounmap((void __iomem *)da8xx_fb_reg_base);
+                iounmap(da8xx_fb_reg_base);
                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
 
         }
@@ -1171,7 +1171,7 @@ static int __devinit fb_probe(struct platform_device *device)
         if (!lcdc_regs)
                 return -EBUSY;
 
-        da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
+        da8xx_fb_reg_base = ioremap(lcdc_regs->start, len);
         if (!da8xx_fb_reg_base) {
                 ret = -EBUSY;
                 goto err_request_mem;
@@ -1392,7 +1392,7 @@ err_clk_put:
         clk_put(fb_clk);
 
 err_ioremap:
-        iounmap((void __iomem *)da8xx_fb_reg_base);
+        iounmap(da8xx_fb_reg_base);
 
 err_request_mem:
         release_mem_region(lcdc_regs->start, len);
diff --git a/drivers/video/ep93xx-fb.c b/drivers/video/ep93xx-fb.c
index 345d96230978..f2c092da84b0 100644
--- a/drivers/video/ep93xx-fb.c
+++ b/drivers/video/ep93xx-fb.c
@@ -24,7 +24,7 @@
 #include <linux/clk.h>
 #include <linux/fb.h>
 
-#include <mach/fb.h>
+#include <linux/platform_data/video-ep93xx.h>
 
 /* Vertical Frame Timing Registers */
 #define EP93XXFB_VLINES_TOTAL                   0x0000  /* SW locked */
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index caad3689b4e6..53ffdfc82a75 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -32,7 +32,7 @@
 #include <linux/io.h>
 #include <linux/math64.h>
 
-#include <mach/imxfb.h>
+#include <linux/platform_data/video-imxfb.h>
 #include <mach/hardware.h>
 
 /*
diff --git a/drivers/video/msm/mddi.c b/drivers/video/msm/mddi.c
index b061d709bc44..bf73f0480061 100644
--- a/drivers/video/msm/mddi.c
+++ b/drivers/video/msm/mddi.c
@@ -29,7 +29,7 @@
 #include <mach/msm_iomap.h>
 #include <mach/irqs.h>
 #include <mach/board.h>
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 #include "mddi_hw.h"
 
 #define FLAG_DISABLE_HIBERNATION 0x0001
diff --git a/drivers/video/msm/mddi_client_dummy.c b/drivers/video/msm/mddi_client_dummy.c
index d2a091cebe2c..f1b0dfcc9717 100644
--- a/drivers/video/msm/mddi_client_dummy.c
+++ b/drivers/video/msm/mddi_client_dummy.c
@@ -20,7 +20,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 
 struct panel_info {
         struct platform_device pdev;
diff --git a/drivers/video/msm/mddi_client_nt35399.c b/drivers/video/msm/mddi_client_nt35399.c
index 7fcd67e132bf..d7a5bf84fb2a 100644
--- a/drivers/video/msm/mddi_client_nt35399.c
+++ b/drivers/video/msm/mddi_client_nt35399.c
@@ -22,7 +22,7 @@
 #include <linux/sched.h>
 #include <linux/gpio.h>
 #include <linux/slab.h>
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 
 static DECLARE_WAIT_QUEUE_HEAD(nt35399_vsync_wait);
 
diff --git a/drivers/video/msm/mddi_client_toshiba.c b/drivers/video/msm/mddi_client_toshiba.c
index 053eb6877330..061d7dfebbf3 100644
--- a/drivers/video/msm/mddi_client_toshiba.c
+++ b/drivers/video/msm/mddi_client_toshiba.c
@@ -22,7 +22,7 @@
 #include <linux/gpio.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 
 
 #define LCD_CONTROL_BLOCK_BASE 0x110000
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index cb2ddf164c98..d1f881e8030e 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -26,7 +26,7 @@
 #include <linux/slab.h>
 
 #include <mach/msm_iomap.h>
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 #include <linux/platform_device.h>
 #include <linux/export.h>
 
diff --git a/drivers/video/msm/mdp_hw.h b/drivers/video/msm/mdp_hw.h
index d80477415caa..a0bacf581b32 100644
--- a/drivers/video/msm/mdp_hw.h
+++ b/drivers/video/msm/mdp_hw.h
@@ -16,7 +16,7 @@
 #define _MDP_HW_H_
 
 #include <mach/msm_iomap.h>
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 
 struct mdp_info {
         struct mdp_device mdp_dev;
diff --git a/drivers/video/msm/mdp_ppp.c b/drivers/video/msm/mdp_ppp.c
index 2b6564e8bfea..be6079cdfbb6 100644
--- a/drivers/video/msm/mdp_ppp.c
+++ b/drivers/video/msm/mdp_ppp.c
@@ -16,7 +16,7 @@
 #include <linux/file.h>
 #include <linux/delay.h>
 #include <linux/msm_mdp.h>
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 
 #include "mdp_hw.h"
 #include "mdp_scale_tables.h"
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index c6e3b4fcdd68..ec08a9ec377d 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -25,7 +25,7 @@
 #include <linux/msm_mdp.h>
 #include <linux/io.h>
 #include <linux/uaccess.h>
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 #include <mach/board.h>
 #include <linux/workqueue.h>
 #include <linux/clk.h>
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index c89f8a8d36d2..d7381088a180 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -27,10 +27,10 @@
 #include <linux/clk.h>
 #include <linux/mutex.h>
 
-#include <mach/dma.h>
+#include <linux/platform_data/dma-imx.h>
 #include <mach/hardware.h>
 #include <mach/ipu.h>
-#include <mach/mx3fb.h>
+#include <linux/platform_data/video-mx3fb.h>
 
 #include <asm/io.h>
 #include <asm/uaccess.h>
diff --git a/drivers/video/nuc900fb.c b/drivers/video/nuc900fb.c
index e10f551ade21..93387555337e 100644
--- a/drivers/video/nuc900fb.c
+++ b/drivers/video/nuc900fb.c
@@ -38,7 +38,7 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-ldm.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-nuc900fb.h>
 
 #include "nuc900fb.h"
 
diff --git a/drivers/video/nuc900fb.h b/drivers/video/nuc900fb.h
index bc7c9300f276..9a1ca6dbb6b2 100644
--- a/drivers/video/nuc900fb.h
+++ b/drivers/video/nuc900fb.h
@@ -16,7 +16,7 @@
 #define __NUC900FB_H
 
 #include <mach/map.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-nuc900fb.h>
 
 enum nuc900_lcddrv_type {
         LCDDRV_NUC910,
diff --git a/drivers/video/omap/lcd_ams_delta.c b/drivers/video/omap/lcd_ams_delta.c
index d3a311327227..ed4cad87fbcd 100644
--- a/drivers/video/omap/lcd_ams_delta.c
+++ b/drivers/video/omap/lcd_ams_delta.c
@@ -27,8 +27,7 @@
 #include <linux/lcd.h>
 #include <linux/gpio.h>
 
-#include <plat/board-ams-delta.h>
-#include <mach/hardware.h>
+#include <mach/board-ams-delta.h>
 
 #include "omapfb.h"
 
diff --git a/drivers/video/omap/lcd_mipid.c b/drivers/video/omap/lcd_mipid.c
index e3880c4a0bb1..b739600c51ac 100644
--- a/drivers/video/omap/lcd_mipid.c
+++ b/drivers/video/omap/lcd_mipid.c
@@ -25,7 +25,7 @@
 #include <linux/spi/spi.h>
 #include <linux/module.h>
 
-#include <plat/lcd_mipid.h>
+#include <linux/platform_data/lcd-mipid.h>
 
 #include "omapfb.h"
 
diff --git a/drivers/video/omap/lcd_osk.c b/drivers/video/omap/lcd_osk.c
index 5914220dfa9c..3aa62da89195 100644
--- a/drivers/video/omap/lcd_osk.c
+++ b/drivers/video/omap/lcd_osk.c
@@ -24,7 +24,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/gpio.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include "omapfb.h"
 
 static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 3f902557690e..4fa2ad43fd97 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -61,7 +61,7 @@
 #include <asm/irq.h>
 #include <asm/div64.h>
 #include <mach/bitfield.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 
 /*
  * Complain if VAR is out of range.
diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c
index 2a5fe6ede845..66a74f9073fb 100644
--- a/drivers/video/vt8500lcdfb.c
+++ b/drivers/video/vt8500lcdfb.c
@@ -30,7 +30,7 @@
 #include <linux/platform_device.h>
 #include <linux/wait.h>
 
-#include <mach/vt8500fb.h>
+#include <linux/platform_data/video-vt8500lcdfb.h>
 
 #include "vt8500lcdfb.h"
 #include "wmt_ge_rops.h"
diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index c8703bd61b74..ffeff4838120 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -29,7 +29,7 @@
 #include <linux/platform_device.h>
 #include <linux/wait.h>
 
-#include <mach/vt8500fb.h>
+#include <linux/platform_data/video-vt8500lcdfb.h>
 
 #include "wm8505fb_regs.h"
 #include "wmt_ge_rops.h"
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 53d75719078e..ad1bb9382a96 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -237,12 +237,12 @@ config OMAP_WATCHDOG
           here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer.
 
 config PNX4008_WATCHDOG
-        tristate "PNX4008 and LPC32XX Watchdog"
-        depends on ARCH_PNX4008 || ARCH_LPC32XX
+        tristate "LPC32XX Watchdog"
+        depends on ARCH_LPC32XX
         select WATCHDOG_CORE
         help
           Say Y here if to include support for the watchdog timer
-          in the PNX4008 or LPC32XX processor.
+          in the LPC32XX processor.
           This driver can be built as a module by choosing M. The module
           will be called pnx4008_wdt.
 
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c
index 59e75d9a6b7f..c1a4d3bf581d 100644
--- a/drivers/watchdog/ks8695_wdt.c
+++ b/drivers/watchdog/ks8695_wdt.c
@@ -24,7 +24,19 @@
 #include <linux/io.h>
 #include <linux/uaccess.h>
 #include <mach/hardware.h>
-#include <mach/regs-timer.h>
+
+#define KS8695_TMR_OFFSET       (0xF0000 + 0xE400)
+#define KS8695_TMR_VA           (KS8695_IO_VA + KS8695_TMR_OFFSET)
+
+/*
+ * Timer registers
+ */
+#define KS8695_TMCON            (0x00)          /* Timer Control Register */
+#define KS8695_T0TC             (0x08)          /* Timer 0 Timeout Count Register */
+#define TMCON_T0EN              (1 << 0)        /* Timer 0 Enable */
+
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG           (0xff)          /* Enable watchdog mode */
 
 #define WDT_DEFAULT_TIME        5       /* seconds */
 #define WDT_MAX_TIME            171     /* seconds */
diff --git a/arch/arm/mach-picoxcell/include/mach/hardware.h b/include/linux/bcm2835_timer.h
index 70ff58192ec9..25680fe0903c 100644
--- a/arch/arm/mach-picoxcell/include/mach/hardware.h
+++ b/include/linux/bcm2835_timer.h
@@ -1,7 +1,5 @@
 /*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This file contains the hardware definitions of the picoXcell SoC devices.
+ * Copyright 2012 Simon Arlott
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,9 +11,12 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
 
-#include <mach/picoxcell_soc.h>
+#ifndef __BCM2835_TIMER_H
+#define __BCM2835_TIMER_H
+
+#include <asm/mach/time.h>
+
+extern struct sys_timer bcm2835_timer;
 
 #endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 77335fac943e..c12731582920 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -26,6 +26,7 @@
 #define CLK_IGNORE_UNUSED       BIT(3) /* do not gate even if unused */
 #define CLK_IS_ROOT             BIT(4) /* root clk, has no parent */
 #define CLK_IS_BASIC            BIT(5) /* Basic clk, can't do a to_clk_foo() */
+#define CLK_GET_RATE_NOCACHE    BIT(6) /* do not use the cached clk rate */
 
 struct clk_hw;
 
@@ -360,6 +361,11 @@ int of_clk_add_provider(struct device_node *np,
 void of_clk_del_provider(struct device_node *np);
 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
                                   void *data);
+struct clk_onecell_data {
+        struct clk **clks;
+        unsigned int clk_num;
+};
+struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
 const char *of_clk_get_parent_name(struct device_node *np, int index);
 void of_clk_init(const struct of_device_id *matches);
 
diff --git a/arch/arm/mach-socfpga/include/mach/timex.h b/include/linux/clk/bcm2835.h
index 43df4354e461..aa937f6c17da 100644
--- a/arch/arm/mach-socfpga/include/mach/timex.h
+++ b/include/linux/clk/bcm2835.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2003 ARM Limited
+ * Copyright (C) 2010 Broadcom
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,4 +16,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#define CLOCK_TICK_RATE         (50000000 / 16)
+#ifndef __LINUX_CLK_BCM2835_H_
+#define __LINUX_CLK_BCM2835_H_
+
+void __init bcm2835_init_clocks(void);
+
+#endif
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/include/linux/irqchip/bcm2835.h
index 0406513be7d8..48a859bc9dca 100644
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ b/include/linux/irqchip/bcm2835.h
@@ -1,7 +1,5 @@
 /*
- *  arch/arm/mach-versatile/include/mach/io.h
- *
- *  Copyright (C) 2003 ARM Limited
+ * Copyright (C) 2010 Broadcom
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,11 +15,15 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
 
-#define PCIO_BASE       0xeb000000ul
+#ifndef __LINUX_IRQCHIP_BCM2835_H_
+#define __LINUX_IRQCHIP_BCM2835_H_
+
+#include <asm/exception.h>
+
+extern void bcm2835_init_irq(void);
 
-#define __io(a)         ((a) + PCIO_BASE)
+extern asmlinkage void __exception_irq_entry bcm2835_handle_irq(
+        struct pt_regs *regs);
 
 #endif
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index 5b90e94399e1..c410d99bd667 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -136,6 +136,7 @@ enum prcmu_clock {
         PRCMU_TIMCLK,
         PRCMU_PLLSOC0,
         PRCMU_PLLSOC1,
+        PRCMU_ARMSS,
         PRCMU_PLLDDR,
         PRCMU_PLLDSI,
         PRCMU_DSI0CLK,
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index f350fd0ba1df..94514710a03f 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -14,6 +14,7 @@
 #define TPS6586X_SLEW_RATE_MASK         0x07
 
 enum {
+        TPS6586X_ID_SYS,
         TPS6586X_ID_SM_0,
         TPS6586X_ID_SM_1,
         TPS6586X_ID_SM_2,
diff --git a/arch/arm/plat-mxc/include/mach/ssi.h b/include/linux/platform_data/asoc-imx-ssi.h
index 63f3c2804239..63f3c2804239 100644
--- a/arch/arm/plat-mxc/include/mach/ssi.h
+++ b/include/linux/platform_data/asoc-imx-ssi.h
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/include/linux/platform_data/asoc-kirkwood.h
index d6a55bd2e578..d6a55bd2e578 100644
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ b/include/linux/platform_data/asoc-kirkwood.h
diff --git a/arch/arm/mach-pxa/include/mach/palmasoc.h b/include/linux/platform_data/asoc-palm27x.h
index 58afb30d5298..58afb30d5298 100644
--- a/arch/arm/mach-pxa/include/mach/palmasoc.h
+++ b/include/linux/platform_data/asoc-palm27x.h
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/include/linux/platform_data/asoc-s3c.h
index aa9875f77c40..aa9875f77c40 100644
--- a/arch/arm/plat-samsung/include/plat/audio.h
+++ b/include/linux/platform_data/asoc-s3c.h
diff --git a/arch/arm/plat-samsung/include/plat/audio-simtec.h b/include/linux/platform_data/asoc-s3c24xx_simtec.h
index 376af5286a3e..376af5286a3e 100644
--- a/arch/arm/plat-samsung/include/plat/audio-simtec.h
+++ b/include/linux/platform_data/asoc-s3c24xx_simtec.h
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/include/linux/platform_data/asoc-ti-mcbsp.h
index 18814127809a..18814127809a 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/include/linux/platform_data/asoc-ti-mcbsp.h
diff --git a/arch/arm/mach-pxa/include/mach/pata_pxa.h b/include/linux/platform_data/ata-pxa.h
index 6cf7df1d5830..6cf7df1d5830 100644
--- a/arch/arm/mach-pxa/include/mach/pata_pxa.h
+++ b/include/linux/platform_data/ata-pxa.h
diff --git a/arch/arm/plat-samsung/include/plat/ata.h b/include/linux/platform_data/ata-samsung_cf.h
index 2a3855a8372a..2a3855a8372a 100644
--- a/arch/arm/plat-samsung/include/plat/ata.h
+++ b/include/linux/platform_data/ata-samsung_cf.h
diff --git a/include/linux/platform_data/atmel-aes.h b/include/linux/platform_data/atmel-aes.h
index e7a1949bad26..ab68082fbcb0 100644
--- a/include/linux/platform_data/atmel-aes.h
+++ b/include/linux/platform_data/atmel-aes.h
@@ -1,7 +1,7 @@
 #ifndef __LINUX_ATMEL_AES_H
 #define __LINUX_ATMEL_AES_H
 
-#include <mach/at_hdmac.h>
+#include <linux/platform_data/dma-atmel.h>
 
 /**
  * struct aes_dma_data - DMA data for AES
diff --git a/arch/arm/plat-mxc/include/mach/mx1_camera.h b/include/linux/platform_data/camera-mx1.h
index 4fd6c70314b4..4fd6c70314b4 100644
--- a/arch/arm/plat-mxc/include/mach/mx1_camera.h
+++ b/include/linux/platform_data/camera-mx1.h
diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/include/linux/platform_data/camera-mx2.h
index 3c080a32dbf5..7ded6f1f74bc 100644
--- a/arch/arm/plat-mxc/include/mach/mx2_cam.h
+++ b/include/linux/platform_data/camera-mx2.h
@@ -23,7 +23,6 @@
 #ifndef __MACH_MX2_CAM_H_
 #define __MACH_MX2_CAM_H_
 
-#define MX2_CAMERA_SWAP16               (1 << 0)
 #define MX2_CAMERA_EXT_VSYNC            (1 << 1)
 #define MX2_CAMERA_CCIR                 (1 << 2)
 #define MX2_CAMERA_CCIR_INTERLACE       (1 << 3)
@@ -31,7 +30,6 @@
 #define MX2_CAMERA_GATED_CLOCK          (1 << 5)
 #define MX2_CAMERA_INV_DATA             (1 << 6)
 #define MX2_CAMERA_PCLK_SAMPLE_RISING   (1 << 7)
-#define MX2_CAMERA_PACK_DIR_MSB         (1 << 8)
 
 /**
  * struct mx2_camera_platform_data - optional platform data for mx2_camera
diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/include/linux/platform_data/camera-mx3.h
index f226ee3777e1..f226ee3777e1 100644
--- a/arch/arm/plat-mxc/include/mach/mx3_camera.h
+++ b/include/linux/platform_data/camera-mx3.h
diff --git a/arch/arm/mach-pxa/include/mach/camera.h b/include/linux/platform_data/camera-pxa.h
index 6709b1cd7c77..6709b1cd7c77 100644
--- a/arch/arm/mach-pxa/include/mach/camera.h
+++ b/include/linux/platform_data/camera-pxa.h
diff --git a/include/linux/platform_data/clk-realview.h b/include/linux/platform_data/clk-realview.h
new file mode 100644
index 000000000000..2e426a7dbc51
--- /dev/null
+++ b/include/linux/platform_data/clk-realview.h
@@ -0,0 +1 @@
+void realview_clk_init(void __iomem *sysbase, bool is_pb1176);
diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h
new file mode 100644
index 000000000000..3af0da1f3be5
--- /dev/null
+++ b/include/linux/platform_data/clk-ux500.h
@@ -0,0 +1,17 @@
+/*
+ * Clock definitions for ux500 platforms
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __CLK_UX500_H
+#define __CLK_UX500_H
+
+void u8500_clk_init(void);
+void u9540_clk_init(void);
+void u8540_clk_init(void);
+
+#endif /* __CLK_UX500_H */
diff --git a/arch/arm/mach-ux500/include/mach/crypto-ux500.h b/include/linux/platform_data/crypto-ux500.h
index 5b2d0817e26a..5b2d0817e26a 100644
--- a/arch/arm/mach-ux500/include/mach/crypto-ux500.h
+++ b/include/linux/platform_data/crypto-ux500.h
diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/include/linux/platform_data/dma-atmel.h
index cab0997be3de..cab0997be3de 100644
--- a/arch/arm/mach-at91/include/mach/at_hdmac.h
+++ b/include/linux/platform_data/dma-atmel.h
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/include/linux/platform_data/dma-ep93xx.h
index e82c642fa53c..e82c642fa53c 100644
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ b/include/linux/platform_data/dma-ep93xx.h
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/include/linux/platform_data/dma-imx-sdma.h
index 3a3942823c20..3a3942823c20 100644
--- a/arch/arm/plat-mxc/include/mach/sdma.h
+++ b/include/linux/platform_data/dma-imx-sdma.h
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/include/linux/platform_data/dma-imx.h
index 1b9080385b46..1b9080385b46 100644
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ b/include/linux/platform_data/dma-imx.h
diff --git a/arch/arm/mach-mmp/include/mach/sram.h b/include/linux/platform_data/dma-mmp_tdma.h
index 239e0fc1bb1f..239e0fc1bb1f 100644
--- a/arch/arm/mach-mmp/include/mach/sram.h
+++ b/include/linux/platform_data/dma-mmp_tdma.h
diff --git a/arch/arm/plat-orion/include/plat/mv_xor.h b/include/linux/platform_data/dma-mv_xor.h
index 2ba1f7d76eef..2ba1f7d76eef 100644
--- a/arch/arm/plat-orion/include/plat/mv_xor.h
+++ b/include/linux/platform_data/dma-mv_xor.h
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/include/linux/platform_data/dsp-omap.h
index 5927709b1908..5927709b1908 100644
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ b/include/linux/platform_data/dsp-omap.h
diff --git a/arch/arm/mach-netx/include/mach/eth.h b/include/linux/platform_data/eth-netx.h
index 88af1ac28ead..88af1ac28ead 100644
--- a/arch/arm/mach-netx/include/mach/eth.h
+++ b/include/linux/platform_data/eth-netx.h
diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/include/linux/platform_data/hwmon-s3c.h
index c167e4429bc7..c167e4429bc7 100644
--- a/arch/arm/plat-samsung/include/plat/hwmon.h
+++ b/include/linux/platform_data/hwmon-s3c.h
diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/include/linux/platform_data/i2c-davinci.h
index 2312d197dfb7..2312d197dfb7 100644
--- a/arch/arm/mach-davinci/include/mach/i2c.h
+++ b/include/linux/platform_data/i2c-davinci.h
diff --git a/arch/arm/plat-mxc/include/mach/i2c.h b/include/linux/platform_data/i2c-imx.h
index 8289d915e615..8289d915e615 100644
--- a/arch/arm/plat-mxc/include/mach/i2c.h
+++ b/include/linux/platform_data/i2c-imx.h
diff --git a/arch/arm/mach-w90x900/include/mach/i2c.h b/include/linux/platform_data/i2c-nuc900.h
index 9ffb12d06e91..9ffb12d06e91 100644
--- a/arch/arm/mach-w90x900/include/mach/i2c.h
+++ b/include/linux/platform_data/i2c-nuc900.h
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/include/linux/platform_data/i2c-s3c2410.h
index 51d52e767a19..51d52e767a19 100644
--- a/arch/arm/plat-samsung/include/plat/iic.h
+++ b/include/linux/platform_data/i2c-s3c2410.h
diff --git a/arch/arm/mach-pxa/include/mach/irda.h b/include/linux/platform_data/irda-pxaficp.h
index 3cd41f77dda4..3cd41f77dda4 100644
--- a/arch/arm/mach-pxa/include/mach/irda.h
+++ b/include/linux/platform_data/irda-pxaficp.h
diff --git a/arch/arm/mach-pxa/include/mach/pxa930_rotary.h b/include/linux/platform_data/keyboard-pxa930_rotary.h
index 053587caffdd..053587caffdd 100644
--- a/arch/arm/mach-pxa/include/mach/pxa930_rotary.h
+++ b/include/linux/platform_data/keyboard-pxa930_rotary.h
diff --git a/arch/arm/plat-spear/include/plat/keyboard.h b/include/linux/platform_data/keyboard-spear.h
index 9248e3a7e333..9248e3a7e333 100644
--- a/arch/arm/plat-spear/include/plat/keyboard.h
+++ b/include/linux/platform_data/keyboard-spear.h
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h b/include/linux/platform_data/keypad-ep93xx.h
index 1e2f4e97f428..1e2f4e97f428 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
+++ b/include/linux/platform_data/keypad-ep93xx.h
diff --git a/arch/arm/plat-nomadik/include/plat/ske.h b/include/linux/platform_data/keypad-nomadik-ske.h
index 31382fbc07dc..31382fbc07dc 100644
--- a/arch/arm/plat-nomadik/include/plat/ske.h
+++ b/include/linux/platform_data/keypad-nomadik-ske.h
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/include/linux/platform_data/keypad-omap.h
index a6b21eddb212..a6b21eddb212 100644
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ b/include/linux/platform_data/keypad-omap.h
diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/include/linux/platform_data/keypad-pxa27x.h
index 5ce8d5e6ea51..5ce8d5e6ea51 100644
--- a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
+++ b/include/linux/platform_data/keypad-pxa27x.h
diff --git a/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h b/include/linux/platform_data/keypad-w90p910.h
index 556778e8ddaa..556778e8ddaa 100644
--- a/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h
+++ b/include/linux/platform_data/keypad-w90p910.h
diff --git a/arch/arm/mach-davinci/include/mach/keyscan.h b/include/linux/platform_data/keyscan-davinci.h
index 7a560e05bda8..7a560e05bda8 100644
--- a/arch/arm/mach-davinci/include/mach/keyscan.h
+++ b/include/linux/platform_data/keyscan-davinci.h
diff --git a/arch/arm/plat-omap/include/plat/lcd_mipid.h b/include/linux/platform_data/lcd-mipid.h
index 8e52c6572281..8e52c6572281 100644
--- a/arch/arm/plat-omap/include/plat/lcd_mipid.h
+++ b/include/linux/platform_data/lcd-mipid.h
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h b/include/linux/platform_data/leds-kirkwood-netxbig.h
index 24b536ebdf13..24b536ebdf13 100644
--- a/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
+++ b/include/linux/platform_data/leds-kirkwood-netxbig.h
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/include/linux/platform_data/leds-kirkwood-ns2.h
index e21272e5f668..e21272e5f668 100644
--- a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
+++ b/include/linux/platform_data/leds-kirkwood-ns2.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h b/include/linux/platform_data/leds-s3c24xx.h
index d8a7672519b6..d8a7672519b6 100644
--- a/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h
+++ b/include/linux/platform_data/leds-s3c24xx.h
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/include/linux/platform_data/mfd-mcp-sa11x0.h
index 4b2860ae3828..4b2860ae3828 100644
--- a/arch/arm/mach-sa1100/include/mach/mcp.h
+++ b/include/linux/platform_data/mfd-mcp-sa11x0.h
diff --git a/arch/arm/plat-samsung/include/plat/mipi_csis.h b/include/linux/platform_data/mipi-csis.h
index c45b1e8d4c2e..c45b1e8d4c2e 100644
--- a/arch/arm/plat-samsung/include/plat/mipi_csis.h
+++ b/include/linux/platform_data/mipi-csis.h
diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/include/linux/platform_data/mmc-davinci.h
index 5ba6b22ce338..5ba6b22ce338 100644
--- a/arch/arm/mach-davinci/include/mach/mmc.h
+++ b/include/linux/platform_data/mmc-davinci.h
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/include/linux/platform_data/mmc-esdhc-imx.h
index aaf97481f413..aaf97481f413 100644
--- a/arch/arm/plat-mxc/include/mach/esdhc.h
+++ b/include/linux/platform_data/mmc-esdhc-imx.h
diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/include/linux/platform_data/mmc-msm_sdcc.h
index ffcd9e3a6a7e..ffcd9e3a6a7e 100644
--- a/arch/arm/mach-msm/include/mach/mmc.h
+++ b/include/linux/platform_data/mmc-msm_sdcc.h
diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/include/linux/platform_data/mmc-mvsdio.h
index 1190efedcb94..1190efedcb94 100644
--- a/arch/arm/plat-orion/include/plat/mvsdio.h
+++ b/include/linux/platform_data/mmc-mvsdio.h
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/include/linux/platform_data/mmc-mxcmmc.h
index 29115f405af9..29115f405af9 100644
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/include/linux/platform_data/mmc-mxcmmc.h
diff --git a/arch/arm/mach-pxa/include/mach/mmc.h b/include/linux/platform_data/mmc-pxamci.h
index 9eb515bb799d..9eb515bb799d 100644
--- a/arch/arm/mach-pxa/include/mach/mmc.h
+++ b/include/linux/platform_data/mmc-pxamci.h
diff --git a/arch/arm/plat-samsung/include/plat/mci.h b/include/linux/platform_data/mmc-s3cmci.h
index c42d31711944..c42d31711944 100644
--- a/arch/arm/plat-samsung/include/plat/mci.h
+++ b/include/linux/platform_data/mmc-s3cmci.h
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/include/linux/platform_data/mmc-sdhci-tegra.h
index 4231bc7b8652..8f8430697686 100644
--- a/arch/arm/mach-tegra/include/mach/sdhci.h
+++ b/include/linux/platform_data/mmc-sdhci-tegra.h
@@ -1,6 +1,4 @@
 /*
- * include/asm-arm/arch-tegra/include/mach/sdhci.h
- *
  * Copyright (C) 2009 Palm, Inc.
  * Author: Yvonne Yip <y@palm.com>
  *
@@ -14,8 +12,8 @@
  * GNU General Public License for more details.
  *
  */
-#ifndef __ASM_ARM_ARCH_TEGRA_SDHCI_H
-#define __ASM_ARM_ARCH_TEGRA_SDHCI_H
+#ifndef __PLATFORM_DATA_TEGRA_SDHCI_H
+#define __PLATFORM_DATA_TEGRA_SDHCI_H
 
 #include <linux/mmc/host.h>
 
diff --git a/arch/arm/mach-pxa/include/mach/pxa930_trkball.h b/include/linux/platform_data/mouse-pxa930_trkball.h
index 5e0789bc4729..5e0789bc4729 100644
--- a/arch/arm/mach-pxa/include/mach/pxa930_trkball.h
+++ b/include/linux/platform_data/mouse-pxa930_trkball.h
diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/include/linux/platform_data/mtd-davinci-aemif.h
index 05b293443097..05b293443097 100644
--- a/arch/arm/mach-davinci/include/mach/aemif.h
+++ b/include/linux/platform_data/mtd-davinci-aemif.h
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/include/linux/platform_data/mtd-davinci.h
index 1cf555aef896..1cf555aef896 100644
--- a/arch/arm/mach-davinci/include/mach/nand.h
+++ b/include/linux/platform_data/mtd-davinci.h
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/include/linux/platform_data/mtd-mxc_nand.h
index 6bb96ef1600b..6bb96ef1600b 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/include/linux/platform_data/mtd-mxc_nand.h
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/include/linux/platform_data/mtd-nand-omap2.h
index 1a68c1e5fe53..1a68c1e5fe53 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/include/linux/platform_data/mtd-nand-pxa3xx.h
index c42f39f20195..c42f39f20195 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/include/linux/platform_data/mtd-nand-pxa3xx.h
diff --git a/arch/arm/plat-samsung/include/plat/nand.h b/include/linux/platform_data/mtd-nand-s3c2410.h
index b64115fa93a4..b64115fa93a4 100644
--- a/arch/arm/plat-samsung/include/plat/nand.h
+++ b/include/linux/platform_data/mtd-nand-s3c2410.h
diff --git a/arch/arm/mach-nomadik/include/mach/nand.h b/include/linux/platform_data/mtd-nomadik-nand.h
index c3c8254c22a5..c3c8254c22a5 100644
--- a/arch/arm/mach-nomadik/include/mach/nand.h
+++ b/include/linux/platform_data/mtd-nomadik-nand.h
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/include/linux/platform_data/mtd-onenand-omap2.h
index 2858667d2e4f..2858667d2e4f 100644
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ b/include/linux/platform_data/mtd-onenand-omap2.h
diff --git a/arch/arm/plat-orion/include/plat/orion_nand.h b/include/linux/platform_data/mtd-orion_nand.h
index 9f3c180834d1..9f3c180834d1 100644
--- a/arch/arm/plat-orion/include/plat/orion_nand.h
+++ b/include/linux/platform_data/mtd-orion_nand.h
diff --git a/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h b/include/linux/platform_data/pcmcia-pxa2xx_viper.h
index d428be4db44c..d428be4db44c 100644
--- a/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h
+++ b/include/linux/platform_data/pcmcia-pxa2xx_viper.h
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/include/linux/platform_data/pinctrl-coh901.h
index e81400c1753a..30dea251b835 100644
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ b/include/linux/platform_data/pinctrl-coh901.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * GPIO block resgister definitions and inline macros for
  * U300 GPIO COH 901 335 or COH 901 571/3
@@ -10,24 +10,13 @@
 #define __MACH_U300_GPIO_U300_H
 
 /**
- * enum u300_gpio_variant - the type of U300 GPIO employed
- */
-enum u300_gpio_variant {
-        U300_GPIO_COH901335,
-        U300_GPIO_COH901571_3_BS335,
-        U300_GPIO_COH901571_3_BS365,
-};
-
-/**
  * struct u300_gpio_platform - U300 GPIO platform data
- * @variant: IP block variant
  * @ports: number of GPIO block ports
  * @gpio_base: first GPIO number for this block (use a free range)
  * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
  * @pinctrl_device: pin control device to spawn as child
  */
 struct u300_gpio_platform {
-        enum u300_gpio_variant variant;
         u8 ports;
         int gpio_base;
         int gpio_irq_base;
diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/include/linux/platform_data/remoteproc-omap.h
index b10eac89e2e9..b10eac89e2e9 100644
--- a/arch/arm/plat-omap/include/plat/remoteproc.h
+++ b/include/linux/platform_data/remoteproc-omap.h
diff --git a/arch/arm/plat-mxc/include/mach/imx-uart.h b/include/linux/platform_data/serial-imx.h
index 4adec9b154dd..4adec9b154dd 100644
--- a/arch/arm/plat-mxc/include/mach/imx-uart.h
+++ b/include/linux/platform_data/serial-imx.h
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/include/linux/platform_data/spi-davinci.h
index 7af305b37868..7af305b37868 100644
--- a/arch/arm/mach-davinci/include/mach/spi.h
+++ b/include/linux/platform_data/spi-davinci.h
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h b/include/linux/platform_data/spi-ep93xx.h
index 9bb63ac13f04..9bb63ac13f04 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
+++ b/include/linux/platform_data/spi-ep93xx.h
diff --git a/arch/arm/plat-mxc/include/mach/spi.h b/include/linux/platform_data/spi-imx.h
index 08be445e8eb8..08be445e8eb8 100644
--- a/arch/arm/plat-mxc/include/mach/spi.h
+++ b/include/linux/platform_data/spi-imx.h
diff --git a/arch/arm/mach-w90x900/include/mach/nuc900_spi.h b/include/linux/platform_data/spi-nuc900.h
index 2c4e0c128501..2c4e0c128501 100644
--- a/arch/arm/mach-w90x900/include/mach/nuc900_spi.h
+++ b/include/linux/platform_data/spi-nuc900.h
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/include/linux/platform_data/spi-omap2-mcspi.h
index a357eb26bd25..a357eb26bd25 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/include/linux/platform_data/spi-omap2-mcspi.h
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/include/linux/platform_data/spi-s3c64xx.h
index ceba18d23a5a..ceba18d23a5a 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/include/linux/platform_data/spi-s3c64xx.h
diff --git a/arch/arm/plat-samsung/include/plat/ts.h b/include/linux/platform_data/touchscreen-s3c2410.h
index 26fdb22e0fc2..26fdb22e0fc2 100644
--- a/arch/arm/plat-samsung/include/plat/ts.h
+++ b/include/linux/platform_data/touchscreen-s3c2410.h
diff --git a/arch/arm/mach-davinci/include/mach/usb.h b/include/linux/platform_data/usb-davinci.h
index e0bc4abe69c2..e0bc4abe69c2 100644
--- a/arch/arm/mach-davinci/include/mach/usb.h
+++ b/include/linux/platform_data/usb-davinci.h
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/include/linux/platform_data/usb-ehci-mxc.h
index 7eb9d1329671..7eb9d1329671 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/include/linux/platform_data/usb-ehci-mxc.h
diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/include/linux/platform_data/usb-ehci-orion.h
index 6fc78e430420..6fc78e430420 100644
--- a/arch/arm/plat-orion/include/plat/ehci-orion.h
+++ b/include/linux/platform_data/usb-ehci-orion.h
diff --git a/arch/arm/plat-samsung/include/plat/ehci.h b/include/linux/platform_data/usb-ehci-s5p.h
index 5f28cae18582..5f28cae18582 100644
--- a/arch/arm/plat-samsung/include/plat/ehci.h
+++ b/include/linux/platform_data/usb-ehci-s5p.h
diff --git a/arch/arm/mach-exynos/include/mach/ohci.h b/include/linux/platform_data/usb-exynos.h
index c256c595be5e..c256c595be5e 100644
--- a/arch/arm/mach-exynos/include/mach/ohci.h
+++ b/include/linux/platform_data/usb-exynos.h
diff --git a/arch/arm/plat-mxc/include/mach/usb.h b/include/linux/platform_data/usb-imx_udc.h
index be273371f34a..be273371f34a 100644
--- a/arch/arm/plat-mxc/include/mach/usb.h
+++ b/include/linux/platform_data/usb-imx_udc.h
diff --git a/arch/arm/mach-ux500/include/mach/usb.h b/include/linux/platform_data/usb-musb-ux500.h
index 4c1cc50a595a..4c1cc50a595a 100644
--- a/arch/arm/mach-ux500/include/mach/usb.h
+++ b/include/linux/platform_data/usb-musb-ux500.h
diff --git a/arch/arm/plat-mxc/include/mach/mx21-usbhost.h b/include/linux/platform_data/usb-mx2.h
index 22d0b596262c..22d0b596262c 100644
--- a/arch/arm/plat-mxc/include/mach/mx21-usbhost.h
+++ b/include/linux/platform_data/usb-mx2.h
diff --git a/arch/arm/mach-pxa/include/mach/ohci.h b/include/linux/platform_data/usb-ohci-pxa27x.h
index 95b6e2a6e514..95b6e2a6e514 100644
--- a/arch/arm/mach-pxa/include/mach/ohci.h
+++ b/include/linux/platform_data/usb-ohci-pxa27x.h
diff --git a/arch/arm/plat-samsung/include/plat/usb-control.h b/include/linux/platform_data/usb-ohci-s3c2410.h
index 7fa1fbefc3f2..7fa1fbefc3f2 100644
--- a/arch/arm/plat-samsung/include/plat/usb-control.h
+++ b/include/linux/platform_data/usb-ohci-s3c2410.h
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h b/include/linux/platform_data/usb-pxa3xx-ulpi.h
index 9d82cb65ea56..9d82cb65ea56 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
+++ b/include/linux/platform_data/usb-pxa3xx-ulpi.h
diff --git a/arch/arm/plat-samsung/include/plat/udc.h b/include/linux/platform_data/usb-s3c2410_udc.h
index de8e2288a509..de8e2288a509 100644
--- a/arch/arm/plat-samsung/include/plat/udc.h
+++ b/include/linux/platform_data/usb-s3c2410_udc.h
diff --git a/arch/arm/mach-ep93xx/include/mach/fb.h b/include/linux/platform_data/video-ep93xx.h
index d5ae11d7c453..d5ae11d7c453 100644
--- a/arch/arm/mach-ep93xx/include/mach/fb.h
+++ b/include/linux/platform_data/video-ep93xx.h
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/include/linux/platform_data/video-imxfb.h
index 9de8f062ad5d..9de8f062ad5d 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/include/linux/platform_data/video-imxfb.h
diff --git a/arch/arm/mach-msm/include/mach/msm_fb.h b/include/linux/platform_data/video-msm_fb.h
index 1f4fc81b3d8f..1f4fc81b3d8f 100644
--- a/arch/arm/mach-msm/include/mach/msm_fb.h
+++ b/include/linux/platform_data/video-msm_fb.h
diff --git a/arch/arm/plat-mxc/include/mach/mx3fb.h b/include/linux/platform_data/video-mx3fb.h
index fdbe60001542..fdbe60001542 100644
--- a/arch/arm/plat-mxc/include/mach/mx3fb.h
+++ b/include/linux/platform_data/video-mx3fb.h
diff --git a/arch/arm/mach-w90x900/include/mach/fb.h b/include/linux/platform_data/video-nuc900fb.h
index cec5ece765ed..cec5ece765ed 100644
--- a/arch/arm/mach-w90x900/include/mach/fb.h
+++ b/include/linux/platform_data/video-nuc900fb.h
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/include/linux/platform_data/video-pxafb.h
index 486b4c519ae2..486b4c519ae2 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/include/linux/platform_data/video-pxafb.h
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500fb.h b/include/linux/platform_data/video-vt8500lcdfb.h
index 7f399c370fe0..7f399c370fe0 100644
--- a/arch/arm/mach-vt8500/include/mach/vt8500fb.h
+++ b/include/linux/platform_data/video-vt8500lcdfb.h
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/include/linux/platform_data/voltage-omap.h
index 5be4d5def427..5be4d5def427 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/include/linux/platform_data/voltage-omap.h
diff --git a/include/linux/power/smartreflex.h b/include/linux/power/smartreflex.h
index 3101e62a1213..4a496ebc7d73 100644
--- a/include/linux/power/smartreflex.h
+++ b/include/linux/power/smartreflex.h
@@ -23,7 +23,7 @@
 #include <linux/types.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
-#include <plat/voltage.h>
+#include <linux/platform_data/voltage-omap.h>
 
 /*
  * Different Smartreflex IPs version. The v1 is the 65nm version used in
diff --git a/sound/soc/ep93xx/ep93xx-ac97.c b/sound/soc/ep93xx/ep93xx-ac97.c
index bdffab33e160..c3521653cfd3 100644
--- a/sound/soc/ep93xx/ep93xx-ac97.c
+++ b/sound/soc/ep93xx/ep93xx-ac97.c
@@ -21,7 +21,7 @@
 #include <sound/ac97_codec.h>
 #include <sound/soc.h>
 
-#include <mach/dma.h>
+#include <linux/platform_data/dma-ep93xx.h>
 #include "ep93xx-pcm.h"
 
 /*
diff --git a/sound/soc/ep93xx/ep93xx-i2s.c b/sound/soc/ep93xx/ep93xx-i2s.c
index 8df8f6dc474f..ac4a7515e7be 100644
--- a/sound/soc/ep93xx/ep93xx-i2s.c
+++ b/sound/soc/ep93xx/ep93xx-i2s.c
@@ -28,7 +28,7 @@
 
 #include <mach/hardware.h>
 #include <mach/ep93xx-regs.h>
-#include <mach/dma.h>
+#include <linux/platform_data/dma-ep93xx.h>
 
 #include "ep93xx-pcm.h"
 
diff --git a/sound/soc/ep93xx/ep93xx-pcm.c b/sound/soc/ep93xx/ep93xx-pcm.c
index 4eea98b42bc8..665d9c94cc17 100644
--- a/sound/soc/ep93xx/ep93xx-pcm.c
+++ b/sound/soc/ep93xx/ep93xx-pcm.c
@@ -25,7 +25,7 @@
 #include <sound/soc.h>
 #include <sound/dmaengine_pcm.h>
 
-#include <mach/dma.h>
+#include <linux/platform_data/dma-ep93xx.h>
 #include <mach/hardware.h>
 #include <mach/ep93xx-regs.h>
 
diff --git a/sound/soc/fsl/imx-pcm-dma.c b/sound/soc/fsl/imx-pcm-dma.c
index 48f9d886f020..89a7755b6f56 100644
--- a/sound/soc/fsl/imx-pcm-dma.c
+++ b/sound/soc/fsl/imx-pcm-dma.c
@@ -30,7 +30,7 @@
 #include <sound/soc.h>
 #include <sound/dmaengine_pcm.h>
 
-#include <mach/dma.h>
+#include <linux/platform_data/dma-imx.h>
 
 #include "imx-pcm.h"
 
diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
index ee27ba3933bd..22c6130957ba 100644
--- a/sound/soc/fsl/imx-pcm-fiq.c
+++ b/sound/soc/fsl/imx-pcm-fiq.c
@@ -30,7 +30,7 @@
 #include <asm/fiq.h>
 
 #include <mach/irqs.h>
-#include <mach/ssi.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 
 #include "imx-ssi.h"
 
diff --git a/sound/soc/fsl/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
index 81d7728cf67f..e6a17baca1ee 100644
--- a/sound/soc/fsl/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -47,7 +47,7 @@
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 
-#include <mach/ssi.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 #include <mach/hardware.h>
 
 #include "imx-ssi.h"
diff --git a/sound/soc/fsl/imx-ssi.h b/sound/soc/fsl/imx-ssi.h
index 5744e86ca878..dc114bdedce5 100644
--- a/sound/soc/fsl/imx-ssi.h
+++ b/sound/soc/fsl/imx-ssi.h
@@ -186,7 +186,7 @@
 #define DRV_NAME "imx-ssi"
 
 #include <linux/dmaengine.h>
-#include <mach/dma.h>
+#include <linux/platform_data/dma-imx.h>
 #include "imx-pcm.h"
 
 struct imx_ssi {
diff --git a/sound/soc/kirkwood/kirkwood-i2s.c b/sound/soc/kirkwood/kirkwood-i2s.c
index 7646dd7f30cb..542538d10ab7 100644
--- a/sound/soc/kirkwood/kirkwood-i2s.c
+++ b/sound/soc/kirkwood/kirkwood-i2s.c
@@ -21,7 +21,7 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-kirkwood.h>
 #include "kirkwood.h"
 
 #define DRV_NAME        "kirkwood-i2s"
diff --git a/sound/soc/kirkwood/kirkwood-openrd.c b/sound/soc/kirkwood/kirkwood-openrd.c
index 80bd59c33be4..c28540aeea25 100644
--- a/sound/soc/kirkwood/kirkwood-openrd.c
+++ b/sound/soc/kirkwood/kirkwood-openrd.c
@@ -17,7 +17,7 @@
 #include <linux/slab.h>
 #include <sound/soc.h>
 #include <mach/kirkwood.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-kirkwood.h>
 #include <asm/mach-types.h>
 #include "../codecs/cs42l51.h"
 
diff --git a/sound/soc/kirkwood/kirkwood-t5325.c b/sound/soc/kirkwood/kirkwood-t5325.c
index f8983635f7ef..c67bbc574987 100644
--- a/sound/soc/kirkwood/kirkwood-t5325.c
+++ b/sound/soc/kirkwood/kirkwood-t5325.c
@@ -16,7 +16,7 @@
 #include <linux/slab.h>
 #include <sound/soc.h>
 #include <mach/kirkwood.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-kirkwood.h>
 #include <asm/mach-types.h>
 #include "../codecs/alc5623.h"
 
diff --git a/sound/soc/omap/am3517evm.c b/sound/soc/omap/am3517evm.c
index df65f98211ec..a52e87d28b6e 100644
--- a/sound/soc/omap/am3517evm.c
+++ b/sound/soc/omap/am3517evm.c
@@ -27,7 +27,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/ams-delta.c b/sound/soc/omap/ams-delta.c
index 7d4fa8ed6699..dc0ee7626626 100644
--- a/sound/soc/omap/ams-delta.c
+++ b/sound/soc/omap/ams-delta.c
@@ -32,8 +32,8 @@
 
 #include <asm/mach-types.h>
 
-#include <plat/board-ams-delta.h>
-#include <plat/mcbsp.h>
+#include <mach/board-ams-delta.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/igep0020.c b/sound/soc/omap/igep0020.c
index e8357819175b..5ed871676ed0 100644
--- a/sound/soc/omap/igep0020.c
+++ b/sound/soc/omap/igep0020.c
@@ -29,7 +29,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index f18e48847323..a681a9a8b846 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -25,7 +25,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include <plat/cpu.h>
 
diff --git a/sound/soc/omap/n810.c b/sound/soc/omap/n810.c
index abac4b690750..521bfc3d2b2b 100644
--- a/sound/soc/omap/n810.c
+++ b/sound/soc/omap/n810.c
@@ -32,7 +32,7 @@
 #include <mach/hardware.h>
 #include <linux/gpio.h>
 #include <linux/module.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index d0ee71d6cc23..1b18627763ce 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -34,7 +34,7 @@
 
 #include <plat/cpu.h>
 #include <plat/dma.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 #include "mcbsp.h"
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c
index 2830dfd05661..e263188841b6 100644
--- a/sound/soc/omap/omap3beagle.c
+++ b/sound/soc/omap/omap3beagle.c
@@ -29,7 +29,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c
index 3d468c9179d7..d632bfbb6983 100644
--- a/sound/soc/omap/omap3evm.c
+++ b/sound/soc/omap/omap3evm.c
@@ -27,7 +27,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/omap3pandora.c b/sound/soc/omap/omap3pandora.c
index 4c3a0978578a..43d950a79ff9 100644
--- a/sound/soc/omap/omap3pandora.c
+++ b/sound/soc/omap/omap3pandora.c
@@ -31,7 +31,7 @@
 #include <sound/soc.h>
 
 #include <asm/mach-types.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/osk5912.c b/sound/soc/omap/osk5912.c
index b1a9d64cbc56..3960e8df9c76 100644
--- a/sound/soc/omap/osk5912.c
+++ b/sound/soc/omap/osk5912.c
@@ -31,7 +31,7 @@
 #include <mach/hardware.h>
 #include <linux/gpio.h>
 #include <linux/module.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/overo.c b/sound/soc/omap/overo.c
index 6ac3e0c3c282..502bce299885 100644
--- a/sound/soc/omap/overo.c
+++ b/sound/soc/omap/overo.c
@@ -29,7 +29,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/rx51.c b/sound/soc/omap/rx51.c
index 2712dd232b6d..d921ddbe3ecb 100644
--- a/sound/soc/omap/rx51.c
+++ b/sound/soc/omap/rx51.c
@@ -31,7 +31,7 @@
 #include <sound/jack.h>
 #include <sound/pcm.h>
 #include <sound/soc.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 #include "../codecs/tpa6130a2.h"
 
 #include <asm/mach-types.h>
diff --git a/sound/soc/omap/sdp3430.c b/sound/soc/omap/sdp3430.c
index 78e14198aa11..597cae769cea 100644
--- a/sound/soc/omap/sdp3430.c
+++ b/sound/soc/omap/sdp3430.c
@@ -33,8 +33,8 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 /* Register descriptions for twl4030 codec part */
 #include <linux/mfd/twl4030-audio.h>
diff --git a/sound/soc/omap/zoom2.c b/sound/soc/omap/zoom2.c
index 920e0d9e03db..23de2b21d696 100644
--- a/sound/soc/omap/zoom2.c
+++ b/sound/soc/omap/zoom2.c
@@ -29,7 +29,7 @@
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 #include <mach/board-zoom.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 /* Register descriptions for twl4030 codec part */
 #include <linux/mfd/twl4030-audio.h>
diff --git a/sound/soc/pxa/palm27x.c b/sound/soc/pxa/palm27x.c
index db24bc685bd3..aa3da91907c6 100644
--- a/sound/soc/pxa/palm27x.c
+++ b/sound/soc/pxa/palm27x.c
@@ -25,7 +25,7 @@
 
 #include <asm/mach-types.h>
 #include <mach/audio.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 
 #include "../codecs/wm9712.h"
 #include "pxa2xx-ac97.h"
diff --git a/sound/soc/samsung/ac97.c b/sound/soc/samsung/ac97.c
index 3d04c1fa6781..14fbcd30cae5 100644
--- a/sound/soc/samsung/ac97.c
+++ b/sound/soc/samsung/ac97.c
@@ -21,7 +21,7 @@
 
 #include <mach/dma.h>
 #include <plat/regs-ac97.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 
 #include "dma.h"
 
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 6ac7b8281a02..40b00a13dcd1 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -20,7 +20,7 @@
 #include <sound/soc.h>
 #include <sound/pcm_params.h>
 
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 
 #include "dma.h"
 #include "idma.h"
diff --git a/sound/soc/samsung/pcm.c b/sound/soc/samsung/pcm.c
index 89b064650f14..c86081992dfd 100644
--- a/sound/soc/samsung/pcm.c
+++ b/sound/soc/samsung/pcm.c
@@ -19,7 +19,7 @@
 #include <sound/soc.h>
 #include <sound/pcm_params.h>
 
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <mach/dma.h>
 
 #include "dma.h"
diff --git a/sound/soc/samsung/s3c24xx_simtec.c b/sound/soc/samsung/s3c24xx_simtec.c
index 656d5afe4ca9..335a7d8a4a8d 100644
--- a/sound/soc/samsung/s3c24xx_simtec.c
+++ b/sound/soc/samsung/s3c24xx_simtec.c
@@ -13,7 +13,7 @@
 
 #include <sound/soc.h>
 
-#include <plat/audio-simtec.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
 
 #include "s3c24xx-i2s.h"
 #include "s3c24xx_simtec.h"
diff --git a/sound/soc/samsung/spdif.c b/sound/soc/samsung/spdif.c
index a5a56a120345..bc24c7af02b2 100644
--- a/sound/soc/samsung/spdif.c
+++ b/sound/soc/samsung/spdif.c
@@ -17,7 +17,7 @@
 #include <sound/soc.h>
 #include <sound/pcm_params.h>
 
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <mach/dma.h>
 
 #include "dma.h"
diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
index 02bcd308c189..19e5fe7cc403 100644
--- a/sound/soc/tegra/Kconfig
+++ b/sound/soc/tegra/Kconfig
@@ -1,6 +1,6 @@
 config SND_SOC_TEGRA
         tristate "SoC Audio for the Tegra System-on-Chip"
-        depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA)
+        depends on ARCH_TEGRA && TEGRA20_APB_DMA
         select REGMAP_MMIO
         select SND_SOC_DMAENGINE_PCM if TEGRA20_APB_DMA
         help
diff --git a/sound/soc/tegra/tegra_pcm.c b/sound/soc/tegra/tegra_pcm.c
index 8d6900c1ee47..e18733963cb4 100644
--- a/sound/soc/tegra/tegra_pcm.c
+++ b/sound/soc/tegra/tegra_pcm.c
@@ -57,237 +57,6 @@ static const struct snd_pcm_hardware tegra_pcm_hardware = {
         .fifo_size              = 4,
 };
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static void tegra_pcm_queue_dma(struct tegra_runtime_data *prtd)
-{
-        struct snd_pcm_substream *substream = prtd->substream;
-        struct snd_dma_buffer *buf = &substream->dma_buffer;
-        struct tegra_dma_req *dma_req;
-        unsigned long addr;
-
-        dma_req = &prtd->dma_req[prtd->dma_req_idx];
-        prtd->dma_req_idx = 1 - prtd->dma_req_idx;
-
-        addr = buf->addr + prtd->dma_pos;
-        prtd->dma_pos += dma_req->size;
-        if (prtd->dma_pos >= prtd->dma_pos_end)
-                prtd->dma_pos = 0;
-
-        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-                dma_req->source_addr = addr;
-        else
-                dma_req->dest_addr = addr;
-
-        tegra_dma_enqueue_req(prtd->dma_chan, dma_req);
-}
-
-static void dma_complete_callback(struct tegra_dma_req *req)
-{
-        struct tegra_runtime_data *prtd = (struct tegra_runtime_data *)req->dev;
-        struct snd_pcm_substream *substream = prtd->substream;
-        struct snd_pcm_runtime *runtime = substream->runtime;
-
-        spin_lock(&prtd->lock);
-
-        if (!prtd->running) {
-                spin_unlock(&prtd->lock);
-                return;
-        }
-
-        if (++prtd->period_index >= runtime->periods)
-                prtd->period_index = 0;
-
-        tegra_pcm_queue_dma(prtd);
-
-        spin_unlock(&prtd->lock);
-
-        snd_pcm_period_elapsed(substream);
-}
-
-static void setup_dma_tx_request(struct tegra_dma_req *req,
-                                        struct tegra_pcm_dma_params * dmap)
-{
-        req->complete = dma_complete_callback;
-        req->to_memory = false;
-        req->dest_addr = dmap->addr;
-        req->dest_wrap = dmap->wrap;
-        req->source_bus_width = 32;
-        req->source_wrap = 0;
-        req->dest_bus_width = dmap->width;
-        req->req_sel = dmap->req_sel;
-}
-
-static void setup_dma_rx_request(struct tegra_dma_req *req,
-                                        struct tegra_pcm_dma_params * dmap)
-{
-        req->complete = dma_complete_callback;
-        req->to_memory = true;
-        req->source_addr = dmap->addr;
-        req->dest_wrap = 0;
-        req->source_bus_width = dmap->width;
-        req->source_wrap = dmap->wrap;
-        req->dest_bus_width = 32;
-        req->req_sel = dmap->req_sel;
-}
-
-static int tegra_pcm_open(struct snd_pcm_substream *substream)
-{
-        struct snd_pcm_runtime *runtime = substream->runtime;
-        struct tegra_runtime_data *prtd;
-        struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct tegra_pcm_dma_params * dmap;
-        int ret = 0;
-
-        prtd = kzalloc(sizeof(struct tegra_runtime_data), GFP_KERNEL);
-        if (prtd == NULL)
-                return -ENOMEM;
-
-        runtime->private_data = prtd;
-        prtd->substream = substream;
-
-        spin_lock_init(&prtd->lock);
-
-        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-                dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-                setup_dma_tx_request(&prtd->dma_req[0], dmap);
-                setup_dma_tx_request(&prtd->dma_req[1], dmap);
-        } else {
-                dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-                setup_dma_rx_request(&prtd->dma_req[0], dmap);
-                setup_dma_rx_request(&prtd->dma_req[1], dmap);
-        }
-
-        prtd->dma_req[0].dev = prtd;
-        prtd->dma_req[1].dev = prtd;
-
-        prtd->dma_chan = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
-        if (prtd->dma_chan == NULL) {
-                ret = -ENOMEM;
-                goto err;
-        }
-
-        /* Set HW params now that initialization is complete */
-        snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);
-
-        /* Ensure that buffer size is a multiple of period size */
-        ret = snd_pcm_hw_constraint_integer(runtime,
-                                                SNDRV_PCM_HW_PARAM_PERIODS);
-        if (ret < 0)
-                goto err;
-
-        return 0;
-
-err:
-        if (prtd->dma_chan) {
-                tegra_dma_free_channel(prtd->dma_chan);
-        }
-
-        kfree(prtd);
-
-        return ret;
-}
-
-static int tegra_pcm_close(struct snd_pcm_substream *substream)
-{
-        struct snd_pcm_runtime *runtime = substream->runtime;
-        struct tegra_runtime_data *prtd = runtime->private_data;
-
-        tegra_dma_free_channel(prtd->dma_chan);
-
-        kfree(prtd);
-
-        return 0;
-}
-
-static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
-                                struct snd_pcm_hw_params *params)
-{
-        struct snd_pcm_runtime *runtime = substream->runtime;
-        struct tegra_runtime_data *prtd = runtime->private_data;
-
-        snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
-
-        prtd->dma_req[0].size = params_period_bytes(params);
-        prtd->dma_req[1].size = prtd->dma_req[0].size;
-
-        return 0;
-}
-
-static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
-{
-        snd_pcm_set_runtime_buffer(substream, NULL);
-
-        return 0;
-}
-
-static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
-{
-        struct snd_pcm_runtime *runtime = substream->runtime;
-        struct tegra_runtime_data *prtd = runtime->private_data;
-        unsigned long flags;
-
-        switch (cmd) {
-        case SNDRV_PCM_TRIGGER_START:
-                prtd->dma_pos = 0;
-                prtd->dma_pos_end = frames_to_bytes(runtime, runtime->periods * runtime->period_size);
-                prtd->period_index = 0;
-                prtd->dma_req_idx = 0;
-                /* Fall-through */
-        case SNDRV_PCM_TRIGGER_RESUME:
-        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-                spin_lock_irqsave(&prtd->lock, flags);
-                prtd->running = 1;
-                spin_unlock_irqrestore(&prtd->lock, flags);
-                tegra_pcm_queue_dma(prtd);
-                tegra_pcm_queue_dma(prtd);
-                break;
-        case SNDRV_PCM_TRIGGER_STOP:
-        case SNDRV_PCM_TRIGGER_SUSPEND:
-        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-                spin_lock_irqsave(&prtd->lock, flags);
-                prtd->running = 0;
-                spin_unlock_irqrestore(&prtd->lock, flags);
-                tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[0]);
-                tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[1]);
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static snd_pcm_uframes_t tegra_pcm_pointer(struct snd_pcm_substream *substream)
-{
-        struct snd_pcm_runtime *runtime = substream->runtime;
-        struct tegra_runtime_data *prtd = runtime->private_data;
-
-        return prtd->period_index * runtime->period_size;
-}
-
-
-static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
-                                struct vm_area_struct *vma)
-{
-        struct snd_pcm_runtime *runtime = substream->runtime;
-
-        return dma_mmap_writecombine(substream->pcm->card->dev, vma,
-                                        runtime->dma_area,
-                                        runtime->dma_addr,
-                                        runtime->dma_bytes);
-}
-
-static struct snd_pcm_ops tegra_pcm_ops = {
-        .open           = tegra_pcm_open,
-        .close          = tegra_pcm_close,
-        .ioctl          = snd_pcm_lib_ioctl,
-        .hw_params      = tegra_pcm_hw_params,
-        .hw_free        = tegra_pcm_hw_free,
-        .trigger        = tegra_pcm_trigger,
-        .pointer        = tegra_pcm_pointer,
-        .mmap           = tegra_pcm_mmap,
-};
-#else
 static int tegra_pcm_open(struct snd_pcm_substream *substream)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
@@ -399,7 +168,6 @@ static struct snd_pcm_ops tegra_pcm_ops = {
         .pointer        = snd_dmaengine_pcm_pointer,
         .mmap           = tegra_pcm_mmap,
 };
-#endif
 
 static int tegra_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
 {
diff --git a/sound/soc/tegra/tegra_pcm.h b/sound/soc/tegra/tegra_pcm.h
index a3a450352dcf..b40279b9f413 100644
--- a/sound/soc/tegra/tegra_pcm.h
+++ b/sound/soc/tegra/tegra_pcm.h
@@ -40,20 +40,6 @@ struct tegra_pcm_dma_params {
         unsigned long req_sel;
 };
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-struct tegra_runtime_data {
-        struct snd_pcm_substream *substream;
-        spinlock_t lock;
-        int running;
-        int dma_pos;
-        int dma_pos_end;
-        int period_index;
-        int dma_req_idx;
-        struct tegra_dma_req dma_req[2];
-        struct tegra_dma_channel *dma_chan;
-};
-#endif
-
 int tegra_pcm_platform_register(struct device *dev);
 void tegra_pcm_platform_unregister(struct device *dev);