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authorJayachandran C <jchandra@broadcom.com>2015-01-07 06:28:28 -0500
committerRalf Baechle <ralf@linux-mips.org>2015-04-01 11:21:49 -0400
commit53f676977dddaa6784dab7b058cfe8895e3c8772 (patch)
tree8f49568829fe71a39db9f0ee81555d22644ec3da
parenta3613be442aaf435d7d3b224c81cea0b0f702d6a (diff)
MIPS: MSI: Update MSI handling for XLP
The per-cpu interrupt ACK using EIRR has to be done just once after all the bits in the status register are processed. PIC ack has to be done once in case of MSI, and for every interrupt in case of MSI-X Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8887/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/pci/msi-xlp.c19
1 files changed, 10 insertions, 9 deletions
diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
index 6a40f24c91b4..3407495fcbe2 100644
--- a/arch/mips/pci/msi-xlp.c
+++ b/arch/mips/pci/msi-xlp.c
@@ -178,13 +178,6 @@ static void xlp_msi_mask_ack(struct irq_data *d)
178 else 178 else
179 nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec); 179 nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
180 180
181 /* Ack at eirr and PIC */
182 ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
183 if (cpu_is_xlp9xx())
184 nlm_pic_ack(md->node->picbase,
185 PIC_9XX_IRT_PCIE_LINK_INDEX(link));
186 else
187 nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
188} 181}
189 182
190static struct irq_chip xlp_msi_chip = { 183static struct irq_chip xlp_msi_chip = {
@@ -230,8 +223,6 @@ static void xlp_msix_mask_ack(struct irq_data *d)
230 } 223 }
231 nlm_write_reg(md->lnkbase, status_reg, 1u << bit); 224 nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
232 225
233 /* Ack at eirr and PIC */
234 ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
235 if (!cpu_is_xlp9xx()) 226 if (!cpu_is_xlp9xx())
236 nlm_pic_ack(md->node->picbase, 227 nlm_pic_ack(md->node->picbase,
237 PIC_IRT_PCIE_MSIX_INDEX(msixvec)); 228 PIC_IRT_PCIE_MSIX_INDEX(msixvec));
@@ -541,6 +532,14 @@ void nlm_dispatch_msi(int node, int lirq)
541 do_IRQ(irqbase + i); 532 do_IRQ(irqbase + i);
542 status &= status - 1; 533 status &= status - 1;
543 } 534 }
535
536 /* Ack at eirr and PIC */
537 ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
538 if (cpu_is_xlp9xx())
539 nlm_pic_ack(md->node->picbase,
540 PIC_9XX_IRT_PCIE_LINK_INDEX(link));
541 else
542 nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
544} 543}
545 544
546void nlm_dispatch_msix(int node, int lirq) 545void nlm_dispatch_msix(int node, int lirq)
@@ -567,4 +566,6 @@ void nlm_dispatch_msix(int node, int lirq)
567 do_IRQ(irqbase + i); 566 do_IRQ(irqbase + i);
568 status &= status - 1; 567 status &= status - 1;
569 } 568 }
569 /* Ack at eirr and PIC */
570 ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
570} 571}