drm/i915: Set i9xx lvds clock limits according to specifications

The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 593c66801d56..aa31b96e5301 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -168,8 +168,8 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
         .vco = { .min = 1400000, .max = 2800000 },
         .n = { .min = 1, .max = 6 },
         .m = { .min = 70, .max = 120 },
-        .m1 = { .min = 10, .max = 22 },
-        .m2 = { .min = 5, .max = 9 },
+        .m1 = { .min = 8, .max = 18 },
+        .m2 = { .min = 3, .max = 7 },
         .p = { .min = 7, .max = 98 },
         .p1 = { .min = 1, .max = 8 },
         .p2 = { .dot_limit = 112000,