Merge branch 'linux-3.18' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

This is the main merge request for Nouveau 3.18, overview:
- various bits of roy's gt21x clock work
- various bits of kepler memory clock work (don't get too excited, there's at least one more major bit left that's busting higher freqs)
- misc fan control improvements
- kepler hdmi infoframe fixes
- dp audio
- l2 cache + cbc improvements

* 'linux-3.18' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (68 commits)
  drm/gt214-/disp: enable dp audio
  drm/gt214-/kms: fix hda eld regression
  drm/g94-/disp: calculate some dp audio constants
  drm/gt214-/kms: perform hda codec setup on displayport too
  drm/gk104-/disp: infoframe registers moved yet again on kepler
  drm/nouveau/bios: parse older ramcfg/timing data like we do newer ones
  drm/nva3/fb/ram: Per-partition regs
  drm/nouveau/fb/ram: Support strided regs
  drm/nv50/fb/ram: Store the number of partitions in the designated fields
  drm/nv50/kms: Set VBLANK time in modeset script
  drm/nouveau/bios: Add rammap support for version 1.0
  drm/gf100-/pwr/memx: block host and fifo around reclock
  drm/nouveau/pwr/memx: fix command ordering around block/unblock
  drm/nouveau/pwr/memx: rename fb off/on to block/unblock
  drm/nva3/clk: Pause the GPU before reclocking
  drm/nouveau/gpio: rename g92 class to g94
  drm/gk104-/fb/ram: move fb enable/disable to same place as nvidia
  drm/gk104/fb/ram: twiddle some more bits when reclocking
  drm/nouveau/bios: parse another large chunk of random memory config data
  drm/gk104-/fb/ram: perform certain steps only when bios data differs
  ...

130 files changed, 5638 insertions, 2464 deletions

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index f5d7f7ce4bc6..12c24c8abf7f 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -38,6 +38,7 @@ nouveau-y += core/subdev/bios/dcb.o
 nouveau-y += core/subdev/bios/disp.o
 nouveau-y += core/subdev/bios/dp.o
 nouveau-y += core/subdev/bios/extdev.o
+nouveau-y += core/subdev/bios/fan.o
 nouveau-y += core/subdev/bios/gpio.o
 nouveau-y += core/subdev/bios/i2c.o
 nouveau-y += core/subdev/bios/init.o
@@ -51,6 +52,8 @@ nouveau-y += core/subdev/bios/therm.o
 nouveau-y += core/subdev/bios/vmap.o
 nouveau-y += core/subdev/bios/volt.o
 nouveau-y += core/subdev/bios/xpio.o
+nouveau-y += core/subdev/bios/M0205.o
+nouveau-y += core/subdev/bios/M0209.o
 nouveau-y += core/subdev/bios/P0260.o
 nouveau-y += core/subdev/bus/hwsq.o
 nouveau-y += core/subdev/bus/nv04.o
@@ -124,12 +127,17 @@ nouveau-y += core/subdev/fb/ramnvc0.o
 nouveau-y += core/subdev/fb/ramnve0.o
 nouveau-y += core/subdev/fb/ramgk20a.o
 nouveau-y += core/subdev/fb/ramgm107.o
+nouveau-y += core/subdev/fb/sddr2.o
 nouveau-y += core/subdev/fb/sddr3.o
 nouveau-y += core/subdev/fb/gddr5.o
+nouveau-y += core/subdev/fuse/base.o
+nouveau-y += core/subdev/fuse/g80.o
+nouveau-y += core/subdev/fuse/gf100.o
+nouveau-y += core/subdev/fuse/gm107.o
 nouveau-y += core/subdev/gpio/base.o
 nouveau-y += core/subdev/gpio/nv10.o
 nouveau-y += core/subdev/gpio/nv50.o
-nouveau-y += core/subdev/gpio/nv92.o
+nouveau-y += core/subdev/gpio/nv94.o
 nouveau-y += core/subdev/gpio/nvd0.o
 nouveau-y += core/subdev/gpio/nve0.o
 nouveau-y += core/subdev/i2c/base.o
@@ -190,6 +198,7 @@ nouveau-y += core/subdev/therm/nv50.o
 nouveau-y += core/subdev/therm/nv84.o
 nouveau-y += core/subdev/therm/nva3.o
 nouveau-y += core/subdev/therm/nvd0.o
+nouveau-y += core/subdev/therm/gm107.o
 nouveau-y += core/subdev/timer/base.o
 nouveau-y += core/subdev/timer/nv04.o
 nouveau-y += core/subdev/timer/gk20a.o
@@ -252,6 +261,7 @@ nouveau-y += core/engine/disp/hdanvd0.o
 nouveau-y += core/engine/disp/hdminv84.o
 nouveau-y += core/engine/disp/hdminva3.o
 nouveau-y += core/engine/disp/hdminvd0.o
+nouveau-y += core/engine/disp/hdminve0.o
 nouveau-y += core/engine/disp/piornv50.o
 nouveau-y += core/engine/disp/sornv50.o
 nouveau-y += core/engine/disp/sornv94.o
diff --git a/drivers/gpu/drm/nouveau/core/core/client.c b/drivers/gpu/drm/nouveau/core/core/client.c
index 68bf06768123..e962433294c3 100644
--- a/drivers/gpu/drm/nouveau/core/core/client.c
+++ b/drivers/gpu/drm/nouveau/core/core/client.c
@@ -91,9 +91,10 @@ nvkm_client_notify_del(struct nouveau_client *client, int index)
 }
 
 int
-nvkm_client_notify_new(struct nouveau_client *client,
+nvkm_client_notify_new(struct nouveau_object *object,
                        struct nvkm_event *event, void *data, u32 size)
 {
+        struct nouveau_client *client = nouveau_client(object);
         struct nvkm_client_notify *notify;
         union {
                 struct nvif_notify_req_v0 v0;
@@ -127,8 +128,8 @@ nvkm_client_notify_new(struct nouveau_client *client,
         }
 
         if (ret == 0) {
-                ret = nvkm_notify_init(event, nvkm_client_notify, false,
-                                       data, size, reply, &notify->n);
+                ret = nvkm_notify_init(object, event, nvkm_client_notify,
+                                       false, data, size, reply, &notify->n);
                 if (ret == 0) {
                         client->notify[index] = notify;
                         notify->client = client;
diff --git a/drivers/gpu/drm/nouveau/core/core/event.c b/drivers/gpu/drm/nouveau/core/core/event.c
index 0540a48c5678..ff2b434b3db4 100644
--- a/drivers/gpu/drm/nouveau/core/core/event.c
+++ b/drivers/gpu/drm/nouveau/core/core/event.c
@@ -20,7 +20,7 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <core/os.h>
+#include <core/object.h>
 #include <core/event.h>
 
 void
diff --git a/drivers/gpu/drm/nouveau/core/core/gpuobj.c b/drivers/gpu/drm/nouveau/core/core/gpuobj.c
index 560b2214cf1c..daee87702502 100644
--- a/drivers/gpu/drm/nouveau/core/core/gpuobj.c
+++ b/drivers/gpu/drm/nouveau/core/core/gpuobj.c
@@ -115,7 +115,7 @@ nouveau_gpuobj_create_(struct nouveau_object *parent,
         gpuobj->size = size;
 
         if (heap) {
-                ret = nouveau_mm_head(heap, 1, size, size,
+                ret = nouveau_mm_head(heap, 0, 1, size, size,
                                       max(align, (u32)1), &gpuobj->node);
                 if (ret)
                         return ret;
diff --git a/drivers/gpu/drm/nouveau/core/core/ioctl.c b/drivers/gpu/drm/nouveau/core/core/ioctl.c
index f7e19bfb489c..692aa92dd850 100644
--- a/drivers/gpu/drm/nouveau/core/core/ioctl.c
+++ b/drivers/gpu/drm/nouveau/core/core/ioctl.c
@@ -349,7 +349,6 @@ nvkm_ioctl_unmap(struct nouveau_handle *handle, void *data, u32 size)
 static int
 nvkm_ioctl_ntfy_new(struct nouveau_handle *handle, void *data, u32 size)
 {
-        struct nouveau_client *client = nouveau_client(handle->object);
         struct nouveau_object *object = handle->object;
         struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
         union {
@@ -365,7 +364,7 @@ nvkm_ioctl_ntfy_new(struct nouveau_handle *handle, void *data, u32 size)
                 if (ret = -ENODEV, ofuncs->ntfy)
                         ret = ofuncs->ntfy(object, args->v0.event, &event);
                 if (ret == 0) {
-                        ret = nvkm_client_notify_new(client, event, data, size);
+                        ret = nvkm_client_notify_new(object, event, data, size);
                         if (ret >= 0) {
                                 args->v0.index = ret;
                                 ret = 0;
diff --git a/drivers/gpu/drm/nouveau/core/core/mm.c b/drivers/gpu/drm/nouveau/core/core/mm.c
index 7a4e0891c5f8..b4f5db66d5b5 100644
--- a/drivers/gpu/drm/nouveau/core/core/mm.c
+++ b/drivers/gpu/drm/nouveau/core/core/mm.c
@@ -28,6 +28,24 @@
 #define node(root, dir) ((root)->nl_entry.dir == &mm->nodes) ? NULL : \
         list_entry((root)->nl_entry.dir, struct nouveau_mm_node, nl_entry)
 
+static void
+nouveau_mm_dump(struct nouveau_mm *mm, const char *header)
+{
+        struct nouveau_mm_node *node;
+
+        printk(KERN_ERR "nouveau: %s\n", header);
+        printk(KERN_ERR "nouveau: node list:\n");
+        list_for_each_entry(node, &mm->nodes, nl_entry) {
+                printk(KERN_ERR "nouveau: \t%08x %08x %d\n",
+                       node->offset, node->length, node->type);
+        }
+        printk(KERN_ERR "nouveau: free list:\n");
+        list_for_each_entry(node, &mm->free, fl_entry) {
+                printk(KERN_ERR "nouveau: \t%08x %08x %d\n",
+                       node->offset, node->length, node->type);
+        }
+}
+
 void
 nouveau_mm_free(struct nouveau_mm *mm, struct nouveau_mm_node **pthis)
 {
@@ -37,29 +55,29 @@ nouveau_mm_free(struct nouveau_mm *mm, struct nouveau_mm_node **pthis)
                 struct nouveau_mm_node *prev = node(this, prev);
                 struct nouveau_mm_node *next = node(this, next);
 
-                if (prev && prev->type == 0) {
+                if (prev && prev->type == NVKM_MM_TYPE_NONE) {
                         prev->length += this->length;
                         list_del(&this->nl_entry);
                         kfree(this); this = prev;
                 }
 
-                if (next && next->type == 0) {
+                if (next && next->type == NVKM_MM_TYPE_NONE) {
                         next->offset  = this->offset;
                         next->length += this->length;
-                        if (this->type == 0)
+                        if (this->type == NVKM_MM_TYPE_NONE)
                                 list_del(&this->fl_entry);
                         list_del(&this->nl_entry);
                         kfree(this); this = NULL;
                 }
 
-                if (this && this->type != 0) {
+                if (this && this->type != NVKM_MM_TYPE_NONE) {
                         list_for_each_entry(prev, &mm->free, fl_entry) {
                                 if (this->offset < prev->offset)
                                         break;
                         }
 
                         list_add_tail(&this->fl_entry, &prev->fl_entry);
-                        this->type = 0;
+                        this->type = NVKM_MM_TYPE_NONE;
                 }
         }
 
@@ -80,27 +98,32 @@ region_head(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size)
 
         b->offset = a->offset;
         b->length = size;
+        b->heap   = a->heap;
         b->type   = a->type;
         a->offset += size;
         a->length -= size;
         list_add_tail(&b->nl_entry, &a->nl_entry);
-        if (b->type == 0)
+        if (b->type == NVKM_MM_TYPE_NONE)
                 list_add_tail(&b->fl_entry, &a->fl_entry);
         return b;
 }
 
 int
-nouveau_mm_head(struct nouveau_mm *mm, u8 type, u32 size_max, u32 size_min,
-                u32 align, struct nouveau_mm_node **pnode)
+nouveau_mm_head(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max,
+                u32 size_min, u32 align, struct nouveau_mm_node **pnode)
 {
         struct nouveau_mm_node *prev, *this, *next;
         u32 mask = align - 1;
         u32 splitoff;
         u32 s, e;
 
-        BUG_ON(!type);
+        BUG_ON(type == NVKM_MM_TYPE_NONE || type == NVKM_MM_TYPE_HOLE);
 
         list_for_each_entry(this, &mm->free, fl_entry) {
+                if (unlikely(heap != NVKM_MM_HEAP_ANY)) {
+                        if (this->heap != heap)
+                                continue;
+                }
                 e = this->offset + this->length;
                 s = this->offset;
 
@@ -149,27 +172,32 @@ region_tail(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size)
         a->length -= size;
         b->offset  = a->offset + a->length;
         b->length  = size;
+        b->heap    = a->heap;
         b->type    = a->type;
 
         list_add(&b->nl_entry, &a->nl_entry);
-        if (b->type == 0)
+        if (b->type == NVKM_MM_TYPE_NONE)
                 list_add(&b->fl_entry, &a->fl_entry);
         return b;
 }
 
 int
-nouveau_mm_tail(struct nouveau_mm *mm, u8 type, u32 size_max, u32 size_min,
-                u32 align, struct nouveau_mm_node **pnode)
+nouveau_mm_tail(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max,
+                u32 size_min, u32 align, struct nouveau_mm_node **pnode)
 {
         struct nouveau_mm_node *prev, *this, *next;
         u32 mask = align - 1;
 
-        BUG_ON(!type);
+        BUG_ON(type == NVKM_MM_TYPE_NONE || type == NVKM_MM_TYPE_HOLE);
 
         list_for_each_entry_reverse(this, &mm->free, fl_entry) {
                 u32 e = this->offset + this->length;
                 u32 s = this->offset;
                 u32 c = 0, a;
+                if (unlikely(heap != NVKM_MM_HEAP_ANY)) {
+                        if (this->heap != heap)
+                                continue;
+                }
 
                 prev = node(this, prev);
                 if (prev && prev->type != type)
@@ -209,9 +237,23 @@ nouveau_mm_tail(struct nouveau_mm *mm, u8 type, u32 size_max, u32 size_min,
 int
 nouveau_mm_init(struct nouveau_mm *mm, u32 offset, u32 length, u32 block)
 {
-        struct nouveau_mm_node *node;
+        struct nouveau_mm_node *node, *prev;
+        u32 next;
 
-        if (block) {
+        if (nouveau_mm_initialised(mm)) {
+                prev = list_last_entry(&mm->nodes, typeof(*node), nl_entry);
+                next = prev->offset + prev->length;
+                if (next != offset) {
+                        BUG_ON(next > offset);
+                        if (!(node = kzalloc(sizeof(*node), GFP_KERNEL)))
+                                return -ENOMEM;
+                        node->type   = NVKM_MM_TYPE_HOLE;
+                        node->offset = next;
+                        node->length = offset - next;
+                        list_add_tail(&node->nl_entry, &mm->nodes);
+                }
+                BUG_ON(block != mm->block_size);
+        } else {
                 INIT_LIST_HEAD(&mm->nodes);
                 INIT_LIST_HEAD(&mm->free);
                 mm->block_size = block;
@@ -230,25 +272,32 @@ nouveau_mm_init(struct nouveau_mm *mm, u32 offset, u32 length, u32 block)
 
         list_add_tail(&node->nl_entry, &mm->nodes);
         list_add_tail(&node->fl_entry, &mm->free);
-        mm->heap_nodes++;
+        node->heap = ++mm->heap_nodes;
         return 0;
 }
 
 int
 nouveau_mm_fini(struct nouveau_mm *mm)
 {
-        if (nouveau_mm_initialised(mm)) {
-                struct nouveau_mm_node *node, *heap =
-                        list_first_entry(&mm->nodes, typeof(*heap), nl_entry);
-                int nodes = 0;
+        struct nouveau_mm_node *node, *temp;
+        int nodes = 0;
 
-                list_for_each_entry(node, &mm->nodes, nl_entry) {
-                        if (WARN_ON(nodes++ == mm->heap_nodes))
+        if (!nouveau_mm_initialised(mm))
+                return 0;
+
+        list_for_each_entry(node, &mm->nodes, nl_entry) {
+                if (node->type != NVKM_MM_TYPE_HOLE) {
+                        if (++nodes > mm->heap_nodes) {
+                                nouveau_mm_dump(mm, "mm not clean!");
                                 return -EBUSY;
+                        }
                 }
-
-                kfree(heap);
         }
 
+        list_for_each_entry_safe(node, temp, &mm->nodes, nl_entry) {
+                list_del(&node->nl_entry);
+                kfree(node);
+        }
+        mm->heap_nodes = 0;
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/core/notify.c b/drivers/gpu/drm/nouveau/core/core/notify.c
index 76adb81bdea2..d1bcde55e9d7 100644
--- a/drivers/gpu/drm/nouveau/core/core/notify.c
+++ b/drivers/gpu/drm/nouveau/core/core/notify.c
@@ -134,14 +134,15 @@ nvkm_notify_fini(struct nvkm_notify *notify)
 }
 
 int
-nvkm_notify_init(struct nvkm_event *event, int (*func)(struct nvkm_notify *),
-                 bool work, void *data, u32 size, u32 reply,
+nvkm_notify_init(struct nouveau_object *object, struct nvkm_event *event,
+                 int (*func)(struct nvkm_notify *), bool work,
+                 void *data, u32 size, u32 reply,
                  struct nvkm_notify *notify)
 {
         unsigned long flags;
         int ret = -ENODEV;
         if ((notify->event = event), event->refs) {
-                ret = event->func->ctor(data, size, notify);
+                ret = event->func->ctor(object, data, size, notify);
                 if (ret == 0 && (ret = -EINVAL, notify->size == reply)) {
                         notify->flags = 0;
                         notify->block = 1;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index 8928f7981d4a..0ef5a5713182 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -505,7 +505,8 @@ nouveau_device_sclass[] = {
 };
 
 static int
-nouveau_device_event_ctor(void *data, u32 size, struct nvkm_notify *notify)
+nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size,
+                          struct nvkm_notify *notify)
 {
         if (!WARN_ON(size != 0)) {
                 notify->size  = 0;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c b/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
index 377ec0b8851e..6295668e29a5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
@@ -26,6 +26,7 @@
 #include <subdev/bus.h>
 #include <subdev/gpio.h>
 #include <subdev/i2c.h>
+#include <subdev/fuse.h>
 #include <subdev/clock.h>
 #include <subdev/therm.h>
 #include <subdev/mxm.h>
@@ -62,10 +63,9 @@ gm100_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
-#if 0
-                device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
-#endif
+                device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                 device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm107_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
@@ -77,8 +77,9 @@ gm100_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-#if 0
                 device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;
+
+#if 0
                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 #endif
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
index 932f84fae459..96f568d1321b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
@@ -26,6 +26,7 @@
 #include <subdev/bus.h>
 #include <subdev/gpio.h>
 #include <subdev/i2c.h>
+#include <subdev/fuse.h>
 #include <subdev/clock.h>
 #include <subdev/therm.h>
 #include <subdev/mxm.h>
@@ -62,6 +63,7 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv50_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -87,6 +89,7 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -115,6 +118,7 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -141,8 +145,9 @@ nv50_identify(struct nouveau_device *device)
         case 0x92:
                 device->cname = "G92";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -169,8 +174,9 @@ nv50_identify(struct nouveau_device *device)
         case 0x94:
                 device->cname = "G94";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -197,8 +203,9 @@ nv50_identify(struct nouveau_device *device)
         case 0x96:
                 device->cname = "G96";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -225,8 +232,9 @@ nv50_identify(struct nouveau_device *device)
         case 0x98:
                 device->cname = "G98";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -253,8 +261,9 @@ nv50_identify(struct nouveau_device *device)
         case 0xa0:
                 device->cname = "G200";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -281,8 +290,9 @@ nv50_identify(struct nouveau_device *device)
         case 0xaa:
                 device->cname = "MCP77/MCP78";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nvaa_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -309,8 +319,9 @@ nv50_identify(struct nouveau_device *device)
         case 0xac:
                 device->cname = "MCP79/MCP7A";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nvaa_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -337,8 +348,9 @@ nv50_identify(struct nouveau_device *device)
         case 0xa3:
                 device->cname = "GT215";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -367,8 +379,9 @@ nv50_identify(struct nouveau_device *device)
         case 0xa5:
                 device->cname = "GT216";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -396,8 +409,9 @@ nv50_identify(struct nouveau_device *device)
         case 0xa8:
                 device->cname = "GT218";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -425,8 +439,9 @@ nv50_identify(struct nouveau_device *device)
         case 0xaf:
                 device->cname = "MCP89";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] =  &g80_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index b4a2917ce555..cd05677ad4b7 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -26,6 +26,7 @@
 #include <subdev/bus.h>
 #include <subdev/gpio.h>
 #include <subdev/i2c.h>
+#include <subdev/fuse.h>
 #include <subdev/clock.h>
 #include <subdev/therm.h>
 #include <subdev/mxm.h>
@@ -60,8 +61,9 @@ nvc0_identify(struct nouveau_device *device)
         case 0xc0:
                 device->cname = "GF100";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -92,8 +94,9 @@ nvc0_identify(struct nouveau_device *device)
         case 0xc4:
                 device->cname = "GF104";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -124,8 +127,9 @@ nvc0_identify(struct nouveau_device *device)
         case 0xc3:
                 device->cname = "GF106";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -155,8 +159,9 @@ nvc0_identify(struct nouveau_device *device)
         case 0xce:
                 device->cname = "GF114";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -187,8 +192,9 @@ nvc0_identify(struct nouveau_device *device)
         case 0xcf:
                 device->cname = "GF116";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -219,8 +225,9 @@ nvc0_identify(struct nouveau_device *device)
         case 0xc1:
                 device->cname = "GF108";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -250,8 +257,9 @@ nvc0_identify(struct nouveau_device *device)
         case 0xc8:
                 device->cname = "GF110";
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
-                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv92_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv94_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nv94_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -284,6 +292,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nvd0_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -315,6 +324,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nvd0_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  gf117_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index cdf9147f32a1..b1b2e484ecfa 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -26,6 +26,7 @@
 #include <subdev/bus.h>
 #include <subdev/gpio.h>
 #include <subdev/i2c.h>
+#include <subdev/fuse.h>
 #include <subdev/clock.h>
 #include <subdev/therm.h>
 #include <subdev/mxm.h>
@@ -62,6 +63,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -95,6 +97,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -128,6 +131,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -161,6 +165,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &gk20a_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
                 device->oclass[NVDEV_SUBDEV_FB     ] =  gk20a_fb_oclass;
                 device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
@@ -180,6 +185,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -213,6 +219,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
@@ -246,6 +253,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
                 device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
                 device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/base.c b/drivers/gpu/drm/nouveau/core/engine/disp/base.c
index 22d55f6cde50..64b84667f3a5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/base.c
@@ -32,7 +32,8 @@
 #include "conn.h"
 
 int
-nouveau_disp_vblank_ctor(void *data, u32 size, struct nvkm_notify *notify)
+nouveau_disp_vblank_ctor(struct nouveau_object *object, void *data, u32 size,
+                         struct nvkm_notify *notify)
 {
         struct nouveau_disp *disp =
                 container_of(notify->event, typeof(*disp), vblank);
@@ -61,7 +62,8 @@ nouveau_disp_vblank(struct nouveau_disp *disp, int head)
 }
 
 static int
-nouveau_disp_hpd_ctor(void *data, u32 size, struct nvkm_notify *notify)
+nouveau_disp_hpd_ctor(struct nouveau_object *object, void *data, u32 size,
+                      struct nvkm_notify *notify)
 {
         struct nouveau_disp *disp =
                 container_of(notify->event, typeof(*disp), hpd);
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c b/drivers/gpu/drm/nouveau/core/engine/disp/conn.c
index 3d1070228977..1496b567dd4a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/conn.c
@@ -126,8 +126,8 @@ nvkm_connector_create_(struct nouveau_object *parent,
                         return 0;
                 }
 
-                ret = nvkm_notify_init(&gpio->event, nvkm_connector_hpd, true,
-                                       &(struct nvkm_gpio_ntfy_req) {
+                ret = nvkm_notify_init(NULL, &gpio->event, nvkm_connector_hpd,
+                                       true, &(struct nvkm_gpio_ntfy_req) {
                                         .mask = NVKM_GPIO_TOGGLED,
                                         .line = func.line,
                                        },
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
index d54da8b5f87e..b3df3fe2dc09 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
@@ -68,6 +68,10 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = gm107_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nvd0_disp_intr;
@@ -80,7 +84,7 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         priv->dac.sense = nv50_dac_sense;
         priv->sor.power = nv50_sor_power;
         priv->sor.hda_eld = nvd0_hda_eld;
-        priv->sor.hdmi = nvd0_hdmi_ctrl;
+        priv->sor.hdmi = nve0_hdmi_ctrl;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
index 8b4e06abe533..fe9ef5894dd4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
@@ -26,6 +26,8 @@
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 
+#include <subdev/timer.h>
+
 #include "nv50.h"
 
 int
@@ -46,16 +48,21 @@ nva3_hda_eld(NV50_DISP_MTHD_V1)
                 return ret;
 
         if (size && args->v0.data[0]) {
+                if (outp->info.type == DCB_OUTPUT_DP) {
+                        nv_mask(priv, 0x61c1e0 + soff, 0x8000000d, 0x80000001);
+                        nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000);
+                }
                 for (i = 0; i < size; i++)
                         nv_wr32(priv, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
                 for (; i < 0x60; i++)
                         nv_wr32(priv, 0x61c440 + soff, (i << 8));
                 nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000003);
-        } else
-        if (size) {
-                nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000001);
         } else {
-                nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000000);
+                if (outp->info.type == DCB_OUTPUT_DP) {
+                        nv_mask(priv, 0x61c1e0 + soff, 0x80000001, 0x80000000);
+                        nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000);
+                }
+                nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size);
         }
 
         return 0;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
index baf558fc12fb..1d4e8432d857 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
@@ -26,10 +26,7 @@
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
+#include <subdev/timer.h>
 
 #include "nv50.h"
 
@@ -40,6 +37,7 @@ nvd0_hda_eld(NV50_DISP_MTHD_V1)
                 struct nv50_disp_sor_hda_eld_v0 v0;
         } *args = data;
         const u32 soff = outp->or * 0x030;
+        const u32 hoff = head * 0x800;
         int ret, i;
 
         nv_ioctl(object, "disp sor hda eld size %d\n", size);
@@ -51,16 +49,22 @@ nvd0_hda_eld(NV50_DISP_MTHD_V1)
                 return ret;
 
         if (size && args->v0.data[0]) {
+                if (outp->info.type == DCB_OUTPUT_DP) {
+                        nv_mask(priv, 0x616618 + hoff, 0x8000000c, 0x80000001);
+                        nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000);
+                }
+                nv_mask(priv, 0x616548 + hoff, 0x00000070, 0x00000000);
                 for (i = 0; i < size; i++)
                         nv_wr32(priv, 0x10ec00 + soff, (i << 8) | args->v0.data[i]);
                 for (; i < 0x60; i++)
                         nv_wr32(priv, 0x10ec00 + soff, (i << 8));
                 nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000003);
-        } else
-        if (size) {
-                nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000001);
         } else {
-                nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000000);
+                if (outp->info.type == DCB_OUTPUT_DP) {
+                        nv_mask(priv, 0x616618 + hoff, 0x80000001, 0x80000000);
+                        nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000);
+                }
+                nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size);
         }
 
         return 0;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c
index 3106d295b48d..bac4fc4570f0 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c
@@ -75,8 +75,5 @@ nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1)
 
         /* HDMI_CTRL */
         nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl);
-
-        /* NFI, audio doesn't work without it though.. */
-        nv_mask(priv, 0x616548 + hoff, 0x00000070, 0x00000000);
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c
new file mode 100644
index 000000000000..528d14ec2f7f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2014 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <core/client.h>
+#include <nvif/unpack.h>
+#include <nvif/class.h>
+
+#include "nv50.h"
+
+int
+nve0_hdmi_ctrl(NV50_DISP_MTHD_V1)
+{
+        const u32 hoff = (head * 0x800);
+        const u32 hdmi = (head * 0x400);
+        union {
+                struct nv50_disp_sor_hdmi_pwr_v0 v0;
+        } *args = data;
+        u32 ctrl;
+        int ret;
+
+        nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size);
+        if (nvif_unpack(args->v0, 0, 0, false)) {
+                nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d "
+                                 "max_ac_packet %d rekey %d\n",
+                         args->v0.version, args->v0.state,
+                         args->v0.max_ac_packet, args->v0.rekey);
+                if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f)
+                        return -EINVAL;
+                ctrl  = 0x40000000 * !!args->v0.state;
+                ctrl |= args->v0.max_ac_packet << 16;
+                ctrl |= args->v0.rekey;
+        } else
+                return ret;
+
+        if (!(ctrl & 0x40000000)) {
+                nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000);
+                nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
+                nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000);
+                return 0;
+        }
+
+        /* AVI InfoFrame */
+        nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000);
+        nv_wr32(priv, 0x690008 + hdmi, 0x000d0282);
+        nv_wr32(priv, 0x69000c + hdmi, 0x0000006f);
+        nv_wr32(priv, 0x690010 + hdmi, 0x00000000);
+        nv_wr32(priv, 0x690014 + hdmi, 0x00000000);
+        nv_wr32(priv, 0x690018 + hdmi, 0x00000000);
+        nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000001);
+
+        /* ??? InfoFrame? */
+        nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
+        nv_wr32(priv, 0x6900cc + hdmi, 0x00000010);
+        nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000001);
+
+        /* ??? */
+        nv_wr32(priv, 0x690080 + hdmi, 0x82000000);
+
+        /* HDMI_CTRL */
+        nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl);
+        return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 4b5bb5d58a54..a7efbff4dc8f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -29,6 +29,7 @@
 #include <core/enum.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
+#include <nvif/event.h>
 
 #include <subdev/bios.h>
 #include <subdev/bios/dcb.h>
@@ -82,6 +83,71 @@ nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
         nouveau_namedb_destroy(&chan->base);
 }
 
+static void
+nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
+{
+        struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+        nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index);
+}
+
+static void
+nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
+{
+        struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+        nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index);
+}
+
+void
+nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid)
+{
+        struct nvif_notify_uevent_rep {
+        } rep;
+
+        nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep));
+}
+
+int
+nv50_disp_chan_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
+                           struct nvkm_notify *notify)
+{
+        struct nv50_disp_dmac *dmac = (void *)object;
+        union {
+                struct nvif_notify_uevent_req none;
+        } *args = data;
+        int ret;
+
+        if (nvif_unvers(args->none)) {
+                notify->size  = sizeof(struct nvif_notify_uevent_rep);
+                notify->types = 1;
+                notify->index = dmac->base.chid;
+                return 0;
+        }
+
+        return ret;
+}
+
+const struct nvkm_event_func
+nv50_disp_chan_uevent = {
+        .ctor = nv50_disp_chan_uevent_ctor,
+        .init = nv50_disp_chan_uevent_init,
+        .fini = nv50_disp_chan_uevent_fini,
+};
+
+int
+nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type,
+                    struct nvkm_event **pevent)
+{
+        struct nv50_disp_priv *priv = (void *)object->engine;
+        switch (type) {
+        case NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT:
+                *pevent = &priv->uevent;
+                return 0;
+        default:
+                break;
+        }
+        return -EINVAL;
+}
+
 int
 nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)
 {
@@ -195,7 +261,7 @@ nv50_disp_dmac_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid);
+        nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid);
 
         /* initialise channel for dma command submission */
         nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
@@ -232,7 +298,7 @@ nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notifications */
         nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
 
         return nv50_disp_chan_fini(&dmac->base, suspend);
@@ -454,7 +520,7 @@ nv50_disp_mast_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610028, 0x00010001, 0x00010001);
+        nv_mask(priv, 0x610028, 0x00010000, 0x00010000);
 
         /* attempt to unstick channel from some unknown state */
         if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
@@ -494,7 +560,7 @@ nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notifications */
         nv_mask(priv, 0x610028, 0x00010001, 0x00000000);
 
         return nv50_disp_chan_fini(&mast->base, suspend);
@@ -507,6 +573,7 @@ nv50_disp_mast_ofuncs = {
         .base.init = nv50_disp_mast_init,
         .base.fini = nv50_disp_mast_fini,
         .base.map  = nv50_disp_chan_map,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
         .chid = 0,
@@ -607,6 +674,7 @@ nv50_disp_sync_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nv50_disp_dmac_init,
         .base.fini = nv50_disp_dmac_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -696,6 +764,7 @@ nv50_disp_ovly_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nv50_disp_dmac_init,
         .base.fini = nv50_disp_dmac_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -813,6 +882,7 @@ nv50_disp_oimm_ofuncs = {
         .base.dtor = nv50_disp_pioc_dtor,
         .base.init = nv50_disp_pioc_init,
         .base.fini = nv50_disp_pioc_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -860,6 +930,7 @@ nv50_disp_curs_ofuncs = {
         .base.dtor = nv50_disp_pioc_dtor,
         .base.init = nv50_disp_pioc_init,
         .base.fini = nv50_disp_pioc_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -1559,7 +1630,7 @@ nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head)
 }
 
 static void
-nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv,
+nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv, int head,
                           struct dcb_output *outp, u32 pclk)
 {
         const int link = !(outp->sorconf.link & 1);
@@ -1568,24 +1639,36 @@ nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv,
         const u32 loff = (link * 0x080) + soff;
         const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8));
         const u32 symbol = 100000;
-        u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x0000f0000;
+        const s32 vactive = nv_rd32(priv, 0x610af8 + (head * 0x540)) & 0xffff;
+        const s32 vblanke = nv_rd32(priv, 0x610ae8 + (head * 0x540)) & 0xffff;
+        const s32 vblanks = nv_rd32(priv, 0x610af0 + (head * 0x540)) & 0xffff;
+        u32 dpctrl = nv_rd32(priv, 0x61c10c + loff);
         u32 clksor = nv_rd32(priv, 0x614300 + soff);
         int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
         int TU, VTUi, VTUf, VTUa;
         u64 link_data_rate, link_ratio, unk;
         u32 best_diff = 64 * symbol;
         u32 link_nr, link_bw, bits;
-
-        /* calculate packed data rate for each lane */
-        if      (dpctrl > 0x00030000) link_nr = 4;
-        else if (dpctrl > 0x00010000) link_nr = 2;
-        else                          link_nr = 1;
-
-        if (clksor & 0x000c0000)
-                link_bw = 270000;
-        else
-                link_bw = 162000;
-
+        u64 value;
+
+        link_bw = (clksor & 0x000c0000) ? 270000 : 162000;
+        link_nr = hweight32(dpctrl & 0x000f0000);
+
+        /* symbols/hblank - algorithm taken from comments in tegra driver */
+        value = vblanke + vactive - vblanks - 7;
+        value = value * link_bw;
+        do_div(value, pclk);
+        value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
+        nv_mask(priv, 0x61c1e8 + soff, 0x0000ffff, value);
+
+        /* symbols/vblank - algorithm taken from comments in tegra driver */
+        value = vblanks - vblanke - 25;
+        value = value * link_bw;
+        do_div(value, pclk);
+        value = value - ((36 / link_nr) + 3) - 1;
+        nv_mask(priv, 0x61c1ec + soff, 0x00ffffff, value);
+
+        /* watermark / activesym */
         if      ((ctrl & 0xf0000) == 0x60000) bits = 30;
         else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
         else                                  bits = 18;
@@ -1731,7 +1814,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
         } else
         if (!outp->info.location) {
                 if (outp->info.type == DCB_OUTPUT_DP)
-                        nv50_disp_intr_unk20_2_dp(priv, &outp->info, pclk);
+                        nv50_disp_intr_unk20_2_dp(priv, head, &outp->info, pclk);
                 oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800;
                 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
                 hval = 0x00000000;
@@ -1846,6 +1929,12 @@ nv50_disp_intr(struct nouveau_subdev *subdev)
                 intr0 &= ~(0x00010000 << chid);
         }
 
+        while (intr0 & 0x0000001f) {
+                u32 chid = __ffs(intr0 & 0x0000001f);
+                nv50_disp_chan_uevent_send(priv, chid);
+                intr0 &= ~(0x00000001 << chid);
+        }
+
         if (intr1 & 0x00000004) {
                 nouveau_disp_vblank(&priv->base, 0);
                 nv_wr32(priv, 0x610024, 0x00000004);
@@ -1880,6 +1969,10 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nv50_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
index 8ab14461f70c..5279feefec06 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
@@ -26,6 +26,8 @@ struct nv50_disp_priv {
         struct work_struct supervisor;
         u32 super;
 
+        struct nvkm_event uevent;
+
         struct {
                 int nr;
         } head;
@@ -75,6 +77,7 @@ int nvd0_hda_eld(NV50_DISP_MTHD_V1);
 int nv84_hdmi_ctrl(NV50_DISP_MTHD_V1);
 int nva3_hdmi_ctrl(NV50_DISP_MTHD_V1);
 int nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1);
+int nve0_hdmi_ctrl(NV50_DISP_MTHD_V1);
 
 int nv50_sor_power(NV50_DISP_MTHD_V1);
 
@@ -116,9 +119,16 @@ struct nv50_disp_chan {
         int chid;
 };
 
+int  nv50_disp_chan_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
 int  nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *);
 u32  nv50_disp_chan_rd32(struct nouveau_object *, u64);
 void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
+extern const struct nvkm_event_func nv50_disp_chan_uevent;
+int  nv50_disp_chan_uevent_ctor(struct nouveau_object *, void *, u32,
+                                struct nvkm_notify *);
+void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int);
+
+extern const struct nvkm_event_func nvd0_disp_chan_uevent;
 
 #define nv50_disp_chan_init(a)                                                 \
         nouveau_namedb_init(&(a)->base)
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
index 788ced1b6182..d36284715b2a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
@@ -236,6 +236,10 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nv84_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
index fa79de906eae..a117064002b1 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
@@ -95,6 +95,10 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nv94_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
index 7af15f5d48dc..c67e68aadd45 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
@@ -112,6 +112,10 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nva0_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
index 6bd39448f8da..22969f355aae 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
@@ -67,6 +67,10 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nva3_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index a4bb3c774ee1..747e64bb9c06 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -43,6 +43,31 @@
 #include "nv50.h"
 
 /*******************************************************************************
+ * EVO channel base class
+ ******************************************************************************/
+
+static void
+nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
+{
+        struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+        nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index);
+}
+
+static void
+nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
+{
+        struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+        nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000001 << index);
+}
+
+const struct nvkm_event_func
+nvd0_disp_chan_uevent = {
+        .ctor = nv50_disp_chan_uevent_ctor,
+        .init = nvd0_disp_chan_uevent_init,
+        .fini = nvd0_disp_chan_uevent_fini,
+};
+
+/*******************************************************************************
  * EVO DMA channel base class
  ******************************************************************************/
 
@@ -77,7 +102,6 @@ nvd0_disp_dmac_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
 
         /* initialise channel for dma command submission */
@@ -115,7 +139,7 @@ nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notification */
         nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
 
@@ -278,7 +302,6 @@ nvd0_disp_mast_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610090, 0x00000001, 0x00000001);
         nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001);
 
         /* initialise channel for dma command submission */
@@ -313,7 +336,7 @@ nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notification */
         nv_mask(priv, 0x610090, 0x00000001, 0x00000000);
         nv_mask(priv, 0x6100a0, 0x00000001, 0x00000000);
 
@@ -326,6 +349,7 @@ nvd0_disp_mast_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nvd0_disp_mast_init,
         .base.fini = nvd0_disp_mast_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -419,6 +443,7 @@ nvd0_disp_sync_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nvd0_disp_dmac_init,
         .base.fini = nvd0_disp_dmac_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -499,6 +524,7 @@ nvd0_disp_ovly_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nvd0_disp_dmac_init,
         .base.fini = nvd0_disp_dmac_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -524,7 +550,6 @@ nvd0_disp_pioc_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
 
         /* activate channel */
@@ -553,7 +578,7 @@ nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notification */
         nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
 
@@ -570,6 +595,7 @@ nvd0_disp_oimm_ofuncs = {
         .base.dtor = nv50_disp_pioc_dtor,
         .base.init = nvd0_disp_pioc_init,
         .base.fini = nvd0_disp_pioc_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -586,6 +612,7 @@ nvd0_disp_curs_ofuncs = {
         .base.dtor = nv50_disp_pioc_dtor,
         .base.init = nvd0_disp_pioc_init,
         .base.fini = nvd0_disp_pioc_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -949,6 +976,9 @@ nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
         const int or = ffs(outp->or) - 1;
         const u32 ctrl = nv_rd32(priv, 0x660200 + (or   * 0x020));
         const u32 conf = nv_rd32(priv, 0x660404 + (head * 0x300));
+        const s32 vactive = nv_rd32(priv, 0x660414 + (head * 0x300)) & 0xffff;
+        const s32 vblanke = nv_rd32(priv, 0x66041c + (head * 0x300)) & 0xffff;
+        const s32 vblanks = nv_rd32(priv, 0x660420 + (head * 0x300)) & 0xffff;
         const u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
         const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1;
         const u32 hoff = (head * 0x800);
@@ -956,23 +986,35 @@ nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
         const u32 loff = (link * 0x080) + soff;
         const u32 symbol = 100000;
         const u32 TU = 64;
-        u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x000f0000;
+        u32 dpctrl = nv_rd32(priv, 0x61c10c + loff);
         u32 clksor = nv_rd32(priv, 0x612300 + soff);
         u32 datarate, link_nr, link_bw, bits;
         u64 ratio, value;
 
+        link_nr  = hweight32(dpctrl & 0x000f0000);
+        link_bw  = (clksor & 0x007c0000) >> 18;
+        link_bw *= 27000;
+
+        /* symbols/hblank - algorithm taken from comments in tegra driver */
+        value = vblanke + vactive - vblanks - 7;
+        value = value * link_bw;
+        do_div(value, pclk);
+        value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
+        nv_mask(priv, 0x616620 + hoff, 0x0000ffff, value);
+
+        /* symbols/vblank - algorithm taken from comments in tegra driver */
+        value = vblanks - vblanke - 25;
+        value = value * link_bw;
+        do_div(value, pclk);
+        value = value - ((36 / link_nr) + 3) - 1;
+        nv_mask(priv, 0x616624 + hoff, 0x00ffffff, value);
+
+        /* watermark */
         if      ((conf & 0x3c0) == 0x180) bits = 30;
         else if ((conf & 0x3c0) == 0x140) bits = 24;
         else                              bits = 18;
         datarate = (pclk * bits) / 8;
 
-        if      (dpctrl > 0x00030000) link_nr = 4;
-        else if (dpctrl > 0x00010000) link_nr = 2;
-        else                          link_nr = 1;
-
-        link_bw  = (clksor & 0x007c0000) >> 18;
-        link_bw *= 27000;
-
         ratio  = datarate;
         ratio *= symbol;
         do_div(ratio, link_nr * link_bw);
@@ -1153,7 +1195,11 @@ nvd0_disp_intr(struct nouveau_subdev *subdev)
 
         if (intr & 0x00000001) {
                 u32 stat = nv_rd32(priv, 0x61008c);
-                nv_wr32(priv, 0x61008c, stat);
+                while (stat) {
+                        int chid = __ffs(stat); stat &= ~(1 << chid);
+                        nv50_disp_chan_uevent_send(priv, chid);
+                        nv_wr32(priv, 0x61008c, 1 << chid);
+                }
                 intr &= ~0x00000001;
         }
 
@@ -1209,6 +1255,10 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nvd0_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nvd0_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
index 47fef1e398c4..db144b2cf06b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
@@ -233,6 +233,10 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nve0_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nvd0_disp_intr;
@@ -245,7 +249,7 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         priv->dac.sense = nv50_dac_sense;
         priv->sor.power = nv50_sor_power;
         priv->sor.hda_eld = nvd0_hda_eld;
-        priv->sor.hdmi = nvd0_hdmi_ctrl;
+        priv->sor.hdmi = nve0_hdmi_ctrl;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
index 04bda4ac4ed3..402d7d67d806 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
@@ -68,6 +68,10 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nvf0_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nvd0_disp_intr;
@@ -80,7 +84,7 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         priv->dac.sense = nv50_dac_sense;
         priv->sor.power = nv50_sor_power;
         priv->sor.hda_eld = nvd0_hda_eld;
-        priv->sor.hdmi = nvd0_hdmi_ctrl;
+        priv->sor.hdmi = nve0_hdmi_ctrl;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
index 6f6e2a898270..667a9070e006 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
@@ -254,7 +254,7 @@ nvkm_output_dp_create_(struct nouveau_object *parent,
         atomic_set(&outp->lt.done, 0);
 
         /* link maintenance */
-        ret = nvkm_notify_init(&i2c->event, nvkm_output_dp_irq, true,
+        ret = nvkm_notify_init(NULL, &i2c->event, nvkm_output_dp_irq, true,
                                &(struct nvkm_i2c_ntfy_req) {
                                 .mask = NVKM_I2C_IRQ,
                                 .port = outp->base.edid->index,
@@ -268,7 +268,7 @@ nvkm_output_dp_create_(struct nouveau_object *parent,
         }
 
         /* hotplug detect, replaces gpio-based mechanism with aux events */
-        ret = nvkm_notify_init(&i2c->event, nvkm_output_dp_hpd, true,
+        ret = nvkm_notify_init(NULL, &i2c->event, nvkm_output_dp_hpd, true,
                                &(struct nvkm_i2c_ntfy_req) {
                                 .mask = NVKM_I2C_PLUG | NVKM_I2C_UNPLUG,
                                 .port = outp->base.edid->index,
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/priv.h b/drivers/gpu/drm/nouveau/core/engine/disp/priv.h
index dbd43ae9df81..6a0511d54ce6 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/priv.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/priv.h
@@ -40,7 +40,8 @@ int  _nouveau_disp_fini(struct nouveau_object *, bool);
 extern struct nouveau_oclass *nvkm_output_oclass;
 extern struct nouveau_oclass *nvkm_connector_oclass;
 
-int  nouveau_disp_vblank_ctor(void *data, u32 size, struct nvkm_notify *);
+int  nouveau_disp_vblank_ctor(struct nouveau_object *, void *data, u32 size,
+                              struct nvkm_notify *);
 void nouveau_disp_vblank(struct nouveau_disp *, int head);
 int  nouveau_disp_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
index 0f999fc45ab9..ac8375cf4eef 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
@@ -34,7 +34,8 @@
 #include <engine/fifo.h>
 
 static int
-nouveau_fifo_event_ctor(void *data, u32 size, struct nvkm_notify *notify)
+nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size,
+                        struct nvkm_notify *notify)
 {
         if (size == 0) {
                 notify->size  = 0;
@@ -170,7 +171,8 @@ _nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data)
 }
 
 int
-nouveau_fifo_uevent_ctor(void *data, u32 size, struct nvkm_notify *notify)
+nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
+                         struct nvkm_notify *notify)
 {
         union {
                 struct nvif_notify_uevent_req none;
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
index 4d2994d8cc32..a0fec205f9db 100644
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
@@ -175,7 +175,8 @@ nv50_software_context_ctor(struct nouveau_object *parent,
                 return ret;
 
         for (i = 0; pdisp && i < pdisp->vblank.index_nr; i++) {
-                ret = nvkm_notify_init(&pdisp->vblank, pclass->vblank, false,
+                ret = nvkm_notify_init(NULL, &pdisp->vblank, pclass->vblank,
+                                       false,
                                        &(struct nvif_notify_head_req_v0) {
                                         .head = i,
                                        },
diff --git a/drivers/gpu/drm/nouveau/core/include/core/client.h b/drivers/gpu/drm/nouveau/core/include/core/client.h
index 1794a05205d8..b0ce9f6680b5 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/client.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/client.h
@@ -48,7 +48,7 @@ int  nouveau_client_init(struct nouveau_client *);
 int  nouveau_client_fini(struct nouveau_client *, bool suspend);
 const char *nouveau_client_name(void *obj);
 
-int nvkm_client_notify_new(struct nouveau_client *, struct nvkm_event *,
+int nvkm_client_notify_new(struct nouveau_object *, struct nvkm_event *,
                            void *data, u32 size);
 int nvkm_client_notify_del(struct nouveau_client *, int index);
 int nvkm_client_notify_get(struct nouveau_client *, int index);
diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h
index 8743766454a5..1d9d893929bb 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/device.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/device.h
@@ -24,6 +24,7 @@ enum nv_subdev_type {
          * been created, and are allowed to assume any subdevs in the
          * list above them exist and have been initialised.
          */
+        NVDEV_SUBDEV_FUSE,
         NVDEV_SUBDEV_MXM,
         NVDEV_SUBDEV_MC,
         NVDEV_SUBDEV_BUS,
diff --git a/drivers/gpu/drm/nouveau/core/include/core/event.h b/drivers/gpu/drm/nouveau/core/include/core/event.h
index 51e55d03330a..92876528972f 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/event.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/event.h
@@ -4,7 +4,8 @@
 #include <core/notify.h>
 
 struct nvkm_event_func {
-        int  (*ctor)(void *data, u32 size, struct nvkm_notify *);
+        int  (*ctor)(struct nouveau_object *, void *data, u32 size,
+                     struct nvkm_notify *);
         void (*send)(void *data, u32 size, struct nvkm_notify *);
         void (*init)(struct nvkm_event *, int type, int index);
         void (*fini)(struct nvkm_event *, int type, int index);
diff --git a/drivers/gpu/drm/nouveau/core/include/core/mm.h b/drivers/gpu/drm/nouveau/core/include/core/mm.h
index 2bf7d0e32261..bfe6931544fe 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/mm.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/mm.h
@@ -6,6 +6,10 @@ struct nouveau_mm_node {
         struct list_head fl_entry;
         struct list_head rl_entry;
 
+#define NVKM_MM_HEAP_ANY 0x00
+        u8  heap;
+#define NVKM_MM_TYPE_NONE 0x00
+#define NVKM_MM_TYPE_HOLE 0xff
         u8  type;
         u32 offset;
         u32 length;
@@ -27,10 +31,10 @@ nouveau_mm_initialised(struct nouveau_mm *mm)
 
 int  nouveau_mm_init(struct nouveau_mm *, u32 offset, u32 length, u32 block);
 int  nouveau_mm_fini(struct nouveau_mm *);
-int  nouveau_mm_head(struct nouveau_mm *, u8 type, u32 size_max, u32 size_min,
-                     u32 align, struct nouveau_mm_node **);
-int  nouveau_mm_tail(struct nouveau_mm *, u8 type, u32 size_max, u32 size_min,
-                     u32 align, struct nouveau_mm_node **);
+int  nouveau_mm_head(struct nouveau_mm *, u8 heap, u8 type, u32 size_max,
+                     u32 size_min, u32 align, struct nouveau_mm_node **);
+int  nouveau_mm_tail(struct nouveau_mm *, u8 heap, u8 type, u32 size_max,
+                     u32 size_min, u32 align, struct nouveau_mm_node **);
 void nouveau_mm_free(struct nouveau_mm *, struct nouveau_mm_node **);
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/notify.h b/drivers/gpu/drm/nouveau/core/include/core/notify.h
index 1262d8f020f3..a7c3c5f578cc 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/notify.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/notify.h
@@ -25,8 +25,9 @@ struct nvkm_notify {
         const void *data;
 };
 
-int  nvkm_notify_init(struct nvkm_event *, int (*func)(struct nvkm_notify *),
-                      bool work, void *data, u32 size, u32 reply,
+int  nvkm_notify_init(struct nouveau_object *, struct nvkm_event *,
+                      int (*func)(struct nvkm_notify *), bool work,
+                      void *data, u32 size, u32 reply,
                       struct nvkm_notify *);
 void nvkm_notify_fini(struct nvkm_notify *);
 void nvkm_notify_get(struct nvkm_notify *);
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
index e5e4d930b2c2..2007453f6fce 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
@@ -116,7 +116,8 @@ extern struct nouveau_oclass *nve0_fifo_oclass;
 extern struct nouveau_oclass *gk20a_fifo_oclass;
 extern struct nouveau_oclass *nv108_fifo_oclass;
 
-int  nouveau_fifo_uevent_ctor(void *, u32, struct nvkm_notify *);
+int  nouveau_fifo_uevent_ctor(struct nouveau_object *, void *, u32,
+                              struct nvkm_notify *);
 void nouveau_fifo_uevent(struct nouveau_fifo *);
 
 void nv04_fifo_intr(struct nouveau_subdev *);
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h b/drivers/gpu/drm/nouveau/core/include/subdev/bar.h
index be037fac534c..257ddf6d36d4 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bar.h
@@ -12,7 +12,6 @@ struct nouveau_bar {
 
         int (*alloc)(struct nouveau_bar *, struct nouveau_object *,
                      struct nouveau_mem *, struct nouveau_object **);
-        void __iomem *iomem;
 
         int (*kmap)(struct nouveau_bar *, struct nouveau_mem *,
                     u32 flags, struct nouveau_vma *);
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h
new file mode 100644
index 000000000000..e171120cec81
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h
@@ -0,0 +1,32 @@
+#ifndef __NVBIOS_M0205_H__
+#define __NVBIOS_M0205_H__
+
+struct nvbios_M0205T {
+        u16 freq;
+};
+
+u32 nvbios_M0205Te(struct nouveau_bios *,
+                   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
+u32 nvbios_M0205Tp(struct nouveau_bios *,
+                   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz,
+                   struct nvbios_M0205T *);
+
+struct nvbios_M0205E {
+        u8 type;
+};
+
+u32 nvbios_M0205Ee(struct nouveau_bios *, int idx,
+                   u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u32 nvbios_M0205Ep(struct nouveau_bios *, int idx,
+                   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+                   struct nvbios_M0205E *);
+
+struct nvbios_M0205S {
+        u8 data;
+};
+
+u32 nvbios_M0205Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr);
+u32 nvbios_M0205Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr,
+                   struct nvbios_M0205S *);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h
new file mode 100644
index 000000000000..67dc50d837bc
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h
@@ -0,0 +1,30 @@
+#ifndef __NVBIOS_M0209_H__
+#define __NVBIOS_M0209_H__
+
+u32 nvbios_M0209Te(struct nouveau_bios *,
+                   u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
+
+struct nvbios_M0209E {
+        u8 v00_40;
+        u8 bits;
+        u8 modulo;
+        u8 v02_40;
+        u8 v02_07;
+        u8 v03;
+};
+
+u32 nvbios_M0209Ee(struct nouveau_bios *, int idx,
+                   u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u32 nvbios_M0209Ep(struct nouveau_bios *, int idx,
+                   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+                   struct nvbios_M0209E *);
+
+struct nvbios_M0209S {
+        u32 data[0x200];
+};
+
+u32 nvbios_M0209Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr);
+u32 nvbios_M0209Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr,
+                   struct nvbios_M0209S *);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h
new file mode 100644
index 000000000000..119d0874e041
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h
@@ -0,0 +1,8 @@
+#ifndef __NVBIOS_FAN_H__
+#define __NVBIOS_FAN_H__
+
+#include <subdev/bios/therm.h>
+
+u16 nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
index c086ac6d677d..a685bbd04568 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
@@ -4,60 +4,118 @@
 struct nouveau_bios;
 
 struct nvbios_ramcfg {
-        unsigned rammap_11_08_01:1;
-        unsigned rammap_11_08_0c:2;
-        unsigned rammap_11_08_10:1;
-        unsigned rammap_11_11_0c:2;
+        unsigned rammap_ver;
+        unsigned rammap_hdr;
+        unsigned rammap_min;
+        unsigned rammap_max;
+        union {
+                struct {
+                        unsigned rammap_10_04_02:1;
+                        unsigned rammap_10_04_08:1;
+                };
+                struct {
+                        unsigned rammap_11_08_01:1;
+                        unsigned rammap_11_08_0c:2;
+                        unsigned rammap_11_08_10:1;
+                        unsigned rammap_11_09_01ff:9;
+                        unsigned rammap_11_0a_03fe:9;
+                        unsigned rammap_11_0a_0400:1;
+                        unsigned rammap_11_0a_0800:1;
+                        unsigned rammap_11_0b_01f0:5;
+                        unsigned rammap_11_0b_0200:1;
+                        unsigned rammap_11_0b_0400:1;
+                        unsigned rammap_11_0b_0800:1;
+                        unsigned rammap_11_0d:8;
+                        unsigned rammap_11_0e:8;
+                        unsigned rammap_11_0f:8;
+                        unsigned rammap_11_11_0c:2;
+                };
+        };
 
-        unsigned ramcfg_11_01_01:1;
-        unsigned ramcfg_11_01_02:1;
-        unsigned ramcfg_11_01_04:1;
-        unsigned ramcfg_11_01_08:1;
-        unsigned ramcfg_11_01_10:1;
-        unsigned ramcfg_11_01_20:1;
-        unsigned ramcfg_11_01_40:1;
-        unsigned ramcfg_11_01_80:1;
-        unsigned ramcfg_11_02_03:2;
-        unsigned ramcfg_11_02_04:1;
-        unsigned ramcfg_11_02_08:1;
-        unsigned ramcfg_11_02_10:1;
-        unsigned ramcfg_11_02_40:1;
-        unsigned ramcfg_11_02_80:1;
-        unsigned ramcfg_11_03_0f:4;
-        unsigned ramcfg_11_03_30:2;
-        unsigned ramcfg_11_03_c0:2;
-        unsigned ramcfg_11_03_f0:4;
-        unsigned ramcfg_11_04:8;
-        unsigned ramcfg_11_06:8;
-        unsigned ramcfg_11_07_02:1;
-        unsigned ramcfg_11_07_04:1;
-        unsigned ramcfg_11_07_08:1;
-        unsigned ramcfg_11_07_10:1;
-        unsigned ramcfg_11_07_40:1;
-        unsigned ramcfg_11_07_80:1;
-        unsigned ramcfg_11_08_01:1;
-        unsigned ramcfg_11_08_02:1;
-        unsigned ramcfg_11_08_04:1;
-        unsigned ramcfg_11_08_08:1;
-        unsigned ramcfg_11_08_10:1;
-        unsigned ramcfg_11_08_20:1;
-        unsigned ramcfg_11_09:8;
+        unsigned ramcfg_ver;
+        unsigned ramcfg_hdr;
+        unsigned ramcfg_timing;
+        union {
+                struct {
+                        unsigned ramcfg_10_02_01:1;
+                        unsigned ramcfg_10_02_02:1;
+                        unsigned ramcfg_10_02_04:1;
+                        unsigned ramcfg_10_02_08:1;
+                        unsigned ramcfg_10_02_10:1;
+                        unsigned ramcfg_10_02_20:1;
+                        unsigned ramcfg_10_02_40:1;
+                        unsigned ramcfg_10_03_0f:4;
+                        unsigned ramcfg_10_05:8;
+                        unsigned ramcfg_10_06:8;
+                        unsigned ramcfg_10_07:8;
+                        unsigned ramcfg_10_08:8;
+                        unsigned ramcfg_10_09_0f:4;
+                        unsigned ramcfg_10_09_f0:4;
+                };
+                struct {
+                        unsigned ramcfg_11_01_01:1;
+                        unsigned ramcfg_11_01_02:1;
+                        unsigned ramcfg_11_01_04:1;
+                        unsigned ramcfg_11_01_08:1;
+                        unsigned ramcfg_11_01_10:1;
+                        unsigned ramcfg_11_01_20:1;
+                        unsigned ramcfg_11_01_40:1;
+                        unsigned ramcfg_11_01_80:1;
+                        unsigned ramcfg_11_02_03:2;
+                        unsigned ramcfg_11_02_04:1;
+                        unsigned ramcfg_11_02_08:1;
+                        unsigned ramcfg_11_02_10:1;
+                        unsigned ramcfg_11_02_40:1;
+                        unsigned ramcfg_11_02_80:1;
+                        unsigned ramcfg_11_03_0f:4;
+                        unsigned ramcfg_11_03_30:2;
+                        unsigned ramcfg_11_03_c0:2;
+                        unsigned ramcfg_11_03_f0:4;
+                        unsigned ramcfg_11_04:8;
+                        unsigned ramcfg_11_06:8;
+                        unsigned ramcfg_11_07_02:1;
+                        unsigned ramcfg_11_07_04:1;
+                        unsigned ramcfg_11_07_08:1;
+                        unsigned ramcfg_11_07_10:1;
+                        unsigned ramcfg_11_07_40:1;
+                        unsigned ramcfg_11_07_80:1;
+                        unsigned ramcfg_11_08_01:1;
+                        unsigned ramcfg_11_08_02:1;
+                        unsigned ramcfg_11_08_04:1;
+                        unsigned ramcfg_11_08_08:1;
+                        unsigned ramcfg_11_08_10:1;
+                        unsigned ramcfg_11_08_20:1;
+                        unsigned ramcfg_11_09:8;
+                };
+        };
 
+        unsigned timing_ver;
+        unsigned timing_hdr;
         unsigned timing[11];
-        unsigned timing_20_2e_03:2;
-        unsigned timing_20_2e_30:2;
-        unsigned timing_20_2e_c0:2;
-        unsigned timing_20_2f_03:2;
-        unsigned timing_20_2c_003f:6;
-        unsigned timing_20_2c_1fc0:7;
-        unsigned timing_20_30_f8:5;
-        unsigned timing_20_30_07:3;
-        unsigned timing_20_31_0007:3;
-        unsigned timing_20_31_0078:4;
-        unsigned timing_20_31_0780:4;
-        unsigned timing_20_31_0800:1;
-        unsigned timing_20_31_7000:3;
-        unsigned timing_20_31_8000:1;
+        union {
+                struct {
+                        unsigned timing_10_WR:8;
+                        unsigned timing_10_CL:8;
+                        unsigned timing_10_ODT:3;
+                        unsigned timing_10_CWL:8;
+                };
+                struct {
+                        unsigned timing_20_2e_03:2;
+                        unsigned timing_20_2e_30:2;
+                        unsigned timing_20_2e_c0:2;
+                        unsigned timing_20_2f_03:2;
+                        unsigned timing_20_2c_003f:6;
+                        unsigned timing_20_2c_1fc0:7;
+                        unsigned timing_20_30_f8:5;
+                        unsigned timing_20_30_07:3;
+                        unsigned timing_20_31_0007:3;
+                        unsigned timing_20_31_0078:4;
+                        unsigned timing_20_31_0780:4;
+                        unsigned timing_20_31_0800:1;
+                        unsigned timing_20_31_7000:3;
+                        unsigned timing_20_31_8000:1;
+                };
+        };
 };
 
 u8 nvbios_ramcfg_count(struct nouveau_bios *);
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
index 5bdf8e4db40a..47e021d3e20d 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
@@ -8,9 +8,10 @@ u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr,
 
 u32 nvbios_rammapEe(struct nouveau_bios *, int idx,
                     u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u32 nvbios_rammapEp(struct nouveau_bios *, int idx,
+                    u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+                    struct nvbios_ramcfg *);
 u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz,
-                    u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_rammapEp(struct nouveau_bios *, u16 mhz,
                     u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
                     struct nvbios_ramcfg *);
 
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h
index 8dc5051df55d..295d093f3b30 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h
@@ -23,6 +23,12 @@ struct nvbios_therm_sensor {
         struct nvbios_therm_threshold thrs_shutdown;
 };
 
+enum nvbios_therm_fan_type {
+        NVBIOS_THERM_FAN_UNK = 0,
+        NVBIOS_THERM_FAN_TOGGLE = 1,
+        NVBIOS_THERM_FAN_PWM = 2,
+};
+
 /* no vbios have more than 6 */
 #define NOUVEAU_TEMP_FAN_TRIP_MAX 10
 struct nouveau_therm_trip_point {
@@ -38,7 +44,9 @@ enum nvbios_therm_fan_mode {
 };
 
 struct nvbios_therm_fan {
-        u16 pwm_freq;
+        enum nvbios_therm_fan_type type;
+
+        u32 pwm_freq;
 
         u8 min_duty;
         u8 max_duty;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
index a5ca00dd2f61..36ed035d4d42 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
@@ -29,6 +29,7 @@ enum nv_clk_src {
         nv_clk_src_mdiv,
 
         nv_clk_src_core,
+        nv_clk_src_core_intm,
         nv_clk_src_shader,
 
         nv_clk_src_mem,
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
index 871e73914b24..8d0032f15205 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
@@ -111,6 +111,7 @@ extern struct nouveau_oclass *gm107_fb_oclass;
 #include <subdev/bios/ramcfg.h>
 
 struct nouveau_ram_data {
+        struct list_head head;
         struct nvbios_ramcfg bios;
         u32 freq;
 };
@@ -136,6 +137,7 @@ struct nouveau_ram {
 
         int ranks;
         int parts;
+        int part_mask;
 
         int  (*get)(struct nouveau_fb *, u64 size, u32 align,
                     u32 size_nc, u32 type, struct nouveau_mem **);
@@ -144,11 +146,6 @@ struct nouveau_ram {
         int  (*calc)(struct nouveau_fb *, u32 freq);
         int  (*prog)(struct nouveau_fb *);
         void (*tidy)(struct nouveau_fb *);
-        struct {
-                u8  version;
-                u32 data;
-                u8  size;
-        } rammap, ramcfg, timing;
         u32 freq;
         u32 mr[16];
         u32 mr1_nuts;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h
new file mode 100644
index 000000000000..0f7fc0c52ab2
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h
@@ -0,0 +1,21 @@
+#ifndef __NOUVEAU_FB_REGS_04_H__
+#define __NOUVEAU_FB_REGS_04_H__
+
+#define NV04_PFB_BOOT_0                                         0x00100000
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT                       0x00000003
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB                  0x00000000
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB                   0x00000001
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB                   0x00000002
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB                  0x00000003
+#       define NV04_PFB_BOOT_0_RAM_WIDTH_128                    0x00000004
+#       define NV04_PFB_BOOT_0_RAM_TYPE                         0x00000028
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT             0x00000000
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT            0x00000008
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK      0x00000010
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT            0x00000018
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT            0x00000020
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16         0x00000028
+#       define NV04_PFB_BOOT_0_UMA_ENABLE                       0x00000100
+#       define NV04_PFB_BOOT_0_UMA_SIZE                         0x0000f000
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h b/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h
new file mode 100644
index 000000000000..2b1ddb2a9a7d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h
@@ -0,0 +1,30 @@
+#ifndef __NOUVEAU_FUSE_H__
+#define __NOUVEAU_FUSE_H__
+
+#include <core/subdev.h>
+#include <core/device.h>
+
+struct nouveau_fuse {
+        struct nouveau_subdev base;
+};
+
+static inline struct nouveau_fuse *
+nouveau_fuse(void *obj)
+{
+        return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FUSE];
+}
+
+#define nouveau_fuse_create(p, e, o, d)                                        \
+        nouveau_fuse_create_((p), (e), (o), sizeof(**d), (void **)d)
+
+int  nouveau_fuse_create_(struct nouveau_object *, struct nouveau_object *,
+                          struct nouveau_oclass *, int, void **);
+void _nouveau_fuse_dtor(struct nouveau_object *);
+int  _nouveau_fuse_init(struct nouveau_object *);
+#define _nouveau_fuse_fini _nouveau_subdev_fini
+
+extern struct nouveau_oclass g80_fuse_oclass;
+extern struct nouveau_oclass gf100_fuse_oclass;
+extern struct nouveau_oclass gm107_fuse_oclass;
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
index b73733d21cc7..f855140dbcb7 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
@@ -40,7 +40,7 @@ nouveau_gpio(void *obj)
 
 extern struct nouveau_oclass *nv10_gpio_oclass;
 extern struct nouveau_oclass *nv50_gpio_oclass;
-extern struct nouveau_oclass *nv92_gpio_oclass;
+extern struct nouveau_oclass *nv94_gpio_oclass;
 extern struct nouveau_oclass *nvd0_gpio_oclass;
 extern struct nouveau_oclass *nve0_gpio_oclass;
 
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
index f73feec151db..bf3d1f611333 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
@@ -47,5 +47,8 @@ void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data);
 void nouveau_memx_wait(struct nouveau_memx *,
                        u32 addr, u32 mask, u32 data, u32 nsec);
 void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec);
+void nouveau_memx_wait_vblank(struct nouveau_memx *);
+void nouveau_memx_block(struct nouveau_memx *);
+void nouveau_memx_unblock(struct nouveau_memx *);
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h b/drivers/gpu/drm/nouveau/core/include/subdev/therm.h
index d4a68179e586..a437597dcafc 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/therm.h
@@ -78,5 +78,6 @@ extern struct nouveau_oclass nv50_therm_oclass;
 extern struct nouveau_oclass nv84_therm_oclass;
 extern struct nouveau_oclass nva3_therm_oclass;
 extern struct nouveau_oclass nvd0_therm_oclass;
+extern struct nouveau_oclass gm107_therm_oclass;
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
index 8bcbdf39cfb2..b1adc69efd88 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
@@ -38,10 +38,12 @@ struct nouveau_barobj {
 static int
 nouveau_barobj_ctor(struct nouveau_object *parent,
                     struct nouveau_object *engine,
-                    struct nouveau_oclass *oclass, void *mem, u32 size,
+                    struct nouveau_oclass *oclass, void *data, u32 size,
                     struct nouveau_object **pobject)
 {
+        struct nouveau_device *device = nv_device(parent);
         struct nouveau_bar *bar = (void *)engine;
+        struct nouveau_mem *mem = data;
         struct nouveau_barobj *barobj;
         int ret;
 
@@ -54,7 +56,13 @@ nouveau_barobj_ctor(struct nouveau_object *parent,
         if (ret)
                 return ret;
 
-        barobj->iomem = bar->iomem + (u32)barobj->vma.offset;
+        barobj->iomem = ioremap(nv_device_resource_start(device, 3) +
+                                (u32)barobj->vma.offset, mem->size << 12);
+        if (!barobj->iomem) {
+                nv_warn(bar, "PRAMIN ioremap failed\n");
+                return -ENOMEM;
+        }
+
         return 0;
 }
 
@@ -63,8 +71,11 @@ nouveau_barobj_dtor(struct nouveau_object *object)
 {
         struct nouveau_bar *bar = (void *)object->engine;
         struct nouveau_barobj *barobj = (void *)object;
-        if (barobj->vma.node)
+        if (barobj->vma.node) {
+                if (barobj->iomem)
+                        iounmap(barobj->iomem);
                 bar->unmap(bar, &barobj->vma);
+        }
         nouveau_object_destroy(&barobj->base);
 }
 
@@ -99,12 +110,11 @@ nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent,
                   struct nouveau_mem *mem, struct nouveau_object **pobject)
 {
         struct nouveau_object *engine = nv_object(bar);
-        int ret = -ENOMEM;
-        if (bar->iomem) {
-                ret = nouveau_object_ctor(parent, engine,
-                                          &nouveau_barobj_oclass,
-                                          mem, 0, pobject);
-        }
+        struct nouveau_object *gpuobj;
+        int ret = nouveau_object_ctor(parent, engine, &nouveau_barobj_oclass,
+                                      mem, 0, &gpuobj);
+        if (ret == 0)
+                *pobject = gpuobj;
         return ret;
 }
 
@@ -113,7 +123,6 @@ nouveau_bar_create_(struct nouveau_object *parent,
                     struct nouveau_object *engine,
                     struct nouveau_oclass *oclass, int length, void **pobject)
 {
-        struct nouveau_device *device = nv_device(parent);
         struct nouveau_bar *bar;
         int ret;
 
@@ -123,21 +132,12 @@ nouveau_bar_create_(struct nouveau_object *parent,
         if (ret)
                 return ret;
 
-        if (nv_device_resource_len(device, 3) != 0) {
-                bar->iomem = ioremap(nv_device_resource_start(device, 3),
-                                     nv_device_resource_len(device, 3));
-                if (!bar->iomem)
-                        nv_warn(bar, "PRAMIN ioremap failed\n");
-        }
-
         return 0;
 }
 
 void
 nouveau_bar_destroy(struct nouveau_bar *bar)
 {
-        if (bar->iomem)
-                iounmap(bar->iomem);
         nouveau_subdev_destroy(&bar->base);
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c b/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c
new file mode 100644
index 000000000000..ac9617c5fc2a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <subdev/bios.h>
+#include <subdev/bios/bit.h>
+#include <subdev/bios/M0205.h>
+
+u32
+nvbios_M0205Te(struct nouveau_bios *bios,
+               u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
+{
+        struct bit_entry bit_M;
+        u32 data = 0x00000000;
+
+        if (!bit_entry(bios, 'M', &bit_M)) {
+                if (bit_M.version == 2 && bit_M.length > 0x08)
+                        data = nv_ro32(bios, bit_M.offset + 0x05);
+                if (data) {
+                        *ver = nv_ro08(bios, data + 0x00);
+                        switch (*ver) {
+                        case 0x10:
+                                *hdr = nv_ro08(bios, data + 0x01);
+                                *len = nv_ro08(bios, data + 0x02);
+                                *ssz = nv_ro08(bios, data + 0x03);
+                                *snr = nv_ro08(bios, data + 0x04);
+                                *cnt = nv_ro08(bios, data + 0x05);
+                                return data;
+                        default:
+                                break;
+                        }
+                }
+        }
+
+        return 0x00000000;
+}
+
+u32
+nvbios_M0205Tp(struct nouveau_bios *bios,
+               u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz,
+               struct nvbios_M0205T *info)
+{
+        u32 data = nvbios_M0205Te(bios, ver, hdr, cnt, len, snr, ssz);
+        memset(info, 0x00, sizeof(*info));
+        switch (!!data * *ver) {
+        case 0x10:
+                info->freq = nv_ro16(bios, data + 0x06);
+                break;
+        default:
+                break;
+        }
+        return data;
+}
+
+u32
+nvbios_M0205Ee(struct nouveau_bios *bios, int idx,
+               u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+{
+        u8  snr, ssz;
+        u32 data = nvbios_M0205Te(bios, ver, hdr, cnt, len, &snr, &ssz);
+        if (data && idx < *cnt) {
+                data = data + *hdr + idx * (*len + (snr * ssz));
+                *hdr = *len;
+                *cnt = snr;
+                *len = ssz;
+                return data;
+        }
+        return 0x00000000;
+}
+
+u32
+nvbios_M0205Ep(struct nouveau_bios *bios, int idx,
+               u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+               struct nvbios_M0205E *info)
+{
+        u32 data = nvbios_M0205Ee(bios, idx, ver, hdr, cnt, len);
+        memset(info, 0x00, sizeof(*info));
+        switch (!!data * *ver) {
+        case 0x10:
+                info->type = nv_ro08(bios, data + 0x00) & 0x0f;
+                return data;
+        default:
+                break;
+        }
+        return 0x00000000;
+}
+
+u32
+nvbios_M0205Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
+{
+
+        u8  cnt, len;
+        u32 data = nvbios_M0205Ee(bios, ent, ver, hdr, &cnt, &len);
+        if (data && idx < cnt) {
+                data = data + *hdr + idx * len;
+                *hdr = len;
+                return data;
+        }
+        return 0x00000000;
+}
+
+u32
+nvbios_M0205Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
+               struct nvbios_M0205S *info)
+{
+        u32 data = nvbios_M0205Se(bios, ent, idx, ver, hdr);
+        memset(info, 0x00, sizeof(*info));
+        switch (!!data * *ver) {
+        case 0x10:
+                info->data = nv_ro08(bios, data + 0x00);
+                return data;
+        default:
+                break;
+        }
+        return 0x00000000;
+}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c b/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c
new file mode 100644
index 000000000000..b142a510e89f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <subdev/bios.h>
+#include <subdev/bios/bit.h>
+#include <subdev/bios/M0209.h>
+
+u32
+nvbios_M0209Te(struct nouveau_bios *bios,
+               u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
+{
+        struct bit_entry bit_M;
+        u32 data = 0x00000000;
+
+        if (!bit_entry(bios, 'M', &bit_M)) {
+                if (bit_M.version == 2 && bit_M.length > 0x0c)
+                        data = nv_ro32(bios, bit_M.offset + 0x09);
+                if (data) {
+                        *ver = nv_ro08(bios, data + 0x00);
+                        switch (*ver) {
+                        case 0x10:
+                                *hdr = nv_ro08(bios, data + 0x01);
+                                *len = nv_ro08(bios, data + 0x02);
+                                *ssz = nv_ro08(bios, data + 0x03);
+                                *snr = 1;
+                                *cnt = nv_ro08(bios, data + 0x04);
+                                return data;
+                        default:
+                                break;
+                        }
+                }
+        }
+
+        return 0x00000000;
+}
+
+u32
+nvbios_M0209Ee(struct nouveau_bios *bios, int idx,
+               u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+{
+        u8  snr, ssz;
+        u32 data = nvbios_M0209Te(bios, ver, hdr, cnt, len, &snr, &ssz);
+        if (data && idx < *cnt) {
+                data = data + *hdr + idx * (*len + (snr * ssz));
+                *hdr = *len;
+                *cnt = snr;
+                *len = ssz;
+                return data;
+        }
+        return 0x00000000;
+}
+
+u32
+nvbios_M0209Ep(struct nouveau_bios *bios, int idx,
+               u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+               struct nvbios_M0209E *info)
+{
+        u32 data = nvbios_M0209Ee(bios, idx, ver, hdr, cnt, len);
+        memset(info, 0x00, sizeof(*info));
+        switch (!!data * *ver) {
+        case 0x10:
+                info->v00_40 = (nv_ro08(bios, data + 0x00) & 0x40) >> 6;
+                info->bits   =  nv_ro08(bios, data + 0x00) & 0x3f;
+                info->modulo =  nv_ro08(bios, data + 0x01);
+                info->v02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
+                info->v02_07 =  nv_ro08(bios, data + 0x02) & 0x07;
+                info->v03    =  nv_ro08(bios, data + 0x03);
+                return data;
+        default:
+                break;
+        }
+        return 0x00000000;
+}
+
+u32
+nvbios_M0209Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
+{
+
+        u8  cnt, len;
+        u32 data = nvbios_M0209Ee(bios, ent, ver, hdr, &cnt, &len);
+        if (data && idx < cnt) {
+                data = data + *hdr + idx * len;
+                *hdr = len;
+                return data;
+        }
+        return 0x00000000;
+}
+
+u32
+nvbios_M0209Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
+               struct nvbios_M0209S *info)
+{
+        struct nvbios_M0209E M0209E;
+        u8  cnt, len;
+        u32 data = nvbios_M0209Ep(bios, ent, ver, hdr, &cnt, &len, &M0209E);
+        if (data) {
+                u32 i, data = nvbios_M0209Se(bios, ent, idx, ver, hdr);
+                memset(info, 0x00, sizeof(*info));
+                switch (!!data * *ver) {
+                case 0x10:
+                        for (i = 0; i < ARRAY_SIZE(info->data); i++) {
+                                u32 bits = (i % M0209E.modulo) * M0209E.bits;
+                                u32 mask = (1ULL << M0209E.bits) - 1;
+                                u16  off = bits / 8;
+                                u8   mod = bits % 8;
+                                info->data[i] = nv_ro32(bios, data + off);
+                                info->data[i] = info->data[i] >> mod;
+                                info->data[i] = info->data[i] & mask;
+                        }
+                        return data;
+                default:
+                        break;
+                }
+        }
+        return 0x00000000;
+}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
index 88606bfaf847..bd8d348385b3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
@@ -124,6 +124,7 @@ dcb_outp_parse(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len,
                struct dcb_output *outp)
 {
         u16 dcb = dcb_outp(bios, idx, ver, len);
+        memset(outp, 0x00, sizeof(*outp));
         if (dcb) {
                 if (*ver >= 0x20) {
                         u32 conn = nv_ro32(bios, dcb + 0x00);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c b/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c
new file mode 100644
index 000000000000..e419892240f5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2014 Martin Peres
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Martin Peres
+ */
+
+#include <subdev/bios.h>
+#include <subdev/bios/bit.h>
+#include <subdev/bios/fan.h>
+
+u16
+nvbios_fan_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+{
+        struct bit_entry bit_P;
+        u16 fan = 0x0000;
+
+        if (!bit_entry(bios, 'P', &bit_P)) {
+                if (bit_P.version == 2 && bit_P.length >= 0x5a)
+                        fan = nv_ro16(bios, bit_P.offset + 0x58);
+
+                if (fan) {
+                        *ver = nv_ro08(bios, fan + 0);
+                        switch (*ver) {
+                        case 0x10:
+                                *hdr = nv_ro08(bios, fan + 1);
+                                *len = nv_ro08(bios, fan + 2);
+                                *cnt = nv_ro08(bios, fan + 3);
+                                return fan;
+                        default:
+                                break;
+                        }
+                }
+        }
+
+        return 0x0000;
+}
+
+u16
+nvbios_fan_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
+                 u8 *cnt, u8 *len)
+{
+        u16 data = nvbios_fan_table(bios, ver, hdr, cnt, len);
+        if (data && idx < *cnt)
+                return data + *hdr + (idx * (*len));
+        return 0x0000;
+}
+
+u16
+nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan)
+{
+        u8 ver, hdr, cnt, len;
+
+        u16 data = nvbios_fan_entry(bios, 0, &ver, &hdr, &cnt, &len);
+        if (data) {
+                u8 type = nv_ro08(bios, data + 0x00);
+                switch (type) {
+                case 0:
+                        fan->type = NVBIOS_THERM_FAN_TOGGLE;
+                        break;
+                case 1:
+                case 2:
+                        /* TODO: Understand the difference between the two! */
+                        fan->type = NVBIOS_THERM_FAN_PWM;
+                        break;
+                default:
+                        fan->type = NVBIOS_THERM_FAN_UNK;
+                }
+
+                fan->min_duty = nv_ro08(bios, data + 0x02);
+                fan->max_duty = nv_ro08(bios, data + 0x03);
+
+                fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff;
+        }
+        return data;
+}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
index 1811b2cb0472..585e69331ccc 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
@@ -75,31 +75,39 @@ nvbios_rammapEe(struct nouveau_bios *bios, int idx,
 }
 
 u32
-nvbios_rammapEm(struct nouveau_bios *bios, u16 khz,
-                u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
-{
-        int idx = 0;
-        u32 data;
-        while ((data = nvbios_rammapEe(bios, idx++, ver, hdr, cnt, len))) {
-                if (khz >= nv_ro16(bios, data + 0x00) &&
-                    khz <= nv_ro16(bios, data + 0x02))
-                        break;
-        }
-        return data;
-}
-
-u32
-nvbios_rammapEp(struct nouveau_bios *bios, u16 khz,
+nvbios_rammapEp(struct nouveau_bios *bios, int idx,
                 u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
                 struct nvbios_ramcfg *p)
 {
-        u32 data = nvbios_rammapEm(bios, khz, ver, hdr, cnt, len);
+        u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp;
         memset(p, 0x00, sizeof(*p));
+        p->rammap_ver = *ver;
+        p->rammap_hdr = *hdr;
         switch (!!data * *ver) {
+        case 0x10:
+                p->rammap_min      =  nv_ro16(bios, data + 0x00);
+                p->rammap_max      =  nv_ro16(bios, data + 0x02);
+                p->rammap_10_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1;
+                p->rammap_10_04_08 = (nv_ro08(bios, data + 0x04) & 0x08) >> 3;
+                break;
         case 0x11:
+                p->rammap_min      =  nv_ro16(bios, data + 0x00);
+                p->rammap_max      =  nv_ro16(bios, data + 0x02);
                 p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0;
                 p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2;
                 p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4;
+                temp = nv_ro32(bios, data + 0x09);
+                p->rammap_11_09_01ff = (temp & 0x000001ff) >> 0;
+                p->rammap_11_0a_03fe = (temp & 0x0003fe00) >> 9;
+                p->rammap_11_0a_0400 = (temp & 0x00040000) >> 18;
+                p->rammap_11_0a_0800 = (temp & 0x00080000) >> 19;
+                p->rammap_11_0b_01f0 = (temp & 0x01f00000) >> 20;
+                p->rammap_11_0b_0200 = (temp & 0x02000000) >> 25;
+                p->rammap_11_0b_0400 = (temp & 0x04000000) >> 26;
+                p->rammap_11_0b_0800 = (temp & 0x08000000) >> 27;
+                p->rammap_11_0d    =  nv_ro08(bios, data + 0x0d);
+                p->rammap_11_0e    =  nv_ro08(bios, data + 0x0e);
+                p->rammap_11_0f    =  nv_ro08(bios, data + 0x0f);
                 p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2;
                 break;
         default:
@@ -110,6 +118,20 @@ nvbios_rammapEp(struct nouveau_bios *bios, u16 khz,
 }
 
 u32
+nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz,
+                u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+                struct nvbios_ramcfg *info)
+{
+        int idx = 0;
+        u32 data;
+        while ((data = nvbios_rammapEp(bios, idx++, ver, hdr, cnt, len, info))) {
+                if (mhz >= info->rammap_min && mhz <= info->rammap_max)
+                        break;
+        }
+        return data;
+}
+
+u32
 nvbios_rammapSe(struct nouveau_bios *bios, u32 data,
                 u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
                 u8 *ver, u8 *hdr)
@@ -129,8 +151,28 @@ nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
                 u8 *ver, u8 *hdr, struct nvbios_ramcfg *p)
 {
         data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr);
+        p->ramcfg_ver = *ver;
+        p->ramcfg_hdr = *hdr;
         switch (!!data * *ver) {
+        case 0x10:
+                p->ramcfg_timing   =  nv_ro08(bios, data + 0x01);
+                p->ramcfg_10_02_01 = (nv_ro08(bios, data + 0x02) & 0x01) >> 0;
+                p->ramcfg_10_02_02 = (nv_ro08(bios, data + 0x02) & 0x02) >> 1;
+                p->ramcfg_10_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2;
+                p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
+                p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
+                p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5;
+                p->ramcfg_10_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
+                p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
+                p->ramcfg_10_05    = (nv_ro08(bios, data + 0x05) & 0xff) >> 0;
+                p->ramcfg_10_06    = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;
+                p->ramcfg_10_07    = (nv_ro08(bios, data + 0x07) & 0xff) >> 0;
+                p->ramcfg_10_08    = (nv_ro08(bios, data + 0x08) & 0xff) >> 0;
+                p->ramcfg_10_09_0f = (nv_ro08(bios, data + 0x09) & 0x0f) >> 0;
+                p->ramcfg_10_09_f0 = (nv_ro08(bios, data + 0x09) & 0xf0) >> 4;
+                break;
         case 0x11:
+                p->ramcfg_timing   =  nv_ro08(bios, data + 0x00);
                 p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0;
                 p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1;
                 p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
index 350d44ab2ba2..46d955eb51eb 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
@@ -89,7 +89,15 @@ nvbios_timingEp(struct nouveau_bios *bios, int idx,
                 struct nvbios_ramcfg *p)
 {
         u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
+        p->timing_ver = *ver;
+        p->timing_hdr = *hdr;
         switch (!!data * *ver) {
+        case 0x10:
+                p->timing_10_WR = nv_ro08(bios, data + 0x00);
+                p->timing_10_CL = nv_ro08(bios, data + 0x02);
+                p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
+                p->timing_10_CWL = nv_ro08(bios, data + 0x13);
+                break;
         case 0x20:
                 p->timing[0] = nv_ro32(bios, data + 0x00);
                 p->timing[1] = nv_ro32(bios, data + 0x04);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
index a276a711294a..e51b72d47129 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
@@ -573,7 +573,7 @@ nouveau_clock_create_(struct nouveau_object *parent,
 
         clk->allow_reclock = allow_reclock;
 
-        ret = nvkm_notify_init(&device->event, nouveau_clock_pwrsrc, true,
+        ret = nvkm_notify_init(NULL, &device->event, nouveau_clock_pwrsrc, true,
                                NULL, 0, 0, &clk->pwrsrc_ntfy);
         if (ret)
                 return ret;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
index 087012b18956..094551d8ad9b 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
@@ -20,8 +20,10 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Ben Skeggs
+ *          Roy Spliet
  */
 
+#include <engine/fifo.h>
 #include <subdev/bios.h>
 #include <subdev/bios/pll.h>
 #include <subdev/timer.h>
@@ -42,9 +44,17 @@ static u32
 read_vco(struct nva3_clock_priv *priv, int clk)
 {
         u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
-        if ((sctl & 0x00000030) != 0x00000030)
+
+        switch (sctl & 0x00000030) {
+        case 0x00000000:
+                return nv_device(priv)->crystal;
+        case 0x00000020:
                 return read_pll(priv, 0x41, 0x00e820);
-        return read_pll(priv, 0x42, 0x00e8a0);
+        case 0x00000030:
+                return read_pll(priv, 0x42, 0x00e8a0);
+        default:
+                return 0;
+        }
 }
 
 static u32
@@ -66,14 +76,25 @@ read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
         if (!ignore_en && !(sctl & 0x00000100))
                 return 0;
 
+        /* out_alt */
+        if (sctl & 0x00000400)
+                return 108000;
+
+        /* vco_out */
         switch (sctl & 0x00003000) {
         case 0x00000000:
-                return nv_device(priv)->crystal;
+                if (!(sctl & 0x00000200))
+                        return nv_device(priv)->crystal;
+                return 0;
         case 0x00002000:
                 if (sctl & 0x00000040)
                         return 108000;
                 return 100000;
         case 0x00003000:
+                /* vco_enable */
+                if (!(sctl & 0x00000001))
+                        return 0;
+
                 sclk = read_vco(priv, clk);
                 sdiv = ((sctl & 0x003f0000) >> 16) + 2;
                 return (sclk * 2) / sdiv;
@@ -95,7 +116,9 @@ read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
                         N = (coef & 0x0000ff00) >> 8;
                         P = (coef & 0x003f0000) >> 16;
 
-                        /* no post-divider on these.. */
+                        /* no post-divider on these..
+                         * XXX: it looks more like two post-"dividers" that
+                         * cross each other out in the default RPLL config */
                         if ((pll & 0x00ff00) == 0x00e800)
                                 P = 1;
 
@@ -114,13 +137,13 @@ static int
 nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
 {
         struct nva3_clock_priv *priv = (void *)clk;
+        u32 hsrc;
 
         switch (src) {
         case nv_clk_src_crystal:
                 return nv_device(priv)->crystal;
-        case nv_clk_src_href:
-                return 100000;
         case nv_clk_src_core:
+        case nv_clk_src_core_intm:
                 return read_pll(priv, 0x00, 0x4200);
         case nv_clk_src_shader:
                 return read_pll(priv, 0x01, 0x4220);
@@ -132,24 +155,33 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
                 return read_clk(priv, 0x21, false);
         case nv_clk_src_daemon:
                 return read_clk(priv, 0x25, false);
+        case nv_clk_src_host:
+                hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28;
+                switch (hsrc) {
+                case 0:
+                        return read_clk(priv, 0x1d, false);
+                case 2:
+                case 3:
+                        return 277000;
+                default:
+                        nv_error(clk, "unknown HOST clock source %d\n", hsrc);
+                        return -EINVAL;
+                }
         default:
                 nv_error(clk, "invalid clock source %d\n", src);
                 return -EINVAL;
         }
+
+        return 0;
 }
 
 int
-nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
+nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
                 struct nva3_clock_info *info)
 {
-        struct nouveau_bios *bios = nouveau_bios(clock);
         struct nva3_clock_priv *priv = (void *)clock;
-        struct nvbios_pll limits;
-        u32 oclk, sclk, sdiv;
-        int P, N, M, diff;
-        int ret;
+        u32 oclk, sclk, sdiv, diff;
 
-        info->pll = 0;
         info->clk = 0;
 
         switch (khz) {
@@ -164,43 +196,69 @@ nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
                 return khz;
         default:
                 sclk = read_vco(priv, clk);
-                sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
-                /* if the clock has a PLL attached, and we can get a within
-                 * [-2, 3) MHz of a divider, we'll disable the PLL and use
-                 * the divider instead.
-                 *
-                 * divider can go as low as 2, limited here because NVIDIA
+                sdiv = min((sclk * 2) / khz, (u32)65);
+                oclk = (sclk * 2) / sdiv;
+                diff = ((khz + 3000) - oclk);
+
+                /* When imprecise, play it safe and aim for a clock lower than
+                 * desired rather than higher */
+                if (diff < 0) {
+                        sdiv++;
+                        oclk = (sclk * 2) / sdiv;
+                }
+
+                /* divider can go as low as 2, limited here because NVIDIA
                  * and the VBIOS on my NVA8 seem to prefer using the PLL
                  * for 810MHz - is there a good reason?
-                 */
+                 * XXX: PLLs with refclk 810MHz?  */
                 if (sdiv > 4) {
-                        oclk = (sclk * 2) / sdiv;
-                        diff = khz - oclk;
-                        if (!pll || (diff >= -2000 && diff < 3000)) {
-                                info->clk = (((sdiv - 2) << 16) | 0x00003100);
-                                return oclk;
-                        }
+                        info->clk = (((sdiv - 2) << 16) | 0x00003100);
+                        return oclk;
                 }
 
-                if (!pll)
-                        return -ERANGE;
                 break;
         }
 
+        return -ERANGE;
+}
+
+int
+nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
+                struct nva3_clock_info *info)
+{
+        struct nouveau_bios *bios = nouveau_bios(clock);
+        struct nva3_clock_priv *priv = (void *)clock;
+        struct nvbios_pll limits;
+        int P, N, M, diff;
+        int ret;
+
+        info->pll = 0;
+
+        /* If we can get a within [-2, 3) MHz of a divider, we'll disable the
+         * PLL and use the divider instead. */
+        ret = nva3_clk_info(clock, clk, khz, info);
+        diff = khz - ret;
+        if (!pll || (diff >= -2000 && diff < 3000)) {
+                goto out;
+        }
+
+        /* Try with PLL */
         ret = nvbios_pll_parse(bios, pll, &limits);
         if (ret)
                 return ret;
 
-        limits.refclk = read_clk(priv, clk - 0x10, true);
-        if (!limits.refclk)
+        ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
+        if (ret != limits.refclk)
                 return -EINVAL;
 
         ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
         if (ret >= 0) {
-                info->clk = nv_rd32(priv, 0x4120 + (clk * 4));
                 info->pll = (P << 16) | (N << 8) | M;
         }
 
+out:
+        info->fb_delay = max(((khz + 7566) / 15133), (u32) 18);
+
         return ret ? ret : -ERANGE;
 }
 
@@ -208,13 +266,76 @@ static int
 calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
          int clk, u32 pll, int idx)
 {
-        int ret = nva3_clock_info(&priv->base, clk, pll, cstate->domain[idx],
+        int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
                                   &priv->eng[idx]);
         if (ret >= 0)
                 return 0;
         return ret;
 }
 
+static int
+calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
+{
+        int ret = 0;
+        u32 kHz = cstate->domain[nv_clk_src_host];
+        struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
+
+        if (kHz == 277000) {
+                info->clk = 0;
+                info->host_out = NVA3_HOST_277;
+                return 0;
+        }
+
+        info->host_out = NVA3_HOST_CLK;
+
+        ret = nva3_clk_info(&priv->base, 0x1d, kHz, info);
+        if (ret >= 0)
+                return 0;
+        return ret;
+}
+
+int
+nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags)
+{
+        struct nouveau_fifo *pfifo = nouveau_fifo(clk);
+
+        /* halt and idle execution engines */
+        nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
+        nv_mask(clk, 0x002504, 0x00000001, 0x00000001);
+        /* Wait until the interrupt handler is finished */
+        if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
+                return -EBUSY;
+
+        if (pfifo)
+                pfifo->pause(pfifo, flags);
+
+        if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
+                return -EIO;
+        if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
+                return -EIO;
+
+        return 0;
+}
+
+void
+nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags)
+{
+        struct nouveau_fifo *pfifo = nouveau_fifo(clk);
+
+        if (pfifo && flags)
+                pfifo->start(pfifo, flags);
+
+        nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
+        nv_mask(clk, 0x020060, 0x00070000, 0x00040000);
+}
+
+static void
+disable_clk_src(struct nva3_clock_priv *priv, u32 src)
+{
+        nv_mask(priv, src, 0x00000100, 0x00000000);
+        nv_mask(priv, src, 0x00000001, 0x00000000);
+}
+
 static void
 prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
 {
@@ -223,24 +344,35 @@ prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
         const u32 src1 = 0x004160 + (clk * 4);
         const u32 ctrl = pll + 0;
         const u32 coef = pll + 4;
+        u32 bypass;
 
         if (info->pll) {
-                nv_mask(priv, src0, 0x00000101, 0x00000101);
+                /* Always start from a non-PLL clock */
+                bypass = nv_rd32(priv, ctrl)  & 0x00000008;
+                if (!bypass) {
+                        nv_mask(priv, src1, 0x00000101, 0x00000101);
+                        nv_mask(priv, ctrl, 0x00000008, 0x00000008);
+                        udelay(20);
+                }
+
+                nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk);
                 nv_wr32(priv, coef, info->pll);
                 nv_mask(priv, ctrl, 0x00000015, 0x00000015);
                 nv_mask(priv, ctrl, 0x00000010, 0x00000000);
-                nv_wait(priv, ctrl, 0x00020000, 0x00020000);
+                if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) {
+                        nv_mask(priv, ctrl, 0x00000010, 0x00000010);
+                        nv_mask(priv, src0, 0x00000101, 0x00000000);
+                        return;
+                }
                 nv_mask(priv, ctrl, 0x00000010, 0x00000010);
                 nv_mask(priv, ctrl, 0x00000008, 0x00000000);
-                nv_mask(priv, src1, 0x00000100, 0x00000000);
-                nv_mask(priv, src1, 0x00000001, 0x00000000);
+                disable_clk_src(priv, src1);
         } else {
                 nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
                 nv_mask(priv, ctrl, 0x00000018, 0x00000018);
                 udelay(20);
                 nv_mask(priv, ctrl, 0x00000001, 0x00000000);
-                nv_mask(priv, src0, 0x00000100, 0x00000000);
-                nv_mask(priv, src0, 0x00000001, 0x00000000);
+                disable_clk_src(priv, src0);
         }
 }
 
@@ -251,18 +383,72 @@ prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
         nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
 }
 
+static void
+prog_host(struct nva3_clock_priv *priv)
+{
+        struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
+        u32 hsrc = (nv_rd32(priv, 0xc040));
+
+        switch (info->host_out) {
+        case NVA3_HOST_277:
+                if ((hsrc & 0x30000000) == 0) {
+                        nv_wr32(priv, 0xc040, hsrc | 0x20000000);
+                        disable_clk_src(priv, 0x4194);
+                }
+                break;
+        case NVA3_HOST_CLK:
+                prog_clk(priv, 0x1d, nv_clk_src_host);
+                if ((hsrc & 0x30000000) >= 0x20000000) {
+                        nv_wr32(priv, 0xc040, hsrc & ~0x30000000);
+                }
+                break;
+        default:
+                break;
+        }
+
+        /* This seems to be a clock gating factor on idle, always set to 64 */
+        nv_wr32(priv, 0xc044, 0x3e);
+}
+
+static void
+prog_core(struct nva3_clock_priv *priv, int idx)
+{
+        struct nva3_clock_info *info = &priv->eng[idx];
+        u32 fb_delay = nv_rd32(priv, 0x10002c);
+
+        if (fb_delay < info->fb_delay)
+                nv_wr32(priv, 0x10002c, info->fb_delay);
+
+        prog_pll(priv, 0x00, 0x004200, idx);
+
+        if (fb_delay > info->fb_delay)
+                nv_wr32(priv, 0x10002c, info->fb_delay);
+}
+
 static int
 nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
 {
         struct nva3_clock_priv *priv = (void *)clk;
+        struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
         int ret;
 
         if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
             (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
             (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
-            (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)))
+            (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) ||
+            (ret = calc_host(priv, cstate)))
                 return ret;
 
+        /* XXX: Should be reading the highest bit in the VBIOS clock to decide
+         * whether to use a PLL or not... but using a PLL defeats the purpose */
+        if (core->pll) {
+                ret = nva3_clk_info(clk, 0x10,
+                                cstate->domain[nv_clk_src_core_intm],
+                                &priv->eng[nv_clk_src_core_intm]);
+                if (ret < 0)
+                        return ret;
+        }
+
         return 0;
 }
 
@@ -270,11 +456,31 @@ static int
 nva3_clock_prog(struct nouveau_clock *clk)
 {
         struct nva3_clock_priv *priv = (void *)clk;
-        prog_pll(priv, 0x00, 0x004200, nv_clk_src_core);
+        struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
+        int ret = 0;
+        unsigned long flags;
+        unsigned long *f = &flags;
+
+        ret = nva3_clock_pre(clk, f);
+        if (ret)
+                goto out;
+
+        if (core->pll)
+                prog_core(priv, nv_clk_src_core_intm);
+
+        prog_core(priv,  nv_clk_src_core);
         prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
         prog_clk(priv, 0x20, nv_clk_src_disp);
         prog_clk(priv, 0x21, nv_clk_src_vdec);
-        return 0;
+        prog_host(priv);
+
+out:
+        if (ret == -EBUSY)
+                f = NULL;
+
+        nva3_clock_post(clk, f);
+
+        return ret;
 }
 
 static void
@@ -284,13 +490,14 @@ nva3_clock_tidy(struct nouveau_clock *clk)
 
 static struct nouveau_clocks
 nva3_domain[] = {
-        { nv_clk_src_crystal, 0xff },
-        { nv_clk_src_href   , 0xff },
-        { nv_clk_src_core   , 0x00, 0, "core", 1000 },
-        { nv_clk_src_shader , 0x01, 0, "shader", 1000 },
-        { nv_clk_src_mem    , 0x02, 0, "memory", 1000 },
-        { nv_clk_src_vdec   , 0x03 },
-        { nv_clk_src_disp   , 0x04 },
+        { nv_clk_src_crystal  , 0xff },
+        { nv_clk_src_core     , 0x00, 0, "core", 1000 },
+        { nv_clk_src_shader   , 0x01, 0, "shader", 1000 },
+        { nv_clk_src_mem      , 0x02, 0, "memory", 1000 },
+        { nv_clk_src_vdec     , 0x03 },
+        { nv_clk_src_disp     , 0x04 },
+        { nv_clk_src_host     , 0x05 },
+        { nv_clk_src_core_intm, 0x06 },
         { nv_clk_src_max }
 };
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h
index 6229a509b42e..a45a1038b12f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h
@@ -6,9 +6,15 @@
 struct nva3_clock_info {
         u32 clk;
         u32 pll;
+        enum {
+                NVA3_HOST_277,
+                NVA3_HOST_CLK,
+        } host_out;
+        u32 fb_delay;
 };
 
-int nva3_clock_info(struct nouveau_clock *, int, u32, u32,
+int nva3_pll_info(struct nouveau_clock *, int, u32, u32,
                     struct nva3_clock_info *);
-
+int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags);
+void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags);
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
index 74e19731b1b7..54aeab8005a0 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
@@ -28,6 +28,7 @@
 #include <subdev/timer.h>
 #include <subdev/clock.h>
 
+#include "nva3.h"
 #include "pll.h"
 
 struct nvaa_clock_priv {
@@ -299,25 +300,14 @@ static int
 nvaa_clock_prog(struct nouveau_clock *clk)
 {
         struct nvaa_clock_priv *priv = (void *)clk;
-        struct nouveau_fifo *pfifo = nouveau_fifo(clk);
+        u32 pllmask = 0, mast;
         unsigned long flags;
-        u32 pllmask = 0, mast, ptherm_gate;
-        int ret = -EBUSY;
-
-        /* halt and idle execution engines */
-        ptherm_gate = nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
-        nv_mask(clk, 0x002504, 0x00000001, 0x00000001);
-        /* Wait until the interrupt handler is finished */
-        if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
-                goto resume;
-
-        if (pfifo)
-                pfifo->pause(pfifo, &flags);
+        unsigned long *f = &flags;
+        int ret = 0;
 
-        if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
-                goto resume;
-        if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
-                goto resume;
+        ret = nva3_clock_pre(clk, f);
+        if (ret)
+                goto out;
 
         /* First switch to safe clocks: href */
         mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640);
@@ -375,15 +365,8 @@ nvaa_clock_prog(struct nouveau_clock *clk)
         }
 
         nv_wr32(clk, 0xc054, mast);
-        ret = 0;
 
 resume:
-        if (pfifo)
-                pfifo->start(pfifo, &flags);
-
-        nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
-        nv_wr32(clk, 0x020060, ptherm_gate);
-
         /* Disable some PLLs and dividers when unused */
         if (priv->csrc != nv_clk_src_core) {
                 nv_wr32(clk, 0x4040, 0x00000000);
@@ -395,6 +378,12 @@ resume:
                 nv_mask(clk, 0x4020, 0x80000000, 0x00000000);
         }
 
+out:
+        if (ret == -EBUSY)
+                f = NULL;
+
+        nva3_clock_post(clk, f);
+
         return ret;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h
index 4fe49cf4c99a..6103484fea72 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h
@@ -26,22 +26,8 @@
 
 #include <core/device.h>
 
-#define NV04_PFB_BOOT_0                                         0x00100000
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT                       0x00000003
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB                  0x00000000
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB                   0x00000001
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB                   0x00000002
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB                  0x00000003
-#       define NV04_PFB_BOOT_0_RAM_WIDTH_128                    0x00000004
-#       define NV04_PFB_BOOT_0_RAM_TYPE                         0x00000028
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT             0x00000000
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT            0x00000008
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK      0x00000010
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT            0x00000018
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT            0x00000020
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16         0x00000028
-#       define NV04_PFB_BOOT_0_UMA_ENABLE                       0x00000100
-#       define NV04_PFB_BOOT_0_UMA_SIZE                         0x0000f000
+#include <subdev/fb/regsnv04.h>
+
 #define NV04_PFB_DEBUG_0                                        0x00100080
 #       define NV04_PFB_DEBUG_0_PAGE_MODE                       0x00000001
 #       define NV04_PFB_DEBUG_0_REFRESH_OFF                     0x00000010
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c
index 66fe959b4f74..7fbbe05d5c60 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c
@@ -40,7 +40,7 @@ nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
         int WL, CL, WR, at[2], dt, ds;
         int rq = ram->freq < 1000000; /* XXX */
 
-        switch (ram->ramcfg.version) {
+        switch (ram->next->bios.ramcfg_ver) {
         case 0x11:
                 pd =  ram->next->bios.ramcfg_11_01_80;
                 lf =  ram->next->bios.ramcfg_11_01_40;
@@ -54,7 +54,7 @@ nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
                 return -ENOSYS;
         }
 
-        switch (ram->timing.version) {
+        switch (ram->next->bios.timing_ver) {
         case 0x20:
                 WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
                 CL = (ram->next->bios.timing[1] & 0x0000001f);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
index f003c1b1893f..2209ade63339 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
@@ -45,7 +45,7 @@ nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
         u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-        if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
+        if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
                 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */
                 else              tile->zcomp = 0x04000000; /* Z24S8 */
                 tile->zcomp |= tile->tag->offset;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c
index f34f4223210b..e2a66c355c50 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c
@@ -32,7 +32,7 @@ nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
         u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-        if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
+        if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
                 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */
                 else              tile->zcomp = 0x00200000; /* Z24S8 */
                 tile->zcomp |= tile->tag->offset;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c
index 69093f7151f0..cbec402ba5b9 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c
@@ -51,7 +51,7 @@ nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
         u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-        if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
+        if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
                 if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */
                 else           tile->zcomp |= 0x02000000; /* Z24S8 */
                 tile->zcomp |= ((tile->tag->offset           ) >> 6);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c
index 161b06e8fc3f..b2cf8c69fb2e 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c
@@ -32,7 +32,7 @@ nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
         u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-        if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
+        if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
                 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */
                 else           tile->zcomp |= 0x08000000; /* Z24S8 */
                 tile->zcomp |= ((tile->tag->offset           ) >> 6);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c
index 2dd3d0aab6bb..b4cdae2a3b2f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c
@@ -32,7 +32,7 @@ nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
         u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-        if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
+        if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
                 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */
                 else           tile->zcomp |= 0x20000000; /* Z24S8 */
                 tile->zcomp |= ((tile->tag->offset           ) >> 6);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
index 95a115ab0c86..52814258c212 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
@@ -33,7 +33,7 @@ nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
         u32 tiles = DIV_ROUND_UP(size, 0x80);
         u32 tags  = round_up(tiles / pfb->ram->parts, 0x100);
         if ( (flags & 2) &&
-            !nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
+            !nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
                 tile->zcomp  = 0x28000000; /* Z24S8_SPLIT_GRAD */
                 tile->zcomp |= ((tile->tag->offset           ) >> 8);
                 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
index 82273f832e42..60322e906dd4 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
@@ -35,6 +35,7 @@ extern struct nouveau_oclass nve0_ram_oclass;
 extern struct nouveau_oclass gk20a_ram_oclass;
 extern struct nouveau_oclass gm107_ram_oclass;
 
+int nouveau_sddr2_calc(struct nouveau_ram *ram);
 int nouveau_sddr3_calc(struct nouveau_ram *ram);
 int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts);
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
index 2af9cfd2c60f..d1fbbe4b00a2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
@@ -12,16 +12,32 @@ struct ramfuc {
 struct ramfuc_reg {
         int sequence;
         bool force;
-        u32 addr[2];
+        u32 addr;
+        u32 stride; /* in bytes */
+        u32 mask;
         u32 data;
 };
 
 static inline struct ramfuc_reg
+ramfuc_stride(u32 addr, u32 stride, u32 mask)
+{
+        return (struct ramfuc_reg) {
+                .sequence = 0,
+                .addr = addr,
+                .stride = stride,
+                .mask = mask,
+                .data = 0xdeadbeef,
+        };
+}
+
+static inline struct ramfuc_reg
 ramfuc_reg2(u32 addr1, u32 addr2)
 {
         return (struct ramfuc_reg) {
                 .sequence = 0,
-                .addr = { addr1, addr2 },
+                .addr = addr1,
+                .stride = addr2 - addr1,
+                .mask = 0x3,
                 .data = 0xdeadbeef,
         };
 }
@@ -29,7 +45,13 @@ ramfuc_reg2(u32 addr1, u32 addr2)
 static noinline struct ramfuc_reg
 ramfuc_reg(u32 addr)
 {
-        return ramfuc_reg2(addr, addr);
+        return (struct ramfuc_reg) {
+                .sequence = 0,
+                .addr = addr,
+                .stride = 0,
+                .mask = 0x1,
+                .data = 0xdeadbeef,
+        };
 }
 
 static inline int
@@ -62,18 +84,25 @@ static inline u32
 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg)
 {
         if (reg->sequence != ram->sequence)
-                reg->data = nv_rd32(ram->pfb, reg->addr[0]);
+                reg->data = nv_rd32(ram->pfb, reg->addr);
         return reg->data;
 }
 
 static inline void
 ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data)
 {
+        unsigned int mask, off = 0;
+
         reg->sequence = ram->sequence;
         reg->data = data;
-        if (reg->addr[0] != reg->addr[1])
-                nouveau_memx_wr32(ram->memx, reg->addr[1], reg->data);
-        nouveau_memx_wr32(ram->memx, reg->addr[0], reg->data);
+
+        for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) {
+                if (mask & 1) {
+                        nouveau_memx_wr32(ram->memx, reg->addr+off, reg->data);
+                }
+
+                off += reg->stride;
+        }
 }
 
 static inline void
@@ -105,14 +134,35 @@ ramfuc_nsec(struct ramfuc *ram, u32 nsec)
         nouveau_memx_nsec(ram->memx, nsec);
 }
 
-#define ram_init(s,p)       ramfuc_init(&(s)->base, (p))
-#define ram_exec(s,e)       ramfuc_exec(&(s)->base, (e))
-#define ram_have(s,r)       ((s)->r_##r.addr[0] != 0x000000)
-#define ram_rd32(s,r)       ramfuc_rd32(&(s)->base, &(s)->r_##r)
-#define ram_wr32(s,r,d)     ramfuc_wr32(&(s)->base, &(s)->r_##r, (d))
-#define ram_nuke(s,r)       ramfuc_nuke(&(s)->base, &(s)->r_##r)
-#define ram_mask(s,r,m,d)   ramfuc_mask(&(s)->base, &(s)->r_##r, (m), (d))
-#define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n))
-#define ram_nsec(s,n)       ramfuc_nsec(&(s)->base, (n))
+static inline void
+ramfuc_wait_vblank(struct ramfuc *ram)
+{
+        nouveau_memx_wait_vblank(ram->memx);
+}
+
+static inline void
+ramfuc_block(struct ramfuc *ram)
+{
+        nouveau_memx_block(ram->memx);
+}
+
+static inline void
+ramfuc_unblock(struct ramfuc *ram)
+{
+        nouveau_memx_unblock(ram->memx);
+}
+
+#define ram_init(s,p)        ramfuc_init(&(s)->base, (p))
+#define ram_exec(s,e)        ramfuc_exec(&(s)->base, (e))
+#define ram_have(s,r)        ((s)->r_##r.addr != 0x000000)
+#define ram_rd32(s,r)        ramfuc_rd32(&(s)->base, &(s)->r_##r)
+#define ram_wr32(s,r,d)      ramfuc_wr32(&(s)->base, &(s)->r_##r, (d))
+#define ram_nuke(s,r)        ramfuc_nuke(&(s)->base, &(s)->r_##r)
+#define ram_mask(s,r,m,d)    ramfuc_mask(&(s)->base, &(s)->r_##r, (m), (d))
+#define ram_wait(s,r,m,d,n)  ramfuc_wait(&(s)->base, (r), (m), (d), (n))
+#define ram_nsec(s,n)        ramfuc_nsec(&(s)->base, (n))
+#define ram_wait_vblank(s)   ramfuc_wait_vblank(&(s)->base)
+#define ram_block(s)         ramfuc_block(&(s)->base)
+#define ram_unblock(s)       ramfuc_unblock(&(s)->base)
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c
index e781080d3327..1972268d1410 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c
@@ -22,22 +22,7 @@
  * Authors: Ben Skeggs
  */
 
-#define NV04_PFB_BOOT_0                                         0x00100000
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT                       0x00000003
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB                  0x00000000
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB                   0x00000001
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB                   0x00000002
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB                  0x00000003
-#       define NV04_PFB_BOOT_0_RAM_WIDTH_128                    0x00000004
-#       define NV04_PFB_BOOT_0_RAM_TYPE                         0x00000028
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT             0x00000000
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT            0x00000008
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK      0x00000010
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT            0x00000018
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT            0x00000020
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16         0x00000028
-#       define NV04_PFB_BOOT_0_UMA_ENABLE                       0x00000100
-#       define NV04_PFB_BOOT_0_UMA_SIZE                         0x0000f000
+#include <subdev/fb/regsnv04.h>
 
 #include "priv.h"
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
index e5d12c24cc43..64a983c96625 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
@@ -280,7 +280,7 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
                 if (align == 16) {
                         int n = (max >> 4) * comp;
 
-                        ret = nouveau_mm_head(tags, 1, n, n, 1, &mem->tag);
+                        ret = nouveau_mm_head(tags, 0, 1, n, n, 1, &mem->tag);
                         if (ret)
                                 mem->tag = NULL;
                 }
@@ -296,9 +296,9 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
         type = nv50_fb_memtype[type];
         do {
                 if (back)
-                        ret = nouveau_mm_tail(heap, type, max, min, align, &r);
+                        ret = nouveau_mm_tail(heap, 0, type, max, min, align, &r);
                 else
-                        ret = nouveau_mm_head(heap, type, max, min, align, &r);
+                        ret = nouveau_mm_head(heap, 0, type, max, min, align, &r);
                 if (ret) {
                         mutex_unlock(&pfb->base.mutex);
                         pfb->ram->put(pfb, &mem);
@@ -319,27 +319,22 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
 static u32
 nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram)
 {
-        int i, parts, colbits, rowbitsa, rowbitsb, banks;
+        int colbits, rowbitsa, rowbitsb, banks;
         u64 rowsize, predicted;
-        u32 r0, r4, rt, ru, rblock_size;
+        u32 r0, r4, rt, rblock_size;
 
         r0 = nv_rd32(pfb, 0x100200);
         r4 = nv_rd32(pfb, 0x100204);
         rt = nv_rd32(pfb, 0x100250);
-        ru = nv_rd32(pfb, 0x001540);
-        nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
-
-        for (i = 0, parts = 0; i < 8; i++) {
-                if (ru & (0x00010000 << i))
-                        parts++;
-        }
+        nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt,
+                        nv_rd32(pfb, 0x001540));
 
         colbits  =  (r4 & 0x0000f000) >> 12;
         rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
         rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
         banks    = 1 << (((r4 & 0x03000000) >> 24) + 2);
 
-        rowsize = parts * banks * (1 << colbits) * 8;
+        rowsize = ram->parts * banks * (1 << colbits) * 8;
         predicted = rowsize << rowbitsa;
         if (r0 & 0x00000004)
                 predicted += rowsize << rowbitsb;
@@ -376,6 +371,9 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
         ram->size = nv_rd32(pfb, 0x10020c);
         ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32);
 
+        ram->part_mask = (nv_rd32(pfb, 0x001540) & 0x00ff0000) >> 16;
+        ram->parts = hweight8(ram->part_mask);
+
         switch (nv_rd32(pfb, 0x100714) & 0x00000007) {
         case 0: ram->type = NV_MEM_TYPE_DDR1; break;
         case 1:
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
index 8076fb195dd5..3601deca0bd5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
@@ -79,20 +79,27 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
         struct nva3_ram *ram = (void *)pfb->ram;
         struct nva3_ramfuc *fuc = &ram->fuc;
         struct nva3_clock_info mclk;
-        u8  ver, cnt, len, strap;
+        struct nouveau_ram_data *next;
+        u8  ver, hdr, cnt, len, strap;
         u32 data;
-        struct {
-                u32 data;
-                u8  size;
-        } rammap, ramcfg, timing;
         u32 r004018, r100760, ctrl;
         u32 unk714, unk718, unk71c;
-        int ret;
+        int ret, i;
+
+        next = &ram->base.target;
+        next->freq = freq;
+        ram->base.next = next;
 
         /* lookup memory config data relevant to the target frequency */
-        rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
-                                     &cnt, &ramcfg.size);
-        if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
+        i = 0;
+        while ((data = nvbios_rammapEp(bios, i++, &ver, &hdr, &cnt, &len,
+                                      &next->bios))) {
+                if (freq / 1000 >= next->bios.rammap_min &&
+                    freq / 1000 <= next->bios.rammap_max)
+                        break;
+        }
+
+        if (!data || ver != 0x10 || hdr < 0x0e) {
                 nv_error(pfb, "invalid/missing rammap entry\n");
                 return -EINVAL;
         }
@@ -104,26 +111,25 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
                 return -EINVAL;
         }
 
-        ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
-        if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
+        data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap,
+                               &ver, &hdr, &next->bios);
+        if (!data || ver != 0x10 || hdr < 0x0e) {
                 nv_error(pfb, "invalid/missing ramcfg entry\n");
                 return -EINVAL;
         }
 
         /* lookup memory timings, if bios says they're present */
-        strap = nv_ro08(bios, ramcfg.data + 0x01);
-        if (strap != 0xff) {
-                timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
-                                             &cnt, &len);
-                if (!timing.data || ver != 0x10 || timing.size < 0x19) {
+        if (next->bios.ramcfg_timing != 0xff) {
+                data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
+                                       &ver, &hdr, &cnt, &len,
+                                       &next->bios);
+                if (!data || ver != 0x10 || hdr < 0x19) {
                         nv_error(pfb, "invalid/missing timing entry\n");
                         return -EINVAL;
                 }
-        } else {
-                timing.data = 0;
         }
 
-        ret = nva3_clock_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
+        ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
         if (ret < 0) {
                 nv_error(pfb, "failed mclk calculation\n");
                 return ret;
@@ -163,17 +169,17 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
                 ram_mask(fuc, 0x004168, 0x003f3141, ctrl);
         }
 
-        if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
+        if (next->bios.ramcfg_10_02_10) {
                 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
         } else {
                 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
         }
 
-        if (!(nv_ro08(bios, rammap.data + 0x04) & 0x02))
+        if (!next->bios.rammap_10_04_02)
                 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
         ram_wr32(fuc, 0x611200, 0x00003300);
-        if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x10))
+        if (!next->bios.ramcfg_10_02_10)
                 ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/
 
         ram_wr32(fuc, 0x1002d4, 0x00000001);
@@ -202,17 +208,16 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
                 ram_wr32(fuc, 0x004018, 0x0000d000 | r004018);
         }
 
-        if ( (nv_ro08(bios, rammap.data + 0x04) & 0x08)) {
-                u32 unk5a0 = (nv_ro16(bios, ramcfg.data + 0x05) << 8) |
-                              nv_ro08(bios, ramcfg.data + 0x05);
-                u32 unk5a4 = (nv_ro16(bios, ramcfg.data + 0x07));
-                u32 unk804 = (nv_ro08(bios, ramcfg.data + 0x09) & 0xf0) << 16 |
-                             (nv_ro08(bios, ramcfg.data + 0x03) & 0x0f) << 16 |
-                             (nv_ro08(bios, ramcfg.data + 0x09) & 0x0f) |
-                             0x80000000;
-                ram_wr32(fuc, 0x1005a0, unk5a0);
-                ram_wr32(fuc, 0x1005a4, unk5a4);
-                ram_wr32(fuc, 0x10f804, unk804);
+        if (next->bios.rammap_10_04_08) {
+                ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 |
+                                        next->bios.ramcfg_10_05 << 8 |
+                                        next->bios.ramcfg_10_05);
+                ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 |
+                                        next->bios.ramcfg_10_07);
+                ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 |
+                                        next->bios.ramcfg_10_03_0f << 16 |
+                                        next->bios.ramcfg_10_09_0f |
+                                        0x80000000);
                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
         } else {
                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
@@ -250,27 +255,26 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
         ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000);
         ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000);
 
-        data = (nv_ro08(bios, ramcfg.data + 0x02) & 0x08) ? 0x00000000 : 0x00001000;
-        ram_mask(fuc, 0x100200, 0x00001000, data);
+        ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12);
 
         unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010;
         unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100;
         unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
-        if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x20))
+        if (next->bios.ramcfg_10_02_20)
                 unk714 |= 0xf0000000;
-        if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x04))
+        if (!next->bios.ramcfg_10_02_04)
                 unk714 |= 0x00000010;
         ram_wr32(fuc, 0x100714, unk714);
 
-        if (nv_ro08(bios, ramcfg.data + 0x02) & 0x01)
+        if (next->bios.ramcfg_10_02_01)
                 unk71c |= 0x00000100;
         ram_wr32(fuc, 0x10071c, unk71c);
 
-        if (nv_ro08(bios, ramcfg.data + 0x02) & 0x02)
+        if (next->bios.ramcfg_10_02_02)
                 unk718 |= 0x00000100;
         ram_wr32(fuc, 0x100718, unk718);
 
-        if (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)
+        if (next->bios.ramcfg_10_02_10)
                 ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/
 
         ram_mask(fuc, mr[0], 0x100, 0x100);
@@ -282,9 +286,9 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
         ram_nsec(fuc, 12000);
 
         ram_wr32(fuc, 0x611200, 0x00003330);
-        if ( (nv_ro08(bios, rammap.data + 0x04) & 0x02))
+        if (next->bios.rammap_10_04_02)
                 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
-        if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
+        if (next->bios.ramcfg_10_02_10) {
                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
                 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
         } else {
@@ -404,11 +408,11 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         ram->fuc.r_0x100714 = ramfuc_reg(0x100714);
         ram->fuc.r_0x100718 = ramfuc_reg(0x100718);
         ram->fuc.r_0x10071c = ramfuc_reg(0x10071c);
-        ram->fuc.r_0x100760 = ramfuc_reg(0x100760);
-        ram->fuc.r_0x1007a0 = ramfuc_reg(0x1007a0);
-        ram->fuc.r_0x1007e0 = ramfuc_reg(0x1007e0);
+        ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask);
+        ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask);
+        ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask);
         ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804);
-        ram->fuc.r_0x1110e0 = ramfuc_reg(0x1110e0);
+        ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask);
         ram->fuc.r_0x111100 = ramfuc_reg(0x111100);
         ram->fuc.r_0x111104 = ramfuc_reg(0x111104);
         ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
index 2b284b192763..735cb9580abe 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
@@ -133,6 +133,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
         struct nouveau_bios *bios = nouveau_bios(pfb);
         struct nvc0_ram *ram = (void *)pfb->ram;
         struct nvc0_ramfuc *fuc = &ram->fuc;
+        struct nvbios_ramcfg cfg;
         u8  ver, cnt, len, strap;
         struct {
                 u32 data;
@@ -145,7 +146,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
 
         /* lookup memory config data relevant to the target frequency */
         rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
-                                     &cnt, &ramcfg.size);
+                                     &cnt, &ramcfg.size, &cfg);
         if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
                 nv_error(pfb, "invalid/missing rammap entry\n");
                 return -EINVAL;
@@ -483,9 +484,9 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
 
         do {
                 if (back)
-                        ret = nouveau_mm_tail(mm, 1, size, ncmin, align, &r);
+                        ret = nouveau_mm_tail(mm, 0, 1, size, ncmin, align, &r);
                 else
-                        ret = nouveau_mm_head(mm, 1, size, ncmin, align, &r);
+                        ret = nouveau_mm_head(mm, 0, 1, size, ncmin, align, &r);
                 if (ret) {
                         mutex_unlock(&pfb->base.mutex);
                         pfb->ram->put(pfb, &mem);
@@ -562,7 +563,7 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
                 offset = (0x0200000000ULL >> 12) + (bsize << 8);
                 length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail;
 
-                ret = nouveau_mm_init(&pfb->vram, offset, length, 0);
+                ret = nouveau_mm_init(&pfb->vram, offset, length, 1);
                 if (ret)
                         nouveau_mm_fini(&pfb->vram);
         }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
index c5b46e302319..6bae474abb44 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
@@ -29,6 +29,8 @@
 #include <subdev/bios/init.h>
 #include <subdev/bios/rammap.h>
 #include <subdev/bios/timing.h>
+#include <subdev/bios/M0205.h>
+#include <subdev/bios/M0209.h>
 
 #include <subdev/clock.h>
 #include <subdev/clock/pll.h>
@@ -41,14 +43,6 @@
 
 #include "ramfuc.h"
 
-/* binary driver only executes this path if the condition (a) is true
- * for any configuration (combination of rammap+ramcfg+timing) that
- * can be reached on a given card.  for now, we will execute the branch
- * unconditionally in the hope that a "false everywhere" in the bios
- * tables doesn't actually mean "don't touch this".
- */
-#define NOTE00(a) 1
-
 struct nve0_ramfuc {
         struct ramfuc base;
 
@@ -134,10 +128,12 @@ struct nve0_ram {
         struct nouveau_ram base;
         struct nve0_ramfuc fuc;
 
+        struct list_head cfg;
         u32 parts;
         u32 pmask;
         u32 pnuts;
 
+        struct nvbios_ramcfg diff;
         int from;
         int mode;
         int N1, fN1, M1, P1;
@@ -241,7 +237,7 @@ nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
 {
         struct nve0_fb_priv *priv = (void *)nouveau_fb(ram);
         struct ramfuc *fuc = &ram->fuc.base;
-        u32 addr = 0x110000 + (reg->addr[0] & 0xfff);
+        u32 addr = 0x110000 + (reg->addr & 0xfff);
         u32 mask = _mask | _copy;
         u32 data = (_data & _mask) | (reg->data & _copy);
         u32 i;
@@ -268,6 +264,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         u32 mask, data;
 
         ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
+        ram_block(fuc);
         ram_wr32(fuc, 0x62c000, 0x0f0f0000);
 
         /* MR1: turn termination on early, for some reason.. */
@@ -478,7 +475,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
 
         data = mask = 0x00000000;
-        if (NOTE00(ramcfg_08_20)) {
+        if (ram->diff.ramcfg_11_08_20) {
                 if (next->bios.ramcfg_11_08_20)
                         data |= 0x01000000;
                 mask |= 0x01000000;
@@ -486,11 +483,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         ram_mask(fuc, 0x10f200, mask, data);
 
         data = mask = 0x00000000;
-        if (NOTE00(ramcfg_02_03 != 0)) {
+        if (ram->diff.ramcfg_11_02_03) {
                 data |= next->bios.ramcfg_11_02_03 << 8;
                 mask |= 0x00000300;
         }
-        if (NOTE00(ramcfg_01_10)) {
+        if (ram->diff.ramcfg_11_01_10) {
                 if (next->bios.ramcfg_11_01_10)
                         data |= 0x70000000;
                 mask |= 0x70000000;
@@ -498,11 +495,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         ram_mask(fuc, 0x10f604, mask, data);
 
         data = mask = 0x00000000;
-        if (NOTE00(timing_30_07 != 0)) {
+        if (ram->diff.timing_20_30_07) {
                 data |= next->bios.timing_20_30_07 << 28;
                 mask |= 0x70000000;
         }
-        if (NOTE00(ramcfg_01_01)) {
+        if (ram->diff.ramcfg_11_01_01) {
                 if (next->bios.ramcfg_11_01_01)
                         data |= 0x00000100;
                 mask |= 0x00000100;
@@ -510,11 +507,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         ram_mask(fuc, 0x10f614, mask, data);
 
         data = mask = 0x00000000;
-        if (NOTE00(timing_30_07 != 0)) {
+        if (ram->diff.timing_20_30_07) {
                 data |= next->bios.timing_20_30_07 << 28;
                 mask |= 0x70000000;
         }
-        if (NOTE00(ramcfg_01_02)) {
+        if (ram->diff.ramcfg_11_01_02) {
                 if (next->bios.ramcfg_11_01_02)
                         data |= 0x00000100;
                 mask |= 0x00000100;
@@ -548,11 +545,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
 
         data = mask = 0x00000000;
-        if (NOTE00(ramcfg_02_03 != 0)) {
+        if (ram->diff.ramcfg_11_02_03) {
                 data |= next->bios.ramcfg_11_02_03;
                 mask |= 0x00000003;
         }
-        if (NOTE00(ramcfg_01_10)) {
+        if (ram->diff.ramcfg_11_01_10) {
                 if (next->bios.ramcfg_11_01_10)
                         data |= 0x00000004;
                 mask |= 0x00000004;
@@ -666,6 +663,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
         if (next->bios.ramcfg_11_07_02)
                 nve0_ram_train(fuc, 0x80020000, 0x01000000);
 
+        ram_unblock(fuc);
         ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
 
         if (next->bios.rammap_11_08_01)
@@ -695,6 +693,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
         u32 mask, data;
 
         ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
+        ram_block(fuc);
         ram_wr32(fuc, 0x62c000, 0x0f0f0000);
 
         if (vc == 1 && ram_have(fuc, gpio2E)) {
@@ -917,6 +916,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
         ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
         ram_nsec(fuc, 1000);
 
+        ram_unblock(fuc);
         ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
 
         if (next->bios.rammap_11_08_01)
@@ -932,58 +932,24 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
  ******************************************************************************/
 
 static int
-nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq,
+nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz,
                    struct nouveau_ram_data *data)
 {
-        struct nouveau_bios *bios = nouveau_bios(pfb);
         struct nve0_ram *ram = (void *)pfb->ram;
-        u8 strap, cnt, len;
-
-        /* lookup memory config data relevant to the target frequency */
-        ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000,
-                                               &ram->base.rammap.version,
-                                               &ram->base.rammap.size,
-                                               &cnt, &len, &data->bios);
-        if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 ||
-             ram->base.rammap.size < 0x09) {
-                nv_error(pfb, "invalid/missing rammap entry\n");
-                return -EINVAL;
-        }
-
-        /* locate specific data set for the attached memory */
-        strap = nvbios_ramcfg_index(nv_subdev(pfb));
-        ram->base.ramcfg.data = nvbios_rammapSp(bios, ram->base.rammap.data,
-                                                ram->base.rammap.version,
-                                                ram->base.rammap.size,
-                                                cnt, len, strap,
-                                                &ram->base.ramcfg.version,
-                                                &ram->base.ramcfg.size,
-                                                &data->bios);
-        if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 ||
-             ram->base.ramcfg.size < 0x08) {
-                nv_error(pfb, "invalid/missing ramcfg entry\n");
-                return -EINVAL;
-        }
-
-        /* lookup memory timings, if bios says they're present */
-        strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00);
-        if (strap != 0xff) {
-                ram->base.timing.data =
-                        nvbios_timingEp(bios, strap, &ram->base.timing.version,
-                                       &ram->base.timing.size, &cnt, &len,
-                                       &data->bios);
-                if (!ram->base.timing.data ||
-                     ram->base.timing.version != 0x20 ||
-                     ram->base.timing.size < 0x33) {
-                        nv_error(pfb, "invalid/missing timing entry\n");
-                        return -EINVAL;
+        struct nouveau_ram_data *cfg;
+        u32 mhz = khz / 1000;
+
+        list_for_each_entry(cfg, &ram->cfg, head) {
+                if (mhz >= cfg->bios.rammap_min &&
+                    mhz <= cfg->bios.rammap_max) {
+                        *data = *cfg;
+                        data->freq = khz;
+                        return 0;
                 }
-        } else {
-                ram->base.timing.data = 0;
         }
 
-        data->freq = freq;
-        return 0;
+        nv_error(ram, "ramcfg data for %dMHz not found\n", mhz);
+        return -EINVAL;
 }
 
 static int
@@ -1106,13 +1072,99 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
         return nve0_ram_calc_xits(pfb, ram->base.next);
 }
 
+static void
+nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq)
+{
+        struct nve0_ram *ram = (void *)pfb->ram;
+        struct nouveau_ram_data *cfg;
+        u32 mhz = freq / 1000;
+        u32 mask, data;
+
+        list_for_each_entry(cfg, &ram->cfg, head) {
+                if (mhz >= cfg->bios.rammap_min &&
+                    mhz <= cfg->bios.rammap_max)
+                        break;
+        }
+
+        if (&cfg->head == &ram->cfg)
+                return;
+
+        if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) {
+                data |= cfg->bios.rammap_11_0a_03fe << 12;
+                mask |= 0x001ff000;
+        }
+        if (ram->diff.rammap_11_09_01ff) {
+                data |= cfg->bios.rammap_11_09_01ff;
+                mask |= 0x000001ff;
+        }
+        nv_mask(pfb, 0x10f468, mask, data);
+
+        if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) {
+                data |= cfg->bios.rammap_11_0a_0400;
+                mask |= 0x00000001;
+        }
+        nv_mask(pfb, 0x10f420, mask, data);
+
+        if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) {
+                data |= cfg->bios.rammap_11_0a_0800;
+                mask |= 0x00000001;
+        }
+        nv_mask(pfb, 0x10f430, mask, data);
+
+        if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) {
+                data |= cfg->bios.rammap_11_0b_01f0;
+                mask |= 0x0000001f;
+        }
+        nv_mask(pfb, 0x10f400, mask, data);
+
+        if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) {
+                data |= cfg->bios.rammap_11_0b_0200 << 9;
+                mask |= 0x00000200;
+        }
+        nv_mask(pfb, 0x10f410, mask, data);
+
+        if (mask = 0, data = 0, ram->diff.rammap_11_0d) {
+                data |= cfg->bios.rammap_11_0d << 16;
+                mask |= 0x00ff0000;
+        }
+        if (ram->diff.rammap_11_0f) {
+                data |= cfg->bios.rammap_11_0f << 8;
+                mask |= 0x0000ff00;
+        }
+        nv_mask(pfb, 0x10f440, mask, data);
+
+        if (mask = 0, data = 0, ram->diff.rammap_11_0e) {
+                data |= cfg->bios.rammap_11_0e << 8;
+                mask |= 0x0000ff00;
+        }
+        if (ram->diff.rammap_11_0b_0800) {
+                data |= cfg->bios.rammap_11_0b_0800 << 7;
+                mask |= 0x00000080;
+        }
+        if (ram->diff.rammap_11_0b_0400) {
+                data |= cfg->bios.rammap_11_0b_0400 << 5;
+                mask |= 0x00000020;
+        }
+        nv_mask(pfb, 0x10f444, mask, data);
+}
+
 static int
 nve0_ram_prog(struct nouveau_fb *pfb)
 {
         struct nouveau_device *device = nv_device(pfb);
         struct nve0_ram *ram = (void *)pfb->ram;
         struct nve0_ramfuc *fuc = &ram->fuc;
-        ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true));
+        struct nouveau_ram_data *next = ram->base.next;
+
+        if (!nouveau_boolopt(device->cfgopt, "NvMemExec", true)) {
+                ram_exec(fuc, false);
+                return (ram->base.next == &ram->base.xition);
+        }
+
+        nve0_ram_prog_0(pfb, 1000);
+        ram_exec(fuc, true);
+        nve0_ram_prog_0(pfb, next->freq);
+
         return (ram->base.next == &ram->base.xition);
 }
 
@@ -1125,24 +1177,147 @@ nve0_ram_tidy(struct nouveau_fb *pfb)
         ram_exec(fuc, false);
 }
 
+struct nve0_ram_train {
+        u16 mask;
+        struct nvbios_M0209S remap;
+        struct nvbios_M0209S type00;
+        struct nvbios_M0209S type01;
+        struct nvbios_M0209S type04;
+        struct nvbios_M0209S type06;
+        struct nvbios_M0209S type07;
+        struct nvbios_M0209S type08;
+        struct nvbios_M0209S type09;
+};
+
+static int
+nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg,
+                    struct nve0_ram_train *train)
+{
+        struct nouveau_bios *bios = nouveau_bios(pfb);
+        struct nvbios_M0205E M0205E;
+        struct nvbios_M0205S M0205S;
+        struct nvbios_M0209E M0209E;
+        struct nvbios_M0209S *remap = &train->remap;
+        struct nvbios_M0209S *value;
+        u8  ver, hdr, cnt, len;
+        u32 data;
+
+        /* determine type of data for this index */
+        if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)))
+                return -ENOENT;
+
+        switch (M0205E.type) {
+        case 0x00: value = &train->type00; break;
+        case 0x01: value = &train->type01; break;
+        case 0x04: value = &train->type04; break;
+        case 0x06: value = &train->type06; break;
+        case 0x07: value = &train->type07; break;
+        case 0x08: value = &train->type08; break;
+        case 0x09: value = &train->type09; break;
+        default:
+                return 0;
+        }
+
+        /* training data index determined by ramcfg strap */
+        if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S)))
+                return -EINVAL;
+        i = M0205S.data;
+
+        /* training data format information */
+        if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E)))
+                return -EINVAL;
+
+        /* ... and the raw data */
+        if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value)))
+                return -EINVAL;
+
+        if (M0209E.v02_07 == 2) {
+                /* of course! why wouldn't we have a pointer to another entry
+                 * in the same table, and use the first one as an array of
+                 * remap indices...
+                 */
+                if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr,
+                                            remap)))
+                        return -EINVAL;
+
+                for (i = 0; i < ARRAY_SIZE(value->data); i++)
+                        value->data[i] = remap->data[value->data[i]];
+        } else
+        if (M0209E.v02_07 != 1)
+                return -EINVAL;
+
+        train->mask |= 1 << M0205E.type;
+        return 0;
+}
+
+static int
+nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train)
+{
+        int i, j;
+
+        if ((train->mask & 0x03d3) != 0x03d3) {
+                nv_warn(pfb, "missing link training data\n");
+                return -EINVAL;
+        }
+
+        for (i = 0; i < 0x30; i++) {
+                for (j = 0; j < 8; j += 4) {
+                        nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8));
+                        nv_wr32(pfb, 0x10f920 + j, 0x00000000 |
+                                                   train->type08.data[i] << 4 |
+                                                   train->type06.data[i]);
+                        nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]);
+                        nv_wr32(pfb, 0x10f920 + j, 0x00000100 |
+                                                   train->type09.data[i] << 4 |
+                                                   train->type07.data[i]);
+                        nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]);
+                }
+        }
+
+        for (j = 0; j < 8; j += 4) {
+                for (i = 0; i < 0x100; i++) {
+                        nv_wr32(pfb, 0x10f968 + j, i);
+                        nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]);
+                }
+        }
+
+        return 0;
+}
+
+static int
+nve0_ram_train_init(struct nouveau_fb *pfb)
+{
+        u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
+        struct nve0_ram_train *train;
+        int ret = -ENOMEM, i;
+
+        if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) {
+                for (i = 0; i < 0x100; i++) {
+                        ret = nve0_ram_train_type(pfb, i, ramcfg, train);
+                        if (ret && ret != -ENOENT)
+                                break;
+                }
+        }
+
+        switch (pfb->ram->type) {
+        case NV_MEM_TYPE_GDDR5:
+                ret = nve0_ram_train_init_0(pfb, train);
+                break;
+        default:
+                ret = 0;
+                break;
+        }
+
+        kfree(train);
+        return ret;
+}
+
 int
 nve0_ram_init(struct nouveau_object *object)
 {
         struct nouveau_fb *pfb = (void *)object->parent;
         struct nve0_ram *ram   = (void *)object;
         struct nouveau_bios *bios = nouveau_bios(pfb);
-        static const u8  train0[] = {
-                0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
-                0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
-        };
-        static const u32 train1[] = {
-                0x00000000, 0xffffffff,
-                0x55555555, 0xaaaaaaaa,
-                0x33333333, 0xcccccccc,
-                0xf0f0f0f0, 0x0f0f0f0f,
-                0x00ff00ff, 0xff00ff00,
-                0x0000ffff, 0xffff0000,
-        };
         u8  ver, hdr, cnt, len, snr, ssz;
         u32 data, save;
         int ret, i;
@@ -1168,51 +1343,107 @@ nve0_ram_init(struct nouveau_object *object)
 
         cnt  = nv_ro08(bios, data + 0x14); /* guess at count */
         data = nv_ro32(bios, data + 0x10); /* guess u32... */
-        save = nv_rd32(pfb, 0x10f65c);
-        for (i = 0; i < cnt; i++) {
-                nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4);
-                nvbios_exec(&(struct nvbios_init) {
-                                .subdev = nv_subdev(pfb),
-                                .bios = bios,
-                                .offset = nv_ro32(bios, data), /* guess u32 */
-                                .execute = 1,
-                            });
-                data += 4;
-        }
-        nv_wr32(pfb, 0x10f65c, save);
+        save = nv_rd32(pfb, 0x10f65c) & 0x000000f0;
+        for (i = 0; i < cnt; i++, data += 4) {
+                if (i != save >> 4) {
+                        nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4);
+                        nvbios_exec(&(struct nvbios_init) {
+                                        .subdev = nv_subdev(pfb),
+                                        .bios = bios,
+                                        .offset = nv_ro32(bios, data),
+                                        .execute = 1,
+                                    });
+                }
+        }
+        nv_mask(pfb, 0x10f65c, 0x000000f0, save);
         nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000);
+        nv_wr32(pfb, 0x10ecc0, 0xffffffff);
+        nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010);
 
-        switch (ram->base.type) {
-        case NV_MEM_TYPE_GDDR5:
-                for (i = 0; i < 0x30; i++) {
-                        nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8));
-                        nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]);
-                        nv_wr32(pfb, 0x10f918,              train1[i % 12]);
-                        nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]);
-                        nv_wr32(pfb, 0x10f918,              train1[i % 12]);
-
-                        nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8));
-                        nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]);
-                        nv_wr32(pfb, 0x10f91c,              train1[i % 12]);
-                        nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]);
-                        nv_wr32(pfb, 0x10f91c,              train1[i % 12]);
-                }
+        return nve0_ram_train_init(pfb);
+}
 
-                for (i = 0; i < 0x100; i++) {
-                        nv_wr32(pfb, 0x10f968, i);
-                        nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]);
-                }
+static int
+nve0_ram_ctor_data(struct nve0_ram *ram, u8 ramcfg, int i)
+{
+        struct nouveau_fb *pfb = (void *)nv_object(ram)->parent;
+        struct nouveau_bios *bios = nouveau_bios(pfb);
+        struct nouveau_ram_data *cfg;
+        struct nvbios_ramcfg *d = &ram->diff;
+        struct nvbios_ramcfg *p, *n;
+        u8  ver, hdr, cnt, len;
+        u32 data;
+        int ret;
 
-                for (i = 0; i < 0x100; i++) {
-                        nv_wr32(pfb, 0x10f96c, i);
-                        nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]);
-                }
-                break;
-        default:
-                break;
+        if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL)))
+                return -ENOMEM;
+        p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios;
+        n = &cfg->bios;
+
+        /* memory config data for a range of target frequencies */
+        data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios);
+        if (ret = -ENOENT, !data)
+                goto done;
+        if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12)
+                goto done;
+
+        /* ... and a portion specific to the attached memory */
+        data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg,
+                               &ver, &hdr, &cfg->bios);
+        if (ret = -EINVAL, !data)
+                goto done;
+        if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a)
+                goto done;
+
+        /* lookup memory timings, if bios says they're present */
+        if (cfg->bios.ramcfg_timing != 0xff) {
+                data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing,
+                                       &ver, &hdr, &cnt, &len,
+                                       &cfg->bios);
+                if (ret = -EINVAL, !data)
+                        goto done;
+                if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33)
+                        goto done;
         }
 
-        return 0;
+        list_add_tail(&cfg->head, &ram->cfg);
+        if (ret = 0, i == 0)
+                goto done;
+
+        d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe;
+        d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff;
+        d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400;
+        d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800;
+        d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0;
+        d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200;
+        d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d;
+        d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f;
+        d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e;
+        d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800;
+        d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400;
+        d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01;
+        d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02;
+        d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10;
+        d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03;
+        d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20;
+        d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07;
+done:
+        if (ret)
+                kfree(cfg);
+        return ret;
+}
+
+static void
+nve0_ram_dtor(struct nouveau_object *object)
+{
+        struct nve0_ram *ram = (void *)object;
+        struct nouveau_ram_data *cfg, *tmp;
+
+        list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) {
+                kfree(cfg);
+        }
+
+        nouveau_ram_destroy(&ram->base);
 }
 
 static int
@@ -1226,6 +1457,7 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct dcb_gpio_func func;
         struct nve0_ram *ram;
         int ret, i;
+        u8  ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
         u32 tmp;
 
         ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram);
@@ -1233,6 +1465,8 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        INIT_LIST_HEAD(&ram->cfg);
+
         switch (ram->base.type) {
         case NV_MEM_TYPE_DDR3:
         case NV_MEM_TYPE_GDDR5:
@@ -1264,7 +1498,26 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 }
         }
 
-        // parse bios data for both pll's
+        /* parse bios data for all rammap table entries up-front, and
+         * build information on whether certain fields differ between
+         * any of the entries.
+         *
+         * the binary driver appears to completely ignore some fields
+         * when all entries contain the same value.  at first, it was
+         * hoped that these were mere optimisations and the bios init
+         * tables had configured as per the values here, but there is
+         * evidence now to suggest that this isn't the case and we do
+         * need to treat this condition as a "don't touch" indicator.
+         */
+        for (i = 0; !ret; i++) {
+                ret = nve0_ram_ctor_data(ram, ramcfg, i);
+                if (ret && ret != -ENOENT) {
+                        nv_error(pfb, "failed to parse ramcfg data\n");
+                        return ret;
+                }
+        }
+
+        /* parse bios data for both pll's */
         ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
         if (ret) {
                 nv_error(pfb, "mclk refpll data not found\n");
@@ -1277,6 +1530,7 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 return ret;
         }
 
+        /* lookup memory voltage gpios */
         ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
         if (ret == 0) {
                 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
@@ -1385,7 +1639,7 @@ nve0_ram_oclass = {
         .handle = 0,
         .ofuncs = &(struct nouveau_ofuncs) {
                 .ctor = nve0_ram_ctor,
-                .dtor = _nouveau_ram_dtor,
+                .dtor = nve0_ram_dtor,
                 .init = nve0_ram_init,
                 .fini = _nouveau_ram_fini,
         }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c
new file mode 100644
index 000000000000..bb1eb8f3e639
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2014 Roy Spliet
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Roy Spliet <rspliet@eclipso.eu>
+ *          Ben Skeggs
+ */
+
+#include "priv.h"
+
+struct ramxlat {
+        int id;
+        u8 enc;
+};
+
+static inline int
+ramxlat(const struct ramxlat *xlat, int id)
+{
+        while (xlat->id >= 0) {
+                if (xlat->id == id)
+                        return xlat->enc;
+                xlat++;
+        }
+        return -EINVAL;
+}
+
+static const struct ramxlat
+ramddr2_cl[] = {
+        { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 },
+        /* The following are available in some, but not all DDR2 docs */
+        { 7, 7 },
+        { -1 }
+};
+
+static const struct ramxlat
+ramddr2_wr[] = {
+        { 2, 1 }, { 3, 2 }, { 4, 3 }, { 5, 4 }, { 6, 5 },
+        /* The following are available in some, but not all DDR2 docs */
+        { 7, 6 },
+        { -1 }
+};
+
+int
+nouveau_sddr2_calc(struct nouveau_ram *ram)
+{
+        int CL, WR, DLL = 0, ODT = 0;
+
+        switch (ram->next->bios.timing_ver) {
+        case 0x10:
+                CL  = ram->next->bios.timing_10_CL;
+                WR  = ram->next->bios.timing_10_WR;
+                DLL = !ram->next->bios.ramcfg_10_02_40;
+                ODT = ram->next->bios.timing_10_ODT & 3;
+                break;
+        case 0x20:
+                CL  = (ram->next->bios.timing[1] & 0x0000001f);
+                WR  = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
+                break;
+        default:
+                return -ENOSYS;
+        }
+
+        CL  = ramxlat(ramddr2_cl, CL);
+        WR  = ramxlat(ramddr2_wr, WR);
+        if (CL < 0 || WR < 0)
+                return -EINVAL;
+
+        ram->mr[0] &= ~0xf70;
+        ram->mr[0] |= (WR & 0x07) << 9;
+        ram->mr[0] |= (CL & 0x07) << 4;
+
+        ram->mr[1] &= ~0x045;
+        ram->mr[1] |= (ODT & 0x1) << 2;
+        ram->mr[1] |= (ODT & 0x2) << 5;
+        ram->mr[1] |= !DLL;
+        return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
index ebd4cd9c35d9..83949b11833a 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
@@ -20,9 +20,9 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Ben Skeggs <bskeggs@redhat.com>
+ *          Roy Spliet <rspliet@eclipso.eu>
  */
 
-#include <subdev/bios.h>
 #include "priv.h"
 
 struct ramxlat {
@@ -69,31 +69,52 @@ ramddr3_cwl[] = {
 int
 nouveau_sddr3_calc(struct nouveau_ram *ram)
 {
-        struct nouveau_bios *bios = nouveau_bios(ram);
-        int WL, CL, WR;
+        int CWL, CL, WR, DLL = 0, ODT = 0;
 
-        switch (!!ram->timing.data * ram->timing.version) {
+        switch (ram->next->bios.timing_ver) {
+        case 0x10:
+                if (ram->next->bios.timing_hdr < 0x17) {
+                        /* XXX: NV50: Get CWL from the timing register */
+                        return -ENOSYS;
+                }
+                CWL = ram->next->bios.timing_10_CWL;
+                CL  = ram->next->bios.timing_10_CL;
+                WR  = ram->next->bios.timing_10_WR;
+                DLL = !ram->next->bios.ramcfg_10_02_40;
+                ODT = ram->next->bios.timing_10_ODT;
+                break;
         case 0x20:
-                WL = (nv_ro16(bios, ram->timing.data + 0x04) & 0x0f80) >> 7;
-                CL =  nv_ro08(bios, ram->timing.data + 0x04) & 0x1f;
-                WR =  nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f;
+                CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
+                CL  = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
+                WR  = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
+                /* XXX: Get these values from the VBIOS instead */
+                DLL = !(ram->mr[1] & 0x1);
+                ODT =   (ram->mr[1] & 0x004) >> 2 |
+                        (ram->mr[1] & 0x040) >> 5 |
+                        (ram->mr[1] & 0x200) >> 7;
                 break;
         default:
                 return -ENOSYS;
         }
 
-        WL = ramxlat(ramddr3_cwl, WL);
-        CL = ramxlat(ramddr3_cl, CL);
-        WR = ramxlat(ramddr3_wr, WR);
-        if (WL < 0 || CL < 0 || WR < 0)
+        CWL = ramxlat(ramddr3_cwl, CWL);
+        CL  = ramxlat(ramddr3_cl, CL);
+        WR  = ramxlat(ramddr3_wr, WR);
+        if (CL < 0 || CWL < 0 || WR < 0)
                 return -EINVAL;
 
-        ram->mr[0] &= ~0xe74;
+        ram->mr[0] &= ~0xf74;
         ram->mr[0] |= (WR & 0x07) << 9;
         ram->mr[0] |= (CL & 0x0e) << 3;
         ram->mr[0] |= (CL & 0x01) << 2;
 
+        ram->mr[1] &= ~0x245;
+        ram->mr[1] |= (ODT & 0x1) << 2;
+        ram->mr[1] |= (ODT & 0x2) << 5;
+        ram->mr[1] |= (ODT & 0x4) << 7;
+        ram->mr[1] |= !DLL;
+
         ram->mr[2] &= ~0x038;
-        ram->mr[2] |= (WL & 0x07) << 3;
+        ram->mr[2] |= (CWL & 0x07) << 3;
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c
new file mode 100644
index 000000000000..9e8e92127715
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2014 Martin Peres
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Martin Peres
+ */
+
+#include <subdev/fuse.h>
+
+int
+_nouveau_fuse_init(struct nouveau_object *object)
+{
+        struct nouveau_fuse *fuse = (void *)object;
+        return nouveau_subdev_init(&fuse->base);
+}
+
+void
+_nouveau_fuse_dtor(struct nouveau_object *object)
+{
+        struct nouveau_fuse *fuse = (void *)object;
+        nouveau_subdev_destroy(&fuse->base);
+}
+
+int
+nouveau_fuse_create_(struct nouveau_object *parent,
+                     struct nouveau_object *engine,
+                     struct nouveau_oclass *oclass, int length, void **pobject)
+{
+        struct nouveau_fuse *fuse;
+        int ret;
+
+        ret = nouveau_subdev_create_(parent, engine, oclass, 0, "FUSE",
+                                     "fuse", length, pobject);
+        fuse = *pobject;
+
+        return ret;
+}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c
new file mode 100644
index 000000000000..a374ade485be
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2014 Martin Peres
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Martin Peres
+ */
+
+#include "priv.h"
+
+struct g80_fuse_priv {
+        struct nouveau_fuse base;
+
+        spinlock_t fuse_enable_lock;
+};
+
+static u32
+g80_fuse_rd32(struct nouveau_object *object, u64 addr)
+{
+        struct g80_fuse_priv *priv = (void *)object;
+        unsigned long flags;
+        u32 fuse_enable, val;
+
+        spin_lock_irqsave(&priv->fuse_enable_lock, flags);
+
+        /* racy if another part of nouveau start writing to this reg */
+        fuse_enable = nv_mask(priv, 0x1084, 0x800, 0x800);
+        val = nv_rd32(priv, 0x21000 + addr);
+        nv_wr32(priv, 0x1084, fuse_enable);
+
+        spin_unlock_irqrestore(&priv->fuse_enable_lock, flags);
+
+        return val;
+}
+
+
+static int
+g80_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+               struct nouveau_oclass *oclass, void *data, u32 size,
+               struct nouveau_object **pobject)
+{
+        struct g80_fuse_priv *priv;
+        int ret;
+
+        ret = nouveau_fuse_create(parent, engine, oclass, &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        spin_lock_init(&priv->fuse_enable_lock);
+
+        return 0;
+}
+
+struct nouveau_oclass
+g80_fuse_oclass = {
+        .handle = NV_SUBDEV(FUSE, 0x50),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = g80_fuse_ctor,
+                .dtor = _nouveau_fuse_dtor,
+                .init = _nouveau_fuse_init,
+                .fini = _nouveau_fuse_fini,
+                .rd32 = g80_fuse_rd32,
+        },
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c
new file mode 100644
index 000000000000..5ed03f54b3d4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2014 Martin Peres
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Martin Peres
+ */
+
+#include "priv.h"
+
+struct gf100_fuse_priv {
+        struct nouveau_fuse base;
+
+        spinlock_t fuse_enable_lock;
+};
+
+static u32
+gf100_fuse_rd32(struct nouveau_object *object, u64 addr)
+{
+        struct gf100_fuse_priv *priv = (void *)object;
+        unsigned long flags;
+        u32 fuse_enable, unk, val;
+
+        spin_lock_irqsave(&priv->fuse_enable_lock, flags);
+
+        /* racy if another part of nouveau start writing to these regs */
+        fuse_enable = nv_mask(priv, 0x22400, 0x800, 0x800);
+        unk = nv_mask(priv, 0x21000, 0x1, 0x1);
+        val = nv_rd32(priv, 0x21100 + addr);
+        nv_wr32(priv, 0x21000, unk);
+        nv_wr32(priv, 0x22400, fuse_enable);
+
+        spin_unlock_irqrestore(&priv->fuse_enable_lock, flags);
+
+        return val;
+}
+
+
+static int
+gf100_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+               struct nouveau_oclass *oclass, void *data, u32 size,
+               struct nouveau_object **pobject)
+{
+        struct gf100_fuse_priv *priv;
+        int ret;
+
+        ret = nouveau_fuse_create(parent, engine, oclass, &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        spin_lock_init(&priv->fuse_enable_lock);
+
+        return 0;
+}
+
+struct nouveau_oclass
+gf100_fuse_oclass = {
+        .handle = NV_SUBDEV(FUSE, 0xC0),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = gf100_fuse_ctor,
+                .dtor = _nouveau_fuse_dtor,
+                .init = _nouveau_fuse_init,
+                .fini = _nouveau_fuse_fini,
+                .rd32 = gf100_fuse_rd32,
+        },
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c
new file mode 100644
index 000000000000..4f1a636c6538
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2014 Martin Peres
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Martin Peres
+ */
+
+#include "priv.h"
+
+struct gm107_fuse_priv {
+        struct nouveau_fuse base;
+};
+
+static u32
+gm107_fuse_rd32(struct nouveau_object *object, u64 addr)
+{
+        struct gf100_fuse_priv *priv = (void *)object;
+
+        return nv_rd32(priv, 0x21100 + addr);
+}
+
+
+static int
+gm107_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+               struct nouveau_oclass *oclass, void *data, u32 size,
+               struct nouveau_object **pobject)
+{
+        struct gm107_fuse_priv *priv;
+        int ret;
+
+        ret = nouveau_fuse_create(parent, engine, oclass, &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+struct nouveau_oclass
+gm107_fuse_oclass = {
+        .handle = NV_SUBDEV(FUSE, 0x117),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = gm107_fuse_ctor,
+                .dtor = _nouveau_fuse_dtor,
+                .init = _nouveau_fuse_init,
+                .fini = _nouveau_fuse_fini,
+                .rd32 = gm107_fuse_rd32,
+        },
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h
new file mode 100644
index 000000000000..d2085411a5cb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h
@@ -0,0 +1,9 @@
+#ifndef __NVKM_FUSE_PRIV_H__
+#define __NVKM_FUSE_PRIV_H__
+
+#include <subdev/fuse.h>
+
+int _nouveau_fuse_init(struct nouveau_object *object);
+void _nouveau_fuse_dtor(struct nouveau_object *object);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
index b1e3ed7c8beb..7ad99b763f4c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
@@ -122,7 +122,8 @@ nouveau_gpio_intr_init(struct nvkm_event *event, int type, int index)
 }
 
 static int
-nouveau_gpio_intr_ctor(void *data, u32 size, struct nvkm_notify *notify)
+nouveau_gpio_intr_ctor(struct nouveau_object *object, void *data, u32 size,
+                       struct nvkm_notify *notify)
 {
         struct nvkm_gpio_ntfy_req *req = data;
         if (!WARN_ON(size != sizeof(*req))) {
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv92.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c
index 252083d376f5..cae404ccadac 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv92.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c
@@ -25,7 +25,7 @@
 #include "priv.h"
 
 void
-nv92_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
+nv94_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
 {
         u32 intr0 = nv_rd32(gpio, 0x00e054);
         u32 intr1 = nv_rd32(gpio, 0x00e074);
@@ -38,7 +38,7 @@ nv92_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
 }
 
 void
-nv92_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
+nv94_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
 {
         u32 inte0 = nv_rd32(gpio, 0x00e050);
         u32 inte1 = nv_rd32(gpio, 0x00e070);
@@ -57,8 +57,8 @@ nv92_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
 }
 
 struct nouveau_oclass *
-nv92_gpio_oclass = &(struct nouveau_gpio_impl) {
-        .base.handle = NV_SUBDEV(GPIO, 0x92),
+nv94_gpio_oclass = &(struct nouveau_gpio_impl) {
+        .base.handle = NV_SUBDEV(GPIO, 0x94),
         .base.ofuncs = &(struct nouveau_ofuncs) {
                 .ctor = _nouveau_gpio_ctor,
                 .dtor = _nouveau_gpio_dtor,
@@ -66,8 +66,8 @@ nv92_gpio_oclass = &(struct nouveau_gpio_impl) {
                 .fini = _nouveau_gpio_fini,
         },
         .lines = 32,
-        .intr_stat = nv92_gpio_intr_stat,
-        .intr_mask = nv92_gpio_intr_mask,
+        .intr_stat = nv94_gpio_intr_stat,
+        .intr_mask = nv94_gpio_intr_mask,
         .drive = nv50_gpio_drive,
         .sense = nv50_gpio_sense,
         .reset = nv50_gpio_reset,
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
index a4682b0956ad..480d6d2af770 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
@@ -77,8 +77,8 @@ nvd0_gpio_oclass = &(struct nouveau_gpio_impl) {
                 .fini = _nouveau_gpio_fini,
         },
         .lines = 32,
-        .intr_stat = nv92_gpio_intr_stat,
-        .intr_mask = nv92_gpio_intr_mask,
+        .intr_stat = nv94_gpio_intr_stat,
+        .intr_mask = nv94_gpio_intr_mask,
         .drive = nvd0_gpio_drive,
         .sense = nvd0_gpio_sense,
         .reset = nvd0_gpio_reset,
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h
index e1724dfc86ae..bff98b86e2b5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h
@@ -56,8 +56,8 @@ void nv50_gpio_reset(struct nouveau_gpio *, u8);
 int  nv50_gpio_drive(struct nouveau_gpio *, int, int, int);
 int  nv50_gpio_sense(struct nouveau_gpio *, int);
 
-void nv92_gpio_intr_stat(struct nouveau_gpio *, u32 *, u32 *);
-void nv92_gpio_intr_mask(struct nouveau_gpio *, u32, u32, u32);
+void nv94_gpio_intr_stat(struct nouveau_gpio *, u32 *, u32 *);
+void nv94_gpio_intr_mask(struct nouveau_gpio *, u32, u32, u32);
 
 void nvd0_gpio_reset(struct nouveau_gpio *, u8);
 int  nvd0_gpio_drive(struct nouveau_gpio *, int, int, int);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
index a652cafde3d6..2b1bf545e488 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
@@ -23,6 +23,7 @@
  */
 
 #include <core/option.h>
+#include <core/object.h>
 #include <core/event.h>
 
 #include <subdev/bios.h>
@@ -346,7 +347,8 @@ nouveau_i2c_intr_init(struct nvkm_event *event, int type, int index)
 }
 
 static int
-nouveau_i2c_intr_ctor(void *data, u32 size, struct nvkm_notify *notify)
+nouveau_i2c_intr_ctor(struct nouveau_object *object, void *data, u32 size,
+                      struct nvkm_notify *notify)
 {
         struct nvkm_i2c_ntfy_req *req = data;
         if (!WARN_ON(size != sizeof(*req))) {
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c
index 7b64befee48f..e8b1401c59c0 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c
@@ -69,7 +69,7 @@ nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
-        ret = nouveau_mm_head(&priv->heap, 1, args->size, args->size,
+        ret = nouveau_mm_head(&priv->heap, 0, 1, args->size, args->size,
                               args->align, &node->mem);
         if (ret)
                 return ret;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c
index 32ed442c5913..7fa331516f84 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c
@@ -31,7 +31,7 @@ nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n,
         struct nvkm_ltc_priv *priv = (void *)ltc;
         int ret;
 
-        ret = nouveau_mm_head(&priv->tags, 1, n, n, 1, pnode);
+        ret = nouveau_mm_head(&priv->tags, 0, 1, n, n, 1, pnode);
         if (ret)
                 *pnode = NULL;
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
index b54b582e72c4..e7b7872481ef 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
@@ -62,16 +62,38 @@ gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth)
         nv_wr32(priv, 0x17ea58, depth);
 }
 
+static const struct nouveau_bitfield
+gf100_ltc_lts_intr_name[] = {
+        { 0x00000001, "IDLE_ERROR_IQ" },
+        { 0x00000002, "IDLE_ERROR_CBC" },
+        { 0x00000004, "IDLE_ERROR_TSTG" },
+        { 0x00000008, "IDLE_ERROR_DSTG" },
+        { 0x00000010, "EVICTED_CB" },
+        { 0x00000020, "ILLEGAL_COMPSTAT" },
+        { 0x00000040, "BLOCKLINEAR_CB" },
+        { 0x00000100, "ECC_SEC_ERROR" },
+        { 0x00000200, "ECC_DED_ERROR" },
+        { 0x00000400, "DEBUG" },
+        { 0x00000800, "ATOMIC_TO_Z" },
+        { 0x00001000, "ILLEGAL_ATOMIC" },
+        { 0x00002000, "BLKACTIVITY_ERR" },
+        {}
+};
+
 static void
-gf100_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
+gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts)
 {
         u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400);
-        u32 stat = nv_rd32(priv, base + 0x020);
+        u32 intr = nv_rd32(priv, base + 0x020);
+        u32 stat = intr & 0x0000ffff;
 
         if (stat) {
-                nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", ltc, lts, stat);
-                nv_wr32(priv, base + 0x020, stat);
+                nv_info(priv, "LTC%d_LTS%d:", ltc, lts);
+                nouveau_bitfield_print(gf100_ltc_lts_intr_name, stat);
+                pr_cont("\n");
         }
+
+        nv_wr32(priv, base + 0x020, intr);
 }
 
 void
@@ -84,14 +106,9 @@ gf100_ltc_intr(struct nouveau_subdev *subdev)
         while (mask) {
                 u32 lts, ltc = __ffs(mask);
                 for (lts = 0; lts < priv->lts_nr; lts++)
-                        gf100_ltc_lts_isr(priv, ltc, lts);
+                        gf100_ltc_lts_intr(priv, ltc, lts);
                 mask &= ~(1 << ltc);
         }
-
-        /* we do something horribly wrong and upset PMFB a lot, so mask off
-         * interrupts from it after the first one until it's fixed
-         */
-        nv_mask(priv, 0x000640, 0x02000000, 0x00000000);
 }
 
 static int
@@ -151,7 +168,7 @@ gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv)
         tag_size += tag_align;
         tag_size  = (tag_size + 0xfff) >> 12; /* round up */
 
-        ret = nouveau_mm_tail(&pfb->vram, 1, tag_size, tag_size, 1,
+        ret = nouveau_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1,
                               &priv->tag_ram);
         if (ret) {
                 priv->num_tags = 0;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
index 4761b2e9af00..a26bed86f384 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
@@ -87,11 +87,6 @@ gm107_ltc_intr(struct nouveau_subdev *subdev)
                         gm107_ltc_lts_isr(priv, ltc, lts);
                 mask &= ~(1 << ltc);
         }
-
-        /* we do something horribly wrong and upset PMFB a lot, so mask off
-         * interrupts from it after the first one until it's fixed
-         */
-        nv_mask(priv, 0x000640, 0x02000000, 0x00000000);
 }
 
 static int
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h
index 594924f39126..41f179d93da6 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h
@@ -4,6 +4,8 @@
 #include <subdev/ltc.h>
 #include <subdev/fb.h>
 
+#include <core/enum.h>
+
 struct nvkm_ltc_priv {
         struct nouveau_ltc base;
         u32 ltc_nr;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
index 69f1f34f6931..0ab55f27ec45 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
@@ -203,6 +203,8 @@ _nouveau_pwr_init(struct nouveau_object *object)
         nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000);
         nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000);
         nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000);
+        nv_rd32(ppwr, 0x000200);
+        nv_wait(ppwr, 0x10a10c, 0x00000006, 0x00000000);
 
         /* upload data segment */
         nv_wr32(ppwr, 0x10a1c0, 0x01000000);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc
new file mode 100644
index 000000000000..214a6d9e088d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2014 Martin Peres <martin.peres@free.fr>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the folloing conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Martin Peres
+ */
+
+/******************************************************************************
+ * arith data segment
+ *****************************************************************************/
+#ifdef INCLUDE_PROC
+#endif
+
+#ifdef INCLUDE_DATA
+#endif
+
+/******************************************************************************
+ * arith code segment
+ *****************************************************************************/
+#ifdef INCLUDE_CODE
+
+// does a 32x32 -> 64 multiplication
+//
+// A * B = A_lo * B_lo
+//        + ( A_hi * B_lo ) << 16
+//        + ( A_lo * B_hi ) << 16
+//        + ( A_hi * B_hi ) << 32
+//
+// $r15 - current
+// $r14 - A
+// $r13 - B
+// $r12 - mul_lo (return)
+// $r11 - mul_hi (return)
+// $r0  - zero
+mulu32_32_64:
+        push $r1 // A_hi
+        push $r2 // B_hi
+        push $r3 // tmp0
+        push $r4 // tmp1
+
+        shr b32 $r1 $r14 16
+        shr b32 $r2 $r13 16
+
+        clear b32 $r12
+        clear b32 $r11
+
+        // A_lo * B_lo
+        mulu $r12 $r14 $r13
+
+        // ( A_hi * B_lo ) << 16
+        mulu $r3 $r1 $r13 // tmp0 = A_hi * B_lo
+        mov b32 $r4 $r3
+        and $r3 0xffff // tmp0 = tmp0_lo
+        shl b32 $r3 16
+        shr b32 $r4 16 // tmp1 = tmp0_hi
+        add b32 $r12 $r3
+        adc b32 $r11 $r4
+
+        // ( A_lo * B_hi ) << 16
+        mulu $r3 $r14 $r2 // tmp0 = A_lo * B_hi
+        mov b32 $r4 $r3
+        and $r3 0xffff // tmp0 = tmp0_lo
+        shl b32 $r3 16
+        shr b32 $r4 16 // tmp1 = tmp0_hi
+        add b32 $r12 $r3
+        adc b32 $r11 $r4
+
+        // ( A_hi * B_hi ) << 32
+        mulu $r3 $r1 $r2 // tmp0 = A_hi * B_hi
+        add b32 $r11 $r3
+
+        pop $r4
+        pop $r3
+        pop $r2
+        pop $r1
+        ret
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
index 8f29badd785f..5cf5be63cbef 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
@@ -98,12 +98,16 @@ wr32:
 // $r14 - ns
 // $r0  - zero
 nsec:
+        push $r9
+        push $r8
         nv_iord($r8, NV_PPWR_TIMER_LOW)
         nsec_loop:
                 nv_iord($r9, NV_PPWR_TIMER_LOW)
                 sub b32 $r9 $r8
                 cmp b32 $r9 $r14
                 bra l #nsec_loop
+        pop $r8
+        pop $r9
         ret
 
 // busy-wait for a period of time
@@ -115,6 +119,8 @@ nsec:
 // $r11 - timeout (ns)
 // $r0  - zero
 wait:
+        push $r9
+        push $r8
         nv_iord($r8, NV_PPWR_TIMER_LOW)
         wait_loop:
                 nv_rd32($r10, $r14)
@@ -126,6 +132,8 @@ wait:
                 cmp b32 $r9 $r11
                 bra l #wait_loop
         wait_done:
+        pop $r8
+        pop $r9
         ret
 
 // $r15 - current (kern)
@@ -242,12 +250,89 @@ intr:
         bclr $flags $p0
         iret
 
-// request the current process be sent a message after a timeout expires
+// calculate the number of ticks in the specified nanoseconds delay
+//
+// $r15 - current
+// $r14 - ns
+// $r14 - ticks (return)
+// $r0  - zero
+ticks_from_ns:
+        push $r12
+        push $r11
+
+        /* try not losing precision (multiply then divide) */
+        imm32($r13, HW_TICKS_PER_US)
+        call #mulu32_32_64
+
+        /* use an immeditate, it's ok because HW_TICKS_PER_US < 16 bits */
+        div $r12 $r12 1000
+
+        /* check if there wasn't any overflow */
+        cmpu b32 $r11 0
+        bra e #ticks_from_ns_quit
+
+        /* let's divide then multiply, too bad for the precision! */
+        div $r14 $r14 1000
+        imm32($r13, HW_TICKS_PER_US)
+        call #mulu32_32_64
+
+        /* this cannot overflow as long as HW_TICKS_PER_US < 1000 */
+
+ticks_from_ns_quit:
+        mov b32 $r14 $r12
+        pop $r11
+        pop $r12
+        ret
+
+// calculate the number of ticks in the specified microsecond delay
+//
+// $r15 - current
+// $r14 - us
+// $r14 - ticks (return)
+// $r0  - zero
+ticks_from_us:
+        push $r12
+        push $r11
+
+        /* simply multiply $us by HW_TICKS_PER_US */
+        imm32($r13, HW_TICKS_PER_US)
+        call #mulu32_32_64
+        mov b32 $r14 $r12
+
+        /* check if there wasn't any overflow */
+        cmpu b32 $r11 0
+        bra e #ticks_from_us_quit
+
+        /* Overflow! */
+        clear b32 $r14
+
+ticks_from_us_quit:
+        pop $r11
+        pop $r12
+        ret
+
+// calculate the number of ticks in the specified microsecond delay
 //
 // $r15 - current
 // $r14 - ticks
+// $r14 - us (return)
+// $r0  - zero
+ticks_to_us:
+        /* simply divide $ticks by HW_TICKS_PER_US */
+        imm32($r13, HW_TICKS_PER_US)
+        div $r14 $r14 $r13
+
+        ret
+
+// request the current process be sent a message after a timeout expires
+//
+// $r15 - current
+// $r14 - ticks (make sure it is < 2^31 to avoid any possible overflow)
 // $r0  - zero
 timer:
+        push $r9
+        push $r8
+
         // interrupts off to prevent racing with timer isr
         bclr $flags ie0
 
@@ -255,13 +340,22 @@ timer:
         ld b32 $r8 D[$r15 + #proc_time]
         cmp b32 $r8 0
         bra g #timer_done
-        st b32 D[$r15 + #proc_time] $r14
 
-        // halt watchdog timer temporarily and check for a pending
-        // interrupt.  if there's one already pending, we can just
-        // bail since the timer isr will queue the next soonest
-        // right after it's done
+        // halt watchdog timer temporarily
+        clear b32 $r8
         nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8)
+
+        // find out how much time elapsed since the last update
+        // of the watchdog and add this time to the wanted ticks
+        nv_iord($r8, NV_PPWR_WATCHDOG_TIME)
+        ld b32 $r9 D[$r0 + #time_prev]
+        sub b32 $r9 $r8
+        add b32 $r14 $r9
+        st b32 D[$r15 + #proc_time] $r14
+
+        // check for a pending interrupt.  if there's one already
+        // pending, we can just bail since the timer isr will
+        // queue the next soonest right after it's done
         nv_iord($r8, NV_PPWR_INTR)
         and $r8 NV_PPWR_INTR_WATCHDOG
         bra nz #timer_enable
@@ -272,10 +366,10 @@ timer:
         cmp b32 $r14 $r0
         bra e #timer_reset
         cmp b32 $r14 $r8
-        bra l #timer_done
-        timer_reset:
-        nv_iowr(NV_PPWR_WATCHDOG_TIME, $r14)
-        st b32 D[$r0 + #time_prev] $r14
+        bra g #timer_enable
+                timer_reset:
+                nv_iowr(NV_PPWR_WATCHDOG_TIME, $r14)
+                st b32 D[$r0 + #time_prev] $r14
 
         // re-enable the watchdog timer
         timer_enable:
@@ -285,6 +379,9 @@ timer:
         // interrupts back on
         timer_done:
         bset $flags ie0
+
+        pop $r8
+        pop $r9
         ret
 
 // send message to another process
@@ -371,6 +468,9 @@ send:
 // $r14 - process
 // $r0  - zero
 recv:
+        push $r9
+        push $r8
+
         ld b32 $r8 D[$r14 + #proc_qget]
         ld b32 $r9 D[$r14 + #proc_qput]
         bclr $flags $p1
@@ -403,6 +503,8 @@ recv:
                 bset $flags $p1
                 pop $r15
         recv_done:
+        pop $r8
+        pop $r9
         ret
 
 init:
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
index 5668e045bac1..96fc984dafdc 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
@@ -250,3 +250,23 @@
 */      st b32 D[$r0] reg /*
 */      clear b32 $r0
 #endif
+
+#define st(size, addr, reg) /*
+*/      movw $r0 addr /*
+*/      st size D[$r0] reg /*
+*/      clear b32 $r0
+
+#define ld(size, reg, addr) /*
+*/      movw $r0 addr /*
+*/      ld size reg D[$r0] /*
+*/      clear b32 $r0
+
+// does a 64+64 -> 64 unsigned addition (C = A + B)
+#define addu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*
+*/    add b32 reg_a_c_lo b_lo /*
+*/    adc b32 reg_a_c_hi b_hi
+
+// does a 64+64 -> 64 substraction (C = A - B)
+#define subu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*
+*/    sub b32 reg_a_c_lo b_lo /*
+*/    sbb b32 reg_a_c_hi b_hi
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
index d43741eccb11..e89789a53b80 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
@@ -43,17 +43,23 @@ process(PROC_MEMX, #memx_init, #memx_recv)
 */      .b32 func
 
 memx_func_head:
-handler(ENTER , 0x0001, 0x0000, #memx_func_enter)
+handler(ENTER , 0x0000, 0x0000, #memx_func_enter)
 memx_func_next:
 handler(LEAVE , 0x0000, 0x0000, #memx_func_leave)
 handler(WR32  , 0x0000, 0x0002, #memx_func_wr32)
 handler(WAIT  , 0x0004, 0x0000, #memx_func_wait)
 handler(DELAY , 0x0001, 0x0000, #memx_func_delay)
+handler(VBLANK, 0x0001, 0x0000, #memx_func_wait_vblank)
 memx_func_tail:
 
 .equ #memx_func_size #memx_func_next - #memx_func_head
 .equ #memx_func_num (#memx_func_tail - #memx_func_head) / #memx_func_size
 
+memx_ts_start:
+.b32 0
+memx_ts_end:
+.b32 0
+
 memx_data_head:
 .skip 0x0800
 memx_data_tail:
@@ -67,19 +73,44 @@ memx_data_tail:
 //
 // $r15 - current (memx)
 // $r4  - packet length
-//      +00: bitmask of heads to wait for vblank on
 // $r3  - opcode desciption
 // $r0  - zero
 memx_func_enter:
+#if NVKM_PPWR_CHIPSET == GT215
+        movw $r8 0x1610
+        nv_rd32($r7, $r8)
+        imm32($r6, 0xfffffffc)
+        and $r7 $r6
+        movw $r6 0x2
+        or $r7 $r6
+        nv_wr32($r8, $r7)
+#else
+        movw $r6 0x001620
+        imm32($r7, ~0x00000aa2);
+        nv_rd32($r8, $r6)
+        and $r8 $r7
+        nv_wr32($r6, $r8)
+
+        imm32($r7, ~0x00000001)
+        nv_rd32($r8, $r6)
+        and $r8 $r7
+        nv_wr32($r6, $r8)
+
+        movw $r6 0x0026f0
+        nv_rd32($r8, $r6)
+        and $r8 $r7
+        nv_wr32($r6, $r8)
+#endif
+
         mov $r6 NV_PPWR_OUTPUT_SET_FB_PAUSE
         nv_iowr(NV_PPWR_OUTPUT_SET, $r6)
         memx_func_enter_wait:
                 nv_iord($r6, NV_PPWR_OUTPUT)
                 and $r6 NV_PPWR_OUTPUT_FB_PAUSE
                 bra z #memx_func_enter_wait
-        //XXX: TODO
-        ld b32 $r6 D[$r1 + 0x00]
-        add b32 $r1 0x04
+
+        nv_iord($r6, NV_PPWR_TIMER_LOW)
+        st b32 D[$r0 + #memx_ts_start] $r6
         ret
 
 // description
@@ -89,14 +120,93 @@ memx_func_enter:
 // $r3  - opcode desciption
 // $r0  - zero
 memx_func_leave:
+        nv_iord($r6, NV_PPWR_TIMER_LOW)
+        st b32 D[$r0 + #memx_ts_end] $r6
+
         mov $r6 NV_PPWR_OUTPUT_CLR_FB_PAUSE
         nv_iowr(NV_PPWR_OUTPUT_CLR, $r6)
         memx_func_leave_wait:
                 nv_iord($r6, NV_PPWR_OUTPUT)
                 and $r6 NV_PPWR_OUTPUT_FB_PAUSE
                 bra nz #memx_func_leave_wait
+
+#if NVKM_PPWR_CHIPSET == GT215
+        movw $r8 0x1610
+        nv_rd32($r7, $r8)
+        imm32($r6, 0xffffffcc)
+        and $r7 $r6
+        nv_wr32($r8, $r7)
+#else
+        movw $r6 0x0026f0
+        imm32($r7, 0x00000001)
+        nv_rd32($r8, $r6)
+        or $r8 $r7
+        nv_wr32($r6, $r8)
+
+        movw $r6 0x001620
+        nv_rd32($r8, $r6)
+        or $r8 $r7
+        nv_wr32($r6, $r8)
+
+        imm32($r7, 0x00000aa2);
+        nv_rd32($r8, $r6)
+        or $r8 $r7
+        nv_wr32($r6, $r8)
+#endif
+        ret
+
+#if NVKM_PPWR_CHIPSET < GF119
+// description
+//
+// $r15 - current (memx)
+// $r4  - packet length
+//      +00: head to wait for vblank on
+// $r3  - opcode desciption
+// $r0  - zero
+memx_func_wait_vblank:
+        ld b32 $r6 D[$r1 + 0x00]
+        cmp b32 $r6 0x0
+        bra z #memx_func_wait_vblank_head0
+        cmp b32 $r6 0x1
+        bra z #memx_func_wait_vblank_head1
+        bra #memx_func_wait_vblank_fini
+
+        memx_func_wait_vblank_head1:
+        movw $r7 0x20
+        bra #memx_func_wait_vblank_0
+
+        memx_func_wait_vblank_head0:
+        movw $r7 0x8
+
+        memx_func_wait_vblank_0:
+                nv_iord($r6, NV_PPWR_INPUT)
+                and $r6 $r7
+                bra nz #memx_func_wait_vblank_0
+
+        memx_func_wait_vblank_1:
+                nv_iord($r6, NV_PPWR_INPUT)
+                and $r6 $r7
+                bra z #memx_func_wait_vblank_1
+
+        memx_func_wait_vblank_fini:
+        add b32 $r1 0x4
+        ret
+
+#else
+
+// XXX: currently no-op
+//
+// $r15 - current (memx)
+// $r4  - packet length
+//      +00: head to wait for vblank on
+// $r3  - opcode desciption
+// $r0  - zero
+memx_func_wait_vblank:
+        add b32 $r1 0x4
         ret
 
+#endif
+
 // description
 //
 // $r15 - current (memx)
@@ -160,14 +270,17 @@ memx_exec:
         push $r13
         mov b32 $r1 $r12
         mov b32 $r2 $r11
+
         memx_exec_next:
-                // fetch the packet header, and locate opcode info
+                // fetch the packet header
                 ld b32 $r3 D[$r1]
                 add b32 $r1 4
-                shr b32 $r4 $r3 16
-                mulu $r3 #memx_func_size
+                extr $r4 $r3 16:31
+                extr $r3 $r3 0:15
 
                 // execute the opcode handler
+                sub b32 $r3 1
+                mulu $r3 #memx_func_size
                 ld b32 $r5 D[$r3 + #memx_func_head + #memx_func]
                 call $r5
 
@@ -176,6 +289,10 @@ memx_exec:
                 bra l #memx_exec_next
 
         // send completion reply
+        ld b32 $r11 D[$r0 + #memx_ts_start]
+        ld b32 $r12 D[$r0 + #memx_ts_end]
+        sub b32 $r12 $r11
+        nv_iord($r11, NV_PPWR_INPUT)
         pop $r13
         pop $r14
         call(send)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
index 17a8a383d91a..b439519ec866 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
@@ -23,6 +23,7 @@
  */
 
 #define NVKM_PPWR_CHIPSET GK208
+#define HW_TICKS_PER_US 324
 
 #define NVKM_FALCON_PC24
 #define NVKM_FALCON_UNSHIFTED_IO
@@ -34,6 +35,7 @@
 .section #nv108_pwr_data
 #define INCLUDE_PROC
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
@@ -44,6 +46,7 @@
 
 #define INCLUDE_DATA
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
@@ -56,6 +59,7 @@
 .section #nv108_pwr_code
 #define INCLUDE_CODE
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
index 986495d533dd..4d278a96b2bb 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
@@ -24,8 +24,8 @@ uint32_t nv108_pwr_data[] = {
         0x00000000,
 /* 0x0058: proc_list_head */
         0x54534f48,
-        0x00000379,
-        0x0000032a,
+        0x00000453,
+        0x00000404,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -46,8 +46,8 @@ uint32_t nv108_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x584d454d,
-        0x00000464,
-        0x00000456,
+        0x0000061c,
+        0x0000060e,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -68,8 +68,8 @@ uint32_t nv108_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x46524550,
-        0x00000468,
-        0x00000466,
+        0x00000620,
+        0x0000061e,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -90,8 +90,8 @@ uint32_t nv108_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x5f433249,
-        0x0000086c,
-        0x00000713,
+        0x00000a24,
+        0x000008cb,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -112,8 +112,8 @@ uint32_t nv108_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x54534554,
-        0x0000088d,
-        0x0000086e,
+        0x00000a45,
+        0x00000a26,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -134,8 +134,8 @@ uint32_t nv108_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x454c4449,
-        0x00000898,
-        0x00000896,
+        0x00000a50,
+        0x00000a4e,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -227,25 +227,31 @@ uint32_t nv108_pwr_data[] = {
         0x00000000,
         0x00000000,
 /* 0x0370: memx_func_head */
-        0x00010000,
-        0x00000000,
-        0x000003a9,
-/* 0x037c: memx_func_next */
         0x00000001,
         0x00000000,
-        0x000003c7,
+        0x00000483,
+/* 0x037c: memx_func_next */
         0x00000002,
+        0x00000000,
+        0x00000500,
+        0x00000003,
         0x00000002,
-        0x000003df,
-        0x00040003,
+        0x00000580,
+        0x00040004,
+        0x00000000,
+        0x0000059d,
+        0x00010005,
+        0x00000000,
+        0x000005b7,
+        0x00010006,
         0x00000000,
-        0x000003fc,
-        0x00010004,
+        0x0000057b,
+/* 0x03b8: memx_func_tail */
+/* 0x03b8: memx_ts_start */
         0x00000000,
-        0x00000416,
-/* 0x03ac: memx_func_tail */
-/* 0x03ac: memx_data_head */
+/* 0x03bc: memx_ts_end */
         0x00000000,
+/* 0x03c0: memx_data_head */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -757,8 +763,9 @@ uint32_t nv108_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0bac: memx_data_tail */
-/* 0x0bac: i2c_scl_map */
+        0x00000000,
+/* 0x0bc0: memx_data_tail */
+/* 0x0bc0: i2c_scl_map */
         0x00000400,
         0x00000800,
         0x00001000,
@@ -769,7 +776,7 @@ uint32_t nv108_pwr_data[] = {
         0x00020000,
         0x00040000,
         0x00080000,
-/* 0x0bd4: i2c_sda_map */
+/* 0x0be8: i2c_sda_map */
         0x00100000,
         0x00200000,
         0x00400000,
@@ -781,10 +788,69 @@ uint32_t nv108_pwr_data[] = {
         0x10000000,
         0x20000000,
         0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
 };
 
 uint32_t nv108_pwr_code[] = {
-        0x02910ef5,
+        0x031c0ef5,
 /* 0x0004: rd32 */
         0xf607a040,
         0x04bd000e,
@@ -812,15 +878,18 @@ uint32_t nv108_pwr_code[] = {
         0x7000d4f1,
         0xf8f61bf4,
 /* 0x005d: nsec */
-        0xcf2c0800,
-/* 0x0062: nsec_loop */
+        0xf990f900,
+        0xcf2c0880,
+/* 0x0066: nsec_loop */
         0x2c090088,
         0xbb0099cf,
         0x9ea60298,
-        0xf8f61ef4,
-/* 0x0071: wait */
-        0xcf2c0800,
-/* 0x0076: wait_loop */
+        0xfcf61ef4,
+        0xf890fc80,
+/* 0x0079: wait */
+        0xf990f900,
+        0xcf2c0880,
+/* 0x0082: wait_loop */
         0xeeb20088,
         0x0000047e,
         0xadfddab2,
@@ -828,28 +897,29 @@ uint32_t nv108_pwr_code[] = {
         0x2c09100b,
         0xbb0099cf,
         0x9ba60298,
-/* 0x0093: wait_done */
-        0xf8e61ef4,
-/* 0x0095: intr_watchdog */
+/* 0x009f: wait_done */
+        0xfce61ef4,
+        0xf890fc80,
+/* 0x00a5: intr_watchdog */
         0x03e99800,
         0xf40096b0,
         0x0a98280b,
         0x029abb9a,
         0x0d0e1cf4,
-        0x01de7e01,
+        0x02617e01,
         0xf494bd00,
-/* 0x00b2: intr_watchdog_next_time */
+/* 0x00c2: intr_watchdog_next_time */
         0x0a98140e,
         0x00a6b09b,
         0xa6080bf4,
         0x061cf49a,
-/* 0x00c0: intr_watchdog_next_time_set */
-/* 0x00c3: intr_watchdog_next_proc */
+/* 0x00d0: intr_watchdog_next_time_set */
+/* 0x00d3: intr_watchdog_next_proc */
         0xb59b09b5,
         0xe0b603e9,
         0x68e6b158,
         0xc81bf402,
-/* 0x00d2: intr */
+/* 0x00e2: intr */
         0x00f900f8,
         0x80f904bd,
         0xa0f990f9,
@@ -865,13 +935,13 @@ uint32_t nv108_pwr_code[] = {
         0xc40088cf,
         0x0bf40289,
         0x9b00b51f,
-        0x957e580e,
+        0xa57e580e,
         0x09980000,
         0x0096b09b,
         0x000d0bf4,
         0x0009f634,
         0x09b504bd,
-/* 0x0125: intr_skip_watchdog */
+/* 0x0135: intr_skip_watchdog */
         0x0089e49a,
         0x360bf408,
         0xcf068849,
@@ -881,20 +951,20 @@ uint32_t nv108_pwr_code[] = {
         0xc0f900cc,
         0xf14f484e,
         0x0d5453e3,
-        0x023f7e00,
+        0x02c27e00,
         0x40c0fc00,
         0x0cf604c0,
-/* 0x0157: intr_subintr_skip_fifo */
+/* 0x0167: intr_subintr_skip_fifo */
         0x4004bd00,
         0x09f60688,
-/* 0x015f: intr_skip_subintr */
+/* 0x016f: intr_skip_subintr */
         0xc404bd00,
         0x0bf42089,
         0xbfa4f107,
-/* 0x0169: intr_skip_pause */
+/* 0x0179: intr_skip_pause */
         0x4089c4ff,
         0xf1070bf4,
-/* 0x0173: intr_skip_user0 */
+/* 0x0183: intr_skip_user0 */
         0x00ffbfa4,
         0x0008f604,
         0x80fc04bd,
@@ -904,304 +974,417 @@ uint32_t nv108_pwr_code[] = {
         0xfca0fcb0,
         0xfc80fc90,
         0x0032f400,
-/* 0x0196: timer */
-        0x32f401f8,
-        0x03f89810,
-        0xf40086b0,
-        0xfeb53a1c,
-        0xf6380003,
+/* 0x01a6: ticks_from_ns */
+        0xc0f901f8,
+        0xd7f1b0f9,
+        0xd3f00144,
+        0x7721f500,
+        0xe8ccec03,
+        0x00b4b003,
+        0xec120bf4,
+        0xf103e8ee,
+        0xf00144d7,
+        0x21f500d3,
+/* 0x01ce: ticks_from_ns_quit */
+        0xceb20377,
+        0xc0fcb0fc,
+/* 0x01d6: ticks_from_us */
+        0xc0f900f8,
+        0xd7f1b0f9,
+        0xd3f00144,
+        0x7721f500,
+        0xb0ceb203,
+        0x0bf400b4,
+/* 0x01ef: ticks_from_us_quit */
+        0xfce4bd05,
+        0xf8c0fcb0,
+/* 0x01f5: ticks_to_us */
+        0x44d7f100,
+        0x00d3f001,
+        0xf8ecedff,
+/* 0x0201: timer */
+        0xf990f900,
+        0x1032f480,
+        0xb003f898,
+        0x1cf40086,
+        0x0084bd4a,
+        0x0008f638,
+        0x340804bd,
+        0x980088cf,
+        0x98bb9a09,
+        0x00e9bb02,
+        0x0803feb5,
+        0x0088cf08,
+        0xf40284f0,
+        0x34081c1b,
+        0xa60088cf,
+        0x080bf4e0,
+        0x1cf4e8a6,
+/* 0x0245: timer_reset */
+        0xf634000d,
+        0x04bd000e,
+/* 0x024f: timer_enable */
+        0x089a0eb5,
+        0xf6380001,
         0x04bd0008,
-        0x88cf0808,
-        0x0284f000,
-        0x081c1bf4,
-        0x0088cf34,
-        0x0bf4e0a6,
-        0xf4e8a608,
-/* 0x01c6: timer_reset */
-        0x3400161e,
-        0xbd000ef6,
-        0x9a0eb504,
-/* 0x01d0: timer_enable */
-        0x38000108,
-        0xbd0008f6,
-/* 0x01d9: timer_done */
-        0x1031f404,
-/* 0x01de: send_proc */
-        0x80f900f8,
-        0xe89890f9,
-        0x04e99805,
-        0xa60486f0,
-        0x2a0bf489,
-        0x940398c4,
-        0x80b60488,
-        0x008ebb18,
-        0xb500fa98,
-        0x8db5008a,
-        0x028cb501,
-        0xb6038bb5,
-        0x94f00190,
-        0x04e9b507,
-/* 0x0217: send_done */
-        0xfc0231f4,
-        0xf880fc90,
-/* 0x021d: find */
-        0x0880f900,
-        0x0131f458,
-/* 0x0224: find_loop */
-        0xa6008a98,
-        0x100bf4ae,
-        0xb15880b6,
-        0xf4026886,
-        0x32f4f11b,
-/* 0x0239: find_done */
-        0xfc8eb201,
-/* 0x023f: send */
-        0x7e00f880,
-        0xf400021d,
-        0x00f89b01,
-/* 0x0248: recv */
-        0x9805e898,
-        0x32f404e9,
-        0xf489a601,
-        0x89c43c0b,
-        0x0180b603,
-        0xb50784f0,
-        0xea9805e8,
-        0xfef0f902,
-        0xf0f9018f,
-        0x9994efb2,
-        0x00e9bb04,
-        0x9818e0b6,
-        0xec9803eb,
-        0x01ed9802,
-        0xf900ee98,
-        0xfef0fca5,
-        0x31f400f8,
-/* 0x028f: recv_done */
-        0xf8f0fc01,
-/* 0x0291: init */
-        0x01084100,
-        0xe70011cf,
-        0xb6010911,
-        0x14fe0814,
-        0x00e04100,
-        0x000013f0,
-        0x0001f61c,
-        0xff0104bd,
-        0x01f61400,
-        0x0104bd00,
-        0x0015f102,
-        0xf6100008,
-        0x04bd0001,
-        0xf000d241,
-        0x10fe0013,
-        0x1031f400,
-        0x38000101,
+/* 0x0258: timer_done */
+        0xfc1031f4,
+        0xf890fc80,
+/* 0x0261: send_proc */
+        0xf980f900,
+        0x05e89890,
+        0xf004e998,
+        0x89a60486,
+        0xc42a0bf4,
+        0x88940398,
+        0x1880b604,
+        0x98008ebb,
+        0x8ab500fa,
+        0x018db500,
+        0xb5028cb5,
+        0x90b6038b,
+        0x0794f001,
+        0xf404e9b5,
+/* 0x029a: send_done */
+        0x90fc0231,
+        0x00f880fc,
+/* 0x02a0: find */
+        0x580880f9,
+/* 0x02a7: find_loop */
+        0x980131f4,
+        0xaea6008a,
+        0xb6100bf4,
+        0x86b15880,
+        0x1bf40268,
+        0x0132f4f1,
+/* 0x02bc: find_done */
+        0x80fc8eb2,
+/* 0x02c2: send */
+        0xa07e00f8,
+        0x01f40002,
+/* 0x02cb: recv */
+        0xf900f89b,
+        0x9880f990,
+        0xe99805e8,
+        0x0132f404,
+        0x0bf489a6,
+        0x0389c43c,
+        0xf00180b6,
+        0xe8b50784,
+        0x02ea9805,
+        0x8ffef0f9,
+        0xb2f0f901,
+        0x049994ef,
+        0xb600e9bb,
+        0xeb9818e0,
+        0x02ec9803,
+        0x9801ed98,
+        0xa5f900ee,
+        0xf8fef0fc,
+        0x0131f400,
+/* 0x0316: recv_done */
+        0x80fcf0fc,
+        0x00f890fc,
+/* 0x031c: init */
+        0xcf010841,
+        0x11e70011,
+        0x14b60109,
+        0x0014fe08,
+        0xf000e041,
+        0x1c000013,
         0xbd0001f6,
-/* 0x02db: init_proc */
-        0x98580f04,
-        0x16b001f1,
-        0xfa0bf400,
-        0xf0b615f9,
-        0xf20ef458,
-/* 0x02ec: host_send */
-        0xcf04b041,
-        0xa0420011,
-        0x0022cf04,
-        0x0bf412a6,
-        0x071ec42e,
-        0xb704ee94,
-        0x980270e0,
-        0xec9803eb,
-        0x01ed9802,
-        0x7e00ee98,
-        0xb600023f,
-        0x1ec40110,
-        0x04b0400f,
-        0xbd000ef6,
-        0xc70ef404,
-/* 0x0328: host_send_done */
-/* 0x032a: host_recv */
-        0x494100f8,
-        0x5413f14e,
-        0xf4e1a652,
-/* 0x0336: host_recv_wait */
-        0xcc41b90b,
-        0x0011cf04,
-        0xcf04c842,
-        0x16f00022,
-        0xf412a608,
-        0x23c4ef0b,
-        0x0434b607,
-        0x02f030b7,
-        0xb5033bb5,
-        0x3db5023c,
-        0x003eb501,
-        0xf00120b6,
-        0xc8400f24,
-        0x0002f604,
-        0x400204bd,
-        0x02f60000,
-        0xf804bd00,
-/* 0x0379: host_init */
-        0x00804100,
-        0xf11014b6,
-        0x40027015,
-        0x01f604d0,
+        0x00ff0104,
+        0x0001f614,
+        0x020104bd,
+        0x080015f1,
+        0x01f61000,
         0x4104bd00,
+        0x13f000e2,
+        0x0010fe00,
+        0x011031f4,
+        0xf6380001,
+        0x04bd0001,
+/* 0x0366: init_proc */
+        0xf198580f,
+        0x0016b001,
+        0xf9fa0bf4,
+        0x58f0b615,
+/* 0x0377: mulu32_32_64 */
+        0xf9f20ef4,
+        0xf920f910,
+        0x9540f930,
+        0xd29510e1,
+        0xbdc4bd10,
+        0xc0edffb4,
+        0xb2301dff,
+        0xff34f134,
+        0x1034b6ff,
+        0xbb1045b6,
+        0xb4bb00c3,
+        0x30e2ff01,
+        0x34f134b2,
+        0x34b6ffff,
+        0x1045b610,
+        0xbb00c3bb,
+        0x12ff01b4,
+        0x00b3bb30,
+        0x30fc40fc,
+        0x10fc20fc,
+/* 0x03c6: host_send */
+        0xb04100f8,
+        0x0011cf04,
+        0xcf04a042,
+        0x12a60022,
+        0xc42e0bf4,
+        0xee94071e,
+        0x70e0b704,
+        0x03eb9802,
+        0x9802ec98,
+        0xee9801ed,
+        0x02c27e00,
+        0x0110b600,
+        0x400f1ec4,
+        0x0ef604b0,
+        0xf404bd00,
+/* 0x0402: host_send_done */
+        0x00f8c70e,
+/* 0x0404: host_recv */
+        0xf14e4941,
+        0xa6525413,
+        0xb90bf4e1,
+/* 0x0410: host_recv_wait */
+        0xcf04cc41,
+        0xc8420011,
+        0x0022cf04,
+        0xa60816f0,
+        0xef0bf412,
+        0xb60723c4,
+        0x30b70434,
+        0x3bb502f0,
+        0x023cb503,
+        0xb5013db5,
+        0x20b6003e,
+        0x0f24f001,
+        0xf604c840,
+        0x04bd0002,
+        0x00004002,
+        0xbd0002f6,
+/* 0x0453: host_init */
+        0x4100f804,
         0x14b60080,
-        0xf015f110,
-        0x04dc4002,
+        0x7015f110,
+        0x04d04002,
+        0xbd0001f6,
+        0x00804104,
+        0xf11014b6,
+        0x4002f015,
+        0x01f604dc,
+        0x0104bd00,
+        0x04c44001,
         0xbd0001f6,
-        0x40010104,
-        0x01f604c4,
-        0xf804bd00,
-/* 0x03a9: memx_func_enter */
-        0x40040600,
-        0x06f607e0,
-/* 0x03b3: memx_func_enter_wait */
-        0x4604bd00,
-        0x66cf07c0,
-        0x0464f000,
-        0x98f70bf4,
-        0x10b60016,
-/* 0x03c7: memx_func_leave */
-        0x0600f804,
-        0x07e44004,
-        0xbd0006f6,
-/* 0x03d1: memx_func_leave_wait */
-        0x07c04604,
-        0xf00066cf,
-        0x1bf40464,
-/* 0x03df: memx_func_wr32 */
-        0x9800f8f7,
-        0x15980016,
-        0x0810b601,
-        0x50f960f9,
+/* 0x0483: memx_func_enter */
+        0xf100f804,
+        0xf1162067,
+        0xf1f55d77,
+        0xb2ffff73,
+        0x00047e6e,
+        0xfdd8b200,
+        0x60f90487,
+        0xd0fc80f9,
+        0x2e7ee0fc,
+        0x77f10000,
+        0x73f1fffe,
+        0x6eb2ffff,
+        0x0000047e,
+        0x87fdd8b2,
+        0xf960f904,
+        0xfcd0fc80,
+        0x002e7ee0,
+        0xf067f100,
+        0x7e6eb226,
+        0xb2000004,
+        0x0487fdd8,
+        0x80f960f9,
         0xe0fcd0fc,
         0x00002e7e,
-        0xf40242b6,
-        0x00f8e81b,
-/* 0x03fc: memx_func_wait */
-        0x88cf2c08,
-        0x001e9800,
-        0x98011d98,
-        0x1b98021c,
-        0x1010b603,
-        0x0000717e,
-/* 0x0416: memx_func_delay */
-        0x1e9800f8,
-        0x0410b600,
-        0x00005d7e,
-/* 0x0422: memx_exec */
-        0xe0f900f8,
-        0xc1b2d0f9,
-/* 0x042a: memx_exec_next */
-        0x1398b2b2,
-        0x0410b600,
-        0xf0103495,
-        0x35980c30,
-        0xa655f9de,
-        0xed1ef412,
+        0xe0400406,
+        0x0006f607,
+/* 0x04ea: memx_func_enter_wait */
+        0xc04604bd,
+        0x0066cf07,
+        0xf40464f0,
+        0x2c06f70b,
+        0xb50066cf,
+        0x00f8ee06,
+/* 0x0500: memx_func_leave */
+        0x66cf2c06,
+        0xef06b500,
+        0xe4400406,
+        0x0006f607,
+/* 0x0512: memx_func_leave_wait */
+        0xc04604bd,
+        0x0066cf07,
+        0xf40464f0,
+        0x67f1f71b,
+        0x77f126f0,
+        0x73f00001,
+        0x7e6eb200,
+        0xb2000004,
+        0x0587fdd8,
+        0x80f960f9,
         0xe0fcd0fc,
-        0x00023f7e,
-/* 0x044a: memx_info */
-        0xac4c00f8,
+        0x00002e7e,
+        0x162067f1,
+        0x047e6eb2,
+        0xd8b20000,
+        0xf90587fd,
+        0xfc80f960,
+        0x7ee0fcd0,
+        0xf100002e,
+        0xf00aa277,
+        0x6eb20073,
+        0x0000047e,
+        0x87fdd8b2,
+        0xf960f905,
+        0xfcd0fc80,
+        0x002e7ee0,
+/* 0x057b: memx_func_wait_vblank */
+        0xb600f800,
+        0x00f80410,
+/* 0x0580: memx_func_wr32 */
+        0x98001698,
+        0x10b60115,
+        0xf960f908,
+        0xfcd0fc50,
+        0x002e7ee0,
+        0x0242b600,
+        0xf8e81bf4,
+/* 0x059d: memx_func_wait */
+        0xcf2c0800,
+        0x1e980088,
+        0x011d9800,
+        0x98021c98,
+        0x10b6031b,
+        0x00797e10,
+/* 0x05b7: memx_func_delay */
+        0x9800f800,
+        0x10b6001e,
+        0x005d7e04,
+/* 0x05c3: memx_exec */
+        0xf900f800,
+        0xb2d0f9e0,
+/* 0x05cb: memx_exec_next */
+        0x98b2b2c1,
+        0x10b60013,
+        0xf034e704,
+        0xe033e701,
+        0x0132b601,
+        0x980c30f0,
+        0x55f9de35,
+        0x1ef412a6,
+        0xee0b98e5,
+        0xbbef0c98,
+        0xc44b02cb,
+        0x00bbcf07,
+        0xe0fcd0fc,
+        0x0002c27e,
+/* 0x0602: memx_info */
+        0xc04c00f8,
         0x08004b03,
-        0x00023f7e,
-/* 0x0456: memx_recv */
+        0x0002c27e,
+/* 0x060e: memx_recv */
         0xd6b000f8,
-        0xc90bf401,
+        0xb20bf401,
         0xf400d6b0,
         0x00f8eb0b,
-/* 0x0464: memx_init */
-/* 0x0466: perf_recv */
+/* 0x061c: memx_init */
+/* 0x061e: perf_recv */
         0x00f800f8,
-/* 0x0468: perf_init */
-/* 0x046a: i2c_drive_scl */
+/* 0x0620: perf_init */
+/* 0x0622: i2c_drive_scl */
         0x36b000f8,
         0x0d0bf400,
         0xf607e040,
         0x04bd0001,
-/* 0x047a: i2c_drive_scl_lo */
+/* 0x0632: i2c_drive_scl_lo */
         0xe44000f8,
         0x0001f607,
         0x00f804bd,
-/* 0x0484: i2c_drive_sda */
+/* 0x063c: i2c_drive_sda */
         0xf40036b0,
         0xe0400d0b,
         0x0002f607,
         0x00f804bd,
-/* 0x0494: i2c_drive_sda_lo */
+/* 0x064c: i2c_drive_sda_lo */
         0xf607e440,
         0x04bd0002,
-/* 0x049e: i2c_sense_scl */
+/* 0x0656: i2c_sense_scl */
         0x32f400f8,
         0x07c44301,
         0xfd0033cf,
         0x0bf40431,
         0x0131f406,
-/* 0x04b0: i2c_sense_scl_done */
-/* 0x04b2: i2c_sense_sda */
+/* 0x0668: i2c_sense_scl_done */
+/* 0x066a: i2c_sense_sda */
         0x32f400f8,
         0x07c44301,
         0xfd0033cf,
         0x0bf40432,
         0x0131f406,
-/* 0x04c4: i2c_sense_sda_done */
-/* 0x04c6: i2c_raise_scl */
+/* 0x067c: i2c_sense_sda_done */
+/* 0x067e: i2c_raise_scl */
         0x40f900f8,
         0x03089844,
-        0x046a7e01,
-/* 0x04d1: i2c_raise_scl_wait */
+        0x06227e01,
+/* 0x0689: i2c_raise_scl_wait */
         0x03e84e00,
         0x00005d7e,
-        0x00049e7e,
+        0x0006567e,
         0xb60901f4,
         0x1bf40142,
-/* 0x04e5: i2c_raise_scl_done */
+/* 0x069d: i2c_raise_scl_done */
         0xf840fcef,
-/* 0x04e9: i2c_start */
-        0x049e7e00,
+/* 0x06a1: i2c_start */
+        0x06567e00,
         0x0d11f400,
-        0x0004b27e,
+        0x00066a7e,
         0xf40611f4,
-/* 0x04fa: i2c_start_rep */
+/* 0x06b2: i2c_start_rep */
         0x00032e0e,
-        0x00046a7e,
-        0x847e0103,
-        0x76bb0004,
+        0x0006227e,
+        0x3c7e0103,
+        0x76bb0006,
         0x0465b600,
         0x659450f9,
         0x0256bb04,
         0x75fd50bd,
         0x7e50fc04,
-        0xb60004c6,
+        0xb600067e,
         0x11f40464,
-/* 0x0525: i2c_start_send */
+/* 0x06dd: i2c_start_send */
         0x7e00031d,
-        0x4e000484,
+        0x4e00063c,
         0x5d7e1388,
         0x00030000,
-        0x00046a7e,
+        0x0006227e,
         0x7e13884e,
-/* 0x053f: i2c_start_out */
+/* 0x06f7: i2c_start_out */
         0xf800005d,
-/* 0x0541: i2c_stop */
+/* 0x06f9: i2c_stop */
         0x7e000300,
-        0x0300046a,
-        0x04847e00,
+        0x03000622,
+        0x063c7e00,
         0x03e84e00,
         0x00005d7e,
-        0x6a7e0103,
-        0x884e0004,
+        0x227e0103,
+        0x884e0006,
         0x005d7e13,
         0x7e010300,
-        0x4e000484,
+        0x4e00063c,
         0x5d7e1388,
         0x00f80000,
-/* 0x0570: i2c_bitw */
-        0x0004847e,
+/* 0x0728: i2c_bitw */
+        0x00063c7e,
         0x7e03e84e,
         0xbb00005d,
         0x65b60076,
@@ -1209,44 +1392,44 @@ uint32_t nv108_pwr_code[] = {
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x0004c67e,
+        0x00067e7e,
         0xf40464b6,
         0x884e1711,
         0x005d7e13,
         0x7e000300,
-        0x4e00046a,
+        0x4e000622,
         0x5d7e1388,
-/* 0x05ae: i2c_bitw_out */
+/* 0x0766: i2c_bitw_out */
         0x00f80000,
-/* 0x05b0: i2c_bitr */
-        0x847e0103,
-        0xe84e0004,
+/* 0x0768: i2c_bitr */
+        0x3c7e0103,
+        0xe84e0006,
         0x005d7e03,
         0x0076bb00,
         0xf90465b6,
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
-        0xc67e50fc,
-        0x64b60004,
+        0x7e7e50fc,
+        0x64b60006,
         0x1a11f404,
-        0x0004b27e,
-        0x6a7e0003,
-        0x884e0004,
+        0x00066a7e,
+        0x227e0003,
+        0x884e0006,
         0x005d7e13,
         0x013cf000,
-/* 0x05f3: i2c_bitr_done */
+/* 0x07ab: i2c_bitr_done */
         0xf80131f4,
-/* 0x05f5: i2c_get_byte */
+/* 0x07ad: i2c_get_byte */
         0x04000500,
-/* 0x05f9: i2c_get_byte_next */
+/* 0x07b1: i2c_get_byte_next */
         0x0154b608,
         0xb60076bb,
         0x50f90465,
         0xbb046594,
         0x50bd0256,
         0xfc0475fd,
-        0x05b07e50,
+        0x07687e50,
         0x0464b600,
         0xfd2a11f4,
         0x42b60553,
@@ -1257,11 +1440,11 @@ uint32_t nv108_pwr_code[] = {
         0x0256bb04,
         0x75fd50bd,
         0x7e50fc04,
-        0xb6000570,
-/* 0x0642: i2c_get_byte_done */
+        0xb6000728,
+/* 0x07fa: i2c_get_byte_done */
         0x00f80464,
-/* 0x0644: i2c_put_byte */
-/* 0x0646: i2c_put_byte_next */
+/* 0x07fc: i2c_put_byte */
+/* 0x07fe: i2c_put_byte_next */
         0x42b60804,
         0x3854ff01,
         0xb60076bb,
@@ -1269,7 +1452,7 @@ uint32_t nv108_pwr_code[] = {
         0xbb046594,
         0x50bd0256,
         0xfc0475fd,
-        0x05707e50,
+        0x07287e50,
         0x0464b600,
         0xb03411f4,
         0x1bf40046,
@@ -1278,21 +1461,21 @@ uint32_t nv108_pwr_code[] = {
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
-        0xb07e50fc,
-        0x64b60005,
+        0x687e50fc,
+        0x64b60007,
         0x0f11f404,
         0xb00076bb,
         0x1bf40136,
         0x0132f406,
-/* 0x069c: i2c_put_byte_done */
-/* 0x069e: i2c_addr */
+/* 0x0854: i2c_put_byte_done */
+/* 0x0856: i2c_addr */
         0x76bb00f8,
         0x0465b600,
         0x659450f9,
         0x0256bb04,
         0x75fd50bd,
         0x7e50fc04,
-        0xb60004e9,
+        0xb60006a1,
         0x11f40464,
         0x2ec3e729,
         0x0134b601,
@@ -1302,32 +1485,32 @@ uint32_t nv108_pwr_code[] = {
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x0006447e,
-/* 0x06e3: i2c_addr_done */
+        0x0007fc7e,
+/* 0x089b: i2c_addr_done */
         0xf80464b6,
-/* 0x06e5: i2c_acquire_addr */
+/* 0x089d: i2c_acquire_addr */
         0xf8cec700,
         0xb705e4b6,
         0xf8d014e0,
-/* 0x06f1: i2c_acquire */
-        0x06e57e00,
+/* 0x08a9: i2c_acquire */
+        0x089d7e00,
         0x00047e00,
         0x03d9f000,
         0x00002e7e,
-/* 0x0702: i2c_release */
-        0xe57e00f8,
-        0x047e0006,
+/* 0x08ba: i2c_release */
+        0x9d7e00f8,
+        0x047e0008,
         0xdaf00000,
         0x002e7e03,
-/* 0x0713: i2c_recv */
+/* 0x08cb: i2c_recv */
         0xf400f800,
         0xc1c70132,
         0x0214b6f8,
         0xf52816b0,
         0xb801371f,
-        0x000bd413,
+        0x000be813,
         0xb8003298,
-        0x000bac13,
+        0x000bc013,
         0xf4003198,
         0xd0f90231,
         0xd0f9e0f9,
@@ -1339,7 +1522,7 @@ uint32_t nv108_pwr_code[] = {
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x0006f17e,
+        0x0008a97e,
         0xfc0464b6,
         0x00d6b0d0,
         0x00b01bf5,
@@ -1349,7 +1532,7 @@ uint32_t nv108_pwr_code[] = {
         0x0256bb04,
         0x75fd50bd,
         0x7e50fc04,
-        0xb600069e,
+        0xb6000856,
         0x11f50464,
         0xc5c700cc,
         0x0076bbe0,
@@ -1357,8 +1540,8 @@ uint32_t nv108_pwr_code[] = {
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
-        0x447e50fc,
-        0x64b60006,
+        0xfc7e50fc,
+        0x64b60007,
         0xa911f504,
         0xbb010500,
         0x65b60076,
@@ -1366,7 +1549,7 @@ uint32_t nv108_pwr_code[] = {
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x00069e7e,
+        0x0008567e,
         0xf50464b6,
         0xbb008711,
         0x65b60076,
@@ -1374,7 +1557,7 @@ uint32_t nv108_pwr_code[] = {
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x0005f57e,
+        0x0007ad7e,
         0xf40464b6,
         0x5bcb6711,
         0x0076bbe0,
@@ -1382,37 +1565,37 @@ uint32_t nv108_pwr_code[] = {
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
-        0x417e50fc,
-        0x64b60005,
+        0xf97e50fc,
+        0x64b60006,
         0xbd5bb204,
         0x410ef474,
-/* 0x0818: i2c_recv_not_rd08 */
+/* 0x09d0: i2c_recv_not_rd08 */
         0xf401d6b0,
         0x00053b1b,
-        0x00069e7e,
+        0x0008567e,
         0xc73211f4,
-        0x447ee0c5,
-        0x11f40006,
+        0xfc7ee0c5,
+        0x11f40007,
         0x7e000528,
-        0xf400069e,
+        0xf4000856,
         0xb5c71f11,
-        0x06447ee0,
+        0x07fc7ee0,
         0x1511f400,
-        0x0005417e,
+        0x0006f97e,
         0xc5c774bd,
         0x091bf408,
         0xf40232f4,
-/* 0x0856: i2c_recv_not_wr08 */
-/* 0x0856: i2c_recv_done */
+/* 0x0a0e: i2c_recv_not_wr08 */
+/* 0x0a0e: i2c_recv_done */
         0xcec7030e,
-        0x07027ef8,
+        0x08ba7ef8,
         0xfce0fc00,
         0x0912f4d0,
-        0x3f7e7cb2,
-/* 0x086a: i2c_recv_exit */
+        0xc27e7cb2,
+/* 0x0a22: i2c_recv_exit */
         0x00f80002,
-/* 0x086c: i2c_init */
-/* 0x086e: test_recv */
+/* 0x0a24: i2c_init */
+/* 0x0a26: test_recv */
         0x584100f8,
         0x0011cf04,
         0x400110b6,
@@ -1420,28 +1603,28 @@ uint32_t nv108_pwr_code[] = {
         0xf104bd00,
         0xf1d900e7,
         0x7e134fe3,
-        0xf8000196,
-/* 0x088d: test_init */
+        0xf8000201,
+/* 0x0a45: test_init */
         0x08004e00,
-        0x0001967e,
-/* 0x0896: idle_recv */
+        0x0002017e,
+/* 0x0a4e: idle_recv */
         0x00f800f8,
-/* 0x0898: idle */
+/* 0x0a50: idle */
         0x410031f4,
         0x11cf0454,
         0x0110b600,
         0xf6045440,
         0x04bd0001,
-/* 0x08ac: idle_loop */
+/* 0x0a64: idle_loop */
         0x32f45801,
-/* 0x08b1: idle_proc */
-/* 0x08b1: idle_proc_exec */
+/* 0x0a69: idle_proc */
+/* 0x0a69: idle_proc_exec */
         0xb210f902,
-        0x02487e1e,
+        0x02cb7e1e,
         0xf410fc00,
         0x31f40911,
         0xf00ef402,
-/* 0x08c4: idle_proc_next */
+/* 0x0a7c: idle_proc_next */
         0xa65810b6,
         0xe81bf41f,
         0xf4e002f4,
@@ -1457,4 +1640,22 @@ uint32_t nv108_pwr_code[] = {
         0x00000000,
         0x00000000,
         0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
 };
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
index 6744fcc06151..daa06c1c655e 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
@@ -23,6 +23,7 @@
  */
 
 #define NVKM_PPWR_CHIPSET GT215
+#define HW_TICKS_PER_US 203 // should be 202.5
 
 //#define NVKM_FALCON_PC24
 //#define NVKM_FALCON_UNSHIFTED_IO
@@ -34,6 +35,7 @@
 .section #nva3_pwr_data
 #define INCLUDE_PROC
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
@@ -44,6 +46,7 @@
 
 #define INCLUDE_DATA
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
@@ -56,6 +59,7 @@
 .section #nva3_pwr_code
 #define INCLUDE_CODE
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
index e087ce3041be..64e97baabc3c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
@@ -24,8 +24,8 @@ uint32_t nva3_pwr_data[] = {
         0x00000000,
 /* 0x0058: proc_list_head */
         0x54534f48,
-        0x00000430,
-        0x000003cd,
+        0x00000512,
+        0x000004af,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -46,8 +46,8 @@ uint32_t nva3_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x584d454d,
-        0x00000542,
-        0x00000534,
+        0x000006e0,
+        0x000006d2,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -68,8 +68,8 @@ uint32_t nva3_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x46524550,
-        0x00000546,
-        0x00000544,
+        0x000006e4,
+        0x000006e2,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -90,8 +90,8 @@ uint32_t nva3_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x5f433249,
-        0x00000976,
-        0x00000819,
+        0x00000b14,
+        0x000009b7,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -112,8 +112,8 @@ uint32_t nva3_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x54534554,
-        0x0000099f,
-        0x00000978,
+        0x00000b3d,
+        0x00000b16,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -134,8 +134,8 @@ uint32_t nva3_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x454c4449,
-        0x000009ab,
-        0x000009a9,
+        0x00000b49,
+        0x00000b47,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -227,25 +227,31 @@ uint32_t nva3_pwr_data[] = {
         0x00000000,
         0x00000000,
 /* 0x0370: memx_func_head */
-        0x00010000,
-        0x00000000,
-        0x0000046f,
-/* 0x037c: memx_func_next */
         0x00000001,
         0x00000000,
-        0x00000496,
+        0x00000551,
+/* 0x037c: memx_func_next */
         0x00000002,
+        0x00000000,
+        0x000005a8,
+        0x00000003,
         0x00000002,
-        0x000004b7,
-        0x00040003,
+        0x0000063a,
+        0x00040004,
+        0x00000000,
+        0x00000656,
+        0x00010005,
+        0x00000000,
+        0x00000673,
+        0x00010006,
         0x00000000,
-        0x000004d3,
-        0x00010004,
+        0x000005f8,
+/* 0x03b8: memx_func_tail */
+/* 0x03b8: memx_ts_start */
         0x00000000,
-        0x000004f0,
-/* 0x03ac: memx_func_tail */
-/* 0x03ac: memx_data_head */
+/* 0x03bc: memx_ts_end */
         0x00000000,
+/* 0x03c0: memx_data_head */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -757,8 +763,9 @@ uint32_t nva3_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0bac: memx_data_tail */
-/* 0x0bac: i2c_scl_map */
+        0x00000000,
+/* 0x0bc0: memx_data_tail */
+/* 0x0bc0: i2c_scl_map */
         0x00001000,
         0x00004000,
         0x00010000,
@@ -769,7 +776,7 @@ uint32_t nva3_pwr_data[] = {
         0x01000000,
         0x04000000,
         0x10000000,
-/* 0x0bd4: i2c_sda_map */
+/* 0x0be8: i2c_sda_map */
         0x00002000,
         0x00008000,
         0x00020000,
@@ -780,7 +787,7 @@ uint32_t nva3_pwr_data[] = {
         0x02000000,
         0x08000000,
         0x20000000,
-/* 0x0bfc: i2c_ctrl */
+/* 0x0c10: i2c_ctrl */
         0x0000e138,
         0x0000e150,
         0x0000e168,
@@ -841,15 +848,10 @@ uint32_t nva3_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
 };
 
 uint32_t nva3_pwr_code[] = {
-        0x030d0ef5,
+        0x039e0ef5,
 /* 0x0004: rd32 */
         0x07a007f1,
         0xd00604b6,
@@ -885,19 +887,22 @@ uint32_t nva3_pwr_code[] = {
         0xd4f100dd,
         0x1bf47000,
 /* 0x007f: nsec */
-        0xf000f8f2,
+        0xf900f8f2,
+        0xf080f990,
         0x84b62c87,
         0x0088cf06,
-/* 0x0088: nsec_loop */
+/* 0x008c: nsec_loop */
         0xb62c97f0,
         0x99cf0694,
         0x0298bb00,
         0xf4069eb8,
-        0x00f8f11e,
-/* 0x009c: wait */
+        0x80fcf11e,
+        0x00f890fc,
+/* 0x00a4: wait */
+        0x80f990f9,
         0xb62c87f0,
         0x88cf0684,
-/* 0x00a5: wait_loop */
+/* 0x00b1: wait_loop */
         0x02eeb900,
         0xb90421f4,
         0xadfd02da,
@@ -907,28 +912,29 @@ uint32_t nva3_pwr_code[] = {
         0x0099cf06,
         0xb80298bb,
         0x1ef4069b,
-/* 0x00c9: wait_done */
-/* 0x00cb: intr_watchdog */
-        0x9800f8df,
+/* 0x00d5: wait_done */
+        0xfc80fcdf,
+/* 0x00db: intr_watchdog */
+        0x9800f890,
         0x96b003e9,
         0x2a0bf400,
         0xbb9a0a98,
         0x1cf4029a,
         0x01d7f00f,
-        0x025421f5,
+        0x02dd21f5,
         0x0ef494bd,
-/* 0x00e9: intr_watchdog_next_time */
+/* 0x00f9: intr_watchdog_next_time */
         0x9b0a9815,
         0xf400a6b0,
         0x9ab8090b,
         0x061cf406,
-/* 0x00f8: intr_watchdog_next_time_set */
-/* 0x00fb: intr_watchdog_next_proc */
+/* 0x0108: intr_watchdog_next_time_set */
+/* 0x010b: intr_watchdog_next_proc */
         0x809b0980,
         0xe0b603e9,
         0x68e6b158,
         0xc61bf402,
-/* 0x010a: intr */
+/* 0x011a: intr */
         0x00f900f8,
         0x80f904bd,
         0xa0f990f9,
@@ -948,13 +954,13 @@ uint32_t nva3_pwr_code[] = {
         0xf40289c4,
         0x0080230b,
         0x58e7f09b,
-        0x98cb21f4,
+        0x98db21f4,
         0x96b09b09,
         0x110bf400,
         0xb63407f0,
         0x09d00604,
         0x8004bd00,
-/* 0x016e: intr_skip_watchdog */
+/* 0x017e: intr_skip_watchdog */
         0x89e49a09,
         0x0bf40800,
         0x8897f148,
@@ -967,22 +973,22 @@ uint32_t nva3_pwr_code[] = {
         0x48e7f1c0,
         0x53e3f14f,
         0x00d7f054,
-        0x02b921f5,
+        0x034221f5,
         0x07f1c0fc,
         0x04b604c0,
         0x000cd006,
-/* 0x01ae: intr_subintr_skip_fifo */
+/* 0x01be: intr_subintr_skip_fifo */
         0x07f104bd,
         0x04b60688,
         0x0009d006,
-/* 0x01ba: intr_skip_subintr */
+/* 0x01ca: intr_skip_subintr */
         0x89c404bd,
         0x070bf420,
         0xffbfa4f1,
-/* 0x01c4: intr_skip_pause */
+/* 0x01d4: intr_skip_pause */
         0xf44089c4,
         0xa4f1070b,
-/* 0x01ce: intr_skip_user0 */
+/* 0x01de: intr_skip_user0 */
         0x07f0ffbf,
         0x0604b604,
         0xbd0008d0,
@@ -993,596 +999,732 @@ uint32_t nva3_pwr_code[] = {
         0x90fca0fc,
         0x00fc80fc,
         0xf80032f4,
-/* 0x01f5: timer */
-        0x1032f401,
-        0xb003f898,
-        0x1cf40086,
-        0x03fe8051,
+/* 0x0205: ticks_from_ns */
+        0xf9c0f901,
+        0xcbd7f1b0,
+        0x00d3f000,
+        0x041321f5,
+        0x03e8ccec,
+        0xf400b4b0,
+        0xeeec120b,
+        0xd7f103e8,
+        0xd3f000cb,
+        0x1321f500,
+/* 0x022d: ticks_from_ns_quit */
+        0x02ceb904,
+        0xc0fcb0fc,
+/* 0x0236: ticks_from_us */
+        0xc0f900f8,
+        0xd7f1b0f9,
+        0xd3f000cb,
+        0x1321f500,
+        0x02ceb904,
+        0xf400b4b0,
+        0xe4bd050b,
+/* 0x0250: ticks_from_us_quit */
+        0xc0fcb0fc,
+/* 0x0256: ticks_to_us */
+        0xd7f100f8,
+        0xd3f000cb,
+        0xecedff00,
+/* 0x0262: timer */
+        0x90f900f8,
+        0x32f480f9,
+        0x03f89810,
+        0xf40086b0,
+        0x84bd651c,
         0xb63807f0,
         0x08d00604,
         0xf004bd00,
-        0x84b60887,
+        0x84b63487,
         0x0088cf06,
-        0xf40284f0,
-        0x87f0261b,
-        0x0684b634,
-        0xb80088cf,
-        0x0bf406e0,
-        0x06e8b809,
-/* 0x0233: timer_reset */
-        0xf01f1ef4,
-        0x04b63407,
-        0x000ed006,
-        0x0e8004bd,
-/* 0x0241: timer_enable */
-        0x0187f09a,
+        0xbb9a0998,
+        0xe9bb0298,
+        0x03fe8000,
+        0xb60887f0,
+        0x88cf0684,
+        0x0284f000,
+        0xf0261bf4,
+        0x84b63487,
+        0x0088cf06,
+        0xf406e0b8,
+        0xe8b8090b,
+        0x111cf406,
+/* 0x02b8: timer_reset */
+        0xb63407f0,
+        0x0ed00604,
+        0x8004bd00,
+/* 0x02c6: timer_enable */
+        0x87f09a0e,
+        0x3807f001,
+        0xd00604b6,
+        0x04bd0008,
+/* 0x02d4: timer_done */
+        0xfc1031f4,
+        0xf890fc80,
+/* 0x02dd: send_proc */
+        0xf980f900,
+        0x05e89890,
+        0xf004e998,
+        0x89b80486,
+        0x2a0bf406,
+        0x940398c4,
+        0x80b60488,
+        0x008ebb18,
+        0x8000fa98,
+        0x8d80008a,
+        0x028c8001,
+        0xb6038b80,
+        0x94f00190,
+        0x04e98007,
+/* 0x0317: send_done */
+        0xfc0231f4,
+        0xf880fc90,
+/* 0x031d: find */
+        0xf080f900,
+        0x31f45887,
+/* 0x0325: find_loop */
+        0x008a9801,
+        0xf406aeb8,
+        0x80b6100b,
+        0x6886b158,
+        0xf01bf402,
+/* 0x033b: find_done */
+        0xb90132f4,
+        0x80fc028e,
+/* 0x0342: send */
+        0x21f500f8,
+        0x01f4031d,
+/* 0x034b: recv */
+        0xf900f897,
+        0x9880f990,
+        0xe99805e8,
+        0x0132f404,
+        0xf40689b8,
+        0x89c43d0b,
+        0x0180b603,
+        0x800784f0,
+        0xea9805e8,
+        0xfef0f902,
+        0xf0f9018f,
+        0x9402efb9,
+        0xe9bb0499,
+        0x18e0b600,
+        0x9803eb98,
+        0xed9802ec,
+        0x00ee9801,
+        0xf0fca5f9,
+        0xf400f8fe,
+        0xf0fc0131,
+/* 0x0398: recv_done */
+        0x90fc80fc,
+/* 0x039e: init */
+        0x17f100f8,
+        0x14b60108,
+        0x0011cf06,
+        0x010911e7,
+        0xfe0814b6,
+        0x17f10014,
+        0x13f000e0,
+        0x1c07f000,
+        0xd00604b6,
+        0x04bd0001,
+        0xf0ff17f0,
+        0x04b61407,
+        0x0001d006,
+        0x17f004bd,
+        0x0015f102,
+        0x1007f008,
+        0xd00604b6,
+        0x04bd0001,
+        0x011a17f1,
+        0xfe0013f0,
+        0x31f40010,
+        0x0117f010,
         0xb63807f0,
-        0x08d00604,
-/* 0x024f: timer_done */
-        0xf404bd00,
-        0x00f81031,
-/* 0x0254: send_proc */
-        0x90f980f9,
-        0x9805e898,
-        0x86f004e9,
-        0x0689b804,
-        0xc42a0bf4,
-        0x88940398,
-        0x1880b604,
-        0x98008ebb,
-        0x8a8000fa,
-        0x018d8000,
-        0x80028c80,
-        0x90b6038b,
-        0x0794f001,
-        0xf404e980,
-/* 0x028e: send_done */
-        0x90fc0231,
-        0x00f880fc,
-/* 0x0294: find */
-        0x87f080f9,
-        0x0131f458,
-/* 0x029c: find_loop */
-        0xb8008a98,
-        0x0bf406ae,
-        0x5880b610,
-        0x026886b1,
-        0xf4f01bf4,
-/* 0x02b2: find_done */
-        0x8eb90132,
-        0xf880fc02,
-/* 0x02b9: send */
-        0x9421f500,
-        0x9701f402,
-/* 0x02c2: recv */
-        0xe89800f8,
-        0x04e99805,
-        0xb80132f4,
-        0x0bf40689,
-        0x0389c43d,
-        0xf00180b6,
-        0xe8800784,
-        0x02ea9805,
-        0x8ffef0f9,
-        0xb9f0f901,
-        0x999402ef,
-        0x00e9bb04,
-        0x9818e0b6,
-        0xec9803eb,
-        0x01ed9802,
-        0xf900ee98,
-        0xfef0fca5,
-        0x31f400f8,
-/* 0x030b: recv_done */
-        0xf8f0fc01,
-/* 0x030d: init */
-        0x0817f100,
-        0x0614b601,
-        0xe70011cf,
-        0xb6010911,
-        0x14fe0814,
-        0xe017f100,
-        0x0013f000,
-        0xb61c07f0,
         0x01d00604,
         0xf004bd00,
-        0x07f0ff17,
-        0x0604b614,
-        0xbd0001d0,
-        0x0217f004,
-        0x080015f1,
-        0xb61007f0,
-        0x01d00604,
-        0xf104bd00,
-        0xf0010a17,
-        0x10fe0013,
-        0x1031f400,
-        0xf00117f0,
-        0x04b63807,
-        0x0001d006,
-        0xf7f004bd,
-/* 0x0371: init_proc */
-        0x01f19858,
-        0xf40016b0,
-        0x15f9fa0b,
-        0xf458f0b6,
-/* 0x0382: host_send */
-        0x17f1f20e,
-        0x14b604b0,
-        0x0011cf06,
-        0x04a027f1,
-        0xcf0624b6,
-        0x12b80022,
-        0x320bf406,
-        0x94071ec4,
-        0xe0b704ee,
-        0xeb980270,
-        0x02ec9803,
-        0x9801ed98,
-        0x21f500ee,
-        0x10b602b9,
-        0x0f1ec401,
-        0x04b007f1,
-        0xd00604b6,
-        0x04bd000e,
-/* 0x03cb: host_send_done */
-        0xf8ba0ef4,
-/* 0x03cd: host_recv */
-        0x4917f100,
-        0x5413f14e,
-        0x06e1b852,
-/* 0x03db: host_recv_wait */
-        0xf1aa0bf4,
-        0xb604cc17,
-        0x11cf0614,
-        0xc827f100,
-        0x0624b604,
-        0xf00022cf,
-        0x12b80816,
-        0xe60bf406,
-        0xb60723c4,
-        0x30b70434,
-        0x3b8002f0,
-        0x023c8003,
-        0x80013d80,
-        0x20b6003e,
-        0x0f24f001,
-        0x04c807f1,
+/* 0x0402: init_proc */
+        0xf19858f7,
+        0x0016b001,
+        0xf9fa0bf4,
+        0x58f0b615,
+/* 0x0413: mulu32_32_64 */
+        0xf9f20ef4,
+        0xf920f910,
+        0x9540f930,
+        0xd29510e1,
+        0xbdc4bd10,
+        0xc0edffb4,
+        0xb9301dff,
+        0x34f10234,
+        0x34b6ffff,
+        0x1045b610,
+        0xbb00c3bb,
+        0xe2ff01b4,
+        0x0234b930,
+        0xffff34f1,
+        0xb61034b6,
+        0xc3bb1045,
+        0x01b4bb00,
+        0xbb3012ff,
+        0x40fc00b3,
+        0x20fc30fc,
+        0x00f810fc,
+/* 0x0464: host_send */
+        0x04b017f1,
+        0xcf0614b6,
+        0x27f10011,
+        0x24b604a0,
+        0x0022cf06,
+        0xf40612b8,
+        0x1ec4320b,
+        0x04ee9407,
+        0x0270e0b7,
+        0x9803eb98,
+        0xed9802ec,
+        0x00ee9801,
+        0x034221f5,
+        0xc40110b6,
+        0x07f10f1e,
+        0x04b604b0,
+        0x000ed006,
+        0x0ef404bd,
+/* 0x04ad: host_send_done */
+/* 0x04af: host_recv */
+        0xf100f8ba,
+        0xf14e4917,
+        0xb8525413,
+        0x0bf406e1,
+/* 0x04bd: host_recv_wait */
+        0xcc17f1aa,
+        0x0614b604,
+        0xf10011cf,
+        0xb604c827,
+        0x22cf0624,
+        0x0816f000,
+        0xf40612b8,
+        0x23c4e60b,
+        0x0434b607,
+        0x02f030b7,
+        0x80033b80,
+        0x3d80023c,
+        0x003e8001,
+        0xf00120b6,
+        0x07f10f24,
+        0x04b604c8,
+        0x0002d006,
+        0x27f004bd,
+        0x0007f040,
         0xd00604b6,
         0x04bd0002,
-        0xf04027f0,
-        0x04b60007,
-        0x0002d006,
-        0x00f804bd,
-/* 0x0430: host_init */
-        0x008017f1,
-        0xf11014b6,
-        0xf1027015,
-        0xb604d007,
-        0x01d00604,
-        0xf104bd00,
-        0xb6008017,
-        0x15f11014,
-        0x07f102f0,
-        0x04b604dc,
-        0x0001d006,
-        0x17f004bd,
-        0xc407f101,
+/* 0x0512: host_init */
+        0x17f100f8,
+        0x14b60080,
+        0x7015f110,
+        0xd007f102,
         0x0604b604,
         0xbd0001d0,
-/* 0x046f: memx_func_enter */
-        0xf000f804,
+        0x8017f104,
+        0x1014b600,
+        0x02f015f1,
+        0x04dc07f1,
+        0xd00604b6,
+        0x04bd0001,
+        0xf10117f0,
+        0xb604c407,
+        0x01d00604,
+        0xf804bd00,
+/* 0x0551: memx_func_enter */
+        0x1087f100,
+        0x028eb916,
+        0xb90421f4,
+        0x67f102d7,
+        0x63f1fffc,
+        0x76fdffff,
+        0x0267f104,
+        0x0576fd00,
+        0x70f980f9,
+        0xe0fcd0fc,
+        0xf03f21f4,
         0x07f10467,
         0x04b607e0,
         0x0006d006,
-/* 0x047e: memx_func_enter_wait */
+/* 0x058a: memx_func_enter_wait */
         0x67f104bd,
         0x64b607c0,
         0x0066cf06,
         0xf40464f0,
-        0x1698f30b,
-        0x0410b600,
-/* 0x0496: memx_func_leave */
-        0x67f000f8,
-        0xe407f104,
-        0x0604b607,
-        0xbd0006d0,
-/* 0x04a5: memx_func_leave_wait */
-        0xc067f104,
+        0x67f0f30b,
+        0x0664b62c,
+        0x800066cf,
+        0x00f8ee06,
+/* 0x05a8: memx_func_leave */
+        0xb62c67f0,
+        0x66cf0664,
+        0xef068000,
+        0xf10467f0,
+        0xb607e407,
+        0x06d00604,
+/* 0x05c3: memx_func_leave_wait */
+        0xf104bd00,
+        0xb607c067,
+        0x66cf0664,
+        0x0464f000,
+        0xf1f31bf4,
+        0xb9161087,
+        0x21f4028e,
+        0x02d7b904,
+        0xffcc67f1,
+        0xffff63f1,
+        0xf90476fd,
+        0xfc70f980,
+        0xf4e0fcd0,
+        0x00f83f21,
+/* 0x05f8: memx_func_wait_vblank */
+        0xb0001698,
+        0x0bf40066,
+        0x0166b013,
+        0xf4060bf4,
+/* 0x060a: memx_func_wait_vblank_head1 */
+        0x77f12e0e,
+        0x0ef40020,
+/* 0x0611: memx_func_wait_vblank_head0 */
+        0x0877f107,
+/* 0x0615: memx_func_wait_vblank_0 */
+        0xc467f100,
         0x0664b607,
-        0xf00066cf,
-        0x1bf40464,
-/* 0x04b7: memx_func_wr32 */
-        0x9800f8f3,
-        0x15980016,
-        0x0810b601,
-        0x50f960f9,
-        0xe0fcd0fc,
-        0xb63f21f4,
-        0x1bf40242,
-/* 0x04d3: memx_func_wait */
-        0xf000f8e9,
-        0x84b62c87,
-        0x0088cf06,
-        0x98001e98,
-        0x1c98011d,
-        0x031b9802,
-        0xf41010b6,
-        0x00f89c21,
-/* 0x04f0: memx_func_delay */
-        0xb6001e98,
-        0x21f40410,
-/* 0x04fb: memx_exec */
-        0xf900f87f,
-        0xb9d0f9e0,
-        0xb2b902c1,
-/* 0x0505: memx_exec_next */
-        0x00139802,
-        0x950410b6,
-        0x30f01034,
-        0xde35980c,
-        0x12b855f9,
-        0xec1ef406,
-        0xe0fcd0fc,
-        0x02b921f5,
-/* 0x0526: memx_info */
-        0xc7f100f8,
-        0xb7f103ac,
-        0x21f50800,
-        0x00f802b9,
-/* 0x0534: memx_recv */
-        0xf401d6b0,
-        0xd6b0c40b,
-        0xe90bf400,
-/* 0x0542: memx_init */
-        0x00f800f8,
-/* 0x0544: perf_recv */
-/* 0x0546: perf_init */
+        0xfd0066cf,
+        0x1bf40467,
+/* 0x0625: memx_func_wait_vblank_1 */
+        0xc467f1f3,
+        0x0664b607,
+        0xfd0066cf,
+        0x0bf40467,
+/* 0x0635: memx_func_wait_vblank_fini */
+        0x0410b6f3,
+/* 0x063a: memx_func_wr32 */
+        0x169800f8,
+        0x01159800,
+        0xf90810b6,
+        0xfc50f960,
+        0xf4e0fcd0,
+        0x42b63f21,
+        0xe91bf402,
+/* 0x0656: memx_func_wait */
+        0x87f000f8,
+        0x0684b62c,
+        0x980088cf,
+        0x1d98001e,
+        0x021c9801,
+        0xb6031b98,
+        0x21f41010,
+/* 0x0673: memx_func_delay */
+        0x9800f8a4,
+        0x10b6001e,
+        0x7f21f404,
+/* 0x067e: memx_exec */
+        0xe0f900f8,
+        0xc1b9d0f9,
+        0x02b2b902,
+/* 0x0688: memx_exec_next */
+        0xb6001398,
+        0x34e70410,
+        0x33e701f0,
+        0x32b601e0,
+        0x0c30f001,
+        0xf9de3598,
+        0x0612b855,
+        0x98e41ef4,
+        0x0c98ee0b,
+        0x02cbbbef,
+        0x07c4b7f1,
+        0xcf06b4b6,
+        0xd0fc00bb,
+        0x21f5e0fc,
+        0x00f80342,
+/* 0x06c4: memx_info */
+        0x03c0c7f1,
+        0x0800b7f1,
+        0x034221f5,
+/* 0x06d2: memx_recv */
+        0xd6b000f8,
+        0xa90bf401,
+        0xf400d6b0,
+        0x00f8e90b,
+/* 0x06e0: memx_init */
+/* 0x06e2: perf_recv */
         0x00f800f8,
-/* 0x0548: i2c_drive_scl */
-        0xf40036b0,
-        0x07f1110b,
-        0x04b607e0,
-        0x0001d006,
-        0x00f804bd,
-/* 0x055c: i2c_drive_scl_lo */
-        0x07e407f1,
-        0xd00604b6,
-        0x04bd0001,
-/* 0x056a: i2c_drive_sda */
+/* 0x06e4: perf_init */
+/* 0x06e6: i2c_drive_scl */
         0x36b000f8,
         0x110bf400,
         0x07e007f1,
         0xd00604b6,
-        0x04bd0002,
-/* 0x057e: i2c_drive_sda_lo */
+        0x04bd0001,
+/* 0x06fa: i2c_drive_scl_lo */
         0x07f100f8,
         0x04b607e4,
+        0x0001d006,
+        0x00f804bd,
+/* 0x0708: i2c_drive_sda */
+        0xf40036b0,
+        0x07f1110b,
+        0x04b607e0,
         0x0002d006,
         0x00f804bd,
-/* 0x058c: i2c_sense_scl */
-        0xf10132f4,
-        0xb607c437,
-        0x33cf0634,
-        0x0431fd00,
-        0xf4060bf4,
-/* 0x05a2: i2c_sense_scl_done */
-        0x00f80131,
-/* 0x05a4: i2c_sense_sda */
-        0xf10132f4,
-        0xb607c437,
-        0x33cf0634,
-        0x0432fd00,
-        0xf4060bf4,
-/* 0x05ba: i2c_sense_sda_done */
-        0x00f80131,
-/* 0x05bc: i2c_raise_scl */
-        0x47f140f9,
-        0x37f00898,
-        0x4821f501,
-/* 0x05c9: i2c_raise_scl_wait */
-        0xe8e7f105,
-        0x7f21f403,
-        0x058c21f5,
-        0xb60901f4,
-        0x1bf40142,
-/* 0x05dd: i2c_raise_scl_done */
-        0xf840fcef,
-/* 0x05e1: i2c_start */
-        0x8c21f500,
-        0x0d11f405,
-        0x05a421f5,
-        0xf40611f4,
-/* 0x05f2: i2c_start_rep */
-        0x37f0300e,
-        0x4821f500,
-        0x0137f005,
-        0x056a21f5,
-        0xb60076bb,
-        0x50f90465,
-        0xbb046594,
-        0x50bd0256,
-        0xfc0475fd,
-        0xbc21f550,
-        0x0464b605,
-/* 0x061f: i2c_start_send */
-        0xf01f11f4,
+/* 0x071c: i2c_drive_sda_lo */
+        0x07e407f1,
+        0xd00604b6,
+        0x04bd0002,
+/* 0x072a: i2c_sense_scl */
+        0x32f400f8,
+        0xc437f101,
+        0x0634b607,
+        0xfd0033cf,
+        0x0bf40431,
+        0x0131f406,
+/* 0x0740: i2c_sense_scl_done */
+/* 0x0742: i2c_sense_sda */
+        0x32f400f8,
+        0xc437f101,
+        0x0634b607,
+        0xfd0033cf,
+        0x0bf40432,
+        0x0131f406,
+/* 0x0758: i2c_sense_sda_done */
+/* 0x075a: i2c_raise_scl */
+        0x40f900f8,
+        0x089847f1,
+        0xf50137f0,
+/* 0x0767: i2c_raise_scl_wait */
+        0xf106e621,
+        0xf403e8e7,
+        0x21f57f21,
+        0x01f4072a,
+        0x0142b609,
+/* 0x077b: i2c_raise_scl_done */
+        0xfcef1bf4,
+/* 0x077f: i2c_start */
+        0xf500f840,
+        0xf4072a21,
+        0x21f50d11,
+        0x11f40742,
+        0x300ef406,
+/* 0x0790: i2c_start_rep */
+        0xf50037f0,
+        0xf006e621,
+        0x21f50137,
+        0x76bb0708,
+        0x0465b600,
+        0x659450f9,
+        0x0256bb04,
+        0x75fd50bd,
+        0xf550fc04,
+        0xb6075a21,
+        0x11f40464,
+/* 0x07bd: i2c_start_send */
+        0x0037f01f,
+        0x070821f5,
+        0x1388e7f1,
+        0xf07f21f4,
         0x21f50037,
-        0xe7f1056a,
+        0xe7f106e6,
         0x21f41388,
-        0x0037f07f,
-        0x054821f5,
-        0x1388e7f1,
-/* 0x063b: i2c_start_out */
-        0xf87f21f4,
-/* 0x063d: i2c_stop */
-        0x0037f000,
-        0x054821f5,
-        0xf50037f0,
-        0xf1056a21,
-        0xf403e8e7,
-        0x37f07f21,
-        0x4821f501,
-        0x88e7f105,
-        0x7f21f413,
+/* 0x07d9: i2c_start_out */
+/* 0x07db: i2c_stop */
+        0xf000f87f,
+        0x21f50037,
+        0x37f006e6,
+        0x0821f500,
+        0xe8e7f107,
+        0x7f21f403,
         0xf50137f0,
-        0xf1056a21,
+        0xf106e621,
         0xf41388e7,
-        0x00f87f21,
-/* 0x0670: i2c_bitw */
-        0x056a21f5,
-        0x03e8e7f1,
-        0xbb7f21f4,
-        0x65b60076,
-        0x9450f904,
-        0x56bb0465,
-        0xfd50bd02,
-        0x50fc0475,
-        0x05bc21f5,
-        0xf40464b6,
-        0xe7f11811,
-        0x21f41388,
-        0x0037f07f,
-        0x054821f5,
-        0x1388e7f1,
-/* 0x06af: i2c_bitw_out */
-        0xf87f21f4,
-/* 0x06b1: i2c_bitr */
-        0x0137f000,
-        0x056a21f5,
-        0x03e8e7f1,
-        0xbb7f21f4,
-        0x65b60076,
-        0x9450f904,
-        0x56bb0465,
-        0xfd50bd02,
-        0x50fc0475,
-        0x05bc21f5,
-        0xf40464b6,
-        0x21f51b11,
-        0x37f005a4,
-        0x4821f500,
-        0x88e7f105,
+        0x37f07f21,
+        0x0821f501,
+        0x88e7f107,
         0x7f21f413,
-        0xf4013cf0,
-/* 0x06f6: i2c_bitr_done */
-        0x00f80131,
-/* 0x06f8: i2c_get_byte */
-        0xf00057f0,
-/* 0x06fe: i2c_get_byte_next */
-        0x54b60847,
-        0x0076bb01,
+/* 0x080e: i2c_bitw */
+        0x21f500f8,
+        0xe7f10708,
+        0x21f403e8,
+        0x0076bb7f,
         0xf90465b6,
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
         0x21f550fc,
-        0x64b606b1,
-        0x2b11f404,
-        0xb60553fd,
-        0x1bf40142,
-        0x0137f0d8,
-        0xb60076bb,
-        0x50f90465,
-        0xbb046594,
-        0x50bd0256,
-        0xfc0475fd,
-        0x7021f550,
-        0x0464b606,
-/* 0x0748: i2c_get_byte_done */
-/* 0x074a: i2c_put_byte */
-        0x47f000f8,
-/* 0x074d: i2c_put_byte_next */
-        0x0142b608,
-        0xbb3854ff,
+        0x64b6075a,
+        0x1811f404,
+        0x1388e7f1,
+        0xf07f21f4,
+        0x21f50037,
+        0xe7f106e6,
+        0x21f41388,
+/* 0x084d: i2c_bitw_out */
+/* 0x084f: i2c_bitr */
+        0xf000f87f,
+        0x21f50137,
+        0xe7f10708,
+        0x21f403e8,
+        0x0076bb7f,
+        0xf90465b6,
+        0x04659450,
+        0xbd0256bb,
+        0x0475fd50,
+        0x21f550fc,
+        0x64b6075a,
+        0x1b11f404,
+        0x074221f5,
+        0xf50037f0,
+        0xf106e621,
+        0xf41388e7,
+        0x3cf07f21,
+        0x0131f401,
+/* 0x0894: i2c_bitr_done */
+/* 0x0896: i2c_get_byte */
+        0x57f000f8,
+        0x0847f000,
+/* 0x089c: i2c_get_byte_next */
+        0xbb0154b6,
         0x65b60076,
         0x9450f904,
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x067021f5,
+        0x084f21f5,
         0xf40464b6,
-        0x46b03411,
-        0xd81bf400,
-        0xb60076bb,
-        0x50f90465,
-        0xbb046594,
-        0x50bd0256,
-        0xfc0475fd,
-        0xb121f550,
-        0x0464b606,
-        0xbb0f11f4,
-        0x36b00076,
-        0x061bf401,
-/* 0x07a3: i2c_put_byte_done */
-        0xf80132f4,
-/* 0x07a5: i2c_addr */
-        0x0076bb00,
+        0x53fd2b11,
+        0x0142b605,
+        0xf0d81bf4,
+        0x76bb0137,
+        0x0465b600,
+        0x659450f9,
+        0x0256bb04,
+        0x75fd50bd,
+        0xf550fc04,
+        0xb6080e21,
+/* 0x08e6: i2c_get_byte_done */
+        0x00f80464,
+/* 0x08e8: i2c_put_byte */
+/* 0x08eb: i2c_put_byte_next */
+        0xb60847f0,
+        0x54ff0142,
+        0x0076bb38,
         0xf90465b6,
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
         0x21f550fc,
-        0x64b605e1,
-        0x2911f404,
-        0x012ec3e7,
-        0xfd0134b6,
-        0x76bb0553,
+        0x64b6080e,
+        0x3411f404,
+        0xf40046b0,
+        0x76bbd81b,
         0x0465b600,
         0x659450f9,
         0x0256bb04,
         0x75fd50bd,
         0xf550fc04,
-        0xb6074a21,
-/* 0x07ea: i2c_addr_done */
-        0x00f80464,
-/* 0x07ec: i2c_acquire_addr */
-        0xb6f8cec7,
-        0xe0b702e4,
-        0xee980bfc,
-/* 0x07fb: i2c_acquire */
-        0xf500f800,
-        0xf407ec21,
-        0xd9f00421,
-        0x3f21f403,
-/* 0x080a: i2c_release */
-        0x21f500f8,
-        0x21f407ec,
-        0x03daf004,
-        0xf83f21f4,
-/* 0x0819: i2c_recv */
-        0x0132f400,
-        0xb6f8c1c7,
-        0x16b00214,
-        0x3a1ff528,
-        0xd413a001,
-        0x0032980b,
-        0x0bac13a0,
-        0xf4003198,
-        0xd0f90231,
-        0xd0f9e0f9,
-        0x000067f1,
-        0x100063f1,
-        0xbb016792,
+        0xb6084f21,
+        0x11f40464,
+        0x0076bb0f,
+        0xf40136b0,
+        0x32f4061b,
+/* 0x0941: i2c_put_byte_done */
+/* 0x0943: i2c_addr */
+        0xbb00f801,
         0x65b60076,
         0x9450f904,
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x07fb21f5,
-        0xfc0464b6,
-        0x00d6b0d0,
-        0x00b31bf5,
-        0xbb0057f0,
-        0x65b60076,
-        0x9450f904,
-        0x56bb0465,
-        0xfd50bd02,
-        0x50fc0475,
-        0x07a521f5,
-        0xf50464b6,
-        0xc700d011,
-        0x76bbe0c5,
-        0x0465b600,
-        0x659450f9,
-        0x0256bb04,
-        0x75fd50bd,
-        0xf550fc04,
-        0xb6074a21,
-        0x11f50464,
-        0x57f000ad,
+        0x077f21f5,
+        0xf40464b6,
+        0xc3e72911,
+        0x34b6012e,
+        0x0553fd01,
+        0xb60076bb,
+        0x50f90465,
+        0xbb046594,
+        0x50bd0256,
+        0xfc0475fd,
+        0xe821f550,
+        0x0464b608,
+/* 0x0988: i2c_addr_done */
+/* 0x098a: i2c_acquire_addr */
+        0xcec700f8,
+        0x02e4b6f8,
+        0x0c10e0b7,
+        0xf800ee98,
+/* 0x0999: i2c_acquire */
+        0x8a21f500,
+        0x0421f409,
+        0xf403d9f0,
+        0x00f83f21,
+/* 0x09a8: i2c_release */
+        0x098a21f5,
+        0xf00421f4,
+        0x21f403da,
+/* 0x09b7: i2c_recv */
+        0xf400f83f,
+        0xc1c70132,
+        0x0214b6f8,
+        0xf52816b0,
+        0xa0013a1f,
+        0x980be813,
+        0x13a00032,
+        0x31980bc0,
+        0x0231f400,
+        0xe0f9d0f9,
+        0x67f1d0f9,
+        0x63f10000,
+        0x67921000,
         0x0076bb01,
         0xf90465b6,
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
         0x21f550fc,
-        0x64b607a5,
-        0x8a11f504,
+        0x64b60999,
+        0xb0d0fc04,
+        0x1bf500d6,
+        0x57f000b3,
         0x0076bb00,
         0xf90465b6,
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
         0x21f550fc,
-        0x64b606f8,
-        0x6a11f404,
-        0xbbe05bcb,
+        0x64b60943,
+        0xd011f504,
+        0xe0c5c700,
+        0xb60076bb,
+        0x50f90465,
+        0xbb046594,
+        0x50bd0256,
+        0xfc0475fd,
+        0xe821f550,
+        0x0464b608,
+        0x00ad11f5,
+        0xbb0157f0,
         0x65b60076,
         0x9450f904,
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x063d21f5,
-        0xb90464b6,
-        0x74bd025b,
-/* 0x091f: i2c_recv_not_rd08 */
-        0xb0430ef4,
-        0x1bf401d6,
-        0x0057f03d,
-        0x07a521f5,
-        0xc73311f4,
-        0x21f5e0c5,
-        0x11f4074a,
-        0x0057f029,
-        0x07a521f5,
-        0xc71f11f4,
-        0x21f5e0b5,
-        0x11f4074a,
-        0x3d21f515,
-        0xc774bd06,
-        0x1bf408c5,
-        0x0232f409,
-/* 0x095f: i2c_recv_not_wr08 */
-/* 0x095f: i2c_recv_done */
-        0xc7030ef4,
-        0x21f5f8ce,
-        0xe0fc080a,
-        0x12f4d0fc,
-        0x027cb90a,
-        0x02b921f5,
-/* 0x0974: i2c_recv_exit */
-/* 0x0976: i2c_init */
-        0x00f800f8,
-/* 0x0978: test_recv */
-        0x05d817f1,
+        0x094321f5,
+        0xf50464b6,
+        0xbb008a11,
+        0x65b60076,
+        0x9450f904,
+        0x56bb0465,
+        0xfd50bd02,
+        0x50fc0475,
+        0x089621f5,
+        0xf40464b6,
+        0x5bcb6a11,
+        0x0076bbe0,
+        0xf90465b6,
+        0x04659450,
+        0xbd0256bb,
+        0x0475fd50,
+        0x21f550fc,
+        0x64b607db,
+        0x025bb904,
+        0x0ef474bd,
+/* 0x0abd: i2c_recv_not_rd08 */
+        0x01d6b043,
+        0xf03d1bf4,
+        0x21f50057,
+        0x11f40943,
+        0xe0c5c733,
+        0x08e821f5,
+        0xf02911f4,
+        0x21f50057,
+        0x11f40943,
+        0xe0b5c71f,
+        0x08e821f5,
+        0xf51511f4,
+        0xbd07db21,
+        0x08c5c774,
+        0xf4091bf4,
+        0x0ef40232,
+/* 0x0afd: i2c_recv_not_wr08 */
+/* 0x0afd: i2c_recv_done */
+        0xf8cec703,
+        0x09a821f5,
+        0xd0fce0fc,
+        0xb90a12f4,
+        0x21f5027c,
+/* 0x0b12: i2c_recv_exit */
+        0x00f80342,
+/* 0x0b14: i2c_init */
+/* 0x0b16: test_recv */
+        0x17f100f8,
+        0x14b605d8,
+        0x0011cf06,
+        0xf10110b6,
+        0xb605d807,
+        0x01d00604,
+        0xf104bd00,
+        0xf1d900e7,
+        0xf5134fe3,
+        0xf8026221,
+/* 0x0b3d: test_init */
+        0x00e7f100,
+        0x6221f508,
+/* 0x0b47: idle_recv */
+        0xf800f802,
+/* 0x0b49: idle */
+        0x0031f400,
+        0x05d417f1,
         0xcf0614b6,
         0x10b60011,
-        0xd807f101,
+        0xd407f101,
         0x0604b605,
         0xbd0001d0,
-        0x00e7f104,
-        0x4fe3f1d9,
-        0xf521f513,
-/* 0x099f: test_init */
-        0xf100f801,
-        0xf50800e7,
-        0xf801f521,
-/* 0x09a9: idle_recv */
-/* 0x09ab: idle */
-        0xf400f800,
-        0x17f10031,
-        0x14b605d4,
-        0x0011cf06,
-        0xf10110b6,
-        0xb605d407,
-        0x01d00604,
-/* 0x09c7: idle_loop */
-        0xf004bd00,
-        0x32f45817,
-/* 0x09cd: idle_proc */
-/* 0x09cd: idle_proc_exec */
-        0xb910f902,
-        0x21f5021e,
-        0x10fc02c2,
-        0xf40911f4,
-        0x0ef40231,
-/* 0x09e1: idle_proc_next */
-        0x5810b6ef,
-        0xf4061fb8,
-        0x02f4e61b,
-        0x0028f4dd,
-        0x00bb0ef4,
+/* 0x0b65: idle_loop */
+        0x5817f004,
+/* 0x0b6b: idle_proc */
+/* 0x0b6b: idle_proc_exec */
+        0xf90232f4,
+        0x021eb910,
+        0x034b21f5,
+        0x11f410fc,
+        0x0231f409,
+/* 0x0b7f: idle_proc_next */
+        0xb6ef0ef4,
+        0x1fb85810,
+        0xe61bf406,
+        0xf4dd02f4,
+        0x0ef40028,
+        0x000000bb,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
         0x00000000,
         0x00000000,
         0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
index 48f79434a449..21bf8cc7618f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
@@ -23,6 +23,7 @@
  */
 
 #define NVKM_PPWR_CHIPSET GF100
+#define HW_TICKS_PER_US 203 // should be 202.5
 
 //#define NVKM_FALCON_PC24
 //#define NVKM_FALCON_UNSHIFTED_IO
@@ -34,6 +35,7 @@
 .section #nvc0_pwr_data
 #define INCLUDE_PROC
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
@@ -44,6 +46,7 @@
 
 #define INCLUDE_DATA
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
@@ -56,6 +59,7 @@
 .section #nvc0_pwr_code
 #define INCLUDE_CODE
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
index 0773ff0e3dc3..ca30fa4011b5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
@@ -24,8 +24,8 @@ uint32_t nvc0_pwr_data[] = {
         0x00000000,
 /* 0x0058: proc_list_head */
         0x54534f48,
-        0x00000430,
-        0x000003cd,
+        0x00000512,
+        0x000004af,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -46,8 +46,8 @@ uint32_t nvc0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x584d454d,
-        0x00000542,
-        0x00000534,
+        0x0000074b,
+        0x0000073d,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -68,8 +68,8 @@ uint32_t nvc0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x46524550,
-        0x00000546,
-        0x00000544,
+        0x0000074f,
+        0x0000074d,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -90,8 +90,8 @@ uint32_t nvc0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x5f433249,
-        0x00000976,
-        0x00000819,
+        0x00000b7f,
+        0x00000a22,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -112,8 +112,8 @@ uint32_t nvc0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x54534554,
-        0x0000099f,
-        0x00000978,
+        0x00000ba8,
+        0x00000b81,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -134,8 +134,8 @@ uint32_t nvc0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x454c4449,
-        0x000009ab,
-        0x000009a9,
+        0x00000bb4,
+        0x00000bb2,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -227,25 +227,31 @@ uint32_t nvc0_pwr_data[] = {
         0x00000000,
         0x00000000,
 /* 0x0370: memx_func_head */
-        0x00010000,
-        0x00000000,
-        0x0000046f,
-/* 0x037c: memx_func_next */
         0x00000001,
         0x00000000,
-        0x00000496,
+        0x00000551,
+/* 0x037c: memx_func_next */
         0x00000002,
+        0x00000000,
+        0x000005db,
+        0x00000003,
         0x00000002,
-        0x000004b7,
-        0x00040003,
+        0x000006a5,
+        0x00040004,
+        0x00000000,
+        0x000006c1,
+        0x00010005,
+        0x00000000,
+        0x000006de,
+        0x00010006,
         0x00000000,
-        0x000004d3,
-        0x00010004,
+        0x00000663,
+/* 0x03b8: memx_func_tail */
+/* 0x03b8: memx_ts_start */
         0x00000000,
-        0x000004f0,
-/* 0x03ac: memx_func_tail */
-/* 0x03ac: memx_data_head */
+/* 0x03bc: memx_ts_end */
         0x00000000,
+/* 0x03c0: memx_data_head */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -757,8 +763,9 @@ uint32_t nvc0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0bac: memx_data_tail */
-/* 0x0bac: i2c_scl_map */
+        0x00000000,
+/* 0x0bc0: memx_data_tail */
+/* 0x0bc0: i2c_scl_map */
         0x00001000,
         0x00004000,
         0x00010000,
@@ -769,7 +776,7 @@ uint32_t nvc0_pwr_data[] = {
         0x01000000,
         0x04000000,
         0x10000000,
-/* 0x0bd4: i2c_sda_map */
+/* 0x0be8: i2c_sda_map */
         0x00002000,
         0x00008000,
         0x00020000,
@@ -780,7 +787,7 @@ uint32_t nvc0_pwr_data[] = {
         0x02000000,
         0x08000000,
         0x20000000,
-/* 0x0bfc: i2c_ctrl */
+/* 0x0c10: i2c_ctrl */
         0x0000e138,
         0x0000e150,
         0x0000e168,
@@ -841,15 +848,10 @@ uint32_t nvc0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
 };
 
 uint32_t nvc0_pwr_code[] = {
-        0x030d0ef5,
+        0x039e0ef5,
 /* 0x0004: rd32 */
         0x07a007f1,
         0xd00604b6,
@@ -885,19 +887,22 @@ uint32_t nvc0_pwr_code[] = {
         0xd4f100dd,
         0x1bf47000,
 /* 0x007f: nsec */
-        0xf000f8f2,
+        0xf900f8f2,
+        0xf080f990,
         0x84b62c87,
         0x0088cf06,
-/* 0x0088: nsec_loop */
+/* 0x008c: nsec_loop */
         0xb62c97f0,
         0x99cf0694,
         0x0298bb00,
         0xf4069eb8,
-        0x00f8f11e,
-/* 0x009c: wait */
+        0x80fcf11e,
+        0x00f890fc,
+/* 0x00a4: wait */
+        0x80f990f9,
         0xb62c87f0,
         0x88cf0684,
-/* 0x00a5: wait_loop */
+/* 0x00b1: wait_loop */
         0x02eeb900,
         0xb90421f4,
         0xadfd02da,
@@ -907,28 +912,29 @@ uint32_t nvc0_pwr_code[] = {
         0x0099cf06,
         0xb80298bb,
         0x1ef4069b,
-/* 0x00c9: wait_done */
-/* 0x00cb: intr_watchdog */
-        0x9800f8df,
+/* 0x00d5: wait_done */
+        0xfc80fcdf,
+/* 0x00db: intr_watchdog */
+        0x9800f890,
         0x96b003e9,
         0x2a0bf400,
         0xbb9a0a98,
         0x1cf4029a,
         0x01d7f00f,
-        0x025421f5,
+        0x02dd21f5,
         0x0ef494bd,
-/* 0x00e9: intr_watchdog_next_time */
+/* 0x00f9: intr_watchdog_next_time */
         0x9b0a9815,
         0xf400a6b0,
         0x9ab8090b,
         0x061cf406,
-/* 0x00f8: intr_watchdog_next_time_set */
-/* 0x00fb: intr_watchdog_next_proc */
+/* 0x0108: intr_watchdog_next_time_set */
+/* 0x010b: intr_watchdog_next_proc */
         0x809b0980,
         0xe0b603e9,
         0x68e6b158,
         0xc61bf402,
-/* 0x010a: intr */
+/* 0x011a: intr */
         0x00f900f8,
         0x80f904bd,
         0xa0f990f9,
@@ -948,13 +954,13 @@ uint32_t nvc0_pwr_code[] = {
         0xf40289c4,
         0x0080230b,
         0x58e7f09b,
-        0x98cb21f4,
+        0x98db21f4,
         0x96b09b09,
         0x110bf400,
         0xb63407f0,
         0x09d00604,
         0x8004bd00,
-/* 0x016e: intr_skip_watchdog */
+/* 0x017e: intr_skip_watchdog */
         0x89e49a09,
         0x0bf40800,
         0x8897f148,
@@ -967,22 +973,22 @@ uint32_t nvc0_pwr_code[] = {
         0x48e7f1c0,
         0x53e3f14f,
         0x00d7f054,
-        0x02b921f5,
+        0x034221f5,
         0x07f1c0fc,
         0x04b604c0,
         0x000cd006,
-/* 0x01ae: intr_subintr_skip_fifo */
+/* 0x01be: intr_subintr_skip_fifo */
         0x07f104bd,
         0x04b60688,
         0x0009d006,
-/* 0x01ba: intr_skip_subintr */
+/* 0x01ca: intr_skip_subintr */
         0x89c404bd,
         0x070bf420,
         0xffbfa4f1,
-/* 0x01c4: intr_skip_pause */
+/* 0x01d4: intr_skip_pause */
         0xf44089c4,
         0xa4f1070b,
-/* 0x01ce: intr_skip_user0 */
+/* 0x01de: intr_skip_user0 */
         0x07f0ffbf,
         0x0604b604,
         0xbd0008d0,
@@ -993,597 +999,733 @@ uint32_t nvc0_pwr_code[] = {
         0x90fca0fc,
         0x00fc80fc,
         0xf80032f4,
-/* 0x01f5: timer */
-        0x1032f401,
-        0xb003f898,
-        0x1cf40086,
-        0x03fe8051,
+/* 0x0205: ticks_from_ns */
+        0xf9c0f901,
+        0xcbd7f1b0,
+        0x00d3f000,
+        0x041321f5,
+        0x03e8ccec,
+        0xf400b4b0,
+        0xeeec120b,
+        0xd7f103e8,
+        0xd3f000cb,
+        0x1321f500,
+/* 0x022d: ticks_from_ns_quit */
+        0x02ceb904,
+        0xc0fcb0fc,
+/* 0x0236: ticks_from_us */
+        0xc0f900f8,
+        0xd7f1b0f9,
+        0xd3f000cb,
+        0x1321f500,
+        0x02ceb904,
+        0xf400b4b0,
+        0xe4bd050b,
+/* 0x0250: ticks_from_us_quit */
+        0xc0fcb0fc,
+/* 0x0256: ticks_to_us */
+        0xd7f100f8,
+        0xd3f000cb,
+        0xecedff00,
+/* 0x0262: timer */
+        0x90f900f8,
+        0x32f480f9,
+        0x03f89810,
+        0xf40086b0,
+        0x84bd651c,
         0xb63807f0,
         0x08d00604,
         0xf004bd00,
-        0x84b60887,
+        0x84b63487,
         0x0088cf06,
-        0xf40284f0,
-        0x87f0261b,
-        0x0684b634,
-        0xb80088cf,
-        0x0bf406e0,
-        0x06e8b809,
-/* 0x0233: timer_reset */
-        0xf01f1ef4,
-        0x04b63407,
-        0x000ed006,
-        0x0e8004bd,
-/* 0x0241: timer_enable */
-        0x0187f09a,
+        0xbb9a0998,
+        0xe9bb0298,
+        0x03fe8000,
+        0xb60887f0,
+        0x88cf0684,
+        0x0284f000,
+        0xf0261bf4,
+        0x84b63487,
+        0x0088cf06,
+        0xf406e0b8,
+        0xe8b8090b,
+        0x111cf406,
+/* 0x02b8: timer_reset */
+        0xb63407f0,
+        0x0ed00604,
+        0x8004bd00,
+/* 0x02c6: timer_enable */
+        0x87f09a0e,
+        0x3807f001,
+        0xd00604b6,
+        0x04bd0008,
+/* 0x02d4: timer_done */
+        0xfc1031f4,
+        0xf890fc80,
+/* 0x02dd: send_proc */
+        0xf980f900,
+        0x05e89890,
+        0xf004e998,
+        0x89b80486,
+        0x2a0bf406,
+        0x940398c4,
+        0x80b60488,
+        0x008ebb18,
+        0x8000fa98,
+        0x8d80008a,
+        0x028c8001,
+        0xb6038b80,
+        0x94f00190,
+        0x04e98007,
+/* 0x0317: send_done */
+        0xfc0231f4,
+        0xf880fc90,
+/* 0x031d: find */
+        0xf080f900,
+        0x31f45887,
+/* 0x0325: find_loop */
+        0x008a9801,
+        0xf406aeb8,
+        0x80b6100b,
+        0x6886b158,
+        0xf01bf402,
+/* 0x033b: find_done */
+        0xb90132f4,
+        0x80fc028e,
+/* 0x0342: send */
+        0x21f500f8,
+        0x01f4031d,
+/* 0x034b: recv */
+        0xf900f897,
+        0x9880f990,
+        0xe99805e8,
+        0x0132f404,
+        0xf40689b8,
+        0x89c43d0b,
+        0x0180b603,
+        0x800784f0,
+        0xea9805e8,
+        0xfef0f902,
+        0xf0f9018f,
+        0x9402efb9,
+        0xe9bb0499,
+        0x18e0b600,
+        0x9803eb98,
+        0xed9802ec,
+        0x00ee9801,
+        0xf0fca5f9,
+        0xf400f8fe,
+        0xf0fc0131,
+/* 0x0398: recv_done */
+        0x90fc80fc,
+/* 0x039e: init */
+        0x17f100f8,
+        0x14b60108,
+        0x0011cf06,
+        0x010911e7,
+        0xfe0814b6,
+        0x17f10014,
+        0x13f000e0,
+        0x1c07f000,
+        0xd00604b6,
+        0x04bd0001,
+        0xf0ff17f0,
+        0x04b61407,
+        0x0001d006,
+        0x17f004bd,
+        0x0015f102,
+        0x1007f008,
+        0xd00604b6,
+        0x04bd0001,
+        0x011a17f1,
+        0xfe0013f0,
+        0x31f40010,
+        0x0117f010,
         0xb63807f0,
-        0x08d00604,
-/* 0x024f: timer_done */
-        0xf404bd00,
-        0x00f81031,
-/* 0x0254: send_proc */
-        0x90f980f9,
-        0x9805e898,
-        0x86f004e9,
-        0x0689b804,
-        0xc42a0bf4,
-        0x88940398,
-        0x1880b604,
-        0x98008ebb,
-        0x8a8000fa,
-        0x018d8000,
-        0x80028c80,
-        0x90b6038b,
-        0x0794f001,
-        0xf404e980,
-/* 0x028e: send_done */
-        0x90fc0231,
-        0x00f880fc,
-/* 0x0294: find */
-        0x87f080f9,
-        0x0131f458,
-/* 0x029c: find_loop */
-        0xb8008a98,
-        0x0bf406ae,
-        0x5880b610,
-        0x026886b1,
-        0xf4f01bf4,
-/* 0x02b2: find_done */
-        0x8eb90132,
-        0xf880fc02,
-/* 0x02b9: send */
-        0x9421f500,
-        0x9701f402,
-/* 0x02c2: recv */
-        0xe89800f8,
-        0x04e99805,
-        0xb80132f4,
-        0x0bf40689,
-        0x0389c43d,
-        0xf00180b6,
-        0xe8800784,
-        0x02ea9805,
-        0x8ffef0f9,
-        0xb9f0f901,
-        0x999402ef,
-        0x00e9bb04,
-        0x9818e0b6,
-        0xec9803eb,
-        0x01ed9802,
-        0xf900ee98,
-        0xfef0fca5,
-        0x31f400f8,
-/* 0x030b: recv_done */
-        0xf8f0fc01,
-/* 0x030d: init */
-        0x0817f100,
-        0x0614b601,
-        0xe70011cf,
-        0xb6010911,
-        0x14fe0814,
-        0xe017f100,
-        0x0013f000,
-        0xb61c07f0,
         0x01d00604,
         0xf004bd00,
-        0x07f0ff17,
-        0x0604b614,
-        0xbd0001d0,
-        0x0217f004,
-        0x080015f1,
-        0xb61007f0,
-        0x01d00604,
-        0xf104bd00,
-        0xf0010a17,
-        0x10fe0013,
-        0x1031f400,
-        0xf00117f0,
-        0x04b63807,
-        0x0001d006,
-        0xf7f004bd,
-/* 0x0371: init_proc */
-        0x01f19858,
-        0xf40016b0,
-        0x15f9fa0b,
-        0xf458f0b6,
-/* 0x0382: host_send */
-        0x17f1f20e,
-        0x14b604b0,
-        0x0011cf06,
-        0x04a027f1,
-        0xcf0624b6,
-        0x12b80022,
-        0x320bf406,
-        0x94071ec4,
-        0xe0b704ee,
-        0xeb980270,
-        0x02ec9803,
-        0x9801ed98,
-        0x21f500ee,
-        0x10b602b9,
-        0x0f1ec401,
-        0x04b007f1,
-        0xd00604b6,
-        0x04bd000e,
-/* 0x03cb: host_send_done */
-        0xf8ba0ef4,
-/* 0x03cd: host_recv */
-        0x4917f100,
-        0x5413f14e,
-        0x06e1b852,
-/* 0x03db: host_recv_wait */
-        0xf1aa0bf4,
-        0xb604cc17,
-        0x11cf0614,
-        0xc827f100,
-        0x0624b604,
-        0xf00022cf,
-        0x12b80816,
-        0xe60bf406,
-        0xb60723c4,
-        0x30b70434,
-        0x3b8002f0,
-        0x023c8003,
-        0x80013d80,
-        0x20b6003e,
-        0x0f24f001,
-        0x04c807f1,
+/* 0x0402: init_proc */
+        0xf19858f7,
+        0x0016b001,
+        0xf9fa0bf4,
+        0x58f0b615,
+/* 0x0413: mulu32_32_64 */
+        0xf9f20ef4,
+        0xf920f910,
+        0x9540f930,
+        0xd29510e1,
+        0xbdc4bd10,
+        0xc0edffb4,
+        0xb9301dff,
+        0x34f10234,
+        0x34b6ffff,
+        0x1045b610,
+        0xbb00c3bb,
+        0xe2ff01b4,
+        0x0234b930,
+        0xffff34f1,
+        0xb61034b6,
+        0xc3bb1045,
+        0x01b4bb00,
+        0xbb3012ff,
+        0x40fc00b3,
+        0x20fc30fc,
+        0x00f810fc,
+/* 0x0464: host_send */
+        0x04b017f1,
+        0xcf0614b6,
+        0x27f10011,
+        0x24b604a0,
+        0x0022cf06,
+        0xf40612b8,
+        0x1ec4320b,
+        0x04ee9407,
+        0x0270e0b7,
+        0x9803eb98,
+        0xed9802ec,
+        0x00ee9801,
+        0x034221f5,
+        0xc40110b6,
+        0x07f10f1e,
+        0x04b604b0,
+        0x000ed006,
+        0x0ef404bd,
+/* 0x04ad: host_send_done */
+/* 0x04af: host_recv */
+        0xf100f8ba,
+        0xf14e4917,
+        0xb8525413,
+        0x0bf406e1,
+/* 0x04bd: host_recv_wait */
+        0xcc17f1aa,
+        0x0614b604,
+        0xf10011cf,
+        0xb604c827,
+        0x22cf0624,
+        0x0816f000,
+        0xf40612b8,
+        0x23c4e60b,
+        0x0434b607,
+        0x02f030b7,
+        0x80033b80,
+        0x3d80023c,
+        0x003e8001,
+        0xf00120b6,
+        0x07f10f24,
+        0x04b604c8,
+        0x0002d006,
+        0x27f004bd,
+        0x0007f040,
         0xd00604b6,
         0x04bd0002,
-        0xf04027f0,
-        0x04b60007,
-        0x0002d006,
-        0x00f804bd,
-/* 0x0430: host_init */
-        0x008017f1,
-        0xf11014b6,
-        0xf1027015,
-        0xb604d007,
-        0x01d00604,
-        0xf104bd00,
-        0xb6008017,
-        0x15f11014,
-        0x07f102f0,
-        0x04b604dc,
-        0x0001d006,
-        0x17f004bd,
-        0xc407f101,
+/* 0x0512: host_init */
+        0x17f100f8,
+        0x14b60080,
+        0x7015f110,
+        0xd007f102,
         0x0604b604,
         0xbd0001d0,
-/* 0x046f: memx_func_enter */
-        0xf000f804,
+        0x8017f104,
+        0x1014b600,
+        0x02f015f1,
+        0x04dc07f1,
+        0xd00604b6,
+        0x04bd0001,
+        0xf10117f0,
+        0xb604c407,
+        0x01d00604,
+        0xf804bd00,
+/* 0x0551: memx_func_enter */
+        0x2067f100,
+        0x5d77f116,
+        0xff73f1f5,
+        0x026eb9ff,
+        0xb90421f4,
+        0x87fd02d8,
+        0xf960f904,
+        0xfcd0fc80,
+        0x3f21f4e0,
+        0xfffe77f1,
+        0xffff73f1,
+        0xf4026eb9,
+        0xd8b90421,
+        0x0487fd02,
+        0x80f960f9,
+        0xe0fcd0fc,
+        0xf13f21f4,
+        0xb926f067,
+        0x21f4026e,
+        0x02d8b904,
+        0xf90487fd,
+        0xfc80f960,
+        0xf4e0fcd0,
+        0x67f03f21,
+        0xe007f104,
+        0x0604b607,
+        0xbd0006d0,
+/* 0x05bd: memx_func_enter_wait */
+        0xc067f104,
+        0x0664b607,
+        0xf00066cf,
+        0x0bf40464,
+        0x2c67f0f3,
+        0xcf0664b6,
+        0x06800066,
+/* 0x05db: memx_func_leave */
+        0xf000f8ee,
+        0x64b62c67,
+        0x0066cf06,
+        0xf0ef0680,
         0x07f10467,
-        0x04b607e0,
+        0x04b607e4,
         0x0006d006,
-/* 0x047e: memx_func_enter_wait */
+/* 0x05f6: memx_func_leave_wait */
         0x67f104bd,
         0x64b607c0,
         0x0066cf06,
         0xf40464f0,
-        0x1698f30b,
+        0x67f1f31b,
+        0x77f126f0,
+        0x73f00001,
+        0x026eb900,
+        0xb90421f4,
+        0x87fd02d8,
+        0xf960f905,
+        0xfcd0fc80,
+        0x3f21f4e0,
+        0x162067f1,
+        0xf4026eb9,
+        0xd8b90421,
+        0x0587fd02,
+        0x80f960f9,
+        0xe0fcd0fc,
+        0xf13f21f4,
+        0xf00aa277,
+        0x6eb90073,
+        0x0421f402,
+        0xfd02d8b9,
+        0x60f90587,
+        0xd0fc80f9,
+        0x21f4e0fc,
+/* 0x0663: memx_func_wait_vblank */
+        0x9800f83f,
+        0x66b00016,
+        0x130bf400,
+        0xf40166b0,
+        0x0ef4060b,
+/* 0x0675: memx_func_wait_vblank_head1 */
+        0x2077f12e,
+        0x070ef400,
+/* 0x067c: memx_func_wait_vblank_head0 */
+        0x000877f1,
+/* 0x0680: memx_func_wait_vblank_0 */
+        0x07c467f1,
+        0xcf0664b6,
+        0x67fd0066,
+        0xf31bf404,
+/* 0x0690: memx_func_wait_vblank_1 */
+        0x07c467f1,
+        0xcf0664b6,
+        0x67fd0066,
+        0xf30bf404,
+/* 0x06a0: memx_func_wait_vblank_fini */
+        0xf80410b6,
+/* 0x06a5: memx_func_wr32 */
+        0x00169800,
+        0xb6011598,
+        0x60f90810,
+        0xd0fc50f9,
+        0x21f4e0fc,
+        0x0242b63f,
+        0xf8e91bf4,
+/* 0x06c1: memx_func_wait */
+        0x2c87f000,
+        0xcf0684b6,
+        0x1e980088,
+        0x011d9800,
+        0x98021c98,
+        0x10b6031b,
+        0xa421f410,
+/* 0x06de: memx_func_delay */
+        0x1e9800f8,
         0x0410b600,
-/* 0x0496: memx_func_leave */
-        0x67f000f8,
-        0xe407f104,
+        0xf87f21f4,
+/* 0x06e9: memx_exec */
+        0xf9e0f900,
+        0x02c1b9d0,
+/* 0x06f3: memx_exec_next */
+        0x9802b2b9,
+        0x10b60013,
+        0xf034e704,
+        0xe033e701,
+        0x0132b601,
+        0x980c30f0,
+        0x55f9de35,
+        0xf40612b8,
+        0x0b98e41e,
+        0xef0c98ee,
+        0xf102cbbb,
+        0xb607c4b7,
+        0xbbcf06b4,
+        0xfcd0fc00,
+        0x4221f5e0,
+/* 0x072f: memx_info */
+        0xf100f803,
+        0xf103c0c7,
+        0xf50800b7,
+        0xf8034221,
+/* 0x073d: memx_recv */
+        0x01d6b000,
+        0xb0a90bf4,
+        0x0bf400d6,
+/* 0x074b: memx_init */
+        0xf800f8e9,
+/* 0x074d: perf_recv */
+/* 0x074f: perf_init */
+        0xf800f800,
+/* 0x0751: i2c_drive_scl */
+        0x0036b000,
+        0xf1110bf4,
+        0xb607e007,
+        0x01d00604,
+        0xf804bd00,
+/* 0x0765: i2c_drive_scl_lo */
+        0xe407f100,
         0x0604b607,
-        0xbd0006d0,
-/* 0x04a5: memx_func_leave_wait */
-        0xc067f104,
-        0x0664b607,
-        0xf00066cf,
-        0x1bf40464,
-/* 0x04b7: memx_func_wr32 */
-        0x9800f8f3,
-        0x15980016,
-        0x0810b601,
-        0x50f960f9,
-        0xe0fcd0fc,
-        0xb63f21f4,
-        0x1bf40242,
-/* 0x04d3: memx_func_wait */
-        0xf000f8e9,
-        0x84b62c87,
-        0x0088cf06,
-        0x98001e98,
-        0x1c98011d,
-        0x031b9802,
-        0xf41010b6,
-        0x00f89c21,
-/* 0x04f0: memx_func_delay */
-        0xb6001e98,
-        0x21f40410,
-/* 0x04fb: memx_exec */
-        0xf900f87f,
-        0xb9d0f9e0,
-        0xb2b902c1,
-/* 0x0505: memx_exec_next */
-        0x00139802,
-        0x950410b6,
-        0x30f01034,
-        0xde35980c,
-        0x12b855f9,
-        0xec1ef406,
-        0xe0fcd0fc,
-        0x02b921f5,
-/* 0x0526: memx_info */
-        0xc7f100f8,
-        0xb7f103ac,
-        0x21f50800,
-        0x00f802b9,
-/* 0x0534: memx_recv */
-        0xf401d6b0,
-        0xd6b0c40b,
-        0xe90bf400,
-/* 0x0542: memx_init */
-        0x00f800f8,
-/* 0x0544: perf_recv */
-/* 0x0546: perf_init */
-        0x00f800f8,
-/* 0x0548: i2c_drive_scl */
-        0xf40036b0,
-        0x07f1110b,
-        0x04b607e0,
-        0x0001d006,
-        0x00f804bd,
-/* 0x055c: i2c_drive_scl_lo */
-        0x07e407f1,
-        0xd00604b6,
-        0x04bd0001,
-/* 0x056a: i2c_drive_sda */
-        0x36b000f8,
-        0x110bf400,
-        0x07e007f1,
-        0xd00604b6,
-        0x04bd0002,
-/* 0x057e: i2c_drive_sda_lo */
-        0x07f100f8,
-        0x04b607e4,
-        0x0002d006,
-        0x00f804bd,
-/* 0x058c: i2c_sense_scl */
-        0xf10132f4,
-        0xb607c437,
-        0x33cf0634,
-        0x0431fd00,
-        0xf4060bf4,
-/* 0x05a2: i2c_sense_scl_done */
-        0x00f80131,
-/* 0x05a4: i2c_sense_sda */
-        0xf10132f4,
-        0xb607c437,
-        0x33cf0634,
-        0x0432fd00,
-        0xf4060bf4,
-/* 0x05ba: i2c_sense_sda_done */
-        0x00f80131,
-/* 0x05bc: i2c_raise_scl */
-        0x47f140f9,
-        0x37f00898,
-        0x4821f501,
-/* 0x05c9: i2c_raise_scl_wait */
-        0xe8e7f105,
-        0x7f21f403,
-        0x058c21f5,
-        0xb60901f4,
-        0x1bf40142,
-/* 0x05dd: i2c_raise_scl_done */
-        0xf840fcef,
-/* 0x05e1: i2c_start */
-        0x8c21f500,
-        0x0d11f405,
-        0x05a421f5,
-        0xf40611f4,
-/* 0x05f2: i2c_start_rep */
-        0x37f0300e,
-        0x4821f500,
-        0x0137f005,
-        0x056a21f5,
-        0xb60076bb,
-        0x50f90465,
-        0xbb046594,
-        0x50bd0256,
-        0xfc0475fd,
-        0xbc21f550,
-        0x0464b605,
-/* 0x061f: i2c_start_send */
-        0xf01f11f4,
+        0xbd0001d0,
+/* 0x0773: i2c_drive_sda */
+        0xb000f804,
+        0x0bf40036,
+        0xe007f111,
+        0x0604b607,
+        0xbd0002d0,
+/* 0x0787: i2c_drive_sda_lo */
+        0xf100f804,
+        0xb607e407,
+        0x02d00604,
+        0xf804bd00,
+/* 0x0795: i2c_sense_scl */
+        0x0132f400,
+        0x07c437f1,
+        0xcf0634b6,
+        0x31fd0033,
+        0x060bf404,
+/* 0x07ab: i2c_sense_scl_done */
+        0xf80131f4,
+/* 0x07ad: i2c_sense_sda */
+        0x0132f400,
+        0x07c437f1,
+        0xcf0634b6,
+        0x32fd0033,
+        0x060bf404,
+/* 0x07c3: i2c_sense_sda_done */
+        0xf80131f4,
+/* 0x07c5: i2c_raise_scl */
+        0xf140f900,
+        0xf0089847,
+        0x21f50137,
+/* 0x07d2: i2c_raise_scl_wait */
+        0xe7f10751,
+        0x21f403e8,
+        0x9521f57f,
+        0x0901f407,
+        0xf40142b6,
+/* 0x07e6: i2c_raise_scl_done */
+        0x40fcef1b,
+/* 0x07ea: i2c_start */
+        0x21f500f8,
+        0x11f40795,
+        0xad21f50d,
+        0x0611f407,
+/* 0x07fb: i2c_start_rep */
+        0xf0300ef4,
         0x21f50037,
-        0xe7f1056a,
-        0x21f41388,
-        0x0037f07f,
-        0x054821f5,
-        0x1388e7f1,
-/* 0x063b: i2c_start_out */
-        0xf87f21f4,
-/* 0x063d: i2c_stop */
-        0x0037f000,
-        0x054821f5,
+        0x37f00751,
+        0x7321f501,
+        0x0076bb07,
+        0xf90465b6,
+        0x04659450,
+        0xbd0256bb,
+        0x0475fd50,
+        0x21f550fc,
+        0x64b607c5,
+        0x1f11f404,
+/* 0x0828: i2c_start_send */
         0xf50037f0,
-        0xf1056a21,
-        0xf403e8e7,
+        0xf1077321,
+        0xf41388e7,
         0x37f07f21,
-        0x4821f501,
-        0x88e7f105,
+        0x5121f500,
+        0x88e7f107,
         0x7f21f413,
-        0xf50137f0,
-        0xf1056a21,
-        0xf41388e7,
-        0x00f87f21,
-/* 0x0670: i2c_bitw */
-        0x056a21f5,
+/* 0x0844: i2c_start_out */
+/* 0x0846: i2c_stop */
+        0x37f000f8,
+        0x5121f500,
+        0x0037f007,
+        0x077321f5,
         0x03e8e7f1,
-        0xbb7f21f4,
-        0x65b60076,
-        0x9450f904,
-        0x56bb0465,
-        0xfd50bd02,
-        0x50fc0475,
-        0x05bc21f5,
-        0xf40464b6,
-        0xe7f11811,
+        0xf07f21f4,
+        0x21f50137,
+        0xe7f10751,
         0x21f41388,
-        0x0037f07f,
-        0x054821f5,
+        0x0137f07f,
+        0x077321f5,
         0x1388e7f1,
-/* 0x06af: i2c_bitw_out */
         0xf87f21f4,
-/* 0x06b1: i2c_bitr */
-        0x0137f000,
-        0x056a21f5,
-        0x03e8e7f1,
-        0xbb7f21f4,
-        0x65b60076,
-        0x9450f904,
-        0x56bb0465,
-        0xfd50bd02,
-        0x50fc0475,
-        0x05bc21f5,
-        0xf40464b6,
-        0x21f51b11,
-        0x37f005a4,
-        0x4821f500,
-        0x88e7f105,
+/* 0x0879: i2c_bitw */
+        0x7321f500,
+        0xe8e7f107,
+        0x7f21f403,
+        0xb60076bb,
+        0x50f90465,
+        0xbb046594,
+        0x50bd0256,
+        0xfc0475fd,
+        0xc521f550,
+        0x0464b607,
+        0xf11811f4,
+        0xf41388e7,
+        0x37f07f21,
+        0x5121f500,
+        0x88e7f107,
         0x7f21f413,
-        0xf4013cf0,
-/* 0x06f6: i2c_bitr_done */
-        0x00f80131,
-/* 0x06f8: i2c_get_byte */
-        0xf00057f0,
-/* 0x06fe: i2c_get_byte_next */
-        0x54b60847,
+/* 0x08b8: i2c_bitw_out */
+/* 0x08ba: i2c_bitr */
+        0x37f000f8,
+        0x7321f501,
+        0xe8e7f107,
+        0x7f21f403,
+        0xb60076bb,
+        0x50f90465,
+        0xbb046594,
+        0x50bd0256,
+        0xfc0475fd,
+        0xc521f550,
+        0x0464b607,
+        0xf51b11f4,
+        0xf007ad21,
+        0x21f50037,
+        0xe7f10751,
+        0x21f41388,
+        0x013cf07f,
+/* 0x08ff: i2c_bitr_done */
+        0xf80131f4,
+/* 0x0901: i2c_get_byte */
+        0x0057f000,
+/* 0x0907: i2c_get_byte_next */
+        0xb60847f0,
+        0x76bb0154,
+        0x0465b600,
+        0x659450f9,
+        0x0256bb04,
+        0x75fd50bd,
+        0xf550fc04,
+        0xb608ba21,
+        0x11f40464,
+        0x0553fd2b,
+        0xf40142b6,
+        0x37f0d81b,
         0x0076bb01,
         0xf90465b6,
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
         0x21f550fc,
-        0x64b606b1,
-        0x2b11f404,
-        0xb60553fd,
-        0x1bf40142,
-        0x0137f0d8,
-        0xb60076bb,
-        0x50f90465,
-        0xbb046594,
-        0x50bd0256,
-        0xfc0475fd,
-        0x7021f550,
-        0x0464b606,
-/* 0x0748: i2c_get_byte_done */
-/* 0x074a: i2c_put_byte */
-        0x47f000f8,
-/* 0x074d: i2c_put_byte_next */
-        0x0142b608,
-        0xbb3854ff,
-        0x65b60076,
-        0x9450f904,
-        0x56bb0465,
-        0xfd50bd02,
-        0x50fc0475,
-        0x067021f5,
-        0xf40464b6,
-        0x46b03411,
-        0xd81bf400,
+        0x64b60879,
+/* 0x0951: i2c_get_byte_done */
+/* 0x0953: i2c_put_byte */
+        0xf000f804,
+/* 0x0956: i2c_put_byte_next */
+        0x42b60847,
+        0x3854ff01,
         0xb60076bb,
         0x50f90465,
         0xbb046594,
         0x50bd0256,
         0xfc0475fd,
-        0xb121f550,
-        0x0464b606,
-        0xbb0f11f4,
-        0x36b00076,
-        0x061bf401,
-/* 0x07a3: i2c_put_byte_done */
-        0xf80132f4,
-/* 0x07a5: i2c_addr */
-        0x0076bb00,
+        0x7921f550,
+        0x0464b608,
+        0xb03411f4,
+        0x1bf40046,
+        0x0076bbd8,
         0xf90465b6,
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
         0x21f550fc,
-        0x64b605e1,
-        0x2911f404,
-        0x012ec3e7,
-        0xfd0134b6,
-        0x76bb0553,
+        0x64b608ba,
+        0x0f11f404,
+        0xb00076bb,
+        0x1bf40136,
+        0x0132f406,
+/* 0x09ac: i2c_put_byte_done */
+/* 0x09ae: i2c_addr */
+        0x76bb00f8,
         0x0465b600,
         0x659450f9,
         0x0256bb04,
         0x75fd50bd,
         0xf550fc04,
-        0xb6074a21,
-/* 0x07ea: i2c_addr_done */
-        0x00f80464,
-/* 0x07ec: i2c_acquire_addr */
-        0xb6f8cec7,
-        0xe0b702e4,
-        0xee980bfc,
-/* 0x07fb: i2c_acquire */
-        0xf500f800,
-        0xf407ec21,
-        0xd9f00421,
-        0x3f21f403,
-/* 0x080a: i2c_release */
-        0x21f500f8,
-        0x21f407ec,
-        0x03daf004,
-        0xf83f21f4,
-/* 0x0819: i2c_recv */
-        0x0132f400,
-        0xb6f8c1c7,
-        0x16b00214,
-        0x3a1ff528,
-        0xd413a001,
-        0x0032980b,
-        0x0bac13a0,
-        0xf4003198,
-        0xd0f90231,
-        0xd0f9e0f9,
-        0x000067f1,
-        0x100063f1,
-        0xbb016792,
+        0xb607ea21,
+        0x11f40464,
+        0x2ec3e729,
+        0x0134b601,
+        0xbb0553fd,
         0x65b60076,
         0x9450f904,
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x07fb21f5,
-        0xfc0464b6,
-        0x00d6b0d0,
-        0x00b31bf5,
-        0xbb0057f0,
+        0x095321f5,
+/* 0x09f3: i2c_addr_done */
+        0xf80464b6,
+/* 0x09f5: i2c_acquire_addr */
+        0xf8cec700,
+        0xb702e4b6,
+        0x980c10e0,
+        0x00f800ee,
+/* 0x0a04: i2c_acquire */
+        0x09f521f5,
+        0xf00421f4,
+        0x21f403d9,
+/* 0x0a13: i2c_release */
+        0xf500f83f,
+        0xf409f521,
+        0xdaf00421,
+        0x3f21f403,
+/* 0x0a22: i2c_recv */
+        0x32f400f8,
+        0xf8c1c701,
+        0xb00214b6,
+        0x1ff52816,
+        0x13a0013a,
+        0x32980be8,
+        0xc013a000,
+        0x0031980b,
+        0xf90231f4,
+        0xf9e0f9d0,
+        0x0067f1d0,
+        0x0063f100,
+        0x01679210,
+        0xb60076bb,
+        0x50f90465,
+        0xbb046594,
+        0x50bd0256,
+        0xfc0475fd,
+        0x0421f550,
+        0x0464b60a,
+        0xd6b0d0fc,
+        0xb31bf500,
+        0x0057f000,
+        0xb60076bb,
+        0x50f90465,
+        0xbb046594,
+        0x50bd0256,
+        0xfc0475fd,
+        0xae21f550,
+        0x0464b609,
+        0x00d011f5,
+        0xbbe0c5c7,
         0x65b60076,
         0x9450f904,
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x07a521f5,
+        0x095321f5,
         0xf50464b6,
-        0xc700d011,
-        0x76bbe0c5,
+        0xf000ad11,
+        0x76bb0157,
         0x0465b600,
         0x659450f9,
         0x0256bb04,
         0x75fd50bd,
         0xf550fc04,
-        0xb6074a21,
+        0xb609ae21,
         0x11f50464,
-        0x57f000ad,
-        0x0076bb01,
-        0xf90465b6,
-        0x04659450,
-        0xbd0256bb,
-        0x0475fd50,
-        0x21f550fc,
-        0x64b607a5,
-        0x8a11f504,
-        0x0076bb00,
-        0xf90465b6,
-        0x04659450,
-        0xbd0256bb,
-        0x0475fd50,
-        0x21f550fc,
-        0x64b606f8,
-        0x6a11f404,
-        0xbbe05bcb,
-        0x65b60076,
-        0x9450f904,
-        0x56bb0465,
-        0xfd50bd02,
-        0x50fc0475,
-        0x063d21f5,
-        0xb90464b6,
-        0x74bd025b,
-/* 0x091f: i2c_recv_not_rd08 */
-        0xb0430ef4,
-        0x1bf401d6,
-        0x0057f03d,
-        0x07a521f5,
-        0xc73311f4,
-        0x21f5e0c5,
-        0x11f4074a,
-        0x0057f029,
-        0x07a521f5,
-        0xc71f11f4,
-        0x21f5e0b5,
-        0x11f4074a,
-        0x3d21f515,
-        0xc774bd06,
-        0x1bf408c5,
-        0x0232f409,
-/* 0x095f: i2c_recv_not_wr08 */
-/* 0x095f: i2c_recv_done */
-        0xc7030ef4,
-        0x21f5f8ce,
-        0xe0fc080a,
-        0x12f4d0fc,
-        0x027cb90a,
-        0x02b921f5,
-/* 0x0974: i2c_recv_exit */
-/* 0x0976: i2c_init */
+        0x76bb008a,
+        0x0465b600,
+        0x659450f9,
+        0x0256bb04,
+        0x75fd50bd,
+        0xf550fc04,
+        0xb6090121,
+        0x11f40464,
+        0xe05bcb6a,
+        0xb60076bb,
+        0x50f90465,
+        0xbb046594,
+        0x50bd0256,
+        0xfc0475fd,
+        0x4621f550,
+        0x0464b608,
+        0xbd025bb9,
+        0x430ef474,
+/* 0x0b28: i2c_recv_not_rd08 */
+        0xf401d6b0,
+        0x57f03d1b,
+        0xae21f500,
+        0x3311f409,
+        0xf5e0c5c7,
+        0xf4095321,
+        0x57f02911,
+        0xae21f500,
+        0x1f11f409,
+        0xf5e0b5c7,
+        0xf4095321,
+        0x21f51511,
+        0x74bd0846,
+        0xf408c5c7,
+        0x32f4091b,
+        0x030ef402,
+/* 0x0b68: i2c_recv_not_wr08 */
+/* 0x0b68: i2c_recv_done */
+        0xf5f8cec7,
+        0xfc0a1321,
+        0xf4d0fce0,
+        0x7cb90a12,
+        0x4221f502,
+/* 0x0b7d: i2c_recv_exit */
+/* 0x0b7f: i2c_init */
+        0xf800f803,
+/* 0x0b81: test_recv */
+        0xd817f100,
+        0x0614b605,
+        0xb60011cf,
+        0x07f10110,
+        0x04b605d8,
+        0x0001d006,
+        0xe7f104bd,
+        0xe3f1d900,
+        0x21f5134f,
+        0x00f80262,
+/* 0x0ba8: test_init */
+        0x0800e7f1,
+        0x026221f5,
+/* 0x0bb2: idle_recv */
         0x00f800f8,
-/* 0x0978: test_recv */
-        0x05d817f1,
-        0xcf0614b6,
-        0x10b60011,
-        0xd807f101,
-        0x0604b605,
-        0xbd0001d0,
-        0x00e7f104,
-        0x4fe3f1d9,
-        0xf521f513,
-/* 0x099f: test_init */
-        0xf100f801,
-        0xf50800e7,
-        0xf801f521,
-/* 0x09a9: idle_recv */
-/* 0x09ab: idle */
-        0xf400f800,
-        0x17f10031,
-        0x14b605d4,
-        0x0011cf06,
-        0xf10110b6,
-        0xb605d407,
-        0x01d00604,
-/* 0x09c7: idle_loop */
-        0xf004bd00,
-        0x32f45817,
-/* 0x09cd: idle_proc */
-/* 0x09cd: idle_proc_exec */
-        0xb910f902,
-        0x21f5021e,
-        0x10fc02c2,
-        0xf40911f4,
-        0x0ef40231,
-/* 0x09e1: idle_proc_next */
-        0x5810b6ef,
-        0xf4061fb8,
-        0x02f4e61b,
-        0x0028f4dd,
-        0x00bb0ef4,
-        0x00000000,
-        0x00000000,
+/* 0x0bb4: idle */
+        0xf10031f4,
+        0xb605d417,
+        0x11cf0614,
+        0x0110b600,
+        0x05d407f1,
+        0xd00604b6,
+        0x04bd0001,
+/* 0x0bd0: idle_loop */
+        0xf45817f0,
+/* 0x0bd6: idle_proc */
+/* 0x0bd6: idle_proc_exec */
+        0x10f90232,
+        0xf5021eb9,
+        0xfc034b21,
+        0x0911f410,
+        0xf40231f4,
+/* 0x0bea: idle_proc_next */
+        0x10b6ef0e,
+        0x061fb858,
+        0xf4e61bf4,
+        0x28f4dd02,
+        0xbb0ef400,
         0x00000000,
 };
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
index 8a89dfe41ce1..b85443261569 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
@@ -23,6 +23,7 @@
  */
 
 #define NVKM_PPWR_CHIPSET GF119
+#define HW_TICKS_PER_US 324
 
 //#define NVKM_FALCON_PC24
 #define NVKM_FALCON_UNSHIFTED_IO
@@ -34,6 +35,7 @@
 .section #nvd0_pwr_data
 #define INCLUDE_PROC
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
@@ -44,6 +46,7 @@
 
 #define INCLUDE_DATA
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
@@ -56,6 +59,7 @@
 .section #nvd0_pwr_code
 #define INCLUDE_CODE
 #include "kernel.fuc"
+#include "arith.fuc"
 #include "host.fuc"
 #include "memx.fuc"
 #include "perf.fuc"
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
index 8d369b3faaba..12d86f72ad10 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
@@ -24,8 +24,8 @@ uint32_t nvd0_pwr_data[] = {
         0x00000000,
 /* 0x0058: proc_list_head */
         0x54534f48,
-        0x000003be,
-        0x00000367,
+        0x0000049d,
+        0x00000446,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -46,8 +46,8 @@ uint32_t nvd0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x584d454d,
-        0x000004b8,
-        0x000004aa,
+        0x00000678,
+        0x0000066a,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -68,8 +68,8 @@ uint32_t nvd0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x46524550,
-        0x000004bc,
-        0x000004ba,
+        0x0000067c,
+        0x0000067a,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -90,8 +90,8 @@ uint32_t nvd0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x5f433249,
-        0x000008d7,
-        0x0000077a,
+        0x00000a97,
+        0x0000093a,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -112,8 +112,8 @@ uint32_t nvd0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x54534554,
-        0x000008fa,
-        0x000008d9,
+        0x00000aba,
+        0x00000a99,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -134,8 +134,8 @@ uint32_t nvd0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x454c4449,
-        0x00000906,
-        0x00000904,
+        0x00000ac6,
+        0x00000ac4,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -227,24 +227,31 @@ uint32_t nvd0_pwr_data[] = {
         0x00000000,
         0x00000000,
 /* 0x0370: memx_func_head */
-        0x00010000,
-        0x00000000,
-        0x000003f4,
-/* 0x037c: memx_func_next */
         0x00000001,
         0x00000000,
-        0x00000415,
+        0x000004d3,
+/* 0x037c: memx_func_next */
         0x00000002,
+        0x00000000,
+        0x00000554,
+        0x00000003,
         0x00000002,
-        0x00000430,
-        0x00040003,
+        0x000005d8,
+        0x00040004,
+        0x00000000,
+        0x000005f4,
+        0x00010005,
+        0x00000000,
+        0x0000060e,
+        0x00010006,
+        0x00000000,
+        0x000005d3,
+/* 0x03b8: memx_func_tail */
+/* 0x03b8: memx_ts_start */
         0x00000000,
-        0x0000044c,
-        0x00010004,
+/* 0x03bc: memx_ts_end */
         0x00000000,
-        0x00000466,
-/* 0x03ac: memx_func_tail */
-/* 0x03ac: memx_data_head */
+/* 0x03c0: memx_data_head */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -757,8 +764,8 @@ uint32_t nvd0_pwr_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0bac: memx_data_tail */
-/* 0x0bac: i2c_scl_map */
+/* 0x0bc0: memx_data_tail */
+/* 0x0bc0: i2c_scl_map */
         0x00000400,
         0x00000800,
         0x00001000,
@@ -769,7 +776,7 @@ uint32_t nvd0_pwr_data[] = {
         0x00020000,
         0x00040000,
         0x00080000,
-/* 0x0bd4: i2c_sda_map */
+/* 0x0be8: i2c_sda_map */
         0x00100000,
         0x00200000,
         0x00400000,
@@ -781,10 +788,69 @@ uint32_t nvd0_pwr_data[] = {
         0x10000000,
         0x20000000,
         0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
 };
 
 uint32_t nvd0_pwr_code[] = {
-        0x02bf0ef5,
+        0x034d0ef5,
 /* 0x0004: rd32 */
         0x07a007f1,
         0xbd000ed0,
@@ -814,17 +880,20 @@ uint32_t nvd0_pwr_code[] = {
         0xd4f100dd,
         0x1bf47000,
 /* 0x0067: nsec */
-        0xf000f8f5,
+        0xf900f8f5,
+        0xf080f990,
         0x88cf2c87,
-/* 0x006d: nsec_loop */
+/* 0x0071: nsec_loop */
         0x2c97f000,
         0xbb0099cf,
         0x9eb80298,
         0xf41ef406,
-/* 0x007e: wait */
-        0x87f000f8,
+        0x90fc80fc,
+/* 0x0086: wait */
+        0x90f900f8,
+        0x87f080f9,
         0x0088cf2c,
-/* 0x0084: wait_loop */
+/* 0x0090: wait_loop */
         0xf402eeb9,
         0xdab90421,
         0x04adfd02,
@@ -833,28 +902,29 @@ uint32_t nvd0_pwr_code[] = {
         0x0099cf2c,
         0xb80298bb,
         0x1ef4069b,
-/* 0x00a5: wait_done */
-/* 0x00a7: intr_watchdog */
-        0x9800f8e2,
+/* 0x00b1: wait_done */
+        0xfc80fce2,
+/* 0x00b7: intr_watchdog */
+        0x9800f890,
         0x96b003e9,
         0x2a0bf400,
         0xbb9a0a98,
         0x1cf4029a,
         0x01d7f00f,
-        0x020621f5,
+        0x028c21f5,
         0x0ef494bd,
-/* 0x00c5: intr_watchdog_next_time */
+/* 0x00d5: intr_watchdog_next_time */
         0x9b0a9815,
         0xf400a6b0,
         0x9ab8090b,
         0x061cf406,
-/* 0x00d4: intr_watchdog_next_time_set */
-/* 0x00d7: intr_watchdog_next_proc */
+/* 0x00e4: intr_watchdog_next_time_set */
+/* 0x00e7: intr_watchdog_next_proc */
         0x809b0980,
         0xe0b603e9,
         0x68e6b158,
         0xc61bf402,
-/* 0x00e6: intr */
+/* 0x00f6: intr */
         0x00f900f8,
         0x80f904bd,
         0xa0f990f9,
@@ -872,12 +942,12 @@ uint32_t nvd0_pwr_code[] = {
         0x0bf40289,
         0x9b008020,
         0xf458e7f0,
-        0x0998a721,
+        0x0998b721,
         0x0096b09b,
         0xf00e0bf4,
         0x09d03407,
         0x8004bd00,
-/* 0x013e: intr_skip_watchdog */
+/* 0x014e: intr_skip_watchdog */
         0x89e49a09,
         0x0bf40800,
         0x8897f13c,
@@ -889,20 +959,20 @@ uint32_t nvd0_pwr_code[] = {
         0xf14f48e7,
         0xf05453e3,
         0x21f500d7,
-        0xc0fc026b,
+        0xc0fc02f1,
         0x04c007f1,
         0xbd000cd0,
-/* 0x0175: intr_subintr_skip_fifo */
+/* 0x0185: intr_subintr_skip_fifo */
         0x8807f104,
         0x0009d006,
-/* 0x017e: intr_skip_subintr */
+/* 0x018e: intr_skip_subintr */
         0x89c404bd,
         0x070bf420,
         0xffbfa4f1,
-/* 0x0188: intr_skip_pause */
+/* 0x0198: intr_skip_pause */
         0xf44089c4,
         0xa4f1070b,
-/* 0x0192: intr_skip_user0 */
+/* 0x01a2: intr_skip_user0 */
         0x07f0ffbf,
         0x0008d004,
         0x80fc04bd,
@@ -912,189 +982,298 @@ uint32_t nvd0_pwr_code[] = {
         0xfca0fcb0,
         0xfc80fc90,
         0x0032f400,
-/* 0x01b6: timer */
-        0x32f401f8,
-        0x03f89810,
-        0xf40086b0,
-        0xfe80421c,
-        0x3807f003,
+/* 0x01c6: ticks_from_ns */
+        0xc0f901f8,
+        0xd7f1b0f9,
+        0xd3f00144,
+        0xb321f500,
+        0xe8ccec03,
+        0x00b4b003,
+        0xec120bf4,
+        0xf103e8ee,
+        0xf00144d7,
+        0x21f500d3,
+/* 0x01ee: ticks_from_ns_quit */
+        0xceb903b3,
+        0xfcb0fc02,
+/* 0x01f7: ticks_from_us */
+        0xf900f8c0,
+        0xf1b0f9c0,
+        0xf00144d7,
+        0x21f500d3,
+        0xceb903b3,
+        0x00b4b002,
+        0xbd050bf4,
+/* 0x0211: ticks_from_us_quit */
+        0xfcb0fce4,
+/* 0x0217: ticks_to_us */
+        0xf100f8c0,
+        0xf00144d7,
+        0xedff00d3,
+/* 0x0223: timer */
+        0xf900f8ec,
+        0xf480f990,
+        0xf8981032,
+        0x0086b003,
+        0xbd531cf4,
+        0x3807f084,
         0xbd0008d0,
-        0x0887f004,
-        0xf00088cf,
-        0x1bf40284,
-        0x3487f020,
-        0xb80088cf,
-        0x0bf406e0,
-        0x06e8b809,
-/* 0x01eb: timer_reset */
-        0xf0191ef4,
-        0x0ed03407,
-        0x8004bd00,
-/* 0x01f6: timer_enable */
-        0x87f09a0e,
-        0x3807f001,
-        0xbd0008d0,
-/* 0x0201: timer_done */
-        0x1031f404,
-/* 0x0206: send_proc */
-        0x80f900f8,
-        0xe89890f9,
+        0x3487f004,
+        0x980088cf,
+        0x98bb9a09,
+        0x00e9bb02,
+        0xf003fe80,
+        0x88cf0887,
+        0x0284f000,
+        0xf0201bf4,
+        0x88cf3487,
+        0x06e0b800,
+        0xb8090bf4,
+        0x1cf406e8,
+/* 0x026d: timer_reset */
+        0x3407f00e,
+        0xbd000ed0,
+        0x9a0e8004,
+/* 0x0278: timer_enable */
+        0xf00187f0,
+        0x08d03807,
+/* 0x0283: timer_done */
+        0xf404bd00,
+        0x80fc1031,
+        0x00f890fc,
+/* 0x028c: send_proc */
+        0x90f980f9,
+        0x9805e898,
+        0x86f004e9,
+        0x0689b804,
+        0xc42a0bf4,
+        0x88940398,
+        0x1880b604,
+        0x98008ebb,
+        0x8a8000fa,
+        0x018d8000,
+        0x80028c80,
+        0x90b6038b,
+        0x0794f001,
+        0xf404e980,
+/* 0x02c6: send_done */
+        0x90fc0231,
+        0x00f880fc,
+/* 0x02cc: find */
+        0x87f080f9,
+        0x0131f458,
+/* 0x02d4: find_loop */
+        0xb8008a98,
+        0x0bf406ae,
+        0x5880b610,
+        0x026886b1,
+        0xf4f01bf4,
+/* 0x02ea: find_done */
+        0x8eb90132,
+        0xf880fc02,
+/* 0x02f1: send */
+        0xcc21f500,
+        0x9701f402,
+/* 0x02fa: recv */
+        0x90f900f8,
+        0xe89880f9,
         0x04e99805,
-        0xb80486f0,
+        0xb80132f4,
         0x0bf40689,
-        0x0398c42a,
-        0xb6048894,
-        0x8ebb1880,
-        0x00fa9800,
-        0x80008a80,
-        0x8c80018d,
-        0x038b8002,
-        0xf00190b6,
-        0xe9800794,
-        0x0231f404,
-/* 0x0240: send_done */
-        0x80fc90fc,
-/* 0x0246: find */
-        0x80f900f8,
-        0xf45887f0,
-/* 0x024e: find_loop */
-        0x8a980131,
-        0x06aeb800,
-        0xb6100bf4,
-        0x86b15880,
-        0x1bf40268,
-        0x0132f4f0,
-/* 0x0264: find_done */
-        0xfc028eb9,
-/* 0x026b: send */
-        0xf500f880,
-        0xf4024621,
-        0x00f89701,
-/* 0x0274: recv */
-        0x9805e898,
-        0x32f404e9,
-        0x0689b801,
-        0xc43d0bf4,
-        0x80b60389,
-        0x0784f001,
-        0x9805e880,
-        0xf0f902ea,
-        0xf9018ffe,
-        0x02efb9f0,
-        0xbb049994,
-        0xe0b600e9,
-        0x03eb9818,
-        0x9802ec98,
-        0xee9801ed,
-        0xfca5f900,
-        0x00f8fef0,
-        0xfc0131f4,
-/* 0x02bd: recv_done */
-/* 0x02bf: init */
-        0xf100f8f0,
-        0xcf010817,
-        0x11e70011,
-        0x14b60109,
-        0x0014fe08,
-        0x00e017f1,
-        0xf00013f0,
-        0x01d01c07,
-        0xf004bd00,
-        0x07f0ff17,
-        0x0001d014,
-        0x17f004bd,
-        0x0015f102,
-        0x1007f008,
-        0xbd0001d0,
-        0xe617f104,
-        0x0013f000,
-        0xf40010fe,
-        0x17f01031,
-        0x3807f001,
-        0xbd0001d0,
-        0x58f7f004,
-/* 0x0314: init_proc */
-        0xb001f198,
-        0x0bf40016,
-        0xb615f9fa,
-        0x0ef458f0,
-/* 0x0325: host_send */
-        0xb017f1f2,
-        0x0011cf04,
-        0x04a027f1,
-        0xb80022cf,
-        0x0bf40612,
-        0x071ec42f,
-        0xb704ee94,
-        0x980270e0,
+        0x0389c43d,
+        0xf00180b6,
+        0xe8800784,
+        0x02ea9805,
+        0x8ffef0f9,
+        0xb9f0f901,
+        0x999402ef,
+        0x00e9bb04,
+        0x9818e0b6,
         0xec9803eb,
         0x01ed9802,
-        0xf500ee98,
-        0xb6026b21,
-        0x1ec40110,
-        0xb007f10f,
-        0x000ed004,
-        0x0ef404bd,
-/* 0x0365: host_send_done */
-/* 0x0367: host_recv */
-        0xf100f8c3,
-        0xf14e4917,
-        0xb8525413,
-        0x0bf406e1,
-/* 0x0375: host_recv_wait */
-        0xcc17f1b3,
-        0x0011cf04,
-        0x04c827f1,
-        0xf00022cf,
-        0x12b80816,
-        0xec0bf406,
-        0xb60723c4,
-        0x30b70434,
-        0x3b8002f0,
-        0x023c8003,
-        0x80013d80,
-        0x20b6003e,
-        0x0f24f001,
-        0x04c807f1,
-        0xbd0002d0,
-        0x4027f004,
-        0xd00007f0,
-        0x04bd0002,
-/* 0x03be: host_init */
+        0xf900ee98,
+        0xfef0fca5,
+        0x31f400f8,
+/* 0x0347: recv_done */
+        0xfcf0fc01,
+        0xf890fc80,
+/* 0x034d: init */
+        0x0817f100,
+        0x0011cf01,
+        0x010911e7,
+        0xfe0814b6,
+        0x17f10014,
+        0x13f000e0,
+        0x1c07f000,
+        0xbd0001d0,
+        0xff17f004,
+        0xd01407f0,
+        0x04bd0001,
+        0xf10217f0,
+        0xf0080015,
+        0x01d01007,
+        0xf104bd00,
+        0xf000f617,
+        0x10fe0013,
+        0x1031f400,
+        0xf00117f0,
+        0x01d03807,
+        0xf004bd00,
+/* 0x03a2: init_proc */
+        0xf19858f7,
+        0x0016b001,
+        0xf9fa0bf4,
+        0x58f0b615,
+/* 0x03b3: mulu32_32_64 */
+        0xf9f20ef4,
+        0xf920f910,
+        0x9540f930,
+        0xd29510e1,
+        0xbdc4bd10,
+        0xc0edffb4,
+        0xb9301dff,
+        0x34f10234,
+        0x34b6ffff,
+        0x1045b610,
+        0xbb00c3bb,
+        0xe2ff01b4,
+        0x0234b930,
+        0xffff34f1,
+        0xb61034b6,
+        0xc3bb1045,
+        0x01b4bb00,
+        0xbb3012ff,
+        0x40fc00b3,
+        0x20fc30fc,
+        0x00f810fc,
+/* 0x0404: host_send */
+        0x04b017f1,
+        0xf10011cf,
+        0xcf04a027,
+        0x12b80022,
+        0x2f0bf406,
+        0x94071ec4,
+        0xe0b704ee,
+        0xeb980270,
+        0x02ec9803,
+        0x9801ed98,
+        0x21f500ee,
+        0x10b602f1,
+        0x0f1ec401,
+        0x04b007f1,
+        0xbd000ed0,
+        0xc30ef404,
+/* 0x0444: host_send_done */
+/* 0x0446: host_recv */
         0x17f100f8,
-        0x14b60080,
-        0x7015f110,
-        0xd007f102,
-        0x0001d004,
-        0x17f104bd,
-        0x14b60080,
-        0xf015f110,
-        0xdc07f102,
-        0x0001d004,
-        0x17f004bd,
-        0xc407f101,
-        0x0001d004,
-        0x00f804bd,
-/* 0x03f4: memx_func_enter */
+        0x13f14e49,
+        0xe1b85254,
+        0xb30bf406,
+/* 0x0454: host_recv_wait */
+        0x04cc17f1,
+        0xf10011cf,
+        0xcf04c827,
+        0x16f00022,
+        0x0612b808,
+        0xc4ec0bf4,
+        0x34b60723,
+        0xf030b704,
+        0x033b8002,
+        0x80023c80,
+        0x3e80013d,
+        0x0120b600,
+        0xf10f24f0,
+        0xd004c807,
+        0x04bd0002,
+        0xf04027f0,
+        0x02d00007,
+        0xf804bd00,
+/* 0x049d: host_init */
+        0x8017f100,
+        0x1014b600,
+        0x027015f1,
+        0x04d007f1,
+        0xbd0001d0,
+        0x8017f104,
+        0x1014b600,
+        0x02f015f1,
+        0x04dc07f1,
+        0xbd0001d0,
+        0x0117f004,
+        0x04c407f1,
+        0xbd0001d0,
+/* 0x04d3: memx_func_enter */
+        0xf100f804,
+        0xf1162067,
+        0xf1f55d77,
+        0xb9ffff73,
+        0x21f4026e,
+        0x02d8b904,
+        0xf90487fd,
+        0xfc80f960,
+        0xf4e0fcd0,
+        0x77f13321,
+        0x73f1fffe,
+        0x6eb9ffff,
+        0x0421f402,
+        0xfd02d8b9,
+        0x60f90487,
+        0xd0fc80f9,
+        0x21f4e0fc,
+        0xf067f133,
+        0x026eb926,
+        0xb90421f4,
+        0x87fd02d8,
+        0xf960f904,
+        0xfcd0fc80,
+        0x3321f4e0,
         0xf10467f0,
         0xd007e007,
         0x04bd0006,
-/* 0x0400: memx_func_enter_wait */
+/* 0x053c: memx_func_enter_wait */
         0x07c067f1,
         0xf00066cf,
         0x0bf40464,
-        0x001698f6,
-        0xf80410b6,
-/* 0x0415: memx_func_leave */
-        0x0467f000,
+        0x2c67f0f6,
+        0x800066cf,
+        0x00f8ee06,
+/* 0x0554: memx_func_leave */
+        0xcf2c67f0,
+        0x06800066,
+        0x0467f0ef,
         0x07e407f1,
         0xbd0006d0,
-/* 0x0421: memx_func_leave_wait */
+/* 0x0569: memx_func_leave_wait */
         0xc067f104,
         0x0066cf07,
         0xf40464f0,
-        0x00f8f61b,
-/* 0x0430: memx_func_wr32 */
+        0x67f1f61b,
+        0x77f126f0,
+        0x73f00001,
+        0x026eb900,
+        0xb90421f4,
+        0x87fd02d8,
+        0xf960f905,
+        0xfcd0fc80,
+        0x3321f4e0,
+        0x162067f1,
+        0xf4026eb9,
+        0xd8b90421,
+        0x0587fd02,
+        0x80f960f9,
+        0xe0fcd0fc,
+        0xf13321f4,
+        0xf00aa277,
+        0x6eb90073,
+        0x0421f402,
+        0xfd02d8b9,
+        0x60f90587,
+        0xd0fc80f9,
+        0x21f4e0fc,
+/* 0x05d3: memx_func_wait_vblank */
+        0xb600f833,
+        0x00f80410,
+/* 0x05d8: memx_func_wr32 */
         0x98001698,
         0x10b60115,
         0xf960f908,
@@ -1102,131 +1281,137 @@ uint32_t nvd0_pwr_code[] = {
         0x3321f4e0,
         0xf40242b6,
         0x00f8e91b,
-/* 0x044c: memx_func_wait */
+/* 0x05f4: memx_func_wait */
         0xcf2c87f0,
         0x1e980088,
         0x011d9800,
         0x98021c98,
         0x10b6031b,
-        0x7e21f410,
-/* 0x0466: memx_func_delay */
+        0x8621f410,
+/* 0x060e: memx_func_delay */
         0x1e9800f8,
         0x0410b600,
         0xf86721f4,
-/* 0x0471: memx_exec */
+/* 0x0619: memx_exec */
         0xf9e0f900,
         0x02c1b9d0,
-/* 0x047b: memx_exec_next */
+/* 0x0623: memx_exec_next */
         0x9802b2b9,
         0x10b60013,
-        0x10349504,
+        0xf034e704,
+        0xe033e701,
+        0x0132b601,
         0x980c30f0,
         0x55f9de35,
         0xf40612b8,
-        0xd0fcec1e,
+        0x0b98e41e,
+        0xef0c98ee,
+        0xf102cbbb,
+        0xcf07c4b7,
+        0xd0fc00bb,
         0x21f5e0fc,
-        0x00f8026b,
-/* 0x049c: memx_info */
-        0x03acc7f1,
+        0x00f802f1,
+/* 0x065c: memx_info */
+        0x03c0c7f1,
         0x0800b7f1,
-        0x026b21f5,
-/* 0x04aa: memx_recv */
+        0x02f121f5,
+/* 0x066a: memx_recv */
         0xd6b000f8,
-        0xc40bf401,
+        0xac0bf401,
         0xf400d6b0,
         0x00f8e90b,
-/* 0x04b8: memx_init */
-/* 0x04ba: perf_recv */
+/* 0x0678: memx_init */
+/* 0x067a: perf_recv */
         0x00f800f8,
-/* 0x04bc: perf_init */
-/* 0x04be: i2c_drive_scl */
+/* 0x067c: perf_init */
+/* 0x067e: i2c_drive_scl */
         0x36b000f8,
         0x0e0bf400,
         0x07e007f1,
         0xbd0001d0,
-/* 0x04cf: i2c_drive_scl_lo */
+/* 0x068f: i2c_drive_scl_lo */
         0xf100f804,
         0xd007e407,
         0x04bd0001,
-/* 0x04da: i2c_drive_sda */
+/* 0x069a: i2c_drive_sda */
         0x36b000f8,
         0x0e0bf400,
         0x07e007f1,
         0xbd0002d0,
-/* 0x04eb: i2c_drive_sda_lo */
+/* 0x06ab: i2c_drive_sda_lo */
         0xf100f804,
         0xd007e407,
         0x04bd0002,
-/* 0x04f6: i2c_sense_scl */
+/* 0x06b6: i2c_sense_scl */
         0x32f400f8,
         0xc437f101,
         0x0033cf07,
         0xf40431fd,
         0x31f4060b,
-/* 0x0509: i2c_sense_scl_done */
-/* 0x050b: i2c_sense_sda */
+/* 0x06c9: i2c_sense_scl_done */
+/* 0x06cb: i2c_sense_sda */
         0xf400f801,
         0x37f10132,
         0x33cf07c4,
         0x0432fd00,
         0xf4060bf4,
-/* 0x051e: i2c_sense_sda_done */
+/* 0x06de: i2c_sense_sda_done */
         0x00f80131,
-/* 0x0520: i2c_raise_scl */
+/* 0x06e0: i2c_raise_scl */
         0x47f140f9,
         0x37f00898,
-        0xbe21f501,
-/* 0x052d: i2c_raise_scl_wait */
-        0xe8e7f104,
+        0x7e21f501,
+/* 0x06ed: i2c_raise_scl_wait */
+        0xe8e7f106,
         0x6721f403,
-        0x04f621f5,
+        0x06b621f5,
         0xb60901f4,
         0x1bf40142,
-/* 0x0541: i2c_raise_scl_done */
+/* 0x0701: i2c_raise_scl_done */
         0xf840fcef,
-/* 0x0545: i2c_start */
-        0xf621f500,
-        0x0d11f404,
-        0x050b21f5,
+/* 0x0705: i2c_start */
+        0xb621f500,
+        0x0d11f406,
+        0x06cb21f5,
         0xf40611f4,
-/* 0x0556: i2c_start_rep */
+/* 0x0716: i2c_start_rep */
         0x37f0300e,
-        0xbe21f500,
-        0x0137f004,
-        0x04da21f5,
+        0x7e21f500,
+        0x0137f006,
+        0x069a21f5,
         0xb60076bb,
         0x50f90465,
         0xbb046594,
         0x50bd0256,
         0xfc0475fd,
-        0x2021f550,
-        0x0464b605,
-/* 0x0583: i2c_start_send */
+        0xe021f550,
+        0x0464b606,
+/* 0x0743: i2c_start_send */
         0xf01f11f4,
         0x21f50037,
-        0xe7f104da,
+        0xe7f1069a,
         0x21f41388,
         0x0037f067,
-        0x04be21f5,
+        0x067e21f5,
         0x1388e7f1,
-/* 0x059f: i2c_start_out */
+/* 0x075f: i2c_start_out */
         0xf86721f4,
-/* 0x05a1: i2c_stop */
+/* 0x0761: i2c_stop */
         0x0037f000,
-        0x04be21f5,
+        0x067e21f5,
         0xf50037f0,
-        0xf104da21,
+        0xf1069a21,
         0xf403e8e7,
         0x37f06721,
-        0xbe21f501,
-        0x88e7f104,
+        0x7e21f501,
+        0x88e7f106,
         0x6721f413,
         0xf50137f0,
-        0xf104da21,
+        0xf1069a21,
         0xf41388e7,
         0x00f86721,
-/* 0x05d4: i2c_bitw */
-        0x04da21f5,
+/* 0x0794: i2c_bitw */
+        0x069a21f5,
         0x03e8e7f1,
         0xbb6721f4,
         0x65b60076,
@@ -1234,18 +1419,18 @@ uint32_t nvd0_pwr_code[] = {
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x052021f5,
+        0x06e021f5,
         0xf40464b6,
         0xe7f11811,
         0x21f41388,
         0x0037f067,
-        0x04be21f5,
+        0x067e21f5,
         0x1388e7f1,
-/* 0x0613: i2c_bitw_out */
+/* 0x07d3: i2c_bitw_out */
         0xf86721f4,
-/* 0x0615: i2c_bitr */
+/* 0x07d5: i2c_bitr */
         0x0137f000,
-        0x04da21f5,
+        0x069a21f5,
         0x03e8e7f1,
         0xbb6721f4,
         0x65b60076,
@@ -1253,19 +1438,19 @@ uint32_t nvd0_pwr_code[] = {
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x052021f5,
+        0x06e021f5,
         0xf40464b6,
         0x21f51b11,
-        0x37f0050b,
-        0xbe21f500,
-        0x88e7f104,
+        0x37f006cb,
+        0x7e21f500,
+        0x88e7f106,
         0x6721f413,
         0xf4013cf0,
-/* 0x065a: i2c_bitr_done */
+/* 0x081a: i2c_bitr_done */
         0x00f80131,
-/* 0x065c: i2c_get_byte */
+/* 0x081c: i2c_get_byte */
         0xf00057f0,
-/* 0x0662: i2c_get_byte_next */
+/* 0x0822: i2c_get_byte_next */
         0x54b60847,
         0x0076bb01,
         0xf90465b6,
@@ -1273,7 +1458,7 @@ uint32_t nvd0_pwr_code[] = {
         0xbd0256bb,
         0x0475fd50,
         0x21f550fc,
-        0x64b60615,
+        0x64b607d5,
         0x2b11f404,
         0xb60553fd,
         0x1bf40142,
@@ -1283,12 +1468,12 @@ uint32_t nvd0_pwr_code[] = {
         0xbb046594,
         0x50bd0256,
         0xfc0475fd,
-        0xd421f550,
-        0x0464b605,
-/* 0x06ac: i2c_get_byte_done */
-/* 0x06ae: i2c_put_byte */
+        0x9421f550,
+        0x0464b607,
+/* 0x086c: i2c_get_byte_done */
+/* 0x086e: i2c_put_byte */
         0x47f000f8,
-/* 0x06b1: i2c_put_byte_next */
+/* 0x0871: i2c_put_byte_next */
         0x0142b608,
         0xbb3854ff,
         0x65b60076,
@@ -1296,7 +1481,7 @@ uint32_t nvd0_pwr_code[] = {
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x05d421f5,
+        0x079421f5,
         0xf40464b6,
         0x46b03411,
         0xd81bf400,
@@ -1305,21 +1490,21 @@ uint32_t nvd0_pwr_code[] = {
         0xbb046594,
         0x50bd0256,
         0xfc0475fd,
-        0x1521f550,
-        0x0464b606,
+        0xd521f550,
+        0x0464b607,
         0xbb0f11f4,
         0x36b00076,
         0x061bf401,
-/* 0x0707: i2c_put_byte_done */
+/* 0x08c7: i2c_put_byte_done */
         0xf80132f4,
-/* 0x0709: i2c_addr */
+/* 0x08c9: i2c_addr */
         0x0076bb00,
         0xf90465b6,
         0x04659450,
         0xbd0256bb,
         0x0475fd50,
         0x21f550fc,
-        0x64b60545,
+        0x64b60705,
         0x2911f404,
         0x012ec3e7,
         0xfd0134b6,
@@ -1329,30 +1514,30 @@ uint32_t nvd0_pwr_code[] = {
         0x0256bb04,
         0x75fd50bd,
         0xf550fc04,
-        0xb606ae21,
-/* 0x074e: i2c_addr_done */
+        0xb6086e21,
+/* 0x090e: i2c_addr_done */
         0x00f80464,
-/* 0x0750: i2c_acquire_addr */
+/* 0x0910: i2c_acquire_addr */
         0xb6f8cec7,
         0xe0b705e4,
         0x00f8d014,
-/* 0x075c: i2c_acquire */
-        0x075021f5,
+/* 0x091c: i2c_acquire */
+        0x091021f5,
         0xf00421f4,
         0x21f403d9,
-/* 0x076b: i2c_release */
+/* 0x092b: i2c_release */
         0xf500f833,
-        0xf4075021,
+        0xf4091021,
         0xdaf00421,
         0x3321f403,
-/* 0x077a: i2c_recv */
+/* 0x093a: i2c_recv */
         0x32f400f8,
         0xf8c1c701,
         0xb00214b6,
         0x1ff52816,
         0x13a0013a,
-        0x32980bd4,
-        0xac13a000,
+        0x32980be8,
+        0xc013a000,
         0x0031980b,
         0xf90231f4,
         0xf9e0f9d0,
@@ -1364,8 +1549,8 @@ uint32_t nvd0_pwr_code[] = {
         0xbb046594,
         0x50bd0256,
         0xfc0475fd,
-        0x5c21f550,
-        0x0464b607,
+        0x1c21f550,
+        0x0464b609,
         0xd6b0d0fc,
         0xb31bf500,
         0x0057f000,
@@ -1374,8 +1559,8 @@ uint32_t nvd0_pwr_code[] = {
         0xbb046594,
         0x50bd0256,
         0xfc0475fd,
-        0x0921f550,
-        0x0464b607,
+        0xc921f550,
+        0x0464b608,
         0x00d011f5,
         0xbbe0c5c7,
         0x65b60076,
@@ -1383,7 +1568,7 @@ uint32_t nvd0_pwr_code[] = {
         0x56bb0465,
         0xfd50bd02,
         0x50fc0475,
-        0x06ae21f5,
+        0x086e21f5,
         0xf50464b6,
         0xf000ad11,
         0x76bb0157,
@@ -1392,7 +1577,7 @@ uint32_t nvd0_pwr_code[] = {
         0x0256bb04,
         0x75fd50bd,
         0xf550fc04,
-        0xb6070921,
+        0xb608c921,
         0x11f50464,
         0x76bb008a,
         0x0465b600,
@@ -1400,7 +1585,7 @@ uint32_t nvd0_pwr_code[] = {
         0x0256bb04,
         0x75fd50bd,
         0xf550fc04,
-        0xb6065c21,
+        0xb6081c21,
         0x11f40464,
         0xe05bcb6a,
         0xb60076bb,
@@ -1408,38 +1593,38 @@ uint32_t nvd0_pwr_code[] = {
         0xbb046594,
         0x50bd0256,
         0xfc0475fd,
-        0xa121f550,
-        0x0464b605,
+        0x6121f550,
+        0x0464b607,
         0xbd025bb9,
         0x430ef474,
-/* 0x0880: i2c_recv_not_rd08 */
+/* 0x0a40: i2c_recv_not_rd08 */
         0xf401d6b0,
         0x57f03d1b,
-        0x0921f500,
-        0x3311f407,
+        0xc921f500,
+        0x3311f408,
         0xf5e0c5c7,
-        0xf406ae21,
+        0xf4086e21,
         0x57f02911,
-        0x0921f500,
-        0x1f11f407,
+        0xc921f500,
+        0x1f11f408,
         0xf5e0b5c7,
-        0xf406ae21,
+        0xf4086e21,
         0x21f51511,
-        0x74bd05a1,
+        0x74bd0761,
         0xf408c5c7,
         0x32f4091b,
         0x030ef402,
-/* 0x08c0: i2c_recv_not_wr08 */
-/* 0x08c0: i2c_recv_done */
+/* 0x0a80: i2c_recv_not_wr08 */
+/* 0x0a80: i2c_recv_done */
         0xf5f8cec7,
-        0xfc076b21,
+        0xfc092b21,
         0xf4d0fce0,
         0x7cb90a12,
-        0x6b21f502,
-/* 0x08d5: i2c_recv_exit */
-/* 0x08d7: i2c_init */
+        0xf121f502,
+/* 0x0a95: i2c_recv_exit */
+/* 0x0a97: i2c_init */
         0xf800f802,
-/* 0x08d9: test_recv */
+/* 0x0a99: test_recv */
         0xd817f100,
         0x0011cf05,
         0xf10110b6,
@@ -1447,29 +1632,29 @@ uint32_t nvd0_pwr_code[] = {
         0x04bd0001,
         0xd900e7f1,
         0x134fe3f1,
-        0x01b621f5,
-/* 0x08fa: test_init */
+        0x022321f5,
+/* 0x0aba: test_init */
         0xe7f100f8,
         0x21f50800,
-        0x00f801b6,
-/* 0x0904: idle_recv */
-/* 0x0906: idle */
+        0x00f80223,
+/* 0x0ac4: idle_recv */
+/* 0x0ac6: idle */
         0x31f400f8,
         0xd417f100,
         0x0011cf05,
         0xf10110b6,
         0xd005d407,
         0x04bd0001,
-/* 0x091c: idle_loop */
+/* 0x0adc: idle_loop */
         0xf45817f0,
-/* 0x0922: idle_proc */
-/* 0x0922: idle_proc_exec */
+/* 0x0ae2: idle_proc */
+/* 0x0ae2: idle_proc_exec */
         0x10f90232,
         0xf5021eb9,
-        0xfc027421,
+        0xfc02fa21,
         0x0911f410,
         0xf40231f4,
-/* 0x0936: idle_proc_next */
+/* 0x0af6: idle_proc_next */
         0x10b6ef0e,
         0x061fb858,
         0xf4e61bf4,
@@ -1521,4 +1706,20 @@ uint32_t nvd0_pwr_code[] = {
         0x00000000,
         0x00000000,
         0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
 };
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
index 574acfa44c8c..522e3079f824 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
@@ -19,11 +19,12 @@
 #define MEMX_MSG_EXEC 1
 
 /* MEMX: script opcode definitions */
-#define MEMX_ENTER  0
-#define MEMX_LEAVE  1
-#define MEMX_WR32   2
-#define MEMX_WAIT   3
-#define MEMX_DELAY  4
+#define MEMX_ENTER  1
+#define MEMX_LEAVE  2
+#define MEMX_WR32   3
+#define MEMX_WAIT   4
+#define MEMX_DELAY  5
+#define MEMX_VBLANK 6
 
 /* I2C_: message identifiers */
 #define I2C__MSG_RD08 0
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
index def6a9ac68cf..65eaa2546cad 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
@@ -20,10 +20,11 @@ memx_out(struct nouveau_memx *memx)
         struct nouveau_pwr *ppwr = memx->ppwr;
         int i;
 
-        if (memx->c.size) {
+        if (memx->c.mthd) {
                 nv_wr32(ppwr, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
                 for (i = 0; i < memx->c.size; i++)
                         nv_wr32(ppwr, 0x10a1c4, memx->c.data[i]);
+                memx->c.mthd = 0;
                 memx->c.size = 0;
         }
 }
@@ -32,7 +33,7 @@ static void
 memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[])
 {
         if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) ||
-            (memx->c.size && memx->c.mthd != mthd))
+            (memx->c.mthd && memx->c.mthd != mthd))
                 memx_out(memx);
         memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0]));
         memx->c.size += size;
@@ -62,8 +63,7 @@ nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx)
                 nv_wr32(ppwr, 0x10a580, 0x00000003);
         } while (nv_rd32(ppwr, 0x10a580) != 0x00000003);
         nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base);
-        nv_wr32(ppwr, 0x10a1c4, 0x00010000 | MEMX_ENTER);
-        nv_wr32(ppwr, 0x10a1c4, 0x00000000);
+
         return 0;
 }
 
@@ -78,7 +78,6 @@ nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
         memx_out(memx);
 
         /* release data segment access */
-        nv_wr32(ppwr, 0x10a1c4, 0x00000000 | MEMX_LEAVE);
         finish = nv_rd32(ppwr, 0x10a1c0) & 0x00ffffff;
         nv_wr32(ppwr, 0x10a580, 0x00000000);
 
@@ -88,6 +87,8 @@ nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
                                  memx->base, finish);
         }
 
+        nv_debug(memx->ppwr, "Exec took %uns, PPWR_IN %08x\n",
+                 reply[0], reply[1]);
         kfree(memx);
         return 0;
 }
@@ -117,4 +118,51 @@ nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec)
         memx_out(memx); /* fuc can't handle multiple */
 }
 
+void
+nouveau_memx_wait_vblank(struct nouveau_memx *memx)
+{
+        struct nouveau_pwr *ppwr = memx->ppwr;
+        u32 heads, x, y, px = 0;
+        int i, head_sync;
+
+        if (nv_device(ppwr)->chipset < 0xd0) {
+                heads = nv_rd32(ppwr, 0x610050);
+                for (i = 0; i < 2; i++) {
+                        /* Heuristic: sync to head with biggest resolution */
+                        if (heads & (2 << (i << 3))) {
+                                x = nv_rd32(ppwr, 0x610b40 + (0x540 * i));
+                                y = (x & 0xffff0000) >> 16;
+                                x &= 0x0000ffff;
+                                if ((x * y) > px) {
+                                        px = (x * y);
+                                        head_sync = i;
+                                }
+                        }
+                }
+        }
+
+        if (px == 0) {
+                nv_debug(memx->ppwr, "WAIT VBLANK !NO ACTIVE HEAD\n");
+                return;
+        }
+
+        nv_debug(memx->ppwr, "WAIT VBLANK HEAD%d\n", head_sync);
+        memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync });
+        memx_out(memx); /* fuc can't handle multiple */
+}
+
+void
+nouveau_memx_block(struct nouveau_memx *memx)
+{
+        nv_debug(memx->ppwr, "   HOST BLOCKED\n");
+        memx_cmd(memx, MEMX_ENTER, 0, NULL);
+}
+
+void
+nouveau_memx_unblock(struct nouveau_memx *memx)
+{
+        nv_debug(memx->ppwr, "   HOST UNBLOCKED\n");
+        memx_cmd(memx, MEMX_LEAVE, 0, NULL);
+}
+
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c
index 016990a8252c..3656d605168f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c
@@ -31,6 +31,8 @@
 #include <subdev/gpio.h>
 #include <subdev/timer.h>
 
+#include <subdev/bios/fan.h>
+
 static int
 nouveau_fan_update(struct nouveau_fan *fan, bool immediate, int target)
 {
@@ -275,8 +277,11 @@ nouveau_therm_fan_ctor(struct nouveau_therm *therm)
         /* other random init... */
         nouveau_therm_fan_set_defaults(therm);
         nvbios_perf_fan_parse(bios, &priv->fan->perf);
-        if (nvbios_therm_fan_parse(bios, &priv->fan->bios))
-                nv_error(therm, "parsing the thermal table failed\n");
+        if (!nvbios_fan_parse(bios, &priv->fan->bios)) {
+                nv_debug(therm, "parsing the fan table failed\n");
+                if (nvbios_therm_fan_parse(bios, &priv->fan->bios))
+                        nv_error(therm, "parsing both fan tables failed\n");
+        }
         nouveau_therm_fan_safety_checks(therm);
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c
index 9a5c07340263..c629d7f2a6a4 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c
@@ -25,6 +25,8 @@
 
 #include <core/option.h>
 #include <subdev/gpio.h>
+#include <subdev/bios.h>
+#include <subdev/bios/fan.h>
 
 #include "priv.h"
 
@@ -86,11 +88,15 @@ nouveau_fanpwm_create(struct nouveau_therm *therm, struct dcb_gpio_func *func)
 {
         struct nouveau_device *device = nv_device(therm);
         struct nouveau_therm_priv *tpriv = (void *)therm;
+        struct nouveau_bios *bios = nouveau_bios(therm);
         struct nouveau_fanpwm_priv *priv;
+        struct nvbios_therm_fan fan;
         u32 divs, duty;
 
+        nvbios_fan_parse(bios, &fan);
+
         if (!nouveau_boolopt(device->cfgopt, "NvFanPWM", func->param) ||
-            !therm->pwm_ctrl ||
+            !therm->pwm_ctrl || fan.type == NVBIOS_THERM_FAN_TOGGLE ||
              therm->pwm_get(therm, func->line, &divs, &duty) == -ENODEV)
                 return -ENODEV;
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c
new file mode 100644
index 000000000000..668cf3322285
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2014 Martin Peres
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Martin Peres
+ */
+
+#include "priv.h"
+
+struct gm107_therm_priv {
+        struct nouveau_therm_priv base;
+};
+
+static int
+gm107_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
+{
+        /* nothing to do, it seems hardwired */
+        return 0;
+}
+
+static int
+gm107_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
+{
+        *divs = nv_rd32(therm, 0x10eb20) & 0x1fff;
+        *duty = nv_rd32(therm, 0x10eb24) & 0x1fff;
+        return 0;
+}
+
+static int
+gm107_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
+{
+        nv_mask(therm, 0x10eb10, 0x1fff, divs); /* keep the high bits */
+        nv_wr32(therm, 0x10eb14, duty | 0x80000000);
+        return 0;
+}
+
+static int
+gm107_fan_pwm_clock(struct nouveau_therm *therm, int line)
+{
+        return nv_device(therm)->crystal * 1000;
+}
+
+static int
+gm107_therm_ctor(struct nouveau_object *parent,
+                struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct gm107_therm_priv *priv;
+        int ret;
+
+        ret = nouveau_therm_create(parent, engine, oclass, &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        priv->base.base.pwm_ctrl = gm107_fan_pwm_ctrl;
+        priv->base.base.pwm_get = gm107_fan_pwm_get;
+        priv->base.base.pwm_set = gm107_fan_pwm_set;
+        priv->base.base.pwm_clock = gm107_fan_pwm_clock;
+        priv->base.base.temp_get = nv84_temp_get;
+        priv->base.base.fan_sense = nva3_therm_fan_sense;
+        priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
+        return nouveau_therm_preinit(&priv->base.base);
+}
+
+struct nouveau_oclass
+gm107_therm_oclass = {
+        .handle = NV_SUBDEV(THERM, 0x117),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = gm107_therm_ctor,
+                .dtor = _nouveau_therm_dtor,
+                .init = nvd0_therm_init,
+                .fini = nv84_therm_fini,
+        },
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c
index 1d15c52fad0c..14e2e09bfc24 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c
@@ -24,6 +24,7 @@
  */
 
 #include "priv.h"
+#include <subdev/fuse.h>
 
 struct nv84_therm_priv {
         struct nouveau_therm_priv base;
@@ -32,7 +33,25 @@ struct nv84_therm_priv {
 int
 nv84_temp_get(struct nouveau_therm *therm)
 {
-        return nv_rd32(therm, 0x20400);
+        struct nouveau_fuse *fuse = nouveau_fuse(therm);
+
+        if (nv_ro32(fuse, 0x1a8) == 1)
+                return nv_rd32(therm, 0x20400);
+        else
+                return -ENODEV;
+}
+
+void
+nv84_sensor_setup(struct nouveau_therm *therm)
+{
+        struct nouveau_fuse *fuse = nouveau_fuse(therm);
+
+        /* enable temperature reading for cards with insane defaults */
+        if (nv_ro32(fuse, 0x1a8) == 1) {
+                nv_mask(therm, 0x20008, 0x80008000, 0x80000000);
+                nv_mask(therm, 0x2000c, 0x80000003, 0x00000000);
+                mdelay(20); /* wait for the temperature to stabilize */
+        }
 }
 
 static void
@@ -171,6 +190,21 @@ nv84_therm_intr(struct nouveau_subdev *subdev)
 }
 
 static int
+nv84_therm_init(struct nouveau_object *object)
+{
+        struct nv84_therm_priv *priv = (void *)object;
+        int ret;
+
+        ret = nouveau_therm_init(&priv->base.base);
+        if (ret)
+                return ret;
+
+        nv84_sensor_setup(&priv->base.base);
+
+        return 0;
+}
+
+static int
 nv84_therm_ctor(struct nouveau_object *parent,
                 struct nouveau_object *engine,
                 struct nouveau_oclass *oclass, void *data, u32 size,
@@ -228,7 +262,7 @@ nv84_therm_oclass = {
         .ofuncs = &(struct nouveau_ofuncs) {
                 .ctor = nv84_therm_ctor,
                 .dtor = _nouveau_therm_dtor,
-                .init = _nouveau_therm_init,
+                .init = nv84_therm_init,
                 .fini = nv84_therm_fini,
         },
 };
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c
index 0478b2e3fb1d..7893357a7e9f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c
@@ -51,6 +51,8 @@ nva3_therm_init(struct nouveau_object *object)
         if (ret)
                 return ret;
 
+        nv84_sensor_setup(&priv->base.base);
+
         /* enable fan tach, count revolutions per-second */
         nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
         if (tach->func != DCB_GPIO_UNUSED) {
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c
index bbf117be572f..b70f7cc649b8 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c
@@ -114,7 +114,7 @@ nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line)
                 return nv_device(therm)->crystal * 1000 / 10;
 }
 
-static int
+int
 nvd0_therm_init(struct nouveau_object *object)
 {
         struct nvd0_therm_priv *priv = (void *)object;
@@ -150,6 +150,8 @@ nvd0_therm_ctor(struct nouveau_object *parent,
         if (ret)
                 return ret;
 
+        nv84_sensor_setup(&priv->base.base);
+
         priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl;
         priv->base.base.pwm_get = nvd0_fan_pwm_get;
         priv->base.base.pwm_set = nvd0_fan_pwm_set;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h
index 916fca5c7816..7dba8c281a0b 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h
@@ -145,10 +145,13 @@ int nv50_fan_pwm_get(struct nouveau_therm *, int, u32 *, u32 *);
 int nv50_fan_pwm_set(struct nouveau_therm *, int, u32, u32);
 int nv50_fan_pwm_clock(struct nouveau_therm *, int);
 int nv84_temp_get(struct nouveau_therm *therm);
+void nv84_sensor_setup(struct nouveau_therm *therm);
 int nv84_therm_fini(struct nouveau_object *object, bool suspend);
 
 int nva3_therm_fan_sense(struct nouveau_therm *);
 
+int nvd0_therm_init(struct nouveau_object *object);
+
 int nouveau_fanpwm_create(struct nouveau_therm *, struct dcb_gpio_func *);
 int nouveau_fantog_create(struct nouveau_therm *, struct dcb_gpio_func *);
 int nouveau_fannil_create(struct nouveau_therm *);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
index 7dd680ff2f6f..f75a683bd47a 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
@@ -296,7 +296,7 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
         int ret;
 
         mutex_lock(&nv_subdev(vmm)->mutex);
-        ret = nouveau_mm_head(&vm->mm, page_shift, msize, msize, align,
+        ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align,
                              &vma->node);
         if (unlikely(ret != 0)) {
                 mutex_unlock(&nv_subdev(vmm)->mutex);
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 615714c1727d..a24faa5e2a2a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -448,7 +448,7 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
         list_add(&ntfy->head, &chan->notifiers);
         ntfy->handle = info->handle;
 
-        ret = nouveau_mm_head(&chan->heap, 1, info->size, info->size, 1,
+        ret = nouveau_mm_head(&chan->heap, 0, 1, info->size, info->size, 1,
                               &ntfy->node);
         if (ret)
                 goto done;
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index 99cd9e4a2aa6..9a362ddd8225 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -36,7 +36,7 @@
 #include "nouveau_abi16.h"
 
 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
-static int nouveau_vram_pushbuf;
+int nouveau_vram_pushbuf;
 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
 
 int
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h
index 20163709d608..8309c24ee698 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.h
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.h
@@ -47,4 +47,6 @@ int  nouveau_channel_new(struct nouveau_drm *, struct nvif_device *,
 void nouveau_channel_del(struct nouveau_channel **);
 int  nouveau_channel_idle(struct nouveau_channel *);
 
+extern int nouveau_vram_pushbuf;
+
 #endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 1ec44c83e919..c8ac9482cf2e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -45,15 +45,15 @@
 #include <nvif/event.h>
 
 MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
-static int nouveau_tv_disable = 0;
+int nouveau_tv_disable = 0;
 module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
 
 MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
-static int nouveau_ignorelid = 0;
+int nouveau_ignorelid = 0;
 module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
 
 MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (default: enabled)");
-static int nouveau_duallink = 1;
+int nouveau_duallink = 1;
 module_param_named(duallink, nouveau_duallink, int, 0400);
 
 struct nouveau_encoder *
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
index 68029d041dd2..629a380c7085 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -105,4 +105,8 @@ nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
 struct drm_connector *
 nouveau_connector_create(struct drm_device *, int index);
 
+extern int nouveau_tv_disable;
+extern int nouveau_ignorelid;
+extern int nouveau_duallink;
+
 #endif /* __NOUVEAU_CONNECTOR_H__ */
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index cee1eaf64117..244d78fc0cb5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -51,6 +51,7 @@
 #include "nouveau_fence.h"
 #include "nouveau_debugfs.h"
 #include "nouveau_usif.h"
+#include "nouveau_connector.h"
 
 MODULE_PARM_DESC(config, "option string to pass to driver core");
 static char *nouveau_config;
@@ -1028,6 +1029,23 @@ static int nouveau_pmops_runtime_idle(struct device *dev)
         return 1;
 }
 
+static void nouveau_display_options(void)
+{
+        DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
+
+        DRM_DEBUG_DRIVER("... tv_disable   : %d\n", nouveau_tv_disable);
+        DRM_DEBUG_DRIVER("... ignorelid    : %d\n", nouveau_ignorelid);
+        DRM_DEBUG_DRIVER("... duallink     : %d\n", nouveau_duallink);
+        DRM_DEBUG_DRIVER("... nofbaccel    : %d\n", nouveau_nofbaccel);
+        DRM_DEBUG_DRIVER("... config       : %s\n", nouveau_config);
+        DRM_DEBUG_DRIVER("... debug        : %s\n", nouveau_debug);
+        DRM_DEBUG_DRIVER("... noaccel      : %d\n", nouveau_noaccel);
+        DRM_DEBUG_DRIVER("... modeset      : %d\n", nouveau_modeset);
+        DRM_DEBUG_DRIVER("... runpm        : %d\n", nouveau_runtime_pm);
+        DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
+        DRM_DEBUG_DRIVER("... pstate       : %d\n", nouveau_pstate);
+}
+
 static const struct dev_pm_ops nouveau_pm_ops = {
         .suspend = nouveau_pmops_suspend,
         .resume = nouveau_pmops_resume,
@@ -1093,6 +1111,8 @@ nouveau_drm_init(void)
         driver_platform = driver_stub;
         driver_platform.set_busid = drm_platform_set_busid;
 
+        nouveau_display_options();
+
         if (nouveau_modeset == -1) {
 #ifdef CONFIG_VGA_CONSOLE
                 if (vgacon_text_force())
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 8bdd27091db8..f0ae10ca3ba9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -52,7 +52,7 @@
 #include "nouveau_crtc.h"
 
 MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
-static int nouveau_nofbaccel = 0;
+int nouveau_nofbaccel = 0;
 module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
 
 static void
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index 34658cfa8f5d..1e2e9e27a03b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -72,5 +72,8 @@ void nouveau_fbcon_accel_save_disable(struct drm_device *dev);
 void nouveau_fbcon_accel_restore(struct drm_device *dev);
 
 void nouveau_fbcon_output_poll_changed(struct drm_device *dev);
+
+extern int nouveau_nofbaccel;
+
 #endif /* __NV50_FBCON_H__ */
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.c b/drivers/gpu/drm/nouveau/nouveau_sysfs.c
index 3c6962d15b26..8fbbf3093d86 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sysfs.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sysfs.c
@@ -29,7 +29,7 @@
 #include "nouveau_sysfs.h"
 
 MODULE_PARM_DESC(pstate, "enable sysfs pstate file, which will be moved in the future");
-static int nouveau_pstate;
+int nouveau_pstate;
 module_param_named(pstate, nouveau_pstate, int, 0400);
 
 static inline struct drm_device *
diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.h b/drivers/gpu/drm/nouveau/nouveau_sysfs.h
index f973378160f8..4e5ea9241b28 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sysfs.h
+++ b/drivers/gpu/drm/nouveau/nouveau_sysfs.h
@@ -16,4 +16,6 @@ nouveau_sysfs(struct drm_device *dev)
 int  nouveau_sysfs_init(struct drm_device *);
 void nouveau_sysfs_fini(struct drm_device *);
 
+extern int nouveau_pstate;
+
 #endif
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 03949eaa629f..fdb3e1adea1e 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1066,7 +1066,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
-        u32 vblan2e = 0, vblan2s = 1;
+        u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
         u32 *push;
         int ret;
 
@@ -1083,6 +1083,11 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
         vblanke = vsynce + vbackp;
         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
         vblanks = vactive - vfrontp - 1;
+        /* XXX: Safe underestimate, even "0" works */
+        vblankus = (vactive - mode->vdisplay - 2) * hactive;
+        vblankus *= 1000;
+        vblankus /= mode->clock;
+
         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
                 vblan2e = vactive + vsynce + vbackp;
                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
@@ -1099,14 +1104,14 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
                         evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
                         evo_data(push, 0x00800000 | mode->clock);
                         evo_data(push, (ilace == 2) ? 2 : 0);
-                        evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
+                        evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 8);
                         evo_data(push, 0x00000000);
                         evo_data(push, (vactive << 16) | hactive);
                         evo_data(push, ( vsynce << 16) | hsynce);
                         evo_data(push, (vblanke << 16) | hblanke);
                         evo_data(push, (vblanks << 16) | hblanks);
                         evo_data(push, (vblan2e << 16) | vblan2s);
-                        evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
+                        evo_data(push, vblankus);
                         evo_data(push, 0x00000000);
                         evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
                         evo_data(push, 0x00000311);
@@ -1651,17 +1656,21 @@ static void
 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
 {
         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+        struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
         struct nouveau_connector *nv_connector;
         struct nv50_disp *disp = nv50_disp(encoder->dev);
-        struct {
-                struct nv50_disp_mthd_v1 base;
-                struct nv50_disp_sor_hda_eld_v0 eld;
+        struct __packed {
+                struct {
+                        struct nv50_disp_mthd_v1 mthd;
+                        struct nv50_disp_sor_hda_eld_v0 eld;
+                } base;
                 u8 data[sizeof(nv_connector->base.eld)];
         } args = {
-                .base.version = 1,
-                .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
-                .base.hasht   = nv_encoder->dcb->hasht,
-                .base.hashm   = nv_encoder->dcb->hashm,
+                .base.mthd.version = 1,
+                .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
+                .base.mthd.hasht   = nv_encoder->dcb->hasht,
+                .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
+                                     (0x0100 << nv_crtc->index),
         };
 
         nv_connector = nouveau_encoder_connector_get(nv_encoder);
@@ -1671,11 +1680,11 @@ nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 
-        nvif_mthd(disp->disp, 0, &args, sizeof(args));
+        nvif_mthd(disp->disp, 0, &args, sizeof(args.base) + args.data[2] * 4);
 }
 
 static void
-nv50_audio_disconnect(struct drm_encoder *encoder)
+nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 {
         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
         struct nv50_disp *disp = nv50_disp(encoder->dev);
@@ -1686,7 +1695,8 @@ nv50_audio_disconnect(struct drm_encoder *encoder)
                 .base.version = 1,
                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
                 .base.hasht   = nv_encoder->dcb->hasht,
-                .base.hashm   = nv_encoder->dcb->hashm,
+                .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
+                                (0x0100 << nv_crtc->index),
         };
 
         nvif_mthd(disp->disp, 0, &args, sizeof(args));
@@ -1745,8 +1755,6 @@ nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
                                (0x0100 << nv_crtc->index),
         };
 
-        nv50_audio_disconnect(encoder);
-
         nvif_mthd(disp->disp, 0, &args, sizeof(args));
 }
 
@@ -1855,6 +1863,7 @@ nv50_sor_disconnect(struct drm_encoder *encoder)
         if (nv_crtc) {
                 nv50_crtc_prepare(&nv_crtc->base);
                 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
+                nv50_audio_disconnect(encoder, nv_crtc);
                 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
         }
 }
@@ -1954,6 +1963,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
                         proto = 0x8;
                 else
                         proto = 0x9;
+                nv50_audio_mode_set(encoder, mode);
                 break;
         default:
                 BUG_ON(1);
diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h
index 573491f84792..e5a27df0672b 100644
--- a/drivers/gpu/drm/nouveau/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/nvif/class.h
@@ -479,6 +479,8 @@ struct nv50_disp_core_channel_dma_v0 {
         __u32 pushbuf;
 };
 
+#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
+
 /* cursor immediate */
 struct nv50_disp_cursor_v0 {
         __u8  version;
@@ -486,6 +488,8 @@ struct nv50_disp_cursor_v0 {
         __u8  pad02[6];
 };
 
+#define NV50_DISP_CURSOR_V0_NTFY_UEVENT                                    0x00
+
 /* base */
 struct nv50_disp_base_channel_dma_v0 {
         __u8  version;
@@ -494,6 +498,8 @@ struct nv50_disp_base_channel_dma_v0 {
         __u32 pushbuf;
 };
 
+#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
+
 /* overlay */
 struct nv50_disp_overlay_channel_dma_v0 {
         __u8  version;
@@ -502,6 +508,8 @@ struct nv50_disp_overlay_channel_dma_v0 {
         __u32 pushbuf;
 };
 
+#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT                       0x00
+
 /* overlay immediate */
 struct nv50_disp_overlay_v0 {
         __u8  version;
@@ -509,6 +517,7 @@ struct nv50_disp_overlay_v0 {
         __u8  pad02[6];
 };
 
+#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT                                   0x00
 
 /*******************************************************************************
  * fermi