aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDmitry Kravkov <dmitry@broadcom.com>2013-10-20 10:51:33 -0400
committerDavid S. Miller <davem@davemloft.net>2013-10-21 18:31:36 -0400
commit4293b9f57a46469d6762be3300e2c3fa6515905d (patch)
treef6020068f1393722e4ed08b40033ab97d0c31c36
parent32316a46f2bbd4a898acf86547197cff8476f442 (diff)
bnx2x: Don't pretend during register dump
As part of a register dump, the interface pretends to have the identity of other interfaces of the same physical device in order to perform HW configuration for them - specifically, it needs to prevent attentions from generating on those functions as the register dump accesses registers in common blocks which whose reading might generate an attention. However, such pretension is unsafe - unlike other flows in which the driver uses pretend, during register dump there is no guarantee no other HW access will take place (by other flows). If such access will take place, the HW will be accessed by the wrong interface, and leave both functions in an incorrect state. This patch removes all pretensions from the register dump flow. Instead, it changes initial configuration of attentions such that no fatal attention will be generated for other functions as a result of the register dump (notice however, a debug print claiming an attention from other functions IS possible during the register dump) Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by: Ariel Elior <ariele@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c40
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h38
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c328
3 files changed, 201 insertions, 205 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
index 324de5f05332..e8efa1c93ffe 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
@@ -891,17 +891,8 @@ static void bnx2x_get_regs(struct net_device *dev,
891 * will re-enable parity attentions right after the dump. 891 * will re-enable parity attentions right after the dump.
892 */ 892 */
893 893
894 /* Disable parity on path 0 */
895 bnx2x_pretend_func(bp, 0);
896 bnx2x_disable_blocks_parity(bp); 894 bnx2x_disable_blocks_parity(bp);
897 895
898 /* Disable parity on path 1 */
899 bnx2x_pretend_func(bp, 1);
900 bnx2x_disable_blocks_parity(bp);
901
902 /* Return to current function */
903 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
904
905 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 896 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
906 dump_hdr.preset = DUMP_ALL_PRESETS; 897 dump_hdr.preset = DUMP_ALL_PRESETS;
907 dump_hdr.version = BNX2X_DUMP_VERSION; 898 dump_hdr.version = BNX2X_DUMP_VERSION;
@@ -928,18 +919,9 @@ static void bnx2x_get_regs(struct net_device *dev,
928 /* Actually read the registers */ 919 /* Actually read the registers */
929 __bnx2x_get_regs(bp, p); 920 __bnx2x_get_regs(bp, p);
930 921
931 /* Re-enable parity attentions on path 0 */ 922 /* Re-enable parity attentions */
932 bnx2x_pretend_func(bp, 0);
933 bnx2x_clear_blocks_parity(bp); 923 bnx2x_clear_blocks_parity(bp);
934 bnx2x_enable_blocks_parity(bp); 924 bnx2x_enable_blocks_parity(bp);
935
936 /* Re-enable parity attentions on path 1 */
937 bnx2x_pretend_func(bp, 1);
938 bnx2x_clear_blocks_parity(bp);
939 bnx2x_enable_blocks_parity(bp);
940
941 /* Return to current function */
942 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
943} 925}
944 926
945static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 927static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
@@ -993,17 +975,8 @@ static int bnx2x_get_dump_data(struct net_device *dev,
993 * will re-enable parity attentions right after the dump. 975 * will re-enable parity attentions right after the dump.
994 */ 976 */
995 977
996 /* Disable parity on path 0 */
997 bnx2x_pretend_func(bp, 0);
998 bnx2x_disable_blocks_parity(bp); 978 bnx2x_disable_blocks_parity(bp);
999 979
1000 /* Disable parity on path 1 */
1001 bnx2x_pretend_func(bp, 1);
1002 bnx2x_disable_blocks_parity(bp);
1003
1004 /* Return to current function */
1005 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1006
1007 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 980 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1008 dump_hdr.preset = bp->dump_preset_idx; 981 dump_hdr.preset = bp->dump_preset_idx;
1009 dump_hdr.version = BNX2X_DUMP_VERSION; 982 dump_hdr.version = BNX2X_DUMP_VERSION;
@@ -1032,19 +1005,10 @@ static int bnx2x_get_dump_data(struct net_device *dev,
1032 /* Actually read the registers */ 1005 /* Actually read the registers */
1033 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 1006 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1034 1007
1035 /* Re-enable parity attentions on path 0 */ 1008 /* Re-enable parity attentions */
1036 bnx2x_pretend_func(bp, 0);
1037 bnx2x_clear_blocks_parity(bp); 1009 bnx2x_clear_blocks_parity(bp);
1038 bnx2x_enable_blocks_parity(bp); 1010 bnx2x_enable_blocks_parity(bp);
1039 1011
1040 /* Re-enable parity attentions on path 1 */
1041 bnx2x_pretend_func(bp, 1);
1042 bnx2x_clear_blocks_parity(bp);
1043 bnx2x_enable_blocks_parity(bp);
1044
1045 /* Return to current function */
1046 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1047
1048 return 0; 1012 return 0;
1049} 1013}
1050 1014
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h
index 76df015f486a..c2dfea7968f4 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h
@@ -640,23 +640,35 @@ static const struct {
640 * [30] MCP Latched ump_tx_parity 640 * [30] MCP Latched ump_tx_parity
641 * [31] MCP Latched scpad_parity 641 * [31] MCP Latched scpad_parity
642 */ 642 */
643#define MISC_AEU_ENABLE_MCP_PRTY_BITS \ 643#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
644 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 644 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
645 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 645 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
646 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 646 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
647
648#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
649 (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
647 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 650 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
648 651
649/* Below registers control the MCP parity attention output. When 652/* Below registers control the MCP parity attention output. When
650 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are 653 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
651 * enabled, when cleared - disabled. 654 * enabled, when cleared - disabled.
652 */ 655 */
653static const u32 mcp_attn_ctl_regs[] = { 656static const struct {
654 MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 657 u32 addr;
655 MISC_REG_AEU_ENABLE4_NIG_0, 658 u32 bits;
656 MISC_REG_AEU_ENABLE4_PXP_0, 659} mcp_attn_ctl_regs[] = {
657 MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 660 { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
658 MISC_REG_AEU_ENABLE4_NIG_1, 661 MISC_AEU_ENABLE_MCP_PRTY_BITS },
659 MISC_REG_AEU_ENABLE4_PXP_1 662 { MISC_REG_AEU_ENABLE4_NIG_0,
663 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
664 { MISC_REG_AEU_ENABLE4_PXP_0,
665 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
666 { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
667 MISC_AEU_ENABLE_MCP_PRTY_BITS },
668 { MISC_REG_AEU_ENABLE4_NIG_1,
669 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
670 { MISC_REG_AEU_ENABLE4_PXP_1,
671 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
660}; 672};
661 673
662static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable) 674static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
@@ -665,14 +677,14 @@ static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
665 u32 reg_val; 677 u32 reg_val;
666 678
667 for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) { 679 for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
668 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]); 680 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);
669 681
670 if (enable) 682 if (enable)
671 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; 683 reg_val |= mcp_attn_ctl_regs[i].bits;
672 else 684 else
673 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; 685 reg_val &= ~mcp_attn_ctl_regs[i].bits;
674 686
675 REG_WR(bp, mcp_attn_ctl_regs[i], reg_val); 687 REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);
676 } 688 }
677} 689}
678 690
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index 236707228f67..7a66bd2b8259 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -4297,65 +4297,60 @@ static void _print_next_block(int idx, const char *blk)
4297 pr_cont("%s%s", idx ? ", " : "", blk); 4297 pr_cont("%s%s", idx ? ", " : "", blk);
4298} 4298}
4299 4299
4300static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, 4300static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4301 int par_num, bool print) 4301 int *par_num, bool print)
4302{ 4302{
4303 int i = 0; 4303 u32 cur_bit;
4304 u32 cur_bit = 0; 4304 bool res;
4305 int i;
4306
4307 res = false;
4308
4305 for (i = 0; sig; i++) { 4309 for (i = 0; sig; i++) {
4306 cur_bit = ((u32)0x1 << i); 4310 cur_bit = (0x1UL << i);
4307 if (sig & cur_bit) { 4311 if (sig & cur_bit) {
4308 switch (cur_bit) { 4312 res |= true; /* Each bit is real error! */
4309 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 4313
4310 if (print) { 4314 if (print) {
4311 _print_next_block(par_num++, "BRB"); 4315 switch (cur_bit) {
4316 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4317 _print_next_block((*par_num)++, "BRB");
4312 _print_parity(bp, 4318 _print_parity(bp,
4313 BRB1_REG_BRB1_PRTY_STS); 4319 BRB1_REG_BRB1_PRTY_STS);
4314 } 4320 break;
4315 break; 4321 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4316 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 4322 _print_next_block((*par_num)++,
4317 if (print) { 4323 "PARSER");
4318 _print_next_block(par_num++, "PARSER");
4319 _print_parity(bp, PRS_REG_PRS_PRTY_STS); 4324 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4320 } 4325 break;
4321 break; 4326 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4322 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 4327 _print_next_block((*par_num)++, "TSDM");
4323 if (print) {
4324 _print_next_block(par_num++, "TSDM");
4325 _print_parity(bp, 4328 _print_parity(bp,
4326 TSDM_REG_TSDM_PRTY_STS); 4329 TSDM_REG_TSDM_PRTY_STS);
4327 } 4330 break;
4328 break; 4331 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4329 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 4332 _print_next_block((*par_num)++,
4330 if (print) {
4331 _print_next_block(par_num++,
4332 "SEARCHER"); 4333 "SEARCHER");
4333 _print_parity(bp, SRC_REG_SRC_PRTY_STS); 4334 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4334 } 4335 break;
4335 break; 4336 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4336 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 4337 _print_next_block((*par_num)++, "TCM");
4337 if (print) { 4338 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4338 _print_next_block(par_num++, "TCM"); 4339 break;
4339 _print_parity(bp, 4340 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4340 TCM_REG_TCM_PRTY_STS); 4341 _print_next_block((*par_num)++,
4341 } 4342 "TSEMI");
4342 break;
4343 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4344 if (print) {
4345 _print_next_block(par_num++, "TSEMI");
4346 _print_parity(bp, 4343 _print_parity(bp,
4347 TSEM_REG_TSEM_PRTY_STS_0); 4344 TSEM_REG_TSEM_PRTY_STS_0);
4348 _print_parity(bp, 4345 _print_parity(bp,
4349 TSEM_REG_TSEM_PRTY_STS_1); 4346 TSEM_REG_TSEM_PRTY_STS_1);
4350 } 4347 break;
4351 break; 4348 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4352 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 4349 _print_next_block((*par_num)++, "XPB");
4353 if (print) {
4354 _print_next_block(par_num++, "XPB");
4355 _print_parity(bp, GRCBASE_XPB + 4350 _print_parity(bp, GRCBASE_XPB +
4356 PB_REG_PB_PRTY_STS); 4351 PB_REG_PB_PRTY_STS);
4352 break;
4357 } 4353 }
4358 break;
4359 } 4354 }
4360 4355
4361 /* Clear the bit */ 4356 /* Clear the bit */
@@ -4363,53 +4358,59 @@ static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4363 } 4358 }
4364 } 4359 }
4365 4360
4366 return par_num; 4361 return res;
4367} 4362}
4368 4363
4369static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, 4364static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4370 int par_num, bool *global, 4365 int *par_num, bool *global,
4371 bool print) 4366 bool print)
4372{ 4367{
4373 int i = 0; 4368 u32 cur_bit;
4374 u32 cur_bit = 0; 4369 bool res;
4370 int i;
4371
4372 res = false;
4373
4375 for (i = 0; sig; i++) { 4374 for (i = 0; sig; i++) {
4376 cur_bit = ((u32)0x1 << i); 4375 cur_bit = (0x1UL << i);
4377 if (sig & cur_bit) { 4376 if (sig & cur_bit) {
4377 res |= true; /* Each bit is real error! */
4378 switch (cur_bit) { 4378 switch (cur_bit) {
4379 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 4379 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4380 if (print) { 4380 if (print) {
4381 _print_next_block(par_num++, "PBF"); 4381 _print_next_block((*par_num)++, "PBF");
4382 _print_parity(bp, PBF_REG_PBF_PRTY_STS); 4382 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4383 } 4383 }
4384 break; 4384 break;
4385 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 4385 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4386 if (print) { 4386 if (print) {
4387 _print_next_block(par_num++, "QM"); 4387 _print_next_block((*par_num)++, "QM");
4388 _print_parity(bp, QM_REG_QM_PRTY_STS); 4388 _print_parity(bp, QM_REG_QM_PRTY_STS);
4389 } 4389 }
4390 break; 4390 break;
4391 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 4391 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4392 if (print) { 4392 if (print) {
4393 _print_next_block(par_num++, "TM"); 4393 _print_next_block((*par_num)++, "TM");
4394 _print_parity(bp, TM_REG_TM_PRTY_STS); 4394 _print_parity(bp, TM_REG_TM_PRTY_STS);
4395 } 4395 }
4396 break; 4396 break;
4397 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 4397 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4398 if (print) { 4398 if (print) {
4399 _print_next_block(par_num++, "XSDM"); 4399 _print_next_block((*par_num)++, "XSDM");
4400 _print_parity(bp, 4400 _print_parity(bp,
4401 XSDM_REG_XSDM_PRTY_STS); 4401 XSDM_REG_XSDM_PRTY_STS);
4402 } 4402 }
4403 break; 4403 break;
4404 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4404 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4405 if (print) { 4405 if (print) {
4406 _print_next_block(par_num++, "XCM"); 4406 _print_next_block((*par_num)++, "XCM");
4407 _print_parity(bp, XCM_REG_XCM_PRTY_STS); 4407 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4408 } 4408 }
4409 break; 4409 break;
4410 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4410 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4411 if (print) { 4411 if (print) {
4412 _print_next_block(par_num++, "XSEMI"); 4412 _print_next_block((*par_num)++,
4413 "XSEMI");
4413 _print_parity(bp, 4414 _print_parity(bp,
4414 XSEM_REG_XSEM_PRTY_STS_0); 4415 XSEM_REG_XSEM_PRTY_STS_0);
4415 _print_parity(bp, 4416 _print_parity(bp,
@@ -4418,7 +4419,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4418 break; 4419 break;
4419 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4420 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4420 if (print) { 4421 if (print) {
4421 _print_next_block(par_num++, 4422 _print_next_block((*par_num)++,
4422 "DOORBELLQ"); 4423 "DOORBELLQ");
4423 _print_parity(bp, 4424 _print_parity(bp,
4424 DORQ_REG_DORQ_PRTY_STS); 4425 DORQ_REG_DORQ_PRTY_STS);
@@ -4426,7 +4427,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4426 break; 4427 break;
4427 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4428 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4428 if (print) { 4429 if (print) {
4429 _print_next_block(par_num++, "NIG"); 4430 _print_next_block((*par_num)++, "NIG");
4430 if (CHIP_IS_E1x(bp)) { 4431 if (CHIP_IS_E1x(bp)) {
4431 _print_parity(bp, 4432 _print_parity(bp,
4432 NIG_REG_NIG_PRTY_STS); 4433 NIG_REG_NIG_PRTY_STS);
@@ -4440,32 +4441,34 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4440 break; 4441 break;
4441 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4442 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4442 if (print) 4443 if (print)
4443 _print_next_block(par_num++, 4444 _print_next_block((*par_num)++,
4444 "VAUX PCI CORE"); 4445 "VAUX PCI CORE");
4445 *global = true; 4446 *global = true;
4446 break; 4447 break;
4447 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4448 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4448 if (print) { 4449 if (print) {
4449 _print_next_block(par_num++, "DEBUG"); 4450 _print_next_block((*par_num)++,
4451 "DEBUG");
4450 _print_parity(bp, DBG_REG_DBG_PRTY_STS); 4452 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4451 } 4453 }
4452 break; 4454 break;
4453 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4455 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4454 if (print) { 4456 if (print) {
4455 _print_next_block(par_num++, "USDM"); 4457 _print_next_block((*par_num)++, "USDM");
4456 _print_parity(bp, 4458 _print_parity(bp,
4457 USDM_REG_USDM_PRTY_STS); 4459 USDM_REG_USDM_PRTY_STS);
4458 } 4460 }
4459 break; 4461 break;
4460 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4462 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4461 if (print) { 4463 if (print) {
4462 _print_next_block(par_num++, "UCM"); 4464 _print_next_block((*par_num)++, "UCM");
4463 _print_parity(bp, UCM_REG_UCM_PRTY_STS); 4465 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4464 } 4466 }
4465 break; 4467 break;
4466 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4468 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4467 if (print) { 4469 if (print) {
4468 _print_next_block(par_num++, "USEMI"); 4470 _print_next_block((*par_num)++,
4471 "USEMI");
4469 _print_parity(bp, 4472 _print_parity(bp,
4470 USEM_REG_USEM_PRTY_STS_0); 4473 USEM_REG_USEM_PRTY_STS_0);
4471 _print_parity(bp, 4474 _print_parity(bp,
@@ -4474,21 +4477,21 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4474 break; 4477 break;
4475 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4478 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4476 if (print) { 4479 if (print) {
4477 _print_next_block(par_num++, "UPB"); 4480 _print_next_block((*par_num)++, "UPB");
4478 _print_parity(bp, GRCBASE_UPB + 4481 _print_parity(bp, GRCBASE_UPB +
4479 PB_REG_PB_PRTY_STS); 4482 PB_REG_PB_PRTY_STS);
4480 } 4483 }
4481 break; 4484 break;
4482 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4485 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4483 if (print) { 4486 if (print) {
4484 _print_next_block(par_num++, "CSDM"); 4487 _print_next_block((*par_num)++, "CSDM");
4485 _print_parity(bp, 4488 _print_parity(bp,
4486 CSDM_REG_CSDM_PRTY_STS); 4489 CSDM_REG_CSDM_PRTY_STS);
4487 } 4490 }
4488 break; 4491 break;
4489 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4492 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4490 if (print) { 4493 if (print) {
4491 _print_next_block(par_num++, "CCM"); 4494 _print_next_block((*par_num)++, "CCM");
4492 _print_parity(bp, CCM_REG_CCM_PRTY_STS); 4495 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4493 } 4496 }
4494 break; 4497 break;
@@ -4499,80 +4502,73 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4499 } 4502 }
4500 } 4503 }
4501 4504
4502 return par_num; 4505 return res;
4503} 4506}
4504 4507
4505static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, 4508static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4506 int par_num, bool print) 4509 int *par_num, bool print)
4507{ 4510{
4508 int i = 0; 4511 u32 cur_bit;
4509 u32 cur_bit = 0; 4512 bool res;
4513 int i;
4514
4515 res = false;
4516
4510 for (i = 0; sig; i++) { 4517 for (i = 0; sig; i++) {
4511 cur_bit = ((u32)0x1 << i); 4518 cur_bit = (0x1UL << i);
4512 if (sig & cur_bit) { 4519 if (sig & cur_bit) {
4513 switch (cur_bit) { 4520 res |= true; /* Each bit is real error! */
4514 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4521 if (print) {
4515 if (print) { 4522 switch (cur_bit) {
4516 _print_next_block(par_num++, "CSEMI"); 4523 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4524 _print_next_block((*par_num)++,
4525 "CSEMI");
4517 _print_parity(bp, 4526 _print_parity(bp,
4518 CSEM_REG_CSEM_PRTY_STS_0); 4527 CSEM_REG_CSEM_PRTY_STS_0);
4519 _print_parity(bp, 4528 _print_parity(bp,
4520 CSEM_REG_CSEM_PRTY_STS_1); 4529 CSEM_REG_CSEM_PRTY_STS_1);
4521 } 4530 break;
4522 break; 4531 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4523 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4532 _print_next_block((*par_num)++, "PXP");
4524 if (print) {
4525 _print_next_block(par_num++, "PXP");
4526 _print_parity(bp, PXP_REG_PXP_PRTY_STS); 4533 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4527 _print_parity(bp, 4534 _print_parity(bp,
4528 PXP2_REG_PXP2_PRTY_STS_0); 4535 PXP2_REG_PXP2_PRTY_STS_0);
4529 _print_parity(bp, 4536 _print_parity(bp,
4530 PXP2_REG_PXP2_PRTY_STS_1); 4537 PXP2_REG_PXP2_PRTY_STS_1);
4531 } 4538 break;
4532 break; 4539 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4533 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4540 _print_next_block((*par_num)++,
4534 if (print) 4541 "PXPPCICLOCKCLIENT");
4535 _print_next_block(par_num++, 4542 break;
4536 "PXPPCICLOCKCLIENT"); 4543 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4537 break; 4544 _print_next_block((*par_num)++, "CFC");
4538 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4539 if (print) {
4540 _print_next_block(par_num++, "CFC");
4541 _print_parity(bp, 4545 _print_parity(bp,
4542 CFC_REG_CFC_PRTY_STS); 4546 CFC_REG_CFC_PRTY_STS);
4543 } 4547 break;
4544 break; 4548 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4545 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4549 _print_next_block((*par_num)++, "CDU");
4546 if (print) {
4547 _print_next_block(par_num++, "CDU");
4548 _print_parity(bp, CDU_REG_CDU_PRTY_STS); 4550 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4549 } 4551 break;
4550 break; 4552 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4551 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4553 _print_next_block((*par_num)++, "DMAE");
4552 if (print) {
4553 _print_next_block(par_num++, "DMAE");
4554 _print_parity(bp, 4554 _print_parity(bp,
4555 DMAE_REG_DMAE_PRTY_STS); 4555 DMAE_REG_DMAE_PRTY_STS);
4556 } 4556 break;
4557 break; 4557 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4558 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4558 _print_next_block((*par_num)++, "IGU");
4559 if (print) {
4560 _print_next_block(par_num++, "IGU");
4561 if (CHIP_IS_E1x(bp)) 4559 if (CHIP_IS_E1x(bp))
4562 _print_parity(bp, 4560 _print_parity(bp,
4563 HC_REG_HC_PRTY_STS); 4561 HC_REG_HC_PRTY_STS);
4564 else 4562 else
4565 _print_parity(bp, 4563 _print_parity(bp,
4566 IGU_REG_IGU_PRTY_STS); 4564 IGU_REG_IGU_PRTY_STS);
4567 } 4565 break;
4568 break; 4566 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4569 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4567 _print_next_block((*par_num)++, "MISC");
4570 if (print) {
4571 _print_next_block(par_num++, "MISC");
4572 _print_parity(bp, 4568 _print_parity(bp,
4573 MISC_REG_MISC_PRTY_STS); 4569 MISC_REG_MISC_PRTY_STS);
4570 break;
4574 } 4571 }
4575 break;
4576 } 4572 }
4577 4573
4578 /* Clear the bit */ 4574 /* Clear the bit */
@@ -4580,40 +4576,49 @@ static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4580 } 4576 }
4581 } 4577 }
4582 4578
4583 return par_num; 4579 return res;
4584} 4580}
4585 4581
4586static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4582static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4587 bool *global, bool print) 4583 int *par_num, bool *global,
4584 bool print)
4588{ 4585{
4589 int i = 0; 4586 bool res = false;
4590 u32 cur_bit = 0; 4587 u32 cur_bit;
4588 int i;
4589
4591 for (i = 0; sig; i++) { 4590 for (i = 0; sig; i++) {
4592 cur_bit = ((u32)0x1 << i); 4591 cur_bit = (0x1UL << i);
4593 if (sig & cur_bit) { 4592 if (sig & cur_bit) {
4594 switch (cur_bit) { 4593 switch (cur_bit) {
4595 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4594 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4596 if (print) 4595 if (print)
4597 _print_next_block(par_num++, "MCP ROM"); 4596 _print_next_block((*par_num)++,
4597 "MCP ROM");
4598 *global = true; 4598 *global = true;
4599 res |= true;
4599 break; 4600 break;
4600 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4601 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4601 if (print) 4602 if (print)
4602 _print_next_block(par_num++, 4603 _print_next_block((*par_num)++,
4603 "MCP UMP RX"); 4604 "MCP UMP RX");
4604 *global = true; 4605 *global = true;
4606 res |= true;
4605 break; 4607 break;
4606 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4608 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4607 if (print) 4609 if (print)
4608 _print_next_block(par_num++, 4610 _print_next_block((*par_num)++,
4609 "MCP UMP TX"); 4611 "MCP UMP TX");
4610 *global = true; 4612 *global = true;
4613 res |= true;
4611 break; 4614 break;
4612 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4615 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4613 if (print) 4616 if (print)
4614 _print_next_block(par_num++, 4617 _print_next_block((*par_num)++,
4615 "MCP SCPAD"); 4618 "MCP SCPAD");
4616 *global = true; 4619 /* clear latched SCPAD PATIRY from MCP */
4620 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4621 1UL << 10);
4617 break; 4622 break;
4618 } 4623 }
4619 4624
@@ -4622,45 +4627,50 @@ static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4622 } 4627 }
4623 } 4628 }
4624 4629
4625 return par_num; 4630 return res;
4626} 4631}
4627 4632
4628static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, 4633static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4629 int par_num, bool print) 4634 int *par_num, bool print)
4630{ 4635{
4631 int i = 0; 4636 u32 cur_bit;
4632 u32 cur_bit = 0; 4637 bool res;
4638 int i;
4639
4640 res = false;
4641
4633 for (i = 0; sig; i++) { 4642 for (i = 0; sig; i++) {
4634 cur_bit = ((u32)0x1 << i); 4643 cur_bit = (0x1UL << i);
4635 if (sig & cur_bit) { 4644 if (sig & cur_bit) {
4636 switch (cur_bit) { 4645 res |= true; /* Each bit is real error! */
4637 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4646 if (print) {
4638 if (print) { 4647 switch (cur_bit) {
4639 _print_next_block(par_num++, "PGLUE_B"); 4648 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4649 _print_next_block((*par_num)++,
4650 "PGLUE_B");
4640 _print_parity(bp, 4651 _print_parity(bp,
4641 PGLUE_B_REG_PGLUE_B_PRTY_STS); 4652 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4642 } 4653 break;
4643 break; 4654 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4644 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4655 _print_next_block((*par_num)++, "ATC");
4645 if (print) {
4646 _print_next_block(par_num++, "ATC");
4647 _print_parity(bp, 4656 _print_parity(bp,
4648 ATC_REG_ATC_PRTY_STS); 4657 ATC_REG_ATC_PRTY_STS);
4658 break;
4649 } 4659 }
4650 break;
4651 } 4660 }
4652
4653 /* Clear the bit */ 4661 /* Clear the bit */
4654 sig &= ~cur_bit; 4662 sig &= ~cur_bit;
4655 } 4663 }
4656 } 4664 }
4657 4665
4658 return par_num; 4666 return res;
4659} 4667}
4660 4668
4661static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4669static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4662 u32 *sig) 4670 u32 *sig)
4663{ 4671{
4672 bool res = false;
4673
4664 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4674 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4665 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4675 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4666 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4676 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
@@ -4677,23 +4687,22 @@ static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4677 if (print) 4687 if (print)
4678 netdev_err(bp->dev, 4688 netdev_err(bp->dev,
4679 "Parity errors detected in blocks: "); 4689 "Parity errors detected in blocks: ");
4680 par_num = bnx2x_check_blocks_with_parity0(bp, 4690 res |= bnx2x_check_blocks_with_parity0(bp,
4681 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4691 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4682 par_num = bnx2x_check_blocks_with_parity1(bp, 4692 res |= bnx2x_check_blocks_with_parity1(bp,
4683 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4693 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4684 par_num = bnx2x_check_blocks_with_parity2(bp, 4694 res |= bnx2x_check_blocks_with_parity2(bp,
4685 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4695 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4686 par_num = bnx2x_check_blocks_with_parity3( 4696 res |= bnx2x_check_blocks_with_parity3(bp,
4687 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4697 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4688 par_num = bnx2x_check_blocks_with_parity4(bp, 4698 res |= bnx2x_check_blocks_with_parity4(bp,
4689 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4699 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4690 4700
4691 if (print) 4701 if (print)
4692 pr_cont("\n"); 4702 pr_cont("\n");
4703 }
4693 4704
4694 return true; 4705 return res;
4695 } else
4696 return false;
4697} 4706}
4698 4707
4699/** 4708/**
@@ -7143,7 +7152,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
7143 int port = BP_PORT(bp); 7152 int port = BP_PORT(bp);
7144 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 7153 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7145 u32 low, high; 7154 u32 low, high;
7146 u32 val; 7155 u32 val, reg;
7147 7156
7148 DP(NETIF_MSG_HW, "starting port init port %d\n", port); 7157 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7149 7158
@@ -7288,6 +7297,17 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
7288 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 7297 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7289 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 7298 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7290 7299
7300 /* SCPAD_PARITY should NOT trigger close the gates */
7301 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7302 REG_WR(bp, reg,
7303 REG_RD(bp, reg) &
7304 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7305
7306 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7307 REG_WR(bp, reg,
7308 REG_RD(bp, reg) &
7309 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7310
7291 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 7311 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7292 7312
7293 if (!CHIP_IS_E1x(bp)) { 7313 if (!CHIP_IS_E1x(bp)) {