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authorOlof Johansson <olof@lixom.net>2014-07-19 01:16:15 -0400
committerOlof Johansson <olof@lixom.net>2014-07-19 01:16:48 -0400
commit412a9bbd1291e6ef0f71bfdf9fbffaac349d5130 (patch)
treed0a0a1c9a35360a61a352683f13bf2b946ec2a80
parentc6ffdc07411d982972fce6b4bfbd1c8b96990a48 (diff)
parent3c9464ed75d6c15ee864da6d8f6a4cd3b0f2c934 (diff)
Merge tag 'omap-for-v3.17/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "omap dts changes for v3.17 merge window, part1" from Tony Lindgren: First set of .dts changes for omaps for v3.17 merge window: - Enable irqchip crossbar interrupt mapping. These changes are based on an immutable irqchip branch set up by Jason Cooper to make it easier to merge the related .dts changes. - Removal of omap2 related static clock data that now comes from device tree. - Enabling of PHY regulators for various omaps - Enabling of PCIe for dra7 - Add support for am437x starterkit - Enable audio for for omap5 - Enable display and am335x-evmsk * tag 'omap-for-v3.17/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (43 commits) ARM: DTS: omap5-uevm: Enable basic audio (McPDM <-> twl6040) ARM: DTS: omap5-uevm: Add node for twl6040 audio codec ARM: DTS: omap5-uevm: Enable palmas clk32kgaudio clock ARM: dts: dra7: Add dt data for PCIe controller ARM: dts: dra7: Add dt data for PCIe PHY ARM: dts: dra7: Add dt data for PCIe PHY control module ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock ARM: dts: dra7-evm: Add regulator information to USB2 PHYs ARM: omap2plus_defconfig: enable TPS65218 configs ARM: dts: AM437x: Add TPS65218 device tree nodes ARM: dts: AM437x: Fix i2c nodes indentation ARM: dts: AM43x: Add TPS65218 device tree nodes ARM: dts: Add devicetree for Gumstix Pepper board ARM: dts: dra7: add crossbar device binding ARM: dts: dra7: add routable-irqs property for gic node ARM: OMAP24xx: clock: remove legacy clock data ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/omap/crossbar.txt36
-rw-r--r--Documentation/devicetree/bindings/arm/omap/omap.txt3
-rw-r--r--Documentation/devicetree/bindings/arm/omap/prcm.txt65
-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts105
-rw-r--r--arch/arm/boot/dts/am335x-pepper.dts653
-rw-r--r--arch/arm/boot/dts/am4372.dtsi8
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts71
-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts613
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts59
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts8
-rw-r--r--arch/arm/boot/dts/dra7.dtsi265
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi39
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi3
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi3
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts68
-rw-r--r--arch/arm/configs/omap2plus_defconfig2
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/cclock2420_data.c1931
-rw-r--r--arch/arm/mach-omap2/cclock2430_data.c2048
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_osc.c69
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_sys.c47
-rw-r--r--arch/arm/mach-omap2/clock.c21
-rw-r--r--arch/arm/mach-omap2/clock.h3
-rw-r--r--arch/arm/mach-omap2/clock2xxx.h2
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h1
-rw-r--r--arch/arm/mach-omap2/io.c7
-rw-r--r--arch/arm/mach-omap2/pm24xx.c4
-rw-r--r--arch/arm/mach-omap2/prm_common.c2
-rw-r--r--drivers/irqchip/irq-crossbar.c168
30 files changed, 2084 insertions, 4230 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index fb88585cfb93..4139db353d0a 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -10,6 +10,7 @@ Required properties:
10- compatible : Should be "ti,irq-crossbar" 10- compatible : Should be "ti,irq-crossbar"
11- reg: Base address and the size of the crossbar registers. 11- reg: Base address and the size of the crossbar registers.
12- ti,max-irqs: Total number of irqs available at the interrupt controller. 12- ti,max-irqs: Total number of irqs available at the interrupt controller.
13- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
13- ti,reg-size: Size of a individual register in bytes. Every individual 14- ti,reg-size: Size of a individual register in bytes. Every individual
14 register is assumed to be of same size. Valid sizes are 1, 2, 4. 15 register is assumed to be of same size. Valid sizes are 1, 2, 4.
15- ti,irqs-reserved: List of the reserved irq lines that are not muxed using 16- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
@@ -17,11 +18,46 @@ Required properties:
17 so crossbar bar driver should not consider them as free 18 so crossbar bar driver should not consider them as free
18 lines. 19 lines.
19 20
21Optional properties:
22- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
23 SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
24 crossbar. These irqs have a crossbar register, but still cannot be used.
25
26- ti,irqs-safe-map: integer which maps to a safe configuration to use
27 when the interrupt controller irq is unused (when not provided, default is 0)
28
20Examples: 29Examples:
21 crossbar_mpu: @4a020000 { 30 crossbar_mpu: @4a020000 {
22 compatible = "ti,irq-crossbar"; 31 compatible = "ti,irq-crossbar";
23 reg = <0x4a002a48 0x130>; 32 reg = <0x4a002a48 0x130>;
24 ti,max-irqs = <160>; 33 ti,max-irqs = <160>;
34 ti,max-crossbar-sources = <400>;
25 ti,reg-size = <2>; 35 ti,reg-size = <2>;
26 ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; 36 ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
37 ti,irqs-skip = <10 133 139 140>;
27 }; 38 };
39
40Consumer:
41========
42See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
43Documentation/devicetree/bindings/arm/gic.txt for further details.
44
45An interrupt consumer on an SoC using crossbar will use:
46 interrupts = <GIC_SPI request_number interrupt_level>
47When the request number is between 0 to that described by
48"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
49request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
50quirky hardware mapping direct to GIC.
51
52Example:
53 device_x@0x4a023000 {
54 /* Crossbar 8 used */
55 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
56 ...
57 };
58
59 device_y@0x4a033000 {
60 /* Direct mapped GIC SPI 1 used */
61 interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
62 ...
63 };
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index d22b216f5d23..0edc90305dfe 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -129,6 +129,9 @@ Boards:
129- AM437x GP EVM 129- AM437x GP EVM
130 compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" 130 compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
131 131
132- AM437x SK EVM: AM437x StarterKit Evaluation Module
133 compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
134
132- DRA742 EVM: Software Development Board for DRA742 135- DRA742 EVM: Software Development Board for DRA742
133 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" 136 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
134 137
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt
new file mode 100644
index 000000000000..79074dac684a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -0,0 +1,65 @@
1OMAP PRCM bindings
2
3Power Reset and Clock Manager lists the device clocks and clockdomains under
4a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it,
5each describing one module and the clock hierarchy under it. see [1] for
6documentation about the individual clock/clockdomain nodes.
7
8[1] Documentation/devicetree/bindings/clock/ti/*
9
10Required properties:
11- compatible: Must be one of:
12 "ti,am3-prcm"
13 "ti,am3-scrm"
14 "ti,am4-prcm"
15 "ti,am4-scrm"
16 "ti,omap2-prcm"
17 "ti,omap2-scrm"
18 "ti,omap3-prm"
19 "ti,omap3-cm"
20 "ti,omap3-scrm"
21 "ti,omap4-cm1"
22 "ti,omap4-prm"
23 "ti,omap4-cm2"
24 "ti,omap4-scrm"
25 "ti,omap5-prm"
26 "ti,omap5-cm-core-aon"
27 "ti,omap5-scrm"
28 "ti,omap5-cm-core"
29 "ti,dra7-prm"
30 "ti,dra7-cm-core-aon"
31 "ti,dra7-cm-core"
32- reg: Contains PRCM module register address range
33 (base address and length)
34- clocks: clocks for this module
35- clockdomains: clockdomains for this module
36
37Example:
38
39cm: cm@48004000 {
40 compatible = "ti,omap3-cm";
41 reg = <0x48004000 0x4000>;
42
43 cm_clocks: clocks {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 };
47
48 cm_clockdomains: clockdomains {
49 };
50}
51
52&cm_clocks {
53 omap2_32k_fck: omap_32k_fck {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
57 };
58};
59
60&cm_clockdomains {
61 core_l3_clkdm: core_l3_clkdm {
62 compatible = "ti,clockdomain";
63 clocks = <&sdrc_ick>;
64 };
65};
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index adb5ed9e269e..df4c195f3d4e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -291,7 +291,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
291 am335x-boneblack.dtb \ 291 am335x-boneblack.dtb \
292 am335x-evm.dtb \ 292 am335x-evm.dtb \
293 am335x-evmsk.dtb \ 293 am335x-evmsk.dtb \
294 am335x-nano.dtb 294 am335x-nano.dtb \
295 am335x-pepper.dtb
295dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ 296dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
296 omap4-panda.dtb \ 297 omap4-panda.dtb \
297 omap4-panda-a4.dtb \ 298 omap4-panda-a4.dtb \
@@ -301,6 +302,7 @@ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
301 omap4-var-dvk-om44.dtb \ 302 omap4-var-dvk-om44.dtb \
302 omap4-var-stk-om44.dtb 303 omap4-var-stk-om44.dtb
303dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ 304dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \
305 am437x-sk-evm.dtb \
304 am437x-gp-evm.dtb 306 am437x-gp-evm.dtb
305dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ 307dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
306 omap5-sbc-t54.dtb \ 308 omap5-sbc-t54.dtb \
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index ab9a34ce524c..59766e2c2980 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -149,12 +149,113 @@
149 "Headphone Jack", "HPLOUT", 149 "Headphone Jack", "HPLOUT",
150 "Headphone Jack", "HPROUT"; 150 "Headphone Jack", "HPROUT";
151 }; 151 };
152
153 panel {
154 compatible = "ti,tilcdc,panel";
155 pinctrl-names = "default", "sleep";
156 pinctrl-0 = <&lcd_pins_default>;
157 pinctrl-1 = <&lcd_pins_sleep>;
158 status = "okay";
159 panel-info {
160 ac-bias = <255>;
161 ac-bias-intrpt = <0>;
162 dma-burst-sz = <16>;
163 bpp = <32>;
164 fdd = <0x80>;
165 sync-edge = <0>;
166 sync-ctrl = <1>;
167 raster-order = <0>;
168 fifo-th = <0>;
169 };
170 display-timings {
171 480x272 {
172 hactive = <480>;
173 vactive = <272>;
174 hback-porch = <43>;
175 hfront-porch = <8>;
176 hsync-len = <4>;
177 vback-porch = <12>;
178 vfront-porch = <4>;
179 vsync-len = <10>;
180 clock-frequency = <9000000>;
181 hsync-active = <0>;
182 vsync-active = <0>;
183 };
184 };
185 };
152}; 186};
153 187
154&am33xx_pinmux { 188&am33xx_pinmux {
155 pinctrl-names = "default"; 189 pinctrl-names = "default";
156 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; 190 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
157 191
192 lcd_pins_default: lcd_pins_default {
193 pinctrl-single,pins = <
194 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
195 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
196 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
197 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
198 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
199 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
200 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
201 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
202 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
203 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
204 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
205 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
206 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
207 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
208 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
209 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
210 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
211 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
212 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
213 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
214 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
215 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
216 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
217 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
218 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
219 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
220 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
221 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
222 >;
223 };
224
225 lcd_pins_sleep: lcd_pins_sleep {
226 pinctrl-single,pins = <
227 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */
228 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */
229 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */
230 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */
231 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */
232 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */
233 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */
234 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */
235 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
236 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
237 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
238 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
239 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
240 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
241 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
242 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
243 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
244 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
245 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
246 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
247 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
248 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
249 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
250 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
251 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */
252 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
253 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
254 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
255 >;
256 };
257
258
158 user_leds_s0: user_leds_s0 { 259 user_leds_s0: user_leds_s0 {
159 pinctrl-single,pins = < 260 pinctrl-single,pins = <
160 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ 261 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
@@ -573,3 +674,7 @@
573 ti,wire-config = <0x00 0x11 0x22 0x33>; 674 ti,wire-config = <0x00 0x11 0x22 0x33>;
574 }; 675 };
575}; 676};
677
678&lcdc {
679 status = "okay";
680};
diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts
new file mode 100644
index 000000000000..0d35ab64641c
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-pepper.dts
@@ -0,0 +1,653 @@
1/*
2 * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include <dt-bindings/input/input.h>
11#include "am33xx.dtsi"
12
13/ {
14 model = "Gumstix Pepper";
15 compatible = "gumstix,am335x-pepper", "ti,am33xx";
16
17 cpus {
18 cpu@0 {
19 cpu0-supply = <&dcdc3_reg>;
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x80000000 0x20000000>; /* 512 MB */
26 };
27
28 buttons: user_buttons {
29 compatible = "gpio-keys";
30 };
31
32 leds: user_leds {
33 compatible = "gpio-leds";
34 };
35
36 panel: lcd_panel {
37 compatible = "ti,tilcdc,panel";
38 };
39
40 sound: sound_iface {
41 compatible = "ti,da830-evm-audio";
42 };
43
44 vbat: fixedregulator@0 {
45 compatible = "regulator-fixed";
46 };
47
48 v3v3c_reg: fixedregulator@1 {
49 compatible = "regulator-fixed";
50 };
51
52 vdd5_reg: fixedregulator@2 {
53 compatible = "regulator-fixed";
54 };
55};
56
57/* I2C Busses */
58&i2c0 {
59 status = "okay";
60 pinctrl-names = "default";
61 pinctrl-0 = <&i2c0_pins>;
62
63 clock-frequency = <400000>;
64
65 tps: tps@24 {
66 reg = <0x24>;
67 };
68
69 eeprom: eeprom@50 {
70 compatible = "at,24c256";
71 reg = <0x50>;
72 };
73
74 audio_codec: tlv320aic3106@1b {
75 compatible = "ti,tlv320aic3106";
76 reg = <0x1b>;
77 };
78
79 accel: lis331dlh@1d {
80 compatible = "st,lis3lv02d";
81 reg = <0x1d>;
82 };
83};
84
85&i2c1 {
86 status = "okay";
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2c1_pins>;
89 clock-frequency = <400000>;
90};
91
92&am33xx_pinmux {
93 i2c0_pins: pinmux_i2c0 {
94 pinctrl-single,pins = <
95 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
96 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
97 >;
98 };
99 i2c1_pins: pinmux_i2c1 {
100 pinctrl-single,pins = <
101 0x10C (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */
102 0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */
103 >;
104 };
105};
106
107/* Accelerometer */
108&accel {
109 pinctrl-names = "default";
110 pinctrl-0 = <&accel_pins>;
111
112 Vdd-supply = <&ldo3_reg>;
113 Vdd_IO-supply = <&ldo3_reg>;
114 st,irq1-click;
115 st,wakeup-x-lo;
116 st,wakeup-x-hi;
117 st,wakeup-y-lo;
118 st,wakeup-y-hi;
119 st,wakeup-z-lo;
120 st,wakeup-z-hi;
121 st,min-limit-x = <92>;
122 st,max-limit-x = <14>;
123 st,min-limit-y = <14>;
124 st,max-limit-y = <92>;
125 st,min-limit-z = <92>;
126 st,max-limit-z = <14>;
127};
128
129&am33xx_pinmux {
130 accel_pins: pinmux_accel {
131 pinctrl-single,pins = <
132 0x98 (PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */
133 >;
134 };
135};
136
137/* Audio */
138&audio_codec {
139 status = "okay";
140
141 gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>;
142 AVDD-supply = <&ldo3_reg>;
143 IOVDD-supply = <&ldo3_reg>;
144 DRVDD-supply = <&ldo3_reg>;
145 DVDD-supply = <&dcdc1_reg>;
146};
147
148&sound {
149 ti,model = "AM335x-EVM";
150 ti,audio-codec = <&audio_codec>;
151 ti,mcasp-controller = <&mcasp0>;
152 ti,codec-clock-rate = <12000000>;
153 ti,audio-routing =
154 "Headphone Jack", "HPLOUT",
155 "Headphone Jack", "HPROUT",
156 "LINE1L", "Line In";
157};
158
159&mcasp0 {
160 status = "okay";
161 pinctrl-names = "default";
162 pinctrl-0 = <&audio_pins>;
163
164 op-mode = <0>; /* MCASP_ISS_MODE */
165 tdm-slots = <2>;
166 serial-dir = <
167 1 2 0 0
168 0 0 0 0
169 0 0 0 0
170 0 0 0 0
171 >;
172 tx-num-evt = <1>;
173 rx-num-evt = <1>;
174};
175
176&am33xx_pinmux {
177 audio_pins: pinmux_audio {
178 pinctrl-single,pins = <
179 0x1AC (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
180 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
181 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
182 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
183 0x1A8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
184 0x40 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */
185 >;
186 };
187};
188
189/* Display: 24-bit LCD Screen */
190&panel {
191 status = "okay";
192 pinctrl-names = "default";
193 pinctrl-0 = <&lcd_pins>;
194 panel-info {
195 ac-bias = <255>;
196 ac-bias-intrpt = <0>;
197 dma-burst-sz = <16>;
198 bpp = <32>;
199 fdd = <0x80>;
200 sync-edge = <0>;
201 sync-ctrl = <1>;
202 raster-order = <0>;
203 fifo-th = <0>;
204 };
205 display-timings {
206 native-mode = <&timing0>;
207 timing0: 480x272 {
208 clock-frequency = <18400000>;
209 hactive = <480>;
210 vactive = <272>;
211 hfront-porch = <8>;
212 hback-porch = <4>;
213 hsync-len = <41>;
214 vfront-porch = <4>;
215 vback-porch = <2>;
216 vsync-len = <10>;
217 hsync-active = <1>;
218 vsync-active = <1>;
219 };
220 };
221};
222
223&lcdc {
224 status = "okay";
225};
226
227&am33xx_pinmux {
228 lcd_pins: pinmux_lcd {
229 pinctrl-single,pins = <
230 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
231 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
232 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
233 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
234 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
235 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
236 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
237 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
238 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
239 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
240 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
241 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
242 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
243 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
244 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
245 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
246 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */
247 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */
248 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */
249 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */
250 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */
251 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */
252 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */
253 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */
254 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
255 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
256 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
257 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
258 /* Display Enable */
259 0x6c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */
260 >;
261 };
262};
263
264/* Ethernet */
265&cpsw_emac0 {
266 status = "okay";
267 phy_id = <&davinci_mdio>, <0>;
268 phy-mode = "rgmii";
269};
270
271&cpsw_emac1 {
272 status = "okay";
273 phy_id = <&davinci_mdio>, <1>;
274 phy-mode = "rgmii";
275};
276
277&davinci_mdio {
278 status = "okay";
279 pinctrl-names = "default";
280 pinctrl-0 = <&mdio_pins>;
281};
282
283&mac {
284 status = "okay";
285 pinctrl-names = "default";
286 pinctrl-0 = <&ethernet_pins>;
287};
288
289
290&am33xx_pinmux {
291 ethernet_pins: pinmux_ethernet {
292 pinctrl-single,pins = <
293 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
294 0x118 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
295 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
296 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
297 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
298 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
299 0x12c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
300 0x130 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
301 0x134 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */
302 0x138 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */
303 0x13c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
304 0x140 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
305 /* ethernet interrupt */
306 0x144 (PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */
307 /* ethernet PHY nReset */
308 0x108 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */
309 >;
310 };
311
312 mdio_pins: pinmux_mdio {
313 pinctrl-single,pins = <
314 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
315 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
316 >;
317 };
318};
319
320/* MMC */
321&mmc1 {
322 /* Bootable SD card slot */
323 status = "okay";
324 vmmc-supply = <&ldo3_reg>;
325 bus-width = <4>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&sd_pins>;
328 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
329};
330
331&mmc2 {
332 /* eMMC (not populated) on MMC #2 */
333 status = "disabled";
334 pinctrl-names = "default";
335 pinctrl-0 = <&emmc_pins>;
336 vmmc-supply = <&ldo3_reg>;
337 bus-width = <8>;
338 ti,non-removable;
339};
340
341&edma {
342 /* Map eDMA MMC2 Events from Crossbar */
343 ti,edma-xbar-event-map = /bits/ 16 <1 12
344 2 13>;
345};
346
347
348&mmc3 {
349 /* Wifi & Bluetooth on MMC #3 */
350 status = "okay";
351 pinctrl-names = "default";
352 pinctrl-0 = <&wireless_pins>;
353 vmmmc-supply = <&v3v3c_reg>;
354 bus-width = <4>;
355 ti,non-removable;
356 dmas = <&edma 12
357 &edma 13>;
358 dma-names = "tx", "rx";
359};
360
361
362&am33xx_pinmux {
363 sd_pins: pinmux_sd_card {
364 pinctrl-single,pins = <
365 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
366 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
367 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
368 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
369 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
370 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
371 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
372 >;
373 };
374 emmc_pins: pinmux_emmc {
375 pinctrl-single,pins = <
376 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
377 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
378 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
379 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
380 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
381 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
382 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
383 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
384 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
385 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
386 /* EMMC nReset */
387 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
388 >;
389 };
390 wireless_pins: pinmux_wireless {
391 pinctrl-single,pins = <
392 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
393 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
394 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
395 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */
396 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
397 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */
398 /* WLAN nReset */
399 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
400 /* WLAN nPower down */
401 0x70 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
402 /* 32kHz Clock */
403 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
404 >;
405 };
406};
407
408/* Power */
409&vbat {
410 regulator-name = "vbat";
411 regulator-min-microvolt = <5000000>;
412 regulator-max-microvolt = <5000000>;
413};
414
415&v3v3c_reg {
416 regulator-name = "v3v3c_reg";
417 regulator-min-microvolt = <3300000>;
418 regulator-max-microvolt = <3300000>;
419 vin-supply = <&vbat>;
420};
421
422&vdd5_reg {
423 regulator-name = "vdd5_reg";
424 regulator-min-microvolt = <5000000>;
425 regulator-max-microvolt = <5000000>;
426 vin-supply = <&vbat>;
427};
428
429/include/ "tps65217.dtsi"
430
431&tps {
432 backlight {
433 isel = <1>; /* ISET1 */
434 fdim = <200>; /* TPS65217_BL_FDIM_200HZ */
435 default-brightness = <80>;
436 };
437
438 regulators {
439 dcdc1_reg: regulator@0 {
440 /* VDD_1V8 system supply */
441 };
442
443 dcdc2_reg: regulator@1 {
444 /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */
445 regulator-name = "vdd_core";
446 regulator-min-microvolt = <925000>;
447 regulator-max-microvolt = <1325000>;
448 regulator-boot-on;
449 };
450
451 dcdc3_reg: regulator@2 {
452 /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */
453 regulator-name = "vdd_mpu";
454 regulator-min-microvolt = <925000>;
455 regulator-max-microvolt = <1150000>;
456 regulator-boot-on;
457 };
458
459 ldo1_reg: regulator@3 {
460 /* VRTC 1.8V always-on supply */
461 regulator-always-on;
462 };
463
464 ldo2_reg: regulator@4 {
465 /* 3.3V rail */
466 };
467
468 ldo3_reg: regulator@5 {
469 /* VDD_3V3A 3.3V rail */
470 regulator-min-microvolt = <3300000>;
471 regulator-max-microvolt = <3300000>;
472 };
473
474 ldo4_reg: regulator@6 {
475 /* VDD_3V3B 3.3V rail */
476 };
477 };
478};
479
480/* SPI Busses */
481&spi0 {
482 status = "okay";
483 pinctrl-names = "default";
484 pinctrl-0 = <&spi0_pins>;
485};
486
487&am33xx_pinmux {
488 spi0_pins: pinmux_spi0 {
489 pinctrl-single,pins = <
490 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
491 0x15C (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
492 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
493 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
494 >;
495 };
496};
497
498/* Touch Screen */
499&tscadc {
500 status = "okay";
501 tsc {
502 ti,wires = <4>;
503 ti,x-plate-resistance = <200>;
504 ti,coordinate-readouts = <5>;
505 ti,wire-config = <0x00 0x11 0x22 0x33>;
506 };
507
508 adc {
509 ti,adc-channels = <4 5 6 7>;
510 };
511};
512
513/* UARTs */
514&uart0 {
515 /* Serial Console */
516 status = "okay";
517 pinctrl-names = "default";
518 pinctrl-0 = <&uart0_pins>;
519};
520
521&uart1 {
522 /* Broken out to J6 header */
523 status = "okay";
524 pinctrl-names = "default";
525 pinctrl-0 = <&uart1_pins>;
526};
527
528&am33xx_pinmux {
529 uart0_pins: pinmux_uart0 {
530 pinctrl-single,pins = <
531 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
532 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
533 >;
534 };
535 uart1_pins: pinmux_uart1 {
536 pinctrl-single,pins = <
537 0x178 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
538 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
539 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
540 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
541 >;
542 };
543};
544
545/* USB */
546&usb {
547 status = "okay";
548
549 pinctrl-names = "default";
550 pinctrl-0 = <&usb_pins>;
551};
552
553&usb_ctrl_mod {
554 status = "okay";
555};
556
557&usb0_phy {
558 status = "okay";
559};
560
561&usb1_phy {
562 status = "okay";
563};
564
565&usb0 {
566 status = "okay";
567 dr_mode = "host";
568};
569
570&usb1 {
571 status = "okay";
572 dr_mode = "host";
573};
574
575&cppi41dma {
576 status = "okay";
577};
578
579&am33xx_pinmux {
580 usb_pins: pinmux_usb {
581 pinctrl-single,pins = <
582 /* USB0 Over-Current (active low) */
583 0x64 (PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */
584 /* USB1 Over-Current (active low) */
585 0x68 (PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */
586 >;
587 };
588};
589
590/* User IO */
591&leds {
592 pinctrl-names = "default";
593 pinctrl-0 = <&user_leds_pins>;
594
595 led@0 {
596 label = "pepper:user0:blue";
597 gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
598 linux,default-trigger = "none";
599 default-state = "off";
600 };
601
602 led@1 {
603 label = "pepper:user1:red";
604 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
605 linux,default-trigger = "none";
606 default-state = "off";
607 };
608};
609
610&buttons {
611 pinctrl-names = "default";
612 pinctrl-0 = <&user_buttons_pins>;
613 #address-cells = <1>;
614 #size-cells = <0>;
615
616 button@0 {
617 label = "home";
618 linux,code = <KEY_HOME>;
619 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
620 gpio-key,wakeup;
621 };
622
623 button@1 {
624 label = "menu";
625 linux,code = <KEY_MENU>;
626 gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
627 gpio-key,wakeup;
628 };
629
630 buttons@2 {
631 label = "power";
632 linux,code = <KEY_POWER>;
633 gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
634 gpio-key,wakeup;
635 };
636};
637
638&am33xx_pinmux {
639 user_leds_pins: pinmux_user_leds {
640 pinctrl-single,pins = <
641 0x50 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */
642 0x54 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
643 >;
644 };
645
646 user_buttons_pins: pinmux_user_buttons {
647 pinctrl-single,pins = <
648 0x58 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
649 0x5C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */
650 0x164 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */
651 >;
652 };
653};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 49fa59622254..8d3c16304636 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -30,7 +30,7 @@
30 cpus { 30 cpus {
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <0>; 32 #size-cells = <0>;
33 cpu@0 { 33 cpu: cpu@0 {
34 compatible = "arm,cortex-a9"; 34 compatible = "arm,cortex-a9";
35 device_type = "cpu"; 35 device_type = "cpu";
36 reg = <0>; 36 reg = <0>;
@@ -270,7 +270,7 @@
270 ti,hwmods = "counter_32k"; 270 ti,hwmods = "counter_32k";
271 }; 271 };
272 272
273 rtc@44e3e000 { 273 rtc: rtc@44e3e000 {
274 compatible = "ti,am4372-rtc","ti,da830-rtc"; 274 compatible = "ti,am4372-rtc","ti,da830-rtc";
275 reg = <0x44e3e000 0x1000>; 275 reg = <0x44e3e000 0x1000>;
276 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH 276 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
@@ -279,7 +279,7 @@
279 status = "disabled"; 279 status = "disabled";
280 }; 280 };
281 281
282 wdt@44e35000 { 282 wdt: wdt@44e35000 {
283 compatible = "ti,am4372-wdt","ti,omap3-wdt"; 283 compatible = "ti,am4372-wdt","ti,omap3-wdt";
284 reg = <0x44e35000 0x1000>; 284 reg = <0x44e35000 0x1000>;
285 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 285 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
@@ -871,7 +871,7 @@
871 #size-cells = <1>; 871 #size-cells = <1>;
872 ranges; 872 ranges;
873 873
874 dispc@4832a400 { 874 dispc: dispc@4832a400 {
875 compatible = "ti,omap3-dispc"; 875 compatible = "ti,omap3-dispc";
876 reg = <0x4832a400 0x400>; 876 reg = <0x4832a400 0x400>;
877 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 877 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 003766c47bbf..f0422c2a7468 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -257,16 +257,73 @@
257}; 257};
258 258
259&i2c0 { 259&i2c0 {
260 status = "okay"; 260 status = "okay";
261 pinctrl-names = "default"; 261 pinctrl-names = "default";
262 pinctrl-0 = <&i2c0_pins>; 262 pinctrl-0 = <&i2c0_pins>;
263 clock-frequency = <400000>;
264
265 tps65218: tps65218@24 {
266 reg = <0x24>;
267 compatible = "ti,tps65218";
268 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
269 interrupt-parent = <&gic>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
272
273 dcdc1: regulator-dcdc1 {
274 compatible = "ti,tps65218-dcdc1";
275 regulator-name = "vdd_core";
276 regulator-min-microvolt = <912000>;
277 regulator-max-microvolt = <1144000>;
278 regulator-boot-on;
279 regulator-always-on;
280 };
281
282 dcdc2: regulator-dcdc2 {
283 compatible = "ti,tps65218-dcdc2";
284 regulator-name = "vdd_mpu";
285 regulator-min-microvolt = <912000>;
286 regulator-max-microvolt = <1378000>;
287 regulator-boot-on;
288 regulator-always-on;
289 };
290
291 dcdc3: regulator-dcdc3 {
292 compatible = "ti,tps65218-dcdc3";
293 regulator-name = "vdcdc3";
294 regulator-min-microvolt = <1350000>;
295 regulator-max-microvolt = <1350000>;
296 regulator-boot-on;
297 regulator-always-on;
298 };
299 dcdc5: regulator-dcdc5 {
300 compatible = "ti,tps65218-dcdc5";
301 regulator-name = "v1_0bat";
302 regulator-min-microvolt = <1000000>;
303 regulator-max-microvolt = <1000000>;
304 };
305
306 dcdc6: regulator-dcdc6 {
307 compatible = "ti,tps65218-dcdc6";
308 regulator-name = "v1_8bat";
309 regulator-min-microvolt = <1800000>;
310 regulator-max-microvolt = <1800000>;
311 };
312
313 ldo1: regulator-ldo1 {
314 compatible = "ti,tps65218-ldo1";
315 regulator-min-microvolt = <1800000>;
316 regulator-max-microvolt = <1800000>;
317 regulator-boot-on;
318 regulator-always-on;
319 };
320 };
263}; 321};
264 322
265&i2c1 { 323&i2c1 {
266 status = "okay"; 324 status = "okay";
267 pinctrl-names = "default"; 325 pinctrl-names = "default";
268 pinctrl-0 = <&i2c1_pins>; 326 pinctrl-0 = <&i2c1_pins>;
269
270 pixcir_ts@5c { 327 pixcir_ts@5c {
271 compatible = "pixcir,pixcir_tangoc"; 328 compatible = "pixcir,pixcir_tangoc";
272 pinctrl-names = "default"; 329 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
new file mode 100644
index 000000000000..859ff3d620ee
--- /dev/null
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -0,0 +1,613 @@
1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x SK EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/pwm/pwm.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18
19/ {
20 model = "TI AM437x SK EVM";
21 compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43";
22
23 aliases {
24 display0 = &lcd0;
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
30 brightness-levels = <0 51 53 56 62 75 101 152 255>;
31 default-brightness-level = <8>;
32 };
33
34 sound {
35 compatible = "ti,da830-evm-audio";
36 ti,model = "AM437x-SK-EVM";
37 ti,audio-codec = <&tlv320aic3106>;
38 ti,mcasp-controller = <&mcasp1>;
39 ti,codec-clock-rate = <24000000>;
40 ti,audio-routing =
41 "Headphone Jack", "HPLOUT",
42 "Headphone Jack", "HPROUT";
43 };
44
45 matrix_keypad: matrix_keypad@0 {
46 compatible = "gpio-matrix-keypad";
47
48 pinctrl-names = "default";
49 pinctrl-0 = <&matrix_keypad_pins>;
50
51 debounce-delay-ms = <5>;
52 col-scan-delay-us = <1500>;
53
54 row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
55 &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
56
57 col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */
58 &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */
59
60 linux,keymap = <
61 MATRIX_KEY(0, 0, KEY_DOWN)
62 MATRIX_KEY(0, 1, KEY_RIGHT)
63 MATRIX_KEY(1, 0, KEY_LEFT)
64 MATRIX_KEY(1, 1, KEY_UP)
65 >;
66 };
67
68 leds {
69 compatible = "gpio-leds";
70
71 pinctrl-names = "default";
72 pinctrl-0 = <&leds_pins>;
73
74 led@0 {
75 label = "am437x-sk:red:heartbeat";
76 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
77 linux,default-trigger = "heartbeat";
78 default-state = "off";
79 };
80
81 led@1 {
82 label = "am437x-sk:green:mmc1";
83 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
84 linux,default-trigger = "mmc0";
85 default-state = "off";
86 };
87
88 led@2 {
89 label = "am437x-sk:blue:cpu0";
90 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
91 linux,default-trigger = "cpu0";
92 default-state = "off";
93 };
94
95 led@3 {
96 label = "am437x-sk:blue:usr3";
97 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
98 default-state = "off";
99 };
100 };
101
102 lcd0: display {
103 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
104 label = "lcd";
105
106 pinctrl-names = "default";
107 pinctrl-0 = <&lcd_pins>;
108
109 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
110
111 panel-timing {
112 clock-frequency = <9000000>;
113 hactive = <480>;
114 vactive = <272>;
115 hfront-porch = <8>;
116 hback-porch = <43>;
117 hsync-len = <4>;
118 vback-porch = <12>;
119 vfront-porch = <4>;
120 vsync-len = <10>;
121 hsync-active = <0>;
122 vsync-active = <0>;
123 de-active = <1>;
124 pixelclk-active = <1>;
125 };
126
127 port {
128 lcd_in: endpoint {
129 remote-endpoint = <&dpi_out>;
130 };
131 };
132 };
133};
134
135&am43xx_pinmux {
136 matrix_keypad_pins: matrix_keypad_pins {
137 pinctrl-single,pins = <
138 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
139 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
140 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
141 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
142 >;
143 };
144
145 leds_pins: leds_pins {
146 pinctrl-single,pins = <
147 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
148 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
149 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
150 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
151 >;
152 };
153
154 i2c0_pins: i2c0_pins {
155 pinctrl-single,pins = <
156 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
157 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
158 >;
159 };
160
161 i2c1_pins: i2c1_pins {
162 pinctrl-single,pins = <
163 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
164 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
165 >;
166 };
167
168 mmc1_pins: pinmux_mmc1_pins {
169 pinctrl-single,pins = <
170 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
171 >;
172 };
173
174 ecap0_pins: backlight_pins {
175 pinctrl-single,pins = <
176 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
177 >;
178 };
179
180 edt_ft5306_ts_pins: edt_ft5306_ts_pins {
181 pinctrl-single,pins = <
182 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
183 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
184 >;
185 };
186
187 cpsw_default: cpsw_default {
188 pinctrl-single,pins = <
189 /* Slave 1 */
190 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
191 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
192 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
193 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
194 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
195 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
196 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
197 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
198 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
199 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
200 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
201 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
202
203 /* Slave 2 */
204 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
205 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
206 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
207 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
208 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
209 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
210 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
211 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
212 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
213 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
214 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
215 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
216 >;
217 };
218
219 cpsw_sleep: cpsw_sleep {
220 pinctrl-single,pins = <
221 /* Slave 1 reset value */
222 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
223 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
224 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
225 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
226 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
227 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
228 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
229 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
230 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
231 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
232 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
233 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
234
235 /* Slave 2 reset value */
236 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
237 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
238 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
239 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
240 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
241 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
242 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
243 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
244 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
245 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
246 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
247 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
248 >;
249 };
250
251 davinci_mdio_default: davinci_mdio_default {
252 pinctrl-single,pins = <
253 /* MDIO */
254 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
255 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
256 >;
257 };
258
259 davinci_mdio_sleep: davinci_mdio_sleep {
260 pinctrl-single,pins = <
261 /* MDIO reset value */
262 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
263 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
264 >;
265 };
266
267 dss_pins: dss_pins {
268 pinctrl-single,pins = <
269 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
270 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
271 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
272 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
273 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
274 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
275 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
276 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
277 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
278 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
279 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
280 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
281 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
282 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
283 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
284 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
285 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
286 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
287 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
288 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
289 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
290 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
291 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
292 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
293 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
294 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
295 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
296 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
297
298 >;
299 };
300
301 qspi_pins: qspi_pins {
302 pinctrl-single,pins = <
303 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
304 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
305 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
306 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
307 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
308 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
309 >;
310 };
311
312 mcasp1_pins: mcasp1_pins {
313 pinctrl-single,pins = <
314 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
315 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
316 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
317 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
318 >;
319 };
320
321 lcd_pins: lcd_pins {
322 pinctrl-single,pins = <
323 /* GPIO 5_8 to select LCD / HDMI */
324 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
325 >;
326 };
327};
328
329&i2c0 {
330 status = "okay";
331 pinctrl-names = "default";
332 pinctrl-0 = <&i2c0_pins>;
333 clock-frequency = <400000>;
334
335 tps@24 {
336 compatible = "ti,tps65218";
337 reg = <0x24>;
338 interrupt-parent = <&gic>;
339 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342
343 dcdc1: regulator-dcdc1 {
344 compatible = "ti,tps65218-dcdc1";
345 /* VDD_CORE limits min of OPP50 and max of OPP100 */
346 regulator-name = "vdd_core";
347 regulator-min-microvolt = <912000>;
348 regulator-max-microvolt = <1144000>;
349 regulator-boot-on;
350 regulator-always-on;
351 };
352
353 dcdc2: regulator-dcdc2 {
354 compatible = "ti,tps65218-dcdc2";
355 /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
356 regulator-name = "vdd_mpu";
357 regulator-min-microvolt = <912000>;
358 regulator-max-microvolt = <1378000>;
359 regulator-boot-on;
360 regulator-always-on;
361 };
362
363 dcdc3: regulator-dcdc3 {
364 compatible = "ti,tps65218-dcdc3";
365 regulator-name = "vdds_ddr";
366 regulator-min-microvolt = <1350000>;
367 regulator-max-microvolt = <1350000>;
368 regulator-boot-on;
369 regulator-always-on;
370 };
371
372 dcdc4: regulator-dcdc4 {
373 compatible = "ti,tps65218-dcdc4";
374 regulator-name = "v3_3d";
375 regulator-min-microvolt = <3300000>;
376 regulator-max-microvolt = <3300000>;
377 regulator-boot-on;
378 regulator-always-on;
379 };
380
381 ldo1: regulator-ldo1 {
382 compatible = "ti,tps65218-ldo1";
383 regulator-name = "v1_8d";
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>;
386 regulator-boot-on;
387 regulator-always-on;
388 };
389
390 };
391
392 at24@50 {
393 compatible = "at24,24c256";
394 pagesize = <64>;
395 reg = <0x50>;
396 };
397};
398
399&i2c1 {
400 status = "okay";
401 pinctrl-names = "default";
402 pinctrl-0 = <&i2c1_pins>;
403 clock-frequency = <400000>;
404
405 edt-ft5306@38 {
406 status = "okay";
407 compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
408 pinctrl-names = "default";
409 pinctrl-0 = <&edt_ft5306_ts_pins>;
410
411 reg = <0x38>;
412 interrupt-parent = <&gpio0>;
413 interrupts = <31 0>;
414
415 wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
416
417 touchscreen-size-x = <480>;
418 touchscreen-size-y = <272>;
419 };
420
421 tlv320aic3106: tlv320aic3106@1b {
422 compatible = "ti,tlv320aic3106";
423 reg = <0x1b>;
424 status = "okay";
425
426 /* Regulators */
427 AVDD-supply = <&dcdc4>;
428 IOVDD-supply = <&dcdc4>;
429 DRVDD-supply = <&dcdc4>;
430 DVDD-supply = <&ldo1>;
431 };
432
433 lis331dlh@18 {
434 compatible = "st,lis331dlh";
435 reg = <0x18>;
436 status = "okay";
437
438 Vdd-supply = <&dcdc4>;
439 Vdd_IO-supply = <&dcdc4>;
440 interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>;
441 };
442};
443
444&epwmss0 {
445 status = "okay";
446};
447
448&ecap0 {
449 status = "okay";
450 pinctrl-names = "default";
451 pinctrl-0 = <&ecap0_pins>;
452};
453
454&gpio0 {
455 status = "okay";
456};
457
458&gpio1 {
459 status = "okay";
460};
461
462&gpio5 {
463 status = "okay";
464};
465
466&mmc1 {
467 status = "okay";
468 pinctrl-names = "default";
469 pinctrl-0 = <&mmc1_pins>;
470
471 vmmc-supply = <&dcdc4>;
472 bus-width = <4>;
473 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
474};
475
476&usb2_phy1 {
477 status = "okay";
478};
479
480&usb1 {
481 dr_mode = "peripheral";
482 status = "okay";
483};
484
485&usb2_phy2 {
486 status = "okay";
487};
488
489&usb2 {
490 dr_mode = "host";
491 status = "okay";
492};
493
494&qspi {
495 status = "okay";
496 pinctrl-names = "default";
497 pinctrl-0 = <&qspi_pins>;
498
499 spi-max-frequency = <48000000>;
500 m25p80@0 {
501 compatible = "mx66l51235l";
502 spi-max-frequency = <48000000>;
503 reg = <0>;
504 spi-cpol;
505 spi-cpha;
506 spi-tx-bus-width = <1>;
507 spi-rx-bus-width = <4>;
508 #address-cells = <1>;
509 #size-cells = <1>;
510
511 /* MTD partition table.
512 * The ROM checks the first 512KiB
513 * for a valid file to boot(XIP).
514 */
515 partition@0 {
516 label = "QSPI.U_BOOT";
517 reg = <0x00000000 0x000080000>;
518 };
519 partition@1 {
520 label = "QSPI.U_BOOT.backup";
521 reg = <0x00080000 0x00080000>;
522 };
523 partition@2 {
524 label = "QSPI.U-BOOT-SPL_OS";
525 reg = <0x00100000 0x00010000>;
526 };
527 partition@3 {
528 label = "QSPI.U_BOOT_ENV";
529 reg = <0x00110000 0x00010000>;
530 };
531 partition@4 {
532 label = "QSPI.U-BOOT-ENV.backup";
533 reg = <0x00120000 0x00010000>;
534 };
535 partition@5 {
536 label = "QSPI.KERNEL";
537 reg = <0x00130000 0x0800000>;
538 };
539 partition@6 {
540 label = "QSPI.FILESYSTEM";
541 reg = <0x00930000 0x36D0000>;
542 };
543 };
544};
545
546&mac {
547 pinctrl-names = "default", "sleep";
548 pinctrl-0 = <&cpsw_default>;
549 pinctrl-1 = <&cpsw_sleep>;
550 dual_emac = <1>;
551 status = "okay";
552};
553
554&davinci_mdio {
555 pinctrl-names = "default", "sleep";
556 pinctrl-0 = <&davinci_mdio_default>;
557 pinctrl-1 = <&davinci_mdio_sleep>;
558 status = "okay";
559};
560
561&cpsw_emac0 {
562 phy_id = <&davinci_mdio>, <4>;
563 phy-mode = "rgmii";
564 dual_emac_res_vlan = <1>;
565};
566
567&cpsw_emac1 {
568 phy_id = <&davinci_mdio>, <5>;
569 phy-mode = "rgmii";
570 dual_emac_res_vlan = <2>;
571};
572
573&elm {
574 status = "okay";
575};
576
577&mcasp1 {
578 pinctrl-names = "default";
579 pinctrl-0 = <&mcasp1_pins>;
580
581 status = "okay";
582
583 op-mode = <0>;
584 tdm-slots = <2>;
585 serial-dir = <
586 0 0 1 2
587 >;
588
589 tx-num-evt = <1>;
590 rx-num-evt = <1>;
591};
592
593&dss {
594 status = "okay";
595
596 pinctrl-names = "default";
597 pinctrl-0 = <&dss_pins>;
598
599 port {
600 dpi_out: endpoint@0 {
601 remote-endpoint = <&lcd_in>;
602 data-lines = <24>;
603 };
604 };
605};
606
607&rtc {
608 status = "okay";
609};
610
611&wdt {
612 status = "okay";
613};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 90098f98a5c8..f1ee74957512 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -327,6 +327,65 @@
327 status = "okay"; 327 status = "okay";
328 pinctrl-names = "default"; 328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c0_pins>; 329 pinctrl-0 = <&i2c0_pins>;
330 clock-frequency = <400000>;
331
332 tps65218: tps65218@24 {
333 reg = <0x24>;
334 compatible = "ti,tps65218";
335 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
336 interrupt-parent = <&gic>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
339
340 dcdc1: regulator-dcdc1 {
341 compatible = "ti,tps65218-dcdc1";
342 regulator-name = "vdd_core";
343 regulator-min-microvolt = <912000>;
344 regulator-max-microvolt = <1144000>;
345 regulator-boot-on;
346 regulator-always-on;
347 };
348
349 dcdc2: regulator-dcdc2 {
350 compatible = "ti,tps65218-dcdc2";
351 regulator-name = "vdd_mpu";
352 regulator-min-microvolt = <912000>;
353 regulator-max-microvolt = <1378000>;
354 regulator-boot-on;
355 regulator-always-on;
356 };
357
358 dcdc3: regulator-dcdc3 {
359 compatible = "ti,tps65218-dcdc3";
360 regulator-name = "vdcdc3";
361 regulator-min-microvolt = <1350000>;
362 regulator-max-microvolt = <1350000>;
363 regulator-boot-on;
364 regulator-always-on;
365 };
366
367 dcdc5: regulator-dcdc5 {
368 compatible = "ti,tps65218-dcdc5";
369 regulator-name = "v1_0bat";
370 regulator-min-microvolt = <1000000>;
371 regulator-max-microvolt = <1000000>;
372 };
373
374 dcdc6: regulator-dcdc6 {
375 compatible = "ti,tps65218-dcdc6";
376 regulator-name = "v1_8bat";
377 regulator-min-microvolt = <1800000>;
378 regulator-max-microvolt = <1800000>;
379 };
380
381 ldo1: regulator-ldo1 {
382 compatible = "ti,tps65218-ldo1";
383 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <1800000>;
385 regulator-boot-on;
386 regulator-always-on;
387 };
388 };
330 389
331 at24@50 { 390 at24@50 {
332 compatible = "at24,24c256"; 391 compatible = "at24,24c256";
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 4adc28039c30..fd96cedf3a07 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -495,3 +495,11 @@
495 }; 495 };
496 }; 496 };
497}; 497};
498
499&usb2_phy1 {
500 phy-supply = <&ldousb_reg>;
501};
502
503&usb2_phy2 {
504 phy-supply = <&ldousb_reg>;
505};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 80127638b379..6563b983a127 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -12,6 +12,9 @@
12 12
13#include "skeleton.dtsi" 13#include "skeleton.dtsi"
14 14
15#define MAX_SOURCES 400
16#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
17
15/ { 18/ {
16 #address-cells = <1>; 19 #address-cells = <1>;
17 #size-cells = <1>; 20 #size-cells = <1>;
@@ -45,6 +48,7 @@
45 compatible = "arm,cortex-a15-gic"; 48 compatible = "arm,cortex-a15-gic";
46 interrupt-controller; 49 interrupt-controller;
47 #interrupt-cells = <3>; 50 #interrupt-cells = <3>;
51 arm,routable-irqs = <192>;
48 reg = <0x48211000 0x1000>, 52 reg = <0x48211000 0x1000>,
49 <0x48212000 0x1000>, 53 <0x48212000 0x1000>,
50 <0x48214000 0x2000>, 54 <0x48214000 0x2000>,
@@ -79,8 +83,8 @@
79 ti,hwmods = "l3_main_1", "l3_main_2"; 83 ti,hwmods = "l3_main_1", "l3_main_2";
80 reg = <0x44000000 0x1000000>, 84 reg = <0x44000000 0x1000000>,
81 <0x45000000 0x1000>; 85 <0x45000000 0x1000>;
82 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 86 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 87 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
84 88
85 prm: prm@4ae06000 { 89 prm: prm@4ae06000 {
86 compatible = "ti,dra7-prm"; 90 compatible = "ti,dra7-prm";
@@ -95,6 +99,75 @@
95 }; 99 };
96 }; 100 };
97 101
102 axi@0 {
103 compatible = "simple-bus";
104 #size-cells = <1>;
105 #address-cells = <1>;
106 ranges = <0x51000000 0x51000000 0x3000
107 0x0 0x20000000 0x10000000>;
108 pcie@51000000 {
109 compatible = "ti,dra7-pcie";
110 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
111 reg-names = "rc_dbics", "ti_conf", "config";
112 interrupts = <0 232 0x4>, <0 233 0x4>;
113 #address-cells = <3>;
114 #size-cells = <2>;
115 device_type = "pci";
116 ranges = <0x81000000 0 0 0x03000 0 0x00010000
117 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
118 #interrupt-cells = <1>;
119 num-lanes = <1>;
120 ti,hwmods = "pcie1";
121 phys = <&pcie1_phy>;
122 phy-names = "pcie-phy0";
123 interrupt-map-mask = <0 0 0 7>;
124 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
125 <0 0 0 2 &pcie1_intc 2>,
126 <0 0 0 3 &pcie1_intc 3>,
127 <0 0 0 4 &pcie1_intc 4>;
128 pcie1_intc: interrupt-controller {
129 interrupt-controller;
130 #address-cells = <0>;
131 #interrupt-cells = <1>;
132 };
133 };
134 };
135
136 axi@1 {
137 compatible = "simple-bus";
138 #size-cells = <1>;
139 #address-cells = <1>;
140 ranges = <0x51800000 0x51800000 0x3000
141 0x0 0x30000000 0x10000000>;
142 status = "disabled";
143 pcie@51000000 {
144 compatible = "ti,dra7-pcie";
145 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
146 reg-names = "rc_dbics", "ti_conf", "config";
147 interrupts = <0 355 0x4>, <0 356 0x4>;
148 #address-cells = <3>;
149 #size-cells = <2>;
150 device_type = "pci";
151 ranges = <0x81000000 0 0 0x03000 0 0x00010000
152 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
153 #interrupt-cells = <1>;
154 num-lanes = <1>;
155 ti,hwmods = "pcie2";
156 phys = <&pcie2_phy>;
157 phy-names = "pcie-phy0";
158 interrupt-map-mask = <0 0 0 7>;
159 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
160 <0 0 0 2 &pcie2_intc 2>,
161 <0 0 0 3 &pcie2_intc 3>,
162 <0 0 0 4 &pcie2_intc 4>;
163 pcie2_intc: interrupt-controller {
164 interrupt-controller;
165 #address-cells = <0>;
166 #interrupt-cells = <1>;
167 };
168 };
169 };
170
98 cm_core_aon: cm_core_aon@4a005000 { 171 cm_core_aon: cm_core_aon@4a005000 {
99 compatible = "ti,dra7-cm-core-aon"; 172 compatible = "ti,dra7-cm-core-aon";
100 reg = <0x4a005000 0x2000>; 173 reg = <0x4a005000 0x2000>;
@@ -155,10 +228,10 @@
155 sdma: dma-controller@4a056000 { 228 sdma: dma-controller@4a056000 {
156 compatible = "ti,omap4430-sdma"; 229 compatible = "ti,omap4430-sdma";
157 reg = <0x4a056000 0x1000>; 230 reg = <0x4a056000 0x1000>;
158 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 231 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 234 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
162 #dma-cells = <1>; 235 #dma-cells = <1>;
163 #dma-channels = <32>; 236 #dma-channels = <32>;
164 #dma-requests = <127>; 237 #dma-requests = <127>;
@@ -167,7 +240,7 @@
167 gpio1: gpio@4ae10000 { 240 gpio1: gpio@4ae10000 {
168 compatible = "ti,omap4-gpio"; 241 compatible = "ti,omap4-gpio";
169 reg = <0x4ae10000 0x200>; 242 reg = <0x4ae10000 0x200>;
170 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 243 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
171 ti,hwmods = "gpio1"; 244 ti,hwmods = "gpio1";
172 gpio-controller; 245 gpio-controller;
173 #gpio-cells = <2>; 246 #gpio-cells = <2>;
@@ -178,7 +251,7 @@
178 gpio2: gpio@48055000 { 251 gpio2: gpio@48055000 {
179 compatible = "ti,omap4-gpio"; 252 compatible = "ti,omap4-gpio";
180 reg = <0x48055000 0x200>; 253 reg = <0x48055000 0x200>;
181 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 254 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
182 ti,hwmods = "gpio2"; 255 ti,hwmods = "gpio2";
183 gpio-controller; 256 gpio-controller;
184 #gpio-cells = <2>; 257 #gpio-cells = <2>;
@@ -189,7 +262,7 @@
189 gpio3: gpio@48057000 { 262 gpio3: gpio@48057000 {
190 compatible = "ti,omap4-gpio"; 263 compatible = "ti,omap4-gpio";
191 reg = <0x48057000 0x200>; 264 reg = <0x48057000 0x200>;
192 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 265 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "gpio3"; 266 ti,hwmods = "gpio3";
194 gpio-controller; 267 gpio-controller;
195 #gpio-cells = <2>; 268 #gpio-cells = <2>;
@@ -200,7 +273,7 @@
200 gpio4: gpio@48059000 { 273 gpio4: gpio@48059000 {
201 compatible = "ti,omap4-gpio"; 274 compatible = "ti,omap4-gpio";
202 reg = <0x48059000 0x200>; 275 reg = <0x48059000 0x200>;
203 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 276 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
204 ti,hwmods = "gpio4"; 277 ti,hwmods = "gpio4";
205 gpio-controller; 278 gpio-controller;
206 #gpio-cells = <2>; 279 #gpio-cells = <2>;
@@ -211,7 +284,7 @@
211 gpio5: gpio@4805b000 { 284 gpio5: gpio@4805b000 {
212 compatible = "ti,omap4-gpio"; 285 compatible = "ti,omap4-gpio";
213 reg = <0x4805b000 0x200>; 286 reg = <0x4805b000 0x200>;
214 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 287 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
215 ti,hwmods = "gpio5"; 288 ti,hwmods = "gpio5";
216 gpio-controller; 289 gpio-controller;
217 #gpio-cells = <2>; 290 #gpio-cells = <2>;
@@ -222,7 +295,7 @@
222 gpio6: gpio@4805d000 { 295 gpio6: gpio@4805d000 {
223 compatible = "ti,omap4-gpio"; 296 compatible = "ti,omap4-gpio";
224 reg = <0x4805d000 0x200>; 297 reg = <0x4805d000 0x200>;
225 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 298 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
226 ti,hwmods = "gpio6"; 299 ti,hwmods = "gpio6";
227 gpio-controller; 300 gpio-controller;
228 #gpio-cells = <2>; 301 #gpio-cells = <2>;
@@ -233,7 +306,7 @@
233 gpio7: gpio@48051000 { 306 gpio7: gpio@48051000 {
234 compatible = "ti,omap4-gpio"; 307 compatible = "ti,omap4-gpio";
235 reg = <0x48051000 0x200>; 308 reg = <0x48051000 0x200>;
236 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 309 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
237 ti,hwmods = "gpio7"; 310 ti,hwmods = "gpio7";
238 gpio-controller; 311 gpio-controller;
239 #gpio-cells = <2>; 312 #gpio-cells = <2>;
@@ -244,7 +317,7 @@
244 gpio8: gpio@48053000 { 317 gpio8: gpio@48053000 {
245 compatible = "ti,omap4-gpio"; 318 compatible = "ti,omap4-gpio";
246 reg = <0x48053000 0x200>; 319 reg = <0x48053000 0x200>;
247 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 320 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
248 ti,hwmods = "gpio8"; 321 ti,hwmods = "gpio8";
249 gpio-controller; 322 gpio-controller;
250 #gpio-cells = <2>; 323 #gpio-cells = <2>;
@@ -255,7 +328,7 @@
255 uart1: serial@4806a000 { 328 uart1: serial@4806a000 {
256 compatible = "ti,omap4-uart"; 329 compatible = "ti,omap4-uart";
257 reg = <0x4806a000 0x100>; 330 reg = <0x4806a000 0x100>;
258 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 331 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
259 ti,hwmods = "uart1"; 332 ti,hwmods = "uart1";
260 clock-frequency = <48000000>; 333 clock-frequency = <48000000>;
261 status = "disabled"; 334 status = "disabled";
@@ -264,7 +337,7 @@
264 uart2: serial@4806c000 { 337 uart2: serial@4806c000 {
265 compatible = "ti,omap4-uart"; 338 compatible = "ti,omap4-uart";
266 reg = <0x4806c000 0x100>; 339 reg = <0x4806c000 0x100>;
267 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 340 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
268 ti,hwmods = "uart2"; 341 ti,hwmods = "uart2";
269 clock-frequency = <48000000>; 342 clock-frequency = <48000000>;
270 status = "disabled"; 343 status = "disabled";
@@ -273,7 +346,7 @@
273 uart3: serial@48020000 { 346 uart3: serial@48020000 {
274 compatible = "ti,omap4-uart"; 347 compatible = "ti,omap4-uart";
275 reg = <0x48020000 0x100>; 348 reg = <0x48020000 0x100>;
276 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 349 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
277 ti,hwmods = "uart3"; 350 ti,hwmods = "uart3";
278 clock-frequency = <48000000>; 351 clock-frequency = <48000000>;
279 status = "disabled"; 352 status = "disabled";
@@ -282,7 +355,7 @@
282 uart4: serial@4806e000 { 355 uart4: serial@4806e000 {
283 compatible = "ti,omap4-uart"; 356 compatible = "ti,omap4-uart";
284 reg = <0x4806e000 0x100>; 357 reg = <0x4806e000 0x100>;
285 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
286 ti,hwmods = "uart4"; 359 ti,hwmods = "uart4";
287 clock-frequency = <48000000>; 360 clock-frequency = <48000000>;
288 status = "disabled"; 361 status = "disabled";
@@ -291,7 +364,7 @@
291 uart5: serial@48066000 { 364 uart5: serial@48066000 {
292 compatible = "ti,omap4-uart"; 365 compatible = "ti,omap4-uart";
293 reg = <0x48066000 0x100>; 366 reg = <0x48066000 0x100>;
294 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 367 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
295 ti,hwmods = "uart5"; 368 ti,hwmods = "uart5";
296 clock-frequency = <48000000>; 369 clock-frequency = <48000000>;
297 status = "disabled"; 370 status = "disabled";
@@ -300,7 +373,7 @@
300 uart6: serial@48068000 { 373 uart6: serial@48068000 {
301 compatible = "ti,omap4-uart"; 374 compatible = "ti,omap4-uart";
302 reg = <0x48068000 0x100>; 375 reg = <0x48068000 0x100>;
303 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 376 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
304 ti,hwmods = "uart6"; 377 ti,hwmods = "uart6";
305 clock-frequency = <48000000>; 378 clock-frequency = <48000000>;
306 status = "disabled"; 379 status = "disabled";
@@ -309,6 +382,7 @@
309 uart7: serial@48420000 { 382 uart7: serial@48420000 {
310 compatible = "ti,omap4-uart"; 383 compatible = "ti,omap4-uart";
311 reg = <0x48420000 0x100>; 384 reg = <0x48420000 0x100>;
385 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
312 ti,hwmods = "uart7"; 386 ti,hwmods = "uart7";
313 clock-frequency = <48000000>; 387 clock-frequency = <48000000>;
314 status = "disabled"; 388 status = "disabled";
@@ -317,6 +391,7 @@
317 uart8: serial@48422000 { 391 uart8: serial@48422000 {
318 compatible = "ti,omap4-uart"; 392 compatible = "ti,omap4-uart";
319 reg = <0x48422000 0x100>; 393 reg = <0x48422000 0x100>;
394 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
320 ti,hwmods = "uart8"; 395 ti,hwmods = "uart8";
321 clock-frequency = <48000000>; 396 clock-frequency = <48000000>;
322 status = "disabled"; 397 status = "disabled";
@@ -325,6 +400,7 @@
325 uart9: serial@48424000 { 400 uart9: serial@48424000 {
326 compatible = "ti,omap4-uart"; 401 compatible = "ti,omap4-uart";
327 reg = <0x48424000 0x100>; 402 reg = <0x48424000 0x100>;
403 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
328 ti,hwmods = "uart9"; 404 ti,hwmods = "uart9";
329 clock-frequency = <48000000>; 405 clock-frequency = <48000000>;
330 status = "disabled"; 406 status = "disabled";
@@ -333,6 +409,7 @@
333 uart10: serial@4ae2b000 { 409 uart10: serial@4ae2b000 {
334 compatible = "ti,omap4-uart"; 410 compatible = "ti,omap4-uart";
335 reg = <0x4ae2b000 0x100>; 411 reg = <0x4ae2b000 0x100>;
412 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
336 ti,hwmods = "uart10"; 413 ti,hwmods = "uart10";
337 clock-frequency = <48000000>; 414 clock-frequency = <48000000>;
338 status = "disabled"; 415 status = "disabled";
@@ -341,7 +418,7 @@
341 timer1: timer@4ae18000 { 418 timer1: timer@4ae18000 {
342 compatible = "ti,omap5430-timer"; 419 compatible = "ti,omap5430-timer";
343 reg = <0x4ae18000 0x80>; 420 reg = <0x4ae18000 0x80>;
344 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 421 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
345 ti,hwmods = "timer1"; 422 ti,hwmods = "timer1";
346 ti,timer-alwon; 423 ti,timer-alwon;
347 }; 424 };
@@ -349,28 +426,28 @@
349 timer2: timer@48032000 { 426 timer2: timer@48032000 {
350 compatible = "ti,omap5430-timer"; 427 compatible = "ti,omap5430-timer";
351 reg = <0x48032000 0x80>; 428 reg = <0x48032000 0x80>;
352 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 429 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
353 ti,hwmods = "timer2"; 430 ti,hwmods = "timer2";
354 }; 431 };
355 432
356 timer3: timer@48034000 { 433 timer3: timer@48034000 {
357 compatible = "ti,omap5430-timer"; 434 compatible = "ti,omap5430-timer";
358 reg = <0x48034000 0x80>; 435 reg = <0x48034000 0x80>;
359 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 436 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
360 ti,hwmods = "timer3"; 437 ti,hwmods = "timer3";
361 }; 438 };
362 439
363 timer4: timer@48036000 { 440 timer4: timer@48036000 {
364 compatible = "ti,omap5430-timer"; 441 compatible = "ti,omap5430-timer";
365 reg = <0x48036000 0x80>; 442 reg = <0x48036000 0x80>;
366 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 443 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
367 ti,hwmods = "timer4"; 444 ti,hwmods = "timer4";
368 }; 445 };
369 446
370 timer5: timer@48820000 { 447 timer5: timer@48820000 {
371 compatible = "ti,omap5430-timer"; 448 compatible = "ti,omap5430-timer";
372 reg = <0x48820000 0x80>; 449 reg = <0x48820000 0x80>;
373 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 450 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
374 ti,hwmods = "timer5"; 451 ti,hwmods = "timer5";
375 ti,timer-dsp; 452 ti,timer-dsp;
376 }; 453 };
@@ -378,7 +455,7 @@
378 timer6: timer@48822000 { 455 timer6: timer@48822000 {
379 compatible = "ti,omap5430-timer"; 456 compatible = "ti,omap5430-timer";
380 reg = <0x48822000 0x80>; 457 reg = <0x48822000 0x80>;
381 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 458 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
382 ti,hwmods = "timer6"; 459 ti,hwmods = "timer6";
383 ti,timer-dsp; 460 ti,timer-dsp;
384 ti,timer-pwm; 461 ti,timer-pwm;
@@ -387,7 +464,7 @@
387 timer7: timer@48824000 { 464 timer7: timer@48824000 {
388 compatible = "ti,omap5430-timer"; 465 compatible = "ti,omap5430-timer";
389 reg = <0x48824000 0x80>; 466 reg = <0x48824000 0x80>;
390 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 467 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
391 ti,hwmods = "timer7"; 468 ti,hwmods = "timer7";
392 ti,timer-dsp; 469 ti,timer-dsp;
393 }; 470 };
@@ -395,7 +472,7 @@
395 timer8: timer@48826000 { 472 timer8: timer@48826000 {
396 compatible = "ti,omap5430-timer"; 473 compatible = "ti,omap5430-timer";
397 reg = <0x48826000 0x80>; 474 reg = <0x48826000 0x80>;
398 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 475 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
399 ti,hwmods = "timer8"; 476 ti,hwmods = "timer8";
400 ti,timer-dsp; 477 ti,timer-dsp;
401 ti,timer-pwm; 478 ti,timer-pwm;
@@ -404,21 +481,21 @@
404 timer9: timer@4803e000 { 481 timer9: timer@4803e000 {
405 compatible = "ti,omap5430-timer"; 482 compatible = "ti,omap5430-timer";
406 reg = <0x4803e000 0x80>; 483 reg = <0x4803e000 0x80>;
407 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 484 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
408 ti,hwmods = "timer9"; 485 ti,hwmods = "timer9";
409 }; 486 };
410 487
411 timer10: timer@48086000 { 488 timer10: timer@48086000 {
412 compatible = "ti,omap5430-timer"; 489 compatible = "ti,omap5430-timer";
413 reg = <0x48086000 0x80>; 490 reg = <0x48086000 0x80>;
414 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 491 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
415 ti,hwmods = "timer10"; 492 ti,hwmods = "timer10";
416 }; 493 };
417 494
418 timer11: timer@48088000 { 495 timer11: timer@48088000 {
419 compatible = "ti,omap5430-timer"; 496 compatible = "ti,omap5430-timer";
420 reg = <0x48088000 0x80>; 497 reg = <0x48088000 0x80>;
421 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 498 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
422 ti,hwmods = "timer11"; 499 ti,hwmods = "timer11";
423 ti,timer-pwm; 500 ti,timer-pwm;
424 }; 501 };
@@ -426,6 +503,7 @@
426 timer13: timer@48828000 { 503 timer13: timer@48828000 {
427 compatible = "ti,omap5430-timer"; 504 compatible = "ti,omap5430-timer";
428 reg = <0x48828000 0x80>; 505 reg = <0x48828000 0x80>;
506 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
429 ti,hwmods = "timer13"; 507 ti,hwmods = "timer13";
430 status = "disabled"; 508 status = "disabled";
431 }; 509 };
@@ -433,6 +511,7 @@
433 timer14: timer@4882a000 { 511 timer14: timer@4882a000 {
434 compatible = "ti,omap5430-timer"; 512 compatible = "ti,omap5430-timer";
435 reg = <0x4882a000 0x80>; 513 reg = <0x4882a000 0x80>;
514 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
436 ti,hwmods = "timer14"; 515 ti,hwmods = "timer14";
437 status = "disabled"; 516 status = "disabled";
438 }; 517 };
@@ -440,6 +519,7 @@
440 timer15: timer@4882c000 { 519 timer15: timer@4882c000 {
441 compatible = "ti,omap5430-timer"; 520 compatible = "ti,omap5430-timer";
442 reg = <0x4882c000 0x80>; 521 reg = <0x4882c000 0x80>;
522 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
443 ti,hwmods = "timer15"; 523 ti,hwmods = "timer15";
444 status = "disabled"; 524 status = "disabled";
445 }; 525 };
@@ -447,6 +527,7 @@
447 timer16: timer@4882e000 { 527 timer16: timer@4882e000 {
448 compatible = "ti,omap5430-timer"; 528 compatible = "ti,omap5430-timer";
449 reg = <0x4882e000 0x80>; 529 reg = <0x4882e000 0x80>;
530 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
450 ti,hwmods = "timer16"; 531 ti,hwmods = "timer16";
451 status = "disabled"; 532 status = "disabled";
452 }; 533 };
@@ -454,7 +535,7 @@
454 wdt2: wdt@4ae14000 { 535 wdt2: wdt@4ae14000 {
455 compatible = "ti,omap4-wdt"; 536 compatible = "ti,omap4-wdt";
456 reg = <0x4ae14000 0x80>; 537 reg = <0x4ae14000 0x80>;
457 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 538 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
458 ti,hwmods = "wd_timer2"; 539 ti,hwmods = "wd_timer2";
459 }; 540 };
460 541
@@ -468,14 +549,14 @@
468 dmm@4e000000 { 549 dmm@4e000000 {
469 compatible = "ti,omap5-dmm"; 550 compatible = "ti,omap5-dmm";
470 reg = <0x4e000000 0x800>; 551 reg = <0x4e000000 0x800>;
471 interrupts = <0 113 0x4>; 552 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
472 ti,hwmods = "dmm"; 553 ti,hwmods = "dmm";
473 }; 554 };
474 555
475 i2c1: i2c@48070000 { 556 i2c1: i2c@48070000 {
476 compatible = "ti,omap4-i2c"; 557 compatible = "ti,omap4-i2c";
477 reg = <0x48070000 0x100>; 558 reg = <0x48070000 0x100>;
478 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 559 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
479 #address-cells = <1>; 560 #address-cells = <1>;
480 #size-cells = <0>; 561 #size-cells = <0>;
481 ti,hwmods = "i2c1"; 562 ti,hwmods = "i2c1";
@@ -485,7 +566,7 @@
485 i2c2: i2c@48072000 { 566 i2c2: i2c@48072000 {
486 compatible = "ti,omap4-i2c"; 567 compatible = "ti,omap4-i2c";
487 reg = <0x48072000 0x100>; 568 reg = <0x48072000 0x100>;
488 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 569 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
489 #address-cells = <1>; 570 #address-cells = <1>;
490 #size-cells = <0>; 571 #size-cells = <0>;
491 ti,hwmods = "i2c2"; 572 ti,hwmods = "i2c2";
@@ -495,7 +576,7 @@
495 i2c3: i2c@48060000 { 576 i2c3: i2c@48060000 {
496 compatible = "ti,omap4-i2c"; 577 compatible = "ti,omap4-i2c";
497 reg = <0x48060000 0x100>; 578 reg = <0x48060000 0x100>;
498 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 579 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>; 580 #address-cells = <1>;
500 #size-cells = <0>; 581 #size-cells = <0>;
501 ti,hwmods = "i2c3"; 582 ti,hwmods = "i2c3";
@@ -505,7 +586,7 @@
505 i2c4: i2c@4807a000 { 586 i2c4: i2c@4807a000 {
506 compatible = "ti,omap4-i2c"; 587 compatible = "ti,omap4-i2c";
507 reg = <0x4807a000 0x100>; 588 reg = <0x4807a000 0x100>;
508 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 589 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
509 #address-cells = <1>; 590 #address-cells = <1>;
510 #size-cells = <0>; 591 #size-cells = <0>;
511 ti,hwmods = "i2c4"; 592 ti,hwmods = "i2c4";
@@ -515,7 +596,7 @@
515 i2c5: i2c@4807c000 { 596 i2c5: i2c@4807c000 {
516 compatible = "ti,omap4-i2c"; 597 compatible = "ti,omap4-i2c";
517 reg = <0x4807c000 0x100>; 598 reg = <0x4807c000 0x100>;
518 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 599 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
519 #address-cells = <1>; 600 #address-cells = <1>;
520 #size-cells = <0>; 601 #size-cells = <0>;
521 ti,hwmods = "i2c5"; 602 ti,hwmods = "i2c5";
@@ -525,7 +606,7 @@
525 mmc1: mmc@4809c000 { 606 mmc1: mmc@4809c000 {
526 compatible = "ti,omap4-hsmmc"; 607 compatible = "ti,omap4-hsmmc";
527 reg = <0x4809c000 0x400>; 608 reg = <0x4809c000 0x400>;
528 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 609 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
529 ti,hwmods = "mmc1"; 610 ti,hwmods = "mmc1";
530 ti,dual-volt; 611 ti,dual-volt;
531 ti,needs-special-reset; 612 ti,needs-special-reset;
@@ -538,7 +619,7 @@
538 mmc2: mmc@480b4000 { 619 mmc2: mmc@480b4000 {
539 compatible = "ti,omap4-hsmmc"; 620 compatible = "ti,omap4-hsmmc";
540 reg = <0x480b4000 0x400>; 621 reg = <0x480b4000 0x400>;
541 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 622 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
542 ti,hwmods = "mmc2"; 623 ti,hwmods = "mmc2";
543 ti,needs-special-reset; 624 ti,needs-special-reset;
544 dmas = <&sdma 47>, <&sdma 48>; 625 dmas = <&sdma 47>, <&sdma 48>;
@@ -549,7 +630,7 @@
549 mmc3: mmc@480ad000 { 630 mmc3: mmc@480ad000 {
550 compatible = "ti,omap4-hsmmc"; 631 compatible = "ti,omap4-hsmmc";
551 reg = <0x480ad000 0x400>; 632 reg = <0x480ad000 0x400>;
552 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 633 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
553 ti,hwmods = "mmc3"; 634 ti,hwmods = "mmc3";
554 ti,needs-special-reset; 635 ti,needs-special-reset;
555 dmas = <&sdma 77>, <&sdma 78>; 636 dmas = <&sdma 77>, <&sdma 78>;
@@ -560,7 +641,7 @@
560 mmc4: mmc@480d1000 { 641 mmc4: mmc@480d1000 {
561 compatible = "ti,omap4-hsmmc"; 642 compatible = "ti,omap4-hsmmc";
562 reg = <0x480d1000 0x400>; 643 reg = <0x480d1000 0x400>;
563 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 644 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
564 ti,hwmods = "mmc4"; 645 ti,hwmods = "mmc4";
565 ti,needs-special-reset; 646 ti,needs-special-reset;
566 dmas = <&sdma 57>, <&sdma 58>; 647 dmas = <&sdma 57>, <&sdma 58>;
@@ -703,7 +784,7 @@
703 mcspi1: spi@48098000 { 784 mcspi1: spi@48098000 {
704 compatible = "ti,omap4-mcspi"; 785 compatible = "ti,omap4-mcspi";
705 reg = <0x48098000 0x200>; 786 reg = <0x48098000 0x200>;
706 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 787 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>; 788 #address-cells = <1>;
708 #size-cells = <0>; 789 #size-cells = <0>;
709 ti,hwmods = "mcspi1"; 790 ti,hwmods = "mcspi1";
@@ -724,7 +805,7 @@
724 mcspi2: spi@4809a000 { 805 mcspi2: spi@4809a000 {
725 compatible = "ti,omap4-mcspi"; 806 compatible = "ti,omap4-mcspi";
726 reg = <0x4809a000 0x200>; 807 reg = <0x4809a000 0x200>;
727 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 808 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
728 #address-cells = <1>; 809 #address-cells = <1>;
729 #size-cells = <0>; 810 #size-cells = <0>;
730 ti,hwmods = "mcspi2"; 811 ti,hwmods = "mcspi2";
@@ -740,7 +821,7 @@
740 mcspi3: spi@480b8000 { 821 mcspi3: spi@480b8000 {
741 compatible = "ti,omap4-mcspi"; 822 compatible = "ti,omap4-mcspi";
742 reg = <0x480b8000 0x200>; 823 reg = <0x480b8000 0x200>;
743 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 824 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
744 #address-cells = <1>; 825 #address-cells = <1>;
745 #size-cells = <0>; 826 #size-cells = <0>;
746 ti,hwmods = "mcspi3"; 827 ti,hwmods = "mcspi3";
@@ -753,7 +834,7 @@
753 mcspi4: spi@480ba000 { 834 mcspi4: spi@480ba000 {
754 compatible = "ti,omap4-mcspi"; 835 compatible = "ti,omap4-mcspi";
755 reg = <0x480ba000 0x200>; 836 reg = <0x480ba000 0x200>;
756 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 837 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
757 #address-cells = <1>; 838 #address-cells = <1>;
758 #size-cells = <0>; 839 #size-cells = <0>;
759 ti,hwmods = "mcspi4"; 840 ti,hwmods = "mcspi4";
@@ -773,6 +854,7 @@
773 clocks = <&qspi_gfclk_div>; 854 clocks = <&qspi_gfclk_div>;
774 clock-names = "fck"; 855 clock-names = "fck";
775 num-cs = <4>; 856 num-cs = <4>;
857 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
776 status = "disabled"; 858 status = "disabled";
777 }; 859 };
778 860
@@ -803,18 +885,76 @@
803 clock-names = "sysclk"; 885 clock-names = "sysclk";
804 #phy-cells = <0>; 886 #phy-cells = <0>;
805 }; 887 };
888
889 pcie1_phy: pciephy@4a094000 {
890 compatible = "ti,phy-pipe3-pcie";
891 reg = <0x4a094000 0x80>, /* phy_rx */
892 <0x4a094400 0x64>; /* phy_tx */
893 reg-names = "phy_rx", "phy_tx";
894 ctrl-module = <&omap_control_pcie1phy>;
895 clocks = <&dpll_pcie_ref_ck>,
896 <&dpll_pcie_ref_m2ldo_ck>,
897 <&optfclk_pciephy1_32khz>,
898 <&optfclk_pciephy1_clk>,
899 <&optfclk_pciephy1_div_clk>,
900 <&optfclk_pciephy_div>;
901 clock-names = "dpll_ref", "dpll_ref_m2",
902 "wkupclk", "refclk",
903 "div-clk", "phy-div";
904 #phy-cells = <0>;
905 id = <1>;
906 ti,hwmods = "pcie1-phy";
907 };
908
909 pcie2_phy: pciephy@4a095000 {
910 compatible = "ti,phy-pipe3-pcie";
911 reg = <0x4a095000 0x80>, /* phy_rx */
912 <0x4a095400 0x64>; /* phy_tx */
913 reg-names = "phy_rx", "phy_tx";
914 ctrl-module = <&omap_control_pcie2phy>;
915 clocks = <&dpll_pcie_ref_ck>,
916 <&dpll_pcie_ref_m2ldo_ck>,
917 <&optfclk_pciephy2_32khz>,
918 <&optfclk_pciephy2_clk>,
919 <&optfclk_pciephy2_div_clk>,
920 <&optfclk_pciephy_div>;
921 clock-names = "dpll_ref", "dpll_ref_m2",
922 "wkupclk", "refclk",
923 "div-clk", "phy-div";
924 #phy-cells = <0>;
925 ti,hwmods = "pcie2-phy";
926 id = <2>;
927 status = "disabled";
928 };
806 }; 929 };
807 930
808 sata: sata@4a141100 { 931 sata: sata@4a141100 {
809 compatible = "snps,dwc-ahci"; 932 compatible = "snps,dwc-ahci";
810 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 933 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
811 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 934 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
812 phys = <&sata_phy>; 935 phys = <&sata_phy>;
813 phy-names = "sata-phy"; 936 phy-names = "sata-phy";
814 clocks = <&sata_ref_clk>; 937 clocks = <&sata_ref_clk>;
815 ti,hwmods = "sata"; 938 ti,hwmods = "sata";
816 }; 939 };
817 940
941 omap_control_pcie1phy: control-phy@0x4a003c40 {
942 compatible = "ti,control-phy-pcie";
943 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
944 reg-names = "power", "control_sma", "pcie_pcs";
945 clocks = <&sys_clkin1>;
946 clock-names = "sysclk";
947 };
948
949 omap_control_pcie2phy: control-pcie@0x4a003c44 {
950 compatible = "ti,control-phy-pcie";
951 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
952 reg-names = "power", "control_sma", "pcie_pcs";
953 clocks = <&sys_clkin1>;
954 clock-names = "sysclk";
955 status = "disabled";
956 };
957
818 omap_control_usb2phy1: control-phy@4a002300 { 958 omap_control_usb2phy1: control-phy@4a002300 {
819 compatible = "ti,control-phy-usb2"; 959 compatible = "ti,control-phy-usb2";
820 reg = <0x4a002300 0x4>; 960 reg = <0x4a002300 0x4>;
@@ -885,7 +1025,7 @@
885 compatible = "ti,dwc3"; 1025 compatible = "ti,dwc3";
886 ti,hwmods = "usb_otg_ss1"; 1026 ti,hwmods = "usb_otg_ss1";
887 reg = <0x48880000 0x10000>; 1027 reg = <0x48880000 0x10000>;
888 interrupts = <0 77 4>; 1028 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
889 #address-cells = <1>; 1029 #address-cells = <1>;
890 #size-cells = <1>; 1030 #size-cells = <1>;
891 utmi-mode = <2>; 1031 utmi-mode = <2>;
@@ -893,7 +1033,7 @@
893 usb1: usb@48890000 { 1033 usb1: usb@48890000 {
894 compatible = "snps,dwc3"; 1034 compatible = "snps,dwc3";
895 reg = <0x48890000 0x17000>; 1035 reg = <0x48890000 0x17000>;
896 interrupts = <0 76 4>; 1036 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
897 phys = <&usb2_phy1>, <&usb3_phy1>; 1037 phys = <&usb2_phy1>, <&usb3_phy1>;
898 phy-names = "usb2-phy", "usb3-phy"; 1038 phy-names = "usb2-phy", "usb3-phy";
899 tx-fifo-resize; 1039 tx-fifo-resize;
@@ -906,7 +1046,7 @@
906 compatible = "ti,dwc3"; 1046 compatible = "ti,dwc3";
907 ti,hwmods = "usb_otg_ss2"; 1047 ti,hwmods = "usb_otg_ss2";
908 reg = <0x488c0000 0x10000>; 1048 reg = <0x488c0000 0x10000>;
909 interrupts = <0 92 4>; 1049 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
910 #address-cells = <1>; 1050 #address-cells = <1>;
911 #size-cells = <1>; 1051 #size-cells = <1>;
912 utmi-mode = <2>; 1052 utmi-mode = <2>;
@@ -914,7 +1054,7 @@
914 usb2: usb@488d0000 { 1054 usb2: usb@488d0000 {
915 compatible = "snps,dwc3"; 1055 compatible = "snps,dwc3";
916 reg = <0x488d0000 0x17000>; 1056 reg = <0x488d0000 0x17000>;
917 interrupts = <0 78 4>; 1057 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
918 phys = <&usb2_phy2>; 1058 phys = <&usb2_phy2>;
919 phy-names = "usb2-phy"; 1059 phy-names = "usb2-phy";
920 tx-fifo-resize; 1060 tx-fifo-resize;
@@ -928,7 +1068,7 @@
928 compatible = "ti,dwc3"; 1068 compatible = "ti,dwc3";
929 ti,hwmods = "usb_otg_ss3"; 1069 ti,hwmods = "usb_otg_ss3";
930 reg = <0x48900000 0x10000>; 1070 reg = <0x48900000 0x10000>;
931 /* interrupts = <0 TBD 4>; */ 1071 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
932 #address-cells = <1>; 1072 #address-cells = <1>;
933 #size-cells = <1>; 1073 #size-cells = <1>;
934 utmi-mode = <2>; 1074 utmi-mode = <2>;
@@ -937,7 +1077,7 @@
937 usb3: usb@48910000 { 1077 usb3: usb@48910000 {
938 compatible = "snps,dwc3"; 1078 compatible = "snps,dwc3";
939 reg = <0x48910000 0x17000>; 1079 reg = <0x48910000 0x17000>;
940 /* interrupts = <0 93 4>; */ 1080 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
941 tx-fifo-resize; 1081 tx-fifo-resize;
942 maximum-speed = "high-speed"; 1082 maximum-speed = "high-speed";
943 dr_mode = "otg"; 1083 dr_mode = "otg";
@@ -948,7 +1088,7 @@
948 compatible = "ti,dwc3"; 1088 compatible = "ti,dwc3";
949 ti,hwmods = "usb_otg_ss4"; 1089 ti,hwmods = "usb_otg_ss4";
950 reg = <0x48940000 0x10000>; 1090 reg = <0x48940000 0x10000>;
951 /* interrupts = <0 TBD 4>; */ 1091 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
952 #address-cells = <1>; 1092 #address-cells = <1>;
953 #size-cells = <1>; 1093 #size-cells = <1>;
954 utmi-mode = <2>; 1094 utmi-mode = <2>;
@@ -957,7 +1097,7 @@
957 usb4: usb@48950000 { 1097 usb4: usb@48950000 {
958 compatible = "snps,dwc3"; 1098 compatible = "snps,dwc3";
959 reg = <0x48950000 0x17000>; 1099 reg = <0x48950000 0x17000>;
960 /* interrupts = <0 TBD 4>; */ 1100 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
961 tx-fifo-resize; 1101 tx-fifo-resize;
962 maximum-speed = "high-speed"; 1102 maximum-speed = "high-speed";
963 dr_mode = "otg"; 1103 dr_mode = "otg";
@@ -967,7 +1107,7 @@
967 elm: elm@48078000 { 1107 elm: elm@48078000 {
968 compatible = "ti,am3352-elm"; 1108 compatible = "ti,am3352-elm";
969 reg = <0x48078000 0xfc0>; /* device IO registers */ 1109 reg = <0x48078000 0xfc0>; /* device IO registers */
970 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1110 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
971 ti,hwmods = "elm"; 1111 ti,hwmods = "elm";
972 status = "disabled"; 1112 status = "disabled";
973 }; 1113 };
@@ -976,7 +1116,7 @@
976 compatible = "ti,am3352-gpmc"; 1116 compatible = "ti,am3352-gpmc";
977 ti,hwmods = "gpmc"; 1117 ti,hwmods = "gpmc";
978 reg = <0x50000000 0x37c>; /* device IO registers */ 1118 reg = <0x50000000 0x37c>; /* device IO registers */
979 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1119 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
980 gpmc,num-cs = <8>; 1120 gpmc,num-cs = <8>;
981 gpmc,num-waitpins = <2>; 1121 gpmc,num-waitpins = <2>;
982 #address-cells = <2>; 1122 #address-cells = <2>;
@@ -994,6 +1134,17 @@
994 clock-names = "fck"; 1134 clock-names = "fck";
995 status = "disabled"; 1135 status = "disabled";
996 }; 1136 };
1137
1138 crossbar_mpu: crossbar@4a020000 {
1139 compatible = "ti,irq-crossbar";
1140 reg = <0x4a002a48 0x130>;
1141 ti,max-irqs = <160>;
1142 ti,max-crossbar-sources = <MAX_SOURCES>;
1143 ti,reg-size = <2>;
1144 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1145 ti,irqs-skip = <10 133 139 140>;
1146 ti,irqs-safe-map = <0>;
1147 };
997 }; 1148 };
998}; 1149};
999 1150
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index c90c76de84d6..b987c4347911 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1152,7 +1152,7 @@
1152 1152
1153 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { 1153 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1154 compatible = "ti,mux-clock"; 1154 compatible = "ti,mux-clock";
1155 clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; 1155 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1156 #clock-cells = <0>; 1156 #clock-cells = <0>;
1157 reg = <0x021c 0x4>; 1157 reg = <0x021c 0x4>;
1158 ti,bit-shift = <7>; 1158 ti,bit-shift = <7>;
@@ -1165,16 +1165,33 @@
1165 reg = <0x021c>, <0x0220>; 1165 reg = <0x021c>, <0x0220>;
1166 }; 1166 };
1167 1167
1168 optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1169 compatible = "ti,gate-clock";
1170 clocks = <&sys_32k_ck>;
1171 #clock-cells = <0>;
1172 reg = <0x13b0>;
1173 ti,bit-shift = <8>;
1174 };
1175
1176 optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1177 compatible = "ti,gate-clock";
1178 clocks = <&sys_32k_ck>;
1179 #clock-cells = <0>;
1180 reg = <0x13b8>;
1181 ti,bit-shift = <8>;
1182 };
1183
1168 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { 1184 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1169 compatible = "ti,divider-clock"; 1185 compatible = "ti,divider-clock";
1170 clocks = <&apll_pcie_ck>; 1186 clocks = <&apll_pcie_ck>;
1171 #clock-cells = <0>; 1187 #clock-cells = <0>;
1172 reg = <0x021c>; 1188 reg = <0x021c>;
1189 ti,dividers = <2>, <1>;
1173 ti,bit-shift = <8>; 1190 ti,bit-shift = <8>;
1174 ti,max-div = <2>; 1191 ti,max-div = <2>;
1175 }; 1192 };
1176 1193
1177 optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { 1194 optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1178 compatible = "ti,gate-clock"; 1195 compatible = "ti,gate-clock";
1179 clocks = <&apll_pcie_ck>; 1196 clocks = <&apll_pcie_ck>;
1180 #clock-cells = <0>; 1197 #clock-cells = <0>;
@@ -1182,7 +1199,15 @@
1182 ti,bit-shift = <9>; 1199 ti,bit-shift = <9>;
1183 }; 1200 };
1184 1201
1185 optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { 1202 optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1203 compatible = "ti,gate-clock";
1204 clocks = <&apll_pcie_ck>;
1205 #clock-cells = <0>;
1206 reg = <0x13b8>;
1207 ti,bit-shift = <9>;
1208 };
1209
1210 optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1186 compatible = "ti,gate-clock"; 1211 compatible = "ti,gate-clock";
1187 clocks = <&optfclk_pciephy_div>; 1212 clocks = <&optfclk_pciephy_div>;
1188 #clock-cells = <0>; 1213 #clock-cells = <0>;
@@ -1190,6 +1215,14 @@
1190 ti,bit-shift = <10>; 1215 ti,bit-shift = <10>;
1191 }; 1216 };
1192 1217
1218 optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1219 compatible = "ti,gate-clock";
1220 clocks = <&optfclk_pciephy_div>;
1221 #clock-cells = <0>;
1222 reg = <0x13b8>;
1223 ti,bit-shift = <10>;
1224 };
1225
1193 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { 1226 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1194 #clock-cells = <0>; 1227 #clock-cells = <0>;
1195 compatible = "fixed-factor-clock"; 1228 compatible = "fixed-factor-clock";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index e83b0468080c..2ad3e3b29411 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -182,3 +182,6 @@
182&i2c2 { 182&i2c2 {
183 compatible = "ti,omap2420-i2c"; 183 compatible = "ti,omap2420-i2c";
184}; 184};
185
186/include/ "omap24xx-clocks.dtsi"
187/include/ "omap2420-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index c4e8013801ee..f9ab99d5c951 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -288,3 +288,6 @@
288&i2c2 { 288&i2c2 {
289 compatible = "ti,omap2430-i2c"; 289 compatible = "ti,omap2430-i2c";
290}; 290};
291
292/include/ "omap24xx-clocks.dtsi"
293/include/ "omap2430-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 1e1b05768cec..159720d6c956 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -100,15 +100,33 @@
100 }; 100 };
101 }; 101 };
102 }; 102 };
103
104 sound: sound {
105 compatible = "ti,abe-twl6040";
106 ti,model = "omap5-uevm";
107
108 ti,mclk-freq = <19200000>;
109
110 ti,mcpdm = <&mcpdm>;
111
112 ti,twl6040 = <&twl6040>;
113
114 /* Audio routing */
115 ti,audio-routing =
116 "Headset Stereophone", "HSOL",
117 "Headset Stereophone", "HSOR",
118 "Line Out", "AUXL",
119 "Line Out", "AUXR",
120 "HSMIC", "Headset Mic",
121 "Headset Mic", "Headset Mic Bias",
122 "AFML", "Line In",
123 "AFMR", "Line In";
124 };
103}; 125};
104 126
105&omap5_pmx_core { 127&omap5_pmx_core {
106 pinctrl-names = "default"; 128 pinctrl-names = "default";
107 pinctrl-0 = < 129 pinctrl-0 = <
108 &twl6040_pins
109 &mcpdm_pins
110 &mcbsp1_pins
111 &mcbsp2_pins
112 &usbhost_pins 130 &usbhost_pins
113 &led_gpio_pins 131 &led_gpio_pins
114 >; 132 >;
@@ -306,6 +324,11 @@
306 ti,wakeup; 324 ti,wakeup;
307 }; 325 };
308 326
327 clk32kgaudio: palmas_clk32k@1 {
328 compatible = "ti,palmas-clk32kgaudio";
329 #clock-cells = <0>;
330 };
331
309 palmas_pmic { 332 palmas_pmic {
310 compatible = "ti,palmas-pmic"; 333 compatible = "ti,palmas-pmic";
311 interrupt-parent = <&palmas>; 334 interrupt-parent = <&palmas>;
@@ -489,6 +512,25 @@
489 }; 512 };
490 }; 513 };
491 }; 514 };
515
516 twl6040: twl@4b {
517 compatible = "ti,twl6040";
518 reg = <0x4b>;
519
520 pinctrl-names = "default";
521 pinctrl-0 = <&twl6040_pins>;
522
523 interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
524 interrupt-parent = <&gic>;
525 ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */
526
527 vio-supply = <&smps7_reg>;
528 v2v1-supply = <&smps9_reg>;
529 enable-active-high;
530
531 clocks = <&clk32kgaudio>;
532 clock-names = "clk32k";
533 };
492}; 534};
493 535
494&i2c5 { 536&i2c5 {
@@ -505,8 +547,22 @@
505 }; 547 };
506}; 548};
507 549
508&mcbsp3 { 550&mcpdm {
509 status = "disabled"; 551 pinctrl-names = "default";
552 pinctrl-0 = <&mcpdm_pins>;
553 status = "okay";
554};
555
556&mcbsp1 {
557 pinctrl-names = "default";
558 pinctrl-0 = <&mcbsp1_pins>;
559 status = "okay";
560};
561
562&mcbsp2 {
563 pinctrl-names = "default";
564 pinctrl-0 = <&mcbsp2_pins>;
565 status = "okay";
510}; 566};
511 567
512&usbhshost { 568&usbhshost {
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 536a137863cb..f650f00e8cee 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -180,6 +180,7 @@ CONFIG_TWL4030_WATCHDOG=y
180CONFIG_MFD_SYSCON=y 180CONFIG_MFD_SYSCON=y
181CONFIG_MFD_PALMAS=y 181CONFIG_MFD_PALMAS=y
182CONFIG_MFD_TPS65217=y 182CONFIG_MFD_TPS65217=y
183CONFIG_MFD_TPS65218=y
183CONFIG_MFD_TPS65910=y 184CONFIG_MFD_TPS65910=y
184CONFIG_TWL6040_CORE=y 185CONFIG_TWL6040_CORE=y
185CONFIG_REGULATOR_FIXED_VOLTAGE=y 186CONFIG_REGULATOR_FIXED_VOLTAGE=y
@@ -188,6 +189,7 @@ CONFIG_REGULATOR_TI_ABB=y
188CONFIG_REGULATOR_TPS65023=y 189CONFIG_REGULATOR_TPS65023=y
189CONFIG_REGULATOR_TPS6507X=y 190CONFIG_REGULATOR_TPS6507X=y
190CONFIG_REGULATOR_TPS65217=y 191CONFIG_REGULATOR_TPS65217=y
192CONFIG_REGULATOR_TPS65218=y
191CONFIG_REGULATOR_TPS65910=y 193CONFIG_REGULATOR_TPS65910=y
192CONFIG_REGULATOR_TWL4030=y 194CONFIG_REGULATOR_TWL4030=y
193CONFIG_REGULATOR_PBIAS=y 195CONFIG_REGULATOR_PBIAS=y
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8ca99e9321e3..06bbadc63a65 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -176,13 +176,11 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
176 176
177# Clock framework 177# Clock framework
178obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 178obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
179obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
180obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o 179obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
181obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o 180obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
182obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o 181obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
183obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o 182obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
184obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o 183obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
185obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
186obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o 184obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
187obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o 185obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
188obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 186obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
deleted file mode 100644
index 3662f4d4c8ea..000000000000
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ /dev/null
@@ -1,1931 +0,0 @@
1/*
2 * OMAP2420 clock data
3 *
4 * Copyright (C) 2005-2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/clk-private.h>
21#include <linux/list.h>
22
23#include "soc.h"
24#include "iomap.h"
25#include "clock.h"
26#include "clock2xxx.h"
27#include "opp2xxx.h"
28#include "cm2xxx.h"
29#include "prm2xxx.h"
30#include "prm-regbits-24xx.h"
31#include "cm-regbits-24xx.h"
32#include "sdrc.h"
33#include "control.h"
34
35#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
36
37/*
38 * 2420 clock tree.
39 *
40 * NOTE:In many cases here we are assigning a 'default' parent. In
41 * many cases the parent is selectable. The set parent calls will
42 * also switch sources.
43 *
44 * Several sources are given initial rates which may be wrong, this will
45 * be fixed up in the init func.
46 *
47 * Things are broadly separated below by clock domains. It is
48 * noteworthy that most peripherals have dependencies on multiple clock
49 * domains. Many get their interface clocks from the L4 domain, but get
50 * functional clocks from fixed sources or other core domain derived
51 * clocks.
52 */
53
54DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
55
56DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
57
58DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
59
60static struct clk osc_ck;
61
62static const struct clk_ops osc_ck_ops = {
63 .recalc_rate = &omap2_osc_clk_recalc,
64};
65
66static struct clk_hw_omap osc_ck_hw = {
67 .hw = {
68 .clk = &osc_ck,
69 },
70};
71
72static struct clk osc_ck = {
73 .name = "osc_ck",
74 .ops = &osc_ck_ops,
75 .hw = &osc_ck_hw.hw,
76 .flags = CLK_IS_ROOT,
77};
78
79DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
80
81static struct clk sys_ck;
82
83static const char *sys_ck_parent_names[] = {
84 "osc_ck",
85};
86
87static const struct clk_ops sys_ck_ops = {
88 .init = &omap2_init_clk_clkdm,
89 .recalc_rate = &omap2xxx_sys_clk_recalc,
90};
91
92DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
93DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
94
95static struct dpll_data dpll_dd = {
96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
97 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
98 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
99 .clk_bypass = &sys_ck,
100 .clk_ref = &sys_ck,
101 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
102 .enable_mask = OMAP24XX_EN_DPLL_MASK,
103 .max_multiplier = 1023,
104 .min_divider = 1,
105 .max_divider = 16,
106};
107
108static struct clk dpll_ck;
109
110static const char *dpll_ck_parent_names[] = {
111 "sys_ck",
112};
113
114static const struct clk_ops dpll_ck_ops = {
115 .init = &omap2_init_clk_clkdm,
116 .get_parent = &omap2_init_dpll_parent,
117 .recalc_rate = &omap2_dpllcore_recalc,
118 .round_rate = &omap2_dpll_round_rate,
119 .set_rate = &omap2_reprogram_dpllcore,
120};
121
122static struct clk_hw_omap dpll_ck_hw = {
123 .hw = {
124 .clk = &dpll_ck,
125 },
126 .ops = &clkhwops_omap2xxx_dpll,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
129};
130
131DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
132
133static struct clk core_ck;
134
135static const char *core_ck_parent_names[] = {
136 "dpll_ck",
137};
138
139static const struct clk_ops core_ck_ops = {
140 .init = &omap2_init_clk_clkdm,
141};
142
143DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
144DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
145
146DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
147 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
148 OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
149 CLK_DIVIDER_ONE_BASED, NULL);
150
151DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
153 OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
155
156static struct clk aes_ick;
157
158static const char *aes_ick_parent_names[] = {
159 "l4_ck",
160};
161
162static const struct clk_ops aes_ick_ops = {
163 .init = &omap2_init_clk_clkdm,
164 .enable = &omap2_dflt_clk_enable,
165 .disable = &omap2_dflt_clk_disable,
166 .is_enabled = &omap2_dflt_clk_is_enabled,
167};
168
169static struct clk_hw_omap aes_ick_hw = {
170 .hw = {
171 .clk = &aes_ick,
172 },
173 .ops = &clkhwops_iclk_wait,
174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
175 .enable_bit = OMAP24XX_EN_AES_SHIFT,
176 .clkdm_name = "core_l4_clkdm",
177};
178
179DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
180
181static struct clk apll54_ck;
182
183static const struct clk_ops apll54_ck_ops = {
184 .init = &omap2_init_clk_clkdm,
185 .enable = &omap2_clk_apll54_enable,
186 .disable = &omap2_clk_apll54_disable,
187 .recalc_rate = &omap2_clk_apll54_recalc,
188};
189
190static struct clk_hw_omap apll54_ck_hw = {
191 .hw = {
192 .clk = &apll54_ck,
193 },
194 .ops = &clkhwops_apll54,
195 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
196 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
197 .flags = ENABLE_ON_INIT,
198 .clkdm_name = "wkup_clkdm",
199};
200
201DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
202
203static struct clk apll96_ck;
204
205static const struct clk_ops apll96_ck_ops = {
206 .init = &omap2_init_clk_clkdm,
207 .enable = &omap2_clk_apll96_enable,
208 .disable = &omap2_clk_apll96_disable,
209 .recalc_rate = &omap2_clk_apll96_recalc,
210};
211
212static struct clk_hw_omap apll96_ck_hw = {
213 .hw = {
214 .clk = &apll96_ck,
215 },
216 .ops = &clkhwops_apll96,
217 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
218 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
219 .flags = ENABLE_ON_INIT,
220 .clkdm_name = "wkup_clkdm",
221};
222
223DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
224
225static struct clk func_96m_ck;
226
227static const char *func_96m_ck_parent_names[] = {
228 "apll96_ck",
229};
230
231DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
232DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
233
234static struct clk cam_fck;
235
236static const char *cam_fck_parent_names[] = {
237 "func_96m_ck",
238};
239
240static struct clk_hw_omap cam_fck_hw = {
241 .hw = {
242 .clk = &cam_fck,
243 },
244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
245 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
246 .clkdm_name = "core_l3_clkdm",
247};
248
249DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
250
251static struct clk cam_ick;
252
253static struct clk_hw_omap cam_ick_hw = {
254 .hw = {
255 .clk = &cam_ick,
256 },
257 .ops = &clkhwops_iclk,
258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
259 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
260 .clkdm_name = "core_l4_clkdm",
261};
262
263DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
264
265static struct clk des_ick;
266
267static struct clk_hw_omap des_ick_hw = {
268 .hw = {
269 .clk = &des_ick,
270 },
271 .ops = &clkhwops_iclk_wait,
272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
273 .enable_bit = OMAP24XX_EN_DES_SHIFT,
274 .clkdm_name = "core_l4_clkdm",
275};
276
277DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
278
279static const struct clksel_rate dsp_fck_core_rates[] = {
280 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
281 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
282 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
283 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
284 { .div = 6, .val = 6, .flags = RATE_IN_242X },
285 { .div = 8, .val = 8, .flags = RATE_IN_242X },
286 { .div = 12, .val = 12, .flags = RATE_IN_242X },
287 { .div = 0 }
288};
289
290static const struct clksel dsp_fck_clksel[] = {
291 { .parent = &core_ck, .rates = dsp_fck_core_rates },
292 { .parent = NULL },
293};
294
295static const char *dsp_fck_parent_names[] = {
296 "core_ck",
297};
298
299static const struct clk_ops dsp_fck_ops = {
300 .init = &omap2_init_clk_clkdm,
301 .enable = &omap2_dflt_clk_enable,
302 .disable = &omap2_dflt_clk_disable,
303 .is_enabled = &omap2_dflt_clk_is_enabled,
304 .recalc_rate = &omap2_clksel_recalc,
305 .set_rate = &omap2_clksel_set_rate,
306 .round_rate = &omap2_clksel_round_rate,
307};
308
309DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
310 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
311 OMAP24XX_CLKSEL_DSP_MASK,
312 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
313 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
314 dsp_fck_parent_names, dsp_fck_ops);
315
316static const struct clksel dsp_ick_clksel[] = {
317 { .parent = &dsp_fck, .rates = dsp_ick_rates },
318 { .parent = NULL },
319};
320
321static const char *dsp_ick_parent_names[] = {
322 "dsp_fck",
323};
324
325DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
326 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
327 OMAP24XX_CLKSEL_DSP_IF_MASK,
328 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
329 OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
330 dsp_ick_parent_names, dsp_fck_ops);
331
332static const struct clksel_rate dss1_fck_sys_rates[] = {
333 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
334 { .div = 0 }
335};
336
337static const struct clksel_rate dss1_fck_core_rates[] = {
338 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
339 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
340 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
341 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
342 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
343 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
344 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
345 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
346 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
347 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
348 { .div = 0 }
349};
350
351static const struct clksel dss1_fck_clksel[] = {
352 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
353 { .parent = &core_ck, .rates = dss1_fck_core_rates },
354 { .parent = NULL },
355};
356
357static const char *dss1_fck_parent_names[] = {
358 "sys_ck", "core_ck",
359};
360
361static struct clk dss1_fck;
362
363static const struct clk_ops dss1_fck_ops = {
364 .init = &omap2_init_clk_clkdm,
365 .enable = &omap2_dflt_clk_enable,
366 .disable = &omap2_dflt_clk_disable,
367 .is_enabled = &omap2_dflt_clk_is_enabled,
368 .recalc_rate = &omap2_clksel_recalc,
369 .get_parent = &omap2_clksel_find_parent_index,
370 .set_parent = &omap2_clksel_set_parent,
371};
372
373DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
374 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
375 OMAP24XX_CLKSEL_DSS1_MASK,
376 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
377 OMAP24XX_EN_DSS1_SHIFT, NULL,
378 dss1_fck_parent_names, dss1_fck_ops);
379
380static const struct clksel_rate dss2_fck_sys_rates[] = {
381 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
382 { .div = 0 }
383};
384
385static const struct clksel_rate dss2_fck_48m_rates[] = {
386 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
387 { .div = 0 }
388};
389
390static const struct clksel_rate func_48m_apll96_rates[] = {
391 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
392 { .div = 0 }
393};
394
395static const struct clksel_rate func_48m_alt_rates[] = {
396 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
397 { .div = 0 }
398};
399
400static const struct clksel func_48m_clksel[] = {
401 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
402 { .parent = &alt_ck, .rates = func_48m_alt_rates },
403 { .parent = NULL },
404};
405
406static const char *func_48m_ck_parent_names[] = {
407 "apll96_ck", "alt_ck",
408};
409
410static struct clk func_48m_ck;
411
412static const struct clk_ops func_48m_ck_ops = {
413 .init = &omap2_init_clk_clkdm,
414 .recalc_rate = &omap2_clksel_recalc,
415 .set_rate = &omap2_clksel_set_rate,
416 .round_rate = &omap2_clksel_round_rate,
417 .get_parent = &omap2_clksel_find_parent_index,
418 .set_parent = &omap2_clksel_set_parent,
419};
420
421static struct clk_hw_omap func_48m_ck_hw = {
422 .hw = {
423 .clk = &func_48m_ck,
424 },
425 .clksel = func_48m_clksel,
426 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
427 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
428 .clkdm_name = "wkup_clkdm",
429};
430
431DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
432
433static const struct clksel dss2_fck_clksel[] = {
434 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
435 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
436 { .parent = NULL },
437};
438
439static const char *dss2_fck_parent_names[] = {
440 "sys_ck", "func_48m_ck",
441};
442
443DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
444 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
445 OMAP24XX_CLKSEL_DSS2_MASK,
446 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
447 OMAP24XX_EN_DSS2_SHIFT, NULL,
448 dss2_fck_parent_names, dss1_fck_ops);
449
450static const char *func_54m_ck_parent_names[] = {
451 "apll54_ck", "alt_ck",
452};
453
454DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
455 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
456 OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
457 0x0, NULL);
458
459static struct clk dss_54m_fck;
460
461static const char *dss_54m_fck_parent_names[] = {
462 "func_54m_ck",
463};
464
465static struct clk_hw_omap dss_54m_fck_hw = {
466 .hw = {
467 .clk = &dss_54m_fck,
468 },
469 .ops = &clkhwops_wait,
470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
471 .enable_bit = OMAP24XX_EN_TV_SHIFT,
472 .clkdm_name = "dss_clkdm",
473};
474
475DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
476
477static struct clk dss_ick;
478
479static struct clk_hw_omap dss_ick_hw = {
480 .hw = {
481 .clk = &dss_ick,
482 },
483 .ops = &clkhwops_iclk,
484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
485 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
486 .clkdm_name = "dss_clkdm",
487};
488
489DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
490
491static struct clk eac_fck;
492
493static struct clk_hw_omap eac_fck_hw = {
494 .hw = {
495 .clk = &eac_fck,
496 },
497 .ops = &clkhwops_wait,
498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
499 .enable_bit = OMAP2420_EN_EAC_SHIFT,
500 .clkdm_name = "core_l4_clkdm",
501};
502
503DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
504
505static struct clk eac_ick;
506
507static struct clk_hw_omap eac_ick_hw = {
508 .hw = {
509 .clk = &eac_ick,
510 },
511 .ops = &clkhwops_iclk_wait,
512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
513 .enable_bit = OMAP2420_EN_EAC_SHIFT,
514 .clkdm_name = "core_l4_clkdm",
515};
516
517DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
518
519static struct clk emul_ck;
520
521static struct clk_hw_omap emul_ck_hw = {
522 .hw = {
523 .clk = &emul_ck,
524 },
525 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
526 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
527 .clkdm_name = "wkup_clkdm",
528};
529
530DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
531
532DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
533
534static struct clk fac_fck;
535
536static const char *fac_fck_parent_names[] = {
537 "func_12m_ck",
538};
539
540static struct clk_hw_omap fac_fck_hw = {
541 .hw = {
542 .clk = &fac_fck,
543 },
544 .ops = &clkhwops_wait,
545 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
546 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
547 .clkdm_name = "core_l4_clkdm",
548};
549
550DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
551
552static struct clk fac_ick;
553
554static struct clk_hw_omap fac_ick_hw = {
555 .hw = {
556 .clk = &fac_ick,
557 },
558 .ops = &clkhwops_iclk_wait,
559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
560 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
561 .clkdm_name = "core_l4_clkdm",
562};
563
564DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
565
566static const struct clksel gfx_fck_clksel[] = {
567 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
568 { .parent = NULL },
569};
570
571static const char *gfx_2d_fck_parent_names[] = {
572 "core_l3_ck",
573};
574
575DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
576 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
577 OMAP_CLKSEL_GFX_MASK,
578 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
579 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
580 gfx_2d_fck_parent_names, dsp_fck_ops);
581
582DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
583 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
584 OMAP_CLKSEL_GFX_MASK,
585 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
586 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
587 gfx_2d_fck_parent_names, dsp_fck_ops);
588
589static struct clk gfx_ick;
590
591static const char *gfx_ick_parent_names[] = {
592 "core_l3_ck",
593};
594
595static struct clk_hw_omap gfx_ick_hw = {
596 .hw = {
597 .clk = &gfx_ick,
598 },
599 .ops = &clkhwops_wait,
600 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
601 .enable_bit = OMAP_EN_GFX_SHIFT,
602 .clkdm_name = "gfx_clkdm",
603};
604
605DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
606
607static struct clk gpios_fck;
608
609static const char *gpios_fck_parent_names[] = {
610 "func_32k_ck",
611};
612
613static struct clk_hw_omap gpios_fck_hw = {
614 .hw = {
615 .clk = &gpios_fck,
616 },
617 .ops = &clkhwops_wait,
618 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
619 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
620 .clkdm_name = "wkup_clkdm",
621};
622
623DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
624
625static struct clk gpios_ick;
626
627static const char *gpios_ick_parent_names[] = {
628 "sys_ck",
629};
630
631static struct clk_hw_omap gpios_ick_hw = {
632 .hw = {
633 .clk = &gpios_ick,
634 },
635 .ops = &clkhwops_iclk_wait,
636 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
637 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
638 .clkdm_name = "wkup_clkdm",
639};
640
641DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
642
643static struct clk gpmc_fck;
644
645static struct clk_hw_omap gpmc_fck_hw = {
646 .hw = {
647 .clk = &gpmc_fck,
648 },
649 .ops = &clkhwops_iclk,
650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
651 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
652 .flags = ENABLE_ON_INIT,
653 .clkdm_name = "core_l3_clkdm",
654};
655
656DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
657
658static const struct clksel_rate gpt_alt_rates[] = {
659 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
660 { .div = 0 }
661};
662
663static const struct clksel omap24xx_gpt_clksel[] = {
664 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
665 { .parent = &sys_ck, .rates = gpt_sys_rates },
666 { .parent = &alt_ck, .rates = gpt_alt_rates },
667 { .parent = NULL },
668};
669
670static const char *gpt10_fck_parent_names[] = {
671 "func_32k_ck", "sys_ck", "alt_ck",
672};
673
674DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
675 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
676 OMAP24XX_CLKSEL_GPT10_MASK,
677 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
678 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
679 gpt10_fck_parent_names, dss1_fck_ops);
680
681static struct clk gpt10_ick;
682
683static struct clk_hw_omap gpt10_ick_hw = {
684 .hw = {
685 .clk = &gpt10_ick,
686 },
687 .ops = &clkhwops_iclk_wait,
688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
689 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
690 .clkdm_name = "core_l4_clkdm",
691};
692
693DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
694
695DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
696 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
697 OMAP24XX_CLKSEL_GPT11_MASK,
698 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
699 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
700 gpt10_fck_parent_names, dss1_fck_ops);
701
702static struct clk gpt11_ick;
703
704static struct clk_hw_omap gpt11_ick_hw = {
705 .hw = {
706 .clk = &gpt11_ick,
707 },
708 .ops = &clkhwops_iclk_wait,
709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
710 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
711 .clkdm_name = "core_l4_clkdm",
712};
713
714DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
715
716DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
717 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
718 OMAP24XX_CLKSEL_GPT12_MASK,
719 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
720 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
721 gpt10_fck_parent_names, dss1_fck_ops);
722
723static struct clk gpt12_ick;
724
725static struct clk_hw_omap gpt12_ick_hw = {
726 .hw = {
727 .clk = &gpt12_ick,
728 },
729 .ops = &clkhwops_iclk_wait,
730 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
731 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
732 .clkdm_name = "core_l4_clkdm",
733};
734
735DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
736
737static const struct clk_ops gpt1_fck_ops = {
738 .init = &omap2_init_clk_clkdm,
739 .enable = &omap2_dflt_clk_enable,
740 .disable = &omap2_dflt_clk_disable,
741 .is_enabled = &omap2_dflt_clk_is_enabled,
742 .recalc_rate = &omap2_clksel_recalc,
743 .set_rate = &omap2_clksel_set_rate,
744 .round_rate = &omap2_clksel_round_rate,
745 .get_parent = &omap2_clksel_find_parent_index,
746 .set_parent = &omap2_clksel_set_parent,
747};
748
749DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
750 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
751 OMAP24XX_CLKSEL_GPT1_MASK,
752 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
753 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
754 gpt10_fck_parent_names, gpt1_fck_ops);
755
756static struct clk gpt1_ick;
757
758static struct clk_hw_omap gpt1_ick_hw = {
759 .hw = {
760 .clk = &gpt1_ick,
761 },
762 .ops = &clkhwops_iclk_wait,
763 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
764 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
765 .clkdm_name = "wkup_clkdm",
766};
767
768DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
769
770DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
771 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
772 OMAP24XX_CLKSEL_GPT2_MASK,
773 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
774 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
775 gpt10_fck_parent_names, dss1_fck_ops);
776
777static struct clk gpt2_ick;
778
779static struct clk_hw_omap gpt2_ick_hw = {
780 .hw = {
781 .clk = &gpt2_ick,
782 },
783 .ops = &clkhwops_iclk_wait,
784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
785 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
786 .clkdm_name = "core_l4_clkdm",
787};
788
789DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
790
791DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
792 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
793 OMAP24XX_CLKSEL_GPT3_MASK,
794 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
795 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
796 gpt10_fck_parent_names, dss1_fck_ops);
797
798static struct clk gpt3_ick;
799
800static struct clk_hw_omap gpt3_ick_hw = {
801 .hw = {
802 .clk = &gpt3_ick,
803 },
804 .ops = &clkhwops_iclk_wait,
805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
806 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
807 .clkdm_name = "core_l4_clkdm",
808};
809
810DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
811
812DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
813 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
814 OMAP24XX_CLKSEL_GPT4_MASK,
815 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
816 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
817 gpt10_fck_parent_names, dss1_fck_ops);
818
819static struct clk gpt4_ick;
820
821static struct clk_hw_omap gpt4_ick_hw = {
822 .hw = {
823 .clk = &gpt4_ick,
824 },
825 .ops = &clkhwops_iclk_wait,
826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
827 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
828 .clkdm_name = "core_l4_clkdm",
829};
830
831DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
832
833DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
834 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
835 OMAP24XX_CLKSEL_GPT5_MASK,
836 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
837 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
838 gpt10_fck_parent_names, dss1_fck_ops);
839
840static struct clk gpt5_ick;
841
842static struct clk_hw_omap gpt5_ick_hw = {
843 .hw = {
844 .clk = &gpt5_ick,
845 },
846 .ops = &clkhwops_iclk_wait,
847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
848 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
849 .clkdm_name = "core_l4_clkdm",
850};
851
852DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
853
854DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
855 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
856 OMAP24XX_CLKSEL_GPT6_MASK,
857 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
858 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
859 gpt10_fck_parent_names, dss1_fck_ops);
860
861static struct clk gpt6_ick;
862
863static struct clk_hw_omap gpt6_ick_hw = {
864 .hw = {
865 .clk = &gpt6_ick,
866 },
867 .ops = &clkhwops_iclk_wait,
868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
869 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
870 .clkdm_name = "core_l4_clkdm",
871};
872
873DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
874
875DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
876 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
877 OMAP24XX_CLKSEL_GPT7_MASK,
878 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
879 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
880 gpt10_fck_parent_names, dss1_fck_ops);
881
882static struct clk gpt7_ick;
883
884static struct clk_hw_omap gpt7_ick_hw = {
885 .hw = {
886 .clk = &gpt7_ick,
887 },
888 .ops = &clkhwops_iclk_wait,
889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
890 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
891 .clkdm_name = "core_l4_clkdm",
892};
893
894DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
895
896DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
897 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
898 OMAP24XX_CLKSEL_GPT8_MASK,
899 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
900 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
901 gpt10_fck_parent_names, dss1_fck_ops);
902
903static struct clk gpt8_ick;
904
905static struct clk_hw_omap gpt8_ick_hw = {
906 .hw = {
907 .clk = &gpt8_ick,
908 },
909 .ops = &clkhwops_iclk_wait,
910 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
911 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
912 .clkdm_name = "core_l4_clkdm",
913};
914
915DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
916
917DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
918 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
919 OMAP24XX_CLKSEL_GPT9_MASK,
920 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
921 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
922 gpt10_fck_parent_names, dss1_fck_ops);
923
924static struct clk gpt9_ick;
925
926static struct clk_hw_omap gpt9_ick_hw = {
927 .hw = {
928 .clk = &gpt9_ick,
929 },
930 .ops = &clkhwops_iclk_wait,
931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
932 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
933 .clkdm_name = "core_l4_clkdm",
934};
935
936DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
937
938static struct clk hdq_fck;
939
940static struct clk_hw_omap hdq_fck_hw = {
941 .hw = {
942 .clk = &hdq_fck,
943 },
944 .ops = &clkhwops_wait,
945 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
946 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
947 .clkdm_name = "core_l4_clkdm",
948};
949
950DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
951
952static struct clk hdq_ick;
953
954static struct clk_hw_omap hdq_ick_hw = {
955 .hw = {
956 .clk = &hdq_ick,
957 },
958 .ops = &clkhwops_iclk_wait,
959 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
960 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
961 .clkdm_name = "core_l4_clkdm",
962};
963
964DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
965
966static struct clk i2c1_fck;
967
968static struct clk_hw_omap i2c1_fck_hw = {
969 .hw = {
970 .clk = &i2c1_fck,
971 },
972 .ops = &clkhwops_wait,
973 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
974 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
975 .clkdm_name = "core_l4_clkdm",
976};
977
978DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
979
980static struct clk i2c1_ick;
981
982static struct clk_hw_omap i2c1_ick_hw = {
983 .hw = {
984 .clk = &i2c1_ick,
985 },
986 .ops = &clkhwops_iclk_wait,
987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
988 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
989 .clkdm_name = "core_l4_clkdm",
990};
991
992DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
993
994static struct clk i2c2_fck;
995
996static struct clk_hw_omap i2c2_fck_hw = {
997 .hw = {
998 .clk = &i2c2_fck,
999 },
1000 .ops = &clkhwops_wait,
1001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1002 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1003 .clkdm_name = "core_l4_clkdm",
1004};
1005
1006DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
1007
1008static struct clk i2c2_ick;
1009
1010static struct clk_hw_omap i2c2_ick_hw = {
1011 .hw = {
1012 .clk = &i2c2_ick,
1013 },
1014 .ops = &clkhwops_iclk_wait,
1015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1016 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1017 .clkdm_name = "core_l4_clkdm",
1018};
1019
1020DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
1021
1022DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
1023 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1024 OMAP2420_CLKSEL_IVA_MASK,
1025 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1026 OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
1027 dsp_fck_parent_names, dsp_fck_ops);
1028
1029static struct clk iva1_mpu_int_ifck;
1030
1031static const char *iva1_mpu_int_ifck_parent_names[] = {
1032 "iva1_ifck",
1033};
1034
1035static const struct clk_ops iva1_mpu_int_ifck_ops = {
1036 .init = &omap2_init_clk_clkdm,
1037 .enable = &omap2_dflt_clk_enable,
1038 .disable = &omap2_dflt_clk_disable,
1039 .is_enabled = &omap2_dflt_clk_is_enabled,
1040 .recalc_rate = &omap_fixed_divisor_recalc,
1041};
1042
1043static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
1044 .hw = {
1045 .clk = &iva1_mpu_int_ifck,
1046 },
1047 .ops = &clkhwops_wait,
1048 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1049 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1050 .clkdm_name = "iva1_clkdm",
1051 .fixed_div = 2,
1052};
1053
1054DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
1055 iva1_mpu_int_ifck_ops);
1056
1057static struct clk mailboxes_ick;
1058
1059static struct clk_hw_omap mailboxes_ick_hw = {
1060 .hw = {
1061 .clk = &mailboxes_ick,
1062 },
1063 .ops = &clkhwops_iclk_wait,
1064 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1065 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1066 .clkdm_name = "core_l4_clkdm",
1067};
1068
1069DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
1070
1071static const struct clksel_rate common_mcbsp_96m_rates[] = {
1072 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1073 { .div = 0 }
1074};
1075
1076static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1077 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1078 { .div = 0 }
1079};
1080
1081static const struct clksel mcbsp_fck_clksel[] = {
1082 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1083 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1084 { .parent = NULL },
1085};
1086
1087static const char *mcbsp1_fck_parent_names[] = {
1088 "func_96m_ck", "mcbsp_clks",
1089};
1090
1091DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1092 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1093 OMAP2_MCBSP1_CLKS_MASK,
1094 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1095 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
1096 mcbsp1_fck_parent_names, dss1_fck_ops);
1097
1098static struct clk mcbsp1_ick;
1099
1100static struct clk_hw_omap mcbsp1_ick_hw = {
1101 .hw = {
1102 .clk = &mcbsp1_ick,
1103 },
1104 .ops = &clkhwops_iclk_wait,
1105 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1106 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1107 .clkdm_name = "core_l4_clkdm",
1108};
1109
1110DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
1111
1112DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1113 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1114 OMAP2_MCBSP2_CLKS_MASK,
1115 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1116 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
1117 mcbsp1_fck_parent_names, dss1_fck_ops);
1118
1119static struct clk mcbsp2_ick;
1120
1121static struct clk_hw_omap mcbsp2_ick_hw = {
1122 .hw = {
1123 .clk = &mcbsp2_ick,
1124 },
1125 .ops = &clkhwops_iclk_wait,
1126 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1127 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1128 .clkdm_name = "core_l4_clkdm",
1129};
1130
1131DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
1132
1133static struct clk mcspi1_fck;
1134
1135static const char *mcspi1_fck_parent_names[] = {
1136 "func_48m_ck",
1137};
1138
1139static struct clk_hw_omap mcspi1_fck_hw = {
1140 .hw = {
1141 .clk = &mcspi1_fck,
1142 },
1143 .ops = &clkhwops_wait,
1144 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1145 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1146 .clkdm_name = "core_l4_clkdm",
1147};
1148
1149DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1150
1151static struct clk mcspi1_ick;
1152
1153static struct clk_hw_omap mcspi1_ick_hw = {
1154 .hw = {
1155 .clk = &mcspi1_ick,
1156 },
1157 .ops = &clkhwops_iclk_wait,
1158 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1159 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1160 .clkdm_name = "core_l4_clkdm",
1161};
1162
1163DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
1164
1165static struct clk mcspi2_fck;
1166
1167static struct clk_hw_omap mcspi2_fck_hw = {
1168 .hw = {
1169 .clk = &mcspi2_fck,
1170 },
1171 .ops = &clkhwops_wait,
1172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1173 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1174 .clkdm_name = "core_l4_clkdm",
1175};
1176
1177DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1178
1179static struct clk mcspi2_ick;
1180
1181static struct clk_hw_omap mcspi2_ick_hw = {
1182 .hw = {
1183 .clk = &mcspi2_ick,
1184 },
1185 .ops = &clkhwops_iclk_wait,
1186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1187 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1188 .clkdm_name = "core_l4_clkdm",
1189};
1190
1191DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
1192
1193static struct clk mmc_fck;
1194
1195static struct clk_hw_omap mmc_fck_hw = {
1196 .hw = {
1197 .clk = &mmc_fck,
1198 },
1199 .ops = &clkhwops_wait,
1200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1201 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1202 .clkdm_name = "core_l4_clkdm",
1203};
1204
1205DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
1206
1207static struct clk mmc_ick;
1208
1209static struct clk_hw_omap mmc_ick_hw = {
1210 .hw = {
1211 .clk = &mmc_ick,
1212 },
1213 .ops = &clkhwops_iclk_wait,
1214 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1215 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1216 .clkdm_name = "core_l4_clkdm",
1217};
1218
1219DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
1220
1221DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
1222 OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1223 OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
1224 CLK_DIVIDER_ONE_BASED, NULL);
1225
1226static struct clk mpu_wdt_fck;
1227
1228static struct clk_hw_omap mpu_wdt_fck_hw = {
1229 .hw = {
1230 .clk = &mpu_wdt_fck,
1231 },
1232 .ops = &clkhwops_wait,
1233 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1234 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1235 .clkdm_name = "wkup_clkdm",
1236};
1237
1238DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
1239
1240static struct clk mpu_wdt_ick;
1241
1242static struct clk_hw_omap mpu_wdt_ick_hw = {
1243 .hw = {
1244 .clk = &mpu_wdt_ick,
1245 },
1246 .ops = &clkhwops_iclk_wait,
1247 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1248 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1249 .clkdm_name = "wkup_clkdm",
1250};
1251
1252DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
1253
1254static struct clk mspro_fck;
1255
1256static struct clk_hw_omap mspro_fck_hw = {
1257 .hw = {
1258 .clk = &mspro_fck,
1259 },
1260 .ops = &clkhwops_wait,
1261 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1262 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1263 .clkdm_name = "core_l4_clkdm",
1264};
1265
1266DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
1267
1268static struct clk mspro_ick;
1269
1270static struct clk_hw_omap mspro_ick_hw = {
1271 .hw = {
1272 .clk = &mspro_ick,
1273 },
1274 .ops = &clkhwops_iclk_wait,
1275 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1276 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1277 .clkdm_name = "core_l4_clkdm",
1278};
1279
1280DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
1281
1282static struct clk omapctrl_ick;
1283
1284static struct clk_hw_omap omapctrl_ick_hw = {
1285 .hw = {
1286 .clk = &omapctrl_ick,
1287 },
1288 .ops = &clkhwops_iclk_wait,
1289 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1290 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1291 .flags = ENABLE_ON_INIT,
1292 .clkdm_name = "wkup_clkdm",
1293};
1294
1295DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
1296
1297static struct clk pka_ick;
1298
1299static struct clk_hw_omap pka_ick_hw = {
1300 .hw = {
1301 .clk = &pka_ick,
1302 },
1303 .ops = &clkhwops_iclk_wait,
1304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1305 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1306 .clkdm_name = "core_l4_clkdm",
1307};
1308
1309DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
1310
1311static struct clk rng_ick;
1312
1313static struct clk_hw_omap rng_ick_hw = {
1314 .hw = {
1315 .clk = &rng_ick,
1316 },
1317 .ops = &clkhwops_iclk_wait,
1318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1319 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1320 .clkdm_name = "core_l4_clkdm",
1321};
1322
1323DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
1324
1325static struct clk sdma_fck;
1326
1327DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
1328DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
1329
1330static struct clk sdma_ick;
1331
1332static struct clk_hw_omap sdma_ick_hw = {
1333 .hw = {
1334 .clk = &sdma_ick,
1335 },
1336 .ops = &clkhwops_iclk,
1337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1338 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1339 .clkdm_name = "core_l3_clkdm",
1340};
1341
1342DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
1343
1344static struct clk sdrc_ick;
1345
1346static struct clk_hw_omap sdrc_ick_hw = {
1347 .hw = {
1348 .clk = &sdrc_ick,
1349 },
1350 .ops = &clkhwops_iclk,
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1352 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1353 .flags = ENABLE_ON_INIT,
1354 .clkdm_name = "core_l3_clkdm",
1355};
1356
1357DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
1358
1359static struct clk sha_ick;
1360
1361static struct clk_hw_omap sha_ick_hw = {
1362 .hw = {
1363 .clk = &sha_ick,
1364 },
1365 .ops = &clkhwops_iclk_wait,
1366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1367 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1368 .clkdm_name = "core_l4_clkdm",
1369};
1370
1371DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
1372
1373static struct clk ssi_l4_ick;
1374
1375static struct clk_hw_omap ssi_l4_ick_hw = {
1376 .hw = {
1377 .clk = &ssi_l4_ick,
1378 },
1379 .ops = &clkhwops_iclk_wait,
1380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1381 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1382 .clkdm_name = "core_l4_clkdm",
1383};
1384
1385DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
1386
1387static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1388 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1389 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1390 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1391 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1392 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1393 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1394 { .div = 0 }
1395};
1396
1397static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1398 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1399 { .parent = NULL },
1400};
1401
1402static const char *ssi_ssr_sst_fck_parent_names[] = {
1403 "core_ck",
1404};
1405
1406DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
1407 ssi_ssr_sst_fck_clksel,
1408 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1409 OMAP24XX_CLKSEL_SSI_MASK,
1410 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1411 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
1412 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
1413
1414static struct clk sync_32k_ick;
1415
1416static struct clk_hw_omap sync_32k_ick_hw = {
1417 .hw = {
1418 .clk = &sync_32k_ick,
1419 },
1420 .ops = &clkhwops_iclk_wait,
1421 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1422 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1423 .flags = ENABLE_ON_INIT,
1424 .clkdm_name = "wkup_clkdm",
1425};
1426
1427DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
1428
1429static const struct clksel_rate common_clkout_src_core_rates[] = {
1430 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1431 { .div = 0 }
1432};
1433
1434static const struct clksel_rate common_clkout_src_sys_rates[] = {
1435 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1436 { .div = 0 }
1437};
1438
1439static const struct clksel_rate common_clkout_src_96m_rates[] = {
1440 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
1441 { .div = 0 }
1442};
1443
1444static const struct clksel_rate common_clkout_src_54m_rates[] = {
1445 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
1446 { .div = 0 }
1447};
1448
1449static const struct clksel common_clkout_src_clksel[] = {
1450 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
1451 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
1452 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
1453 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
1454 { .parent = NULL },
1455};
1456
1457static const char *sys_clkout_src_parent_names[] = {
1458 "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
1459};
1460
1461DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
1462 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
1463 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
1464 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1465
1466DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
1467 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
1468 OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1469
1470DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
1471 common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
1472 OMAP2420_CLKOUT2_SOURCE_MASK,
1473 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
1474 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1475
1476DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
1477 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
1478 OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1479
1480static struct clk uart1_fck;
1481
1482static struct clk_hw_omap uart1_fck_hw = {
1483 .hw = {
1484 .clk = &uart1_fck,
1485 },
1486 .ops = &clkhwops_wait,
1487 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1488 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1489 .clkdm_name = "core_l4_clkdm",
1490};
1491
1492DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1493
1494static struct clk uart1_ick;
1495
1496static struct clk_hw_omap uart1_ick_hw = {
1497 .hw = {
1498 .clk = &uart1_ick,
1499 },
1500 .ops = &clkhwops_iclk_wait,
1501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1502 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1503 .clkdm_name = "core_l4_clkdm",
1504};
1505
1506DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
1507
1508static struct clk uart2_fck;
1509
1510static struct clk_hw_omap uart2_fck_hw = {
1511 .hw = {
1512 .clk = &uart2_fck,
1513 },
1514 .ops = &clkhwops_wait,
1515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1516 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1517 .clkdm_name = "core_l4_clkdm",
1518};
1519
1520DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1521
1522static struct clk uart2_ick;
1523
1524static struct clk_hw_omap uart2_ick_hw = {
1525 .hw = {
1526 .clk = &uart2_ick,
1527 },
1528 .ops = &clkhwops_iclk_wait,
1529 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1530 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1531 .clkdm_name = "core_l4_clkdm",
1532};
1533
1534DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
1535
1536static struct clk uart3_fck;
1537
1538static struct clk_hw_omap uart3_fck_hw = {
1539 .hw = {
1540 .clk = &uart3_fck,
1541 },
1542 .ops = &clkhwops_wait,
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1544 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1545 .clkdm_name = "core_l4_clkdm",
1546};
1547
1548DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1549
1550static struct clk uart3_ick;
1551
1552static struct clk_hw_omap uart3_ick_hw = {
1553 .hw = {
1554 .clk = &uart3_ick,
1555 },
1556 .ops = &clkhwops_iclk_wait,
1557 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1558 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1559 .clkdm_name = "core_l4_clkdm",
1560};
1561
1562DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
1563
1564static struct clk usb_fck;
1565
1566static struct clk_hw_omap usb_fck_hw = {
1567 .hw = {
1568 .clk = &usb_fck,
1569 },
1570 .ops = &clkhwops_wait,
1571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1572 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1573 .clkdm_name = "core_l3_clkdm",
1574};
1575
1576DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
1577
1578static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1579 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1580 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1581 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1582 { .div = 0 }
1583};
1584
1585static const struct clksel usb_l4_ick_clksel[] = {
1586 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1587 { .parent = NULL },
1588};
1589
1590static const char *usb_l4_ick_parent_names[] = {
1591 "core_l3_ck",
1592};
1593
1594DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
1595 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1596 OMAP24XX_CLKSEL_USB_MASK,
1597 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1598 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
1599 usb_l4_ick_parent_names, dsp_fck_ops);
1600
1601static struct clk virt_prcm_set;
1602
1603static const char *virt_prcm_set_parent_names[] = {
1604 "mpu_ck",
1605};
1606
1607static const struct clk_ops virt_prcm_set_ops = {
1608 .recalc_rate = &omap2_table_mpu_recalc,
1609 .set_rate = &omap2_select_table_rate,
1610 .round_rate = &omap2_round_to_table_rate,
1611};
1612
1613DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
1614DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
1615
1616static const struct clksel_rate vlynq_fck_96m_rates[] = {
1617 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1618 { .div = 0 }
1619};
1620
1621static const struct clksel_rate vlynq_fck_core_rates[] = {
1622 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1623 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1624 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1625 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1626 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1627 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1628 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1629 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1630 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1631 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1632 { .div = 0 }
1633};
1634
1635static const struct clksel vlynq_fck_clksel[] = {
1636 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1637 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1638 { .parent = NULL },
1639};
1640
1641static const char *vlynq_fck_parent_names[] = {
1642 "func_96m_ck", "core_ck",
1643};
1644
1645DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
1646 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1647 OMAP2420_CLKSEL_VLYNQ_MASK,
1648 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1649 OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
1650 vlynq_fck_parent_names, dss1_fck_ops);
1651
1652static struct clk vlynq_ick;
1653
1654static struct clk_hw_omap vlynq_ick_hw = {
1655 .hw = {
1656 .clk = &vlynq_ick,
1657 },
1658 .ops = &clkhwops_iclk_wait,
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1660 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1661 .clkdm_name = "core_l3_clkdm",
1662};
1663
1664DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
1665
1666static struct clk wdt1_ick;
1667
1668static struct clk_hw_omap wdt1_ick_hw = {
1669 .hw = {
1670 .clk = &wdt1_ick,
1671 },
1672 .ops = &clkhwops_iclk_wait,
1673 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1674 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1675 .clkdm_name = "wkup_clkdm",
1676};
1677
1678DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1679
1680static struct clk wdt3_fck;
1681
1682static struct clk_hw_omap wdt3_fck_hw = {
1683 .hw = {
1684 .clk = &wdt3_fck,
1685 },
1686 .ops = &clkhwops_wait,
1687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1688 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1689 .clkdm_name = "core_l4_clkdm",
1690};
1691
1692DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
1693
1694static struct clk wdt3_ick;
1695
1696static struct clk_hw_omap wdt3_ick_hw = {
1697 .hw = {
1698 .clk = &wdt3_ick,
1699 },
1700 .ops = &clkhwops_iclk_wait,
1701 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1702 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1703 .clkdm_name = "core_l4_clkdm",
1704};
1705
1706DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
1707
1708static struct clk wdt4_fck;
1709
1710static struct clk_hw_omap wdt4_fck_hw = {
1711 .hw = {
1712 .clk = &wdt4_fck,
1713 },
1714 .ops = &clkhwops_wait,
1715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1716 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1717 .clkdm_name = "core_l4_clkdm",
1718};
1719
1720DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
1721
1722static struct clk wdt4_ick;
1723
1724static struct clk_hw_omap wdt4_ick_hw = {
1725 .hw = {
1726 .clk = &wdt4_ick,
1727 },
1728 .ops = &clkhwops_iclk_wait,
1729 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1730 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1731 .clkdm_name = "core_l4_clkdm",
1732};
1733
1734DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1735
1736/*
1737 * clkdev integration
1738 */
1739
1740static struct omap_clk omap2420_clks[] = {
1741 /* external root sources */
1742 CLK(NULL, "func_32k_ck", &func_32k_ck),
1743 CLK(NULL, "secure_32k_ck", &secure_32k_ck),
1744 CLK(NULL, "osc_ck", &osc_ck),
1745 CLK(NULL, "sys_ck", &sys_ck),
1746 CLK(NULL, "alt_ck", &alt_ck),
1747 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
1748 /* internal analog sources */
1749 CLK(NULL, "dpll_ck", &dpll_ck),
1750 CLK(NULL, "apll96_ck", &apll96_ck),
1751 CLK(NULL, "apll54_ck", &apll54_ck),
1752 /* internal prcm root sources */
1753 CLK(NULL, "func_54m_ck", &func_54m_ck),
1754 CLK(NULL, "core_ck", &core_ck),
1755 CLK(NULL, "func_96m_ck", &func_96m_ck),
1756 CLK(NULL, "func_48m_ck", &func_48m_ck),
1757 CLK(NULL, "func_12m_ck", &func_12m_ck),
1758 CLK(NULL, "sys_clkout_src", &sys_clkout_src),
1759 CLK(NULL, "sys_clkout", &sys_clkout),
1760 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src),
1761 CLK(NULL, "sys_clkout2", &sys_clkout2),
1762 CLK(NULL, "emul_ck", &emul_ck),
1763 /* mpu domain clocks */
1764 CLK(NULL, "mpu_ck", &mpu_ck),
1765 /* dsp domain clocks */
1766 CLK(NULL, "dsp_fck", &dsp_fck),
1767 CLK(NULL, "dsp_ick", &dsp_ick),
1768 CLK(NULL, "iva1_ifck", &iva1_ifck),
1769 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck),
1770 /* GFX domain clocks */
1771 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
1772 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
1773 CLK(NULL, "gfx_ick", &gfx_ick),
1774 /* DSS domain clocks */
1775 CLK("omapdss_dss", "ick", &dss_ick),
1776 CLK(NULL, "dss_ick", &dss_ick),
1777 CLK(NULL, "dss1_fck", &dss1_fck),
1778 CLK(NULL, "dss2_fck", &dss2_fck),
1779 CLK(NULL, "dss_54m_fck", &dss_54m_fck),
1780 /* L3 domain clocks */
1781 CLK(NULL, "core_l3_ck", &core_l3_ck),
1782 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
1783 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
1784 /* L4 domain clocks */
1785 CLK(NULL, "l4_ck", &l4_ck),
1786 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
1787 /* virtual meta-group clock */
1788 CLK(NULL, "virt_prcm_set", &virt_prcm_set),
1789 /* general l4 interface ck, multi-parent functional clk */
1790 CLK(NULL, "gpt1_ick", &gpt1_ick),
1791 CLK(NULL, "gpt1_fck", &gpt1_fck),
1792 CLK(NULL, "gpt2_ick", &gpt2_ick),
1793 CLK(NULL, "gpt2_fck", &gpt2_fck),
1794 CLK(NULL, "gpt3_ick", &gpt3_ick),
1795 CLK(NULL, "gpt3_fck", &gpt3_fck),
1796 CLK(NULL, "gpt4_ick", &gpt4_ick),
1797 CLK(NULL, "gpt4_fck", &gpt4_fck),
1798 CLK(NULL, "gpt5_ick", &gpt5_ick),
1799 CLK(NULL, "gpt5_fck", &gpt5_fck),
1800 CLK(NULL, "gpt6_ick", &gpt6_ick),
1801 CLK(NULL, "gpt6_fck", &gpt6_fck),
1802 CLK(NULL, "gpt7_ick", &gpt7_ick),
1803 CLK(NULL, "gpt7_fck", &gpt7_fck),
1804 CLK(NULL, "gpt8_ick", &gpt8_ick),
1805 CLK(NULL, "gpt8_fck", &gpt8_fck),
1806 CLK(NULL, "gpt9_ick", &gpt9_ick),
1807 CLK(NULL, "gpt9_fck", &gpt9_fck),
1808 CLK(NULL, "gpt10_ick", &gpt10_ick),
1809 CLK(NULL, "gpt10_fck", &gpt10_fck),
1810 CLK(NULL, "gpt11_ick", &gpt11_ick),
1811 CLK(NULL, "gpt11_fck", &gpt11_fck),
1812 CLK(NULL, "gpt12_ick", &gpt12_ick),
1813 CLK(NULL, "gpt12_fck", &gpt12_fck),
1814 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
1815 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
1816 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
1817 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
1818 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
1819 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
1820 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
1821 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
1822 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
1823 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
1824 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
1825 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
1826 CLK(NULL, "uart1_ick", &uart1_ick),
1827 CLK(NULL, "uart1_fck", &uart1_fck),
1828 CLK(NULL, "uart2_ick", &uart2_ick),
1829 CLK(NULL, "uart2_fck", &uart2_fck),
1830 CLK(NULL, "uart3_ick", &uart3_ick),
1831 CLK(NULL, "uart3_fck", &uart3_fck),
1832 CLK(NULL, "gpios_ick", &gpios_ick),
1833 CLK(NULL, "gpios_fck", &gpios_fck),
1834 CLK("omap_wdt", "ick", &mpu_wdt_ick),
1835 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
1836 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
1837 CLK(NULL, "sync_32k_ick", &sync_32k_ick),
1838 CLK(NULL, "wdt1_ick", &wdt1_ick),
1839 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
1840 CLK("omap24xxcam", "fck", &cam_fck),
1841 CLK(NULL, "cam_fck", &cam_fck),
1842 CLK("omap24xxcam", "ick", &cam_ick),
1843 CLK(NULL, "cam_ick", &cam_ick),
1844 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
1845 CLK(NULL, "wdt4_ick", &wdt4_ick),
1846 CLK(NULL, "wdt4_fck", &wdt4_fck),
1847 CLK(NULL, "wdt3_ick", &wdt3_ick),
1848 CLK(NULL, "wdt3_fck", &wdt3_fck),
1849 CLK(NULL, "mspro_ick", &mspro_ick),
1850 CLK(NULL, "mspro_fck", &mspro_fck),
1851 CLK("mmci-omap.0", "ick", &mmc_ick),
1852 CLK(NULL, "mmc_ick", &mmc_ick),
1853 CLK("mmci-omap.0", "fck", &mmc_fck),
1854 CLK(NULL, "mmc_fck", &mmc_fck),
1855 CLK(NULL, "fac_ick", &fac_ick),
1856 CLK(NULL, "fac_fck", &fac_fck),
1857 CLK(NULL, "eac_ick", &eac_ick),
1858 CLK(NULL, "eac_fck", &eac_fck),
1859 CLK("omap_hdq.0", "ick", &hdq_ick),
1860 CLK(NULL, "hdq_ick", &hdq_ick),
1861 CLK("omap_hdq.0", "fck", &hdq_fck),
1862 CLK(NULL, "hdq_fck", &hdq_fck),
1863 CLK("omap_i2c.1", "ick", &i2c1_ick),
1864 CLK(NULL, "i2c1_ick", &i2c1_ick),
1865 CLK(NULL, "i2c1_fck", &i2c1_fck),
1866 CLK("omap_i2c.2", "ick", &i2c2_ick),
1867 CLK(NULL, "i2c2_ick", &i2c2_ick),
1868 CLK(NULL, "i2c2_fck", &i2c2_fck),
1869 CLK(NULL, "gpmc_fck", &gpmc_fck),
1870 CLK(NULL, "sdma_fck", &sdma_fck),
1871 CLK(NULL, "sdma_ick", &sdma_ick),
1872 CLK(NULL, "sdrc_ick", &sdrc_ick),
1873 CLK(NULL, "vlynq_ick", &vlynq_ick),
1874 CLK(NULL, "vlynq_fck", &vlynq_fck),
1875 CLK(NULL, "des_ick", &des_ick),
1876 CLK("omap-sham", "ick", &sha_ick),
1877 CLK(NULL, "sha_ick", &sha_ick),
1878 CLK("omap_rng", "ick", &rng_ick),
1879 CLK(NULL, "rng_ick", &rng_ick),
1880 CLK("omap-aes", "ick", &aes_ick),
1881 CLK(NULL, "aes_ick", &aes_ick),
1882 CLK(NULL, "pka_ick", &pka_ick),
1883 CLK(NULL, "usb_fck", &usb_fck),
1884 CLK("musb-hdrc", "fck", &osc_ck),
1885 CLK(NULL, "timer_32k_ck", &func_32k_ck),
1886 CLK(NULL, "timer_sys_ck", &sys_ck),
1887 CLK(NULL, "timer_ext_ck", &alt_ck),
1888 CLK(NULL, "cpufreq_ck", &virt_prcm_set),
1889};
1890
1891
1892static const char *enable_init_clks[] = {
1893 "apll96_ck",
1894 "apll54_ck",
1895 "sync_32k_ick",
1896 "omapctrl_ick",
1897 "gpmc_fck",
1898 "sdrc_ick",
1899};
1900
1901/*
1902 * init code
1903 */
1904
1905int __init omap2420_clk_init(void)
1906{
1907 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1908 cpu_mask = RATE_IN_242X;
1909 rate_table = omap2420_rate_table;
1910
1911 omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
1912
1913 omap2xxx_clkt_vps_check_bootloader_rates();
1914
1915 omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks));
1916
1917 omap2xxx_clkt_vps_late_init();
1918
1919 omap2_clk_disable_autoidle_all();
1920
1921 omap2_clk_enable_init_clocks(enable_init_clks,
1922 ARRAY_SIZE(enable_init_clks));
1923
1924 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1925 (clk_get_rate(&sys_ck) / 1000000),
1926 (clk_get_rate(&sys_ck) / 100000) % 10,
1927 (clk_get_rate(&dpll_ck) / 1000000),
1928 (clk_get_rate(&mpu_ck) / 1000000));
1929
1930 return 0;
1931}
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
deleted file mode 100644
index 5e4b037bb24c..000000000000
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ /dev/null
@@ -1,2048 +0,0 @@
1/*
2 * OMAP2430 clock data
3 *
4 * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/clk-private.h>
19#include <linux/list.h>
20
21#include "soc.h"
22#include "iomap.h"
23#include "clock.h"
24#include "clock2xxx.h"
25#include "opp2xxx.h"
26#include "cm2xxx.h"
27#include "prm2xxx.h"
28#include "prm-regbits-24xx.h"
29#include "cm-regbits-24xx.h"
30#include "sdrc.h"
31#include "control.h"
32
33#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
34
35/*
36 * 2430 clock tree.
37 *
38 * NOTE:In many cases here we are assigning a 'default' parent. In
39 * many cases the parent is selectable. The set parent calls will
40 * also switch sources.
41 *
42 * Several sources are given initial rates which may be wrong, this will
43 * be fixed up in the init func.
44 *
45 * Things are broadly separated below by clock domains. It is
46 * noteworthy that most peripherals have dependencies on multiple clock
47 * domains. Many get their interface clocks from the L4 domain, but get
48 * functional clocks from fixed sources or other core domain derived
49 * clocks.
50 */
51
52DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
53
54DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
55
56DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
57
58static struct clk osc_ck;
59
60static const struct clk_ops osc_ck_ops = {
61 .enable = &omap2_enable_osc_ck,
62 .disable = omap2_disable_osc_ck,
63 .recalc_rate = &omap2_osc_clk_recalc,
64};
65
66static struct clk_hw_omap osc_ck_hw = {
67 .hw = {
68 .clk = &osc_ck,
69 },
70};
71
72static struct clk osc_ck = {
73 .name = "osc_ck",
74 .ops = &osc_ck_ops,
75 .hw = &osc_ck_hw.hw,
76 .flags = CLK_IS_ROOT,
77};
78
79DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
80
81static struct clk sys_ck;
82
83static const char *sys_ck_parent_names[] = {
84 "osc_ck",
85};
86
87static const struct clk_ops sys_ck_ops = {
88 .init = &omap2_init_clk_clkdm,
89 .recalc_rate = &omap2xxx_sys_clk_recalc,
90};
91
92DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
93DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
94
95static struct dpll_data dpll_dd = {
96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
97 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
98 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
99 .clk_bypass = &sys_ck,
100 .clk_ref = &sys_ck,
101 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
102 .enable_mask = OMAP24XX_EN_DPLL_MASK,
103 .max_multiplier = 1023,
104 .min_divider = 1,
105 .max_divider = 16,
106};
107
108static struct clk dpll_ck;
109
110static const char *dpll_ck_parent_names[] = {
111 "sys_ck",
112};
113
114static const struct clk_ops dpll_ck_ops = {
115 .init = &omap2_init_clk_clkdm,
116 .get_parent = &omap2_init_dpll_parent,
117 .recalc_rate = &omap2_dpllcore_recalc,
118 .round_rate = &omap2_dpll_round_rate,
119 .set_rate = &omap2_reprogram_dpllcore,
120};
121
122static struct clk_hw_omap dpll_ck_hw = {
123 .hw = {
124 .clk = &dpll_ck,
125 },
126 .ops = &clkhwops_omap2xxx_dpll,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
129};
130
131DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
132
133static struct clk core_ck;
134
135static const char *core_ck_parent_names[] = {
136 "dpll_ck",
137};
138
139static const struct clk_ops core_ck_ops = {
140 .init = &omap2_init_clk_clkdm,
141};
142
143DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
144DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
145
146DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
147 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
148 OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
149 CLK_DIVIDER_ONE_BASED, NULL);
150
151DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
153 OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
155
156static struct clk aes_ick;
157
158static const char *aes_ick_parent_names[] = {
159 "l4_ck",
160};
161
162static const struct clk_ops aes_ick_ops = {
163 .init = &omap2_init_clk_clkdm,
164 .enable = &omap2_dflt_clk_enable,
165 .disable = &omap2_dflt_clk_disable,
166 .is_enabled = &omap2_dflt_clk_is_enabled,
167};
168
169static struct clk_hw_omap aes_ick_hw = {
170 .hw = {
171 .clk = &aes_ick,
172 },
173 .ops = &clkhwops_iclk_wait,
174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
175 .enable_bit = OMAP24XX_EN_AES_SHIFT,
176 .clkdm_name = "core_l4_clkdm",
177};
178
179DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
180
181static struct clk apll54_ck;
182
183static const struct clk_ops apll54_ck_ops = {
184 .init = &omap2_init_clk_clkdm,
185 .enable = &omap2_clk_apll54_enable,
186 .disable = &omap2_clk_apll54_disable,
187 .recalc_rate = &omap2_clk_apll54_recalc,
188};
189
190static struct clk_hw_omap apll54_ck_hw = {
191 .hw = {
192 .clk = &apll54_ck,
193 },
194 .ops = &clkhwops_apll54,
195 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
196 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
197 .flags = ENABLE_ON_INIT,
198 .clkdm_name = "wkup_clkdm",
199};
200
201DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
202
203static struct clk apll96_ck;
204
205static const struct clk_ops apll96_ck_ops = {
206 .init = &omap2_init_clk_clkdm,
207 .enable = &omap2_clk_apll96_enable,
208 .disable = &omap2_clk_apll96_disable,
209 .recalc_rate = &omap2_clk_apll96_recalc,
210};
211
212static struct clk_hw_omap apll96_ck_hw = {
213 .hw = {
214 .clk = &apll96_ck,
215 },
216 .ops = &clkhwops_apll96,
217 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
218 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
219 .flags = ENABLE_ON_INIT,
220 .clkdm_name = "wkup_clkdm",
221};
222
223DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
224
225static const char *func_96m_ck_parent_names[] = {
226 "apll96_ck", "alt_ck",
227};
228
229DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0,
230 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT,
231 OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL);
232
233static struct clk cam_fck;
234
235static const char *cam_fck_parent_names[] = {
236 "func_96m_ck",
237};
238
239static struct clk_hw_omap cam_fck_hw = {
240 .hw = {
241 .clk = &cam_fck,
242 },
243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
244 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
245 .clkdm_name = "core_l3_clkdm",
246};
247
248DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
249
250static struct clk cam_ick;
251
252static struct clk_hw_omap cam_ick_hw = {
253 .hw = {
254 .clk = &cam_ick,
255 },
256 .ops = &clkhwops_iclk,
257 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
258 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
259 .clkdm_name = "core_l4_clkdm",
260};
261
262DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
263
264static struct clk des_ick;
265
266static struct clk_hw_omap des_ick_hw = {
267 .hw = {
268 .clk = &des_ick,
269 },
270 .ops = &clkhwops_iclk_wait,
271 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
272 .enable_bit = OMAP24XX_EN_DES_SHIFT,
273 .clkdm_name = "core_l4_clkdm",
274};
275
276DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
277
278static const struct clksel_rate dsp_fck_core_rates[] = {
279 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
280 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
281 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
282 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
283 { .div = 0 }
284};
285
286static const struct clksel dsp_fck_clksel[] = {
287 { .parent = &core_ck, .rates = dsp_fck_core_rates },
288 { .parent = NULL },
289};
290
291static const char *dsp_fck_parent_names[] = {
292 "core_ck",
293};
294
295static struct clk dsp_fck;
296
297static const struct clk_ops dsp_fck_ops = {
298 .init = &omap2_init_clk_clkdm,
299 .enable = &omap2_dflt_clk_enable,
300 .disable = &omap2_dflt_clk_disable,
301 .is_enabled = &omap2_dflt_clk_is_enabled,
302 .recalc_rate = &omap2_clksel_recalc,
303 .set_rate = &omap2_clksel_set_rate,
304 .round_rate = &omap2_clksel_round_rate,
305};
306
307DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
308 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
309 OMAP24XX_CLKSEL_DSP_MASK,
310 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
311 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
312 dsp_fck_parent_names, dsp_fck_ops);
313
314static const struct clksel_rate dss1_fck_sys_rates[] = {
315 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
316 { .div = 0 }
317};
318
319static const struct clksel_rate dss1_fck_core_rates[] = {
320 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
321 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
322 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
323 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
324 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
325 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
326 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
327 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
328 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
329 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
330 { .div = 0 }
331};
332
333static const struct clksel dss1_fck_clksel[] = {
334 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
335 { .parent = &core_ck, .rates = dss1_fck_core_rates },
336 { .parent = NULL },
337};
338
339static const char *dss1_fck_parent_names[] = {
340 "sys_ck", "core_ck",
341};
342
343static const struct clk_ops dss1_fck_ops = {
344 .init = &omap2_init_clk_clkdm,
345 .enable = &omap2_dflt_clk_enable,
346 .disable = &omap2_dflt_clk_disable,
347 .is_enabled = &omap2_dflt_clk_is_enabled,
348 .recalc_rate = &omap2_clksel_recalc,
349 .get_parent = &omap2_clksel_find_parent_index,
350 .set_parent = &omap2_clksel_set_parent,
351};
352
353DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
354 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
355 OMAP24XX_CLKSEL_DSS1_MASK,
356 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
357 OMAP24XX_EN_DSS1_SHIFT, NULL,
358 dss1_fck_parent_names, dss1_fck_ops);
359
360static const struct clksel_rate dss2_fck_sys_rates[] = {
361 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
362 { .div = 0 }
363};
364
365static const struct clksel_rate dss2_fck_48m_rates[] = {
366 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
367 { .div = 0 }
368};
369
370static const struct clksel_rate func_48m_apll96_rates[] = {
371 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
372 { .div = 0 }
373};
374
375static const struct clksel_rate func_48m_alt_rates[] = {
376 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
377 { .div = 0 }
378};
379
380static const struct clksel func_48m_clksel[] = {
381 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
382 { .parent = &alt_ck, .rates = func_48m_alt_rates },
383 { .parent = NULL },
384};
385
386static const char *func_48m_ck_parent_names[] = {
387 "apll96_ck", "alt_ck",
388};
389
390static struct clk func_48m_ck;
391
392static const struct clk_ops func_48m_ck_ops = {
393 .init = &omap2_init_clk_clkdm,
394 .recalc_rate = &omap2_clksel_recalc,
395 .set_rate = &omap2_clksel_set_rate,
396 .round_rate = &omap2_clksel_round_rate,
397 .get_parent = &omap2_clksel_find_parent_index,
398 .set_parent = &omap2_clksel_set_parent,
399};
400
401static struct clk_hw_omap func_48m_ck_hw = {
402 .hw = {
403 .clk = &func_48m_ck,
404 },
405 .clksel = func_48m_clksel,
406 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
407 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
408 .clkdm_name = "wkup_clkdm",
409};
410
411DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
412
413static const struct clksel dss2_fck_clksel[] = {
414 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
415 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
416 { .parent = NULL },
417};
418
419static const char *dss2_fck_parent_names[] = {
420 "sys_ck", "func_48m_ck",
421};
422
423DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
424 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
425 OMAP24XX_CLKSEL_DSS2_MASK,
426 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
427 OMAP24XX_EN_DSS2_SHIFT, NULL,
428 dss2_fck_parent_names, dss1_fck_ops);
429
430static const char *func_54m_ck_parent_names[] = {
431 "apll54_ck", "alt_ck",
432};
433
434DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
435 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
436 OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL);
437
438static struct clk dss_54m_fck;
439
440static const char *dss_54m_fck_parent_names[] = {
441 "func_54m_ck",
442};
443
444static struct clk_hw_omap dss_54m_fck_hw = {
445 .hw = {
446 .clk = &dss_54m_fck,
447 },
448 .ops = &clkhwops_wait,
449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
450 .enable_bit = OMAP24XX_EN_TV_SHIFT,
451 .clkdm_name = "dss_clkdm",
452};
453
454DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
455
456static struct clk dss_ick;
457
458static struct clk_hw_omap dss_ick_hw = {
459 .hw = {
460 .clk = &dss_ick,
461 },
462 .ops = &clkhwops_iclk,
463 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
464 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
465 .clkdm_name = "dss_clkdm",
466};
467
468DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
469
470static struct clk emul_ck;
471
472static struct clk_hw_omap emul_ck_hw = {
473 .hw = {
474 .clk = &emul_ck,
475 },
476 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
477 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
478 .clkdm_name = "wkup_clkdm",
479};
480
481DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
482
483DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
484
485static struct clk fac_fck;
486
487static const char *fac_fck_parent_names[] = {
488 "func_12m_ck",
489};
490
491static struct clk_hw_omap fac_fck_hw = {
492 .hw = {
493 .clk = &fac_fck,
494 },
495 .ops = &clkhwops_wait,
496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
497 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
498 .clkdm_name = "core_l4_clkdm",
499};
500
501DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
502
503static struct clk fac_ick;
504
505static struct clk_hw_omap fac_ick_hw = {
506 .hw = {
507 .clk = &fac_ick,
508 },
509 .ops = &clkhwops_iclk_wait,
510 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
511 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
512 .clkdm_name = "core_l4_clkdm",
513};
514
515DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
516
517static const struct clksel gfx_fck_clksel[] = {
518 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
519 { .parent = NULL },
520};
521
522static const char *gfx_2d_fck_parent_names[] = {
523 "core_l3_ck",
524};
525
526DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
527 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
528 OMAP_CLKSEL_GFX_MASK,
529 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
530 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
531 gfx_2d_fck_parent_names, dsp_fck_ops);
532
533DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
534 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
535 OMAP_CLKSEL_GFX_MASK,
536 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
537 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
538 gfx_2d_fck_parent_names, dsp_fck_ops);
539
540static struct clk gfx_ick;
541
542static const char *gfx_ick_parent_names[] = {
543 "core_l3_ck",
544};
545
546static struct clk_hw_omap gfx_ick_hw = {
547 .hw = {
548 .clk = &gfx_ick,
549 },
550 .ops = &clkhwops_wait,
551 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
552 .enable_bit = OMAP_EN_GFX_SHIFT,
553 .clkdm_name = "gfx_clkdm",
554};
555
556DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
557
558static struct clk gpio5_fck;
559
560static const char *gpio5_fck_parent_names[] = {
561 "func_32k_ck",
562};
563
564static struct clk_hw_omap gpio5_fck_hw = {
565 .hw = {
566 .clk = &gpio5_fck,
567 },
568 .ops = &clkhwops_wait,
569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
570 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
571 .clkdm_name = "core_l4_clkdm",
572};
573
574DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops);
575
576static struct clk gpio5_ick;
577
578static struct clk_hw_omap gpio5_ick_hw = {
579 .hw = {
580 .clk = &gpio5_ick,
581 },
582 .ops = &clkhwops_iclk_wait,
583 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
584 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
585 .clkdm_name = "core_l4_clkdm",
586};
587
588DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops);
589
590static struct clk gpios_fck;
591
592static struct clk_hw_omap gpios_fck_hw = {
593 .hw = {
594 .clk = &gpios_fck,
595 },
596 .ops = &clkhwops_wait,
597 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
598 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
599 .clkdm_name = "wkup_clkdm",
600};
601
602DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
603
604static struct clk gpios_ick;
605
606static const char *gpios_ick_parent_names[] = {
607 "sys_ck",
608};
609
610static struct clk_hw_omap gpios_ick_hw = {
611 .hw = {
612 .clk = &gpios_ick,
613 },
614 .ops = &clkhwops_iclk_wait,
615 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
616 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
617 .clkdm_name = "wkup_clkdm",
618};
619
620DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
621
622static struct clk gpmc_fck;
623
624static struct clk_hw_omap gpmc_fck_hw = {
625 .hw = {
626 .clk = &gpmc_fck,
627 },
628 .ops = &clkhwops_iclk,
629 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
630 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
631 .flags = ENABLE_ON_INIT,
632 .clkdm_name = "core_l3_clkdm",
633};
634
635DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
636
637static const struct clksel_rate gpt_alt_rates[] = {
638 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
639 { .div = 0 }
640};
641
642static const struct clksel omap24xx_gpt_clksel[] = {
643 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
644 { .parent = &sys_ck, .rates = gpt_sys_rates },
645 { .parent = &alt_ck, .rates = gpt_alt_rates },
646 { .parent = NULL },
647};
648
649static const char *gpt10_fck_parent_names[] = {
650 "func_32k_ck", "sys_ck", "alt_ck",
651};
652
653DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
654 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
655 OMAP24XX_CLKSEL_GPT10_MASK,
656 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
657 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
658 gpt10_fck_parent_names, dss1_fck_ops);
659
660static struct clk gpt10_ick;
661
662static struct clk_hw_omap gpt10_ick_hw = {
663 .hw = {
664 .clk = &gpt10_ick,
665 },
666 .ops = &clkhwops_iclk_wait,
667 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
668 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
669 .clkdm_name = "core_l4_clkdm",
670};
671
672DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
673
674DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
675 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
676 OMAP24XX_CLKSEL_GPT11_MASK,
677 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
678 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
679 gpt10_fck_parent_names, dss1_fck_ops);
680
681static struct clk gpt11_ick;
682
683static struct clk_hw_omap gpt11_ick_hw = {
684 .hw = {
685 .clk = &gpt11_ick,
686 },
687 .ops = &clkhwops_iclk_wait,
688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
689 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
690 .clkdm_name = "core_l4_clkdm",
691};
692
693DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
694
695DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
696 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
697 OMAP24XX_CLKSEL_GPT12_MASK,
698 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
699 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
700 gpt10_fck_parent_names, dss1_fck_ops);
701
702static struct clk gpt12_ick;
703
704static struct clk_hw_omap gpt12_ick_hw = {
705 .hw = {
706 .clk = &gpt12_ick,
707 },
708 .ops = &clkhwops_iclk_wait,
709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
710 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
711 .clkdm_name = "core_l4_clkdm",
712};
713
714DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
715
716static const struct clk_ops gpt1_fck_ops = {
717 .init = &omap2_init_clk_clkdm,
718 .enable = &omap2_dflt_clk_enable,
719 .disable = &omap2_dflt_clk_disable,
720 .is_enabled = &omap2_dflt_clk_is_enabled,
721 .recalc_rate = &omap2_clksel_recalc,
722 .set_rate = &omap2_clksel_set_rate,
723 .round_rate = &omap2_clksel_round_rate,
724 .get_parent = &omap2_clksel_find_parent_index,
725 .set_parent = &omap2_clksel_set_parent,
726};
727
728DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
729 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
730 OMAP24XX_CLKSEL_GPT1_MASK,
731 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
732 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
733 gpt10_fck_parent_names, gpt1_fck_ops);
734
735static struct clk gpt1_ick;
736
737static struct clk_hw_omap gpt1_ick_hw = {
738 .hw = {
739 .clk = &gpt1_ick,
740 },
741 .ops = &clkhwops_iclk_wait,
742 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
743 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
744 .clkdm_name = "wkup_clkdm",
745};
746
747DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
748
749DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
750 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
751 OMAP24XX_CLKSEL_GPT2_MASK,
752 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
753 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
754 gpt10_fck_parent_names, dss1_fck_ops);
755
756static struct clk gpt2_ick;
757
758static struct clk_hw_omap gpt2_ick_hw = {
759 .hw = {
760 .clk = &gpt2_ick,
761 },
762 .ops = &clkhwops_iclk_wait,
763 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
764 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
765 .clkdm_name = "core_l4_clkdm",
766};
767
768DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
769
770DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
771 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
772 OMAP24XX_CLKSEL_GPT3_MASK,
773 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
774 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
775 gpt10_fck_parent_names, dss1_fck_ops);
776
777static struct clk gpt3_ick;
778
779static struct clk_hw_omap gpt3_ick_hw = {
780 .hw = {
781 .clk = &gpt3_ick,
782 },
783 .ops = &clkhwops_iclk_wait,
784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
785 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
786 .clkdm_name = "core_l4_clkdm",
787};
788
789DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
790
791DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
792 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
793 OMAP24XX_CLKSEL_GPT4_MASK,
794 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
795 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
796 gpt10_fck_parent_names, dss1_fck_ops);
797
798static struct clk gpt4_ick;
799
800static struct clk_hw_omap gpt4_ick_hw = {
801 .hw = {
802 .clk = &gpt4_ick,
803 },
804 .ops = &clkhwops_iclk_wait,
805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
806 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
807 .clkdm_name = "core_l4_clkdm",
808};
809
810DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
811
812DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
813 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
814 OMAP24XX_CLKSEL_GPT5_MASK,
815 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
816 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
817 gpt10_fck_parent_names, dss1_fck_ops);
818
819static struct clk gpt5_ick;
820
821static struct clk_hw_omap gpt5_ick_hw = {
822 .hw = {
823 .clk = &gpt5_ick,
824 },
825 .ops = &clkhwops_iclk_wait,
826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
827 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
828 .clkdm_name = "core_l4_clkdm",
829};
830
831DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
832
833DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
834 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
835 OMAP24XX_CLKSEL_GPT6_MASK,
836 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
837 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
838 gpt10_fck_parent_names, dss1_fck_ops);
839
840static struct clk gpt6_ick;
841
842static struct clk_hw_omap gpt6_ick_hw = {
843 .hw = {
844 .clk = &gpt6_ick,
845 },
846 .ops = &clkhwops_iclk_wait,
847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
848 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
849 .clkdm_name = "core_l4_clkdm",
850};
851
852DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
853
854DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
855 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
856 OMAP24XX_CLKSEL_GPT7_MASK,
857 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
858 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
859 gpt10_fck_parent_names, dss1_fck_ops);
860
861static struct clk gpt7_ick;
862
863static struct clk_hw_omap gpt7_ick_hw = {
864 .hw = {
865 .clk = &gpt7_ick,
866 },
867 .ops = &clkhwops_iclk_wait,
868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
869 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
870 .clkdm_name = "core_l4_clkdm",
871};
872
873DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
874
875static struct clk gpt8_fck;
876
877DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
878 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
879 OMAP24XX_CLKSEL_GPT8_MASK,
880 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
881 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
882 gpt10_fck_parent_names, dss1_fck_ops);
883
884static struct clk gpt8_ick;
885
886static struct clk_hw_omap gpt8_ick_hw = {
887 .hw = {
888 .clk = &gpt8_ick,
889 },
890 .ops = &clkhwops_iclk_wait,
891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
892 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
893 .clkdm_name = "core_l4_clkdm",
894};
895
896DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
897
898DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
899 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
900 OMAP24XX_CLKSEL_GPT9_MASK,
901 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
902 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
903 gpt10_fck_parent_names, dss1_fck_ops);
904
905static struct clk gpt9_ick;
906
907static struct clk_hw_omap gpt9_ick_hw = {
908 .hw = {
909 .clk = &gpt9_ick,
910 },
911 .ops = &clkhwops_iclk_wait,
912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
913 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
914 .clkdm_name = "core_l4_clkdm",
915};
916
917DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
918
919static struct clk hdq_fck;
920
921static struct clk_hw_omap hdq_fck_hw = {
922 .hw = {
923 .clk = &hdq_fck,
924 },
925 .ops = &clkhwops_wait,
926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
927 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
928 .clkdm_name = "core_l4_clkdm",
929};
930
931DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
932
933static struct clk hdq_ick;
934
935static struct clk_hw_omap hdq_ick_hw = {
936 .hw = {
937 .clk = &hdq_ick,
938 },
939 .ops = &clkhwops_iclk_wait,
940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
941 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
942 .clkdm_name = "core_l4_clkdm",
943};
944
945DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
946
947static struct clk i2c1_ick;
948
949static struct clk_hw_omap i2c1_ick_hw = {
950 .hw = {
951 .clk = &i2c1_ick,
952 },
953 .ops = &clkhwops_iclk_wait,
954 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
955 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
956 .clkdm_name = "core_l4_clkdm",
957};
958
959DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
960
961static struct clk i2c2_ick;
962
963static struct clk_hw_omap i2c2_ick_hw = {
964 .hw = {
965 .clk = &i2c2_ick,
966 },
967 .ops = &clkhwops_iclk_wait,
968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
969 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
970 .clkdm_name = "core_l4_clkdm",
971};
972
973DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
974
975static struct clk i2chs1_fck;
976
977static struct clk_hw_omap i2chs1_fck_hw = {
978 .hw = {
979 .clk = &i2chs1_fck,
980 },
981 .ops = &clkhwops_omap2430_i2chs_wait,
982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
983 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
984 .clkdm_name = "core_l4_clkdm",
985};
986
987DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops);
988
989static struct clk i2chs2_fck;
990
991static struct clk_hw_omap i2chs2_fck_hw = {
992 .hw = {
993 .clk = &i2chs2_fck,
994 },
995 .ops = &clkhwops_omap2430_i2chs_wait,
996 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
997 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
998 .clkdm_name = "core_l4_clkdm",
999};
1000
1001DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops);
1002
1003static struct clk icr_ick;
1004
1005static struct clk_hw_omap icr_ick_hw = {
1006 .hw = {
1007 .clk = &icr_ick,
1008 },
1009 .ops = &clkhwops_iclk_wait,
1010 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1011 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1012 .clkdm_name = "wkup_clkdm",
1013};
1014
1015DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops);
1016
1017static const struct clksel dsp_ick_clksel[] = {
1018 { .parent = &dsp_fck, .rates = dsp_ick_rates },
1019 { .parent = NULL },
1020};
1021
1022static const char *iva2_1_ick_parent_names[] = {
1023 "dsp_fck",
1024};
1025
1026DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel,
1027 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1028 OMAP24XX_CLKSEL_DSP_IF_MASK,
1029 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1030 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
1031 iva2_1_ick_parent_names, dsp_fck_ops);
1032
1033static struct clk mailboxes_ick;
1034
1035static struct clk_hw_omap mailboxes_ick_hw = {
1036 .hw = {
1037 .clk = &mailboxes_ick,
1038 },
1039 .ops = &clkhwops_iclk_wait,
1040 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1041 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1042 .clkdm_name = "core_l4_clkdm",
1043};
1044
1045DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
1046
1047static const struct clksel_rate common_mcbsp_96m_rates[] = {
1048 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1049 { .div = 0 }
1050};
1051
1052static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1053 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1054 { .div = 0 }
1055};
1056
1057static const struct clksel mcbsp_fck_clksel[] = {
1058 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1059 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1060 { .parent = NULL },
1061};
1062
1063static const char *mcbsp1_fck_parent_names[] = {
1064 "func_96m_ck", "mcbsp_clks",
1065};
1066
1067DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1068 OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1069 OMAP2_MCBSP1_CLKS_MASK,
1070 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1071 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
1072 mcbsp1_fck_parent_names, dss1_fck_ops);
1073
1074static struct clk mcbsp1_ick;
1075
1076static struct clk_hw_omap mcbsp1_ick_hw = {
1077 .hw = {
1078 .clk = &mcbsp1_ick,
1079 },
1080 .ops = &clkhwops_iclk_wait,
1081 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1082 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1083 .clkdm_name = "core_l4_clkdm",
1084};
1085
1086DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
1087
1088DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1089 OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1090 OMAP2_MCBSP2_CLKS_MASK,
1091 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1092 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
1093 mcbsp1_fck_parent_names, dss1_fck_ops);
1094
1095static struct clk mcbsp2_ick;
1096
1097static struct clk_hw_omap mcbsp2_ick_hw = {
1098 .hw = {
1099 .clk = &mcbsp2_ick,
1100 },
1101 .ops = &clkhwops_iclk_wait,
1102 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1103 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1104 .clkdm_name = "core_l4_clkdm",
1105};
1106
1107DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
1108
1109DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1110 OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1111 OMAP2_MCBSP3_CLKS_MASK,
1112 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1113 OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait,
1114 mcbsp1_fck_parent_names, dss1_fck_ops);
1115
1116static struct clk mcbsp3_ick;
1117
1118static struct clk_hw_omap mcbsp3_ick_hw = {
1119 .hw = {
1120 .clk = &mcbsp3_ick,
1121 },
1122 .ops = &clkhwops_iclk_wait,
1123 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1124 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1125 .clkdm_name = "core_l4_clkdm",
1126};
1127
1128DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops);
1129
1130DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1131 OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1132 OMAP2_MCBSP4_CLKS_MASK,
1133 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1134 OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait,
1135 mcbsp1_fck_parent_names, dss1_fck_ops);
1136
1137static struct clk mcbsp4_ick;
1138
1139static struct clk_hw_omap mcbsp4_ick_hw = {
1140 .hw = {
1141 .clk = &mcbsp4_ick,
1142 },
1143 .ops = &clkhwops_iclk_wait,
1144 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1145 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1146 .clkdm_name = "core_l4_clkdm",
1147};
1148
1149DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops);
1150
1151DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1152 OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1153 OMAP2_MCBSP5_CLKS_MASK,
1154 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1155 OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait,
1156 mcbsp1_fck_parent_names, dss1_fck_ops);
1157
1158static struct clk mcbsp5_ick;
1159
1160static struct clk_hw_omap mcbsp5_ick_hw = {
1161 .hw = {
1162 .clk = &mcbsp5_ick,
1163 },
1164 .ops = &clkhwops_iclk_wait,
1165 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1166 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1167 .clkdm_name = "core_l4_clkdm",
1168};
1169
1170DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops);
1171
1172static struct clk mcspi1_fck;
1173
1174static const char *mcspi1_fck_parent_names[] = {
1175 "func_48m_ck",
1176};
1177
1178static struct clk_hw_omap mcspi1_fck_hw = {
1179 .hw = {
1180 .clk = &mcspi1_fck,
1181 },
1182 .ops = &clkhwops_wait,
1183 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1184 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1185 .clkdm_name = "core_l4_clkdm",
1186};
1187
1188DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1189
1190static struct clk mcspi1_ick;
1191
1192static struct clk_hw_omap mcspi1_ick_hw = {
1193 .hw = {
1194 .clk = &mcspi1_ick,
1195 },
1196 .ops = &clkhwops_iclk_wait,
1197 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1198 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1199 .clkdm_name = "core_l4_clkdm",
1200};
1201
1202DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
1203
1204static struct clk mcspi2_fck;
1205
1206static struct clk_hw_omap mcspi2_fck_hw = {
1207 .hw = {
1208 .clk = &mcspi2_fck,
1209 },
1210 .ops = &clkhwops_wait,
1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1212 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1213 .clkdm_name = "core_l4_clkdm",
1214};
1215
1216DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1217
1218static struct clk mcspi2_ick;
1219
1220static struct clk_hw_omap mcspi2_ick_hw = {
1221 .hw = {
1222 .clk = &mcspi2_ick,
1223 },
1224 .ops = &clkhwops_iclk_wait,
1225 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1226 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1227 .clkdm_name = "core_l4_clkdm",
1228};
1229
1230DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
1231
1232static struct clk mcspi3_fck;
1233
1234static struct clk_hw_omap mcspi3_fck_hw = {
1235 .hw = {
1236 .clk = &mcspi3_fck,
1237 },
1238 .ops = &clkhwops_wait,
1239 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1240 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1241 .clkdm_name = "core_l4_clkdm",
1242};
1243
1244DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1245
1246static struct clk mcspi3_ick;
1247
1248static struct clk_hw_omap mcspi3_ick_hw = {
1249 .hw = {
1250 .clk = &mcspi3_ick,
1251 },
1252 .ops = &clkhwops_iclk_wait,
1253 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1254 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1255 .clkdm_name = "core_l4_clkdm",
1256};
1257
1258DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops);
1259
1260static const struct clksel_rate mdm_ick_core_rates[] = {
1261 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1262 { .div = 4, .val = 4, .flags = RATE_IN_243X },
1263 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1264 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1265 { .div = 0 }
1266};
1267
1268static const struct clksel mdm_ick_clksel[] = {
1269 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1270 { .parent = NULL },
1271};
1272
1273static const char *mdm_ick_parent_names[] = {
1274 "core_ck",
1275};
1276
1277DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel,
1278 OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1279 OMAP2430_CLKSEL_MDM_MASK,
1280 OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1281 OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1282 &clkhwops_iclk_wait, mdm_ick_parent_names,
1283 dsp_fck_ops);
1284
1285static struct clk mdm_intc_ick;
1286
1287static struct clk_hw_omap mdm_intc_ick_hw = {
1288 .hw = {
1289 .clk = &mdm_intc_ick,
1290 },
1291 .ops = &clkhwops_iclk_wait,
1292 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1293 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1294 .clkdm_name = "core_l4_clkdm",
1295};
1296
1297DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops);
1298
1299static struct clk mdm_osc_ck;
1300
1301static struct clk_hw_omap mdm_osc_ck_hw = {
1302 .hw = {
1303 .clk = &mdm_osc_ck,
1304 },
1305 .ops = &clkhwops_iclk_wait,
1306 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1307 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1308 .clkdm_name = "mdm_clkdm",
1309};
1310
1311DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
1312
1313static struct clk mmchs1_fck;
1314
1315static struct clk_hw_omap mmchs1_fck_hw = {
1316 .hw = {
1317 .clk = &mmchs1_fck,
1318 },
1319 .ops = &clkhwops_wait,
1320 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1321 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1322 .clkdm_name = "core_l4_clkdm",
1323};
1324
1325DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops);
1326
1327static struct clk mmchs1_ick;
1328
1329static struct clk_hw_omap mmchs1_ick_hw = {
1330 .hw = {
1331 .clk = &mmchs1_ick,
1332 },
1333 .ops = &clkhwops_iclk_wait,
1334 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1335 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1336 .clkdm_name = "core_l4_clkdm",
1337};
1338
1339DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops);
1340
1341static struct clk mmchs2_fck;
1342
1343static struct clk_hw_omap mmchs2_fck_hw = {
1344 .hw = {
1345 .clk = &mmchs2_fck,
1346 },
1347 .ops = &clkhwops_wait,
1348 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1349 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1350 .clkdm_name = "core_l4_clkdm",
1351};
1352
1353DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops);
1354
1355static struct clk mmchs2_ick;
1356
1357static struct clk_hw_omap mmchs2_ick_hw = {
1358 .hw = {
1359 .clk = &mmchs2_ick,
1360 },
1361 .ops = &clkhwops_iclk_wait,
1362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1363 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1364 .clkdm_name = "core_l4_clkdm",
1365};
1366
1367DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops);
1368
1369static struct clk mmchsdb1_fck;
1370
1371static struct clk_hw_omap mmchsdb1_fck_hw = {
1372 .hw = {
1373 .clk = &mmchsdb1_fck,
1374 },
1375 .ops = &clkhwops_wait,
1376 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1377 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1378 .clkdm_name = "core_l4_clkdm",
1379};
1380
1381DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops);
1382
1383static struct clk mmchsdb2_fck;
1384
1385static struct clk_hw_omap mmchsdb2_fck_hw = {
1386 .hw = {
1387 .clk = &mmchsdb2_fck,
1388 },
1389 .ops = &clkhwops_wait,
1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1391 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1392 .clkdm_name = "core_l4_clkdm",
1393};
1394
1395DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops);
1396
1397DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
1398 OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1399 OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
1400 CLK_DIVIDER_ONE_BASED, NULL);
1401
1402static struct clk mpu_wdt_fck;
1403
1404static struct clk_hw_omap mpu_wdt_fck_hw = {
1405 .hw = {
1406 .clk = &mpu_wdt_fck,
1407 },
1408 .ops = &clkhwops_wait,
1409 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1410 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1411 .clkdm_name = "wkup_clkdm",
1412};
1413
1414DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops);
1415
1416static struct clk mpu_wdt_ick;
1417
1418static struct clk_hw_omap mpu_wdt_ick_hw = {
1419 .hw = {
1420 .clk = &mpu_wdt_ick,
1421 },
1422 .ops = &clkhwops_iclk_wait,
1423 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1424 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1425 .clkdm_name = "wkup_clkdm",
1426};
1427
1428DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
1429
1430static struct clk mspro_fck;
1431
1432static struct clk_hw_omap mspro_fck_hw = {
1433 .hw = {
1434 .clk = &mspro_fck,
1435 },
1436 .ops = &clkhwops_wait,
1437 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1438 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1439 .clkdm_name = "core_l4_clkdm",
1440};
1441
1442DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
1443
1444static struct clk mspro_ick;
1445
1446static struct clk_hw_omap mspro_ick_hw = {
1447 .hw = {
1448 .clk = &mspro_ick,
1449 },
1450 .ops = &clkhwops_iclk_wait,
1451 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1452 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1453 .clkdm_name = "core_l4_clkdm",
1454};
1455
1456DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
1457
1458static struct clk omapctrl_ick;
1459
1460static struct clk_hw_omap omapctrl_ick_hw = {
1461 .hw = {
1462 .clk = &omapctrl_ick,
1463 },
1464 .ops = &clkhwops_iclk_wait,
1465 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1466 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1467 .flags = ENABLE_ON_INIT,
1468 .clkdm_name = "wkup_clkdm",
1469};
1470
1471DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
1472
1473static struct clk pka_ick;
1474
1475static struct clk_hw_omap pka_ick_hw = {
1476 .hw = {
1477 .clk = &pka_ick,
1478 },
1479 .ops = &clkhwops_iclk_wait,
1480 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1481 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1482 .clkdm_name = "core_l4_clkdm",
1483};
1484
1485DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
1486
1487static struct clk rng_ick;
1488
1489static struct clk_hw_omap rng_ick_hw = {
1490 .hw = {
1491 .clk = &rng_ick,
1492 },
1493 .ops = &clkhwops_iclk_wait,
1494 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1495 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1496 .clkdm_name = "core_l4_clkdm",
1497};
1498
1499DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
1500
1501static struct clk sdma_fck;
1502
1503DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
1504DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
1505
1506static struct clk sdma_ick;
1507
1508static struct clk_hw_omap sdma_ick_hw = {
1509 .hw = {
1510 .clk = &sdma_ick,
1511 },
1512 .ops = &clkhwops_iclk,
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1514 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1515 .clkdm_name = "core_l3_clkdm",
1516};
1517
1518DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
1519
1520static struct clk sdrc_ick;
1521
1522static struct clk_hw_omap sdrc_ick_hw = {
1523 .hw = {
1524 .clk = &sdrc_ick,
1525 },
1526 .ops = &clkhwops_iclk,
1527 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1528 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1529 .flags = ENABLE_ON_INIT,
1530 .clkdm_name = "core_l3_clkdm",
1531};
1532
1533DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
1534
1535static struct clk sha_ick;
1536
1537static struct clk_hw_omap sha_ick_hw = {
1538 .hw = {
1539 .clk = &sha_ick,
1540 },
1541 .ops = &clkhwops_iclk_wait,
1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1543 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1544 .clkdm_name = "core_l4_clkdm",
1545};
1546
1547DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
1548
1549static struct clk ssi_l4_ick;
1550
1551static struct clk_hw_omap ssi_l4_ick_hw = {
1552 .hw = {
1553 .clk = &ssi_l4_ick,
1554 },
1555 .ops = &clkhwops_iclk_wait,
1556 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1557 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1558 .clkdm_name = "core_l4_clkdm",
1559};
1560
1561DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
1562
1563static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1564 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1565 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1566 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1567 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1568 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1569 { .div = 0 }
1570};
1571
1572static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1573 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1574 { .parent = NULL },
1575};
1576
1577static const char *ssi_ssr_sst_fck_parent_names[] = {
1578 "core_ck",
1579};
1580
1581DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
1582 ssi_ssr_sst_fck_clksel,
1583 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1584 OMAP24XX_CLKSEL_SSI_MASK,
1585 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1586 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
1587 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
1588
1589static struct clk sync_32k_ick;
1590
1591static struct clk_hw_omap sync_32k_ick_hw = {
1592 .hw = {
1593 .clk = &sync_32k_ick,
1594 },
1595 .ops = &clkhwops_iclk_wait,
1596 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1597 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1598 .flags = ENABLE_ON_INIT,
1599 .clkdm_name = "wkup_clkdm",
1600};
1601
1602DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
1603
1604static const struct clksel_rate common_clkout_src_core_rates[] = {
1605 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1606 { .div = 0 }
1607};
1608
1609static const struct clksel_rate common_clkout_src_sys_rates[] = {
1610 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1611 { .div = 0 }
1612};
1613
1614static const struct clksel_rate common_clkout_src_96m_rates[] = {
1615 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
1616 { .div = 0 }
1617};
1618
1619static const struct clksel_rate common_clkout_src_54m_rates[] = {
1620 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
1621 { .div = 0 }
1622};
1623
1624static const struct clksel common_clkout_src_clksel[] = {
1625 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
1626 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
1627 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
1628 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
1629 { .parent = NULL },
1630};
1631
1632static const char *sys_clkout_src_parent_names[] = {
1633 "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
1634};
1635
1636DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
1637 OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
1638 OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
1639 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1640
1641DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
1642 OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
1643 OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1644
1645static struct clk uart1_fck;
1646
1647static struct clk_hw_omap uart1_fck_hw = {
1648 .hw = {
1649 .clk = &uart1_fck,
1650 },
1651 .ops = &clkhwops_wait,
1652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1653 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1654 .clkdm_name = "core_l4_clkdm",
1655};
1656
1657DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1658
1659static struct clk uart1_ick;
1660
1661static struct clk_hw_omap uart1_ick_hw = {
1662 .hw = {
1663 .clk = &uart1_ick,
1664 },
1665 .ops = &clkhwops_iclk_wait,
1666 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1667 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1668 .clkdm_name = "core_l4_clkdm",
1669};
1670
1671DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
1672
1673static struct clk uart2_fck;
1674
1675static struct clk_hw_omap uart2_fck_hw = {
1676 .hw = {
1677 .clk = &uart2_fck,
1678 },
1679 .ops = &clkhwops_wait,
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1681 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1682 .clkdm_name = "core_l4_clkdm",
1683};
1684
1685DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1686
1687static struct clk uart2_ick;
1688
1689static struct clk_hw_omap uart2_ick_hw = {
1690 .hw = {
1691 .clk = &uart2_ick,
1692 },
1693 .ops = &clkhwops_iclk_wait,
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1696 .clkdm_name = "core_l4_clkdm",
1697};
1698
1699DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
1700
1701static struct clk uart3_fck;
1702
1703static struct clk_hw_omap uart3_fck_hw = {
1704 .hw = {
1705 .clk = &uart3_fck,
1706 },
1707 .ops = &clkhwops_wait,
1708 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1709 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1710 .clkdm_name = "core_l4_clkdm",
1711};
1712
1713DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1714
1715static struct clk uart3_ick;
1716
1717static struct clk_hw_omap uart3_ick_hw = {
1718 .hw = {
1719 .clk = &uart3_ick,
1720 },
1721 .ops = &clkhwops_iclk_wait,
1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1723 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1724 .clkdm_name = "core_l4_clkdm",
1725};
1726
1727DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
1728
1729static struct clk usb_fck;
1730
1731static struct clk_hw_omap usb_fck_hw = {
1732 .hw = {
1733 .clk = &usb_fck,
1734 },
1735 .ops = &clkhwops_wait,
1736 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1737 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1738 .clkdm_name = "core_l3_clkdm",
1739};
1740
1741DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
1742
1743static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1744 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1745 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1746 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1747 { .div = 0 }
1748};
1749
1750static const struct clksel usb_l4_ick_clksel[] = {
1751 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1752 { .parent = NULL },
1753};
1754
1755static const char *usb_l4_ick_parent_names[] = {
1756 "core_l3_ck",
1757};
1758
1759DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
1760 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1761 OMAP24XX_CLKSEL_USB_MASK,
1762 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1763 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
1764 usb_l4_ick_parent_names, dsp_fck_ops);
1765
1766static struct clk usbhs_ick;
1767
1768static struct clk_hw_omap usbhs_ick_hw = {
1769 .hw = {
1770 .clk = &usbhs_ick,
1771 },
1772 .ops = &clkhwops_iclk_wait,
1773 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1774 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1775 .clkdm_name = "core_l3_clkdm",
1776};
1777
1778DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops);
1779
1780static struct clk virt_prcm_set;
1781
1782static const char *virt_prcm_set_parent_names[] = {
1783 "mpu_ck",
1784};
1785
1786static const struct clk_ops virt_prcm_set_ops = {
1787 .recalc_rate = &omap2_table_mpu_recalc,
1788 .set_rate = &omap2_select_table_rate,
1789 .round_rate = &omap2_round_to_table_rate,
1790};
1791
1792DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
1793DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
1794
1795static struct clk wdt1_ick;
1796
1797static struct clk_hw_omap wdt1_ick_hw = {
1798 .hw = {
1799 .clk = &wdt1_ick,
1800 },
1801 .ops = &clkhwops_iclk_wait,
1802 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1803 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1804 .clkdm_name = "wkup_clkdm",
1805};
1806
1807DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1808
1809static struct clk wdt4_fck;
1810
1811static struct clk_hw_omap wdt4_fck_hw = {
1812 .hw = {
1813 .clk = &wdt4_fck,
1814 },
1815 .ops = &clkhwops_wait,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1817 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1818 .clkdm_name = "core_l4_clkdm",
1819};
1820
1821DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops);
1822
1823static struct clk wdt4_ick;
1824
1825static struct clk_hw_omap wdt4_ick_hw = {
1826 .hw = {
1827 .clk = &wdt4_ick,
1828 },
1829 .ops = &clkhwops_iclk_wait,
1830 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1831 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1832 .clkdm_name = "core_l4_clkdm",
1833};
1834
1835DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1836
1837/*
1838 * clkdev integration
1839 */
1840
1841static struct omap_clk omap2430_clks[] = {
1842 /* external root sources */
1843 CLK(NULL, "func_32k_ck", &func_32k_ck),
1844 CLK(NULL, "secure_32k_ck", &secure_32k_ck),
1845 CLK(NULL, "osc_ck", &osc_ck),
1846 CLK("twl", "fck", &osc_ck),
1847 CLK(NULL, "sys_ck", &sys_ck),
1848 CLK(NULL, "alt_ck", &alt_ck),
1849 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
1850 /* internal analog sources */
1851 CLK(NULL, "dpll_ck", &dpll_ck),
1852 CLK(NULL, "apll96_ck", &apll96_ck),
1853 CLK(NULL, "apll54_ck", &apll54_ck),
1854 /* internal prcm root sources */
1855 CLK(NULL, "func_54m_ck", &func_54m_ck),
1856 CLK(NULL, "core_ck", &core_ck),
1857 CLK(NULL, "func_96m_ck", &func_96m_ck),
1858 CLK(NULL, "func_48m_ck", &func_48m_ck),
1859 CLK(NULL, "func_12m_ck", &func_12m_ck),
1860 CLK(NULL, "sys_clkout_src", &sys_clkout_src),
1861 CLK(NULL, "sys_clkout", &sys_clkout),
1862 CLK(NULL, "emul_ck", &emul_ck),
1863 /* mpu domain clocks */
1864 CLK(NULL, "mpu_ck", &mpu_ck),
1865 /* dsp domain clocks */
1866 CLK(NULL, "dsp_fck", &dsp_fck),
1867 CLK(NULL, "iva2_1_ick", &iva2_1_ick),
1868 /* GFX domain clocks */
1869 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
1870 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
1871 CLK(NULL, "gfx_ick", &gfx_ick),
1872 /* Modem domain clocks */
1873 CLK(NULL, "mdm_ick", &mdm_ick),
1874 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck),
1875 /* DSS domain clocks */
1876 CLK("omapdss_dss", "ick", &dss_ick),
1877 CLK(NULL, "dss_ick", &dss_ick),
1878 CLK(NULL, "dss1_fck", &dss1_fck),
1879 CLK(NULL, "dss2_fck", &dss2_fck),
1880 CLK(NULL, "dss_54m_fck", &dss_54m_fck),
1881 /* L3 domain clocks */
1882 CLK(NULL, "core_l3_ck", &core_l3_ck),
1883 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
1884 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
1885 /* L4 domain clocks */
1886 CLK(NULL, "l4_ck", &l4_ck),
1887 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
1888 /* virtual meta-group clock */
1889 CLK(NULL, "virt_prcm_set", &virt_prcm_set),
1890 /* general l4 interface ck, multi-parent functional clk */
1891 CLK(NULL, "gpt1_ick", &gpt1_ick),
1892 CLK(NULL, "gpt1_fck", &gpt1_fck),
1893 CLK(NULL, "gpt2_ick", &gpt2_ick),
1894 CLK(NULL, "gpt2_fck", &gpt2_fck),
1895 CLK(NULL, "gpt3_ick", &gpt3_ick),
1896 CLK(NULL, "gpt3_fck", &gpt3_fck),
1897 CLK(NULL, "gpt4_ick", &gpt4_ick),
1898 CLK(NULL, "gpt4_fck", &gpt4_fck),
1899 CLK(NULL, "gpt5_ick", &gpt5_ick),
1900 CLK(NULL, "gpt5_fck", &gpt5_fck),
1901 CLK(NULL, "gpt6_ick", &gpt6_ick),
1902 CLK(NULL, "gpt6_fck", &gpt6_fck),
1903 CLK(NULL, "gpt7_ick", &gpt7_ick),
1904 CLK(NULL, "gpt7_fck", &gpt7_fck),
1905 CLK(NULL, "gpt8_ick", &gpt8_ick),
1906 CLK(NULL, "gpt8_fck", &gpt8_fck),
1907 CLK(NULL, "gpt9_ick", &gpt9_ick),
1908 CLK(NULL, "gpt9_fck", &gpt9_fck),
1909 CLK(NULL, "gpt10_ick", &gpt10_ick),
1910 CLK(NULL, "gpt10_fck", &gpt10_fck),
1911 CLK(NULL, "gpt11_ick", &gpt11_ick),
1912 CLK(NULL, "gpt11_fck", &gpt11_fck),
1913 CLK(NULL, "gpt12_ick", &gpt12_ick),
1914 CLK(NULL, "gpt12_fck", &gpt12_fck),
1915 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
1916 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
1917 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
1918 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
1919 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
1920 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
1921 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
1922 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
1923 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
1924 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
1925 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
1926 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
1927 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
1928 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
1929 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
1930 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
1931 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
1932 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
1933 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
1934 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
1935 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
1936 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
1937 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
1938 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
1939 CLK(NULL, "uart1_ick", &uart1_ick),
1940 CLK(NULL, "uart1_fck", &uart1_fck),
1941 CLK(NULL, "uart2_ick", &uart2_ick),
1942 CLK(NULL, "uart2_fck", &uart2_fck),
1943 CLK(NULL, "uart3_ick", &uart3_ick),
1944 CLK(NULL, "uart3_fck", &uart3_fck),
1945 CLK(NULL, "gpios_ick", &gpios_ick),
1946 CLK(NULL, "gpios_fck", &gpios_fck),
1947 CLK("omap_wdt", "ick", &mpu_wdt_ick),
1948 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
1949 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
1950 CLK(NULL, "sync_32k_ick", &sync_32k_ick),
1951 CLK(NULL, "wdt1_ick", &wdt1_ick),
1952 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
1953 CLK(NULL, "icr_ick", &icr_ick),
1954 CLK("omap24xxcam", "fck", &cam_fck),
1955 CLK(NULL, "cam_fck", &cam_fck),
1956 CLK("omap24xxcam", "ick", &cam_ick),
1957 CLK(NULL, "cam_ick", &cam_ick),
1958 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
1959 CLK(NULL, "wdt4_ick", &wdt4_ick),
1960 CLK(NULL, "wdt4_fck", &wdt4_fck),
1961 CLK(NULL, "mspro_ick", &mspro_ick),
1962 CLK(NULL, "mspro_fck", &mspro_fck),
1963 CLK(NULL, "fac_ick", &fac_ick),
1964 CLK(NULL, "fac_fck", &fac_fck),
1965 CLK("omap_hdq.0", "ick", &hdq_ick),
1966 CLK(NULL, "hdq_ick", &hdq_ick),
1967 CLK("omap_hdq.1", "fck", &hdq_fck),
1968 CLK(NULL, "hdq_fck", &hdq_fck),
1969 CLK("omap_i2c.1", "ick", &i2c1_ick),
1970 CLK(NULL, "i2c1_ick", &i2c1_ick),
1971 CLK(NULL, "i2chs1_fck", &i2chs1_fck),
1972 CLK("omap_i2c.2", "ick", &i2c2_ick),
1973 CLK(NULL, "i2c2_ick", &i2c2_ick),
1974 CLK(NULL, "i2chs2_fck", &i2chs2_fck),
1975 CLK(NULL, "gpmc_fck", &gpmc_fck),
1976 CLK(NULL, "sdma_fck", &sdma_fck),
1977 CLK(NULL, "sdma_ick", &sdma_ick),
1978 CLK(NULL, "sdrc_ick", &sdrc_ick),
1979 CLK(NULL, "des_ick", &des_ick),
1980 CLK("omap-sham", "ick", &sha_ick),
1981 CLK(NULL, "sha_ick", &sha_ick),
1982 CLK("omap_rng", "ick", &rng_ick),
1983 CLK(NULL, "rng_ick", &rng_ick),
1984 CLK("omap-aes", "ick", &aes_ick),
1985 CLK(NULL, "aes_ick", &aes_ick),
1986 CLK(NULL, "pka_ick", &pka_ick),
1987 CLK(NULL, "usb_fck", &usb_fck),
1988 CLK("musb-omap2430", "ick", &usbhs_ick),
1989 CLK(NULL, "usbhs_ick", &usbhs_ick),
1990 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
1991 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
1992 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
1993 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
1994 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
1995 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
1996 CLK(NULL, "gpio5_ick", &gpio5_ick),
1997 CLK(NULL, "gpio5_fck", &gpio5_fck),
1998 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick),
1999 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck),
2000 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck),
2001 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck),
2002 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck),
2003 CLK(NULL, "timer_32k_ck", &func_32k_ck),
2004 CLK(NULL, "timer_sys_ck", &sys_ck),
2005 CLK(NULL, "timer_ext_ck", &alt_ck),
2006 CLK(NULL, "cpufreq_ck", &virt_prcm_set),
2007};
2008
2009static const char *enable_init_clks[] = {
2010 "apll96_ck",
2011 "apll54_ck",
2012 "sync_32k_ick",
2013 "omapctrl_ick",
2014 "gpmc_fck",
2015 "sdrc_ick",
2016};
2017
2018/*
2019 * init code
2020 */
2021
2022int __init omap2430_clk_init(void)
2023{
2024 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2025 cpu_mask = RATE_IN_243X;
2026 rate_table = omap2430_rate_table;
2027
2028 omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
2029
2030 omap2xxx_clkt_vps_check_bootloader_rates();
2031
2032 omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks));
2033
2034 omap2xxx_clkt_vps_late_init();
2035
2036 omap2_clk_disable_autoidle_all();
2037
2038 omap2_clk_enable_init_clocks(enable_init_clks,
2039 ARRAY_SIZE(enable_init_clks));
2040
2041 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2042 (clk_get_rate(&sys_ck) / 1000000),
2043 (clk_get_rate(&sys_ck) / 100000) % 10,
2044 (clk_get_rate(&dpll_ck) / 1000000),
2045 (clk_get_rate(&mpu_ck) / 1000000));
2046
2047 return 0;
2048}
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
deleted file mode 100644
index 0717dff1bc04..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * OMAP2xxx osc_clk-specific clock code
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#undef DEBUG
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include "clock.h"
27#include "clock2xxx.h"
28#include "prm2xxx_3xxx.h"
29#include "prm-regbits-24xx.h"
30
31/*
32 * XXX This does not actually enable the osc_ck, since the osc_ck must
33 * be running for this function to be called. Instead, this function
34 * is used to disable an autoidle mode on the osc_ck. The existing
35 * clk_enable/clk_disable()-based usecounting for osc_ck should be
36 * replaced with autoidle-based usecounting.
37 */
38int omap2_enable_osc_ck(struct clk_hw *clk)
39{
40 u32 pcc;
41
42 pcc = readl_relaxed(prcm_clksrc_ctrl);
43
44 writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
45
46 return 0;
47}
48
49/*
50 * XXX This does not actually disable the osc_ck, since doing so would
51 * immediately halt the system. Instead, this function is used to
52 * enable an autoidle mode on the osc_ck. The existing
53 * clk_enable/clk_disable()-based usecounting for osc_ck should be
54 * replaced with autoidle-based usecounting.
55 */
56void omap2_disable_osc_ck(struct clk_hw *clk)
57{
58 u32 pcc;
59
60 pcc = readl_relaxed(prcm_clksrc_ctrl);
61
62 writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
63}
64
65unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
66 unsigned long parent_rate)
67{
68 return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
69}
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
deleted file mode 100644
index 58dd3a9b726c..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * OMAP2xxx sys_clk-specific clock code
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#undef DEBUG
19
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include "clock.h"
26#include "clock2xxx.h"
27#include "prm2xxx_3xxx.h"
28#include "prm-regbits-24xx.h"
29
30void __iomem *prcm_clksrc_ctrl;
31
32u32 omap2xxx_get_sysclkdiv(void)
33{
34 u32 div;
35
36 div = readl_relaxed(prcm_clksrc_ctrl);
37 div &= OMAP_SYSCLKDIV_MASK;
38 div >>= OMAP_SYSCLKDIV_SHIFT;
39
40 return div;
41}
42
43unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
44 unsigned long parent_rate)
45{
46 return parent_rate / omap2xxx_get_sysclkdiv();
47}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 591581a66532..4ac6e3d2df03 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -82,27 +82,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
82} 82}
83 83
84/* 84/*
85 * Used for clocks that have the same value as the parent clock,
86 * divided by some factor
87 */
88unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
89 unsigned long parent_rate)
90{
91 struct clk_hw_omap *oclk;
92
93 if (!hw) {
94 pr_warn("%s: hw is NULL\n", __func__);
95 return -EINVAL;
96 }
97
98 oclk = to_clk_hw_omap(hw);
99
100 WARN_ON(!oclk->fixed_div);
101
102 return parent_rate / oclk->fixed_div;
103}
104
105/*
106 * OMAP2+ specific clock functions 85 * OMAP2+ specific clock functions
107 */ 86 */
108 87
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 12f54d428d7c..bb6723842c4a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -178,9 +178,6 @@ struct clksel {
178 const struct clksel_rate *rates; 178 const struct clksel_rate *rates;
179}; 179};
180 180
181unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
182 unsigned long parent_rate);
183
184/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 181/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
185#define CORE_CLK_SRC_32K 0x0 182#define CORE_CLK_SRC_32K 0x0
186#define CORE_CLK_SRC_DPLL 0x1 183#define CORE_CLK_SRC_DPLL 0x1
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index 45f41a411603..a090225ceeba 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -45,8 +45,6 @@ int omap2430_clk_init(void);
45#define omap2430_clk_init() do { } while(0) 45#define omap2430_clk_init() do { } while(0)
46#endif 46#endif
47 47
48extern void __iomem *prcm_clksrc_ctrl;
49
50extern struct clk_hw *dclk_hw; 48extern struct clk_hw *dclk_hw;
51int omap2_enable_osc_ck(struct clk_hw *hw); 49int omap2_enable_osc_ck(struct clk_hw *hw);
52void omap2_disable_osc_ck(struct clk_hw *hw); 50void omap2_disable_osc_ck(struct clk_hw *hw);
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 8538669cc2ad..d7a5d11cbcbf 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -107,6 +107,7 @@
107#define OMAP24XX_AUTO_DPLL_SHIFT 0 107#define OMAP24XX_AUTO_DPLL_SHIFT 0
108#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) 108#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
109#define OMAP24XX_APLLS_CLKIN_SHIFT 23 109#define OMAP24XX_APLLS_CLKIN_SHIFT 23
110#define OMAP24XX_APLLS_CLKIN_WIDTH 3
110#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) 111#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
111#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) 112#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
112#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) 113#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 8f559450c876..1271fe902ca8 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -53,6 +53,7 @@
53#include "prm2xxx.h" 53#include "prm2xxx.h"
54#include "prm3xxx.h" 54#include "prm3xxx.h"
55#include "prm44xx.h" 55#include "prm44xx.h"
56#include "opp2xxx.h"
56 57
57/* 58/*
58 * omap_clk_soc_init: points to a function that does the SoC-specific 59 * omap_clk_soc_init: points to a function that does the SoC-specific
@@ -410,7 +411,8 @@ void __init omap2420_init_early(void)
410 omap242x_clockdomains_init(); 411 omap242x_clockdomains_init();
411 omap2420_hwmod_init(); 412 omap2420_hwmod_init();
412 omap_hwmod_init_postsetup(); 413 omap_hwmod_init_postsetup();
413 omap_clk_soc_init = omap2420_clk_init; 414 omap_clk_soc_init = omap2420_dt_clk_init;
415 rate_table = omap2420_rate_table;
414} 416}
415 417
416void __init omap2420_init_late(void) 418void __init omap2420_init_late(void)
@@ -439,7 +441,8 @@ void __init omap2430_init_early(void)
439 omap243x_clockdomains_init(); 441 omap243x_clockdomains_init();
440 omap2430_hwmod_init(); 442 omap2430_hwmod_init();
441 omap_hwmod_init_postsetup(); 443 omap_hwmod_init_postsetup();
442 omap_clk_soc_init = omap2430_clk_init; 444 omap_clk_soc_init = omap2430_dt_clk_init;
445 rate_table = omap2430_rate_table;
443} 446}
444 447
445void __init omap2430_init_late(void) 448void __init omap2430_init_late(void)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index a5ea988ff340..d7ac05c6e5e2 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -249,6 +249,10 @@ static void __init prcm_setup_regs(void)
249 /* Enable wake-up events */ 249 /* Enable wake-up events */
250 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, 250 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
251 WKUP_MOD, PM_WKEN); 251 WKUP_MOD, PM_WKEN);
252
253 /* Enable SYS_CLKEN control when all domains idle */
254 omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
255 OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
252} 256}
253 257
254int __init omap2_pm_init(void) 258int __init omap2_pm_init(void)
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 25e8b8232115..76ca320f007c 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -472,6 +472,8 @@ static struct of_device_id omap_prcm_dt_match_table[] = {
472 { .compatible = "ti,am3-scrm" }, 472 { .compatible = "ti,am3-scrm" },
473 { .compatible = "ti,am4-prcm" }, 473 { .compatible = "ti,am4-prcm" },
474 { .compatible = "ti,am4-scrm" }, 474 { .compatible = "ti,am4-scrm" },
475 { .compatible = "ti,omap2-prcm" },
476 { .compatible = "ti,omap2-scrm" },
475 { .compatible = "ti,omap3-prm" }, 477 { .compatible = "ti,omap3-prm" },
476 { .compatible = "ti,omap3-cm" }, 478 { .compatible = "ti,omap3-cm" },
477 { .compatible = "ti,omap3-scrm" }, 479 { .compatible = "ti,omap3-scrm" },
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 3d15d16a7088..85c2985d8bcb 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -15,22 +15,31 @@
15#include <linux/of_irq.h> 15#include <linux/of_irq.h>
16#include <linux/slab.h> 16#include <linux/slab.h>
17#include <linux/irqchip/arm-gic.h> 17#include <linux/irqchip/arm-gic.h>
18#include <linux/irqchip/irq-crossbar.h>
18 19
19#define IRQ_FREE -1 20#define IRQ_FREE -1
21#define IRQ_RESERVED -2
22#define IRQ_SKIP -3
20#define GIC_IRQ_START 32 23#define GIC_IRQ_START 32
21 24
22/* 25/**
26 * struct crossbar_device - crossbar device description
23 * @int_max: maximum number of supported interrupts 27 * @int_max: maximum number of supported interrupts
28 * @safe_map: safe default value to initialize the crossbar
29 * @max_crossbar_sources: Maximum number of crossbar sources
24 * @irq_map: array of interrupts to crossbar number mapping 30 * @irq_map: array of interrupts to crossbar number mapping
25 * @crossbar_base: crossbar base address 31 * @crossbar_base: crossbar base address
26 * @register_offsets: offsets for each irq number 32 * @register_offsets: offsets for each irq number
33 * @write: register write function pointer
27 */ 34 */
28struct crossbar_device { 35struct crossbar_device {
29 uint int_max; 36 uint int_max;
37 uint safe_map;
38 uint max_crossbar_sources;
30 uint *irq_map; 39 uint *irq_map;
31 void __iomem *crossbar_base; 40 void __iomem *crossbar_base;
32 int *register_offsets; 41 int *register_offsets;
33 void (*write) (int, int); 42 void (*write)(int, int);
34}; 43};
35 44
36static struct crossbar_device *cb; 45static struct crossbar_device *cb;
@@ -50,11 +59,22 @@ static inline void crossbar_writeb(int irq_no, int cb_no)
50 writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); 59 writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
51} 60}
52 61
62static inline int get_prev_map_irq(int cb_no)
63{
64 int i;
65
66 for (i = cb->int_max - 1; i >= 0; i--)
67 if (cb->irq_map[i] == cb_no)
68 return i;
69
70 return -ENODEV;
71}
72
53static inline int allocate_free_irq(int cb_no) 73static inline int allocate_free_irq(int cb_no)
54{ 74{
55 int i; 75 int i;
56 76
57 for (i = 0; i < cb->int_max; i++) { 77 for (i = cb->int_max - 1; i >= 0; i--) {
58 if (cb->irq_map[i] == IRQ_FREE) { 78 if (cb->irq_map[i] == IRQ_FREE) {
59 cb->irq_map[i] = cb_no; 79 cb->irq_map[i] = cb_no;
60 return i; 80 return i;
@@ -64,19 +84,47 @@ static inline int allocate_free_irq(int cb_no)
64 return -ENODEV; 84 return -ENODEV;
65} 85}
66 86
87static inline bool needs_crossbar_write(irq_hw_number_t hw)
88{
89 int cb_no;
90
91 if (hw > GIC_IRQ_START) {
92 cb_no = cb->irq_map[hw - GIC_IRQ_START];
93 if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP)
94 return true;
95 }
96
97 return false;
98}
99
67static int crossbar_domain_map(struct irq_domain *d, unsigned int irq, 100static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
68 irq_hw_number_t hw) 101 irq_hw_number_t hw)
69{ 102{
70 cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]); 103 if (needs_crossbar_write(hw))
104 cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
105
71 return 0; 106 return 0;
72} 107}
73 108
109/**
110 * crossbar_domain_unmap - unmap a crossbar<->irq connection
111 * @d: domain of irq to unmap
112 * @irq: virq number
113 *
114 * We do not maintain a use count of total number of map/unmap
115 * calls for a particular irq to find out if a irq can be really
116 * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
117 * after which irq is anyways unusable. So an explicit map has to be called
118 * after that.
119 */
74static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq) 120static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
75{ 121{
76 irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq; 122 irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
77 123
78 if (hw > GIC_IRQ_START) 124 if (needs_crossbar_write(hw)) {
79 cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE; 125 cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
126 cb->write(hw - GIC_IRQ_START, cb->safe_map);
127 }
80} 128}
81 129
82static int crossbar_domain_xlate(struct irq_domain *d, 130static int crossbar_domain_xlate(struct irq_domain *d,
@@ -85,18 +133,41 @@ static int crossbar_domain_xlate(struct irq_domain *d,
85 unsigned long *out_hwirq, 133 unsigned long *out_hwirq,
86 unsigned int *out_type) 134 unsigned int *out_type)
87{ 135{
88 unsigned long ret; 136 int ret;
137 int req_num = intspec[1];
138 int direct_map_num;
139
140 if (req_num >= cb->max_crossbar_sources) {
141 direct_map_num = req_num - cb->max_crossbar_sources;
142 if (direct_map_num < cb->int_max) {
143 ret = cb->irq_map[direct_map_num];
144 if (ret == IRQ_RESERVED || ret == IRQ_SKIP) {
145 /* We use the interrupt num as h/w irq num */
146 ret = direct_map_num;
147 goto found;
148 }
149 }
150
151 pr_err("%s: requested crossbar number %d > max %d\n",
152 __func__, req_num, cb->max_crossbar_sources);
153 return -EINVAL;
154 }
89 155
90 ret = allocate_free_irq(intspec[1]); 156 ret = get_prev_map_irq(req_num);
157 if (ret >= 0)
158 goto found;
91 159
92 if (IS_ERR_VALUE(ret)) 160 ret = allocate_free_irq(req_num);
161
162 if (ret < 0)
93 return ret; 163 return ret;
94 164
165found:
95 *out_hwirq = ret + GIC_IRQ_START; 166 *out_hwirq = ret + GIC_IRQ_START;
96 return 0; 167 return 0;
97} 168}
98 169
99const struct irq_domain_ops routable_irq_domain_ops = { 170static const struct irq_domain_ops routable_irq_domain_ops = {
100 .map = crossbar_domain_map, 171 .map = crossbar_domain_map,
101 .unmap = crossbar_domain_unmap, 172 .unmap = crossbar_domain_unmap,
102 .xlate = crossbar_domain_xlate 173 .xlate = crossbar_domain_xlate
@@ -104,22 +175,36 @@ const struct irq_domain_ops routable_irq_domain_ops = {
104 175
105static int __init crossbar_of_init(struct device_node *node) 176static int __init crossbar_of_init(struct device_node *node)
106{ 177{
107 int i, size, max, reserved = 0, entry; 178 int i, size, max = 0, reserved = 0, entry;
108 const __be32 *irqsr; 179 const __be32 *irqsr;
180 int ret = -ENOMEM;
109 181
110 cb = kzalloc(sizeof(*cb), GFP_KERNEL); 182 cb = kzalloc(sizeof(*cb), GFP_KERNEL);
111 183
112 if (!cb) 184 if (!cb)
113 return -ENOMEM; 185 return ret;
114 186
115 cb->crossbar_base = of_iomap(node, 0); 187 cb->crossbar_base = of_iomap(node, 0);
116 if (!cb->crossbar_base) 188 if (!cb->crossbar_base)
117 goto err1; 189 goto err_cb;
190
191 of_property_read_u32(node, "ti,max-crossbar-sources",
192 &cb->max_crossbar_sources);
193 if (!cb->max_crossbar_sources) {
194 pr_err("missing 'ti,max-crossbar-sources' property\n");
195 ret = -EINVAL;
196 goto err_base;
197 }
118 198
119 of_property_read_u32(node, "ti,max-irqs", &max); 199 of_property_read_u32(node, "ti,max-irqs", &max);
120 cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL); 200 if (!max) {
201 pr_err("missing 'ti,max-irqs' property\n");
202 ret = -EINVAL;
203 goto err_base;
204 }
205 cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
121 if (!cb->irq_map) 206 if (!cb->irq_map)
122 goto err2; 207 goto err_base;
123 208
124 cb->int_max = max; 209 cb->int_max = max;
125 210
@@ -137,15 +222,35 @@ static int __init crossbar_of_init(struct device_node *node)
137 i, &entry); 222 i, &entry);
138 if (entry > max) { 223 if (entry > max) {
139 pr_err("Invalid reserved entry\n"); 224 pr_err("Invalid reserved entry\n");
140 goto err3; 225 ret = -EINVAL;
226 goto err_irq_map;
227 }
228 cb->irq_map[entry] = IRQ_RESERVED;
229 }
230 }
231
232 /* Skip irqs hardwired to bypass the crossbar */
233 irqsr = of_get_property(node, "ti,irqs-skip", &size);
234 if (irqsr) {
235 size /= sizeof(__be32);
236
237 for (i = 0; i < size; i++) {
238 of_property_read_u32_index(node,
239 "ti,irqs-skip",
240 i, &entry);
241 if (entry > max) {
242 pr_err("Invalid skip entry\n");
243 ret = -EINVAL;
244 goto err_irq_map;
141 } 245 }
142 cb->irq_map[entry] = 0; 246 cb->irq_map[entry] = IRQ_SKIP;
143 } 247 }
144 } 248 }
145 249
146 cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL); 250
251 cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
147 if (!cb->register_offsets) 252 if (!cb->register_offsets)
148 goto err3; 253 goto err_irq_map;
149 254
150 of_property_read_u32(node, "ti,reg-size", &size); 255 of_property_read_u32(node, "ti,reg-size", &size);
151 256
@@ -161,7 +266,8 @@ static int __init crossbar_of_init(struct device_node *node)
161 break; 266 break;
162 default: 267 default:
163 pr_err("Invalid reg-size property\n"); 268 pr_err("Invalid reg-size property\n");
164 goto err4; 269 ret = -EINVAL;
270 goto err_reg_offset;
165 break; 271 break;
166 } 272 }
167 273
@@ -170,25 +276,37 @@ static int __init crossbar_of_init(struct device_node *node)
170 * reserved irqs. so find and store the offsets once. 276 * reserved irqs. so find and store the offsets once.
171 */ 277 */
172 for (i = 0; i < max; i++) { 278 for (i = 0; i < max; i++) {
173 if (!cb->irq_map[i]) 279 if (cb->irq_map[i] == IRQ_RESERVED)
174 continue; 280 continue;
175 281
176 cb->register_offsets[i] = reserved; 282 cb->register_offsets[i] = reserved;
177 reserved += size; 283 reserved += size;
178 } 284 }
179 285
286 of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
287 /* Initialize the crossbar with safe map to start with */
288 for (i = 0; i < max; i++) {
289 if (cb->irq_map[i] == IRQ_RESERVED ||
290 cb->irq_map[i] == IRQ_SKIP)
291 continue;
292
293 cb->write(i, cb->safe_map);
294 }
295
180 register_routable_domain_ops(&routable_irq_domain_ops); 296 register_routable_domain_ops(&routable_irq_domain_ops);
181 return 0; 297 return 0;
182 298
183err4: 299err_reg_offset:
184 kfree(cb->register_offsets); 300 kfree(cb->register_offsets);
185err3: 301err_irq_map:
186 kfree(cb->irq_map); 302 kfree(cb->irq_map);
187err2: 303err_base:
188 iounmap(cb->crossbar_base); 304 iounmap(cb->crossbar_base);
189err1: 305err_cb:
190 kfree(cb); 306 kfree(cb);
191 return -ENOMEM; 307
308 cb = NULL;
309 return ret;
192} 310}
193 311
194static const struct of_device_id crossbar_match[] __initconst = { 312static const struct of_device_id crossbar_match[] __initconst = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 18:33:37 -0400